184 lines
4.1 KiB
ArmAsm
184 lines
4.1 KiB
ArmAsm
/*
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* Copyright (c) 2006-2019, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2013-07-05 Bernard the first version
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* 2019-07-28 zdzn add smp support
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*/
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#include "../rtconfig.h"
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.section .text, "ax"
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#ifdef RT_USING_SMP
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#define rt_hw_interrupt_disable rt_hw_local_irq_disable
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#define rt_hw_interrupt_enable rt_hw_local_irq_enable
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#endif
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/*
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* rt_base_t rt_hw_interrupt_disable();
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*/
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.globl rt_hw_interrupt_disable
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rt_hw_interrupt_disable:
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mrs r0, cpsr
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cpsid i
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bx lr
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/*
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* void rt_hw_interrupt_enable(rt_base_t level);
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*/
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.globl rt_hw_interrupt_enable
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rt_hw_interrupt_enable:
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msr cpsr, r0
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bx lr
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/*
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* void rt_hw_context_switch_to(rt_uint32 to, struct rt_thread *to_thread);
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* r0 --> to (thread stack)
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* r1 --> to_thread
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*/
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.globl rt_hw_context_switch_to
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rt_hw_context_switch_to:
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ldr sp, [r0] @ get new task stack pointer
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#ifdef RT_USING_SMP
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mov r0, r1
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bl rt_cpus_lock_status_restore
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#endif /*RT_USING_SMP*/
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b rt_hw_context_switch_exit
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.section .bss.share.isr
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_guest_switch_lvl:
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.word 0
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.globl vmm_virq_update
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.section .text.isr, "ax"
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/*
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* void rt_hw_context_switch(rt_uint32 from, rt_uint32 to, struct rt_thread *to_thread);
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* r0 --> from (from_thread stack)
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* r1 --> to (to_thread stack)
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* r2 --> to_thread
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*/
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.globl rt_hw_context_switch
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rt_hw_context_switch:
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stmfd sp!, {lr} @ push pc (lr should be pushed in place of PC)
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stmfd sp!, {r0-r12, lr} @ push lr & register file
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mrs r4, cpsr
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tst lr, #0x01
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orrne r4, r4, #0x20 @ it's thumb code
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stmfd sp!, {r4} @ push cpsr
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#ifdef RT_USING_SMART
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stmfd sp, {r13, r14}^ @ push usr_sp usr_lr
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sub sp, #8
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#endif
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#ifdef RT_USING_FPU
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/* fpu context */
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vmrs r6, fpexc
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tst r6, #(1<<30)
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beq 1f
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vstmdb sp!, {d0-d15}
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vstmdb sp!, {d16-d31}
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vmrs r5, fpscr
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stmfd sp!, {r5}
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1:
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stmfd sp!, {r6}
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#endif
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str sp, [r0] @ store sp in preempted tasks TCB
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ldr sp, [r1] @ get new task stack pointer
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#ifdef RT_USING_SMP
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mov r0, r2
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bl rt_cpus_lock_status_restore
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#endif /*RT_USING_SMP*/
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b rt_hw_context_switch_exit
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/*
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* void rt_hw_context_switch_interrupt(rt_uint32 from, rt_uint32 to);
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*/
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.equ Mode_USR, 0x10
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.equ Mode_FIQ, 0x11
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.equ Mode_IRQ, 0x12
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.equ Mode_SVC, 0x13
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.equ Mode_ABT, 0x17
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.equ Mode_UND, 0x1B
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.equ Mode_SYS, 0x1F
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.equ I_Bit, 0x80 @ when I bit is set, IRQ is disabled
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.equ F_Bit, 0x40 @ when F bit is set, FIQ is disabled
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.globl rt_thread_switch_interrupt_flag
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.globl rt_interrupt_from_thread
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.globl rt_interrupt_to_thread
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.globl rt_hw_context_switch_interrupt
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rt_hw_context_switch_interrupt:
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#ifdef RT_USING_SMP
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/* r0 :svc_mod context
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* r1 :addr of from_thread's sp
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* r2 :addr of to_thread's sp
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* r3 :to_thread's tcb
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*/
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str r0, [r1]
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ldr sp, [r2]
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mov r0, r3
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bl rt_cpus_lock_status_restore
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b rt_hw_context_switch_exit
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#else /*RT_USING_SMP*/
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ldr r2, =rt_thread_switch_interrupt_flag
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ldr r3, [r2]
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cmp r3, #1
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beq _reswitch
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ldr ip, =rt_interrupt_from_thread @ set rt_interrupt_from_thread
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mov r3, #1 @ set rt_thread_switch_interrupt_flag to 1
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str r0, [ip]
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str r3, [r2]
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_reswitch:
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ldr r2, =rt_interrupt_to_thread @ set rt_interrupt_to_thread
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str r1, [r2]
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bx lr
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#endif /*RT_USING_SMP*/
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.global rt_hw_context_switch_exit
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rt_hw_context_switch_exit:
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#ifdef RT_USING_SMP
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#ifdef RT_USING_SIGNALS
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mov r0, sp
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cps #Mode_IRQ
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bl rt_signal_check
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cps #Mode_SVC
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mov sp, r0
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#endif
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#endif
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#ifdef RT_USING_FPU
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/* fpu context */
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ldmfd sp!, {r6}
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vmsr fpexc, r6
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tst r6, #(1<<30)
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beq 1f
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ldmfd sp!, {r5}
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vmsr fpscr, r5
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vldmia sp!, {d16-d31}
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vldmia sp!, {d0-d15}
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#endif
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#ifdef RT_USING_SMART
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ldmfd sp, {r13, r14}^ /* usr_sp, usr_lr */
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add sp, #8
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#endif
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ldmfd sp!, {r4}
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msr spsr_cxsf, r4 /* original mode */
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ldmfd sp!, {r0-r12,lr,pc}^ /* irq return */
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