371 lines
24 KiB
C
371 lines
24 KiB
C
/*!
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\file gd32f10x_fmc.h
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\brief definitions for the FMC
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\version 2014-12-26, V1.0.0, firmware for GD32F10x
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\version 2017-06-20, V2.0.0, firmware for GD32F10x
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\version 2018-07-31, V2.1.0, firmware for GD32F10x
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*/
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/*
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Copyright (c) 2018, GigaDevice Semiconductor Inc.
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All rights reserved.
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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1. Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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2. Redistributions in binary form must reproduce the above copyright notice,
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this list of conditions and the following disclaimer in the documentation
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and/or other materials provided with the distribution.
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3. Neither the name of the copyright holder nor the names of its contributors
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may be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
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INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
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PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY
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OF SUCH DAMAGE.
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*/
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#ifndef GD32F10X_FMC_H
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#define GD32F10X_FMC_H
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#include "gd32f10x.h"
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/* FMC and option byte definition */
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#define FMC FMC_BASE /*!< FMC register base address */
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#define OB OB_BASE /*!< option bytes base address */
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/* registers definitions */
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#define FMC_WS REG32((FMC) + 0x00U) /*!< FMC wait state register */
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#define FMC_KEY0 REG32((FMC) + 0x04U) /*!< FMC unlock key register 0 */
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#define FMC_OBKEY REG32((FMC) + 0x08U) /*!< FMC option bytes unlock key register */
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#define FMC_STAT0 REG32((FMC) + 0x0CU) /*!< FMC status register 0 */
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#define FMC_CTL0 REG32((FMC) + 0x10U) /*!< FMC control register 0 */
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#define FMC_ADDR0 REG32((FMC) + 0x14U) /*!< FMC address register 0 */
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#define FMC_OBSTAT REG32((FMC) + 0x1CU) /*!< FMC option bytes status register */
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#define FMC_WP REG32((FMC) + 0x20U) /*!< FMC erase/program protection register */
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#define FMC_KEY1 REG32((FMC) + 0x44U) /*!< FMC unlock key register 1 */
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#define FMC_STAT1 REG32((FMC) + 0x4CU) /*!< FMC status register 1 */
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#define FMC_CTL1 REG32((FMC) + 0x50U) /*!< FMC control register 1 */
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#define FMC_ADDR1 REG32((FMC) + 0x54U) /*!< FMC address register 1 */
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#define FMC_WSEN REG32((FMC) + 0xFCU) /*!< FMC wait state enable register */
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#define FMC_PID REG32((FMC) + 0x100U) /*!< FMC product ID register */
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#define OB_SPC REG16((OB) + 0x00U) /*!< option byte security protection value */
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#define OB_USER REG16((OB) + 0x02U) /*!< option byte user value*/
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#define OB_WP0 REG16((OB) + 0x08U) /*!< option byte write protection 0 */
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#define OB_WP1 REG16((OB) + 0x0AU) /*!< option byte write protection 1 */
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#define OB_WP2 REG16((OB) + 0x0CU) /*!< option byte write protection 2 */
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#define OB_WP3 REG16((OB) + 0x0EU) /*!< option byte write protection 3 */
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/* bits definitions */
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/* FMC_WS */
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#define FMC_WS_WSCNT BITS(0,2) /*!< wait state counter */
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/* FMC_KEY0 */
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#define FMC_KEY0_KEY BITS(0,31) /*!< FMC_CTL0 unlock key bits */
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/* FMC_OBKEY */
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#define FMC_OBKEY_OBKEY BITS(0,31) /*!< option bytes unlock key bits */
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/* FMC_STAT0 */
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#define FMC_STAT0_BUSY BIT(0) /*!< flash busy flag bit */
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#define FMC_STAT0_PGERR BIT(2) /*!< flash program error flag bit */
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#define FMC_STAT0_WPERR BIT(4) /*!< erase/program protection error flag bit */
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#define FMC_STAT0_ENDF BIT(5) /*!< end of operation flag bit */
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/* FMC_CTL0 */
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#define FMC_CTL0_PG BIT(0) /*!< main flash program for bank0 command bit */
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#define FMC_CTL0_PER BIT(1) /*!< main flash page erase for bank0 command bit */
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#define FMC_CTL0_MER BIT(2) /*!< main flash mass erase for bank0 command bit */
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#define FMC_CTL0_OBPG BIT(4) /*!< option bytes program command bit */
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#define FMC_CTL0_OBER BIT(5) /*!< option bytes erase command bit */
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#define FMC_CTL0_START BIT(6) /*!< send erase command to FMC bit */
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#define FMC_CTL0_LK BIT(7) /*!< FMC_CTL0 lock bit */
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#define FMC_CTL0_OBWEN BIT(9) /*!< option bytes erase/program enable bit */
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#define FMC_CTL0_ERRIE BIT(10) /*!< error interrupt enable bit */
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#define FMC_CTL0_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
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/* FMC_ADDR0 */
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#define FMC_ADDR0_ADDR BITS(0,31) /*!< flash erase/program command address bits */
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/* FMC_OBSTAT */
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#define FMC_OBSTAT_OBERR BIT(0) /*!< option bytes read error bit. */
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#define FMC_OBSTAT_SPC BIT(1) /*!< option bytes security protection code */
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#define FMC_OBSTAT_USER BITS(2,9) /*!< store USER of option bytes block after system reset */
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#define FMC_OBSTAT_DATA BITS(10,25) /*!< store DATA of option bytes block after system reset. */
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/* FMC_WP */
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#define FMC_WP_WP BITS(0,31) /*!< store WP of option bytes block after system reset */
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/* FMC_KEY1 */
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#define FMC_KEY1_KEY BITS(0,31) /*!< FMC_CTL1 unlock key bits */
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/* FMC_STAT1 */
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#define FMC_STAT1_BUSY BIT(0) /*!< flash busy flag bit */
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#define FMC_STAT1_PGERR BIT(2) /*!< flash program error flag bit */
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#define FMC_STAT1_WPERR BIT(4) /*!< erase/program protection error flag bit */
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#define FMC_STAT1_ENDF BIT(5) /*!< end of operation flag bit */
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/* FMC_CTL1 */
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#define FMC_CTL1_PG BIT(0) /*!< main flash program for bank1 command bit */
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#define FMC_CTL1_PER BIT(1) /*!< main flash page erase for bank1 command bit */
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#define FMC_CTL1_MER BIT(2) /*!< main flash mass erase for bank1 command bit */
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#define FMC_CTL1_START BIT(6) /*!< send erase command to FMC bit */
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#define FMC_CTL1_LK BIT(7) /*!< FMC_CTL1 lock bit */
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#define FMC_CTL1_ERRIE BIT(10) /*!< error interrupt enable bit */
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#define FMC_CTL1_ENDIE BIT(12) /*!< end of operation interrupt enable bit */
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/* FMC_ADDR1 */
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#define FMC_ADDR1_ADDR BITS(0,31) /*!< flash erase/program command address bits */
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/* FMC_WSEN */
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#define FMC_WSEN_WSEN BIT(0) /*!< FMC wait state enable bit */
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/* FMC_PID */
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#define FMC_PID_PID BITS(0,31) /*!< product ID bits */
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/* constants definitions */
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/* define the FMC bit position and its register index offset */
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#define FMC_REGIDX_BIT(regidx, bitpos) (((uint32_t)(regidx) << 6) | (uint32_t)(bitpos))
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#define FMC_REG_VAL(offset) (REG32(FMC + ((uint32_t)(offset) >> 6)))
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#define FMC_BIT_POS(val) ((uint32_t)(val) & 0x1FU)
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#define FMC_REGIDX_BITS(regidx, bitpos0, bitpos1) (((uint32_t)(regidx) << 12) | ((uint32_t)(bitpos0) << 6) | (uint32_t)(bitpos1))
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#define FMC_REG_VALS(offset) (REG32(FMC + ((uint32_t)(offset) >> 12)))
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#define FMC_BIT_POS0(val) (((uint32_t)(val) >> 6) & 0x1FU)
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#define FMC_BIT_POS1(val) ((uint32_t)(val) & 0x1FU)
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#define FMC_REG_OFFSET_GET(flag) ((uint32_t)(flag) >> 12)
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/* configuration register */
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#define FMC_STAT0_REG_OFFSET 0x0CU /*!< status register 0 offset */
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#define FMC_CTL0_REG_OFFSET 0x10U /*!< control register 0 offset */
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#define FMC_STAT1_REG_OFFSET 0x4CU /*!< status register 1 offset */
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#define FMC_CTL1_REG_OFFSET 0x50U /*!< control register 1 offset */
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#define FMC_OBSTAT_REG_OFFSET 0x1CU /*!< option byte status register offset */
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/* fmc state */
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typedef enum
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{
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FMC_READY, /*!< the operation has been completed */
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FMC_BUSY, /*!< the operation is in progress */
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FMC_PGERR, /*!< program error */
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FMC_WPERR, /*!< erase/program protection error */
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FMC_TOERR, /*!< timeout error */
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}fmc_state_enum;
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/* FMC interrupt enable */
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typedef enum
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{
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FMC_INT_BANK0_END = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 12U), /*!< enable FMC end of program interrupt */
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FMC_INT_BANK0_ERR = FMC_REGIDX_BIT(FMC_CTL0_REG_OFFSET, 10U), /*!< enable FMC error interrupt */
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FMC_INT_BANK1_END = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 12U), /*!< enable FMC bank1 end of program interrupt */
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FMC_INT_BANK1_ERR = FMC_REGIDX_BIT(FMC_CTL1_REG_OFFSET, 10U), /*!< enable FMC bank1 error interrupt */
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}fmc_int_enum;
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/* FMC flags */
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typedef enum
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{
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FMC_FLAG_BANK0_BUSY = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 0U), /*!< FMC bank0 busy flag */
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FMC_FLAG_BANK0_PGERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 2U), /*!< FMC bank0 operation error flag bit */
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FMC_FLAG_BANK0_WPERR = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 4U), /*!< FMC bank0 erase/program protection error flag bit */
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FMC_FLAG_BANK0_END = FMC_REGIDX_BIT(FMC_STAT0_REG_OFFSET, 5U), /*!< FMC bank0 end of operation flag bit */
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FMC_FLAG_OBERR = FMC_REGIDX_BIT(FMC_OBSTAT_REG_OFFSET, 0U), /*!< FMC option bytes read error flag */
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FMC_FLAG_BANK1_BUSY = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 0U), /*!< FMC bank1 busy flag */
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FMC_FLAG_BANK1_PGERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 2U), /*!< FMC bank1 operation error flag bit */
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FMC_FLAG_BANK1_WPERR = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 4U), /*!< FMC bank1 erase/program protection error flag bit */
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FMC_FLAG_BANK1_END = FMC_REGIDX_BIT(FMC_STAT1_REG_OFFSET, 5U), /*!< FMC bank1 end of operation flag bit */
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}fmc_flag_enum;
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/* FMC interrupt flags */
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typedef enum
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{
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FMC_INT_FLAG_BANK0_PGERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 2U, 10U), /*!< FMC bank0 operation error interrupt flag bit */
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FMC_INT_FLAG_BANK0_WPERR = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 4U, 10U), /*!< FMC bank0 erase/program protection error interrupt flag bit */
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FMC_INT_FLAG_BANK0_END = FMC_REGIDX_BITS(FMC_STAT0_REG_OFFSET, 5U, 12U), /*!< FMC bank0 end of operation interrupt flag bit */
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FMC_INT_FLAG_BANK1_PGERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 2U, 10U), /*!< FMC bank1 operation error interrupt flag bit */
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FMC_INT_FLAG_BANK1_WPERR = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 4U, 10U), /*!< FMC bank1 erase/program protection error interrupt flag bit */
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FMC_INT_FLAG_BANK1_END = FMC_REGIDX_BITS(FMC_STAT1_REG_OFFSET, 5U, 12U), /*!< FMC bank1 end of operation interrupt flag bit */
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}fmc_interrupt_flag_enum;
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/* unlock key */
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#define UNLOCK_KEY0 ((uint32_t)0x45670123U) /*!< unlock key 0 */
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#define UNLOCK_KEY1 ((uint32_t)0xCDEF89ABU) /*!< unlock key 1 */
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/* FMC wait state counter */
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#define WS_WSCNT(regval) (BITS(0,2) & ((uint32_t)(regval)))
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#define WS_WSCNT_0 WS_WSCNT(0) /*!< FMC 0 wait */
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#define WS_WSCNT_1 WS_WSCNT(1) /*!< FMC 1 wait */
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#define WS_WSCNT_2 WS_WSCNT(2) /*!< FMC 2 wait */
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/* option bytes software/hardware free watch dog timer */
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#define OB_FWDGT_SW ((uint8_t)0x01U) /*!< software free watchdog */
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#define OB_FWDGT_HW ((uint8_t)0x00U) /*!< hardware free watchdog */
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/* option bytes reset or not entering deep sleep mode */
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#define OB_DEEPSLEEP_NRST ((uint8_t)0x02U) /*!< no reset when entering deepsleep mode */
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#define OB_DEEPSLEEP_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering deepsleep mode */
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/* option bytes reset or not entering standby mode */
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#define OB_STDBY_NRST ((uint8_t)0x04U) /*!< no reset when entering deepsleep mode */
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#define OB_STDBY_RST ((uint8_t)0x00U) /*!< generate a reset instead of entering standby mode */
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/* option bytes boot bank value */
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#define OB_BOOT_B0 ((uint8_t)0x08U) /*!< boot from bank0 */
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#define OB_BOOT_B1 ((uint8_t)0x00U) /*!< boot from bank1 */
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#define OB_USER_MASK ((uint8_t)0xF0U) /*!< MASK value */
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/* read protect configure */
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#define FMC_NSPC ((uint8_t)0xA5U) /*!< no security protection */
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#define FMC_USPC ((uint8_t)0xBBU) /*!< under security protection */
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/* OB_SPC */
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#define OB_SPC_SPC ((uint32_t)0x000000FFU) /*!< option byte security protection value */
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#define OB_SPC_SPC_N ((uint32_t)0x0000FF00U) /*!< option byte security protection complement value */
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/* OB_USER */
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#define OB_USER_USER ((uint32_t)0x00FF0000U) /*!< user option value */
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#define OB_USER_USER_N ((uint32_t)0xFF000000U) /*!< user option complement value */
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/* OB_WP0 */
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#define OB_WP0_WP0 ((uint32_t)0x000000FFU) /*!< FMC write protection option value */
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/* OB_WP1 */
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#define OB_WP1_WP1 ((uint32_t)0x0000FF00U) /*!< FMC write protection option complement value */
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/* OB_WP2 */
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#define OB_WP2_WP2 ((uint32_t)0x00FF0000U) /*!< FMC write protection option value */
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/* OB_WP3 */
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#define OB_WP3_WP3 ((uint32_t)0xFF000000U) /*!< FMC write protection option complement value */
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/* option bytes write protection */
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#define OB_WP_0 ((uint32_t)0x00000001U) /*!< erase/program protection of sector 0 */
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#define OB_WP_1 ((uint32_t)0x00000002U) /*!< erase/program protection of sector 1 */
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#define OB_WP_2 ((uint32_t)0x00000004U) /*!< erase/program protection of sector 2 */
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#define OB_WP_3 ((uint32_t)0x00000008U) /*!< erase/program protection of sector 3 */
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#define OB_WP_4 ((uint32_t)0x00000010U) /*!< erase/program protection of sector 4 */
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#define OB_WP_5 ((uint32_t)0x00000020U) /*!< erase/program protection of sector 5 */
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#define OB_WP_6 ((uint32_t)0x00000040U) /*!< erase/program protection of sector 6 */
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#define OB_WP_7 ((uint32_t)0x00000080U) /*!< erase/program protection of sector 7 */
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#define OB_WP_8 ((uint32_t)0x00000100U) /*!< erase/program protection of sector 8 */
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#define OB_WP_9 ((uint32_t)0x00000200U) /*!< erase/program protection of sector 9 */
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#define OB_WP_10 ((uint32_t)0x00000400U) /*!< erase/program protection of sector 10 */
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#define OB_WP_11 ((uint32_t)0x00000800U) /*!< erase/program protection of sector 11 */
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#define OB_WP_12 ((uint32_t)0x00001000U) /*!< erase/program protection of sector 12 */
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#define OB_WP_13 ((uint32_t)0x00002000U) /*!< erase/program protection of sector 13 */
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#define OB_WP_14 ((uint32_t)0x00004000U) /*!< erase/program protection of sector 14 */
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#define OB_WP_15 ((uint32_t)0x00008000U) /*!< erase/program protection of sector 15 */
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#define OB_WP_16 ((uint32_t)0x00010000U) /*!< erase/program protection of sector 16 */
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#define OB_WP_17 ((uint32_t)0x00020000U) /*!< erase/program protection of sector 17 */
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#define OB_WP_18 ((uint32_t)0x00040000U) /*!< erase/program protection of sector 18 */
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#define OB_WP_19 ((uint32_t)0x00080000U) /*!< erase/program protection of sector 19 */
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#define OB_WP_20 ((uint32_t)0x00100000U) /*!< erase/program protection of sector 20 */
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#define OB_WP_21 ((uint32_t)0x00200000U) /*!< erase/program protection of sector 21 */
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#define OB_WP_22 ((uint32_t)0x00400000U) /*!< erase/program protection of sector 22 */
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#define OB_WP_23 ((uint32_t)0x00800000U) /*!< erase/program protection of sector 23 */
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#define OB_WP_24 ((uint32_t)0x01000000U) /*!< erase/program protection of sector 24 */
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#define OB_WP_25 ((uint32_t)0x02000000U) /*!< erase/program protection of sector 25 */
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#define OB_WP_26 ((uint32_t)0x04000000U) /*!< erase/program protection of sector 26 */
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#define OB_WP_27 ((uint32_t)0x08000000U) /*!< erase/program protection of sector 27 */
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#define OB_WP_28 ((uint32_t)0x10000000U) /*!< erase/program protection of sector 28 */
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#define OB_WP_29 ((uint32_t)0x20000000U) /*!< erase/program protection of sector 29 */
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#define OB_WP_30 ((uint32_t)0x40000000U) /*!< erase/program protection of sector 30 */
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#define OB_WP_31 ((uint32_t)0x80000000U) /*!< erase/program protection of sector 31 */
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#define OB_WP_ALL ((uint32_t)0xFFFFFFFFU) /*!< erase/program protection of all sectors */
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/* FMC timeout */
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#define FMC_TIMEOUT_COUNT ((uint32_t)0x000F0000U) /*!< FMC timeout count value */
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/* FMC BANK address */
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#define FMC_BANK0_END_ADDRESS ((uint32_t)0x0807FFFFU) /*!< FMC bank0 end address */
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#define FMC_BANK0_SIZE ((uint32_t)0x00000200U) /*!< FMC bank0 size */
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#define FMC_SIZE (*(uint16_t *)0x1FFFF7E0U) /*!< FMC size */
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/* function declarations */
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/* FMC main memory programming functions */
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/* set the FMC wait state counter */
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void fmc_wscnt_set(uint32_t wscnt);
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/* unlock the main FMC operation */
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void fmc_unlock(void);
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/* unlock the FMC bank0 operation */
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void fmc_bank0_unlock(void);
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/* unlock the FMC bank1 operation */
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void fmc_bank1_unlock(void);
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/* lock the main FMC operation */
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void fmc_lock(void);
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/* lock the bank0 FMC operation */
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void fmc_bank0_lock(void);
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/* lock the bank1 FMC operation */
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void fmc_bank1_lock(void);
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/* FMC erase page */
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fmc_state_enum fmc_page_erase(uint32_t page_address);
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/* FMC erase whole chip */
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fmc_state_enum fmc_mass_erase(void);
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/* FMC erase whole bank0 */
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fmc_state_enum fmc_bank0_erase(void);
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/* FMC erase whole bank1 */
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fmc_state_enum fmc_bank1_erase(void);
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/* FMC program a word at the corresponding address */
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fmc_state_enum fmc_word_program(uint32_t address, uint32_t data);
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/* FMC program a half word at the corresponding address */
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fmc_state_enum fmc_halfword_program(uint32_t address, uint16_t data);
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/* FMC option bytes programming functions */
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/* unlock the option byte operation */
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void ob_unlock(void);
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/* lock the option byte operation */
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void ob_lock(void);
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/* erase the option byte */
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fmc_state_enum ob_erase(void);
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/* enable write protect */
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fmc_state_enum ob_write_protection_enable(uint32_t ob_wp);
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/* configure the option byte security protection */
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fmc_state_enum ob_security_protection_config(uint8_t ob_spc);
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/* write the FMC option byte */
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fmc_state_enum ob_user_write(uint8_t ob_fwdgt, uint8_t ob_deepsleep, uint8_t ob_stdby, uint8_t ob_boot);
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/* program option bytes data */
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fmc_state_enum ob_data_program(uint32_t address, uint8_t data);
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/* get the FMC option byte user */
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uint8_t ob_user_get(void);
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/* get OB_DATA in register FMC_OBSTAT */
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uint16_t ob_data_get(void);
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/* get the FMC option byte write protection */
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uint32_t ob_write_protection_get(void);
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/* get option byte security protection code value */
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FlagStatus ob_spc_get(void);
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/* FMC interrupts and flags management functions */
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/* enable FMC interrupt */
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void fmc_interrupt_enable(uint32_t interrupt);
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/* disable FMC interrupt */
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void fmc_interrupt_disable(uint32_t interrupt);
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/* check flag is set or not */
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FlagStatus fmc_flag_get(uint32_t flag);
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/* clear the FMC flag */
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void fmc_flag_clear(uint32_t flag);
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/* get FMC interrupt flag state */
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FlagStatus fmc_interrupt_flag_get(fmc_interrupt_flag_enum flag);
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/* clear FMC interrupt flag state */
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void fmc_interrupt_flag_clear(fmc_interrupt_flag_enum flag);
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/* return the FMC bank0 state */
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fmc_state_enum fmc_bank0_state_get(void);
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/* return the FMC bank1 state */
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fmc_state_enum fmc_bank1_state_get(void);
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/* check FMC bank0 ready or not */
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fmc_state_enum fmc_bank0_ready_wait(uint32_t timeout);
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/* check FMC bank1 ready or not */
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fmc_state_enum fmc_bank1_ready_wait(uint32_t timeout);
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#endif /* GD32F10X_FMC_H */
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