499 lines
17 KiB
ArmAsm
499 lines
17 KiB
ArmAsm
;/*****************************************************************************/
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;/* SAM7.S: Startup file for Atmel AT91SAM7 device series */
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;/*****************************************************************************/
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;/* <<< Use Configuration Wizard in Context Menu >>> */
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;/*****************************************************************************/
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;/* This file is part of the uVision/ARM development tools. */
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;/* Copyright (c) 2005-2006 Keil Software. All rights reserved. */
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;/* This software may only be used under the terms of a valid, current, */
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;/* end user licence from KEIL for a compatible version of KEIL software */
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;/* development tools. Nothing else gives you the right to use this software. */
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;/*****************************************************************************/
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;/*
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; * The SAM7.S code is executed after CPU Reset. This file may be
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; * translated with the following SET symbols. In uVision these SET
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; * symbols are entered under Options - ASM - Define.
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; *
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; * REMAP: when set the startup code remaps exception vectors from
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; * on-chip RAM to address 0.
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; *
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; * RAM_INTVEC: when set the startup code copies exception vectors
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; * from on-chip Flash to on-chip RAM.
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; */
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; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
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Mode_USR EQU 0x10
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Mode_FIQ EQU 0x11
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Mode_IRQ EQU 0x12
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Mode_SVC EQU 0x13
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Mode_ABT EQU 0x17
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Mode_UND EQU 0x1B
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Mode_SYS EQU 0x1F
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I_Bit EQU 0x80 ; when I bit is set, IRQ is disabled
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F_Bit EQU 0x40 ; when F bit is set, FIQ is disabled
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; Internal Memory Base Addresses
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FLASH_BASE EQU 0x00100000
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RAM_BASE EQU 0x00200000
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;// <h> Stack Configuration (Stack Sizes in Bytes)
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;// <o0> Undefined Mode <0x0-0xFFFFFFFF:8>
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;// <o1> Supervisor Mode <0x0-0xFFFFFFFF:8>
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;// <o2> Abort Mode <0x0-0xFFFFFFFF:8>
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;// <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
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;// <o4> Interrupt Mode <0x0-0xFFFFFFFF:8>
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;// <o5> User/System Mode <0x0-0xFFFFFFFF:8>
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;// </h>
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UND_Stack_Size EQU 0x00000000
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SVC_Stack_Size EQU 0x00000100
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ABT_Stack_Size EQU 0x00000000
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FIQ_Stack_Size EQU 0x00000000
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IRQ_Stack_Size EQU 0x00000100
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USR_Stack_Size EQU 0x00000100
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ISR_Stack_Size EQU (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + \
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FIQ_Stack_Size + IRQ_Stack_Size)
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AREA STACK, NOINIT, READWRITE, ALIGN=3
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Stack_Mem SPACE USR_Stack_Size
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__initial_sp SPACE ISR_Stack_Size
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Stack_Top
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;// <h> Heap Configuration
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;// <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF>
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;// </h>
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Heap_Size EQU 0x00000000
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AREA HEAP, NOINIT, READWRITE, ALIGN=3
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__heap_base
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Heap_Mem SPACE Heap_Size
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__heap_limit
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; Reset Controller (RSTC) definitions
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RSTC_BASE EQU 0xFFFFFD00 ; RSTC Base Address
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RSTC_MR EQU 0x08 ; RSTC_MR Offset
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;/*
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;// <e> Reset Controller (RSTC)
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;// <o1.0> URSTEN: User Reset Enable
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;// <i> Enables NRST Pin to generate Reset
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;// <o1.8..11> ERSTL: External Reset Length <0-15>
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;// <i> External Reset Time in 2^(ERSTL+1) Slow Clock Cycles
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;// </e>
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;*/
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RSTC_SETUP EQU 1
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RSTC_MR_Val EQU 0xA5000401
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; Embedded Flash Controller (EFC) definitions
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EFC_BASE EQU 0xFFFFFF00 ; EFC Base Address
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EFC0_FMR EQU 0x60 ; EFC0_FMR Offset
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EFC1_FMR EQU 0x70 ; EFC1_FMR Offset
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;// <e> Embedded Flash Controller 0 (EFC0)
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;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
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;// <i> Number of Master Clock Cycles in 1us
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;// <o1.8..9> FWS: Flash Wait State
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;// <0=> Read: 1 cycle / Write: 2 cycles
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;// <1=> Read: 2 cycle / Write: 3 cycles
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;// <2=> Read: 3 cycle / Write: 4 cycles
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;// <3=> Read: 4 cycle / Write: 4 cycles
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;// </e>
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EFC0_SETUP EQU 1
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EFC0_FMR_Val EQU 0x00320100
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;// <e> Embedded Flash Controller 1 (EFC1)
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;// <o1.16..23> FMCN: Flash Microsecond Cycle Number <0-255>
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;// <i> Number of Master Clock Cycles in 1us
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;// <o1.8..9> FWS: Flash Wait State
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;// <0=> Read: 1 cycle / Write: 2 cycles
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;// <1=> Read: 2 cycle / Write: 3 cycles
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;// <2=> Read: 3 cycle / Write: 4 cycles
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;// <3=> Read: 4 cycle / Write: 4 cycles
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;// </e>
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EFC1_SETUP EQU 0
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EFC1_FMR_Val EQU 0x00320100
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; Watchdog Timer (WDT) definitions
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WDT_BASE EQU 0xFFFFFD40 ; WDT Base Address
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WDT_MR EQU 0x04 ; WDT_MR Offset
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;// <e> Watchdog Timer (WDT)
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;// <o1.0..11> WDV: Watchdog Counter Value <0-4095>
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;// <o1.16..27> WDD: Watchdog Delta Value <0-4095>
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;// <o1.12> WDFIEN: Watchdog Fault Interrupt Enable
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;// <o1.13> WDRSTEN: Watchdog Reset Enable
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;// <o1.14> WDRPROC: Watchdog Reset Processor
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;// <o1.28> WDDBGHLT: Watchdog Debug Halt
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;// <o1.29> WDIDLEHLT: Watchdog Idle Halt
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;// <o1.15> WDDIS: Watchdog Disable
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;// </e>
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WDT_SETUP EQU 1
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WDT_MR_Val EQU 0x00008000
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; Power Mangement Controller (PMC) definitions
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PMC_BASE EQU 0xFFFFFC00 ; PMC Base Address
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PMC_MOR EQU 0x20 ; PMC_MOR Offset
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PMC_MCFR EQU 0x24 ; PMC_MCFR Offset
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PMC_PLLR EQU 0x2C ; PMC_PLLR Offset
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PMC_MCKR EQU 0x30 ; PMC_MCKR Offset
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PMC_SR EQU 0x68 ; PMC_SR Offset
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PMC_MOSCEN EQU (1<<0) ; Main Oscillator Enable
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PMC_OSCBYPASS EQU (1<<1) ; Main Oscillator Bypass
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PMC_OSCOUNT EQU (0xFF<<8) ; Main OScillator Start-up Time
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PMC_DIV EQU (0xFF<<0) ; PLL Divider
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PMC_PLLCOUNT EQU (0x3F<<8) ; PLL Lock Counter
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PMC_OUT EQU (0x03<<14) ; PLL Clock Frequency Range
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PMC_MUL EQU (0x7FF<<16) ; PLL Multiplier
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PMC_USBDIV EQU (0x03<<28) ; USB Clock Divider
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PMC_CSS EQU (3<<0) ; Clock Source Selection
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PMC_PRES EQU (7<<2) ; Prescaler Selection
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PMC_MOSCS EQU (1<<0) ; Main Oscillator Stable
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PMC_LOCK EQU (1<<2) ; PLL Lock Status
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PMC_MCKRDY EQU (1<<3) ; Master Clock Status
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;// <e> Power Mangement Controller (PMC)
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;// <h> Main Oscillator
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;// <o1.0> MOSCEN: Main Oscillator Enable
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;// <o1.1> OSCBYPASS: Oscillator Bypass
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;// <o1.8..15> OSCCOUNT: Main Oscillator Startup Time <0-255>
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;// </h>
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;// <h> Phase Locked Loop (PLL)
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;// <o2.0..7> DIV: PLL Divider <0-255>
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;// <o2.16..26> MUL: PLL Multiplier <0-2047>
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;// <i> PLL Output is multiplied by MUL+1
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;// <o2.14..15> OUT: PLL Clock Frequency Range
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;// <0=> 80..160MHz <1=> Reserved
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;// <2=> 150..220MHz <3=> Reserved
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;// <o2.8..13> PLLCOUNT: PLL Lock Counter <0-63>
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;// <o2.28..29> USBDIV: USB Clock Divider
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;// <0=> None <1=> 2 <2=> 4 <3=> Reserved
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;// </h>
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;// <o3.0..1> CSS: Clock Source Selection
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;// <0=> Slow Clock
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;// <1=> Main Clock
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;// <2=> Reserved
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;// <3=> PLL Clock
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;// <o3.2..4> PRES: Prescaler
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;// <0=> None
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;// <1=> Clock / 2 <2=> Clock / 4
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;// <3=> Clock / 8 <4=> Clock / 16
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;// <5=> Clock / 32 <6=> Clock / 64
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;// <7=> Reserved
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;// </e>
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PMC_SETUP EQU 1
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PMC_MOR_Val EQU 0x00000601
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PMC_PLLR_Val EQU 0x00191C05
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PMC_MCKR_Val EQU 0x00000007
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PRESERVE8
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; Area Definition and Entry Point
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; Startup Code must be linked first at Address at which it expects to run.
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AREA RESET, CODE, READONLY
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ARM
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; Exception Vectors
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; Mapped to Address 0.
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; Absolute addressing mode must be used.
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; Dummy Handlers are implemented as infinite loops which can be modified.
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Vectors LDR PC,Reset_Addr
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LDR PC,Undef_Addr
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LDR PC,SWI_Addr
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LDR PC,PAbt_Addr
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LDR PC,DAbt_Addr
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NOP ; Reserved Vector
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LDR PC,IRQ_Addr
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LDR PC,FIQ_Addr
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Reset_Addr DCD Reset_Handler
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Undef_Addr DCD Undef_Handler
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SWI_Addr DCD SWI_Handler
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PAbt_Addr DCD PAbt_Handler
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DAbt_Addr DCD DAbt_Handler
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DCD 0 ; Reserved Address
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IRQ_Addr DCD IRQ_Handler
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FIQ_Addr DCD FIQ_Handler
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Undef_Handler B Undef_Handler
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SWI_Handler B SWI_Handler
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PAbt_Handler B PAbt_Handler
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DAbt_Handler B DAbt_Handler
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FIQ_Handler B FIQ_Handler
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; Reset Handler
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EXPORT Reset_Handler
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Reset_Handler
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; Setup RSTC
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IF RSTC_SETUP != 0
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LDR R0, =RSTC_BASE
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LDR R1, =RSTC_MR_Val
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STR R1, [R0, #RSTC_MR]
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ENDIF
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; Setup EFC0
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IF EFC0_SETUP != 0
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LDR R0, =EFC_BASE
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LDR R1, =EFC0_FMR_Val
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STR R1, [R0, #EFC0_FMR]
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ENDIF
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; Setup EFC1
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IF EFC1_SETUP != 0
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LDR R0, =EFC_BASE
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LDR R1, =EFC1_FMR_Val
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STR R1, [R0, #EFC1_FMR]
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ENDIF
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; Setup WDT
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IF WDT_SETUP != 0
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LDR R0, =WDT_BASE
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LDR R1, =WDT_MR_Val
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STR R1, [R0, #WDT_MR]
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ENDIF
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; Setup PMC
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IF PMC_SETUP != 0
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LDR R0, =PMC_BASE
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; Setup Main Oscillator
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LDR R1, =PMC_MOR_Val
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STR R1, [R0, #PMC_MOR]
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; Wait until Main Oscillator is stablilized
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IF (PMC_MOR_Val:AND:PMC_MOSCEN) != 0
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MOSCS_Loop LDR R2, [R0, #PMC_SR]
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ANDS R2, R2, #PMC_MOSCS
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BEQ MOSCS_Loop
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ENDIF
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; Setup the PLL
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IF (PMC_PLLR_Val:AND:PMC_MUL) != 0
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LDR R1, =PMC_PLLR_Val
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STR R1, [R0, #PMC_PLLR]
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; Wait until PLL is stabilized
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PLL_Loop LDR R2, [R0, #PMC_SR]
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ANDS R2, R2, #PMC_LOCK
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BEQ PLL_Loop
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ENDIF
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; Select Clock
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IF (PMC_MCKR_Val:AND:PMC_CSS) == 1 ; Main Clock Selected
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LDR R1, =PMC_MCKR_Val
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AND R1, #PMC_CSS
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STR R1, [R0, #PMC_MCKR]
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WAIT_Rdy1 LDR R2, [R0, #PMC_SR]
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ANDS R2, R2, #PMC_MCKRDY
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BEQ WAIT_Rdy1
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LDR R1, =PMC_MCKR_Val
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STR R1, [R0, #PMC_MCKR]
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WAIT_Rdy2 LDR R2, [R0, #PMC_SR]
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ANDS R2, R2, #PMC_MCKRDY
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BEQ WAIT_Rdy2
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ELIF (PMC_MCKR_Val:AND:PMC_CSS) == 3 ; PLL Clock Selected
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LDR R1, =PMC_MCKR_Val
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AND R1, #PMC_PRES
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STR R1, [R0, #PMC_MCKR]
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WAIT_Rdy1 LDR R2, [R0, #PMC_SR]
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ANDS R2, R2, #PMC_MCKRDY
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BEQ WAIT_Rdy1
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LDR R1, =PMC_MCKR_Val
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STR R1, [R0, #PMC_MCKR]
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WAIT_Rdy2 LDR R2, [R0, #PMC_SR]
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ANDS R2, R2, #PMC_MCKRDY
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BEQ WAIT_Rdy2
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ENDIF ; Select Clock
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ENDIF ; PMC_SETUP
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; Copy Exception Vectors to Internal RAM
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IF :DEF:RAM_INTVEC
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ADR R8, Vectors ; Source
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LDR R9, =RAM_BASE ; Destination
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LDMIA R8!, {R0-R7} ; Load Vectors
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STMIA R9!, {R0-R7} ; Store Vectors
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LDMIA R8!, {R0-R7} ; Load Handler Addresses
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STMIA R9!, {R0-R7} ; Store Handler Addresses
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ENDIF
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; Remap on-chip RAM to address 0
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MC_BASE EQU 0xFFFFFF00 ; MC Base Address
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MC_RCR EQU 0x00 ; MC_RCR Offset
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IF :DEF:REMAP
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LDR R0, =MC_BASE
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MOV R1, #1
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STR R1, [R0, #MC_RCR] ; Remap
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ENDIF
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; Setup Stack for each mode
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LDR R0, =Stack_Top
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; Enter Undefined Instruction Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #UND_Stack_Size
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; Enter Abort Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #ABT_Stack_Size
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; Enter FIQ Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #FIQ_Stack_Size
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; Enter IRQ Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #IRQ_Stack_Size
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; Enter Supervisor Mode and set its Stack Pointer
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MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
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MOV SP, R0
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SUB R0, R0, #SVC_Stack_Size
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; Enter User Mode and set its Stack Pointer
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; MSR CPSR_c, #Mode_USR
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IF :DEF:__MICROLIB
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EXPORT __initial_sp
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ELSE
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MOV SP, R0
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SUB SL, SP, #USR_Stack_Size
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ENDIF
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; Enter the C code
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IMPORT __main
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LDR R0, =__main
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BX R0
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IMPORT rt_interrupt_enter
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IMPORT rt_interrupt_leave
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IMPORT rt_thread_switch_interrput_flag
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IMPORT rt_interrupt_from_thread
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IMPORT rt_interrupt_to_thread
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IMPORT rt_hw_trap_irq
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IRQ_Handler PROC
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EXPORT IRQ_Handler
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STMFD sp!, {r0-r12,lr}
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BL rt_interrupt_enter
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BL rt_hw_trap_irq
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BL rt_interrupt_leave
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; if rt_thread_switch_interrput_flag set, jump to
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; rt_hw_context_switch_interrupt_do and don't return
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LDR r0, =rt_thread_switch_interrput_flag
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LDR r1, [r0]
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CMP r1, #1
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BEQ rt_hw_context_switch_interrupt_do
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LDMFD sp!, {r0-r12,lr}
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SUBS pc, lr, #4
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ENDP
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; /*
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; * void rt_hw_context_switch_interrupt_do(rt_base_t flag)
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; */
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rt_hw_context_switch_interrupt_do PROC
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EXPORT rt_hw_context_switch_interrupt_do
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MOV r1, #0 ; clear flag
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STR r1, [r0]
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LDMFD sp!, {r0-r12,lr}; reload saved registers
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STMFD sp!, {r0-r3} ; save r0-r3
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MOV r1, sp
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ADD sp, sp, #16 ; restore sp
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SUB r2, lr, #4 ; save old task's pc to r2
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MRS r3, spsr ; get cpsr of interrupt thread
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; switch to SVC mode and no interrupt
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MSR cpsr_c, #I_Bit|F_Bit|Mode_SVC
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STMFD sp!, {r2} ; push old task's pc
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STMFD sp!, {r4-r12,lr}; push old task's lr,r12-r4
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MOV r4, r1 ; Special optimised code below
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MOV r5, r3
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LDMFD r4!, {r0-r3}
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STMFD sp!, {r0-r3} ; push old task's r3-r0
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STMFD sp!, {r5} ; push old task's cpsr
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MRS r4, spsr
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STMFD sp!, {r4} ; push old task's spsr
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LDR r4, =rt_interrupt_from_thread
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LDR r5, [r4]
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STR sp, [r5] ; store sp in preempted tasks's TCB
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LDR r6, =rt_interrupt_to_thread
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LDR r6, [r6]
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LDR sp, [r6] ; get new task's stack pointer
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LDMFD sp!, {r4} ; pop new task's spsr
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MSR spsr_cxsf, r4
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LDMFD sp!, {r4} ; pop new task's psr
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MSR cpsr_cxsf, r4
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LDMFD sp!, {r0-r12,lr,pc} ; pop new task's r0-r12,lr & pc
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|
ENDP
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|
IF :DEF:__MICROLIB
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|
|
|
EXPORT __heap_base
|
|
EXPORT __heap_limit
|
|
|
|
ELSE
|
|
; User Initial Stack & Heap
|
|
AREA |.text|, CODE, READONLY
|
|
|
|
IMPORT __use_two_region_memory
|
|
EXPORT __user_initial_stackheap
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|
__user_initial_stackheap
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|
|
|
LDR R0, = Heap_Mem
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|
LDR R1, =(Stack_Mem + USR_Stack_Size)
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|
LDR R2, = (Heap_Mem + Heap_Size)
|
|
LDR R3, = Stack_Mem
|
|
BX LR
|
|
ENDIF
|
|
|
|
END
|