94 lines
1.9 KiB
C
94 lines
1.9 KiB
C
#include "jz47xx.h"
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#include "cache.h"
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#define CACHE_SIZE 16*1024
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#define CACHE_LINE_SIZE 32
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#define KSEG0 0x80000000
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#define K0_TO_K1() \
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do { \
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unsigned long __k0_addr; \
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\
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__asm__ __volatile__( \
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"la %0, 1f\n\t" \
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"or %0, %0, %1\n\t" \
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"jr %0\n\t" \
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"nop\n\t" \
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"1: nop\n" \
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: "=&r"(__k0_addr) \
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: "r" (0x20000000) ); \
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} while(0)
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#define K1_TO_K0() \
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do { \
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unsigned long __k0_addr; \
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__asm__ __volatile__( \
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"nop;nop;nop;nop;nop;nop;nop\n\t" \
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"la %0, 1f\n\t" \
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"jr %0\n\t" \
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"nop\n\t" \
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"1: nop\n" \
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: "=&r" (__k0_addr)); \
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} while (0)
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#define INVALIDATE_BTB() \
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do { \
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unsigned long tmp; \
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__asm__ __volatile__( \
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".set mips32\n\t" \
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"mfc0 %0, $16, 7\n\t" \
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"nop\n\t" \
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"ori %0, 2\n\t" \
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"mtc0 %0, $16, 7\n\t" \
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"nop\n\t" \
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".set mips2\n\t" \
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: "=&r" (tmp)); \
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} while (0)
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#define SYNC_WB() __asm__ __volatile__ ("sync")
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#define cache_op(op,addr) \
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__asm__ __volatile__( \
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" .set noreorder \n" \
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" .set mips32\n\t \n" \
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" cache %0, %1 \n" \
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" .set mips0 \n" \
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" .set reorder" \
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: \
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: "i" (op), "m" (*(unsigned char *)(addr)))
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void __icache_invalidate_all(void)
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{
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unsigned int i;
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K0_TO_K1();
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asm volatile (".set noreorder\n"
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".set mips32\n\t"
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"mtc0\t$0,$28\n\t"
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"mtc0\t$0,$29\n"
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".set mips0\n"
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".set reorder\n");
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for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
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cache_op(Index_Store_Tag_I, i);
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K1_TO_K0();
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INVALIDATE_BTB();
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}
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void __dcache_writeback_all(void)
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{
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unsigned int i;
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for (i=KSEG0;i<KSEG0+CACHE_SIZE;i+=CACHE_LINE_SIZE)
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cache_op(Index_Writeback_Inv_D, i);
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SYNC_WB();
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}
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void rt_hw_cache_init(void)
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{
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__dcache_writeback_all();
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__icache_invalidate_all();
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}
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