826 lines
28 KiB
C
826 lines
28 KiB
C
/**
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******************************************************************************
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* @file ft32f0xx_spi.c
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* @author FMD AE
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* @brief This file provides firmware functions to manage the following
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* functionalities of the Serial peripheral interface (SPI):
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* + Initialization and Configuration
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* + Data transfers functions
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* + Hardware CRC Calculation
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* + DMA transfers management
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* + Interrupts and flags management
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* @version V1.0.0
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* @data 2021-07-01
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******************************************************************************
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*/
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/* Includes ------------------------------------------------------------------*/
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#include "ft32f0xx_spi.h"
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#include "ft32f0xx_rcc.h"
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/* SPI registers Masks */
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#define CR1_CLEAR_MASK ((uint16_t)0x3040)
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#define CR1_CLEAR_MASK2 ((uint16_t)0xFFFB)
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#define CR2_LDMA_MASK ((uint16_t)0x9FFF)
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#define I2SCFGR_CLEAR_Mask ((uint16_t)0xF040)
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/**
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* @brief Deinitializes the SPIx peripheral registers to their default
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* reset values.
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @retval None
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*/
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void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
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{
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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if (SPIx == SPI1)
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{
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/* Enable SPI1 reset state */
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
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/* Release SPI1 from reset state */
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RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
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}
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else
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{
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if (SPIx == SPI2)
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{
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/* Enable SPI2 reset state */
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
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/* Release SPI2 from reset state */
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RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
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}
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}
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}
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/**
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* @brief Fills each SPI_InitStruct member with its default value.
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* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
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* @retval None
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*/
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void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
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{
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/*--------------- Reset SPI init structure parameters values -----------------*/
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/* Initialize the SPI_Direction member */
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SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
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/* Initialize the SPI_Mode member */
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SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
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/* Initialize the SPI_DataSize member */
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SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
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/* Initialize the SPI_CPOL member */
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SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
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/* Initialize the SPI_CPHA member */
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SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
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/* Initialize the SPI_NSS member */
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SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
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/* Initialize the SPI_BaudRatePrescaler member */
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SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
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/* Initialize the SPI_FirstBit member */
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SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
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/* Initialize the SPI_CRCPolynomial member */
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SPI_InitStruct->SPI_CRCPolynomial = 7;
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}
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/**
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* @brief Initializes the SPIx peripheral according to the specified
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* parameters in the SPI_InitStruct.
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @param SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
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* contains the configuration information for the specified SPI peripheral.
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* @retval None
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*/
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void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
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{
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uint16_t tmpreg = 0;
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/* check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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/* Check the SPI parameters */
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assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
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assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
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assert_param(IS_SPI_DATA_SIZE(SPI_InitStruct->SPI_DataSize));
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assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
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assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
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assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
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assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
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assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
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assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
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/*---------------------------- SPIx CR1 Configuration ------------------------*/
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/* Get the SPIx CR1 value */
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tmpreg = SPIx->CR1;
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/* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, CPOL and CPHA bits */
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tmpreg &= CR1_CLEAR_MASK;
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/* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
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master/slave mode, CPOL and CPHA */
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/* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
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/* Set SSM, SSI bit according to SPI_NSS values */
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/* Set LSBFirst bit according to SPI_FirstBit value */
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/* Set BR bits according to SPI_BaudRatePrescaler value */
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/* Set CPOL bit according to SPI_CPOL value */
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/* Set CPHA bit according to SPI_CPHA value */
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tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_FirstBit |
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SPI_InitStruct->SPI_CPOL | SPI_InitStruct->SPI_CPHA |
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SPI_InitStruct->SPI_NSS | SPI_InitStruct->SPI_BaudRatePrescaler);
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/* Write to SPIx CR1 */
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SPIx->CR1 = tmpreg;
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/*-------------------------Data Size Configuration -----------------------*/
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/* Get the SPIx CR2 value */
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tmpreg = SPIx->CR2;
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/* Clear DS[3:0] bits */
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tmpreg &=(uint16_t)~SPI_CR2_DS;
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/* Configure SPIx: Data Size */
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tmpreg |= (uint16_t)(SPI_InitStruct->SPI_DataSize);
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/* Write to SPIx CR2 */
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SPIx->CR2 = tmpreg;
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/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
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/* Write to SPIx CRCPOLY */
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SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
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/*---------------------------- SPIx CR1 Configuration ------------------------*/
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/* Get the SPIx CR1 value */
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tmpreg = SPIx->CR1;
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/* Clear MSTR bit */
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tmpreg &= CR1_CLEAR_MASK2;
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/* Configure SPIx: master/slave mode */
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/* Set MSTR bit according to SPI_Mode */
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tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Mode);
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/* Write to SPIx CR1 */
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SPIx->CR1 = tmpreg;
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// /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
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// SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
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}
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/**
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* @brief Enables or disables the specified SPI peripheral.
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @param NewState: new state of the SPIx peripheral.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the selected SPI peripheral */
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SPIx->CR1 |= SPI_CR1_SPE;
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}
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else
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{
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/* Disable the selected SPI peripheral */
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SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
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}
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}
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/**
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* @brief Enables or disables the TI Mode.
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*
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* @note This function can be called only after the SPI_Init() function has
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* been called.
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* @note When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA
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* are not taken into consideration and are configured by hardware
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* respectively to the TI mode requirements.
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*
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @param NewState: new state of the selected SPI TI communication mode.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the TI mode for the selected SPI peripheral */
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SPIx->CR2 |= SPI_CR2_FRF;
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}
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else
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{
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/* Disable the TI mode for the selected SPI peripheral */
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SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRF);
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}
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}
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/**
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* @brief Configures the data size for the selected SPI.
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @param SPI_DataSize: specifies the SPI data size.
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* For the SPIx peripheral this parameter can be one of the following values:
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* @arg SPI_DataSize_4b: Set data size to 4 bits
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* @arg SPI_DataSize_5b: Set data size to 5 bits
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* @arg SPI_DataSize_6b: Set data size to 6 bits
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* @arg SPI_DataSize_7b: Set data size to 7 bits
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* @arg SPI_DataSize_8b: Set data size to 8 bits
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* @arg SPI_DataSize_9b: Set data size to 9 bits
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* @arg SPI_DataSize_10b: Set data size to 10 bits
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* @arg SPI_DataSize_11b: Set data size to 11 bits
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* @arg SPI_DataSize_12b: Set data size to 12 bits
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* @arg SPI_DataSize_13b: Set data size to 13 bits
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* @arg SPI_DataSize_14b: Set data size to 14 bits
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* @arg SPI_DataSize_15b: Set data size to 15 bits
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* @arg SPI_DataSize_16b: Set data size to 16 bits
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* @retval None
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*/
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void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
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{
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uint16_t tmpreg = 0;
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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assert_param(IS_SPI_DATA_SIZE(SPI_DataSize));
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/* Read the CR2 register */
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tmpreg = SPIx->CR2;
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/* Clear DS[3:0] bits */
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tmpreg &= (uint16_t)~SPI_CR2_DS;
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/* Set new DS[3:0] bits value */
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tmpreg |= SPI_DataSize;
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SPIx->CR2 = tmpreg;
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}
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/**
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* @brief Configures the FIFO reception threshold for the selected SPI.
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @param SPI_RxFIFOThreshold: specifies the FIFO reception threshold.
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* This parameter can be one of the following values:
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* @arg SPI_RxFIFOThreshold_HF: RXNE event is generated if the FIFO
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* level is greater or equal to 1/2.
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* @arg SPI_RxFIFOThreshold_QF: RXNE event is generated if the FIFO
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* level is greater or equal to 1/4.
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* @retval None
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*/
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void SPI_RxFIFOThresholdConfig(SPI_TypeDef* SPIx, uint16_t SPI_RxFIFOThreshold)
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{
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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assert_param(IS_SPI_RX_FIFO_THRESHOLD(SPI_RxFIFOThreshold));
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/* Clear FRXTH bit */
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SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_FRXTH);
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/* Set new FRXTH bit value */
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SPIx->CR2 |= SPI_RxFIFOThreshold;
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}
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/**
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* @brief Selects the data transfer direction in bidirectional mode for the specified SPI.
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @param SPI_Direction: specifies the data transfer direction in bidirectional mode.
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* This parameter can be one of the following values:
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* @arg SPI_Direction_Tx: Selects Tx transmission direction
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* @arg SPI_Direction_Rx: Selects Rx receive direction
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* @retval None
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*/
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void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
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{
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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assert_param(IS_SPI_DIRECTION(SPI_Direction));
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if (SPI_Direction == SPI_Direction_Tx)
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{
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/* Set the Tx only mode */
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SPIx->CR1 |= SPI_Direction_Tx;
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}
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else
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{
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/* Set the Rx only mode */
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SPIx->CR1 &= SPI_Direction_Rx;
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}
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}
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/**
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* @brief Configures internally by software the NSS pin for the selected SPI.
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* @note This function can be called only after the SPI_Init() function has
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* been called.
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @param SPI_NSSInternalSoft: specifies the SPI NSS internal state.
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* This parameter can be one of the following values:
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* @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
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* @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
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* @retval None
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*/
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void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
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{
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
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if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
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{
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/* Set NSS pin internally by software */
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SPIx->CR1 |= SPI_NSSInternalSoft_Set;
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}
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else
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{
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/* Reset NSS pin internally by software */
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SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
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}
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}
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/**
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* @brief Enables or disables the SS output for the selected SPI.
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* @note This function can be called only after the SPI_Init() function has
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* been called and the NSS hardware management mode is selected.
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @param NewState: new state of the SPIx SS output.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the selected SPI SS output */
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SPIx->CR2 |= SPI_CR2_SSOE;
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}
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else
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{
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/* Disable the selected SPI SS output */
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SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
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}
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}
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/**
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* @brief Enables or disables the NSS pulse management mode.
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* @note This function can be called only after the SPI_Init() function has
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* been called.
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* @note When TI mode is selected, the control bits NSSP is not taken into
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* consideration and are configured by hardware respectively to the
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* TI mode requirements.
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @param NewState: new state of the NSS pulse management mode.
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* This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void SPI_NSSPulseModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
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{
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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assert_param(IS_FUNCTIONAL_STATE(NewState));
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if (NewState != DISABLE)
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{
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/* Enable the NSS pulse management mode */
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SPIx->CR2 |= SPI_CR2_NSSP;
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}
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else
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{
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/* Disable the NSS pulse management mode */
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SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_NSSP);
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}
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}
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/**
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* @}
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*/
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/**
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* @brief Transmits a Data through the SPIx/I2Sx peripheral.
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* @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral.
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* @param Data: Data to be transmitted.
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* @retval None
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*/
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void SPI_SendData8(SPI_TypeDef* SPIx, uint8_t Data)
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{
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uint32_t spixbase = 0x00;
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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spixbase = (uint32_t)SPIx;
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spixbase += 0x0C;
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*(__IO uint8_t *) spixbase = Data;
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}
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/**
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* @brief Transmits a Data through the SPIx/I2Sx peripheral.
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* @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
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* the SPI peripheral.
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* @param Data: Data to be transmitted.
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* @retval None
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*/
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void SPI_I2S_SendData16(SPI_TypeDef* SPIx, uint16_t Data)
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{
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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SPIx->DR = (uint16_t)Data;
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}
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/**
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* @brief Returns the most recent received data by the SPIx/I2Sx peripheral.
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* @param SPIx: where x can be 1 or 2 in SPI mode to select the SPI peripheral.
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* @retval The value of the received data.
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*/
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uint8_t SPI_ReceiveData8(SPI_TypeDef* SPIx)
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{
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uint32_t spixbase = 0x00;
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spixbase = (uint32_t)SPIx;
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spixbase += 0x0C;
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return *(__IO uint8_t *) spixbase;
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}
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/**
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* @brief Returns the most recent received data by the SPIx peripheral.
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* @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
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* the SPI peripheral.
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* @retval The value of the received data.
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*/
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uint16_t SPI_I2S_ReceiveData16(SPI_TypeDef* SPIx)
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{
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return SPIx->DR;
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}
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/**
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* @}
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*/
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/**
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* @brief Configures the CRC calculation length for the selected SPI.
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* @note This function can be called only after the SPI_Init() function has
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* been called.
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* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
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* @param SPI_CRCLength: specifies the SPI CRC calculation length.
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* This parameter can be one of the following values:
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* @arg SPI_CRCLength_8b: Set CRC Calculation to 8 bits
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* @arg SPI_CRCLength_16b: Set CRC Calculation to 16 bits
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* @retval None
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*/
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void SPI_CRCLengthConfig(SPI_TypeDef* SPIx, uint16_t SPI_CRCLength)
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{
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/* Check the parameters */
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assert_param(IS_SPI_ALL_PERIPH(SPIx));
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|
assert_param(IS_SPI_CRC_LENGTH(SPI_CRCLength));
|
|
|
|
/* Clear CRCL bit */
|
|
SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCL);
|
|
|
|
/* Set new CRCL bit value */
|
|
SPIx->CR1 |= SPI_CRCLength;
|
|
}
|
|
|
|
/**
|
|
* @brief Enables or disables the CRC value calculation of the transferred bytes.
|
|
* @note This function can be called only after the SPI_Init() function has
|
|
* been called.
|
|
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
|
|
* @param NewState: new state of the SPIx CRC value calculation.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
/* Enable the selected SPI CRC calculation */
|
|
SPIx->CR1 |= SPI_CR1_CRCEN;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the selected SPI CRC calculation */
|
|
SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Transmit the SPIx CRC value.
|
|
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
|
|
* @retval None
|
|
*/
|
|
void SPI_TransmitCRC(SPI_TypeDef* SPIx)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
|
|
|
/* Enable the selected SPI CRC transmission */
|
|
SPIx->CR1 |= SPI_CR1_CRCNEXT;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the transmit or the receive CRC register value for the specified SPI.
|
|
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
|
|
* @param SPI_CRC: specifies the CRC register to be read.
|
|
* This parameter can be one of the following values:
|
|
* @arg SPI_CRC_Tx: Selects Tx CRC register
|
|
* @arg SPI_CRC_Rx: Selects Rx CRC register
|
|
* @retval The selected CRC register value..
|
|
*/
|
|
uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
|
|
{
|
|
uint16_t crcreg = 0;
|
|
/* Check the parameters */
|
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
|
assert_param(IS_SPI_CRC(SPI_CRC));
|
|
|
|
if (SPI_CRC != SPI_CRC_Rx)
|
|
{
|
|
/* Get the Tx CRC register */
|
|
crcreg = SPIx->TXCRCR;
|
|
}
|
|
else
|
|
{
|
|
/* Get the Rx CRC register */
|
|
crcreg = SPIx->RXCRCR;
|
|
}
|
|
/* Return the selected CRC register */
|
|
return crcreg;
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the CRC Polynomial register value for the specified SPI.
|
|
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
|
|
* @retval The CRC Polynomial register value.
|
|
*/
|
|
uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
|
|
|
/* Return the CRC polynomial register */
|
|
return SPIx->CRCPR;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
/**
|
|
* @brief Enables or disables the SPIx/I2Sx DMA interface.
|
|
* @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
|
|
* the SPI peripheral.
|
|
* @param SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled.
|
|
* This parameter can be any combination of the following values:
|
|
* @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
|
|
* @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
|
|
* @param NewState: new state of the selected SPI DMA transfer request.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
assert_param(IS_SPI_I2S_DMA_REQ(SPI_I2S_DMAReq));
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
/* Enable the selected SPI DMA requests */
|
|
SPIx->CR2 |= SPI_I2S_DMAReq;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the selected SPI DMA requests */
|
|
SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Configures the number of data to transfer type(Even/Odd) for the DMA
|
|
* last transfers and for the selected SPI.
|
|
* @note This function have a meaning only if DMA mode is selected and if
|
|
* the packing mode is used (data length <= 8 and DMA transfer size halfword)
|
|
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
|
|
* @param SPI_LastDMATransfer: specifies the SPI last DMA transfers state.
|
|
* This parameter can be one of the following values:
|
|
* @arg SPI_LastDMATransfer_TxEvenRxEven: Number of data for transmission Even
|
|
* and number of data for reception Even.
|
|
* @arg SPI_LastDMATransfer_TxOddRxEven: Number of data for transmission Odd
|
|
* and number of data for reception Even.
|
|
* @arg SPI_LastDMATransfer_TxEvenRxOdd: Number of data for transmission Even
|
|
* and number of data for reception Odd.
|
|
* @arg SPI_LastDMATransfer_TxOddRxOdd: Number of data for transmission Odd
|
|
* and number of data for reception Odd.
|
|
* @retval None
|
|
*/
|
|
void SPI_LastDMATransferCmd(SPI_TypeDef* SPIx, uint16_t SPI_LastDMATransfer)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
|
assert_param(IS_SPI_LAST_DMA_TRANSFER(SPI_LastDMATransfer));
|
|
|
|
/* Clear LDMA_TX and LDMA_RX bits */
|
|
SPIx->CR2 &= CR2_LDMA_MASK;
|
|
|
|
/* Set new LDMA_TX and LDMA_RX bits value */
|
|
SPIx->CR2 |= SPI_LastDMATransfer;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
/**
|
|
* @brief Enables or disables the specified SPI/I2S interrupts.
|
|
* @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
|
|
* the SPI peripheral.
|
|
* @param SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled.
|
|
* This parameter can be one of the following values:
|
|
* @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
|
|
* @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
|
|
* @arg SPI_I2S_IT_ERR: Error interrupt mask
|
|
* @param NewState: new state of the specified SPI interrupt.
|
|
* This parameter can be: ENABLE or DISABLE.
|
|
* @retval None
|
|
*/
|
|
void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
|
|
{
|
|
uint16_t itpos = 0, itmask = 0 ;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
|
assert_param(IS_FUNCTIONAL_STATE(NewState));
|
|
assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
|
|
|
|
/* Get the SPI IT index */
|
|
itpos = SPI_I2S_IT >> 4;
|
|
|
|
/* Set the IT mask */
|
|
itmask = (uint16_t)1 << (uint16_t)itpos;
|
|
|
|
if (NewState != DISABLE)
|
|
{
|
|
/* Enable the selected SPI interrupt */
|
|
SPIx->CR2 |= itmask;
|
|
}
|
|
else
|
|
{
|
|
/* Disable the selected SPI interrupt */
|
|
SPIx->CR2 &= (uint16_t)~itmask;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the current SPIx Transmission FIFO filled level.
|
|
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
|
|
* @retval The Transmission FIFO filling state.
|
|
* - SPI_TransmissionFIFOStatus_Empty: when FIFO is empty
|
|
* - SPI_TransmissionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
|
|
* - SPI_TransmissionFIFOStatus_HalfFull: if more than 1 half-full.
|
|
* - SPI_TransmissionFIFOStatus_Full: when FIFO is full.
|
|
*/
|
|
uint16_t SPI_GetTransmissionFIFOStatus(SPI_TypeDef* SPIx)
|
|
{
|
|
/* Get the SPIx Transmission FIFO level bits */
|
|
return (uint16_t)((SPIx->SR & SPI_SR_FTLVL));
|
|
}
|
|
|
|
/**
|
|
* @brief Returns the current SPIx Reception FIFO filled level.
|
|
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
|
|
* @retval The Reception FIFO filling state.
|
|
* - SPI_ReceptionFIFOStatus_Empty: when FIFO is empty
|
|
* - SPI_ReceptionFIFOStatus_1QuarterFull: if more than 1 quarter-full.
|
|
* - SPI_ReceptionFIFOStatus_HalfFull: if more than 1 half-full.
|
|
* - SPI_ReceptionFIFOStatus_Full: when FIFO is full.
|
|
*/
|
|
uint16_t SPI_GetReceptionFIFOStatus(SPI_TypeDef* SPIx)
|
|
{
|
|
/* Get the SPIx Reception FIFO level bits */
|
|
return (uint16_t)((SPIx->SR & SPI_SR_FRLVL));
|
|
}
|
|
|
|
/**
|
|
* @brief Checks whether the specified SPI flag is set or not.
|
|
* @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
|
|
* the SPI peripheral.
|
|
* @param SPI_I2S_FLAG: specifies the SPI flag to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
|
|
* @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
|
|
* @arg SPI_I2S_FLAG_BSY: Busy flag.
|
|
* @arg SPI_I2S_FLAG_OVR: Overrun flag.
|
|
* @arg SPI_FLAG_MODF: Mode Fault flag.
|
|
* @arg SPI_FLAG_CRCERR: CRC Error flag.
|
|
* @arg SPI_I2S_FLAG_FRE: TI frame format error flag.
|
|
* @arg I2S_FLAG_UDR: Underrun Error flag.
|
|
* @arg I2S_FLAG_CHSIDE: Channel Side flag.
|
|
* @retval The new state of SPI_I2S_FLAG (SET or RESET).
|
|
*/
|
|
FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
|
|
{
|
|
FlagStatus bitstatus = RESET;
|
|
/* Check the parameters */
|
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
|
assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
|
|
|
|
/* Check the status of the specified SPI flag */
|
|
if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
|
|
{
|
|
/* SPI_I2S_FLAG is set */
|
|
bitstatus = SET;
|
|
}
|
|
else
|
|
{
|
|
/* SPI_I2S_FLAG is reset */
|
|
bitstatus = RESET;
|
|
}
|
|
/* Return the SPI_I2S_FLAG status */
|
|
return bitstatus;
|
|
}
|
|
|
|
/**
|
|
* @brief Clears the SPIx CRC Error (CRCERR) flag.
|
|
* @param SPIx: where x can be 1 or 2 to select the SPI peripheral.
|
|
* @param SPI_I2S_FLAG: specifies the SPI flag to clear.
|
|
* This function clears only CRCERR flag.
|
|
* @note OVR (OverRun error) flag is cleared by software sequence: a read
|
|
* operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by
|
|
* a read operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
|
|
* @note MODF (Mode Fault) flag is cleared by software sequence: a read/write
|
|
* operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by
|
|
* a write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
|
|
* @retval None
|
|
*/
|
|
void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
|
|
{
|
|
/* Check the parameters */
|
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
|
assert_param(IS_SPI_CLEAR_FLAG(SPI_I2S_FLAG));
|
|
|
|
/* Clear the selected SPI CRC Error (CRCERR) flag */
|
|
SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
|
|
}
|
|
|
|
/**
|
|
* @brief Checks whether the specified SPI/I2S interrupt has occurred or not.
|
|
* @param SPIx: where x can be 1 or 2 in SPI mode or 1 in I2S mode to select
|
|
* the SPI peripheral.
|
|
* @param SPI_I2S_IT: specifies the SPI interrupt source to check.
|
|
* This parameter can be one of the following values:
|
|
* @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
|
|
* @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
|
|
* @arg SPI_IT_MODF: Mode Fault interrupt.
|
|
* @arg SPI_I2S_IT_OVR: Overrun interrupt.
|
|
* @arg I2S_IT_UDR: Underrun interrupt.
|
|
* @arg SPI_I2S_IT_FRE: Format Error interrupt.
|
|
* @retval The new state of SPI_I2S_IT (SET or RESET).
|
|
*/
|
|
ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
|
|
{
|
|
ITStatus bitstatus = RESET;
|
|
uint16_t itpos = 0, itmask = 0, enablestatus = 0;
|
|
|
|
/* Check the parameters */
|
|
assert_param(IS_SPI_ALL_PERIPH(SPIx));
|
|
assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
|
|
|
|
/* Get the SPI_I2S_IT index */
|
|
itpos = 0x01 << (SPI_I2S_IT & 0x0F);
|
|
|
|
/* Get the SPI_I2S_IT IT mask */
|
|
itmask = SPI_I2S_IT >> 4;
|
|
|
|
/* Set the IT mask */
|
|
itmask = 0x01 << itmask;
|
|
|
|
/* Get the SPI_I2S_IT enable bit status */
|
|
enablestatus = (SPIx->CR2 & itmask) ;
|
|
|
|
/* Check the status of the specified SPI interrupt */
|
|
if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
|
|
{
|
|
/* SPI_I2S_IT is set */
|
|
bitstatus = SET;
|
|
}
|
|
else
|
|
{
|
|
/* SPI_I2S_IT is reset */
|
|
bitstatus = RESET;
|
|
}
|
|
/* Return the SPI_I2S_IT status */
|
|
return bitstatus;
|
|
}
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/**
|
|
* @}
|
|
*/
|
|
|
|
/************************ (C) COPYRIGHT FMD *****END OF FILE****/
|