277 lines
12 KiB
C
277 lines
12 KiB
C
/**
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*****************************************************************************
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* @file cmem7_misc.h
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*
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* @brief CMEM7 miscellaneous header file
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*
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*
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* @version V1.0
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* @date 3. September 2013
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*
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* @note
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*
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*****************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2>
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*****************************************************************************
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*/
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#ifndef __CMEM7_MISC_H
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#define __CMEM7_MISC_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "cmem7.h"
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#include "cmem7_conf.h"
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/**
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* @brief NVIC initialization structure
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*/
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/**
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@code
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The table below gives the allowed values of the pre-emption priority and subpriority according
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to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
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============================================================================================================================
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NVIC_PriorityGroup | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority | Description
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============================================================================================================================
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NVIC_PriorityGroup_0 | 0 | 0-15 | 0 bits for pre-emption priority
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| | | 4 bits for subpriority
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----------------------------------------------------------------------------------------------------------------------------
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NVIC_PriorityGroup_1 | 0-1 | 0-7 | 1 bits for pre-emption priority
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| | | 3 bits for subpriority
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----------------------------------------------------------------------------------------------------------------------------
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NVIC_PriorityGroup_2 | 0-3 | 0-3 | 2 bits for pre-emption priority
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| | | 2 bits for subpriority
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----------------------------------------------------------------------------------------------------------------------------
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NVIC_PriorityGroup_3 | 0-7 | 0-1 | 3 bits for pre-emption priority
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| | | 1 bits for subpriority
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----------------------------------------------------------------------------------------------------------------------------
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NVIC_PriorityGroup_4 | 0-15 | 0 | 4 bits for pre-emption priority
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| | | 0 bits for subpriority
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============================================================================================================================
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@endcode
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*/
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typedef struct
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{
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uint8_t NVIC_IRQChannel; /*!< Specifies the IRQ channel to be enabled or disabled.
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This parameter can be a value of @ref IRQn_Type
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(For the complete Capital-micro Devices IRQ Channels list, please
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refer to cmem7.h file) */
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uint8_t NVIC_IRQChannelPreemptionPriority; /*!< Specifies the pre-emption priority for the IRQ channel
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specified in NVIC_IRQChannel. This parameter can be a value
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between 0 and 15 as described in the table @ref NVIC_Priority_Table */
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uint8_t NVIC_IRQChannelSubPriority; /*!< Specifies the subpriority level for the IRQ channel specified
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in NVIC_IRQChannel. This parameter can be a value
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between 0 and 15 as described in the table @ref NVIC_Priority_Table */
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BOOL NVIC_IRQChannelCmd; /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
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will be enabled or disabled.
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This parameter can be set either to ENABLE or DISABLE */
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} NVIC_InitTypeDef;
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/** @defgroup NVIC_VectTab
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* @{
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*/
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#define NVIC_VectTab_CME_CODE ((uint32_t)0x00000000)
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#define NVIC_VectTab_RAM ((uint32_t)0x20000000)
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#define NVIC_VectTab_FLASH ((uint32_t)0x08000000)
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#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_CME_CODE) || \
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((VECTTAB) == NVIC_VectTab_RAM) || \
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((VECTTAB) == NVIC_VectTab_FLASH))
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/**
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* @}
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*/
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/** @defgroup NVIC_LP
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* @{
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*/
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#define NVIC_LP_SEVONPEND ((uint8_t)0x10)
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#define NVIC_LP_SLEEPDEEP ((uint8_t)0x04)
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#define NVIC_LP_SLEEPONEXIT ((uint8_t)0x02)
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#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
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((LP) == NVIC_LP_SLEEPDEEP) || \
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((LP) == NVIC_LP_SLEEPONEXIT))
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/**
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* @}
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*/
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/** @defgroup NVIC_PriorityGroup
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* @{
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*/
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#define NVIC_PriorityGroup_0 ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
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4 bits for subpriority */
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#define NVIC_PriorityGroup_1 ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
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3 bits for subpriority */
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#define NVIC_PriorityGroup_2 ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
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2 bits for subpriority */
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#define NVIC_PriorityGroup_3 ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
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1 bits for subpriority */
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#define NVIC_PriorityGroup_4 ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
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0 bits for subpriority */
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#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
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((GROUP) == NVIC_PriorityGroup_1) || \
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((GROUP) == NVIC_PriorityGroup_2) || \
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((GROUP) == NVIC_PriorityGroup_3) || \
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((GROUP) == NVIC_PriorityGroup_4))
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/**
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* @}
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*/
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#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
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#define IS_NVIC_SUB_PRIORITY(PRIORITY) ((PRIORITY) < 0x10)
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#define IS_NVIC_OFFSET(OFFSET) ((OFFSET) < 0x000FFFFF)
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/**
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* @brief Configures the priority grouping: pre-emption priority and subpriority.
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* @param NVIC_PriorityGroup: specifies the priority grouping bits length.
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* This parameter can be one of the following values, ref as @ref NVIC_PriorityGroup:
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* @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
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* 4 bits for subpriority
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* @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
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* 3 bits for subpriority
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* @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
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* 2 bits for subpriority
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* @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
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* 1 bits for subpriority
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* @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
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* 0 bits for subpriority
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* @retval None
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*/
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void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
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/**
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* @brief Initializes the NVIC peripheral according to the specified
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* parameters in the NVIC_InitStruct.
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* @param NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
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* the configuration information for the specified NVIC peripheral.
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* @retval None
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*/
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void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
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/**
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* @brief Sets the vector table location and Offset.
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* @param NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
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* This parameter can be one of the following values, ref as @ref NVIC_VectTab:
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* @arg NVIC_VectTab_RAM
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* @arg NVIC_VectTab_FLASH
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* @param Offset: Vector Table base offset field. This value must be a multiple
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* of 0x200.
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* @retval None
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*/
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void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
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/**
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* @brief Selects the condition for the system to enter low power mode.
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* @param LowPowerMode: Specifies the new mode for the system to enter low power mode.
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* This parameter can be one of the following values, ref as @ref NVIC_LP:
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* @arg NVIC_LP_SEVONPEND
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* @arg NVIC_LP_SLEEPDEEP
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* @arg NVIC_LP_SLEEPONEXIT
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* @param NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
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* @retval None
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*/
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void NVIC_SystemLPConfig(uint8_t LowPowerMode, BOOL NewState);
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/**
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* @brief Memory map from address 'from' to 'address 'to' and open icache or not
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* @param[in] from address to be mapped from
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* @param[in] to address to be mapped to
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* @param[in] isIcacheOn icache is on or off
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* @retval None
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*/
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void GLB_MMAP(uint32_t from, uint32_t to, BOOL isIcacheOn);
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/**
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* @brief Convert the mapping destination address to source address
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* @param[in] to address to be mapped to
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* @retval uint32_t address to be mapped from
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*/
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uint32_t GLB_ConvertToMappingFromAddr(uint32_t to);
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/**
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* @brief Convert the mapping source address to destination address
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* @param[in] from address to be mapped from
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* @retval uint32_t address to be mapped to
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*/
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uint32_t GLB_ConvertToMappingToAddr(uint32_t from);
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/**
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* @brief Set NMI irq number, it should be one of @ref IRQn_Type.
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* @Note You can assign any valid IRQn_Type to NMI. After that, you will enter NMI
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* interrupt routine if the specific 'irq' occurs. By default, NMI irq number
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* is 0, same as ETH_INT_IRQn
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* @param[in] irq irq number
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* @retval None
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*/
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void GLB_SetNmiIrqNum(uint32_t irq);
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/** @defgroup SYS_CLK_SEL
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* @{
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*/
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#define SYS_CLK_SEL_OSC 0x0
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#define SYS_CLK_SEL_DLL 0x1
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#define SYS_CLK_SEL_CRYSTAL 0x2
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#define SYS_CLK_SEL_EXTERNAL 0x3
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/**
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* @}
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*/
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/**
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* @brief Select system clock source, it should be one of @ref SYS_CLK_SEL.
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* @Note You MUST make sure externel clock has been stabled if clock
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* source is external before call this function.
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* Default value is SYS_CLK_SEL_OSC
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* @param[in] irq irq number
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* @retval None
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*/
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void GLB_SelectSysClkSource(uint8_t source);
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/**
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* @brief Simulate instruction 'STRB' or 'STRH' with 'BFI'
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* @Note In M7, you have to write a register in 32-bit alignment,
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* not in 8-bit or 16-bit.
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* @param[in] addr register address to be written
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* @param[in] value value to be written
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* @param[in] lsb LSB in register to be written
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* @param[in] len bit length to be written
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* @retval None
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*/
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//#define aaaa(len) __asm("LDR len, 11")
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#define CMEM7_BFI(addr, value, lsb, len) \
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do { \
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unsigned long tmp; \
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unsigned long tmp1 = (unsigned long)addr; \
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\
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__asm("LDR tmp, [tmp1]\n" \
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"BFI tmp, "#value", "#lsb", "#len" \n" \
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"STR tmp, [tmp1]\n"); \
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} while (0)
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CMEM7_MISC_H */
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