186 lines
3.8 KiB
C
186 lines
3.8 KiB
C
/**
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*****************************************************************************
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* @file cmem7_ddr.h
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*
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* @brief CMEM7 AES header file
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*
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*
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* @version V1.0
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* @date 3. September 2013
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*
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* @note
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*
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*****************************************************************************
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* @attention
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*
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* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
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* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
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* TIME. AS A RESULT, CAPITAL-MICRO SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
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* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
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* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
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* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
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*
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* <h2><center>© COPYRIGHT 2013 Capital-micro </center></h2>
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*****************************************************************************
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*/
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#ifndef __CMEM7_DDR_H
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#define __CMEM7_DDR_H
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "cmem7.h"
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#include "cmem7_conf.h"
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/** @defgroup _MEM_TYPE
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* @{
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*/
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enum _MEM_TYPE
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{
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MEM_DDR2=1,
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MEM_DDR3
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} ;
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/**
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* @}
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*/
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/** @defgroup _BUS_WIDTH
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* @{
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*/
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enum _BUS_WIDTH
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{
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BUS_WIDTH_8,
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BUS_WIDTH_16,
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BUS_WIDTH_MAX
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};
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/**
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* @}
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*/
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/** @defgroup _CHIP_TYPE
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* @{
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*/
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enum _CHIP_TYPE
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{
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_32Mbx8,
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_64Mbx8,
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_128Mbx8,
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_256Mbx8,
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_512Mbx8,
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_16Mbx16,
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_32Mbx16,
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_64Mbx16,
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_128Mbx16,
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_256Mbx16,
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_512Mbx16,
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CHIP_TYPE_MAX
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};
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/**
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* @}
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*/
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/** @defgroup _CHIP_NUM
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* @{
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*/
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enum _CHIP_NUM
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{
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CHIP_NUM_x1,
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CHIP_NUM_x2,
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CHIP_NUM_MAX
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};
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/**
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* @}
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*/
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/** @defgroup MEM_CHIP_INFO
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* @{
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*/
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typedef struct {
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uint8_t mem_type; /*!< ddr type @ref _MEM_TYPE*/
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uint8_t Bus_width; /*!< ddr qs bus width @ref _BUS_WIDTH*/
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uint8_t Chip_type; /*!< chip type @ref _CHIP_TYPE*/
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uint8_t Chip_num; /*!< chip number @ref _CHIP_NUM*/
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uint8_t Chip_bank; /*!< chip bank number*/
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} MEM_CHIP_INFO;
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/**
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* @}
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*/
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/** @defgroup DDR2MEM
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* @{
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*/
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typedef struct {
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uint32_t tCK; /*!< Period of clock(ps), not data period */
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uint32_t tCL; /*!< tCL */
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uint32_t tRCD; /*!< tRCD */
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uint32_t tRP; /*!< tRP */
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uint32_t tRC; /*!< tRC */
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uint32_t tRAS; /*!< tRAS */
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uint32_t tWR; /*!< tWR */
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uint32_t tRRD; /*!< tRRD */
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uint32_t tWTR; /*!< tWTR */
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uint32_t tRTP; /*!< tRTP */
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uint32_t tFAW; /*!< tFAW */
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} DDR2MEM; /*!< DDR2ʱ<32><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/**
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* @}
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*/
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/** @defgroup DDR3MEM
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* @{
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*/
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typedef struct {
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uint32_t tCK; /*!< Period of clock(ps), not data period */
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uint32_t tCL; /*!< tCL */
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uint32_t tWCL; /*!< tWCL */
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uint32_t tRCD; /*!< tRCD */
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uint32_t tRAS; /*!< tRAS */
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uint32_t tRP; /*!< tRP */
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uint32_t tRC; /*!< tRC */
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uint32_t tRRD; /*!< tRRD */
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uint32_t tFAW; /*!< tFAW */
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uint32_t tWR; /*!< tWR */
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uint32_t tRTP; /*!< tRTP */
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uint32_t tZQoper; /*!< tZQCL */
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uint32_t tZQCS; /*!< tZQCS */
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} DDR3MEM; /*!< DDR3ʱ<33><CAB1><EFBFBD><EFBFBD><EFBFBD><EFBFBD> */
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/**
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* @}
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*/
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/** @defgroup DDR2PREDEF
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* @{
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*/
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extern const DDR2MEM DDR2PREDEF[]; /*!< Pre-defined DDR2 Timing in library */
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#define DDR2_400C 0 /*!< sg5E: DDR2-400C CL=4, tCK=5000ps */
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/**
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* @}
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*/
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/** @defgroup DDR3PREDEF
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* @{
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*/
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extern const DDR3MEM DDR3PREDEF[]; /*!< Pre-defined DDR3 Timing in library */
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#define DDR3_400 0
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#define DDR3_667 1
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/**
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* @}
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*/
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/**
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* @brief DDR Timing Configuration
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* @param[in] chip information ,A pointer to struct @ref MEM_CHIP_INFO
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* @param[in] ddr A pointer to struct @ref DDR2MEM or @ref DDR3MEM that specified DDR Timing. Some typital DDR2/3 Timings are defined in arrays @ref DDR2PREDEF and @ref DDR3PREDEF.
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* @retval void
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*/
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BOOL DDR_Init(const MEM_CHIP_INFO *chip_info, const void *ddr);
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#ifdef __cplusplus
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}
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#endif
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#endif /* __CMEM7_DDR_H */
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