333 lines
8.0 KiB
C
333 lines
8.0 KiB
C
/**************************************************************************//**
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*
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* @copyright (C) 2020 Nuvoton Technology Corp. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-11-11 Wayne First version
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*
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******************************************************************************/
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#include <rthw.h>
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#include <rtthread.h>
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#include "NuMicro.h"
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#include "drv_sys.h"
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#define SYS_MIN_INT_SOURCE 1
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#define SYS_MAX_INT_SOURCE 62
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#define SYS_NUM_OF_AICREG 16
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#define INT_IRQ 0x00
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#define INT_FIQ 0x01
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extern rt_uint32_t rt_interrupt_nest;
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rt_uint32_t rt_interrupt_from_thread, rt_interrupt_to_thread;
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rt_uint32_t rt_thread_switch_interrupt_flag;
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struct rt_irq_desc irq_desc[SYS_MAX_INT_SOURCE + 1];
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void rt_hw_interrupt_dummy_handler(int vector, void *param)
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{
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rt_kprintf("Unhandled interrupt %d occurred!!!\n", vector);
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RT_ASSERT(0);
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}
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void rt_hw_interrupt_set_priority(int vector, int IntTypeLevel)
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{
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sysSetInterruptPriorityLevel((IRQn_Type)vector, (UINT32)IntTypeLevel);
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}
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void rt_interrupt_dispatch(rt_uint32_t fiq_irq)
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{
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rt_isr_handler_t isr_func;
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rt_uint32_t volatile _mIPER, _mISNR;
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void *param;
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/* Get irq number */
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_mIPER = (inpw(REG_AIC_IPER) >> 2) & 0x3f;
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_mISNR = inpw(REG_AIC_ISNR) & 0x3f;
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if (_mISNR != 0)
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{
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if (_mIPER == _mISNR)
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{
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/* Get interrupt service routine */
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isr_func = irq_desc[_mISNR].handler;
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param = irq_desc[_mISNR].param;
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#ifdef RT_USING_INTERRUPT_INFO
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irq_desc[_mISNR].counter ++;
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#endif
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/* Turn to interrupt service routine */
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isr_func(_mISNR, param);
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}
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}
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/* Handled the ISR. */
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outpw(REG_AIC_EOSCR, 1);
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}
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void rt_hw_interrupt_init(void)
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{
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int i;
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*((volatile unsigned int *)REG_AIC_ISR) = 0xFFFFFFFF; // disable all interrupt channel
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*((volatile unsigned int *)REG_AIC_ISRH) = 0xFFFFFFFF; // disable all interrupt channel
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/* init interrupt nest, and context in thread sp */
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rt_interrupt_nest = 0;
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rt_interrupt_from_thread = 0;
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rt_interrupt_to_thread = 0;
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rt_thread_switch_interrupt_flag = 0;
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for (i = SYS_MIN_INT_SOURCE; i <= SYS_MAX_INT_SOURCE; i++)
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{
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rt_hw_interrupt_install(i, rt_hw_interrupt_dummy_handler, RT_NULL, (char *)"dummy");
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rt_hw_interrupt_mask(i);
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}
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}
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rt_isr_handler_t rt_hw_interrupt_install(int vector, rt_isr_handler_t handler, void *param, const char *name)
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{
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rt_isr_handler_t old_handler = RT_NULL;
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if (vector > SYS_MAX_INT_SOURCE)
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return RT_NULL;
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/* Set default priority IRQ_LEVEL_7 */
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rt_hw_interrupt_set_priority(vector, IRQ_LEVEL_7);
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old_handler = irq_desc[vector].handler;
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if (handler != RT_NULL)
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{
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irq_desc[vector].handler = (rt_isr_handler_t)handler;
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irq_desc[vector].param = param;
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#ifdef RT_USING_INTERRUPT_INFO
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rt_snprintf(irq_desc[vector].name, RT_NAME_MAX - 1, "%s", name);
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irq_desc[vector].counter = 0;
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#endif
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}
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return old_handler;
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}
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/* Disable interrupt */
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void rt_hw_interrupt_mask(int vector)
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{
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sysDisableInterrupt((IRQn_Type)vector);
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}
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void rt_hw_interrupt_umask(int vector)
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{
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sysEnableInterrupt((IRQn_Type)vector);
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}
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/* TYPE
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* #define LOW_LEVEL_SENSITIVE 0x00
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* #define HIGH_LEVEL_SENSITIVE 0x40
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* #define NEGATIVE_EDGE_TRIGGER 0x80
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* #define POSITIVE_EDGE_TRIGGER 0xC0
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*/
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void rt_hw_interrupt_set_type(int vector, int type)
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{
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sysSetInterruptType((IRQn_Type)vector, (UINT32) type);
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}
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void rt_low_level_init(void)
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{
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/* Unlock write-protect */
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SYS_UnlockReg();
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/* Close WDT first, to avoid WDT timer is enabled IBR timeout reset. */
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WDT_Close();
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/* Lock write-protect */
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SYS_LockReg();
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}
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void nu_clock_base_init(void)
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{
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nu_sys_ipclk_enable(CPUCKEN);
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nu_sys_ipclk_enable(HCLKCKEN);
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nu_sys_ipclk_enable(HCLK1CKEN);
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nu_sys_ipclk_enable(HCLK3CKEN);
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nu_sys_ipclk_enable(HCLK4CKEN);
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nu_sys_ipclk_enable(PCLKCKEN);
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nu_sys_ipclk_enable(SRAMCKEN);
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nu_sys_ipclk_enable(DDRCKEN);
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}
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void machine_reset(void)
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{
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rt_kprintf("machine_reset...\n");
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rt_hw_interrupt_disable();
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/* Unlock */
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SYS_UnlockReg();
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nu_sys_ip_reset(CHIPRST);
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while (1);
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}
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void machine_shutdown(void)
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{
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rt_kprintf("machine_shutdown...\n");
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rt_hw_interrupt_disable();
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/* Unlock */
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SYS_UnlockReg();
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while (1);
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}
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void nu_sys_ip_reset(E_SYS_IPRST eIPRstIdx)
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{
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uint32_t volatile u32IPRSTRegAddr;
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uint32_t u32IPRSTRegBit;
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rt_uint32_t level;
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if (eIPRstIdx >= SYS_IPRST_CNT)
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return;
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u32IPRSTRegAddr = REG_SYS_AHBIPRST + (4ul * (eIPRstIdx / 32));
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u32IPRSTRegBit = eIPRstIdx % 32;
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/* Enter critical section */
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level = rt_hw_interrupt_disable();
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/* Unlock write-protect */
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SYS_UnlockReg();
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/* Enable IP reset */
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outpw(u32IPRSTRegAddr, inpw(u32IPRSTRegAddr) | (1 << u32IPRSTRegBit));
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/* Disable IP reset */
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outpw(u32IPRSTRegAddr, inpw(u32IPRSTRegAddr) & ~(1 << u32IPRSTRegBit));
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/* Wait it done. */
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while (inpw(u32IPRSTRegAddr) & (1 << u32IPRSTRegBit)) {}
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/* Lock write protect */
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SYS_LockReg();
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/* Leave critical section */
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rt_hw_interrupt_enable(level);
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}
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static void _nu_sys_ipclk(E_SYS_IPCLK eIPClkIdx, uint32_t bEnable)
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{
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uint32_t volatile u32IPCLKRegAddr;
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uint32_t u32IPCLKRegBit;
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rt_uint32_t level;
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if (eIPClkIdx >= SYS_IPCLK_CNT)
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return;
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u32IPCLKRegAddr = REG_CLK_HCLKEN + (4ul * (eIPClkIdx / 32));
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u32IPCLKRegBit = eIPClkIdx % 32;
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/* Enter critical section */
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level = rt_hw_interrupt_disable();
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if (bEnable)
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{
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/* Enable IP CLK */
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outpw(u32IPCLKRegAddr, inpw(u32IPCLKRegAddr) | (1 << u32IPCLKRegBit));
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}
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else
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{
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/* Disable IP CLK */
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outpw(u32IPCLKRegAddr, inpw(u32IPCLKRegAddr) & ~(1 << u32IPCLKRegBit));
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}
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/* Leave critical section */
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rt_hw_interrupt_enable(level);
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}
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void nu_sys_ipclk_enable(E_SYS_IPCLK eIPClkIdx)
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{
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_nu_sys_ipclk(eIPClkIdx, 1);
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}
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void nu_sys_ipclk_disable(E_SYS_IPCLK eIPClkIdx)
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{
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_nu_sys_ipclk(eIPClkIdx, 0);
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}
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E_SYS_USB0_ID nu_sys_usb0_role(void)
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{
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/* Check Role on USB0 dual-role port. */
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/*
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[17] USB0_IDS
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USB0_ID Status
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0 = USB port 0 used as a USB device port.
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1 = USB port 0 used as a USB host port.
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*/
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return ((inpw(REG_SYS_MISCISR) & (1 << 17)) > 0) ? USB0_ID_HOST : USB0_ID_DEVICE;
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}
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#ifdef RT_USING_FINSH
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#include <finsh.h>
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#ifdef FINSH_USING_MSH
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int cmd_reset(int argc, char **argv)
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{
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rt_hw_cpu_reset();
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return 0;
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}
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MSH_CMD_EXPORT_ALIAS(cmd_reset, reset, restart the system);
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int cmd_shutdown(int argc, char **argv)
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{
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rt_hw_cpu_shutdown();
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return 0;
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}
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MSH_CMD_EXPORT_ALIAS(cmd_shutdown, shutdown, shutdown the system);
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int nu_clocks(int argc, char **argv)
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{
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rt_kprintf("SYS_UPLL = %d MHz\n", sysGetClock(SYS_UPLL));
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rt_kprintf("SYS_APLL = %d MHz\n", sysGetClock(SYS_APLL));
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rt_kprintf("SYS_SYSTEM = %d MHz\n", sysGetClock(SYS_SYSTEM));
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rt_kprintf("SYS_HCLK1 = %d MHz\n", sysGetClock(SYS_HCLK1));
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rt_kprintf("SYS_HCLK234 = %d MHz\n", sysGetClock(SYS_HCLK234));
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rt_kprintf("SYS_PCLK = %d MHz\n", sysGetClock(SYS_PCLK));
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rt_kprintf("SYS_CPU = %d MHz\n", sysGetClock(SYS_CPU));
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rt_kprintf("CLK_HCLKEN = %08X\n", inpw(REG_CLK_HCLKEN));
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rt_kprintf("CLK_PCLKEN0 = %08X\n", inpw(REG_CLK_PCLKEN0));
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rt_kprintf("CLK_PCLKEN1 = %08X\n", inpw(REG_CLK_PCLKEN1));
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return 0;
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}
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MSH_CMD_EXPORT(nu_clocks, Get all system clocks);
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#ifdef RT_USING_INTERRUPT_INFO
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int list_interrupt(int argc, char **argv)
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{
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int i;
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for (i = SYS_MIN_INT_SOURCE; i <= SYS_MAX_INT_SOURCE; i++)
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{
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if (irq_desc[i].handler != rt_hw_interrupt_dummy_handler)
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{
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rt_kprintf("[%d] %s: %d\n", i, irq_desc[i].name, irq_desc[i].counter);
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}
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}
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return 0;
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}
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MSH_CMD_EXPORT(list_interrupt, list registered interrupts);
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#endif
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#endif
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#endif
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