278 lines
8.2 KiB
Plaintext
278 lines
8.2 KiB
Plaintext
#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4
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; The first line specifies a preprocessor command that the linker invokes
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; to pass a scatter file through a C preprocessor.
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;*******************************************************************************
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;* \file cy8c6xxa_cm4_dual.sct
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;* \version 2.91
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;*
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;* Linker file for the ARMCC.
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;*
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;* The main purpose of the linker script is to describe how the sections in the
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;* input files should be mapped into the output file, and to control the memory
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;* layout of the output file.
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;*
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;* \note The entry point location is fixed and starts at 0x10000000. The valid
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;* application image should be placed there.
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;*
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;* \note The linker files included with the PDL template projects must be
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;* generic and handle all common use cases. Your project may not use every
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;* section defined in the linker files. In that case you may see the warnings
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;* during the build process: L6314W (no section matches pattern) and/or L6329W
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;* (pattern only matches removed unused sections). In your project, you can
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;* suppress the warning by passing the "--diag_suppress=L6314W,L6329W" option to
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;* the linker, simply comment out or remove the relevant code in the linker
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;* file.
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;*
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;*******************************************************************************
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;* \copyright
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;* Copyright 2016-2021 Cypress Semiconductor Corporation
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;* SPDX-License-Identifier: Apache-2.0
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;*
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;* Licensed under the Apache License, Version 2.0 (the "License");
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;* you may not use this file except in compliance with the License.
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;* You may obtain a copy of the License at
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;*
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;* http://www.apache.org/licenses/LICENSE-2.0
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;*
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;* Unless required by applicable law or agreed to in writing, software
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;* distributed under the License is distributed on an "AS IS" BASIS,
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;* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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;* See the License for the specific language governing permissions and
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;* limitations under the License.
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;******************************************************************************/
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; The defines below describe the location and size of blocks of memory in the target.
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; Use these defines to specify the memory regions available for allocation.
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; The following defines control RAM and flash memory allocation for the CM4 core.
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; You can change the memory allocation by editing RAM and Flash defines.
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; Note that 2 KB of RAM (at the end of the SRAM) are reserved for system use.
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; Using this memory region for other purposes will lead to unexpected behavior.
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; Your changes must be aligned with the corresponding defines for CM0+ core in 'xx_cm0plus.scat',
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; where 'xx' is the device group; for example, 'cy8c6xx7_cm0plus.scat'.
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; RAM
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#define RAM_START 0x08002000
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#define RAM_SIZE 0x000FD800
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; Flash
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#define FLASH_START 0x10000000
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#define FLASH_SIZE 0x00200000
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; The size of the stack section at the end of CM4 SRAM
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#define STACK_SIZE 0x00001000
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; By default, the COMPONENT_CM0P_SLEEP prebuilt image is used for the CM0p core.
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; More about CM0+ prebuilt images, see here:
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; https://github.com/cypresssemiconductorco/psoc6cm0p
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; The size of the Cortex-M0+ application flash image
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#define FLASH_CM0P_SIZE 0x2000
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; The following defines describe a 32K flash region used for EEPROM emulation.
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; This region can also be used as the general purpose flash.
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; You can assign sections to this memory region for only one of the cores.
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; Note some middleware (e.g. BLE, Emulated EEPROM) can place their data into this memory region.
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; Therefore, repurposing this memory region will prevent such middleware from operation.
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#define EM_EEPROM_START 0x14000000
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#define EM_EEPROM_SIZE 0x8000
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; The following defines describe device specific memory regions and must not be changed.
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; Supervisory flash: User data
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#define SFLASH_USER_DATA_START 0x16000800
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#define SFLASH_USER_DATA_SIZE 0x00000800
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; Supervisory flash: Normal Access Restrictions (NAR)
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#define SFLASH_NAR_START 0x16001A00
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#define SFLASH_NAR_SIZE 0x00000200
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; Supervisory flash: Public Key
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#define SFLASH_PUBLIC_KEY_START 0x16005A00
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#define SFLASH_PUBLIC_KEY_SIZE 0x00000C00
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; Supervisory flash: Table of Content # 2
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#define SFLASH_TOC_2_START 0x16007C00
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#define SFLASH_TOC_2_SIZE 0x00000200
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; Supervisory flash: Table of Content # 2 Copy
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#define SFLASH_RTOC_2_START 0x16007E00
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#define SFLASH_RTOC_2_SIZE 0x00000200
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; External memory
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#define XIP_START 0x18000000
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#define XIP_SIZE 0x08000000
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; eFuse
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#define EFUSE_START 0x90700000
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#define EFUSE_SIZE 0x100000
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; Cortex-M0+ application flash image area
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LR_IROM FLASH_START FLASH_CM0P_SIZE
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{
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.cy_m0p_image +0 FLASH_CM0P_SIZE
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{
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* (.cy_m0p_image)
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}
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}
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; Cortex-M4 application flash area
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LR_IROM1 (FLASH_START + FLASH_CM0P_SIZE) (FLASH_SIZE - FLASH_CM0P_SIZE)
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{
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ER_FLASH_VECTORS +0
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{
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* (RESET, +FIRST)
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}
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ER_FLASH_CODE +0 FIXED
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{
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* (InRoot$$Sections)
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* (+RO)
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}
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ER_RAM_VECTORS RAM_START UNINIT
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{
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* (RESET_RAM, +FIRST)
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}
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RW_RAM_DATA +0
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{
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* (.cy_ramfunc)
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* (+RW, +ZI)
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}
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; Place variables in the section that should not be initialized during the
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; device startup.
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RW_IRAM1 +0 UNINIT
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{
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* (.noinit)
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}
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; Application heap area (HEAP)
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ARM_LIB_HEAP +0 EMPTY ((RAM_START+RAM_SIZE)-AlignExpr(ImageLimit(RW_IRAM1), 8)-STACK_SIZE)
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{
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}
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; Stack region growing down
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ARM_LIB_STACK (RAM_START+RAM_SIZE) EMPTY -STACK_SIZE
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{
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}
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; Used for the digital signature of the secure application and the
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; Bootloader SDK application. The size of the section depends on the required
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; data size.
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.cy_app_signature (FLASH_START + FLASH_SIZE - 256) 256
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{
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* (.cy_app_signature)
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}
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}
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; Emulated EEPROM Flash area
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LR_EM_EEPROM EM_EEPROM_START EM_EEPROM_SIZE
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{
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.cy_em_eeprom +0
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{
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* (.cy_em_eeprom)
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}
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}
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; Supervisory flash: User data
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LR_SFLASH_USER_DATA SFLASH_USER_DATA_START SFLASH_USER_DATA_SIZE
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{
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.cy_sflash_user_data +0
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{
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* (.cy_sflash_user_data)
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}
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}
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; Supervisory flash: Normal Access Restrictions (NAR)
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LR_SFLASH_NAR SFLASH_NAR_START SFLASH_NAR_SIZE
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{
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.cy_sflash_nar +0
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{
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* (.cy_sflash_nar)
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}
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}
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; Supervisory flash: Public Key
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LR_SFLASH_PUBLIC_KEY SFLASH_PUBLIC_KEY_START SFLASH_PUBLIC_KEY_SIZE
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{
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.cy_sflash_public_key +0
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{
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* (.cy_sflash_public_key)
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}
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}
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; Supervisory flash: Table of Content # 2
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LR_SFLASH_TOC_2 SFLASH_TOC_2_START SFLASH_TOC_2_SIZE
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{
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.cy_toc_part2 +0
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{
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* (.cy_toc_part2)
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}
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}
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; Supervisory flash: Table of Content # 2 Copy
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LR_SFLASH_RTOC_2 SFLASH_RTOC_2_START SFLASH_RTOC_2_SIZE
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{
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.cy_rtoc_part2 +0
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{
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* (.cy_rtoc_part2)
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}
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}
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; Places the code in the Execute in Place (XIP) section. See the smif driver documentation for details.
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LR_EROM XIP_START XIP_SIZE
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{
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cy_xip +0
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{
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* (.cy_xip)
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}
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}
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; eFuse
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LR_EFUSE EFUSE_START EFUSE_SIZE
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{
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.cy_efuse +0
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{
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* (.cy_efuse)
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}
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}
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; The section is used for additional metadata (silicon revision, Silicon/JTAG ID, etc.) storage.
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CYMETA 0x90500000
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{
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.cymeta +0 { * (.cymeta) }
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}
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/* The following symbols used by the cymcuelftool. */
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/* Flash */
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#define __cy_memory_0_start 0x10000000
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#define __cy_memory_0_length 0x00200000
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#define __cy_memory_0_row_size 0x200
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/* Emulated EEPROM Flash area */
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#define __cy_memory_1_start 0x14000000
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#define __cy_memory_1_length 0x8000
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#define __cy_memory_1_row_size 0x200
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/* Supervisory Flash */
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#define __cy_memory_2_start 0x16000000
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#define __cy_memory_2_length 0x8000
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#define __cy_memory_2_row_size 0x200
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/* XIP */
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#define __cy_memory_3_start 0x18000000
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#define __cy_memory_3_length 0x08000000
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#define __cy_memory_3_row_size 0x200
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/* eFuse */
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#define __cy_memory_4_start 0x90700000
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#define __cy_memory_4_length 0x100000
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#define __cy_memory_4_row_size 1
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/* [] END OF FILE */
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