129 lines
3.4 KiB
C
129 lines
3.4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Copyright (C) 2010-2011 Canonical Ltd <jeremy.kerr@canonical.com>
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* Copyright (C) 2011-2012 Mike Turquette, Linaro Ltd <mturquette@linaro.org>
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*
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* Fixed rate clock implementation
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*/
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#include "ccu.h"
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#include "clk-fixed-rate.h"
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#include <stdlib.h>
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/*
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* DOC: basic fixed-rate clock that cannot gate
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*
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* Traits of this clock:
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* prepare - clk_(un)prepare only ensures parents are prepared
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* enable - clk_enable only ensures parents are enabled
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* rate - rate is always a fixed value. No clk_set_rate support
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* parent - fixed parent. No clk_set_parent support
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*/
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static unsigned long clk_fixed_rate_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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return to_clk_fixed_rate(hw)->fixed_rate;
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}
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static unsigned long clk_fixed_rate_recalc_accuracy(struct clk_hw *hw,
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unsigned long parent_accuracy)
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{
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return to_clk_fixed_rate(hw)->fixed_accuracy;
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}
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const struct clk_ops clk_fixed_rate_ops =
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{
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.recalc_rate = clk_fixed_rate_recalc_rate,
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.recalc_accuracy = clk_fixed_rate_recalc_accuracy,
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};
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/**
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* clk_hw_register_fixed_rate_with_accuracy - register fixed-rate clock with
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* the clock framework
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* @dev: device that is registering this clock
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* @name: name of this clock
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* @parent_name: name of clock's parent
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* @flags: framework-specific flags
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* @fixed_rate: non-adjustable clock rate
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* @fixed_accuracy: non-adjustable clock rate
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*/
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int clk_hw_register_fixed_rate_with_accuracy(
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const char *name, u32 id, const char *parent_name, unsigned long flags,
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unsigned long fixed_rate, unsigned long fixed_accuracy)
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{
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struct clk_fixed_rate *fixed;
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struct clk_hw *hw;
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struct clk_init_data init;
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int ret;
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/* allocate fixed-rate clock */
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fixed = (struct clk_fixed_rate *)malloc(sizeof(*fixed));
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if (!fixed)
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{
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return -1;
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}
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init.name = name;
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init.ops = &clk_fixed_rate_ops;
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init.flags = flags;
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init.parent_names = (parent_name ? &parent_name : NULL);
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init.num_parents = (parent_name ? 1 : 0);
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/* struct clk_fixed_rate assignments */
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fixed->fixed_rate = fixed_rate;
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fixed->fixed_accuracy = fixed_accuracy;
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fixed->hw.init = &init;
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/* register the clock */
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hw = &fixed->hw;
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hw->type = HAL_SUNXI_FIXED_CCU;
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hw->id = id;
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ret = clk_hw_register(hw);
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if (ret)
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{
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free(fixed);
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hw = NULL;
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return -1;
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}
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return 0;
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}
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int clk_register_fixed_rate_with_accuracy(const char *name, u32 id,
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const char *parent_name, unsigned long flags,
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unsigned long fixed_rate, unsigned long fixed_accuracy)
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{
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return clk_hw_register_fixed_rate_with_accuracy(name, id, parent_name,
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flags, fixed_rate, fixed_accuracy);
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}
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int sunxi_fixed_clk_init(void)
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{
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int ret = -1;
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ret = clk_register_fixed_rate_with_accuracy("dcxo24M", CLK_SRC_HOSC24M, NULL, 0, 24000000, 0);
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if (ret)
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{
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printf("register clock dcxo24M error\n");
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}
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ret = clk_register_fixed_rate_with_accuracy("fix_losc", CLK_SRC_LOSC, NULL, 0, 32768, 0);
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if (ret)
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{
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printf("register clock dcxo24M error\n");
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}
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ret = clk_register_fixed_rate_with_accuracy("rc-16m", CLK_SRC_RC_16M, NULL, 0, 16000000, 300000000);
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if (ret)
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{
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printf("register clock dcxo24M error\n");
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}
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ret = clk_register_fixed_rate_with_accuracy("ext-32k", CLK_SRC_EXT_32K, NULL, 0, 32768, 0);
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if (ret)
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{
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printf("register clock dcxo24M error\n");
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}
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return ret;
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}
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