326 lines
16 KiB
C
326 lines
16 KiB
C
//*****************************************************************************
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//
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// am_reg_nvic.h
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//! @file
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//!
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//! @brief Register macros for the NVIC module
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.11 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_REG_NVIC_H
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#define AM_REG_NVIC_H
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//*****************************************************************************
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//
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// Instance finder. (1 instance(s) available)
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//
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//*****************************************************************************
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#define AM_REG_NVIC_NUM_MODULES 1
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#define AM_REG_NVICn(n) \
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(REG_NVIC_BASEADDR + 0x00000000 * n)
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//*****************************************************************************
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//
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// Register offsets.
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//
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//*****************************************************************************
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#define AM_REG_NVIC_ISER0_O 0xE000E100
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#define AM_REG_NVIC_ICER0_O 0xE000E180
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#define AM_REG_NVIC_ISPR0_O 0xE000E200
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#define AM_REG_NVIC_ICPR0_O 0xE000E280
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#define AM_REG_NVIC_IABR0_O 0xE000E300
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#define AM_REG_NVIC_IPR0_O 0xE000E400
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#define AM_REG_NVIC_IPR1_O 0xE000E404
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#define AM_REG_NVIC_IPR2_O 0xE000E408
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#define AM_REG_NVIC_IPR3_O 0xE000E40C
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#define AM_REG_NVIC_IPR4_O 0xE000E410
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#define AM_REG_NVIC_IPR5_O 0xE000E414
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#define AM_REG_NVIC_IPR6_O 0xE000E418
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#define AM_REG_NVIC_IPR7_O 0xE000E41C
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//*****************************************************************************
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//
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// NVIC_ISER0 - Interrupt Set-Enable Register 0
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//
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//*****************************************************************************
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// NVIC_ISERn[31:0] are the set-enable bits for interrupts 31 through 0.
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#define AM_REG_NVIC_ISER0_BITS_S 0
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#define AM_REG_NVIC_ISER0_BITS_M 0xFFFFFFFF
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#define AM_REG_NVIC_ISER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// NVIC_ICER0 - Interrupt Clear-Enable Register 0
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//
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//*****************************************************************************
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// NVIC_ISERn[31:0] are the clear-enable bits for interrupts 31 through 0.
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#define AM_REG_NVIC_ICER0_BITS_S 0
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#define AM_REG_NVIC_ICER0_BITS_M 0xFFFFFFFF
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#define AM_REG_NVIC_ICER0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// NVIC_ISPR0 - Interrupt Set-Pending Register 0
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//
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//*****************************************************************************
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// NVIC_ISERn[31:0] are the set-pending bits for interrupts 31 through 0.
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#define AM_REG_NVIC_ISPR0_BITS_S 0
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#define AM_REG_NVIC_ISPR0_BITS_M 0xFFFFFFFF
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#define AM_REG_NVIC_ISPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// NVIC_ICPR0 - Interrupt Clear-Pending Register 0
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//
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//*****************************************************************************
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// NVIC_ISERn[31:0] are the clear-pending bits for interrupts 31 through 0.
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#define AM_REG_NVIC_ICPR0_BITS_S 0
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#define AM_REG_NVIC_ICPR0_BITS_M 0xFFFFFFFF
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#define AM_REG_NVIC_ICPR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// NVIC_IABR0 - Interrupt Active Bit Register 0
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//
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//*****************************************************************************
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// NVIC_ISERn[31:0] are the interrupt active bits for interrupts 31 through 0.
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#define AM_REG_NVIC_IABR0_BITS_S 0
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#define AM_REG_NVIC_IABR0_BITS_M 0xFFFFFFFF
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#define AM_REG_NVIC_IABR0_BITS(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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//*****************************************************************************
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//
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// NVIC_IPR0 - Interrupt Priority Register 0
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//
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//*****************************************************************************
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// Priority assignment for interrupt vector 3.
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#define AM_REG_NVIC_IPR0_PRI_N3_S 24
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#define AM_REG_NVIC_IPR0_PRI_N3_M 0xFF000000
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#define AM_REG_NVIC_IPR0_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
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// Priority assignment for interrupt vector 2.
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#define AM_REG_NVIC_IPR0_PRI_N2_S 16
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#define AM_REG_NVIC_IPR0_PRI_N2_M 0x00FF0000
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#define AM_REG_NVIC_IPR0_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
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// Priority assignment for interrupt vector 1.
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#define AM_REG_NVIC_IPR0_PRI_N1_S 8
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#define AM_REG_NVIC_IPR0_PRI_N1_M 0x0000FF00
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#define AM_REG_NVIC_IPR0_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
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// Priority assignment for interrupt vector 0.
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#define AM_REG_NVIC_IPR0_PRI_N0_S 0
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#define AM_REG_NVIC_IPR0_PRI_N0_M 0x000000FF
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#define AM_REG_NVIC_IPR0_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// NVIC_IPR1 - Interrupt Priority Register 1
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//
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//*****************************************************************************
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// Priority assignment for interrupt vector 7.
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#define AM_REG_NVIC_IPR1_PRI_N3_S 24
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#define AM_REG_NVIC_IPR1_PRI_N3_M 0xFF000000
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#define AM_REG_NVIC_IPR1_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
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// Priority assignment for interrupt vector 6.
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#define AM_REG_NVIC_IPR1_PRI_N2_S 16
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#define AM_REG_NVIC_IPR1_PRI_N2_M 0x00FF0000
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#define AM_REG_NVIC_IPR1_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
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// Priority assignment for interrupt vector 5.
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#define AM_REG_NVIC_IPR1_PRI_N1_S 8
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#define AM_REG_NVIC_IPR1_PRI_N1_M 0x0000FF00
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#define AM_REG_NVIC_IPR1_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
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// Priority assignment for interrupt vector 4.
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#define AM_REG_NVIC_IPR1_PRI_N0_S 0
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#define AM_REG_NVIC_IPR1_PRI_N0_M 0x000000FF
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#define AM_REG_NVIC_IPR1_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// NVIC_IPR2 - Interrupt Priority Register 2
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//
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//*****************************************************************************
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// Priority assignment for interrupt vector 11.
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#define AM_REG_NVIC_IPR2_PRI_N3_S 24
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#define AM_REG_NVIC_IPR2_PRI_N3_M 0xFF000000
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#define AM_REG_NVIC_IPR2_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
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// Priority assignment for interrupt vector 10.
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#define AM_REG_NVIC_IPR2_PRI_N2_S 16
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#define AM_REG_NVIC_IPR2_PRI_N2_M 0x00FF0000
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#define AM_REG_NVIC_IPR2_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
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// Priority assignment for interrupt vector 9.
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#define AM_REG_NVIC_IPR2_PRI_N1_S 8
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#define AM_REG_NVIC_IPR2_PRI_N1_M 0x0000FF00
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#define AM_REG_NVIC_IPR2_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
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// Priority assignment for interrupt vector 8.
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#define AM_REG_NVIC_IPR2_PRI_N0_S 0
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#define AM_REG_NVIC_IPR2_PRI_N0_M 0x000000FF
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#define AM_REG_NVIC_IPR2_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// NVIC_IPR3 - Interrupt Priority Register 3
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//
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//*****************************************************************************
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// Priority assignment for interrupt vector 15.
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#define AM_REG_NVIC_IPR3_PRI_N3_S 24
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#define AM_REG_NVIC_IPR3_PRI_N3_M 0xFF000000
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#define AM_REG_NVIC_IPR3_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
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// Priority assignment for interrupt vector 14.
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#define AM_REG_NVIC_IPR3_PRI_N2_S 16
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#define AM_REG_NVIC_IPR3_PRI_N2_M 0x00FF0000
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#define AM_REG_NVIC_IPR3_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
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// Priority assignment for interrupt vector 13.
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#define AM_REG_NVIC_IPR3_PRI_N1_S 8
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#define AM_REG_NVIC_IPR3_PRI_N1_M 0x0000FF00
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#define AM_REG_NVIC_IPR3_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
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// Priority assignment for interrupt vector 12.
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#define AM_REG_NVIC_IPR3_PRI_N0_S 0
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#define AM_REG_NVIC_IPR3_PRI_N0_M 0x000000FF
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#define AM_REG_NVIC_IPR3_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// NVIC_IPR4 - Interrupt Priority Register 4
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//
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//*****************************************************************************
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// Priority assignment for interrupt vector 19.
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#define AM_REG_NVIC_IPR4_PRI_N3_S 24
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#define AM_REG_NVIC_IPR4_PRI_N3_M 0xFF000000
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#define AM_REG_NVIC_IPR4_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
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// Priority assignment for interrupt vector 18.
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#define AM_REG_NVIC_IPR4_PRI_N2_S 16
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#define AM_REG_NVIC_IPR4_PRI_N2_M 0x00FF0000
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#define AM_REG_NVIC_IPR4_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
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// Priority assignment for interrupt vector 17.
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#define AM_REG_NVIC_IPR4_PRI_N1_S 8
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#define AM_REG_NVIC_IPR4_PRI_N1_M 0x0000FF00
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#define AM_REG_NVIC_IPR4_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
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// Priority assignment for interrupt vector 16.
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#define AM_REG_NVIC_IPR4_PRI_N0_S 0
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#define AM_REG_NVIC_IPR4_PRI_N0_M 0x000000FF
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#define AM_REG_NVIC_IPR4_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// NVIC_IPR5 - Interrupt Priority Register 5
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//
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//*****************************************************************************
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// Priority assignment for interrupt vector 23.
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#define AM_REG_NVIC_IPR5_PRI_N3_S 24
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#define AM_REG_NVIC_IPR5_PRI_N3_M 0xFF000000
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#define AM_REG_NVIC_IPR5_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
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// Priority assignment for interrupt vector 22.
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#define AM_REG_NVIC_IPR5_PRI_N2_S 16
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#define AM_REG_NVIC_IPR5_PRI_N2_M 0x00FF0000
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#define AM_REG_NVIC_IPR5_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
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// Priority assignment for interrupt vector 21.
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#define AM_REG_NVIC_IPR5_PRI_N1_S 8
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#define AM_REG_NVIC_IPR5_PRI_N1_M 0x0000FF00
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#define AM_REG_NVIC_IPR5_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
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// Priority assignment for interrupt vector 20.
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#define AM_REG_NVIC_IPR5_PRI_N0_S 0
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#define AM_REG_NVIC_IPR5_PRI_N0_M 0x000000FF
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#define AM_REG_NVIC_IPR5_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// NVIC_IPR6 - Interrupt Priority Register 6
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//
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//*****************************************************************************
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// Priority assignment for interrupt vector 27.
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#define AM_REG_NVIC_IPR6_PRI_N3_S 24
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#define AM_REG_NVIC_IPR6_PRI_N3_M 0xFF000000
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#define AM_REG_NVIC_IPR6_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
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// Priority assignment for interrupt vector 26.
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#define AM_REG_NVIC_IPR6_PRI_N2_S 16
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#define AM_REG_NVIC_IPR6_PRI_N2_M 0x00FF0000
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#define AM_REG_NVIC_IPR6_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
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// Priority assignment for interrupt vector 25.
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#define AM_REG_NVIC_IPR6_PRI_N1_S 8
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#define AM_REG_NVIC_IPR6_PRI_N1_M 0x0000FF00
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#define AM_REG_NVIC_IPR6_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
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// Priority assignment for interrupt vector 24.
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#define AM_REG_NVIC_IPR6_PRI_N0_S 0
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#define AM_REG_NVIC_IPR6_PRI_N0_M 0x000000FF
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#define AM_REG_NVIC_IPR6_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
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//*****************************************************************************
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//
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// NVIC_IPR7 - Interrupt Priority Register 7
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//
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//*****************************************************************************
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// Priority assignment for interrupt vector 31.
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#define AM_REG_NVIC_IPR7_PRI_N3_S 24
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#define AM_REG_NVIC_IPR7_PRI_N3_M 0xFF000000
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#define AM_REG_NVIC_IPR7_PRI_N3(n) (((uint32_t)(n) << 24) & 0xFF000000)
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// Priority assignment for interrupt vector 30.
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#define AM_REG_NVIC_IPR7_PRI_N2_S 16
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#define AM_REG_NVIC_IPR7_PRI_N2_M 0x00FF0000
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#define AM_REG_NVIC_IPR7_PRI_N2(n) (((uint32_t)(n) << 16) & 0x00FF0000)
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// Priority assignment for interrupt vector 29.
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#define AM_REG_NVIC_IPR7_PRI_N1_S 8
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#define AM_REG_NVIC_IPR7_PRI_N1_M 0x0000FF00
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#define AM_REG_NVIC_IPR7_PRI_N1(n) (((uint32_t)(n) << 8) & 0x0000FF00)
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// Priority assignment for interrupt vector 28.
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#define AM_REG_NVIC_IPR7_PRI_N0_S 0
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#define AM_REG_NVIC_IPR7_PRI_N0_M 0x000000FF
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#define AM_REG_NVIC_IPR7_PRI_N0(n) (((uint32_t)(n) << 0) & 0x000000FF)
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#endif // AM_REG_NVIC_H
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