2675 lines
87 KiB
C
2675 lines
87 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2018 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_edma.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.edma"
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#endif
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#define EDMA_TRANSFER_ENABLED_MASK 0x80U
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get instance number for EDMA.
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*
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* @param base EDMA peripheral base address.
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*/
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static uint32_t EDMA_GetInstance(DMA_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Array to map EDMA instance number to base pointer. */
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static DMA_Type *const s_edmaBases[] = DMA_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Array to map EDMA instance number to clock name. */
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static const clock_ip_name_t s_edmaClockName[] = EDMA_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*! @brief Array to map EDMA instance number to IRQ number. */
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static const IRQn_Type s_edmaIRQNumber[][FSL_FEATURE_EDMA_MODULE_CHANNEL] = DMA_CHN_IRQS;
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/*! @brief Pointers to transfer handle for each EDMA channel. */
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static edma_handle_t *s_EDMAHandle[FSL_FEATURE_EDMA_MODULE_CHANNEL * FSL_FEATURE_SOC_EDMA_COUNT];
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/*******************************************************************************
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* Code
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******************************************************************************/
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static uint32_t EDMA_GetInstance(DMA_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_edmaBases); instance++)
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{
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if (s_edmaBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_edmaBases));
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return instance;
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}
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/*!
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* brief Push content of TCD structure into hardware TCD register.
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*
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* param base EDMA peripheral base address.
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* param channel EDMA channel number.
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* param tcd Point to TCD structure.
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*/
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void EDMA_InstallTCD(DMA_Type *base, uint32_t channel, edma_tcd_t *tcd)
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{
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assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
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assert(tcd != NULL);
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assert(((uint32_t)tcd & 0x1FU) == 0);
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/* Push tcd into hardware TCD register */
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base->TCD[channel].SADDR = tcd->SADDR;
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base->TCD[channel].SOFF = tcd->SOFF;
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base->TCD[channel].ATTR = tcd->ATTR;
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base->TCD[channel].NBYTES_MLNO = tcd->NBYTES;
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base->TCD[channel].SLAST = tcd->SLAST;
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base->TCD[channel].DADDR = tcd->DADDR;
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base->TCD[channel].DOFF = tcd->DOFF;
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base->TCD[channel].CITER_ELINKNO = tcd->CITER;
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base->TCD[channel].DLAST_SGA = tcd->DLAST_SGA;
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/* Clear DONE bit first, otherwise ESG cannot be set */
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base->TCD[channel].CSR = 0;
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base->TCD[channel].CSR = tcd->CSR;
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base->TCD[channel].BITER_ELINKNO = tcd->BITER;
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}
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/*!
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* brief Initializes the eDMA peripheral.
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*
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* This function ungates the eDMA clock and configures the eDMA peripheral according
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* to the configuration structure.
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*
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* param base eDMA peripheral base address.
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* param config A pointer to the configuration structure, see "edma_config_t".
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* note This function enables the minor loop map feature.
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*/
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void EDMA_Init(DMA_Type *base, const edma_config_t *config)
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{
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assert(config != NULL);
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uint32_t tmpreg;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate EDMA peripheral clock */
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CLOCK_EnableClock(s_edmaClockName[EDMA_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* clear all the enabled request, status to make sure EDMA status is in normal condition */
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base->ERQ = 0U;
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base->INT = 0xFFFFFFFFU;
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base->ERR = 0xFFFFFFFFU;
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/* Configure EDMA peripheral according to the configuration structure. */
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tmpreg = base->CR;
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tmpreg &= ~(DMA_CR_ERCA_MASK | DMA_CR_HOE_MASK | DMA_CR_CLM_MASK | DMA_CR_EDBG_MASK);
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tmpreg |= (DMA_CR_ERCA(config->enableRoundRobinArbitration) | DMA_CR_HOE(config->enableHaltOnError) |
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DMA_CR_CLM(config->enableContinuousLinkMode) | DMA_CR_EDBG(config->enableDebugMode) | DMA_CR_EMLM(true));
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base->CR = tmpreg;
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}
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/*!
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* brief Deinitializes the eDMA peripheral.
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*
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* This function gates the eDMA clock.
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*
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* param base eDMA peripheral base address.
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*/
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void EDMA_Deinit(DMA_Type *base)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Gate EDMA peripheral clock */
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CLOCK_DisableClock(s_edmaClockName[EDMA_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Gets the eDMA default configuration structure.
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*
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* This function sets the configuration structure to default values.
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* The default configuration is set to the following values.
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* code
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* config.enableContinuousLinkMode = false;
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* config.enableHaltOnError = true;
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* config.enableRoundRobinArbitration = false;
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* config.enableDebugMode = false;
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* endcode
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*
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* param config A pointer to the eDMA configuration structure.
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*/
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void EDMA_GetDefaultConfig(edma_config_t *config)
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{
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assert(config != NULL);
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/* Initializes the configure structure to zero. */
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memset(config, 0, sizeof(*config));
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config->enableRoundRobinArbitration = false;
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config->enableHaltOnError = true;
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config->enableContinuousLinkMode = false;
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config->enableDebugMode = false;
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}
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/*!
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* brief Sets all TCD registers to default values.
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*
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* This function sets TCD registers for this channel to default values.
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*
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* param base eDMA peripheral base address.
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* param channel eDMA channel number.
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* note This function must not be called while the channel transfer is ongoing
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* or it causes unpredictable results.
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* note This function enables the auto stop request feature.
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*/
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void EDMA_ResetChannel(DMA_Type *base, uint32_t channel)
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{
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assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
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EDMA_TcdReset((edma_tcd_t *)&base->TCD[channel]);
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}
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/*!
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* brief Configures the eDMA transfer attribute.
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*
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* This function configures the transfer attribute, including source address, destination address,
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* transfer size, address offset, and so on. It also configures the scatter gather feature if the
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* user supplies the TCD address.
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* Example:
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* code
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* edma_transfer_t config;
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* edma_tcd_t tcd;
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* config.srcAddr = ..;
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* config.destAddr = ..;
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* ...
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* EDMA_SetTransferConfig(DMA0, channel, &config, &stcd);
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* endcode
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*
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* param base eDMA peripheral base address.
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* param channel eDMA channel number.
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* param config Pointer to eDMA transfer configuration structure.
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* param nextTcd Point to TCD structure. It can be NULL if users
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* do not want to enable scatter/gather feature.
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* note If nextTcd is not NULL, it means scatter gather feature is enabled
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* and DREQ bit is cleared in the previous transfer configuration, which
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* is set in the eDMA_ResetChannel.
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*/
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void EDMA_SetTransferConfig(DMA_Type *base, uint32_t channel, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
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{
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assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
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assert(config != NULL);
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assert(((uint32_t)nextTcd & 0x1FU) == 0);
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EDMA_TcdSetTransferConfig((edma_tcd_t *)&base->TCD[channel], config, nextTcd);
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}
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/*!
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* brief Configures the eDMA minor offset feature.
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*
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* The minor offset means that the signed-extended value is added to the source address or destination
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* address after each minor loop.
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*
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* param base eDMA peripheral base address.
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* param channel eDMA channel number.
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* param config A pointer to the minor offset configuration structure.
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*/
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void EDMA_SetMinorOffsetConfig(DMA_Type *base, uint32_t channel, const edma_minor_offset_config_t *config)
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{
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assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
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assert(config != NULL);
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uint32_t tmpreg;
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tmpreg = base->TCD[channel].NBYTES_MLOFFYES;
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tmpreg &= ~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
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tmpreg |=
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(DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
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DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
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base->TCD[channel].NBYTES_MLOFFYES = tmpreg;
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}
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/*!
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* brief Sets the channel link for the eDMA transfer.
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*
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* This function configures either the minor link or the major link mode. The minor link means that the channel link is
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* triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
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* exhausted.
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*
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* param base eDMA peripheral base address.
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* param channel eDMA channel number.
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* param type A channel link type, which can be one of the following:
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* arg kEDMA_LinkNone
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* arg kEDMA_MinorLink
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* arg kEDMA_MajorLink
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* param linkedChannel The linked channel number.
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* note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
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*/
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void EDMA_SetChannelLink(DMA_Type *base, uint32_t channel, edma_channel_link_type_t type, uint32_t linkedChannel)
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{
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assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
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assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
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EDMA_TcdSetChannelLink((edma_tcd_t *)&base->TCD[channel], type, linkedChannel);
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}
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/*!
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* brief Sets the bandwidth for the eDMA transfer.
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*
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* Because the eDMA processes the minor loop, it continuously generates read/write sequences
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* until the minor count is exhausted. The bandwidth forces the eDMA to stall after the completion of
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* each read/write access to control the bus request bandwidth seen by the crossbar switch.
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*
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* param base eDMA peripheral base address.
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* param channel eDMA channel number.
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* param bandWidth A bandwidth setting, which can be one of the following:
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* arg kEDMABandwidthStallNone
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* arg kEDMABandwidthStall4Cycle
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* arg kEDMABandwidthStall8Cycle
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*/
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void EDMA_SetBandWidth(DMA_Type *base, uint32_t channel, edma_bandwidth_t bandWidth)
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{
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assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
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base->TCD[channel].CSR = (base->TCD[channel].CSR & (~DMA_CSR_BWC_MASK)) | DMA_CSR_BWC(bandWidth);
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}
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/*!
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* brief Sets the source modulo and the destination modulo for the eDMA transfer.
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*
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* This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
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* calculation is performed or the original register value. It provides the ability to implement a circular data
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* queue easily.
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*
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* param base eDMA peripheral base address.
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* param channel eDMA channel number.
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* param srcModulo A source modulo value.
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* param destModulo A destination modulo value.
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*/
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void EDMA_SetModulo(DMA_Type *base, uint32_t channel, edma_modulo_t srcModulo, edma_modulo_t destModulo)
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{
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assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
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uint32_t tmpreg;
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tmpreg = base->TCD[channel].ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
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base->TCD[channel].ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
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}
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/*!
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* brief Enables the interrupt source for the eDMA transfer.
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*
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* param base eDMA peripheral base address.
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* param channel eDMA channel number.
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* param mask The mask of interrupt source to be set. Users need to use
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* the defined edma_interrupt_enable_t type.
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*/
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void EDMA_EnableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
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{
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assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
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/* Enable error interrupt */
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if (mask & kEDMA_ErrorInterruptEnable)
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{
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base->EEI |= (0x1U << channel);
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}
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/* Enable Major interrupt */
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if (mask & kEDMA_MajorInterruptEnable)
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{
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base->TCD[channel].CSR |= DMA_CSR_INTMAJOR_MASK;
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}
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/* Enable Half major interrupt */
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if (mask & kEDMA_HalfInterruptEnable)
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{
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base->TCD[channel].CSR |= DMA_CSR_INTHALF_MASK;
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}
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}
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/*!
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* brief Disables the interrupt source for the eDMA transfer.
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*
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* param base eDMA peripheral base address.
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* param channel eDMA channel number.
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* param mask The mask of the interrupt source to be set. Use
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* the defined edma_interrupt_enable_t type.
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*/
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void EDMA_DisableChannelInterrupts(DMA_Type *base, uint32_t channel, uint32_t mask)
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{
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assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
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/* Disable error interrupt */
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if (mask & kEDMA_ErrorInterruptEnable)
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{
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base->EEI &= ~(0x1U << channel);
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}
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/* Disable Major interrupt */
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if (mask & kEDMA_MajorInterruptEnable)
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{
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base->TCD[channel].CSR &= ~DMA_CSR_INTMAJOR_MASK;
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}
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/* Disable Half major interrupt */
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if (mask & kEDMA_HalfInterruptEnable)
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{
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base->TCD[channel].CSR &= ~DMA_CSR_INTHALF_MASK;
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}
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}
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/*!
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* brief Sets all fields to default values for the TCD structure.
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*
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* This function sets all fields for this TCD structure to default value.
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*
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* param tcd Pointer to the TCD structure.
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* note This function enables the auto stop request feature.
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*/
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void EDMA_TcdReset(edma_tcd_t *tcd)
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{
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assert(tcd != NULL);
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assert(((uint32_t)tcd & 0x1FU) == 0);
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/* Reset channel TCD */
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tcd->SADDR = 0U;
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tcd->SOFF = 0U;
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tcd->ATTR = 0U;
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tcd->NBYTES = 0U;
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tcd->SLAST = 0U;
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tcd->DADDR = 0U;
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tcd->DOFF = 0U;
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tcd->CITER = 0U;
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tcd->DLAST_SGA = 0U;
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/* Enable auto disable request feature */
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tcd->CSR = DMA_CSR_DREQ(true);
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tcd->BITER = 0U;
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}
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/*!
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* brief Configures the eDMA TCD transfer attribute.
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*
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* The TCD is a transfer control descriptor. The content of the TCD is the same as the hardware TCD registers.
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* The STCD is used in the scatter-gather mode.
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* This function configures the TCD transfer attribute, including source address, destination address,
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* transfer size, address offset, and so on. It also configures the scatter gather feature if the
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* user supplies the next TCD address.
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* Example:
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* code
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* edma_transfer_t config = {
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* ...
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* }
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* edma_tcd_t tcd __aligned(32);
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* edma_tcd_t nextTcd __aligned(32);
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* EDMA_TcdSetTransferConfig(&tcd, &config, &nextTcd);
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* endcode
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*
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* param tcd Pointer to the TCD structure.
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* param config Pointer to eDMA transfer configuration structure.
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* param nextTcd Pointer to the next TCD structure. It can be NULL if users
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* do not want to enable scatter/gather feature.
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* note TCD address should be 32 bytes aligned or it causes an eDMA error.
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* note If the nextTcd is not NULL, the scatter gather feature is enabled
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* and DREQ bit is cleared in the previous transfer configuration, which
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* is set in the EDMA_TcdReset.
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*/
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void EDMA_TcdSetTransferConfig(edma_tcd_t *tcd, const edma_transfer_config_t *config, edma_tcd_t *nextTcd)
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{
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assert(tcd != NULL);
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assert(((uint32_t)tcd & 0x1FU) == 0);
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assert(config != NULL);
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assert(((uint32_t)nextTcd & 0x1FU) == 0);
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/* source address */
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tcd->SADDR = config->srcAddr;
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/* destination address */
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tcd->DADDR = config->destAddr;
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/* Source data and destination data transfer size */
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tcd->ATTR = DMA_ATTR_SSIZE(config->srcTransferSize) | DMA_ATTR_DSIZE(config->destTransferSize);
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/* Source address signed offset */
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tcd->SOFF = config->srcOffset;
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/* Destination address signed offset */
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tcd->DOFF = config->destOffset;
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/* Minor byte transfer count */
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tcd->NBYTES = config->minorLoopBytes;
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/* Current major iteration count */
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tcd->CITER = config->majorLoopCounts;
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/* Starting major iteration count */
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tcd->BITER = config->majorLoopCounts;
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/* Enable scatter/gather processing */
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if (nextTcd != NULL)
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{
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tcd->DLAST_SGA = (uint32_t)nextTcd;
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/*
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Before call EDMA_TcdSetTransferConfig or EDMA_SetTransferConfig,
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user must call EDMA_TcdReset or EDMA_ResetChannel which will set
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DREQ, so must use "|" or "&" rather than "=".
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Clear the DREQ bit because scatter gather has been enabled, so the
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previous transfer is not the last transfer, and channel request should
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be enabled at the next transfer(the next TCD).
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*/
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|
tcd->CSR = (tcd->CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Configures the eDMA TCD minor offset feature.
|
|
*
|
|
* A minor offset is a signed-extended value added to the source address or a destination
|
|
* address after each minor loop.
|
|
*
|
|
* param tcd A point to the TCD structure.
|
|
* param config A pointer to the minor offset configuration structure.
|
|
*/
|
|
void EDMA_TcdSetMinorOffsetConfig(edma_tcd_t *tcd, const edma_minor_offset_config_t *config)
|
|
{
|
|
assert(tcd != NULL);
|
|
assert(((uint32_t)tcd & 0x1FU) == 0);
|
|
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = tcd->NBYTES &
|
|
~(DMA_NBYTES_MLOFFYES_SMLOE_MASK | DMA_NBYTES_MLOFFYES_DMLOE_MASK | DMA_NBYTES_MLOFFYES_MLOFF_MASK);
|
|
tmpreg |=
|
|
(DMA_NBYTES_MLOFFYES_SMLOE(config->enableSrcMinorOffset) |
|
|
DMA_NBYTES_MLOFFYES_DMLOE(config->enableDestMinorOffset) | DMA_NBYTES_MLOFFYES_MLOFF(config->minorOffset));
|
|
tcd->NBYTES = tmpreg;
|
|
}
|
|
|
|
/*!
|
|
* brief Sets the channel link for the eDMA TCD.
|
|
*
|
|
* This function configures either a minor link or a major link. The minor link means the channel link is
|
|
* triggered every time CITER decreases by 1. The major link means that the channel link is triggered when the CITER is
|
|
* exhausted.
|
|
*
|
|
* note Users should ensure that DONE flag is cleared before calling this interface, or the configuration is invalid.
|
|
* param tcd Point to the TCD structure.
|
|
* param type Channel link type, it can be one of:
|
|
* arg kEDMA_LinkNone
|
|
* arg kEDMA_MinorLink
|
|
* arg kEDMA_MajorLink
|
|
* param linkedChannel The linked channel number.
|
|
*/
|
|
void EDMA_TcdSetChannelLink(edma_tcd_t *tcd, edma_channel_link_type_t type, uint32_t linkedChannel)
|
|
{
|
|
assert(tcd != NULL);
|
|
assert(((uint32_t)tcd & 0x1FU) == 0);
|
|
assert(linkedChannel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
|
|
|
|
if (type == kEDMA_MinorLink) /* Minor link config */
|
|
{
|
|
uint32_t tmpreg;
|
|
|
|
/* Enable minor link */
|
|
tcd->CITER |= DMA_CITER_ELINKYES_ELINK_MASK;
|
|
tcd->BITER |= DMA_BITER_ELINKYES_ELINK_MASK;
|
|
/* Set linked channel */
|
|
tmpreg = tcd->CITER & (~DMA_CITER_ELINKYES_LINKCH_MASK);
|
|
tmpreg |= DMA_CITER_ELINKYES_LINKCH(linkedChannel);
|
|
tcd->CITER = tmpreg;
|
|
tmpreg = tcd->BITER & (~DMA_BITER_ELINKYES_LINKCH_MASK);
|
|
tmpreg |= DMA_BITER_ELINKYES_LINKCH(linkedChannel);
|
|
tcd->BITER = tmpreg;
|
|
}
|
|
else if (type == kEDMA_MajorLink) /* Major link config */
|
|
{
|
|
uint32_t tmpreg;
|
|
|
|
/* Enable major link */
|
|
tcd->CSR |= DMA_CSR_MAJORELINK_MASK;
|
|
/* Set major linked channel */
|
|
tmpreg = tcd->CSR & (~DMA_CSR_MAJORLINKCH_MASK);
|
|
tcd->CSR = tmpreg | DMA_CSR_MAJORLINKCH(linkedChannel);
|
|
}
|
|
else /* Link none */
|
|
{
|
|
tcd->CITER &= ~DMA_CITER_ELINKYES_ELINK_MASK;
|
|
tcd->BITER &= ~DMA_BITER_ELINKYES_ELINK_MASK;
|
|
tcd->CSR &= ~DMA_CSR_MAJORELINK_MASK;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Sets the source modulo and the destination modulo for the eDMA TCD.
|
|
*
|
|
* This function defines a specific address range specified to be the value after (SADDR + SOFF)/(DADDR + DOFF)
|
|
* calculation is performed or the original register value. It provides the ability to implement a circular data
|
|
* queue easily.
|
|
*
|
|
* param tcd A pointer to the TCD structure.
|
|
* param srcModulo A source modulo value.
|
|
* param destModulo A destination modulo value.
|
|
*/
|
|
void EDMA_TcdSetModulo(edma_tcd_t *tcd, edma_modulo_t srcModulo, edma_modulo_t destModulo)
|
|
{
|
|
assert(tcd != NULL);
|
|
assert(((uint32_t)tcd & 0x1FU) == 0);
|
|
|
|
uint32_t tmpreg;
|
|
|
|
tmpreg = tcd->ATTR & (~(DMA_ATTR_SMOD_MASK | DMA_ATTR_DMOD_MASK));
|
|
tcd->ATTR = tmpreg | DMA_ATTR_DMOD(destModulo) | DMA_ATTR_SMOD(srcModulo);
|
|
}
|
|
|
|
/*!
|
|
* brief Enables the interrupt source for the eDMA TCD.
|
|
*
|
|
* param tcd Point to the TCD structure.
|
|
* param mask The mask of interrupt source to be set. Users need to use
|
|
* the defined edma_interrupt_enable_t type.
|
|
*/
|
|
void EDMA_TcdEnableInterrupts(edma_tcd_t *tcd, uint32_t mask)
|
|
{
|
|
assert(tcd != NULL);
|
|
|
|
/* Enable Major interrupt */
|
|
if (mask & kEDMA_MajorInterruptEnable)
|
|
{
|
|
tcd->CSR |= DMA_CSR_INTMAJOR_MASK;
|
|
}
|
|
|
|
/* Enable Half major interrupt */
|
|
if (mask & kEDMA_HalfInterruptEnable)
|
|
{
|
|
tcd->CSR |= DMA_CSR_INTHALF_MASK;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Disables the interrupt source for the eDMA TCD.
|
|
*
|
|
* param tcd Point to the TCD structure.
|
|
* param mask The mask of interrupt source to be set. Users need to use
|
|
* the defined edma_interrupt_enable_t type.
|
|
*/
|
|
void EDMA_TcdDisableInterrupts(edma_tcd_t *tcd, uint32_t mask)
|
|
{
|
|
assert(tcd != NULL);
|
|
|
|
/* Disable Major interrupt */
|
|
if (mask & kEDMA_MajorInterruptEnable)
|
|
{
|
|
tcd->CSR &= ~DMA_CSR_INTMAJOR_MASK;
|
|
}
|
|
|
|
/* Disable Half major interrupt */
|
|
if (mask & kEDMA_HalfInterruptEnable)
|
|
{
|
|
tcd->CSR &= ~DMA_CSR_INTHALF_MASK;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Gets the remaining major loop count from the eDMA current channel TCD.
|
|
*
|
|
* This function checks the TCD (Task Control Descriptor) status for a specified
|
|
* eDMA channel and returns the number of major loop count that has not finished.
|
|
*
|
|
* param base eDMA peripheral base address.
|
|
* param channel eDMA channel number.
|
|
* return Major loop count which has not been transferred yet for the current TCD.
|
|
* note 1. This function can only be used to get unfinished major loop count of transfer without
|
|
* the next TCD, or it might be inaccuracy.
|
|
* 2. The unfinished/remaining transfer bytes cannot be obtained directly from registers while
|
|
* the channel is running.
|
|
* Because to calculate the remaining bytes, the initial NBYTES configured in DMA_TCDn_NBYTES_MLNO
|
|
* register is needed while the eDMA IP does not support getting it while a channel is active.
|
|
* In another word, the NBYTES value reading is always the actual (decrementing) NBYTES value the dma_engine
|
|
* is working with while a channel is running.
|
|
* Consequently, to get the remaining transfer bytes, a software-saved initial value of NBYTES (for example
|
|
* copied before enabling the channel) is needed. The formula to calculate it is shown below:
|
|
* RemainingBytes = RemainingMajorLoopCount * NBYTES(initially configured)
|
|
*/
|
|
uint32_t EDMA_GetRemainingMajorLoopCount(DMA_Type *base, uint32_t channel)
|
|
{
|
|
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
|
|
|
|
uint32_t remainingCount = 0;
|
|
|
|
if (DMA_CSR_DONE_MASK & base->TCD[channel].CSR)
|
|
{
|
|
remainingCount = 0;
|
|
}
|
|
else
|
|
{
|
|
/* Calculate the unfinished bytes */
|
|
if (base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_ELINK_MASK)
|
|
{
|
|
remainingCount =
|
|
(base->TCD[channel].CITER_ELINKYES & DMA_CITER_ELINKYES_CITER_MASK) >> DMA_CITER_ELINKYES_CITER_SHIFT;
|
|
}
|
|
else
|
|
{
|
|
remainingCount =
|
|
(base->TCD[channel].CITER_ELINKNO & DMA_CITER_ELINKNO_CITER_MASK) >> DMA_CITER_ELINKNO_CITER_SHIFT;
|
|
}
|
|
}
|
|
|
|
return remainingCount;
|
|
}
|
|
|
|
/*!
|
|
* brief Gets the eDMA channel status flags.
|
|
*
|
|
* param base eDMA peripheral base address.
|
|
* param channel eDMA channel number.
|
|
* return The mask of channel status flags. Users need to use the
|
|
* _edma_channel_status_flags type to decode the return variables.
|
|
*/
|
|
uint32_t EDMA_GetChannelStatusFlags(DMA_Type *base, uint32_t channel)
|
|
{
|
|
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
|
|
|
|
uint32_t retval = 0;
|
|
|
|
/* Get DONE bit flag */
|
|
retval |= ((base->TCD[channel].CSR & DMA_CSR_DONE_MASK) >> DMA_CSR_DONE_SHIFT);
|
|
/* Get ERROR bit flag */
|
|
retval |= (((base->ERR >> channel) & 0x1U) << 1U);
|
|
/* Get INT bit flag */
|
|
retval |= (((base->INT >> channel) & 0x1U) << 2U);
|
|
|
|
return retval;
|
|
}
|
|
|
|
/*!
|
|
* brief Clears the eDMA channel status flags.
|
|
*
|
|
* param base eDMA peripheral base address.
|
|
* param channel eDMA channel number.
|
|
* param mask The mask of channel status to be cleared. Users need to use
|
|
* the defined _edma_channel_status_flags type.
|
|
*/
|
|
void EDMA_ClearChannelStatusFlags(DMA_Type *base, uint32_t channel, uint32_t mask)
|
|
{
|
|
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
|
|
|
|
/* Clear DONE bit flag */
|
|
if (mask & kEDMA_DoneFlag)
|
|
{
|
|
base->CDNE = channel;
|
|
}
|
|
/* Clear ERROR bit flag */
|
|
if (mask & kEDMA_ErrorFlag)
|
|
{
|
|
base->CERR = channel;
|
|
}
|
|
/* Clear INT bit flag */
|
|
if (mask & kEDMA_InterruptFlag)
|
|
{
|
|
base->CINT = channel;
|
|
}
|
|
}
|
|
|
|
static uint8_t Get_StartInstance(void)
|
|
{
|
|
static uint8_t StartInstanceNum;
|
|
|
|
#if defined(DMA0)
|
|
StartInstanceNum = EDMA_GetInstance(DMA0);
|
|
#elif defined(DMA1)
|
|
StartInstanceNum = EDMA_GetInstance(DMA1);
|
|
#elif defined(DMA2)
|
|
StartInstanceNum = EDMA_GetInstance(DMA2);
|
|
#elif defined(DMA3)
|
|
StartInstanceNum = EDMA_GetInstance(DMA3);
|
|
#endif
|
|
|
|
return StartInstanceNum;
|
|
}
|
|
|
|
/*!
|
|
* brief Creates the eDMA handle.
|
|
*
|
|
* This function is called if using the transactional API for eDMA. This function
|
|
* initializes the internal state of the eDMA handle.
|
|
*
|
|
* param handle eDMA handle pointer. The eDMA handle stores callback function and
|
|
* parameters.
|
|
* param base eDMA peripheral base address.
|
|
* param channel eDMA channel number.
|
|
*/
|
|
void EDMA_CreateHandle(edma_handle_t *handle, DMA_Type *base, uint32_t channel)
|
|
{
|
|
assert(handle != NULL);
|
|
assert(channel < FSL_FEATURE_EDMA_MODULE_CHANNEL);
|
|
|
|
uint32_t edmaInstance;
|
|
uint32_t channelIndex;
|
|
uint8_t StartInstance;
|
|
edma_tcd_t *tcdRegs;
|
|
|
|
/* Zero the handle */
|
|
memset(handle, 0, sizeof(*handle));
|
|
|
|
handle->base = base;
|
|
handle->channel = channel;
|
|
/* Get the DMA instance number */
|
|
edmaInstance = EDMA_GetInstance(base);
|
|
StartInstance = Get_StartInstance();
|
|
channelIndex = ((edmaInstance - StartInstance) * FSL_FEATURE_EDMA_MODULE_CHANNEL) + channel;
|
|
s_EDMAHandle[channelIndex] = handle;
|
|
|
|
/* Enable NVIC interrupt */
|
|
EnableIRQ(s_edmaIRQNumber[edmaInstance][channel]);
|
|
|
|
/*
|
|
Reset TCD registers to zero. Unlike the EDMA_TcdReset(DREQ will be set),
|
|
CSR will be 0. Because in order to suit EDMA busy check mechanism in
|
|
EDMA_SubmitTransfer, CSR must be set 0.
|
|
*/
|
|
tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
|
|
tcdRegs->SADDR = 0;
|
|
tcdRegs->SOFF = 0;
|
|
tcdRegs->ATTR = 0;
|
|
tcdRegs->NBYTES = 0;
|
|
tcdRegs->SLAST = 0;
|
|
tcdRegs->DADDR = 0;
|
|
tcdRegs->DOFF = 0;
|
|
tcdRegs->CITER = 0;
|
|
tcdRegs->DLAST_SGA = 0;
|
|
tcdRegs->CSR = 0;
|
|
tcdRegs->BITER = 0;
|
|
}
|
|
|
|
/*!
|
|
* brief Installs the TCDs memory pool into the eDMA handle.
|
|
*
|
|
* This function is called after the EDMA_CreateHandle to use scatter/gather feature. This function shall only be used
|
|
* while users need to use scatter gather mode. Scatter gather mode enables EDMA to load a new transfer control block
|
|
* (tcd) in hardware, and automatically reconfigure that DMA channel for a new transfer.
|
|
* Users need to prepare tcd memory and also configure tcds using interface EDMA_SubmitTransfer.
|
|
*
|
|
* param handle eDMA handle pointer.
|
|
* param tcdPool A memory pool to store TCDs. It must be 32 bytes aligned.
|
|
* param tcdSize The number of TCD slots.
|
|
*/
|
|
void EDMA_InstallTCDMemory(edma_handle_t *handle, edma_tcd_t *tcdPool, uint32_t tcdSize)
|
|
{
|
|
assert(handle != NULL);
|
|
assert(((uint32_t)tcdPool & 0x1FU) == 0);
|
|
|
|
/* Initialize tcd queue attribute. */
|
|
handle->header = 0;
|
|
handle->tail = 0;
|
|
handle->tcdUsed = 0;
|
|
handle->tcdSize = tcdSize;
|
|
handle->flags = 0;
|
|
handle->tcdPool = tcdPool;
|
|
}
|
|
|
|
/*!
|
|
* brief Installs a callback function for the eDMA transfer.
|
|
*
|
|
* This callback is called in the eDMA IRQ handler. Use the callback to do something after
|
|
* the current major loop transfer completes. This function will be called every time one tcd finished transfer.
|
|
*
|
|
* param handle eDMA handle pointer.
|
|
* param callback eDMA callback function pointer.
|
|
* param userData A parameter for the callback function.
|
|
*/
|
|
void EDMA_SetCallback(edma_handle_t *handle, edma_callback callback, void *userData)
|
|
{
|
|
assert(handle != NULL);
|
|
|
|
handle->callback = callback;
|
|
handle->userData = userData;
|
|
}
|
|
|
|
/*!
|
|
* brief Prepares the eDMA transfer structure.
|
|
*
|
|
* This function prepares the transfer configuration structure according to the user input.
|
|
*
|
|
* param config The user configuration structure of type edma_transfer_t.
|
|
* param srcAddr eDMA transfer source address.
|
|
* param srcWidth eDMA transfer source address width(bytes).
|
|
* param destAddr eDMA transfer destination address.
|
|
* param destWidth eDMA transfer destination address width(bytes).
|
|
* param bytesEachRequest eDMA transfer bytes per channel request.
|
|
* param transferBytes eDMA transfer bytes to be transferred.
|
|
* param type eDMA transfer type.
|
|
* note The data address and the data width must be consistent. For example, if the SRC
|
|
* is 4 bytes, the source address must be 4 bytes aligned, or it results in
|
|
* source address error (SAE).
|
|
*/
|
|
void EDMA_PrepareTransfer(edma_transfer_config_t *config,
|
|
void *srcAddr,
|
|
uint32_t srcWidth,
|
|
void *destAddr,
|
|
uint32_t destWidth,
|
|
uint32_t bytesEachRequest,
|
|
uint32_t transferBytes,
|
|
edma_transfer_type_t type)
|
|
{
|
|
assert(config != NULL);
|
|
assert(srcAddr != NULL);
|
|
assert(destAddr != NULL);
|
|
assert((srcWidth == 1U) || (srcWidth == 2U) || (srcWidth == 4U) || (srcWidth == 16U) || (srcWidth == 32U));
|
|
assert((destWidth == 1U) || (destWidth == 2U) || (destWidth == 4U) || (destWidth == 16U) || (destWidth == 32U));
|
|
assert(transferBytes % bytesEachRequest == 0);
|
|
|
|
/* Initializes the configure structure to zero. */
|
|
memset(config, 0, sizeof(*config));
|
|
|
|
config->destAddr = (uint32_t)destAddr;
|
|
config->srcAddr = (uint32_t)srcAddr;
|
|
config->minorLoopBytes = bytesEachRequest;
|
|
config->majorLoopCounts = transferBytes / bytesEachRequest;
|
|
switch (srcWidth)
|
|
{
|
|
case 1U:
|
|
config->srcTransferSize = kEDMA_TransferSize1Bytes;
|
|
break;
|
|
case 2U:
|
|
config->srcTransferSize = kEDMA_TransferSize2Bytes;
|
|
break;
|
|
case 4U:
|
|
config->srcTransferSize = kEDMA_TransferSize4Bytes;
|
|
break;
|
|
case 16U:
|
|
config->srcTransferSize = kEDMA_TransferSize16Bytes;
|
|
break;
|
|
case 32U:
|
|
config->srcTransferSize = kEDMA_TransferSize32Bytes;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
switch (destWidth)
|
|
{
|
|
case 1U:
|
|
config->destTransferSize = kEDMA_TransferSize1Bytes;
|
|
break;
|
|
case 2U:
|
|
config->destTransferSize = kEDMA_TransferSize2Bytes;
|
|
break;
|
|
case 4U:
|
|
config->destTransferSize = kEDMA_TransferSize4Bytes;
|
|
break;
|
|
case 16U:
|
|
config->destTransferSize = kEDMA_TransferSize16Bytes;
|
|
break;
|
|
case 32U:
|
|
config->destTransferSize = kEDMA_TransferSize32Bytes;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
switch (type)
|
|
{
|
|
case kEDMA_MemoryToMemory:
|
|
config->destOffset = destWidth;
|
|
config->srcOffset = srcWidth;
|
|
break;
|
|
case kEDMA_MemoryToPeripheral:
|
|
config->destOffset = 0U;
|
|
config->srcOffset = srcWidth;
|
|
break;
|
|
case kEDMA_PeripheralToMemory:
|
|
config->destOffset = destWidth;
|
|
config->srcOffset = 0U;
|
|
break;
|
|
default:
|
|
break;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief Submits the eDMA transfer request.
|
|
*
|
|
* This function submits the eDMA transfer request according to the transfer configuration structure.
|
|
* In scatter gather mode, call this function will add a configured tcd to the circular list of tcd pool.
|
|
* The tcd pools is setup by call function EDMA_InstallTCDMemory before.
|
|
*
|
|
* param handle eDMA handle pointer.
|
|
* param config Pointer to eDMA transfer configuration structure.
|
|
* retval kStatus_EDMA_Success It means submit transfer request succeed.
|
|
* retval kStatus_EDMA_QueueFull It means TCD queue is full. Submit transfer request is not allowed.
|
|
* retval kStatus_EDMA_Busy It means the given channel is busy, need to submit request later.
|
|
*/
|
|
status_t EDMA_SubmitTransfer(edma_handle_t *handle, const edma_transfer_config_t *config)
|
|
{
|
|
assert(handle != NULL);
|
|
assert(config != NULL);
|
|
|
|
edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
|
|
|
|
if (handle->tcdPool == NULL)
|
|
{
|
|
/*
|
|
Check if EDMA is busy: if the given channel started transfer, CSR will be not zero. Because
|
|
if it is the last transfer, DREQ will be set. If not, ESG will be set. So in order to suit
|
|
this check mechanism, EDMA_CreatHandle will clear CSR register.
|
|
*/
|
|
if ((tcdRegs->CSR != 0) && ((tcdRegs->CSR & DMA_CSR_DONE_MASK) == 0))
|
|
{
|
|
return kStatus_EDMA_Busy;
|
|
}
|
|
else
|
|
{
|
|
EDMA_SetTransferConfig(handle->base, handle->channel, config, NULL);
|
|
/* Enable auto disable request feature */
|
|
handle->base->TCD[handle->channel].CSR |= DMA_CSR_DREQ_MASK;
|
|
/* Enable major interrupt */
|
|
handle->base->TCD[handle->channel].CSR |= DMA_CSR_INTMAJOR_MASK;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
}
|
|
else /* Use the TCD queue. */
|
|
{
|
|
uint32_t primask;
|
|
uint32_t csr;
|
|
int8_t currentTcd;
|
|
int8_t previousTcd;
|
|
int8_t nextTcd;
|
|
|
|
/* Check if tcd pool is full. */
|
|
primask = DisableGlobalIRQ();
|
|
if (handle->tcdUsed >= handle->tcdSize)
|
|
{
|
|
EnableGlobalIRQ(primask);
|
|
|
|
return kStatus_EDMA_QueueFull;
|
|
}
|
|
currentTcd = handle->tail;
|
|
handle->tcdUsed++;
|
|
/* Calculate index of next TCD */
|
|
nextTcd = currentTcd + 1U;
|
|
if (nextTcd == handle->tcdSize)
|
|
{
|
|
nextTcd = 0U;
|
|
}
|
|
/* Advance queue tail index */
|
|
handle->tail = nextTcd;
|
|
EnableGlobalIRQ(primask);
|
|
/* Calculate index of previous TCD */
|
|
previousTcd = currentTcd ? currentTcd - 1U : handle->tcdSize - 1U;
|
|
/* Configure current TCD block. */
|
|
EDMA_TcdReset(&handle->tcdPool[currentTcd]);
|
|
EDMA_TcdSetTransferConfig(&handle->tcdPool[currentTcd], config, NULL);
|
|
/* Enable major interrupt */
|
|
handle->tcdPool[currentTcd].CSR |= DMA_CSR_INTMAJOR_MASK;
|
|
/* Link current TCD with next TCD for identification of current TCD */
|
|
handle->tcdPool[currentTcd].DLAST_SGA = (uint32_t)&handle->tcdPool[nextTcd];
|
|
/* Chain from previous descriptor unless tcd pool size is 1(this descriptor is its own predecessor). */
|
|
if (currentTcd != previousTcd)
|
|
{
|
|
/* Enable scatter/gather feature in the previous TCD block. */
|
|
csr = (handle->tcdPool[previousTcd].CSR | DMA_CSR_ESG_MASK) & ~DMA_CSR_DREQ_MASK;
|
|
handle->tcdPool[previousTcd].CSR = csr;
|
|
/*
|
|
Check if the TCD block in the registers is the previous one (points to current TCD block). It
|
|
is used to check if the previous TCD linked has been loaded in TCD register. If so, it need to
|
|
link the TCD register in case link the current TCD with the dead chain when TCD loading occurs
|
|
before link the previous TCD block.
|
|
*/
|
|
if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[currentTcd])
|
|
{
|
|
/* Clear the DREQ bits for the dynamic scatter gather */
|
|
tcdRegs->CSR |= DMA_CSR_DREQ_MASK;
|
|
/* Enable scatter/gather also in the TCD registers. */
|
|
csr = tcdRegs->CSR | DMA_CSR_ESG_MASK;
|
|
/* Must write the CSR register one-time, because the transfer maybe finished anytime. */
|
|
tcdRegs->CSR = csr;
|
|
/*
|
|
It is very important to check the ESG bit!
|
|
Because this hardware design: if DONE bit is set, the ESG bit can not be set. So it can
|
|
be used to check if the dynamic TCD link operation is successful. If ESG bit is not set
|
|
and the DLAST_SGA is not the next TCD address(it means the dynamic TCD link succeed and
|
|
the current TCD block has been loaded into TCD registers), it means transfer finished
|
|
and TCD link operation fail, so must install TCD content into TCD registers and enable
|
|
transfer again. And if ESG is set, it means transfer has not finished, so TCD dynamic
|
|
link succeed.
|
|
*/
|
|
if (tcdRegs->CSR & DMA_CSR_ESG_MASK)
|
|
{
|
|
tcdRegs->CSR &= ~DMA_CSR_DREQ_MASK;
|
|
return kStatus_Success;
|
|
}
|
|
/*
|
|
Check whether the current TCD block is already loaded in the TCD registers. It is another
|
|
condition when ESG bit is not set: it means the dynamic TCD link succeed and the current
|
|
TCD block has been loaded into TCD registers.
|
|
*/
|
|
if (tcdRegs->DLAST_SGA == (uint32_t)&handle->tcdPool[nextTcd])
|
|
{
|
|
return kStatus_Success;
|
|
}
|
|
/*
|
|
If go to this, means the previous transfer finished, and the DONE bit is set.
|
|
So shall configure TCD registers.
|
|
*/
|
|
}
|
|
else if (tcdRegs->DLAST_SGA != 0)
|
|
{
|
|
/* The current TCD block has been linked successfully. */
|
|
return kStatus_Success;
|
|
}
|
|
else
|
|
{
|
|
/*
|
|
DLAST_SGA is 0 and it means the first submit transfer, so shall configure
|
|
TCD registers.
|
|
*/
|
|
}
|
|
}
|
|
/* There is no live chain, TCD block need to be installed in TCD registers. */
|
|
EDMA_InstallTCD(handle->base, handle->channel, &handle->tcdPool[currentTcd]);
|
|
/* Enable channel request again. */
|
|
if (handle->flags & EDMA_TRANSFER_ENABLED_MASK)
|
|
{
|
|
handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
|
|
}
|
|
|
|
return kStatus_Success;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief eDMA starts transfer.
|
|
*
|
|
* This function enables the channel request. Users can call this function after submitting the transfer request
|
|
* or before submitting the transfer request.
|
|
*
|
|
* param handle eDMA handle pointer.
|
|
*/
|
|
void EDMA_StartTransfer(edma_handle_t *handle)
|
|
{
|
|
assert(handle != NULL);
|
|
|
|
if (handle->tcdPool == NULL)
|
|
{
|
|
handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
|
|
}
|
|
else /* Use the TCD queue. */
|
|
{
|
|
uint32_t primask;
|
|
edma_tcd_t *tcdRegs = (edma_tcd_t *)&handle->base->TCD[handle->channel];
|
|
|
|
handle->flags |= EDMA_TRANSFER_ENABLED_MASK;
|
|
|
|
/* Check if there was at least one descriptor submitted since reset (TCD in registers is valid) */
|
|
if (tcdRegs->DLAST_SGA != 0U)
|
|
{
|
|
primask = DisableGlobalIRQ();
|
|
/* Check if channel request is actually disable. */
|
|
if ((handle->base->ERQ & (1U << handle->channel)) == 0U)
|
|
{
|
|
/* Check if transfer is paused. */
|
|
if ((!(tcdRegs->CSR & DMA_CSR_DONE_MASK)) || (tcdRegs->CSR & DMA_CSR_ESG_MASK))
|
|
{
|
|
/*
|
|
Re-enable channel request must be as soon as possible, so must put it into
|
|
critical section to avoid task switching or interrupt service routine.
|
|
*/
|
|
handle->base->SERQ = DMA_SERQ_SERQ(handle->channel);
|
|
}
|
|
}
|
|
EnableGlobalIRQ(primask);
|
|
}
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief eDMA stops transfer.
|
|
*
|
|
* This function disables the channel request to pause the transfer. Users can call EDMA_StartTransfer()
|
|
* again to resume the transfer.
|
|
*
|
|
* param handle eDMA handle pointer.
|
|
*/
|
|
void EDMA_StopTransfer(edma_handle_t *handle)
|
|
{
|
|
assert(handle != NULL);
|
|
|
|
handle->flags &= (~EDMA_TRANSFER_ENABLED_MASK);
|
|
handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
|
|
}
|
|
|
|
/*!
|
|
* brief eDMA aborts transfer.
|
|
*
|
|
* This function disables the channel request and clear transfer status bits.
|
|
* Users can submit another transfer after calling this API.
|
|
*
|
|
* param handle DMA handle pointer.
|
|
*/
|
|
void EDMA_AbortTransfer(edma_handle_t *handle)
|
|
{
|
|
handle->base->CERQ = DMA_CERQ_CERQ(handle->channel);
|
|
/*
|
|
Clear CSR to release channel. Because if the given channel started transfer,
|
|
CSR will be not zero. Because if it is the last transfer, DREQ will be set.
|
|
If not, ESG will be set.
|
|
*/
|
|
handle->base->TCD[handle->channel].CSR = 0;
|
|
/* Cancel all next TCD transfer. */
|
|
handle->base->TCD[handle->channel].DLAST_SGA = 0;
|
|
|
|
/* Handle the tcd */
|
|
if (handle->tcdPool != NULL)
|
|
{
|
|
handle->header = 0;
|
|
handle->tail = 0;
|
|
handle->tcdUsed = 0;
|
|
}
|
|
}
|
|
|
|
/*!
|
|
* brief eDMA IRQ handler for the current major loop transfer completion.
|
|
*
|
|
* This function clears the channel major interrupt flag and calls
|
|
* the callback function if it is not NULL.
|
|
*
|
|
* Note:
|
|
* For the case using TCD queue, when the major iteration count is exhausted, additional operations are performed.
|
|
* These include the final address adjustments and reloading of the BITER field into the CITER.
|
|
* Assertion of an optional interrupt request also occurs at this time, as does a possible fetch of a new TCD from
|
|
* memory using the scatter/gather address pointer included in the descriptor (if scatter/gather is enabled).
|
|
*
|
|
* For instance, when the time interrupt of TCD[0] happens, the TCD[1] has already been loaded into the eDMA engine.
|
|
* As sga and sga_index are calculated based on the DLAST_SGA bitfield lies in the TCD_CSR register, the sga_index
|
|
* in this case should be 2 (DLAST_SGA of TCD[1] stores the address of TCD[2]). Thus, the "tcdUsed" updated should be
|
|
* (tcdUsed - 2U) which indicates the number of TCDs can be loaded in the memory pool (because TCD[0] and TCD[1] have
|
|
* been loaded into the eDMA engine at this point already.).
|
|
*
|
|
* For the last two continuous ISRs in a scatter/gather process, they both load the last TCD (The last ISR does not
|
|
* load a new TCD) from the memory pool to the eDMA engine when major loop completes.
|
|
* Therefore, ensure that the header and tcdUsed updated are identical for them.
|
|
* tcdUsed are both 0 in this case as no TCD to be loaded.
|
|
*
|
|
* See the "eDMA basic data flow" in the eDMA Functional description section of the Reference Manual for
|
|
* further details.
|
|
*
|
|
* param handle eDMA handle pointer.
|
|
*/
|
|
void EDMA_HandleIRQ(edma_handle_t *handle)
|
|
{
|
|
assert(handle != NULL);
|
|
|
|
/* Clear EDMA interrupt flag */
|
|
handle->base->CINT = handle->channel;
|
|
if ((handle->tcdPool == NULL) && (handle->callback != NULL))
|
|
{
|
|
(handle->callback)(handle, handle->userData, true, 0);
|
|
}
|
|
else /* Use the TCD queue. Please refer to the API descriptions in the eDMA header file for detailed information. */
|
|
{
|
|
uint32_t sga = handle->base->TCD[handle->channel].DLAST_SGA;
|
|
uint32_t sga_index;
|
|
int32_t tcds_done;
|
|
uint8_t new_header;
|
|
bool transfer_done;
|
|
|
|
/* Check if transfer is already finished. */
|
|
transfer_done = ((handle->base->TCD[handle->channel].CSR & DMA_CSR_DONE_MASK) != 0);
|
|
/* Get the offset of the next transfer TCD blocks to be loaded into the eDMA engine. */
|
|
sga -= (uint32_t)handle->tcdPool;
|
|
/* Get the index of the next transfer TCD blocks to be loaded into the eDMA engine. */
|
|
sga_index = sga / sizeof(edma_tcd_t);
|
|
/* Adjust header positions. */
|
|
if (transfer_done)
|
|
{
|
|
/* New header shall point to the next TCD to be loaded (current one is already finished) */
|
|
new_header = sga_index;
|
|
}
|
|
else
|
|
{
|
|
/* New header shall point to this descriptor currently loaded (not finished yet) */
|
|
new_header = sga_index ? sga_index - 1U : handle->tcdSize - 1U;
|
|
}
|
|
/* Calculate the number of finished TCDs */
|
|
if (new_header == handle->header)
|
|
{
|
|
if (handle->tcdUsed == handle->tcdSize)
|
|
{
|
|
tcds_done = handle->tcdUsed;
|
|
}
|
|
else
|
|
{
|
|
/* No TCD in the memory are going to be loaded or internal error occurs. */
|
|
tcds_done = 0;
|
|
}
|
|
}
|
|
else
|
|
{
|
|
tcds_done = new_header - handle->header;
|
|
if (tcds_done < 0)
|
|
{
|
|
tcds_done += handle->tcdSize;
|
|
}
|
|
}
|
|
/* Advance header which points to the TCD to be loaded into the eDMA engine from memory. */
|
|
handle->header = new_header;
|
|
/* Release TCD blocks. tcdUsed is the TCD number which can be used/loaded in the memory pool. */
|
|
handle->tcdUsed -= tcds_done;
|
|
/* Invoke callback function. */
|
|
if (handle->callback)
|
|
{
|
|
(handle->callback)(handle, handle->userData, transfer_done, tcds_done);
|
|
}
|
|
|
|
/* clear the DONE bit here is meaningful for below cases:
|
|
*1.A new TCD has been loaded to EDMA already:
|
|
* need to clear the DONE bit in the IRQ handler to avoid TCD in EDMA been overwritten
|
|
* if peripheral request isn't coming before next transfer request.
|
|
*2.A new TCD has not been loaded to EDMA:
|
|
* for the case that transfer request occur in the privious edma callback, this is a case that doesn't
|
|
* need scatter gather, so keep DONE bit during the next transfer request will re-install the TCD.
|
|
*/
|
|
if (transfer_done)
|
|
{
|
|
handle->base->CDNE = handle->channel;
|
|
}
|
|
}
|
|
}
|
|
|
|
/* 8 channels (Shared): kl28 */
|
|
#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 8U
|
|
|
|
#if defined(DMA0)
|
|
void DMA0_04_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[0]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[4]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_15_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[1]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[5]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_26_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[2]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[6]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_37_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[3]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[7]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
|
|
#if defined(DMA1)
|
|
|
|
#if defined(DMA0)
|
|
void DMA1_04_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[8]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[12]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_15_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[9]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[13]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_26_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[10]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[14]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_37_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[11]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[15]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
#else
|
|
void DMA1_04_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[0]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[4]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_15_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[1]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[5]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_26_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[2]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[6]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_37_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[3]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[7]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif
|
|
#endif /* 8 channels (Shared) */
|
|
|
|
/* 16 channels (Shared): K32H844P */
|
|
#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 16U
|
|
|
|
void DMA0_08_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[0]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[8]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_19_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[1]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[9]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_210_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[2]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[10]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_311_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[3]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[11]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_412_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[4]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[12]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_513_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[5]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[13]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_614_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[6]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[14]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_715_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[7]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[15]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
#if defined(DMA1)
|
|
void DMA1_08_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 0U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[16]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 8U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[24]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_19_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 1U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[17]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 9U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[25]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_210_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 2U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[18]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 10U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[26]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_311_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 3U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[19]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 11U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[27]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_412_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 4U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[20]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 12U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[28]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_513_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 5U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[21]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 13U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[29]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_614_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 6U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[22]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 14U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[30]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_715_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 7U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[23]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA1, 15U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[31]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif
|
|
#endif /* 16 channels (Shared) */
|
|
|
|
/* 32 channels (Shared): k80 */
|
|
#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
|
|
|
|
void DMA0_DMA16_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[0]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[16]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_DMA17_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[1]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[17]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA2_DMA18_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[2]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[18]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA3_DMA19_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[3]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[19]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA4_DMA20_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[4]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[20]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA5_DMA21_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[5]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[21]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA6_DMA22_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[6]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[22]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA7_DMA23_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[7]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[23]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA8_DMA24_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[8]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[24]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA9_DMA25_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[9]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[25]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA10_DMA26_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[10]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[26]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA11_DMA27_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[11]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[27]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA12_DMA28_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[12]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[28]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA13_DMA29_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[13]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[29]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA14_DMA30_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[14]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[30]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA15_DMA31_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[15]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[31]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif /* 32 channels (Shared) */
|
|
|
|
/* 32 channels (Shared): MCIMX7U5_M4 */
|
|
#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL == 32U
|
|
|
|
void DMA0_0_4_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 0U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[0]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 4U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[4]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_1_5_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 1U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[1]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 5U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[5]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_2_6_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 2U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[2]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 6U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[6]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_3_7_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 3U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[3]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 7U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[7]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_8_12_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 8U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[8]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 12U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[12]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_9_13_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 9U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[9]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 13U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[13]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_10_14_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 10U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[10]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 14U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[14]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_11_15_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 11U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[11]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 15U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[15]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_16_20_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 16U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[16]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 20U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[20]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_17_21_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 17U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[17]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 21U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[21]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_18_22_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 18U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[18]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 22U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[22]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_19_23_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 19U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[19]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 23U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[23]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_24_28_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 24U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[24]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 28U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[28]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_25_29_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 25U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[25]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 29U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[29]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_26_30_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 26U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[26]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 30U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[30]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA0_27_31_DriverIRQHandler(void)
|
|
{
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 27U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[27]);
|
|
}
|
|
if ((EDMA_GetChannelStatusFlags(DMA0, 31U) & kEDMA_InterruptFlag) != 0U)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[31]);
|
|
}
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif /* 32 channels (Shared): MCIMX7U5 */
|
|
|
|
/* 4 channels (No Shared): kv10 */
|
|
#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 0
|
|
|
|
void DMA0_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[0]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA1_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[1]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA2_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[2]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA3_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[3]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
/* 8 channels (No Shared) */
|
|
#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 4U
|
|
|
|
void DMA4_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[4]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA5_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[5]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA6_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[6]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA7_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[7]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 8 */
|
|
|
|
/* 16 channels (No Shared) */
|
|
#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 8U
|
|
|
|
void DMA8_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[8]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA9_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[9]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA10_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[10]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA11_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[11]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA12_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[12]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA13_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[13]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA14_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[14]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA15_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[15]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 16 */
|
|
|
|
/* 32 channels (No Shared) */
|
|
#if defined(FSL_FEATURE_EDMA_MODULE_CHANNEL) && FSL_FEATURE_EDMA_MODULE_CHANNEL > 16U
|
|
|
|
void DMA16_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[16]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA17_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[17]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA18_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[18]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA19_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[19]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA20_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[20]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA21_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[21]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA22_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[22]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA23_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[23]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA24_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[24]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA25_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[25]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA26_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[26]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA27_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[27]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA28_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[28]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA29_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[29]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA30_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[30]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
|
|
void DMA31_DriverIRQHandler(void)
|
|
{
|
|
EDMA_HandleIRQ(s_EDMAHandle[31]);
|
|
/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
|
|
exception return operation might vector to incorrect interrupt */
|
|
#if defined __CORTEX_M && (__CORTEX_M == 4U)
|
|
__DSB();
|
|
#endif
|
|
}
|
|
#endif /* FSL_FEATURE_EDMA_MODULE_CHANNEL == 32 */
|
|
|
|
#endif /* 4/8/16/32 channels (No Shared) */
|