55 lines
1.4 KiB
C
55 lines
1.4 KiB
C
#ifndef _LS2K1000_H__
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#define _LS2K1000_H__
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#include <mips.h>
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#include "interrupt.h"
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#include <rthw.h>
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#define APB_BASE CKSEG1ADDR(0xbfe00000)
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#define UART0_BASE_ADDR (0xbfe00000)
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#define UART0_OFF (0x0)
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#define UART0_BASE CKSEG1ADDR(UART0_BASE_ADDR + UART0_OFF)
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#define UARTx_BASE(x) ((APB_BASE | (0x0 << 12) | (x << 8)))
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#define LIOINTC0_BASE CKSEG1ADDR(0x1fe11400)
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#define CORE0_INTISR0 CKSEG1ADDR(0x1fe11040)
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#define LIOINTC1_BASE CKSEG1ADDR(0x1fe11440)
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#define CORE0_INTISR1 CKSEG1ADDR(0x1fe11048)
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#define GPIO_BASE (0xFFFFFFFFBFE10500)
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#define PLL_SYS_BASE (0xFFFFFFFFBFE10480)
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#define RTC_BASE (0xFFFFFFFFBFE07820)
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#define GEN_CONFIG0_REG (0xFFFFFFFFBfe10420)
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/*
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* General PM Configuration Register
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*/
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#define PMCON_BASE (APB_BASE | (0x7 << 12))
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/*
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* Power Management1 Configuration Registers
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*/
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#define PM1_BASE (PMCON_BASE + 0x0C)
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#define PM1_STS HWREG32(PM1_BASE)
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#define PM1_EN HWREG32(PM1_BASE + 0x04)
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#define PM1_CNT HWREG32(PM1_BASE + 0x08)
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/*
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* Watch Dog Configuration Registers
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*/
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#define WDT_BASE (PMCON_BASE + 0x30)
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#define WDT_EN HWREG32(WDT_BASE)
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#define WDT_SET HWREG32(WDT_BASE + 0x04)
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#define WDT_TIMER HWREG32(WDT_BASE + 0x08)
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void rt_hw_timer_handler(void);
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void rt_hw_uart_init(void);
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#endif
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