460 lines
23 KiB
C
460 lines
23 KiB
C
//*****************************************************************************
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//
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// hw_flash.h - Macros used when accessing the flash controller.
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//
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// Copyright (c) 2005-2011 Texas Instruments Incorporated. All rights reserved.
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// Software License Agreement
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//
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// Texas Instruments (TI) is supplying this software for use solely and
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// exclusively on TI's microcontroller products. The software is owned by
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// TI and/or its suppliers, and is protected under applicable copyright
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// laws. You may not combine this software with "viral" open-source
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// software in order to form a larger program.
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//
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// THIS SOFTWARE IS PROVIDED "AS IS" AND WITH ALL FAULTS.
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// NO WARRANTIES, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING, BUT
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// NOT LIMITED TO, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. TI SHALL NOT, UNDER ANY
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// CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR CONSEQUENTIAL
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// DAMAGES, FOR ANY REASON WHATSOEVER.
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//
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// This is part of revision 8264 of the Stellaris Firmware Development Package.
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//
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//*****************************************************************************
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#ifndef __HW_FLASH_H__
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#define __HW_FLASH_H__
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//*****************************************************************************
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//
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// The following are defines for the FLASH register offsets.
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//
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//*****************************************************************************
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#define FLASH_FMA 0x400FD000 // Flash Memory Address
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#define FLASH_FMD 0x400FD004 // Flash Memory Data
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#define FLASH_FMC 0x400FD008 // Flash Memory Control
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#define FLASH_FCRIS 0x400FD00C // Flash Controller Raw Interrupt
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// Status
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#define FLASH_FCIM 0x400FD010 // Flash Controller Interrupt Mask
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#define FLASH_FCMISC 0x400FD014 // Flash Controller Masked
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// Interrupt Status and Clear
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#define FLASH_FMC2 0x400FD020 // Flash Memory Control 2
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#define FLASH_FWBVAL 0x400FD030 // Flash Write Buffer Valid
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#define FLASH_FCTL 0x400FD0F8 // Flash Control
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#define FLASH_FWBN 0x400FD100 // Flash Write Buffer n
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#define FLASH_FSIZE 0x400FDFC0 // Flash Size
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#define FLASH_SSIZE 0x400FDFC4 // SRAM Size
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#define FLASH_ROMSWMAP 0x400FDFCC // ROM Software Map
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#define FLASH_RMCTL 0x400FE0F0 // ROM Control
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#define FLASH_FMPRE 0x400FE130 // Flash Memory Protection Read
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// Enable
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#define FLASH_FMPPE 0x400FE134 // Flash Memory Protection Program
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// Enable
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#define FLASH_USECRL 0x400FE140 // USec Reload
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#define FLASH_USERDBG 0x400FE1D0 // User Debug
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#define FLASH_BOOTCFG 0x400FE1D0 // Boot Configuration
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#define FLASH_USERREG0 0x400FE1E0 // User Register 0
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#define FLASH_USERREG1 0x400FE1E4 // User Register 1
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#define FLASH_USERREG2 0x400FE1E8 // User Register 2
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#define FLASH_USERREG3 0x400FE1EC // User Register 3
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#define FLASH_FMPRE0 0x400FE200 // Flash Memory Protection Read
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// Enable 0
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#define FLASH_FMPRE1 0x400FE204 // Flash Memory Protection Read
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// Enable 1
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#define FLASH_FMPRE2 0x400FE208 // Flash Memory Protection Read
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// Enable 2
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#define FLASH_FMPRE3 0x400FE20C // Flash Memory Protection Read
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// Enable 3
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#define FLASH_FMPRE4 0x400FE210 // Flash Memory Protection Read
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// Enable 4
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#define FLASH_FMPRE5 0x400FE214 // Flash Memory Protection Read
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// Enable 5
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#define FLASH_FMPRE6 0x400FE218 // Flash Memory Protection Read
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// Enable 6
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#define FLASH_FMPRE7 0x400FE21C // Flash Memory Protection Read
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// Enable 7
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#define FLASH_FMPPE0 0x400FE400 // Flash Memory Protection Program
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// Enable 0
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#define FLASH_FMPPE1 0x400FE404 // Flash Memory Protection Program
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// Enable 1
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#define FLASH_FMPPE2 0x400FE408 // Flash Memory Protection Program
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// Enable 2
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#define FLASH_FMPPE3 0x400FE40C // Flash Memory Protection Program
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// Enable 3
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#define FLASH_FMPPE4 0x400FE410 // Flash Memory Protection Program
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// Enable 4
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#define FLASH_FMPPE5 0x400FE414 // Flash Memory Protection Program
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// Enable 5
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#define FLASH_FMPPE6 0x400FE418 // Flash Memory Protection Program
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// Enable 6
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#define FLASH_FMPPE7 0x400FE41C // Flash Memory Protection Program
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// Enable 7
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FMA register.
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//
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//*****************************************************************************
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#define FLASH_FMA_OFFSET_M 0x0007FFFF // Address Offset
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#define FLASH_FMA_OFFSET_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FMD register.
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//
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//*****************************************************************************
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#define FLASH_FMD_DATA_M 0xFFFFFFFF // Data Value
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#define FLASH_FMD_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FMC register.
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//
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//*****************************************************************************
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#define FLASH_FMC_WRKEY 0xA4420000 // FLASH write key
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#define FLASH_FMC_COMT 0x00000008 // Commit Register Value
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#define FLASH_FMC_MERASE 0x00000004 // Mass Erase Flash Memory
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#define FLASH_FMC_ERASE 0x00000002 // Erase a Page of Flash Memory
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#define FLASH_FMC_WRITE 0x00000001 // Write a Word into Flash Memory
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FCRIS register.
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//
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//*****************************************************************************
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#define FLASH_FCRIS_PROGRIS 0x00002000 // PROGVER Raw Interrupt Status
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#define FLASH_FCRIS_ERRIS 0x00000800 // ERVER Raw Interrupt Status
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#define FLASH_FCRIS_INVDRIS 0x00000400 // Invalid Data Raw Interrupt
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// Status
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#define FLASH_FCRIS_VOLTRIS 0x00000200 // VOLTSTAT Raw Interrupt Status
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#define FLASH_FCRIS_ERIS 0x00000004 // EEPROM Raw Interrupt Status
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#define FLASH_FCRIS_PRIS 0x00000002 // Programming Raw Interrupt Status
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#define FLASH_FCRIS_ARIS 0x00000001 // Access Raw Interrupt Status
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FCIM register.
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//
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//*****************************************************************************
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#define FLASH_FCIM_PROGMASK 0x00002000 // PROGVER Interrupt Mask
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#define FLASH_FCIM_ERMASK 0x00000800 // ERVER Interrupt Mask
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#define FLASH_FCIM_INVDMASK 0x00000400 // Invalid Data Interrupt Mask
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#define FLASH_FCIM_VOLTMASK 0x00000200 // VOLT Interrupt Mask
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#define FLASH_FCIM_EMASK 0x00000004 // EEPROM Interrupt Mask
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#define FLASH_FCIM_PMASK 0x00000002 // Programming Interrupt Mask
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#define FLASH_FCIM_AMASK 0x00000001 // Access Interrupt Mask
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FCMISC register.
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//
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//*****************************************************************************
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#define FLASH_FCMISC_PROGMISC 0x00002000 // PROGVER Masked Interrupt Status
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// and Clear
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#define FLASH_FCMISC_ERMISC 0x00000800 // ERVER Masked Interrupt Status
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// and Clear
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#define FLASH_FCMISC_INVDMISC 0x00000400 // Invalid Data Masked Interrupt
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// Status and Clear
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#define FLASH_FCMISC_VOLTMISC 0x00000200 // VOLT Masked Interrupt Status and
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// Clear
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#define FLASH_FCMISC_EMISC 0x00000004 // EEPROM Masked Interrupt Status
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// and Clear
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#define FLASH_FCMISC_PMISC 0x00000002 // Programming Masked Interrupt
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// Status and Clear
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#define FLASH_FCMISC_AMISC 0x00000001 // Access Masked Interrupt Status
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// and Clear
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FMC2 register.
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//
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//*****************************************************************************
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#define FLASH_FMC2_WRKEY 0xA4420000 // FLASH write key
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#define FLASH_FMC2_WRBUF 0x00000001 // Buffered Flash Memory Write
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FWBVAL register.
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//
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//*****************************************************************************
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#define FLASH_FWBVAL_FWB_M 0xFFFFFFFF // Flash Memory Write Buffer
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FCTL register.
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//
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//*****************************************************************************
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#define FLASH_FCTL_USDACK 0x00000002 // User Shut Down Acknowledge
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#define FLASH_FCTL_USDREQ 0x00000001 // User Shut Down Request
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FWBN register.
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//
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//*****************************************************************************
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#define FLASH_FWBN_DATA_M 0xFFFFFFFF // Data
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FSIZE register.
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//
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//*****************************************************************************
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#define FLASH_FSIZE_SIZE_M 0x0000FFFF // Flash Size
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#define FLASH_FSIZE_SIZE_8KB 0x00000003 // 8 KB of Flash
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#define FLASH_FSIZE_SIZE_16KB 0x00000007 // 16 KB of Flash
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#define FLASH_FSIZE_SIZE_32KB 0x0000000F // 32 KB of Flash
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#define FLASH_FSIZE_SIZE_64KB 0x0000001F // 64 KB of Flash
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#define FLASH_FSIZE_SIZE_96KB 0x0000002F // 96 KB of Flash
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#define FLASH_FSIZE_SIZE_128KB 0x0000003F // 128 KB of Flash
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#define FLASH_FSIZE_SIZE_192KB 0x0000005F // 192 KB of Flash
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#define FLASH_FSIZE_SIZE_256KB 0x0000007F // 256 KB of Flash
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_SSIZE register.
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//
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//*****************************************************************************
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#define FLASH_SSIZE_SIZE_M 0x0000FFFF // SRAM Size
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#define FLASH_SSIZE_SIZE_2KB 0x00000007 // 2 KB of SRAM
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#define FLASH_SSIZE_SIZE_4KB 0x0000000F // 4 KB of SRAM
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#define FLASH_SSIZE_SIZE_6KB 0x00000017 // 6 KB of SRAM
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#define FLASH_SSIZE_SIZE_8KB 0x0000001F // 8 KB of SRAM
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#define FLASH_SSIZE_SIZE_12KB 0x0000002F // 12 KB of SRAM
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#define FLASH_SSIZE_SIZE_16KB 0x0000003F // 16 KB of SRAM
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#define FLASH_SSIZE_SIZE_20KB 0x0000004F // 20 KB of SRAM
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#define FLASH_SSIZE_SIZE_24KB 0x0000005F // 24 KB of SRAM
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#define FLASH_SSIZE_SIZE_32KB 0x0000007F // 32 KB of SRAM
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_ROMSWMAP register.
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//
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//*****************************************************************************
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#define FLASH_ROMSWMAP_SAFERTOS 0x00000001 // SafeRTOS Present
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_RMCTL register.
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//
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//*****************************************************************************
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#define FLASH_RMCTL_BA 0x00000001 // Boot Alias
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_USECRL register.
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//
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//*****************************************************************************
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#define FLASH_USECRL_M 0x000000FF // Microsecond Reload Value
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#define FLASH_USECRL_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_USERDBG register.
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//
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//*****************************************************************************
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#define FLASH_USERDBG_NW 0x80000000 // User Debug Not Written
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#define FLASH_USERDBG_DATA_M 0x7FFFFFFC // User Data
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#define FLASH_USERDBG_DBG1 0x00000002 // Debug Control 1
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#define FLASH_USERDBG_DBG0 0x00000001 // Debug Control 0
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#define FLASH_USERDBG_DATA_S 2
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_BOOTCFG register.
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//
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//*****************************************************************************
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#define FLASH_BOOTCFG_NW 0x80000000 // Not Written
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#define FLASH_BOOTCFG_PORT_M 0x0000E000 // Boot GPIO Port
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#define FLASH_BOOTCFG_PORT_A 0x00000000 // Port A
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#define FLASH_BOOTCFG_PORT_B 0x00002000 // Port B
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#define FLASH_BOOTCFG_PORT_C 0x00004000 // Port C
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#define FLASH_BOOTCFG_PORT_D 0x00006000 // Port D
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#define FLASH_BOOTCFG_PORT_E 0x00008000 // Port E
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#define FLASH_BOOTCFG_PORT_F 0x0000A000 // Port F
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#define FLASH_BOOTCFG_PORT_G 0x0000C000 // Port G
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#define FLASH_BOOTCFG_PORT_H 0x0000E000 // Port H
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#define FLASH_BOOTCFG_PIN_M 0x00001C00 // Boot GPIO Pin
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#define FLASH_BOOTCFG_PIN_0 0x00000000 // Pin 0
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#define FLASH_BOOTCFG_PIN_1 0x00000400 // Pin 1
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#define FLASH_BOOTCFG_PIN_2 0x00000800 // Pin 2
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#define FLASH_BOOTCFG_PIN_3 0x00000C00 // Pin 3
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#define FLASH_BOOTCFG_PIN_4 0x00001000 // Pin 4
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#define FLASH_BOOTCFG_PIN_5 0x00001400 // Pin 5
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#define FLASH_BOOTCFG_PIN_6 0x00001800 // Pin 6
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#define FLASH_BOOTCFG_PIN_7 0x00001C00 // Pin 7
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#define FLASH_BOOTCFG_POL 0x00000200 // Boot GPIO Polarity
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#define FLASH_BOOTCFG_EN 0x00000100 // Boot GPIO Enable
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#define FLASH_BOOTCFG_DBG1 0x00000002 // Debug Control 1
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#define FLASH_BOOTCFG_DBG0 0x00000001 // Debug Control 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_USERREG0 register.
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//
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//*****************************************************************************
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#define FLASH_USERREG0_NW 0x80000000 // Not Written
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#define FLASH_USERREG0_DATA_M 0x7FFFFFFF // User Data
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#define FLASH_USERREG0_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_USERREG1 register.
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//
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//*****************************************************************************
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#define FLASH_USERREG1_NW 0x80000000 // Not Written
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#define FLASH_USERREG1_DATA_M 0x7FFFFFFF // User Data
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#define FLASH_USERREG1_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_USERREG2 register.
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//
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//*****************************************************************************
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#define FLASH_USERREG2_NW 0x80000000 // Not Written
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#define FLASH_USERREG2_DATA_M 0x7FFFFFFF // User Data
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#define FLASH_USERREG2_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_USERREG3 register.
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//
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//*****************************************************************************
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#define FLASH_USERREG3_NW 0x80000000 // Not Written
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#define FLASH_USERREG3_DATA_M 0x7FFFFFFF // User Data
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#define FLASH_USERREG3_DATA_S 0
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//*****************************************************************************
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//
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// The following are defines for the bit fields in the FLASH_FMPRE and
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// FLASH_FMPPE registers.
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//
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//*****************************************************************************
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#define FLASH_FMP_BLOCK_31 0x80000000 // Enable for block 31
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#define FLASH_FMP_BLOCK_30 0x40000000 // Enable for block 30
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#define FLASH_FMP_BLOCK_29 0x20000000 // Enable for block 29
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#define FLASH_FMP_BLOCK_28 0x10000000 // Enable for block 28
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#define FLASH_FMP_BLOCK_27 0x08000000 // Enable for block 27
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#define FLASH_FMP_BLOCK_26 0x04000000 // Enable for block 26
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#define FLASH_FMP_BLOCK_25 0x02000000 // Enable for block 25
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#define FLASH_FMP_BLOCK_24 0x01000000 // Enable for block 24
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#define FLASH_FMP_BLOCK_23 0x00800000 // Enable for block 23
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#define FLASH_FMP_BLOCK_22 0x00400000 // Enable for block 22
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#define FLASH_FMP_BLOCK_21 0x00200000 // Enable for block 21
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#define FLASH_FMP_BLOCK_20 0x00100000 // Enable for block 20
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#define FLASH_FMP_BLOCK_19 0x00080000 // Enable for block 19
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#define FLASH_FMP_BLOCK_18 0x00040000 // Enable for block 18
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#define FLASH_FMP_BLOCK_17 0x00020000 // Enable for block 17
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#define FLASH_FMP_BLOCK_16 0x00010000 // Enable for block 16
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#define FLASH_FMP_BLOCK_15 0x00008000 // Enable for block 15
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#define FLASH_FMP_BLOCK_14 0x00004000 // Enable for block 14
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#define FLASH_FMP_BLOCK_13 0x00002000 // Enable for block 13
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#define FLASH_FMP_BLOCK_12 0x00001000 // Enable for block 12
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#define FLASH_FMP_BLOCK_11 0x00000800 // Enable for block 11
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#define FLASH_FMP_BLOCK_10 0x00000400 // Enable for block 10
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#define FLASH_FMP_BLOCK_9 0x00000200 // Enable for block 9
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#define FLASH_FMP_BLOCK_8 0x00000100 // Enable for block 8
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#define FLASH_FMP_BLOCK_7 0x00000080 // Enable for block 7
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#define FLASH_FMP_BLOCK_6 0x00000040 // Enable for block 6
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#define FLASH_FMP_BLOCK_5 0x00000020 // Enable for block 5
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#define FLASH_FMP_BLOCK_4 0x00000010 // Enable for block 4
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#define FLASH_FMP_BLOCK_3 0x00000008 // Enable for block 3
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#define FLASH_FMP_BLOCK_2 0x00000004 // Enable for block 2
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#define FLASH_FMP_BLOCK_1 0x00000002 // Enable for block 1
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#define FLASH_FMP_BLOCK_0 0x00000001 // Enable for block 0
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//*****************************************************************************
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//
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// The following are defines for the erase size of the FLASH block that is
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// erased by an erase operation, and the protect size is the size of the FLASH
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// block that is protected by each protection register.
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//
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//*****************************************************************************
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#define FLASH_PROTECT_SIZE 0x00000800
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#define FLASH_ERASE_SIZE 0x00000400
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//*****************************************************************************
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//
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// The following definitions are deprecated.
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//
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//*****************************************************************************
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#ifndef DEPRECATED
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//*****************************************************************************
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//
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// The following are deprecated defines for the FLASH register offsets.
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//
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//*****************************************************************************
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#define FLASH_RMVER 0x400FE0F4 // ROM Version Register
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the FLASH_FMC
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// register.
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//
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//*****************************************************************************
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#define FLASH_FMC_WRKEY_MASK 0xFFFF0000 // FLASH write key mask
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#define FLASH_FMC_WRKEY_M 0xFFFF0000 // Flash Memory Write Key
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#define FLASH_FMC_WRKEY_S 16
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the FLASH_FCRIS
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// register.
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//
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//*****************************************************************************
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#define FLASH_FCRIS_PROGRAM 0x00000002 // Programming status
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#define FLASH_FCRIS_ACCESS 0x00000001 // Invalid access status
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the FLASH_FCIM
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// register.
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//
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//*****************************************************************************
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#define FLASH_FCIM_PROGRAM 0x00000002 // Programming mask
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#define FLASH_FCIM_ACCESS 0x00000001 // Invalid access mask
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the FLASH_FCMISC
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// register.
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//
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//*****************************************************************************
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#define FLASH_FCMISC_PROGRAM 0x00000002 // Programming status
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#define FLASH_FCMISC_ACCESS 0x00000001 // Invalid access status
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the FLASH_RMVER
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// register.
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//
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//*****************************************************************************
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#define FLASH_RMVER_CONT_M 0xFF000000 // ROM Contents
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#define FLASH_RMVER_CONT_LM 0x00000000 // Stellaris Boot Loader &
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// DriverLib
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#define FLASH_RMVER_CONT_LM_AES 0x02000000 // Stellaris Boot Loader &
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// DriverLib with AES
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#define FLASH_RMVER_CONT_LM_AES_SAFERTOS \
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0x03000000 // Stellaris Boot Loader &
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// DriverLib with AES and SAFERTOS
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#define FLASH_RMVER_CONT_LM_AES2 \
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0x05000000 // Stellaris Boot Loader &
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// DriverLib with AES
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#define FLASH_RMVER_VER_M 0x0000FF00 // ROM Version
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#define FLASH_RMVER_REV_M 0x000000FF // ROM Revision
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#define FLASH_RMVER_VER_S 8
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#define FLASH_RMVER_REV_S 0
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//*****************************************************************************
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//
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// The following are deprecated defines for the bit fields in the FLASH_USECRL
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// register.
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//
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//*****************************************************************************
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#define FLASH_USECRL_MASK 0x000000FF // Clock per uSec
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#define FLASH_USECRL_SHIFT 0
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#endif
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#endif // __HW_FLASH_H__
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