943f83d58f
1. Add "drv_eth.c" for all imxrt platforms. 2. Add ksz8081 phy driver for imxrt1052-nxp-evk board. 3. Disable the LED demo in main.c file if enable the ENET and ksz8081 phy, because the PINs of LED and ksz8081 reset are from the same GPIO. 4. Update the relevant Kconfig and Sconscript files. Signed-off-by: Gavin Liu <gavin-liugang@outlook.com>
201 lines
8.1 KiB
C
201 lines
8.1 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef _FSL_PHY_H_
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#define _FSL_PHY_H_
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#include "fsl_enet.h"
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/*!
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* @addtogroup phy_driver
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* @{
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief PHY driver version */
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#define FSL_PHY_DRIVER_VERSION (MAKE_VERSION(2, 0, 0)) /*!< Version 2.0.0. */
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/*! @brief Defines the PHY registers. */
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#define PHY_BASICCONTROL_REG 0x00U /*!< The PHY basic control register. */
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#define PHY_BASICSTATUS_REG 0x01U /*!< The PHY basic status register. */
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#define PHY_ID1_REG 0x02U /*!< The PHY ID one register. */
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#define PHY_ID2_REG 0x03U /*!< The PHY ID two register. */
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#define PHY_AUTONEG_ADVERTISE_REG 0x04U /*!< The PHY auto-negotiate advertise register. */
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#define PHY_CONTROL1_REG 0x1EU /*!< The PHY control one register. */
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#define PHY_CONTROL2_REG 0x1FU /*!< The PHY control two register. */
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#define PHY_CONTROL_ID1 0x22U /*!< The PHY ID1*/
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/*! @brief Defines the mask flag in basic control register. */
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#define PHY_BCTL_DUPLEX_MASK 0x0100U /*!< The PHY duplex bit mask. */
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#define PHY_BCTL_RESTART_AUTONEG_MASK 0x0200U /*!< The PHY restart auto negotiation mask. */
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#define PHY_BCTL_AUTONEG_MASK 0x1000U /*!< The PHY auto negotiation bit mask. */
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#define PHY_BCTL_SPEED_MASK 0x2000U /*!< The PHY speed bit mask. */
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#define PHY_BCTL_LOOP_MASK 0x4000U /*!< The PHY loop bit mask. */
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#define PHY_BCTL_RESET_MASK 0x8000U /*!< The PHY reset bit mask. */
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#define PHY_BCTL_SPEED_100M_MASK 0x2000U /*!< The PHY 100M speed mask. */
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/*!@brief Defines the mask flag of operation mode in control two register*/
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#define PHY_CTL2_REMOTELOOP_MASK 0x0004U /*!< The PHY remote loopback mask. */
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#define PHY_CTL2_REFCLK_SELECT_MASK 0x0080U /*!< The PHY RMII reference clock select. */
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#define PHY_CTL1_10HALFDUPLEX_MASK 0x0001U /*!< The PHY 10M half duplex mask. */
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#define PHY_CTL1_100HALFDUPLEX_MASK 0x0002U /*!< The PHY 100M half duplex mask. */
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#define PHY_CTL1_10FULLDUPLEX_MASK 0x0005U /*!< The PHY 10M full duplex mask. */
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#define PHY_CTL1_100FULLDUPLEX_MASK 0x0006U /*!< The PHY 100M full duplex mask. */
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#define PHY_CTL1_SPEEDUPLX_MASK 0x0007U /*!< The PHY speed and duplex mask. */
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#define PHY_CTL1_ENERGYDETECT_MASK 0x10U /*!< The PHY signal present on rx differential pair. */
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#define PHY_CTL1_LINKUP_MASK 0x100U /*!< The PHY link up. */
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#define PHY_LINK_READY_MASK (PHY_CTL1_ENERGYDETECT_MASK | PHY_CTL1_LINKUP_MASK)
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/*! @brief Defines the mask flag in basic status register. */
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#define PHY_BSTATUS_LINKSTATUS_MASK 0x0004U /*!< The PHY link status mask. */
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#define PHY_BSTATUS_AUTONEGABLE_MASK 0x0008U /*!< The PHY auto-negotiation ability mask. */
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#define PHY_BSTATUS_AUTONEGCOMP_MASK 0x0020U /*!< The PHY auto-negotiation complete mask. */
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/*! @brief Defines the mask flag in PHY auto-negotiation advertise register. */
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#define PHY_100BaseT4_ABILITY_MASK 0x200U /*!< The PHY have the T4 ability. */
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#define PHY_100BASETX_FULLDUPLEX_MASK 0x100U /*!< The PHY has the 100M full duplex ability.*/
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#define PHY_100BASETX_HALFDUPLEX_MASK 0x080U /*!< The PHY has the 100M full duplex ability.*/
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#define PHY_10BASETX_FULLDUPLEX_MASK 0x040U /*!< The PHY has the 10M full duplex ability.*/
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#define PHY_10BASETX_HALFDUPLEX_MASK 0x020U /*!< The PHY has the 10M full duplex ability.*/
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/*! @brief Defines the PHY status. */
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enum _phy_status
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{
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kStatus_PHY_SMIVisitTimeout = MAKE_STATUS(kStatusGroup_PHY, 1), /*!< ENET PHY SMI visit timeout. */
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kStatus_PHY_AutoNegotiateFail = MAKE_STATUS(kStatusGroup_PHY, 2) /*!< ENET PHY AutoNegotiate Fail. */
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};
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/*! @brief Defines the PHY link speed. This is align with the speed for ENET MAC. */
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typedef enum _phy_speed
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{
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kPHY_Speed10M = 0U, /*!< ENET PHY 10M speed. */
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kPHY_Speed100M /*!< ENET PHY 100M speed. */
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} phy_speed_t;
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/*! @brief Defines the PHY link duplex. */
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typedef enum _phy_duplex
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{
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kPHY_HalfDuplex = 0U, /*!< ENET PHY half duplex. */
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kPHY_FullDuplex /*!< ENET PHY full duplex. */
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} phy_duplex_t;
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/*! @brief Defines the PHY loopback mode. */
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typedef enum _phy_loop
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{
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kPHY_LocalLoop = 0U, /*!< ENET PHY local loopback. */
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kPHY_RemoteLoop /*!< ENET PHY remote loopback. */
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} phy_loop_t;
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/*******************************************************************************
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* API
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******************************************************************************/
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#if defined(__cplusplus)
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extern "C" {
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#endif
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/*!
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* @name PHY Driver
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* @{
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*/
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/*!
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* @brief Initializes PHY.
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*
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* This function initialize the SMI interface and initialize PHY.
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* The SMI is the MII management interface between PHY and MAC, which should be
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* firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param srcClock_Hz The module clock frequency - system clock for MII management interface - SMI.
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* @retval kStatus_Success PHY initialize success
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* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
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* @retval kStatus_PHY_AutoNegotiateFail PHY auto negotiate fail
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*/
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status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz);
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/*!
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* @brief PHY Write function. This function write data over the SMI to
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* the specified PHY register. This function is called by all PHY interfaces.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param phyReg The PHY register.
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* @param data The data written to the PHY register.
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* @retval kStatus_Success PHY write success
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* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
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*/
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status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data);
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/*!
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* @brief PHY Read function. This interface read data over the SMI from the
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* specified PHY register. This function is called by all PHY interfaces.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param phyReg The PHY register.
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* @param dataPtr The address to store the data read from the PHY register.
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* @retval kStatus_Success PHY read success
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* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
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*/
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status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr);
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/*!
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* @brief Enables/disables PHY loopback.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param mode The loopback mode to be enabled, please see "phy_loop_t".
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* the two loopback mode should not be both set. when one loopback mode is set
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* the other one should be disabled.
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* @param speed PHY speed for loopback mode.
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* @param enable True to enable, false to disable.
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* @retval kStatus_Success PHY loopback success
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* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
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*/
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status_t PHY_EnableLoopback(ENET_Type *base, uint32_t phyAddr, phy_loop_t mode, phy_speed_t speed, bool enable);
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/*!
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* @brief Gets the PHY link status.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param status The link up or down status of the PHY.
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* - true the link is up.
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* - false the link is down.
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* @retval kStatus_Success PHY get link status success
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* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
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*/
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status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status);
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/*!
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* @brief Gets the PHY link speed and duplex.
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*
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* @param base ENET peripheral base address.
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* @param phyAddr The PHY address.
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* @param speed The address of PHY link speed.
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* @param duplex The link duplex of PHY.
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* @retval kStatus_Success PHY get link speed and duplex success
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* @retval kStatus_PHY_SMIVisitTimeout PHY SMI visit time out
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*/
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status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex);
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/* @} */
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#if defined(__cplusplus)
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}
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#endif
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/*! @}*/
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#endif /* _FSL_PHY_H_ */
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