368 lines
8.4 KiB
C
368 lines
8.4 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020-02-20 bigmagic first version
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*/
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#include <mmu.h>
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#include <stddef.h>
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#include <rthw.h>
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#define TTBR_CNP 1
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typedef unsigned long int uint64_t;
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static unsigned long main_tbl[512 * 20] __attribute__((aligned (4096)));
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#define IS_ALIGNED(x, a) (((x) & ((typeof(x))(a) - 1)) == 0)
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#define PMD_TYPE_SECT (1 << 0)
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#define PMD_TYPE_TABLE (3 << 0)
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#define PTE_TYPE_PAGE (3 << 0)
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#define BITS_PER_VA 39
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/* Granule size of 4KB is being used */
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#define GRANULE_SIZE_SHIFT 12
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#define GRANULE_SIZE (1 << GRANULE_SIZE_SHIFT)
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#define XLAT_ADDR_MASK ((1UL << BITS_PER_VA) - GRANULE_SIZE)
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#define PMD_TYPE_MASK (3 << 0)
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int free_idx = 1;
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void __asm_invalidate_icache_all(void);
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void __asm_flush_dcache_all(void);
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int __asm_flush_l3_cache(void);
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void __asm_flush_dcache_range(unsigned long long start, unsigned long long end);
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void __asm_invalidate_dcache_all(void);
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void __asm_invalidate_icache_all(void);
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void mmu_memset(char *dst, char v, size_t len)
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{
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while (len--)
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{
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*dst++ = v;
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}
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}
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static unsigned long __page_off = 0;
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static unsigned long get_free_page(void)
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{
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__page_off += 512;
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return (unsigned long)(main_tbl + __page_off);
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}
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static inline unsigned int get_sctlr(void)
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{
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unsigned int val;
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asm volatile("mrs %0, sctlr_el1" : "=r" (val) : : "cc");
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return val;
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}
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static inline void set_sctlr(unsigned int val)
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{
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asm volatile("msr sctlr_el1, %0" : : "r" (val) : "cc");
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asm volatile("isb");
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}
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void mmu_init(void)
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{
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unsigned long val64;
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unsigned long val32;
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val64 = 0x007f6eUL;
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__asm__ volatile("msr MAIR_EL1, %0\n dsb sy\n"::"r"(val64));
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__asm__ volatile("mrs %0, MAIR_EL1\n dsb sy\n":"=r"(val64));
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//TCR_EL1
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val32 = (16UL << 0)//48bit
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| (0x0UL << 6)
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| (0x0UL << 7)
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| (0x3UL << 8)
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| (0x3UL << 10)//Inner Shareable
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| (0x2UL << 12)
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| (0x0UL << 14)//4K
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| (0x0UL << 16)
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| (0x0UL << 22)
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| (0x1UL << 23)
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| (0x2UL << 30)
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| (0x1UL << 32)
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| (0x0UL << 35)
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| (0x0UL << 36)
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| (0x0UL << 37)
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| (0x0UL << 38);
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__asm__ volatile("msr TCR_EL1, %0\n"::"r"(val32));
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__asm__ volatile("mrs %0, TCR_EL1\n":"=r"(val32));
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__asm__ volatile("msr TTBR0_EL1, %0\n dsb sy\n"::"r"(main_tbl));
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__asm__ volatile("mrs %0, TTBR0_EL1\n dsb sy\n":"=r"(val64));
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mmu_memset((char *)main_tbl, 0, 4096);
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}
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void mmu_enable(void)
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{
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unsigned long val64;
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unsigned long val32;
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__asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val64));
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val64 &= ~0x1000; //disable I
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__asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\n isb sy\n"::"r"(val64));
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__asm__ volatile("IC IALLUIS\n dsb sy\n isb sy\n");
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__asm__ volatile("tlbi vmalle1\n dsb sy\n isb sy\n");
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//SCTLR_EL1, turn on mmu
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__asm__ volatile("mrs %0, SCTLR_EL1\n":"=r"(val32));
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val32 |= 0x1005; //enable mmu, I C M
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__asm__ volatile("dmb sy\n msr SCTLR_EL1, %0\nisb sy\n"::"r"(val32));
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rt_hw_icache_enable();
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rt_hw_dcache_enable();
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}
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static int map_single_page_2M(unsigned long* lv0_tbl, unsigned long va, unsigned long pa, unsigned long attr)
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{
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int level;
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unsigned long* cur_lv_tbl = lv0_tbl;
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unsigned long page;
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unsigned long off;
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int level_shift = 39;
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if (va & (0x200000UL - 1))
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{
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return MMU_MAP_ERROR_VANOTALIGN;
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}
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if (pa & (0x200000UL - 1))
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{
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return MMU_MAP_ERROR_PANOTALIGN;
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}
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for (level = 0; level < 2; level++)
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{
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off = (va >> level_shift);
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off &= MMU_LEVEL_MASK;
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if ((cur_lv_tbl[off] & 1) == 0)
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{
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page = get_free_page();
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if (!page)
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{
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return MMU_MAP_ERROR_NOPAGE;
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}
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mmu_memset((char *)page, 0, 4096);
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cur_lv_tbl[off] = page | 0x3UL;
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}
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page = cur_lv_tbl[off];
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if (!(page & 0x2))
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{
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//is block! error!
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return MMU_MAP_ERROR_CONFLICT;
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}
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cur_lv_tbl = (unsigned long*)(page & 0x0000fffffffff000UL);
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level_shift -= 9;
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}
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attr &= 0xfff0000000000ffcUL;
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pa |= (attr | 0x1UL); //block
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off = (va >> 21);
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off &= MMU_LEVEL_MASK;
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cur_lv_tbl[off] = pa;
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return 0;
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}
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int armv8_map_2M(unsigned long va, unsigned long pa, int count, unsigned long attr)
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{
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int i;
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int ret;
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if (va & (0x200000 - 1))
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{
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return -1;
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}
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if (pa & (0x200000 - 1))
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{
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return -1;
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}
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for (i = 0; i < count; i++)
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{
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ret = map_single_page_2M((unsigned long *)main_tbl, va, pa, attr);
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va += 0x200000;
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pa += 0x200000;
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if (ret != 0)
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{
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return ret;
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}
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}
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return 0;
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}
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static void set_table(uint64_t *pt, uint64_t *table_addr)
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{
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uint64_t val;
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val = (0x3UL | (uint64_t)table_addr);
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*pt = val;
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}
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void mmu_memset2(unsigned char *dst, char v, int len)
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{
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while (len--)
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{
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*dst++ = v;
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}
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}
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static uint64_t *create_table(void)
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{
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uint64_t *new_table = (uint64_t *)((unsigned char *)&main_tbl[0] + free_idx * 4096); //+ free_idx * GRANULE_SIZE;
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/* Mark all entries as invalid */
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mmu_memset2((unsigned char *)new_table, 0, 4096);
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free_idx++;
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return new_table;
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}
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static int pte_type(uint64_t *pte)
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{
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return *pte & PMD_TYPE_MASK;
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}
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static int level2shift(int level)
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{
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/* Page is 12 bits wide, every level translates 9 bits */
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return (12 + 9 * (3 - level));
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}
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static uint64_t *get_level_table(uint64_t *pte)
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{
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uint64_t *table = (uint64_t *)(*pte & XLAT_ADDR_MASK);
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if (pte_type(pte) != PMD_TYPE_TABLE)
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{
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table = create_table();
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set_table(pte, table);
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}
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return table;
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}
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static void map_region(uint64_t virt, uint64_t phys, uint64_t size, uint64_t attr)
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{
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uint64_t block_size = 0;
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uint64_t block_shift = 0;
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uint64_t *pte;
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uint64_t idx = 0;
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uint64_t addr = 0;
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uint64_t *table = 0;
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int level = 0;
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addr = virt;
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while (size)
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{
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table = &main_tbl[0];
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for (level = 0; level < 4; level++)
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{
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block_shift = level2shift(level);
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idx = addr >> block_shift;
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idx = idx%512;
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block_size = (uint64_t)(1L << block_shift);
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pte = table + idx;
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if (size >= block_size && IS_ALIGNED(addr, block_size))
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{
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attr &= 0xfff0000000000ffcUL;
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if(level != 3)
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{
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*pte = phys | (attr | 0x1UL);
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}
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else
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{
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*pte = phys | (attr | 0x3UL);
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}
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addr += block_size;
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phys += block_size;
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size -= block_size;
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break;
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}
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table = get_level_table(pte);
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}
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}
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}
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void armv8_map(unsigned long va, unsigned long pa, unsigned long size, unsigned long attr)
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{
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map_region(va, pa, size, attr);
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}
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void rt_hw_dcache_enable(void)
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{
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if (!(get_sctlr() & CR_M))
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{
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rt_kprintf("please init mmu!\n");
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}
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else
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{
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set_sctlr(get_sctlr() | CR_C);
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}
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}
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void rt_hw_dcache_flush_all(void)
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{
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int ret;
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__asm_flush_dcache_all();
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ret = __asm_flush_l3_cache();
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if (ret)
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{
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rt_kprintf("flushing dcache returns 0x%x\n", ret);
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}
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else
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{
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rt_kprintf("flushing dcache successfully.\n");
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}
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}
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void rt_hw_dcache_flush_range(unsigned long start_addr, unsigned long size)
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{
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__asm_flush_dcache_range(start_addr, start_addr + size);
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}
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void rt_hw_dcache_invalidate_range(unsigned long start_addr,unsigned long size)
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{
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__asm_flush_dcache_range(start_addr, start_addr + size);
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}
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void rt_hw_dcache_invalidate_all(void)
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{
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__asm_invalidate_dcache_all();
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}
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void rt_hw_dcache_disable(void)
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{
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/* if cache isn't enabled no need to disable */
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if(!(get_sctlr() & CR_C))
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{
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rt_kprintf("need enable cache!\n");
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return;
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}
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set_sctlr(get_sctlr() & ~CR_C);
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}
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//icache
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void rt_hw_icache_enable(void)
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{
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__asm_invalidate_icache_all();
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set_sctlr(get_sctlr() | CR_I);
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}
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void rt_hw_icache_invalidate_all(void)
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{
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__asm_invalidate_icache_all();
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}
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void rt_hw_icache_disable(void)
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{
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set_sctlr(get_sctlr() & ~CR_I);
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}
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