523 lines
12 KiB
C
523 lines
12 KiB
C
/* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the People's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY¡¯S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS¡¯SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY¡¯S TECHNOLOGY.
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <stdio.h>
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#include <stdlib.h>
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#include <interrupt.h>
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#include <hal_clk.h>
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#include <hal_gpio.h>
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#include <hal_reset.h>
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#include <hal_cfg.h>
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#include <script.h>
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#include "common_cir.h"
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#include "platform_cir.h"
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#include "sunxi_hal_cir.h"
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#ifdef CONFIG_DRIVERS_IR_DEBUG
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#define CIR_INFO(fmt, arg...) printf("%s()%d " fmt, __func__, __LINE__, ##arg)
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#else
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#define CIR_INFO(fmt, arg...) do{}while(0);
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#endif
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#define CIR_ERR(fmt, arg...) printf("%s()%d " fmt, __func__, __LINE__, ##arg)
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static uint32_t base[CIR_MASTER_NUM] = {
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SUNXI_IRADC_PBASE,
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};
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static uint32_t irq[CIR_MASTER_NUM] = {
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SUNXI_IRQ_IRADC,
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};
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static cir_gpio_t pin[CIR_MASTER_NUM] = {
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{GPIOB(7), 5, 0},
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};
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sunxi_cir_t sunxi_cir[CIR_MASTER_NUM];
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void sunxi_cir_callback_register(cir_port_t port, cir_callback_t callback)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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cir->callback = callback;
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}
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static irqreturn_t sunxi_cir_handler(int irq, void *dev)
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{
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sunxi_cir_t *cir = (sunxi_cir_t *)dev;
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uint32_t int_flag, count;
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uint32_t reg_data, i = 0;
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int_flag = readl(cir->base + CIR_RXSTA);
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writel(int_flag, cir->base + CIR_RXSTA);
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count = (int_flag & RAC) >> RAC_OFFSET;
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for(i = 0; i < count; i++)
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{
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reg_data = readl(cir->base + CIR_RXFIFO);
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if (cir->callback)
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cir->callback(cir->port, RA, reg_data);
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}
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if ((int_flag & ROI) && cir->callback) {
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cir->callback(cir->port, ROI, 0);
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}
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if ((int_flag & RPE) && cir->callback)
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{
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cir->callback(cir->port, RA, 0);
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cir->callback(cir->port, RPE, 0);
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}
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return 0;
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}
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void sunxi_cir_mode_enable(cir_port_t port, uint8_t enable)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val;
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if (!cir->status)
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return ;
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reg_val = readl(cir->base + CIR_CTRL);
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if (enable)
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reg_val |= CIR_ENABLE;
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else
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reg_val &= ~CIR_ENABLE;
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writel(reg_val, cir->base + CIR_CTRL);
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}
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void sunxi_cir_mode_config(cir_port_t port, cir_mode_t mode)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val;
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if (!cir->status)
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return ;
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reg_val = readl(cir->base + CIR_CTRL);
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reg_val &= ~CIR_MODE;
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reg_val |= (mode << CIR_MODE_OFFSET);
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writel(reg_val, cir->base + CIR_CTRL);
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}
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void sunxi_cir_sample_clock_select(cir_port_t port, cir_sample_clock_t div)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val = 0;
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if (!cir->status)
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return ;
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reg_val = readl(cir->base + CIR_CONFIG);
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if (div == CIR_CLK) {
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reg_val &= ~SCS;
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reg_val |= SCS2;
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} else {
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reg_val &= ~SCS2;
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reg_val |= div;
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}
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writel(reg_val, cir->base + CIR_CONFIG);
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}
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void sunxi_cir_sample_noise_threshold(cir_port_t port, int8_t threshold)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val = 0;
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if (!cir->status || threshold > 0x3f)
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return ;
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reg_val = readl(cir->base + CIR_CONFIG);
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reg_val &= ~NTHR;
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reg_val |= (threshold << NTHR_OFFSET);
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writel(reg_val, cir->base + CIR_CONFIG);
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}
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void sunxi_cir_sample_idle_threshold(cir_port_t port, int8_t threshold)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val = 0;
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if (!cir->status || threshold > 0x3f)
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return ;
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reg_val = readl(cir->base + CIR_CONFIG);
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reg_val &= ~ITHR;
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reg_val |= (threshold << ITHR_OFFSET);
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writel(reg_val, cir->base + CIR_CONFIG);
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}
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void sunxi_cir_sample_active_threshold(cir_port_t port, int8_t threshold)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val = 0;
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if (!cir->status || threshold > 0x3f)
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return ;
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reg_val = readl(cir->base + CIR_CONFIG);
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reg_val &= ~ATHR;
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reg_val |= (threshold << ATHR_OFFSET);
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writel(reg_val, cir->base + CIR_CONFIG);
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}
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void sunxi_cir_sample_active_thrctrl(cir_port_t port, int8_t enable)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val = 0;
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if (!cir->status)
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return ;
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reg_val = readl(cir->base + CIR_CONFIG);
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if (enable)
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reg_val |= ATHC;
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else
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reg_val &= ~ATHC;
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writel(reg_val, cir->base + CIR_CONFIG);
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}
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void sunxi_cir_fifo_level(cir_port_t port, int8_t size)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val = 0;
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if (!cir->status || size > 0x3f + 1)
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return ;
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reg_val = readl(cir->base + CIR_RXINT);
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reg_val &= ~RAL;
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reg_val |= ((size -1) << RAL_OFFSET);
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writel(reg_val, cir->base + CIR_RXINT);
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}
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void sunxi_cir_irq_enable(cir_port_t port, int enable)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val = 0;
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if (!cir->status)
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return ;
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reg_val = readl(cir->base + CIR_RXINT);
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reg_val &= ~IRQ_MASK;
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enable &= IRQ_MASK;
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reg_val |= enable;
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writel(reg_val, cir->base + CIR_RXINT);
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}
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void sunxi_cir_irq_disable(cir_port_t port)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val = 0;
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if (!cir->status)
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return ;
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reg_val = readl(cir->base + CIR_RXINT);
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reg_val &= ~IRQ_MASK;
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writel(reg_val, cir->base + CIR_RXINT);
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}
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void sunxi_cir_signal_invert(cir_port_t port, uint8_t invert)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val = 0;
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if (!cir->status)
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return ;
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reg_val = readl(cir->base + CIR_RXCTRL);
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if (invert)
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reg_val |= RPPI;
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else
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reg_val &= ~RPPI;
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writel(reg_val, cir->base + CIR_RXCTRL);
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}
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void sunxi_cir_module_enable(cir_port_t port, int8_t enable)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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int reg_val = 0;
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if (!cir->status)
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return ;
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reg_val = readl(cir->base + CIR_CTRL);
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if (enable)
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reg_val |= (GEN | RXEN);
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else
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reg_val &= ~(GEN | RXEN);
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writel(reg_val, cir->base + CIR_CTRL);
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}
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static int sunxi_cir_gpio_init(sunxi_cir_t *cir)
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{
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user_gpio_set_t irpin = {0};
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cir_gpio_t pin_cir;
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Hal_Cfg_GetKeyValue("cir", "cir_pin", (int32_t *)&irpin, (sizeof(user_gpio_set_t) + 3) / sizeof(int));
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pin_cir.gpio = (irpin.port - 1) * PINS_PER_BANK + irpin.port_num;
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pin_cir.enable_mux = irpin.mul_sel;
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pin_cir.disable_mux = 0;
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return hal_gpio_pinmux_set_function(pin_cir.gpio, pin_cir.enable_mux);
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}
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static int sunxi_cir_gpio_exit(sunxi_cir_t *cir)
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{
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cir_gpio_t *cir_pin = cir->pin;
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return hal_gpio_pinmux_set_function(cir_pin->gpio, cir_pin->disable_mux);
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}
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#if defined(CONFIG_ARCH_SUN20IW1)
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static int sunxi_cir_clk_init(sunxi_cir_t *cir)
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{
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int ret = 0;
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cir->cir_clk_type_R = HAL_SUNXI_R_CCU;
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cir->cir_clk_type_FIXED = HAL_SUNXI_FIXED_CCU;
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cir->m_clk_id = CLK_R_APB0_IRRX;
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cir->p_clk_id = CLK_SRC_HOSC24M;
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cir->b_clk_id = CLK_R_APB0_BUS_IRRX;
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cir->mclk = hal_clock_get(cir->cir_clk_type_R, cir->m_clk_id);
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if (hal_clock_enable(cir->mclk)) {
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CIR_ERR("cir mclk enabled failed\n");
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return -1;
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}
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cir->pclk = hal_clock_get(cir->cir_clk_type_FIXED, cir->p_clk_id);
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if (hal_clock_enable(cir->pclk)) {
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CIR_ERR("cir pclk enabled failed\n");
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return -1;
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}
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cir->bclk = hal_clock_get(cir->cir_clk_type_R, cir->b_clk_id);
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if (hal_clock_enable(cir->bclk)) {
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CIR_ERR("cir bclk enabled failed\n");
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return -1;
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}
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ret = hal_clk_set_parent(cir->mclk, cir->pclk);
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if (ret) {
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printf("hal_clk_set_parent failed\n");
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return -1;
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}
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hal_reset_type_t cir_reset_type = HAL_SUNXI_R_RESET;
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hal_reset_id_t cir_reset_id = RST_R_APB0_BUS_IRRX;
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cir->cir_reset = hal_reset_control_get(cir_reset_type, cir_reset_id);
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if (hal_reset_control_deassert(cir->cir_reset)) {
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CIR_ERR("cir reset deassert failed\n");
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return -1;
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}
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return 0;
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}
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#else
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static int sunxi_cir_clk_init(sunxi_cir_t *cir)
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{
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int ret = 0;
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int TEST_CLK_TYPE = 1;
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int TEST_CLK_DATA = 1;
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int TEST_RESET_TYPE = 1;
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int TEST_RESET_DATA = 1;
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cir->test_clk_type = TEST_CLK_TYPE;
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cir->test_clk_id = TEST_CLK_DATA;
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cir->test_clk = hal_clock_get(cir->test_clk_type, cir->test_clk_id);
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if (hal_clock_enable(cir->test_clk)) {
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CIR_ERR("cir TEST_CLK enabled failed\n");
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return -1;
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}
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hal_reset_type_t cir_reset_type = TEST_RESET_TYPE;
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hal_reset_id_t cir_reset_id = TEST_RESET_DATA;
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cir->cir_reset = hal_reset_control_get(cir_reset_type, cir_reset_id);
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if (hal_reset_control_deassert(cir->cir_reset)) {
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CIR_ERR("cir reset deassert failed\n");
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return -1;
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}
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return 0;
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}
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#endif
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#if defined(CONFIG_ARCH_SUN20IW1)
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static int sunxi_cir_clk_exit(sunxi_cir_t *cir)
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{
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hal_clock_disable(cir->bclk);
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hal_clock_put(cir->bclk);
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hal_clock_disable(cir->pclk);
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hal_clock_put(cir->pclk);
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hal_clock_disable(cir->mclk);
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hal_clock_put(cir->mclk);
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hal_reset_control_assert(cir->cir_reset);
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hal_reset_control_put(cir->cir_reset);
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return 0;
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}
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#else
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static int sunxi_cir_clk_exit(sunxi_cir_t *cir)
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{
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hal_clock_disable(cir->test_clk);
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hal_clock_put(cir->test_clk);
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hal_reset_control_assert(cir->cir_reset);
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hal_reset_control_put(cir->cir_reset);
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return 0;
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}
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#endif
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static cir_status_t sunxi_cir_hw_init(sunxi_cir_t *cir)
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{
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if (sunxi_cir_clk_init(cir))
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return CIR_CLK_ERR;
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if (sunxi_cir_gpio_init(cir))
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return CIR_PIN_ERR;
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if (request_irq(cir->irq, sunxi_cir_handler, 0, "cir-irq", cir)) {
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printf("cir request irq err\n");
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return CIR_IRQ_ERR;
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}
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enable_irq(cir->irq);
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return CIR_OK;
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}
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static void sunxi_cir_hw_exit(sunxi_cir_t *cir)
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{
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disable_irq(cir->irq);
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free_irq(cir->irq, cir);
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sunxi_cir_gpio_exit(cir);
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sunxi_cir_clk_exit(cir);
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}
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#ifdef CONFIG_STANDBY
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void sunxi_cir_suspend(cir_port_t port)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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disable_irq(cir->irq);
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hal_clock_disable(cir->bclk);
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hal_clock_disable(cir->mclk);
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sunxi_cir_gpio_exit(cir);
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return;
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}
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void sunxi_cir_resume(cir_port_t port)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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sunxi_cir_gpio_init(cir);
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sunxi_cir_clk_init(cir);
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enable_irq(cir->irq);
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return;
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}
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#endif
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cir_status_t sunxi_cir_init(cir_port_t port)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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cir_status_t ret = 0;
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cir->port = port;
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cir->base = base[port];
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cir->irq = irq[port];
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cir->pin = &pin[port];
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cir->status = 1;
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ret = sunxi_cir_hw_init(cir);
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if (ret)
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{
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CIR_ERR("cir[%d] hardware init error, ret:%d\n", port, ret);
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return ret;
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}
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return ret;
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}
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void sunxi_cir_deinit(cir_port_t port)
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{
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sunxi_cir_t *cir = &sunxi_cir[port];
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cir->status = 0;
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sunxi_cir_hw_exit(cir);
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}
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