134 lines
5.3 KiB
C
134 lines
5.3 KiB
C
////////////////////////////////////////////////////////////////////////////////
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/// @file reg_wwdg.h
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/// @author AE TEAM
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/// @brief THIS FILE CONTAINS ALL THE FUNCTIONS PROTOTYPES FOR THE SERIES OF
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/// MM32 FIRMWARE LIBRARY.
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////////////////////////////////////////////////////////////////////////////////
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/// @attention
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///
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/// THE EXISTING FIRMWARE IS ONLY FOR REFERENCE, WHICH IS DESIGNED TO PROVIDE
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/// CUSTOMERS WITH CODING INFORMATION ABOUT THEIR PRODUCTS SO THEY CAN SAVE
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/// TIME. THEREFORE, MINDMOTION SHALL NOT BE LIABLE FOR ANY DIRECT, INDIRECT OR
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/// CONSEQUENTIAL DAMAGES ABOUT ANY CLAIMS ARISING OUT OF THE CONTENT OF SUCH
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/// HARDWARE AND/OR THE USE OF THE CODING INFORMATION CONTAINED HEREIN IN
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/// CONNECTION WITH PRODUCTS MADE BY CUSTOMERS.
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///
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/// <H2><CENTER>© COPYRIGHT MINDMOTION </CENTER></H2>
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////////////////////////////////////////////////////////////////////////////////
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// Define to prevent recursive inclusion
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#ifndef __REG_WWDG_H
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#define __REG_WWDG_H
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// Files includes
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#include <stdint.h>
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#include <stdbool.h>
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#include "types.h"
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#if defined ( __CC_ARM )
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#pragma anon_unions
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#endif
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////////////////////////////////////////////////////////////////////////////////
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/// @brief WWDG Base Address Definition
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////////////////////////////////////////////////////////////////////////////////
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#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00) ///< Base Address: 0x40002C00
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////////////////////////////////////////////////////////////////////////////////
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/// @brief WWDG Register Structure Definition
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////////////////////////////////////////////////////////////////////////////////
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#undef USENCOMBINEREGISTER
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#undef USENNEWREGISTER
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#undef USENOLDREGISTER
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#define USENCOMBINEREGISTER
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#ifdef USENCOMBINEREGISTER
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typedef struct {
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__IO u32 CR; ///< Control register offset: 0x00
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union {
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__IO u32 CFGR; ///< Configuration register offset: 0x04
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__IO u32 CFR;
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};
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__IO u32 SR; ///< Status register offset: 0x08
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} WWDG_TypeDef;
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#endif
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#ifdef USENNEWREGISTER
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typedef struct {
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__IO u32 CR; ///< Control register offset: 0x00
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__IO u32 CFGR; ///< Configuration register offset: 0x04
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__IO u32 SR; ///< Status register offset: 0x08
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} WWDG_TypeDef;
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#endif
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#ifdef USENOLDREGISTER
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typedef struct {
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__IO u32 CR;
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__IO u32 CFR;
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__IO u32 SR;
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} WWDG_TypeDef;
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#endif
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////////////////////////////////////////////////////////////////////////////////
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/// @brief WWDG type pointer Definition
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////////////////////////////////////////////////////////////////////////////////
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#define WWDG ((WWDG_TypeDef*) WWDG_BASE)
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////////////////////////////////////////////////////////////////////////////////
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/// @brief WWDG_CR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define WWDG_CR_CNT_Pos (0)
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#define WWDG_CR_CNT (0x7FU << WWDG_CR_CNT_Pos) ///< T[6:0] bits (7-Bit counter (MSB to LSB))
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#define WWDG_CR_WDGA_Pos (7)
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#define WWDG_CR_WDGA (0x01U << WWDG_CR_WDGA_Pos) ///< Activation bit
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////////////////////////////////////////////////////////////////////////////////
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/// @brief WWDG_CFR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define WWDG_CFGR_WINDOW_Pos (0)
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#define WWDG_CFGR_WINDOW (0x7FU << WWDG_CFGR_WINDOW_Pos) ///< W[6:0] bits (7-bit window value)
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#define WWDG_CFGR_WDGTB_Pos (7)
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#define WWDG_CFGR_WDGTB (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base)
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#define WWDG_CFGR_WDGTB_1 (0x00U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /1)
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#define WWDG_CFGR_WDGTB_2 (0x01U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /2)
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#define WWDG_CFGR_WDGTB_4 (0x02U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /4)
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#define WWDG_CFGR_WDGTB_8 (0x03U << WWDG_CFGR_WDGTB_Pos) ///< WDGTB[1:0] bits (Timer Base /8)
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#define WWDG_CFGR_EWI_Pos (9)
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#define WWDG_CFGR_EWI (0x01U << WWDG_CFGR_EWI_Pos) ///< Early Wakeup Interrupt
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////////////////////////////////////////////////////////////////////////////////
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/// @brief WWDG_SR Register Bit Definition
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////////////////////////////////////////////////////////////////////////////////
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#define WWDG_SR_EWIF_Pos (0)
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#define WWDG_SR_EWIF (0x01U << WWDG_SR_EWIF_Pos) ///< Early Wakeup Interrupt Flag
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/// @}
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/// @}
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/// @}
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////////////////////////////////////////////////////////////////////////////////
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#endif
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////////////////////////////////////////////////////////////////////////////////
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