115 lines
5.8 KiB
Markdown
115 lines
5.8 KiB
Markdown
# STM32H743-Nucleo BSP Introduction
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[中文](README_zh.md)
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## MCU: STM32H743ZI @480MHz, 2MB FLASH, 1MB RAM
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STM32H742xI/G and STM32H743xI/G devices are based on the high-performance Arm® Cortex®-M7 32-bit RISC core operating at up to 480 MHz. The Cortex® -M7 core features a floating point unit (FPU) which supports Arm® double-precision (IEEE 754 compliant) and single-precision data-processing instructions and data types. STM32H742xI/G and STM32H743xI/G devices support a full set of DSP instructions and a memory protection unit (MPU) to enhance application security.
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STM32H742xI/G and STM32H743xI/G devices incorporate high-speed embedded memories with a dual-bank Flash memory of up to 2 Mbytes, up to 1 Mbyte of RAM (including 192 Kbytes of TCM RAM, up to 864 Kbytes of user SRAM and 4 Kbytes of backup SRAM), as well as an extensive range of enhanced I/Os and peripherals connected to APB buses, AHB buses, 2x32-bit multi-AHB bus matrix and a multi layer AXI interconnect supporting internal and external memory access.
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#### KEY FEATURES
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- Core
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- 32-bit Arm® Cortex®-M7 core with double-precision FPU and L1 cache: 16 Kbytes of data and 16 Kbytes of instruction cache; frequency up to 480 MHz, MPU, 1027 DMIPS/ 2.14 DMIPS/MHz (Dhrystone 2.1), and DSP instructions
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- Memories
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- Up to 2 Mbytes of Flash memory with read-while-write support
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- Up to 1 Mbyte of RAM: 192 Kbytes of TCM RAM (inc. 64 Kbytes of ITCM RAM + 128 Kbytes of DTCM RAM for time critical routines), Up to 864 Kbytes of user SRAM, and 4 Kbytes of SRAM in Backup domain
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- Dual mode Quad-SPI memory interface running up to 133 MHz
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- Flexible external memory controller with up to 32-bit data bus: SRAM, PSRAM, SDRAM/LPSDR SDRAM, NOR/NAND Flash memory clocked up to 100 MHz in Synchronous mode
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- CRC calculation unit
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- Security
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- ROP, PC-ROP, active tamper
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- General-purpose input/outputs
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- Up to 168 I/O ports with interrupt capability
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- Reset and power management
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- 3 separate power domains which can be independently clock-gated or switched off:
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- D1: high-performance capabilities
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- D2: communication peripherals and timers
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- D3: reset/clock control/power management
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- 1.62 to 3.6 V application supply and I/Os
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- POR, PDR, PVD and BOR
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- Dedicated USB power embedding a 3.3 V internal regulator to supply the internal PHYs
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- Embedded regulator (LDO) with configurable scalable output to supply the digital circuitry
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- Voltage scaling in Run and Stop mode (6 configurable ranges)
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- Backup regulator (~0.9 V)
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- Voltage reference for analog peripheral/VREF+
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- Low-power modes: Sleep, Stop, Standby and VBAT supporting battery charging
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- Low-power consumption
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- VBAT battery operating mode with charging capability
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- CPU and domain power state monitoring pins
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- 2.95 μA in Standby mode (Backup SRAM OFF, RTC/LSE ON)
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- Clock management
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- Internal oscillators: 64 MHz HSI, 48 MHz HSI48, 4 MHz CSI, 32 kHz LSI
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- External oscillators: 4-48 MHz HSE, 32.768 kHz LSE
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- 3× PLLs (1 for the system clock, 2 for kernel clocks) with Fractional mode
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- Interconnect matrix
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- 4 DMA controllers to unload the CPU
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- 1× high-speed master direct memory access controller (MDMA) with linked list support
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- 2× dual-port DMAs with FIFO
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- 1× basic DMA with request router capabilities
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- Up to 35 communication peripherals
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- 4× I2Cs FM+ interfaces (SMBus/PMBus)
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- 4× USARTs/4x UARTs (ISO7816 interface, LIN, IrDA, up to 12.5 Mbit/s) and 1x LPUART
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- 6× SPIs, 3 with muxed duplex I2S audio class accuracy via internal audio PLL or external clock, 1x I2S in LP domain (up to 150 MHz)
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- 4x SAIs (serial audio interface)
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- SPDIFRX interface
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- SWPMI single-wire protocol master I/F
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- MDIO Slave interface
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- 2× SD/SDIO/MMC interfaces (up to 125 MHz)
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- 2× CAN controllers: 2 with CAN FD, 1 with time-triggered CAN (TT-CAN)
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- 2× USB OTG interfaces (1FS, 1HS/FS) crystal-less solution with LPM and BCD
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- Ethernet MAC interface with DMA controller
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- HDMI-CEC
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- 8- to 14-bit camera interface (up to 80 MHz)
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- 11 analog peripherals
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- 3× ADCs with 16-bit max. resolution (up to 36 channels, up to 3.6 MSPS)
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- 1× temperature sensor
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- 2× 12-bit D/A converters (1 MHz)
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- 2× ultra-low-power comparators
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- 2× operational amplifiers (7.3 MHz bandwidth)
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- 1× digital filters for sigma delta modulator (DFSDM) with 8 channels/4 filters
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- Graphics
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- LCD-TFT controller up to XGA resolution
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- Chrom-ART graphical hardware Accelerator™ (DMA2D) to reduce CPU load
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- Hardware JPEG Codec
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- Up to 22 timers and watchdogs
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- 1× high-resolution timer (2.1 ns max resolution)
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- 2× 32-bit timers with up to 4 IC/OC/PWM or pulse counter and quadrature (incremental) encoder input (up to 240 MHz)
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- 2× 16-bit advanced motor control timers (up to 240 MHz)
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- 10× 16-bit general-purpose timers (up to 240 MHz)
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- 5× 16-bit low-power timers (up to 240 MHz)
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- 2× watchdogs (independent and window)
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- 1× SysTick timer
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- RTC with sub-second accuracy and hardware calendar
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- Debug mode
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- SWD & JTAG interfaces
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- 4-Kbyte Embedded Trace Buffer
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- True random number generators (3 oscillators each)
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- 96-bit unique ID
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## Read more
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| Documents | Description |
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| :----------------------------------------------------------: | :----------------------------------------------------------: |
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| [STM32_Nucleo-144_BSP_Introduction](../docs/STM32_Nucleo-144_BSP_Introduction.md) | How to run RT-Thread on STM32 Nucleo-144 boards (**Must-Read**) |
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| [STM32H743ZI ST Official Website](https://www.st.com/en/microcontrollers-microprocessors/stm32h743zi.html#documentation) | STM32H743ZI datasheet and other resources |
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## Maintained By
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[tyustli](https://github.com/tyustli)
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## Translated By
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Meco Man @ RT-Thread Community
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> jiantingman@foxmail.com
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>
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> https://github.com/mysterywolf |