261 lines
8.3 KiB
C
261 lines
8.3 KiB
C
/*
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* Copyright 2017, 2019-2020 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_mipi_csi2rx.h"
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/*
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* The MIPI CSI2 peripheral can not work independently, some other control and
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* status registers must be used together. There are two integration methods
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* with these registers.
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*
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* 1. The registers are collected in one dedicated module: CSR.
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* 2. The registers are scattered in multiple modules.
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*
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*/
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.mipi_csi2rx"
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#endif
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#if (defined(FSL_FEATURE_CSI2RX_CSR_OFFSET) && FSL_FEATURE_CSI2RX_CSR_OFFSET)
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#define CSI2RX_GET_CSR(csi_base) (MIPI_CSI_CSR_Type *)((uint32_t)(csi_base) - (uint32_t)FSL_FEATURE_CSI2RX_CSR_OFFSET)
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#define MIPI_CSI2RX_HAS_CSR 1
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#else
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#define MIPI_CSI2RX_HAS_CSR 0
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#include "fsl_soc_mipi_csi2rx.h"
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#endif
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#if MIPI_CSI2RX_HAS_CSR
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/* Macro Map */
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#ifndef MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CTL_CLK_OFF_MASK
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#define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CTL_CLK_OFF_MASK \
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MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL(2U)
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#define MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_SW_RESET_MASK \
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MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CONTROLLER_CLOCK_RESET_CONTROL(1U)
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#endif
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#ifndef MIPI_CSI_CSR_PHY_CTRL_CONTI_CLK_MODE_MASK
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#define MIPI_CSI_CSR_PHY_CTRL_CONTI_CLK_MODE_MASK MIPI_CSI_CSR_PHY_CTRL_CONT_CLK_MODE_MASK
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#endif
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#ifndef MIPI_CSI_CSR_PHY_CTRL_PRG_RXHS_SETTLE
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#define MIPI_CSI_CSR_PHY_CTRL_PRG_RXHS_SETTLE(x) MIPI_CSI_CSR_PHY_CTRL_S_PRG_RXHS_SETTLE(x)
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#endif
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Returns an instance number given a base address.
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*
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* If an invalid base address is passed, debug builds will assert. Release builds will just return
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* instance number 0.
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*
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* @param base The CSI2RX peripheral base address.
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* @return CSI2RX instance number starting from 0.
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*/
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uint32_t CSI2RX_GetInstance(MIPI_CSI2RX_Type *base);
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#if MIPI_CSI2RX_HAS_CSR
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/*!
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* @brief Perform CSI2RX resource reset in system level.
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*
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* @param base The CSI2RX peripheral base address.
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* @param reset Pass in true to set to reset state, false to release reset.
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*/
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static void MIPI_CSI2RX_SoftwareReset(MIPI_CSI2RX_Type *base, bool reset);
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/*!
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* @brief Initialize the CSI2RX interface.
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*
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* @param base The CSI2RX peripheral base address.
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* @param tHsSettle_EscClk t-HS_SETTLE in esc clock period.
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*/
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static void MIPI_CSI2RX_InitInterface(MIPI_CSI2RX_Type *base, uint8_t tHsSettle_EscClk);
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/*!
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* @brief Deinitialize the CSI2RX interface.
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*
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* @param base The CSI2RX peripheral base address.
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*/
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static void MIPI_CSI2RX_DeinitInterface(MIPI_CSI2RX_Type *base);
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#endif
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! @brief Array to map MIPI CSI2RX instance number to base address. */
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static const uint32_t s_csi2rxBaseAddrs[] = MIPI_CSI2RX_BASE_ADDRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to MPI CSI2RX clocks for each instance. */
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static const clock_ip_name_t s_csi2rxClocks[] = MIPI_CSI2RX_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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#if MIPI_CSI2RX_HAS_CSR
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static void MIPI_CSI2RX_SoftwareReset(MIPI_CSI2RX_Type *base, bool reset)
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{
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MIPI_CSI_CSR_Type *csr = CSI2RX_GET_CSR(base);
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if (reset)
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{
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csr->CONTROLLER_CLOCK_RESET_CONTROL = MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CTL_CLK_OFF_MASK;
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}
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else
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{
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csr->CONTROLLER_CLOCK_RESET_CONTROL = MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CTL_CLK_OFF_MASK;
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csr->CONTROLLER_CLOCK_RESET_CONTROL = MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_SW_RESET_MASK |
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MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CTL_CLK_OFF_MASK;
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}
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}
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static void MIPI_CSI2RX_InitInterface(MIPI_CSI2RX_Type *base, uint8_t tHsSettle_EscClk)
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{
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MIPI_CSI_CSR_Type *csr = CSI2RX_GET_CSR(base);
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/* Pixel link control */
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csr->PLM_CTRL = 0;
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/* Configure the PHY. */
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csr->PHY_CTRL = MIPI_CSI_CSR_PHY_CTRL_RX_ENABLE_MASK | /* Enable RX. */
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MIPI_CSI_CSR_PHY_CTRL_AUTO_PD_EN_MASK | /* Auto power down unused lanes. */
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MIPI_CSI_CSR_PHY_CTRL_PD_MASK | MIPI_CSI_CSR_PHY_CTRL_DDRCLK_EN_MASK | /* Enable the DDR clock. */
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MIPI_CSI_CSR_PHY_CTRL_CONTI_CLK_MODE_MASK | /* Continue clock. */
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MIPI_CSI_CSR_PHY_CTRL_RTERM_SEL_MASK | /* LPRX voltage level enable HS termination */
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MIPI_CSI_CSR_PHY_CTRL_PRG_RXHS_SETTLE(tHsSettle_EscClk - 1UL); /* T(HS-SETTLE) */
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/* Don't support interlace currently. */
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csr->VC_INTERLACED = 0U;
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/* Don't mask any data type */
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#if defined(MIPI_CSI_CSR_DATA_TYPE_DISABLE_BF_DATA_TYPE_DISABLE_MASK)
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csr->DATA_TYPE_DISABLE_BF = 0U;
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#else
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csr->DATA_TYPE_DIS = 0U;
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#endif
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/* VC fence. */
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#if defined(MIPI_CSI_CSR_STREAM_FENCING_CONTROL_STREAM_FENCING_CONTROL_MASK)
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csr->STREAM_FENCING_CONTROL = 0U;
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#else
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csr->STREAM_FENCING_CTRL = 0U;
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#endif
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#if defined(MIPI_CSI_CSR_PLM_CTRL_PL_CLOCK_RUNNING_MASK)
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/* Wait for PL clock active. */
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while (0UL != (csr->PLM_CTRL & MIPI_CSI_CSR_PLM_CTRL_PL_CLOCK_RUNNING_MASK))
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{
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}
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#endif
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/* Enable pixel link master. */
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csr->PLM_CTRL |= (MIPI_CSI_CSR_PLM_CTRL_ENABLE_MASK | MIPI_CSI_CSR_PLM_CTRL_VALID_OVERRIDE_MASK);
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/* Power up PHY. */
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csr->PHY_CTRL &= ~MIPI_CSI_CSR_PHY_CTRL_PD_MASK;
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/* Start clock. */
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csr->CONTROLLER_CLOCK_RESET_CONTROL = MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_SW_RESET_MASK;
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}
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static void MIPI_CSI2RX_DeinitInterface(MIPI_CSI2RX_Type *base)
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{
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MIPI_CSI_CSR_Type *csr = CSI2RX_GET_CSR(base);
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/* Disable the PHY. */
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csr->PHY_CTRL = 0;
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/* Disable the pixel link master. */
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csr->PLM_CTRL = 0;
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/* Stop the clock and assert reset. */
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csr->CONTROLLER_CLOCK_RESET_CONTROL = MIPI_CSI_CSR_CONTROLLER_CLOCK_RESET_CONTROL_CTL_CLK_OFF_MASK;
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}
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#endif
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uint32_t CSI2RX_GetInstance(MIPI_CSI2RX_Type *base)
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{
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uint32_t i;
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for (i = 0U; i < ARRAY_SIZE(s_csi2rxBaseAddrs); i++)
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{
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if ((uint32_t)base == s_csi2rxBaseAddrs[i])
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{
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return i;
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}
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}
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assert(false);
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return 0;
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}
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/*!
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* brief Enables and configures the CSI2RX peripheral module.
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*
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* param base CSI2RX peripheral address.
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* param config CSI2RX module configuration structure.
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*/
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void CSI2RX_Init(MIPI_CSI2RX_Type *base, const csi2rx_config_t *config)
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{
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assert(NULL != config);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* un-gate clock */
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(void)CLOCK_EnableClock(s_csi2rxClocks[CSI2RX_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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MIPI_CSI2RX_SoftwareReset(base, false);
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CSI2RX_REG_CFG_NUM_LANES(base) = config->laneNum - 1UL;
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CSI2RX_REG_CFG_DISABLE_DATA_LANES(base) =
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MIPI_CSI2RX_CSI2RX_CFG_NUM_LANES_csi2rx_cfg_num_lanes_MASK & ~((1UL << (uint32_t)config->laneNum) - 1UL);
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/* Don't disable data types. */
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CSI2RX_REG_CFG_DISABLE_PAYLOAD_0(base) = 0;
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CSI2RX_REG_CFG_DISABLE_PAYLOAD_1(base) = 0;
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/* Disable all interrupts. */
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CSI2RX_REG_IRQ_MASK(base) = MIPI_CSI2RX_CSI2RX_IRQ_MASK_csi2rx_irq_mask_MASK;
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MIPI_CSI2RX_InitInterface(base, config->tHsSettle_EscClk);
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}
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/*!
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* brief Disables the CSI2RX peripheral module.
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*
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* param base CSI2RX peripheral address.
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*/
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void CSI2RX_Deinit(MIPI_CSI2RX_Type *base)
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{
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MIPI_CSI2RX_DeinitInterface(base);
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MIPI_CSI2RX_SoftwareReset(base, true);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* gate clock */
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(void)CLOCK_DisableClock(s_csi2rxClocks[CSI2RX_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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