519 lines
17 KiB
C
519 lines
17 KiB
C
/*
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* Copyright 2020-2021 NXP
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* All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_dcdc.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.dcdc_soc"
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#endif
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* brief Gets instance number for DCDC module.
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*
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* param base DCDC peripheral base address
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*/
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static uint32_t DCDC_GetInstance(DCDC_Type *base);
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/*!
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* brief Converts the byte array to word.
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*
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* param ptrArray Pointer to the byte array.
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* return The converted result.
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*/
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static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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/*! brief Pointers to DCDC bases for each instance. */
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static DCDC_Type *const s_dcdcBases[] = DCDC_BASE_PTRS;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! brief Pointers to DCDC clocks for each instance. */
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static const clock_ip_name_t s_dcdcClocks[] = DCDC_CLOCKS;
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* CodDCDC_GetstatusFlagse
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******************************************************************************/
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static uint32_t DCDC_GetInstance(DCDC_Type *base)
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{
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uint32_t instance;
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/* Find the instance index from base address mappings. */
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for (instance = 0; instance < ARRAY_SIZE(s_dcdcBases); instance++)
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{
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if (s_dcdcBases[instance] == base)
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{
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break;
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}
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}
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assert(instance < ARRAY_SIZE(s_dcdcBases));
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return instance;
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}
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static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray)
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{
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assert(ptrArray != NULL);
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uint32_t temp32 = 0UL;
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uint32_t index;
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for (index = 0U; index < 4U; index++)
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{
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temp32 |= (uint32_t)ptrArray[index] << ((index % 4UL) * 8UL);
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}
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return temp32;
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}
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/*!
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* brief Initializes the basic resource of DCDC module, such as control mode, etc.
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*
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* param base DCDC peripheral base address.
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* param config Pointer to the configuration structure.
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*/
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void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config)
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{
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Enable the clock. */
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CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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uint32_t tmp32 = base->CTRL0;
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tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode);
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if (config->enableDcdcTimeout)
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{
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tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK;
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}
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if (config->enableSwitchingConverterOutput)
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{
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tmp32 |= DCDC_CTRL0_DIG_EN_MASK;
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}
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tmp32 |= DCDC_CTRL0_ENABLE_MASK;
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base->CTRL0 = tmp32;
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}
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/*!
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* brief De-initializes the DCDC module.
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*
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* param base DCDC peripheral base address.
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*/
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void DCDC_Deinit(DCDC_Type *base)
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{
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/* Disables DCDC. */
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base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK;
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Disable the clock. */
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CLOCK_DisableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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}
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/*!
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* brief Gets the default setting for DCDC, such as control mode, etc.
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*
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* This function initializes the user configuration structure to a default value. The default values are:
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* code
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* config->controlMode = kDCDC_StaticControl;
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* config->trimInputMode = kDCDC_SampleTrimInput;
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* config->enableDcdcTimeout = false;
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* config->enableSwitchingConverterOutput = false;
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* endcode
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*
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* param config Pointer to configuration structure. See to dcdc_config_t.
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*/
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void DCDC_GetDefaultConfig(dcdc_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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config->controlMode = kDCDC_StaticControl;
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config->trimInputMode = kDCDC_SampleTrimInput;
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config->enableDcdcTimeout = false;
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config->enableSwitchingConverterOutput = false;
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}
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/*!
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* brief Gets the default setting for detection configuration.
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*
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* The default configuration are set according to responding registers' setting when powered on.
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* They are:
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* code
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* config->enableXtalokDetection = false;
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* config->powerDownOverVoltageVdd1P8Detection = true;
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* config->powerDownOverVoltageVdd1P0Detection = true;
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* config->powerDownLowVoltageDetection = false;
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* config->powerDownOverCurrentDetection = true;
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* config->powerDownPeakCurrentDetection = true;
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* config->powerDownZeroCrossDetection = true;
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* config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A;
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* endcode
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*
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* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
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*/
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void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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config->enableXtalokDetection = false;
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config->powerDownOverVoltageVdd1P8Detection = true;
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config->powerDownOverVoltageVdd1P0Detection = true;
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config->powerDownLowVoltageDetection = false;
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config->powerDownOverCurrentDetection = true;
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config->powerDownPeakCurrentDetection = true;
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config->powerDownZeroCrossDetection = true;
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config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A;
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}
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/*!
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* breif Configures the DCDC detection.
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*
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* param base DCDC peripheral base address.
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* param config Pointer to configuration structure. See to "dcdc_detection_config_t"
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*/
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void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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/* Configure the DCDC_REG0 register. */
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tmp32 = base->REG0 &
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~(DCDC_REG0_XTALOK_DISABLE_MASK | DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK | DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK |
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DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK | DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK |
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DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_CUR_SNS_THRSH_MASK);
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tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold);
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if (false == config->enableXtalokDetection)
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{
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tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK;
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}
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if (config->powerDownOverVoltageVdd1P8Detection)
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{
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tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK;
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}
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if (config->powerDownOverVoltageVdd1P0Detection)
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{
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tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK;
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}
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if (config->powerDownLowVoltageDetection)
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{
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tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK;
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}
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if (config->powerDownOverCurrentDetection)
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{
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tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK;
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}
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if (config->powerDownPeakCurrentDetection)
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{
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tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK;
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}
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if (config->powerDownZeroCrossDetection)
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{
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tmp32 |= DCDC_REG0_PWD_ZCD_MASK;
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}
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base->REG0 = tmp32;
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}
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/*!
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* brief Configures the DCDC clock source.
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*
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* param base DCDC peripheral base address.
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* param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
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*/
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void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
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{
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uint32_t tmp32;
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/* Configure the DCDC_REG0 register. */
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tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK |
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DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK);
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switch (clockSource)
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{
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case kDCDC_ClockInternalOsc:
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tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK;
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break;
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case kDCDC_ClockExternalOsc:
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/* Choose the external clock and disable the internal clock. */
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tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK;
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break;
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case kDCDC_ClockAutoSwitch:
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/* Set to switch from internal ring osc to xtal 24M if auto mode is enabled. */
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tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK;
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break;
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default:
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assert(false);
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break;
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}
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base->REG0 = tmp32;
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}
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/*!
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* brief Gets the default setting for low power configuration.
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*
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* The default configuration are set according to responding registers' setting when powered on.
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* They are:
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* code
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* config->enableAdjustHystereticValue = false;
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* endcode
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*
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* param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
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*/
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void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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config->enableAdjustHystereticValue = false;
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}
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/*!
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* brief Configures the DCDC low power.
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*
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* param base DCDC peripheral base address.
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* param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
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*/
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void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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/* Configure the DCDC_REG0 register. */
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tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK);
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if (config->enableAdjustHystereticValue)
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{
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tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK;
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}
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base->REG0 = tmp32;
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}
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/*!
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* brief Gets the default setting for loop control configuration.
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*
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* The default configuration are set according to responding registers' setting when powered on.
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* They are:
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* code
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* config->enableCommonHysteresis = false;
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* config->enableCommonThresholdDetection = false;
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* config->enableInvertHysteresisSign = false;
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* config->enableRCThresholdDetection = false;
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* config->enableRCScaleCircuit = 0U;
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* config->complementFeedForwardStep = 0U;
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* config->controlParameterMagnitude = 2U;
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* config->integralProportionalRatio = 2U;
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* endcode
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*
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* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
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*/
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void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
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{
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assert(NULL != config);
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/* Initializes the configure structure to zero. */
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(void)memset(config, 0, sizeof(*config));
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config->enableCommonHysteresis = false;
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config->enableCommonThresholdDetection = false;
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config->enableInvertHysteresisSign = false;
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config->enableRCThresholdDetection = false;
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config->enableRCScaleCircuit = 0U;
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config->complementFeedForwardStep = 0U;
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config->controlParameterMagnitude = 2U;
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config->integralProportionalRatio = 2U;
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}
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/*!
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* brief Configures the DCDC loop control.
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*
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* param base DCDC peripheral base address.
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* param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
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*/
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void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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/* Configure the DCDC_REG1 register. */
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tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK |
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DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK);
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if (config->enableCommonHysteresis)
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{
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tmp32 |= DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK;
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}
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if (config->enableCommonThresholdDetection)
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{
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tmp32 |= DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK;
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}
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if (config->enableDifferentialHysteresis)
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{
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tmp32 |= DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK;
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}
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if (config->enableDifferentialThresholdDetection)
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{
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tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK;
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}
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base->REG1 = tmp32;
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/* configure the DCDC_REG2 register. */
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tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |
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DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK |
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DCDC_REG2_LOOPCTRL_DC_R_MASK | DCDC_REG2_LOOPCTRL_DC_C_MASK);
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tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |
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DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) |
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DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) |
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DCDC_REG2_LOOPCTRL_EN_RCSCALE(config->enableRCScaleCircuit);
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if (config->enableInvertHysteresisSign)
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{
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tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK;
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}
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if (config->enableRCThresholdDetection)
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{
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tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK;
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}
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base->REG2 = tmp32;
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}
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/*!
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* brief Configures for the min power.
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*
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* param base DCDC peripheral base address.
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* param config Pointer to configuration structure. See to "dcdc_min_power_config_t".
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*/
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void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
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if (config->enableUseHalfFreqForContinuous)
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{
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tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
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}
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base->REG3 = tmp32;
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}
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/*!
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* brief Configures the DCDC internal regulator.
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*
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* param base DCDC peripheral base address.
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* param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
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*/
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void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
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{
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assert(NULL != config);
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uint32_t tmp32;
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tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK;
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tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint);
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base->REG3 = tmp32;
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}
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/*!
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* brief Initializes DCDC module when the control mode selected as setpoint mode.
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*
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* note The function should be invoked in the initial step to config the
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* DCDC via setpoint control mode.
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*
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* param base DCDC peripheral base address.
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* param config The pointer to the structure dcdc_setpoint_config_t.
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*/
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void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config)
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{
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assert(config != NULL);
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/* Enable DCDC Dig Logic. */
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base->REG5 = config->enableDigLogicMap;
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/* Set DCDC power mode. */
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base->REG6 = config->lowpowerMap;
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base->REG7 = config->standbyMap;
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base->REG7P = config->standbyLowpowerMap;
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/* Set target voltage of VDD1P8 in buck mode. */
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base->REG8 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage);
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base->REG9 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 4U);
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base->REG10 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 8U);
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base->REG11 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 12U);
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/* Set target voltage of VDD1P0 in buck mode. */
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base->REG12 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage);
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base->REG13 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 4U);
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base->REG14 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 8U);
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base->REG15 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 12U);
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/* Set target voltage of VDD1P8 in low power mode. */
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base->REG16 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage);
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base->REG17 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 4U);
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base->REG18 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 8U);
|
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base->REG19 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 12U);
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|
|
|
/* Set target voltage of VDD1P0 in low power mode. */
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base->REG20 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage);
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base->REG21 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 4U);
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base->REG22 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 8U);
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base->REG23 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 12U);
|
|
|
|
/* Enable DCDC module. */
|
|
base->REG4 = config->enableDCDCMap;
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}
|
|
|
|
/*!
|
|
* brief Boots DCDC into DCM(discontinous conduction mode).
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|
*
|
|
* pwd_zcd=0x0;
|
|
* DM_CTRL = 1'b1;
|
|
* pwd_cmp_offset=0x0;
|
|
* dcdc_loopctrl_en_rcscale=0x3 or 0x5;
|
|
* DCM_set_ctrl=1'b1;
|
|
*
|
|
* param base DCDC peripheral base address.
|
|
*/
|
|
void DCDC_BootIntoDCM(DCDC_Type *base)
|
|
{
|
|
base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
|
|
base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK;
|
|
base->REG1 |= DCDC_REG1_DM_CTRL_MASK;
|
|
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x5U);
|
|
base->REG3 &= ~(DCDC_REG3_DISABLE_IDLE_SKIP_MASK | DCDC_REG3_DISABLE_PULSE_SKIP_MASK);
|
|
base->REG3 |= DCDC_REG3_ENABLE_FF_MASK;
|
|
}
|
|
|
|
/*!
|
|
* brief Boots DCDC into CCM(continous conduction mode).
|
|
*
|
|
* pwd_zcd=0x1;
|
|
* pwd_cmp_offset=0x0;
|
|
* dcdc_loopctrl_en_rcscale=0x3;
|
|
*
|
|
* param base DCDC peripheral base address.
|
|
*/
|
|
void DCDC_BootIntoCCM(DCDC_Type *base)
|
|
{
|
|
base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;
|
|
base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U);
|
|
}
|