358 lines
19 KiB
C
358 lines
19 KiB
C
/*
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* Copyright 2019 NXP
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* All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include "fsl_anatop_ai.h"
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/* Component ID definition, used by tools. */
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#ifndef FSL_COMPONENT_ID
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#define FSL_COMPONENT_ID "platform.drivers.anatop_ai"
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#endif
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uint32_t ANATOP_AI_Access(anatop_ai_itf_t itf, bool isWrite, anatop_ai_reg_t addr, uint32_t wdata)
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{
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uint32_t temp;
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uint32_t rdata;
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uint32_t pre_toggle_done;
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uint32_t toggle_done;
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switch (itf)
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{
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case kAI_Itf_Ldo:
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if (isWrite)
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{
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ANADIG_MISC->VDDSOC_AI_CTRL &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
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temp = ANADIG_MISC->VDDSOC_AI_CTRL;
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temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) &
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ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
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ANADIG_MISC->VDDSOC_AI_CTRL = temp;
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ANADIG_MISC->VDDSOC_AI_WDATA = wdata; /* write ai data */
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ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */
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}
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else /* read */
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{
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temp = ANADIG_MISC->VDDSOC_AI_CTRL;
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temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
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temp |= (1UL << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT) &
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ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK;
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ANADIG_MISC->VDDSOC_AI_CTRL = temp;
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temp = ANADIG_MISC->VDDSOC_AI_CTRL;
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temp &= ~ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT) &
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ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK;
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ANADIG_MISC->VDDSOC_AI_CTRL = temp;
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ANADIG_PMU->PMU_LDO_PLL ^= ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK; /* toggle */
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rdata = ANADIG_MISC->VDDSOC_AI_RDATA; /* read data */
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return rdata;
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}
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break;
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case kAI_Itf_1g:
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if (isWrite)
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{
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pre_toggle_done =
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK; /* get pre_toggle_done */
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
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temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
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temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
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ANADIG_MISC->VDDSOC2PLL_AI_WDATA_1G = wdata; /* write ai data */
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^=
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */
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do
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{
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toggle_done =
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(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done
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toggle */
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} while (toggle_done == pre_toggle_done);
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}
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else
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{
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pre_toggle_done =
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(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* get pre_toggle_done */
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temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
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temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
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temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT) &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
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temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G;
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temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT) &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G = temp;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G ^=
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK; /* toggle */
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do
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{
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toggle_done =
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(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_1G &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK); /* wait toggle done
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toggle */
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} while (toggle_done == pre_toggle_done);
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rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_1G; /* read data */
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return rdata;
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}
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break;
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case kAI_Itf_Audio:
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if (isWrite)
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{
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pre_toggle_done =
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* get pre_toggle_done */
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &=
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~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
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temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
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temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
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ANADIG_MISC->VDDSOC2PLL_AI_WDATA_AUDIO = wdata; /* write ai data */
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^=
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */
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do
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{
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toggle_done =
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(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* wait toggle done
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toggle */
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} while (toggle_done == pre_toggle_done);
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &=
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~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
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}
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else
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{
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pre_toggle_done =
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(ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK); /* get pre_toggle_done
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*/
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temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
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temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
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temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT) &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
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temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO;
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temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT) &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO = temp;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO ^=
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK; /* toggle */
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do
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{
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toggle_done =
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_AUDIO &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK; /* wait toggle done
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toggle */
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} while (toggle_done == pre_toggle_done);
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rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_AUDIO; /* read data */
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return rdata;
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}
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break;
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case kAI_Itf_Video:
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if (isWrite)
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{
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pre_toggle_done =
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &=
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~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
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temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
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temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
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ANADIG_MISC->VDDSOC2PLL_AI_WDATA_VIDEO = wdata; /* write ai data */
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^=
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */
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do
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{
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toggle_done =
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done
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toggle */
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} while (toggle_done == pre_toggle_done);
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &=
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~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
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}
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else
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{
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pre_toggle_done =
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* get pre_toggle_done */
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temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
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temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
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temp |= (1UL << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT) &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
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temp = ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO;
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temp &= ~ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT) &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO = temp;
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO ^=
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK; /* toggle */
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do
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{
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toggle_done =
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ANADIG_MISC->VDDSOC2PLL_AI_CTRL_VIDEO &
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ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK; /* wait toggle done
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toggle */
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} while (toggle_done == pre_toggle_done);
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rdata = ANADIG_MISC->VDDSOC2PLL_AI_RDATA_VIDEO; /* read data */
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return rdata;
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}
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break;
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case kAI_Itf_400m:
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if (isWrite)
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{
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pre_toggle_done =
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ANADIG_MISC->VDDLPSR_AI400M_CTRL &
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ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */
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ANADIG_MISC->VDDLPSR_AI400M_CTRL &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
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temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
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temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) &
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ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
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ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
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ANADIG_MISC->VDDLPSR_AI400M_WDATA = wdata; /* write ai data */
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ANADIG_MISC->VDDLPSR_AI400M_CTRL ^=
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ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */
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do
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{
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toggle_done =
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ANADIG_MISC->VDDLPSR_AI400M_CTRL &
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ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */
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} while (toggle_done == pre_toggle_done);
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}
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else
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{
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pre_toggle_done =
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ANADIG_MISC->VDDLPSR_AI400M_CTRL &
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ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* get pre_toggle_done */
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temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
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temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
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temp |= (1UL << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT) &
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ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK;
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ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
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temp = ANADIG_MISC->VDDLPSR_AI400M_CTRL;
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temp &= ~ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT) &
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ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK;
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ANADIG_MISC->VDDLPSR_AI400M_CTRL = temp;
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ANADIG_MISC->VDDLPSR_AI400M_CTRL ^=
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ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK; /* toggle */
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do
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{
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toggle_done =
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ANADIG_MISC->VDDLPSR_AI400M_CTRL &
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ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK; /* wait toggle done toggle */
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} while (toggle_done == pre_toggle_done);
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rdata = ANADIG_MISC->VDDLPSR_AI400M_RDATA; /* read data */
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return rdata;
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}
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break;
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case kAI_Itf_Temp:
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if (isWrite)
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{
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ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
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temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
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temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
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ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
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ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
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ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */
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ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */
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}
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else
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{
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temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
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temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
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temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) &
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ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
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ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
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temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
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temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
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ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
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ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
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ANADIG_TEMPSENSOR->TEMPSENSOR ^= ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK; /* toggle */
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rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_TMPSNS; /* read data */
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return rdata;
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}
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break;
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case kAI_Itf_Bandgap:
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if (isWrite)
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{
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ANADIG_MISC->VDDLPSR_AI_CTRL &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
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temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
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temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
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temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
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ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
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ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
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ANADIG_MISC->VDDLPSR_AI_WDATA = wdata; /* write ai data */
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ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */
|
|
}
|
|
else
|
|
{
|
|
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
|
|
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
|
|
temp |= (1UL << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT) &
|
|
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK;
|
|
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
|
|
|
|
temp = ANADIG_MISC->VDDLPSR_AI_CTRL;
|
|
temp &= ~ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
|
|
temp |= ((uint32_t)addr << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT) &
|
|
ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK;
|
|
ANADIG_MISC->VDDLPSR_AI_CTRL = temp;
|
|
ANADIG_PMU->PMU_REF_CTRL ^= ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK; /* toggle */
|
|
rdata = ANADIG_MISC->VDDLPSR_AI_RDATA_REFTOP; /* read data */
|
|
return rdata;
|
|
}
|
|
break;
|
|
default:
|
|
/* This branch should never be hit. */
|
|
break;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void ANATOP_AI_Write(anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata)
|
|
{
|
|
(void)ANATOP_AI_Access(itf, true, addr, wdata);
|
|
}
|
|
|
|
uint32_t ANATOP_AI_Read(anatop_ai_itf_t itf, anatop_ai_reg_t addr)
|
|
{
|
|
uint32_t rdata;
|
|
rdata = ANATOP_AI_Access(itf, false, addr, 0);
|
|
return rdata;
|
|
}
|
|
|
|
void ANATOP_AI_WriteWithMaskShift(
|
|
anatop_ai_itf_t itf, anatop_ai_reg_t addr, uint32_t wdata, uint32_t mask, uint32_t shift)
|
|
{
|
|
uint32_t rdata;
|
|
rdata = ANATOP_AI_Read(itf, addr);
|
|
rdata = (rdata & (~mask)) | ((wdata << shift) & mask);
|
|
ANATOP_AI_Write(itf, addr, rdata);
|
|
}
|