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rt-thread/bsp/imxrt/libraries/MIMXRT1170/MIMXRT1176/MIMXRT1176_cm7.h

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/*
** ###################################################################
** Processors: MIMXRT1176AVM8A_cm7
** MIMXRT1176CVM8A_cm7
** MIMXRT1176DVMAA_cm7
**
** Compilers: Freescale C/C++ for Embedded ARM
** GNU C Compiler
** IAR ANSI C/C++ Compiler for ARM
** Keil ARM C/C++ Compiler
** MCUXpresso Compiler
**
** Reference manual: IMXRT1170RM, Rev 1, 02/2021
** Version: rev. 1.0, 2020-12-29
** Build: b220119
**
** Abstract:
** CMSIS Peripheral Access Layer for MIMXRT1176_cm7
**
** Copyright 1997-2016 Freescale Semiconductor, Inc.
** Copyright 2016-2022 NXP
** All rights reserved.
**
** SPDX-License-Identifier: BSD-3-Clause
**
** http: www.nxp.com
** mail: support@nxp.com
**
** Revisions:
** - rev. 0.1 (2018-03-05)
** Initial version.
** - rev. 1.0 (2020-12-29)
** Update header files to align with IMXRT1170RM Rev.0.
**
** ###################################################################
*/
/*!
* @file MIMXRT1176_cm7.h
* @version 1.0
* @date 2020-12-29
* @brief CMSIS Peripheral Access Layer for MIMXRT1176_cm7
*
* CMSIS Peripheral Access Layer for MIMXRT1176_cm7
*/
#ifndef _MIMXRT1176_CM7_H_
#define _MIMXRT1176_CM7_H_ /**< Symbol preventing repeated inclusion */
/** Memory map major version (memory maps with equal major version number are
* compatible) */
#define MCU_MEM_MAP_VERSION 0x0100U
/** Memory map minor version */
#define MCU_MEM_MAP_VERSION_MINOR 0x0000U
/* ----------------------------------------------------------------------------
--
---------------------------------------------------------------------------- */
/* Extra XRDC2 definition */
#define XRDC2_MAKE_MEM(mrc, mrgd) (((mrc) << 5U) | (mrgd))
#define XRDC2_GET_MRC(mem) ((mem) >> 5U)
#define XRDC2_GET_MRGD(mem) ((mem) & 31U)
#define XRDC2_MAKE_PERIPH(pac, pdac) (((pac) << 8U) | (pdac))
#define XRDC2_GET_PAC(periph) ((periph) >> 8U)
#define XRDC2_GET_PDAC(periph) ((periph) & 255U)
/* ----------------------------------------------------------------------------
-- Interrupt vector numbers
---------------------------------------------------------------------------- */
/*!
* @addtogroup Interrupt_vector_numbers Interrupt vector numbers
* @{
*/
/** Interrupt Number Definitions */
#define NUMBER_OF_INT_VECTORS 234 /**< Number of interrupts in the Vector table */
typedef enum IRQn {
/* Auxiliary constants */
NotAvail_IRQn = -128, /**< Not available device specific interrupt */
/* Core interrupts */
NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
HardFault_IRQn = -13, /**< Cortex-M7 SV Hard Fault Interrupt */
MemoryManagement_IRQn = -12, /**< Cortex-M7 Memory Management Interrupt */
BusFault_IRQn = -11, /**< Cortex-M7 Bus Fault Interrupt */
UsageFault_IRQn = -10, /**< Cortex-M7 Usage Fault Interrupt */
SVCall_IRQn = -5, /**< Cortex-M7 SV Call Interrupt */
DebugMonitor_IRQn = -4, /**< Cortex-M7 Debug Monitor Interrupt */
PendSV_IRQn = -2, /**< Cortex-M7 Pend SV Interrupt */
SysTick_IRQn = -1, /**< Cortex-M7 System Tick Interrupt */
/* Device specific interrupts */
DMA0_DMA16_IRQn = 0, /**< DMA channel 0/16 transfer complete */
DMA1_DMA17_IRQn = 1, /**< DMA channel 1/17 transfer complete */
DMA2_DMA18_IRQn = 2, /**< DMA channel 2/18 transfer complete */
DMA3_DMA19_IRQn = 3, /**< DMA channel 3/19 transfer complete */
DMA4_DMA20_IRQn = 4, /**< DMA channel 4/20 transfer complete */
DMA5_DMA21_IRQn = 5, /**< DMA channel 5/21 transfer complete */
DMA6_DMA22_IRQn = 6, /**< DMA channel 6/22 transfer complete */
DMA7_DMA23_IRQn = 7, /**< DMA channel 7/23 transfer complete */
DMA8_DMA24_IRQn = 8, /**< DMA channel 8/24 transfer complete */
DMA9_DMA25_IRQn = 9, /**< DMA channel 9/25 transfer complete */
DMA10_DMA26_IRQn = 10, /**< DMA channel 10/26 transfer complete */
DMA11_DMA27_IRQn = 11, /**< DMA channel 11/27 transfer complete */
DMA12_DMA28_IRQn = 12, /**< DMA channel 12/28 transfer complete */
DMA13_DMA29_IRQn = 13, /**< DMA channel 13/29 transfer complete */
DMA14_DMA30_IRQn = 14, /**< DMA channel 14/30 transfer complete */
DMA15_DMA31_IRQn = 15, /**< DMA channel 15/31 transfer complete */
DMA_ERROR_IRQn = 16, /**< DMA error interrupt channels 0-15 / 16-31 */
CTI_TRIGGER_OUT0_IRQn = 17, /**< CTI_TRIGGER_OUT0 */
CTI_TRIGGER_OUT1_IRQn = 18, /**< CTI_TRIGGER_OUT1 */
CORE_IRQn = 19, /**< CorePlatform exception IRQ */
LPUART1_IRQn = 20, /**< LPUART1 TX interrupt and RX interrupt */
LPUART2_IRQn = 21, /**< LPUART2 TX interrupt and RX interrupt */
LPUART3_IRQn = 22, /**< LPUART3 TX interrupt and RX interrupt */
LPUART4_IRQn = 23, /**< LPUART4 TX interrupt and RX interrupt */
LPUART5_IRQn = 24, /**< LPUART5 TX interrupt and RX interrupt */
LPUART6_IRQn = 25, /**< LPUART6 TX interrupt and RX interrupt */
LPUART7_IRQn = 26, /**< LPUART7 TX interrupt and RX interrupt */
LPUART8_IRQn = 27, /**< LPUART8 TX interrupt and RX interrupt */
LPUART9_IRQn = 28, /**< LPUART9 TX interrupt and RX interrupt */
LPUART10_IRQn = 29, /**< LPUART10 TX interrupt and RX interrupt */
LPUART11_IRQn = 30, /**< LPUART11 TX interrupt and RX interrupt */
LPUART12_IRQn = 31, /**< LPUART12 TX interrupt and RX interrupt */
LPI2C1_IRQn = 32, /**< LPI2C1 interrupt */
LPI2C2_IRQn = 33, /**< LPI2C2 interrupt */
LPI2C3_IRQn = 34, /**< LPI2C3 interrupt */
LPI2C4_IRQn = 35, /**< LPI2C4 interrupt */
LPI2C5_IRQn = 36, /**< LPI2C5 interrupt */
LPI2C6_IRQn = 37, /**< LPI2C6 interrupt */
LPSPI1_IRQn = 38, /**< LPSPI1 interrupt request line to the core */
LPSPI2_IRQn = 39, /**< LPSPI2 interrupt request line to the core */
LPSPI3_IRQn = 40, /**< LPSPI3 interrupt request line to the core */
LPSPI4_IRQn = 41, /**< LPSPI4 interrupt request line to the core */
LPSPI5_IRQn = 42, /**< LPSPI5 interrupt request line to the core */
LPSPI6_IRQn = 43, /**< LPSPI6 interrupt request line to the core */
CAN1_IRQn = 44, /**< CAN1 interrupt */
CAN1_ERROR_IRQn = 45, /**< CAN1 error interrupt */
CAN2_IRQn = 46, /**< CAN2 interrupt */
CAN2_ERROR_IRQn = 47, /**< CAN2 error interrupt */
CAN3_IRQn = 48, /**< CAN3 interrupt */
CAN3_ERROR_IRQn = 49, /**< CAN3 erro interrupt */
FLEXRAM_IRQn = 50, /**< FlexRAM address out of range Or access hit IRQ */
KPP_IRQn = 51, /**< Keypad nterrupt */
Reserved68_IRQn = 52, /**< Reserved interrupt */
GPR_IRQ_IRQn = 53, /**< GPR interrupt */
eLCDIF_IRQn = 54, /**< eLCDIF interrupt */
LCDIFv2_IRQn = 55, /**< LCDIFv2 interrupt */
CSI_IRQn = 56, /**< CSI interrupt */
PXP_IRQn = 57, /**< PXP interrupt */
MIPI_CSI_IRQn = 58, /**< MIPI_CSI interrupt */
MIPI_DSI_IRQn = 59, /**< MIPI_DSI interrupt */
GPU2D_IRQn = 60, /**< GPU2D interrupt */
GPIO6_Combined_0_15_IRQn = 61, /**< Combined interrupt indication for GPIO6 signal 0 throughout 15 */
GPIO6_Combined_16_31_IRQn = 62, /**< Combined interrupt indication for GPIO6 signal 16 throughout 31 */
DAC_IRQn = 63, /**< DAC interrupt */
KEY_MANAGER_IRQn = 64, /**< PUF interrupt */
WDOG2_IRQn = 65, /**< WDOG2 interrupt */
SNVS_HP_NON_TZ_IRQn = 66, /**< SRTC Consolidated Interrupt. Non TZ */
SNVS_HP_TZ_IRQn = 67, /**< SRTC Security Interrupt. TZ */
SNVS_PULSE_EVENT_IRQn = 68, /**< ON-OFF button press shorter than 5 secs (pulse event) */
CAAM_IRQ0_IRQn = 69, /**< CAAM interrupt queue for JQ0 */
CAAM_IRQ1_IRQn = 70, /**< CAAM interrupt queue for JQ1 */
CAAM_IRQ2_IRQn = 71, /**< CAAM interrupt queue for JQ2 */
CAAM_IRQ3_IRQn = 72, /**< CAAM interrupt queue for JQ3 */
CAAM_RECORVE_ERRPR_IRQn = 73, /**< CAAM interrupt for recoverable error */
CAAM_RTIC_IRQn = 74, /**< CAAM interrupt for RTIC */
CDOG_IRQn = 75, /**< CDOG interrupt */
SAI1_IRQn = 76, /**< SAI1 interrupt */
SAI2_IRQn = 77, /**< SAI1 interrupt */
SAI3_RX_IRQn = 78, /**< SAI3 interrupt */
SAI3_TX_IRQn = 79, /**< SAI3 interrupt */
SAI4_RX_IRQn = 80, /**< SAI4 interrupt */
SAI4_TX_IRQn = 81, /**< SAI4 interrupt */
SPDIF_IRQn = 82, /**< SPDIF interrupt */
TMPSNS_INT_IRQn = 83, /**< TMPSNS interrupt */
TMPSNS_LOW_HIGH_IRQn = 84, /**< TMPSNS low high interrupt */
TMPSNS_PANIC_IRQn = 85, /**< TMPSNS panic interrupt */
LPSR_LP8_BROWNOUT_IRQn = 86, /**< LPSR 1p8 brownout interrupt */
LPSR_LP0_BROWNOUT_IRQn = 87, /**< LPSR 1p0 brownout interrupt */
ADC1_IRQn = 88, /**< ADC1 interrupt */
ADC2_IRQn = 89, /**< ADC2 interrupt */
USBPHY1_IRQn = 90, /**< USBPHY1 interrupt */
USBPHY2_IRQn = 91, /**< USBPHY2 interrupt */
RDC_IRQn = 92, /**< RDC interrupt */
GPIO13_Combined_0_31_IRQn = 93, /**< Combined interrupt indication for GPIO13 signal 0 throughout 31 */
Reserved110_IRQn = 94, /**< Reserved interrupt */
DCIC1_IRQn = 95, /**< DCIC1 interrupt */
DCIC2_IRQn = 96, /**< DCIC2 interrupt */
ASRC_IRQn = 97, /**< ASRC interrupt */
FLEXRAM_ECC_IRQn = 98, /**< FlexRAM ECC fatal interrupt */
CM7_GPIO2_3_IRQn = 99, /**< CM7_GPIO2,CM7_GPIO3 interrupt */
GPIO1_Combined_0_15_IRQn = 100, /**< Combined interrupt indication for GPIO1 signal 0 throughout 15 */
GPIO1_Combined_16_31_IRQn = 101, /**< Combined interrupt indication for GPIO1 signal 16 throughout 31 */
GPIO2_Combined_0_15_IRQn = 102, /**< Combined interrupt indication for GPIO2 signal 0 throughout 15 */
GPIO2_Combined_16_31_IRQn = 103, /**< Combined interrupt indication for GPIO2 signal 16 throughout 31 */
GPIO3_Combined_0_15_IRQn = 104, /**< Combined interrupt indication for GPIO3 signal 0 throughout 15 */
GPIO3_Combined_16_31_IRQn = 105, /**< Combined interrupt indication for GPIO3 signal 16 throughout 31 */
GPIO4_Combined_0_15_IRQn = 106, /**< Combined interrupt indication for GPIO4 signal 0 throughout 15 */
GPIO4_Combined_16_31_IRQn = 107, /**< Combined interrupt indication for GPIO4 signal 16 throughout 31 */
GPIO5_Combined_0_15_IRQn = 108, /**< Combined interrupt indication for GPIO5 signal 0 throughout 15 */
GPIO5_Combined_16_31_IRQn = 109, /**< Combined interrupt indication for GPIO5 signal 16 throughout 31 */
FLEXIO1_IRQn = 110, /**< FLEXIO1 interrupt */
FLEXIO2_IRQn = 111, /**< FLEXIO2 interrupt */
WDOG1_IRQn = 112, /**< WDOG1 interrupt */
RTWDOG3_IRQn = 113, /**< RTWDOG3 interrupt */
EWM_IRQn = 114, /**< EWM interrupt */
OCOTP_READ_FUSE_ERROR_IRQn = 115, /**< OCOTP read fuse error interrupt */
OCOTP_READ_DONE_ERROR_IRQn = 116, /**< OCOTP read fuse done interrupt */
GPC_IRQn = 117, /**< GPC interrupt */
MUA_IRQn = 118, /**< MUA interrupt */
GPT1_IRQn = 119, /**< GPT1 interrupt */
GPT2_IRQn = 120, /**< GPT2 interrupt */
GPT3_IRQn = 121, /**< GPT3 interrupt */
GPT4_IRQn = 122, /**< GPT4 interrupt */
GPT5_IRQn = 123, /**< GPT5 interrupt */
GPT6_IRQn = 124, /**< GPT6 interrupt */
PWM1_0_IRQn = 125, /**< PWM1 capture 0, compare 0, or reload 0 interrupt */
PWM1_1_IRQn = 126, /**< PWM1 capture 1, compare 1, or reload 0 interrupt */
PWM1_2_IRQn = 127, /**< PWM1 capture 2, compare 2, or reload 0 interrupt */
PWM1_3_IRQn = 128, /**< PWM1 capture 3, compare 3, or reload 0 interrupt */
PWM1_FAULT_IRQn = 129, /**< PWM1 fault or reload error interrupt */
FLEXSPI1_IRQn = 130, /**< FlexSPI1 interrupt */
FLEXSPI2_IRQn = 131, /**< FlexSPI2 interrupt */
SEMC_IRQn = 132, /**< SEMC interrupt */
USDHC1_IRQn = 133, /**< USDHC1 interrupt */
USDHC2_IRQn = 134, /**< USDHC2 interrupt */
USB_OTG2_IRQn = 135, /**< USBO2 USB OTG2 */
USB_OTG1_IRQn = 136, /**< USBO2 USB OTG1 */
ENET_IRQn = 137, /**< ENET interrupt */
ENET_1588_Timer_IRQn = 138, /**< ENET_1588_Timer interrupt */
ENET_1G_MAC0_Tx_Rx_1_IRQn = 139, /**< ENET 1G MAC0 transmit/receive 1 */
ENET_1G_MAC0_Tx_Rx_2_IRQn = 140, /**< ENET 1G MAC0 transmit/receive 2 */
ENET_1G_IRQn = 141, /**< ENET 1G interrupt */
ENET_1G_1588_Timer_IRQn = 142, /**< ENET_1G_1588_Timer interrupt */
XBAR1_IRQ_0_1_IRQn = 143, /**< XBAR1 interrupt */
XBAR1_IRQ_2_3_IRQn = 144, /**< XBAR1 interrupt */
ADC_ETC_IRQ0_IRQn = 145, /**< ADCETC IRQ0 interrupt */
ADC_ETC_IRQ1_IRQn = 146, /**< ADCETC IRQ1 interrupt */
ADC_ETC_IRQ2_IRQn = 147, /**< ADCETC IRQ2 interrupt */
ADC_ETC_IRQ3_IRQn = 148, /**< ADCETC IRQ3 interrupt */
ADC_ETC_ERROR_IRQ_IRQn = 149, /**< ADCETC Error IRQ interrupt */
Reserved166_IRQn = 150, /**< Reserved interrupt */
Reserved167_IRQn = 151, /**< Reserved interrupt */
Reserved168_IRQn = 152, /**< Reserved interrupt */
Reserved169_IRQn = 153, /**< Reserved interrupt */
Reserved170_IRQn = 154, /**< Reserved interrupt */
PIT1_IRQn = 155, /**< PIT1 interrupt */
PIT2_IRQn = 156, /**< PIT2 interrupt */
ACMP1_IRQn = 157, /**< ACMP interrupt */
ACMP2_IRQn = 158, /**< ACMP interrupt */
ACMP3_IRQn = 159, /**< ACMP interrupt */
ACMP4_IRQn = 160, /**< ACMP interrupt */
Reserved177_IRQn = 161, /**< Reserved interrupt */
Reserved178_IRQn = 162, /**< Reserved interrupt */
Reserved179_IRQn = 163, /**< Reserved interrupt */
Reserved180_IRQn = 164, /**< Reserved interrupt */
ENC1_IRQn = 165, /**< ENC1 interrupt */
ENC2_IRQn = 166, /**< ENC2 interrupt */
ENC3_IRQn = 167, /**< ENC3 interrupt */
ENC4_IRQn = 168, /**< ENC4 interrupt */
Reserved185_IRQn = 169, /**< Reserved interrupt */
Reserved186_IRQn = 170, /**< Reserved interrupt */
TMR1_IRQn = 171, /**< TMR1 interrupt */
TMR2_IRQn = 172, /**< TMR2 interrupt */
TMR3_IRQn = 173, /**< TMR3 interrupt */
TMR4_IRQn = 174, /**< TMR4 interrupt */
SEMA4_CP0_IRQn = 175, /**< SEMA4 CP0 interrupt */
SEMA4_CP1_IRQn = 176, /**< SEMA4 CP1 interrupt */
PWM2_0_IRQn = 177, /**< PWM2 capture 0, compare 0, or reload 0 interrupt */
PWM2_1_IRQn = 178, /**< PWM2 capture 1, compare 1, or reload 0 interrupt */
PWM2_2_IRQn = 179, /**< PWM2 capture 2, compare 2, or reload 0 interrupt */
PWM2_3_IRQn = 180, /**< PWM2 capture 3, compare 3, or reload 0 interrupt */
PWM2_FAULT_IRQn = 181, /**< PWM2 fault or reload error interrupt */
PWM3_0_IRQn = 182, /**< PWM3 capture 0, compare 0, or reload 0 interrupt */
PWM3_1_IRQn = 183, /**< PWM3 capture 1, compare 1, or reload 0 interrupt */
PWM3_2_IRQn = 184, /**< PWM3 capture 2, compare 2, or reload 0 interrupt */
PWM3_3_IRQn = 185, /**< PWM3 capture 3, compare 3, or reload 0 interrupt */
PWM3_FAULT_IRQn = 186, /**< PWM3 fault or reload error interrupt */
PWM4_0_IRQn = 187, /**< PWM4 capture 0, compare 0, or reload 0 interrupt */
PWM4_1_IRQn = 188, /**< PWM4 capture 1, compare 1, or reload 0 interrupt */
PWM4_2_IRQn = 189, /**< PWM4 capture 2, compare 2, or reload 0 interrupt */
PWM4_3_IRQn = 190, /**< PWM4 capture 3, compare 3, or reload 0 interrupt */
PWM4_FAULT_IRQn = 191, /**< PWM4 fault or reload error interrupt */
Reserved208_IRQn = 192, /**< Reserved interrupt */
Reserved209_IRQn = 193, /**< Reserved interrupt */
Reserved210_IRQn = 194, /**< Reserved interrupt */
Reserved211_IRQn = 195, /**< Reserved interrupt */
Reserved212_IRQn = 196, /**< Reserved interrupt */
Reserved213_IRQn = 197, /**< Reserved interrupt */
Reserved214_IRQn = 198, /**< Reserved interrupt */
Reserved215_IRQn = 199, /**< Reserved interrupt */
PDM_HWVAD_EVENT_IRQn = 200, /**< HWVAD event interrupt */
PDM_HWVAD_ERROR_IRQn = 201, /**< HWVAD error interrupt */
PDM_EVENT_IRQn = 202, /**< PDM event interrupt */
PDM_ERROR_IRQn = 203, /**< PDM error interrupt */
EMVSIM1_IRQn = 204, /**< EMVSIM1 interrupt */
EMVSIM2_IRQn = 205, /**< EMVSIM2 interrupt */
MECC1_INT_IRQn = 206, /**< MECC1 int */
MECC1_FATAL_INT_IRQn = 207, /**< MECC1 fatal int */
MECC2_INT_IRQn = 208, /**< MECC2 int */
MECC2_FATAL_INT_IRQn = 209, /**< MECC2 fatal int */
XECC_FLEXSPI1_INT_IRQn = 210, /**< XECC int */
XECC_FLEXSPI1_FATAL_INT_IRQn = 211, /**< XECC fatal int */
XECC_FLEXSPI2_INT_IRQn = 212, /**< XECC int */
XECC_FLEXSPI2_FATAL_INT_IRQn = 213, /**< XECC fatal int */
XECC_SEMC_INT_IRQn = 214, /**< XECC int */
XECC_SEMC_FATAL_INT_IRQn = 215, /**< XECC fatal int */
ENET_QOS_IRQn = 216, /**< ENET_QOS interrupt */
ENET_QOS_PMT_IRQn = 217 /**< ENET_QOS_PMT interrupt */
} IRQn_Type;
/*!
* @}
*/ /* end of group Interrupt_vector_numbers */
/* ----------------------------------------------------------------------------
-- Cortex M7 Core Configuration
---------------------------------------------------------------------------- */
/*!
* @addtogroup Cortex_Core_Configuration Cortex M7 Core Configuration
* @{
*/
#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
#define __ICACHE_PRESENT 1 /**< Defines if an ICACHE is present or not */
#define __DCACHE_PRESENT 1 /**< Defines if an DCACHE is present or not */
#define __DTCM_PRESENT 1 /**< Defines if an DTCM is present or not */
#define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
#include "core_cm7.h" /* Core Peripheral Access Layer */
#include "system_MIMXRT1176_cm7.h" /* Device specific configuration file */
/*!
* @}
*/ /* end of group Cortex_Core_Configuration */
/* ----------------------------------------------------------------------------
-- Mapping Information
---------------------------------------------------------------------------- */
/*!
* @addtogroup Mapping_Information Mapping Information
* @{
*/
/** Mapping Information */
/*!
* @addtogroup rdc_mapping
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @brief Structure for the RDC mapping
*
* Defines the structure for the RDC resource collections.
*/
/*
* Domain of these masters are not assigned by RDC
* CM7, CM7_DMA: Always use domain ID 0.
* CM4, CM4_DMA: Use domain ID 0 in single core case, 1 in dual core case.
* CAAM: Defined in CAAM mst_a[x]icid[10]
* LCDIFv2: Defined in LCDIF2 user bit[0]
* SSARC: Defined in SSARC user bit[0]
*/
typedef enum _rdc_master
{
kRDC_Master_ENET_1G_TX = 1U, /**< ENET_1G_TX */
kRDC_Master_ENET_1G_RX = 2U, /**< ENET_1G_RX */
kRDC_Master_ENET = 3U, /**< ENET */
kRDC_Master_ENET_QOS = 4U, /**< ENET_QOS */
kRDC_Master_USDHC1 = 5U, /**< USDHC1 */
kRDC_Master_USDHC2 = 6U, /**< USDHC2 */
kRDC_Master_USB = 7U, /**< USB */
kRDC_Master_GPU = 8U, /**< GPU */
kRDC_Master_PXP = 9U, /**< PXP */
kRDC_Master_LCDIF = 10U, /**< LCDIF */
kRDC_Master_CSI = 11U, /**< CSI */
} rdc_master_t;
typedef enum _rdc_mem
{
kRDC_Mem_MRC0_0 = 0U,
kRDC_Mem_MRC0_1 = 1U,
kRDC_Mem_MRC0_2 = 2U,
kRDC_Mem_MRC0_3 = 3U,
kRDC_Mem_MRC0_4 = 4U,
kRDC_Mem_MRC0_5 = 5U,
kRDC_Mem_MRC0_6 = 6U,
kRDC_Mem_MRC0_7 = 7U,
kRDC_Mem_MRC1_0 = 8U,
kRDC_Mem_MRC1_1 = 9U,
kRDC_Mem_MRC1_2 = 10U,
kRDC_Mem_MRC1_3 = 11U,
kRDC_Mem_MRC1_4 = 12U,
kRDC_Mem_MRC1_5 = 13U,
kRDC_Mem_MRC1_6 = 14U,
kRDC_Mem_MRC1_7 = 15U,
kRDC_Mem_MRC2_0 = 16U,
kRDC_Mem_MRC2_1 = 17U,
kRDC_Mem_MRC2_2 = 18U,
kRDC_Mem_MRC2_3 = 19U,
kRDC_Mem_MRC2_4 = 20U,
kRDC_Mem_MRC2_5 = 21U,
kRDC_Mem_MRC2_6 = 22U,
kRDC_Mem_MRC2_7 = 23U,
kRDC_Mem_MRC3_0 = 24U,
kRDC_Mem_MRC3_1 = 25U,
kRDC_Mem_MRC3_2 = 26U,
kRDC_Mem_MRC3_3 = 27U,
kRDC_Mem_MRC3_4 = 28U,
kRDC_Mem_MRC3_5 = 29U,
kRDC_Mem_MRC3_6 = 30U,
kRDC_Mem_MRC3_7 = 31U,
kRDC_Mem_MRC4_0 = 32U,
kRDC_Mem_MRC4_1 = 33U,
kRDC_Mem_MRC4_2 = 34U,
kRDC_Mem_MRC4_3 = 35U,
kRDC_Mem_MRC4_4 = 36U,
kRDC_Mem_MRC4_5 = 37U,
kRDC_Mem_MRC4_6 = 38U,
kRDC_Mem_MRC4_7 = 39U,
kRDC_Mem_MRC5_0 = 40U,
kRDC_Mem_MRC5_1 = 41U,
kRDC_Mem_MRC5_2 = 42U,
kRDC_Mem_MRC5_3 = 43U,
kRDC_Mem_MRC6_0 = 44U,
kRDC_Mem_MRC6_1 = 45U,
kRDC_Mem_MRC6_2 = 46U,
kRDC_Mem_MRC6_3 = 47U,
kRDC_Mem_MRC7_0 = 48U,
kRDC_Mem_MRC7_1 = 49U,
kRDC_Mem_MRC7_2 = 50U,
kRDC_Mem_MRC7_3 = 51U,
kRDC_Mem_MRC7_4 = 52U,
kRDC_Mem_MRC7_5 = 53U,
kRDC_Mem_MRC7_6 = 54U,
kRDC_Mem_MRC7_7 = 55U,
kRDC_Mem_MRC8_0 = 56U,
kRDC_Mem_MRC8_1 = 57U,
kRDC_Mem_MRC8_2 = 58U,
} rdc_mem_t;
typedef enum _rdc_periph
{
kRDC_Periph_MTR = 0U, /**< MTR */
kRDC_Periph_MECC1 = 1U, /**< MECC1 */
kRDC_Periph_MECC2 = 2U, /**< MECC2 */
kRDC_Periph_FLEXSPI1 = 3U, /**< FlexSPI1 */
kRDC_Periph_FLEXSPI2 = 4U, /**< FlexSPI2 */
kRDC_Periph_SEMC = 5U, /**< SEMC */
kRDC_Periph_CM7_IMXRT = 6U, /**< CM7_IMXRT */
kRDC_Periph_EWM = 7U, /**< EWM */
kRDC_Periph_WDOG1 = 8U, /**< WDOG1 */
kRDC_Periph_WDOG2 = 9U, /**< WDOG2 */
kRDC_Periph_WDOG3 = 10U, /**< WDOG3 */
kRDC_Periph_AOI_XBAR = 11U, /**< AOI_XBAR */
kRDC_Periph_ADC_ETC = 12U, /**< ADC_ETC */
kRDC_Periph_CAAM_1 = 13U, /**< CAAM_1 */
kRDC_Periph_ADC1 = 14U, /**< ADC1 */
kRDC_Periph_ADC2 = 15U, /**< ADC2 */
kRDC_Periph_TSC_DIG = 16U, /**< TSC_DIG */
kRDC_Periph_DAC = 17U, /**< DAC */
kRDC_Periph_IEE = 18U, /**< IEE */
kRDC_Periph_DMAMUX = 19U, /**< DMAMUX */
kRDC_Periph_EDMA = 19U, /**< EDMA */
kRDC_Periph_LPUART1 = 20U, /**< LPUART1 */
kRDC_Periph_LPUART2 = 21U, /**< LPUART2 */
kRDC_Periph_LPUART3 = 22U, /**< LPUART3 */
kRDC_Periph_LPUART4 = 23U, /**< LPUART4 */
kRDC_Periph_LPUART5 = 24U, /**< LPUART5 */
kRDC_Periph_LPUART6 = 25U, /**< LPUART6 */
kRDC_Periph_LPUART7 = 26U, /**< LPUART7 */
kRDC_Periph_LPUART8 = 27U, /**< LPUART8 */
kRDC_Periph_LPUART9 = 28U, /**< LPUART9 */
kRDC_Periph_LPUART10 = 29U, /**< LPUART10 */
kRDC_Periph_FLEXIO1 = 30U, /**< FlexIO1 */
kRDC_Periph_FLEXIO2 = 31U, /**< FlexIO2 */
kRDC_Periph_CAN1 = 32U, /**< CAN1 */
kRDC_Periph_CAN2 = 33U, /**< CAN2 */
kRDC_Periph_PIT1 = 34U, /**< PIT1 */
kRDC_Periph_KPP = 35U, /**< KPP */
kRDC_Periph_IOMUXC_GPR = 36U, /**< IOMUXC_GPR */
kRDC_Periph_IOMUXC = 37U, /**< IOMUXC */
kRDC_Periph_GPT1 = 38U, /**< GPT1 */
kRDC_Periph_GPT2 = 39U, /**< GPT2 */
kRDC_Periph_GPT3 = 40U, /**< GPT3 */
kRDC_Periph_GPT4 = 41U, /**< GPT4 */
kRDC_Periph_GPT5 = 42U, /**< GPT5 */
kRDC_Periph_GPT6 = 43U, /**< GPT6 */
kRDC_Periph_LPI2C1 = 44U, /**< LPI2C1 */
kRDC_Periph_LPI2C2 = 45U, /**< LPI2C2 */
kRDC_Periph_LPI2C3 = 46U, /**< LPI2C3 */
kRDC_Periph_LPI2C4 = 47U, /**< LPI2C4 */
kRDC_Periph_LPSPI1 = 48U, /**< LPSPI1 */
kRDC_Periph_LPSPI2 = 49U, /**< LPSPI2 */
kRDC_Periph_LPSPI3 = 50U, /**< LPSPI3 */
kRDC_Periph_LPSPI4 = 51U, /**< LPSPI4 */
kRDC_Periph_GPIO_1_6 = 52U, /**< GPIO_1_6 */
kRDC_Periph_CCM_OBS = 53U, /**< CCM_OBS */
kRDC_Periph_SIM1 = 54U, /**< SIM1 */
kRDC_Periph_SIM2 = 55U, /**< SIM2 */
kRDC_Periph_QTIMER1 = 56U, /**< QTimer1 */
kRDC_Periph_QTIMER2 = 57U, /**< QTimer2 */
kRDC_Periph_QTIMER3 = 58U, /**< QTimer3 */
kRDC_Periph_QTIMER4 = 59U, /**< QTimer4 */
kRDC_Periph_ENC1 = 60U, /**< ENC1 */
kRDC_Periph_ENC2 = 61U, /**< ENC2 */
kRDC_Periph_ENC3 = 62U, /**< ENC3 */
kRDC_Periph_ENC4 = 63U, /**< ENC4 */
kRDC_Periph_FLEXPWM1 = 64U, /**< FLEXPWM1 */
kRDC_Periph_FLEXPWM2 = 65U, /**< FLEXPWM2 */
kRDC_Periph_FLEXPWM3 = 66U, /**< FLEXPWM3 */
kRDC_Periph_FLEXPWM4 = 67U, /**< FLEXPWM4 */
kRDC_Periph_CAAM_2 = 68U, /**< CAAM_2 */
kRDC_Periph_CAAM_3 = 69U, /**< CAAM_3 */
kRDC_Periph_ACMP1 = 70U, /**< ACMP1 */
kRDC_Periph_ACMP2 = 71U, /**< ACMP2 */
kRDC_Periph_ACMP3 = 72U, /**< ACMP3 */
kRDC_Periph_ACMP4 = 73U, /**< ACMP4 */
kRDC_Periph_CAAM = 74U, /**< CAAM */
kRDC_Periph_SPDIF = 75U, /**< SPDIF */
kRDC_Periph_SAI1 = 76U, /**< SAI1 */
kRDC_Periph_SAI2 = 77U, /**< SAI2 */
kRDC_Periph_SAI3 = 78U, /**< SAI3 */
kRDC_Periph_ASRC = 79U, /**< ASRC */
kRDC_Periph_USDHC1 = 80U, /**< USDHC1 */
kRDC_Periph_USDHC2 = 81U, /**< USDHC2 */
kRDC_Periph_ENET_1G = 82U, /**< ENET_1G */
kRDC_Periph_ENET = 83U, /**< ENET */
kRDC_Periph_USB_PL301 = 84U, /**< USB_PL301 */
kRDC_Periph_USBPHY2 = 85U, /**< USBPHY2 */
kRDC_Periph_USB_OTG2 = 85U, /**< USB_OTG2 */
kRDC_Periph_USBPHY1 = 86U, /**< USBPHY1 */
kRDC_Periph_USB_OTG1 = 86U, /**< USB_OTG1 */
kRDC_Periph_ENET_QOS = 87U, /**< ENET_QOS */
kRDC_Periph_CAAM_5 = 88U, /**< CAAM_5 */
kRDC_Periph_CSI = 89U, /**< CSI */
kRDC_Periph_LCDIF1 = 90U, /**< LCDIF1 */
kRDC_Periph_LCDIF2 = 91U, /**< LCDIF2 */
kRDC_Periph_MIPI_DSI = 92U, /**< MIPI_DSI */
kRDC_Periph_MIPI_CSI = 93U, /**< MIPI_CSI */
kRDC_Periph_PXP = 94U, /**< PXP */
kRDC_Periph_VIDEO_MUX = 95U, /**< VIDEO_MUX */
kRDC_Periph_PGMC_SRC_GPC = 96U, /**< PGMC_SRC_GPC */
kRDC_Periph_IOMUXC_LPSR = 97U, /**< IOMUXC_LPSR */
kRDC_Periph_IOMUXC_LPSR_GPR = 98U, /**< IOMUXC_LPSR_GPR */
kRDC_Periph_WDOG4 = 99U, /**< WDOG4 */
kRDC_Periph_DMAMUX_LPSR = 100U, /**< DMAMUX_LPSR */
kRDC_Periph_EDMA_LPSR = 100U, /**< EDMA_LPSR */
kRDC_Periph_Reserved = 101U, /**< Reserved */
kRDC_Periph_MIC = 102U, /**< MIC */
kRDC_Periph_LPUART11 = 103U, /**< LPUART11 */
kRDC_Periph_LPUART12 = 104U, /**< LPUART12 */
kRDC_Periph_LPSPI5 = 105U, /**< LPSPI5 */
kRDC_Periph_LPSPI6 = 106U, /**< LPSPI6 */
kRDC_Periph_LPI2C5 = 107U, /**< LPI2C5 */
kRDC_Periph_LPI2C6 = 108U, /**< LPI2C6 */
kRDC_Periph_CAN3 = 109U, /**< CAN3 */
kRDC_Periph_SAI4 = 110U, /**< SAI4 */
kRDC_Periph_SEMA1 = 111U, /**< SEMA1 */
kRDC_Periph_GPIO_7_12 = 112U, /**< GPIO_7_12 */
kRDC_Periph_KEY_MANAGER = 113U, /**< KEY_MANAGER */
kRDC_Periph_ANATOP = 114U, /**< ANATOP */
kRDC_Periph_SNVS_HP_WRAPPER = 115U, /**< SNVS_HP_WRAPPER */
kRDC_Periph_IOMUXC_SNVS = 116U, /**< IOMUXC_SNVS */
kRDC_Periph_IOMUXC_SNVS_GPR = 117U, /**< IOMUXC_SNVS_GPR */
kRDC_Periph_SNVS_SRAM = 118U, /**< SNVS_SRAM */
kRDC_Periph_GPIO13 = 119U, /**< GPIO13 */
kRDC_Periph_ROMCP = 120U, /**< ROMCP */
kRDC_Periph_DCDC = 121U, /**< DCDC */
kRDC_Periph_OCOTP_CTRL_WRAPPER = 122U, /**< OCOTP_CTRL_WRAPPER */
kRDC_Periph_PIT2 = 123U, /**< PIT2 */
kRDC_Periph_SSARC = 124U, /**< SSARC */
kRDC_Periph_CCM = 125U, /**< CCM */
kRDC_Periph_CAAM_6 = 126U, /**< CAAM_6 */
kRDC_Periph_CAAM_7 = 127U, /**< CAAM_7 */
} rdc_periph_t;
/* @} */
typedef enum _xbar_input_signal
{
kXBARA1_InputLogicLow = 0|0x100U, /**< LOGIC_LOW output assigned to XBARA1_IN0 input. */
kXBARA1_InputLogicHigh = 1|0x100U, /**< LOGIC_HIGH output assigned to XBARA1_IN1 input. */
kXBARA1_InputRESERVED2 = 2|0x100U, /**< XBARA1_IN2 input is reserved. */
kXBARA1_InputRESERVED3 = 3|0x100U, /**< XBARA1_IN3 input is reserved. */
kXBARA1_InputIomuxXbarInout04 = 4|0x100U, /**< IOMUX_XBAR_INOUT04 output assigned to XBARA1_IN4 input. */
kXBARA1_InputIomuxXbarInout05 = 5|0x100U, /**< IOMUX_XBAR_INOUT05 output assigned to XBARA1_IN5 input. */
kXBARA1_InputIomuxXbarInout06 = 6|0x100U, /**< IOMUX_XBAR_INOUT06 output assigned to XBARA1_IN6 input. */
kXBARA1_InputIomuxXbarInout07 = 7|0x100U, /**< IOMUX_XBAR_INOUT07 output assigned to XBARA1_IN7 input. */
kXBARA1_InputIomuxXbarInout08 = 8|0x100U, /**< IOMUX_XBAR_INOUT08 output assigned to XBARA1_IN8 input. */
kXBARA1_InputIomuxXbarInout09 = 9|0x100U, /**< IOMUX_XBAR_INOUT09 output assigned to XBARA1_IN9 input. */
kXBARA1_InputIomuxXbarInout10 = 10|0x100U, /**< IOMUX_XBAR_INOUT10 output assigned to XBARA1_IN10 input. */
kXBARA1_InputIomuxXbarInout11 = 11|0x100U, /**< IOMUX_XBAR_INOUT11 output assigned to XBARA1_IN11 input. */
kXBARA1_InputIomuxXbarInout12 = 12|0x100U, /**< IOMUX_XBAR_INOUT12 output assigned to XBARA1_IN12 input. */
kXBARA1_InputIomuxXbarInout13 = 13|0x100U, /**< IOMUX_XBAR_INOUT13 output assigned to XBARA1_IN13 input. */
kXBARA1_InputIomuxXbarInout14 = 14|0x100U, /**< IOMUX_XBAR_INOUT14 output assigned to XBARA1_IN14 input. */
kXBARA1_InputIomuxXbarInout15 = 15|0x100U, /**< IOMUX_XBAR_INOUT15 output assigned to XBARA1_IN15 input. */
kXBARA1_InputIomuxXbarInout16 = 16|0x100U, /**< IOMUX_XBAR_INOUT16 output assigned to XBARA1_IN16 input. */
kXBARA1_InputIomuxXbarInout17 = 17|0x100U, /**< IOMUX_XBAR_INOUT17 output assigned to XBARA1_IN17 input. */
kXBARA1_InputIomuxXbarInout18 = 18|0x100U, /**< IOMUX_XBAR_INOUT18 output assigned to XBARA1_IN18 input. */
kXBARA1_InputIomuxXbarInout19 = 19|0x100U, /**< IOMUX_XBAR_INOUT19 output assigned to XBARA1_IN19 input. */
kXBARA1_InputIomuxXbarInout20 = 20|0x100U, /**< IOMUX_XBAR_INOUT20 output assigned to XBARA1_IN20 input. */
kXBARA1_InputIomuxXbarInout21 = 21|0x100U, /**< IOMUX_XBAR_INOUT21 output assigned to XBARA1_IN21 input. */
kXBARA1_InputIomuxXbarInout22 = 22|0x100U, /**< IOMUX_XBAR_INOUT22 output assigned to XBARA1_IN22 input. */
kXBARA1_InputIomuxXbarInout23 = 23|0x100U, /**< IOMUX_XBAR_INOUT23 output assigned to XBARA1_IN23 input. */
kXBARA1_InputIomuxXbarInout24 = 24|0x100U, /**< IOMUX_XBAR_INOUT24 output assigned to XBARA1_IN24 input. */
kXBARA1_InputIomuxXbarInout25 = 25|0x100U, /**< IOMUX_XBAR_INOUT25 output assigned to XBARA1_IN25 input. */
kXBARA1_InputIomuxXbarInout26 = 26|0x100U, /**< IOMUX_XBAR_INOUT26 output assigned to XBARA1_IN26 input. */
kXBARA1_InputIomuxXbarInout27 = 27|0x100U, /**< IOMUX_XBAR_INOUT27 output assigned to XBARA1_IN27 input. */
kXBARA1_InputIomuxXbarInout28 = 28|0x100U, /**< IOMUX_XBAR_INOUT28 output assigned to XBARA1_IN28 input. */
kXBARA1_InputIomuxXbarInout29 = 29|0x100U, /**< IOMUX_XBAR_INOUT29 output assigned to XBARA1_IN29 input. */
kXBARA1_InputIomuxXbarInout30 = 30|0x100U, /**< IOMUX_XBAR_INOUT30 output assigned to XBARA1_IN30 input. */
kXBARA1_InputIomuxXbarInout31 = 31|0x100U, /**< IOMUX_XBAR_INOUT31 output assigned to XBARA1_IN31 input. */
kXBARA1_InputIomuxXbarInout32 = 32|0x100U, /**< IOMUX_XBAR_INOUT32 output assigned to XBARA1_IN32 input. */
kXBARA1_InputIomuxXbarInout33 = 33|0x100U, /**< IOMUX_XBAR_INOUT33 output assigned to XBARA1_IN33 input. */
kXBARA1_InputIomuxXbarInout34 = 34|0x100U, /**< IOMUX_XBAR_INOUT34 output assigned to XBARA1_IN34 input. */
kXBARA1_InputIomuxXbarInout35 = 35|0x100U, /**< IOMUX_XBAR_INOUT35 output assigned to XBARA1_IN35 input. */
kXBARA1_InputIomuxXbarInout36 = 36|0x100U, /**< IOMUX_XBAR_INOUT36 output assigned to XBARA1_IN36 input. */
kXBARA1_InputIomuxXbarInout37 = 37|0x100U, /**< IOMUX_XBAR_INOUT37 output assigned to XBARA1_IN37 input. */
kXBARA1_InputIomuxXbarInout38 = 38|0x100U, /**< IOMUX_XBAR_INOUT38 output assigned to XBARA1_IN38 input. */
kXBARA1_InputIomuxXbarInout39 = 39|0x100U, /**< IOMUX_XBAR_INOUT39 output assigned to XBARA1_IN39 input. */
kXBARA1_InputIomuxXbarInout40 = 40|0x100U, /**< IOMUX_XBAR_INOUT40 output assigned to XBARA1_IN40 input. */
kXBARA1_InputRESERVED41 = 41|0x100U, /**< XBARA1_IN41 input is reserved. */
kXBARA1_InputAcmp1Out = 42|0x100U, /**< ACMP1_OUT output assigned to XBARA1_IN42 input. */
kXBARA1_InputAcmp2Out = 43|0x100U, /**< ACMP2_OUT output assigned to XBARA1_IN43 input. */
kXBARA1_InputAcmp3Out = 44|0x100U, /**< ACMP3_OUT output assigned to XBARA1_IN44 input. */
kXBARA1_InputAcmp4Out = 45|0x100U, /**< ACMP4_OUT output assigned to XBARA1_IN45 input. */
kXBARA1_InputRESERVED46 = 46|0x100U, /**< XBARA1_IN46 input is reserved. */
kXBARA1_InputRESERVED47 = 47|0x100U, /**< XBARA1_IN47 input is reserved. */
kXBARA1_InputRESERVED48 = 48|0x100U, /**< XBARA1_IN48 input is reserved. */
kXBARA1_InputRESERVED49 = 49|0x100U, /**< XBARA1_IN49 input is reserved. */
kXBARA1_InputQtimer1Timer0 = 50|0x100U, /**< QTIMER1_TIMER0 output assigned to XBARA1_IN50 input. */
kXBARA1_InputQtimer1Timer1 = 51|0x100U, /**< QTIMER1_TIMER1 output assigned to XBARA1_IN51 input. */
kXBARA1_InputQtimer1Timer2 = 52|0x100U, /**< QTIMER1_TIMER2 output assigned to XBARA1_IN52 input. */
kXBARA1_InputQtimer1Timer3 = 53|0x100U, /**< QTIMER1_TIMER3 output assigned to XBARA1_IN53 input. */
kXBARA1_InputQtimer2Timer0 = 54|0x100U, /**< QTIMER2_TIMER0 output assigned to XBARA1_IN54 input. */
kXBARA1_InputQtimer2Timer1 = 55|0x100U, /**< QTIMER2_TIMER1 output assigned to XBARA1_IN55 input. */
kXBARA1_InputQtimer2Timer2 = 56|0x100U, /**< QTIMER2_TIMER2 output assigned to XBARA1_IN56 input. */
kXBARA1_InputQtimer2Timer3 = 57|0x100U, /**< QTIMER2_TIMER3 output assigned to XBARA1_IN57 input. */
kXBARA1_InputQtimer3Timer0 = 58|0x100U, /**< QTIMER3_TIMER0 output assigned to XBARA1_IN58 input. */
kXBARA1_InputQtimer3Timer1 = 59|0x100U, /**< QTIMER3_TIMER1 output assigned to XBARA1_IN59 input. */
kXBARA1_InputQtimer3Timer2 = 60|0x100U, /**< QTIMER3_TIMER2 output assigned to XBARA1_IN60 input. */
kXBARA1_InputQtimer3Timer3 = 61|0x100U, /**< QTIMER3_TIMER3 output assigned to XBARA1_IN61 input. */
kXBARA1_InputQtimer4Timer0 = 62|0x100U, /**< QTIMER4_TIMER0 output assigned to XBARA1_IN62 input. */
kXBARA1_InputQtimer4Timer1 = 63|0x100U, /**< QTIMER4_TIMER1 output assigned to XBARA1_IN63 input. */
kXBARA1_InputQtimer4Timer2 = 64|0x100U, /**< QTIMER4_TIMER2 output assigned to XBARA1_IN64 input. */
kXBARA1_InputQtimer4Timer3 = 65|0x100U, /**< QTIMER4_TIMER3 output assigned to XBARA1_IN65 input. */
kXBARA1_InputRESERVED66 = 66|0x100U, /**< XBARA1_IN66 input is reserved. */
kXBARA1_InputRESERVED67 = 67|0x100U, /**< XBARA1_IN67 input is reserved. */
kXBARA1_InputRESERVED68 = 68|0x100U, /**< XBARA1_IN68 input is reserved. */
kXBARA1_InputRESERVED69 = 69|0x100U, /**< XBARA1_IN69 input is reserved. */
kXBARA1_InputRESERVED70 = 70|0x100U, /**< XBARA1_IN70 input is reserved. */
kXBARA1_InputRESERVED71 = 71|0x100U, /**< XBARA1_IN71 input is reserved. */
kXBARA1_InputRESERVED72 = 72|0x100U, /**< XBARA1_IN72 input is reserved. */
kXBARA1_InputRESERVED73 = 73|0x100U, /**< XBARA1_IN73 input is reserved. */
kXBARA1_InputFlexpwm1Pwm0OutTrig0 = 74|0x100U, /**< FLEXPWM1_PWM0_OUT_TRIG0 output assigned to XBARA1_IN74 input. */
kXBARA1_InputFlexpwm1Pwm0OutTrig1 = 75|0x100U, /**< FLEXPWM1_PWM0_OUT_TRIG1 output assigned to XBARA1_IN75 input. */
kXBARA1_InputFlexpwm1Pwm1OutTrig0 = 76|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG0 output assigned to XBARA1_IN76 input. */
kXBARA1_InputFlexpwm1Pwm1OutTrig1 = 77|0x100U, /**< FLEXPWM1_PWM1_OUT_TRIG1 output assigned to XBARA1_IN77 input. */
kXBARA1_InputFlexpwm1Pwm2OutTrig0 = 78|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG0 output assigned to XBARA1_IN78 input. */
kXBARA1_InputFlexpwm1Pwm2OutTrig1 = 79|0x100U, /**< FLEXPWM1_PWM2_OUT_TRIG1 output assigned to XBARA1_IN79 input. */
kXBARA1_InputFlexpwm1Pwm3OutTrig0 = 80|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG0 output assigned to XBARA1_IN80 input. */
kXBARA1_InputFlexpwm1Pwm3OutTrig1 = 81|0x100U, /**< FLEXPWM1_PWM3_OUT_TRIG1 output assigned to XBARA1_IN81 input. */
kXBARA1_InputFlexpwm2Pwm0OutTrig01 = 82|0x100U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN82 input. */
kXBARA1_InputFlexpwm2Pwm1OutTrig01 = 83|0x100U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN83 input. */
kXBARA1_InputFlexpwm2Pwm2OutTrig01 = 84|0x100U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN84 input. */
kXBARA1_InputFlexpwm2Pwm3OutTrig01 = 85|0x100U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN85 input. */
kXBARA1_InputFlexpwm3Pwm0OutTrig01 = 86|0x100U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN86 input. */
kXBARA1_InputFlexpwm3Pwm1OutTrig01 = 87|0x100U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN87 input. */
kXBARA1_InputFlexpwm3Pwm2OutTrig01 = 88|0x100U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN88 input. */
kXBARA1_InputFlexpwm3Pwm3OutTrig01 = 89|0x100U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN89 input. */
kXBARA1_InputFlexpwm4Pwm0OutTrig01 = 90|0x100U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARA1_IN90 input. */
kXBARA1_InputFlexpwm4Pwm1OutTrig01 = 91|0x100U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARA1_IN91 input. */
kXBARA1_InputFlexpwm4Pwm2OutTrig01 = 92|0x100U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARA1_IN92 input. */
kXBARA1_InputFlexpwm4Pwm3OutTrig01 = 93|0x100U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARA1_IN93 input. */
kXBARA1_InputRESERVED94 = 94|0x100U, /**< XBARA1_IN94 input is reserved. */
kXBARA1_InputRESERVED95 = 95|0x100U, /**< XBARA1_IN95 input is reserved. */
kXBARA1_InputRESERVED96 = 96|0x100U, /**< XBARA1_IN96 input is reserved. */
kXBARA1_InputRESERVED97 = 97|0x100U, /**< XBARA1_IN97 input is reserved. */
kXBARA1_InputRESERVED98 = 98|0x100U, /**< XBARA1_IN98 input is reserved. */
kXBARA1_InputRESERVED99 = 99|0x100U, /**< XBARA1_IN99 input is reserved. */
kXBARA1_InputRESERVED100 = 100|0x100U, /**< XBARA1_IN100 input is reserved. */
kXBARA1_InputRESERVED101 = 101|0x100U, /**< XBARA1_IN101 input is reserved. */
kXBARA1_InputPit1Trigger0 = 102|0x100U, /**< PIT1_TRIGGER0 output assigned to XBARA1_IN102 input. */
kXBARA1_InputPit1Trigger1 = 103|0x100U, /**< PIT1_TRIGGER1 output assigned to XBARA1_IN103 input. */
kXBARA1_InputPit1Trigger2 = 104|0x100U, /**< PIT1_TRIGGER2 output assigned to XBARA1_IN104 input. */
kXBARA1_InputPit1Trigger3 = 105|0x100U, /**< PIT1_TRIGGER3 output assigned to XBARA1_IN105 input. */
kXBARA1_InputDec1PosMatch = 106|0x100U, /**< DEC1_POS_MATCH output assigned to XBARA1_IN106 input. */
kXBARA1_InputDec2PosMatch = 107|0x100U, /**< DEC2_POS_MATCH output assigned to XBARA1_IN107 input. */
kXBARA1_InputDec3PosMatch = 108|0x100U, /**< DEC3_POS_MATCH output assigned to XBARA1_IN108 input. */
kXBARA1_InputDec4PosMatch = 109|0x100U, /**< DEC4_POS_MATCH output assigned to XBARA1_IN109 input. */
kXBARA1_InputRESERVED110 = 110|0x100U, /**< XBARA1_IN110 input is reserved. */
kXBARA1_InputRESERVED111 = 111|0x100U, /**< XBARA1_IN111 input is reserved. */
kXBARA1_InputDmaDone0 = 112|0x100U, /**< DMA_DONE0 output assigned to XBARA1_IN112 input. */
kXBARA1_InputDmaDone1 = 113|0x100U, /**< DMA_DONE1 output assigned to XBARA1_IN113 input. */
kXBARA1_InputDmaDone2 = 114|0x100U, /**< DMA_DONE2 output assigned to XBARA1_IN114 input. */
kXBARA1_InputDmaDone3 = 115|0x100U, /**< DMA_DONE3 output assigned to XBARA1_IN115 input. */
kXBARA1_InputDmaDone4 = 116|0x100U, /**< DMA_DONE4 output assigned to XBARA1_IN116 input. */
kXBARA1_InputDmaDone5 = 117|0x100U, /**< DMA_DONE5 output assigned to XBARA1_IN117 input. */
kXBARA1_InputDmaDone6 = 118|0x100U, /**< DMA_DONE6 output assigned to XBARA1_IN118 input. */
kXBARA1_InputDmaDone7 = 119|0x100U, /**< DMA_DONE7 output assigned to XBARA1_IN119 input. */
kXBARA1_InputDmaLpsrDone0 = 120|0x100U, /**< DMA_LPSR_DONE0 output assigned to XBARA1_IN120 input. */
kXBARA1_InputDmaLpsrDone1 = 121|0x100U, /**< DMA_LPSR_DONE1 output assigned to XBARA1_IN121 input. */
kXBARA1_InputDmaLpsrDone2 = 122|0x100U, /**< DMA_LPSR_DONE2 output assigned to XBARA1_IN122 input. */
kXBARA1_InputDmaLpsrDone3 = 123|0x100U, /**< DMA_LPSR_DONE3 output assigned to XBARA1_IN123 input. */
kXBARA1_InputDmaLpsrDone4 = 124|0x100U, /**< DMA_LPSR_DONE4 output assigned to XBARA1_IN124 input. */
kXBARA1_InputDmaLpsrDone5 = 125|0x100U, /**< DMA_LPSR_DONE5 output assigned to XBARA1_IN125 input. */
kXBARA1_InputDmaLpsrDone6 = 126|0x100U, /**< DMA_LPSR_DONE6 output assigned to XBARA1_IN126 input. */
kXBARA1_InputDmaLpsrDone7 = 127|0x100U, /**< DMA_LPSR_DONE7 output assigned to XBARA1_IN127 input. */
kXBARA1_InputAoi1Out0 = 128|0x100U, /**< AOI1_OUT0 output assigned to XBARA1_IN128 input. */
kXBARA1_InputAoi1Out1 = 129|0x100U, /**< AOI1_OUT1 output assigned to XBARA1_IN129 input. */
kXBARA1_InputAoi1Out2 = 130|0x100U, /**< AOI1_OUT2 output assigned to XBARA1_IN130 input. */
kXBARA1_InputAoi1Out3 = 131|0x100U, /**< AOI1_OUT3 output assigned to XBARA1_IN131 input. */
kXBARA1_InputAoi2Out0 = 132|0x100U, /**< AOI2_OUT0 output assigned to XBARA1_IN132 input. */
kXBARA1_InputAoi2Out1 = 133|0x100U, /**< AOI2_OUT1 output assigned to XBARA1_IN133 input. */
kXBARA1_InputAoi2Out2 = 134|0x100U, /**< AOI2_OUT2 output assigned to XBARA1_IN134 input. */
kXBARA1_InputAoi2Out3 = 135|0x100U, /**< AOI2_OUT3 output assigned to XBARA1_IN135 input. */
kXBARA1_InputAdcEtc0Coco0 = 136|0x100U, /**< ADC_ETC0_COCO0 output assigned to XBARA1_IN136 input. */
kXBARA1_InputAdcEtc0Coco1 = 137|0x100U, /**< ADC_ETC0_COCO1 output assigned to XBARA1_IN137 input. */
kXBARA1_InputAdcEtc0Coco2 = 138|0x100U, /**< ADC_ETC0_COCO2 output assigned to XBARA1_IN138 input. */
kXBARA1_InputAdcEtc0Coco3 = 139|0x100U, /**< ADC_ETC0_COCO3 output assigned to XBARA1_IN139 input. */
kXBARA1_InputAdcEtc1Coco0 = 140|0x100U, /**< ADC_ETC1_COCO0 output assigned to XBARA1_IN140 input. */
kXBARA1_InputAdcEtc1Coco1 = 141|0x100U, /**< ADC_ETC1_COCO1 output assigned to XBARA1_IN141 input. */
kXBARA1_InputAdcEtc1Coco2 = 142|0x100U, /**< ADC_ETC1_COCO2 output assigned to XBARA1_IN142 input. */
kXBARA1_InputAdcEtc1Coco3 = 143|0x100U, /**< ADC_ETC1_COCO3 output assigned to XBARA1_IN143 input. */
kXBARB2_InputLogicLow = 0|0x200U, /**< LOGIC_LOW output assigned to XBARB2_IN0 input. */
kXBARB2_InputLogicHigh = 1|0x200U, /**< LOGIC_HIGH output assigned to XBARB2_IN1 input. */
kXBARB2_InputAcmp1Out = 2|0x200U, /**< ACMP1_OUT output assigned to XBARB2_IN2 input. */
kXBARB2_InputAcmp2Out = 3|0x200U, /**< ACMP2_OUT output assigned to XBARB2_IN3 input. */
kXBARB2_InputAcmp3Out = 4|0x200U, /**< ACMP3_OUT output assigned to XBARB2_IN4 input. */
kXBARB2_InputAcmp4Out = 5|0x200U, /**< ACMP4_OUT output assigned to XBARB2_IN5 input. */
kXBARB2_InputRESERVED6 = 6|0x200U, /**< XBARB2_IN6 input is reserved. */
kXBARB2_InputRESERVED7 = 7|0x200U, /**< XBARB2_IN7 input is reserved. */
kXBARB2_InputRESERVED8 = 8|0x200U, /**< XBARB2_IN8 input is reserved. */
kXBARB2_InputRESERVED9 = 9|0x200U, /**< XBARB2_IN9 input is reserved. */
kXBARB2_InputQtimer1Timer0 = 10|0x200U, /**< QTIMER1_TIMER0 output assigned to XBARB2_IN10 input. */
kXBARB2_InputQtimer1Timer1 = 11|0x200U, /**< QTIMER1_TIMER1 output assigned to XBARB2_IN11 input. */
kXBARB2_InputQtimer1Timer2 = 12|0x200U, /**< QTIMER1_TIMER2 output assigned to XBARB2_IN12 input. */
kXBARB2_InputQtimer1Timer3 = 13|0x200U, /**< QTIMER1_TIMER3 output assigned to XBARB2_IN13 input. */
kXBARB2_InputQtimer2Timer0 = 14|0x200U, /**< QTIMER2_TIMER0 output assigned to XBARB2_IN14 input. */
kXBARB2_InputQtimer2Timer1 = 15|0x200U, /**< QTIMER2_TIMER1 output assigned to XBARB2_IN15 input. */
kXBARB2_InputQtimer2Timer2 = 16|0x200U, /**< QTIMER2_TIMER2 output assigned to XBARB2_IN16 input. */
kXBARB2_InputQtimer2Timer3 = 17|0x200U, /**< QTIMER2_TIMER3 output assigned to XBARB2_IN17 input. */
kXBARB2_InputQtimer3Timer0 = 18|0x200U, /**< QTIMER3_TIMER0 output assigned to XBARB2_IN18 input. */
kXBARB2_InputQtimer3Timer1 = 19|0x200U, /**< QTIMER3_TIMER1 output assigned to XBARB2_IN19 input. */
kXBARB2_InputQtimer3Timer2 = 20|0x200U, /**< QTIMER3_TIMER2 output assigned to XBARB2_IN20 input. */
kXBARB2_InputQtimer3Timer3 = 21|0x200U, /**< QTIMER3_TIMER3 output assigned to XBARB2_IN21 input. */
kXBARB2_InputQtimer4Timer0 = 22|0x200U, /**< QTIMER4_TIMER0 output assigned to XBARB2_IN22 input. */
kXBARB2_InputQtimer4Timer1 = 23|0x200U, /**< QTIMER4_TIMER1 output assigned to XBARB2_IN23 input. */
kXBARB2_InputQtimer4Timer2 = 24|0x200U, /**< QTIMER4_TIMER2 output assigned to XBARB2_IN24 input. */
kXBARB2_InputQtimer4Timer3 = 25|0x200U, /**< QTIMER4_TIMER3 output assigned to XBARB2_IN25 input. */
kXBARB2_InputRESERVED26 = 26|0x200U, /**< XBARB2_IN26 input is reserved. */
kXBARB2_InputRESERVED27 = 27|0x200U, /**< XBARB2_IN27 input is reserved. */
kXBARB2_InputRESERVED28 = 28|0x200U, /**< XBARB2_IN28 input is reserved. */
kXBARB2_InputRESERVED29 = 29|0x200U, /**< XBARB2_IN29 input is reserved. */
kXBARB2_InputRESERVED30 = 30|0x200U, /**< XBARB2_IN30 input is reserved. */
kXBARB2_InputRESERVED31 = 31|0x200U, /**< XBARB2_IN31 input is reserved. */
kXBARB2_InputRESERVED32 = 32|0x200U, /**< XBARB2_IN32 input is reserved. */
kXBARB2_InputRESERVED33 = 33|0x200U, /**< XBARB2_IN33 input is reserved. */
kXBARB2_InputFlexpwm1Pwm0OutTrig01 = 34|0x200U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN34 input. */
kXBARB2_InputFlexpwm1Pwm1OutTrig01 = 35|0x200U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN35 input. */
kXBARB2_InputFlexpwm1Pwm2OutTrig01 = 36|0x200U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN36 input. */
kXBARB2_InputFlexpwm1Pwm3OutTrig01 = 37|0x200U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN37 input. */
kXBARB2_InputFlexpwm2Pwm0OutTrig01 = 38|0x200U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN38 input. */
kXBARB2_InputFlexpwm2Pwm1OutTrig01 = 39|0x200U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN39 input. */
kXBARB2_InputFlexpwm2Pwm2OutTrig01 = 40|0x200U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN40 input. */
kXBARB2_InputFlexpwm2Pwm3OutTrig01 = 41|0x200U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN41 input. */
kXBARB2_InputFlexpwm3Pwm0OutTrig01 = 42|0x200U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN42 input. */
kXBARB2_InputFlexpwm3Pwm1OutTrig01 = 43|0x200U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN43 input. */
kXBARB2_InputFlexpwm3Pwm2OutTrig01 = 44|0x200U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN44 input. */
kXBARB2_InputFlexpwm3Pwm3OutTrig01 = 45|0x200U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN45 input. */
kXBARB2_InputFlexpwm4Pwm0OutTrig01 = 46|0x200U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB2_IN46 input. */
kXBARB2_InputFlexpwm4Pwm1OutTrig01 = 47|0x200U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB2_IN47 input. */
kXBARB2_InputFlexpwm4Pwm2OutTrig01 = 48|0x200U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB2_IN48 input. */
kXBARB2_InputFlexpwm4Pwm3OutTrig01 = 49|0x200U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB2_IN49 input. */
kXBARB2_InputRESERVED50 = 50|0x200U, /**< XBARB2_IN50 input is reserved. */
kXBARB2_InputRESERVED51 = 51|0x200U, /**< XBARB2_IN51 input is reserved. */
kXBARB2_InputRESERVED52 = 52|0x200U, /**< XBARB2_IN52 input is reserved. */
kXBARB2_InputRESERVED53 = 53|0x200U, /**< XBARB2_IN53 input is reserved. */
kXBARB2_InputRESERVED54 = 54|0x200U, /**< XBARB2_IN54 input is reserved. */
kXBARB2_InputRESERVED55 = 55|0x200U, /**< XBARB2_IN55 input is reserved. */
kXBARB2_InputRESERVED56 = 56|0x200U, /**< XBARB2_IN56 input is reserved. */
kXBARB2_InputRESERVED57 = 57|0x200U, /**< XBARB2_IN57 input is reserved. */
kXBARB2_InputPit1Trigger0 = 58|0x200U, /**< PIT1_TRIGGER0 output assigned to XBARB2_IN58 input. */
kXBARB2_InputPit1Trigger1 = 59|0x200U, /**< PIT1_TRIGGER1 output assigned to XBARB2_IN59 input. */
kXBARB2_InputAdcEtc0Coco0 = 60|0x200U, /**< ADC_ETC0_COCO0 output assigned to XBARB2_IN60 input. */
kXBARB2_InputAdcEtc0Coco1 = 61|0x200U, /**< ADC_ETC0_COCO1 output assigned to XBARB2_IN61 input. */
kXBARB2_InputAdcEtc0Coco2 = 62|0x200U, /**< ADC_ETC0_COCO2 output assigned to XBARB2_IN62 input. */
kXBARB2_InputAdcEtc0Coco3 = 63|0x200U, /**< ADC_ETC0_COCO3 output assigned to XBARB2_IN63 input. */
kXBARB2_InputAdcEtc1Coco0 = 64|0x200U, /**< ADC_ETC1_COCO0 output assigned to XBARB2_IN64 input. */
kXBARB2_InputAdcEtc1Coco1 = 65|0x200U, /**< ADC_ETC1_COCO1 output assigned to XBARB2_IN65 input. */
kXBARB2_InputAdcEtc1Coco2 = 66|0x200U, /**< ADC_ETC1_COCO2 output assigned to XBARB2_IN66 input. */
kXBARB2_InputAdcEtc1Coco3 = 67|0x200U, /**< ADC_ETC1_COCO3 output assigned to XBARB2_IN67 input. */
kXBARB2_InputRESERVED68 = 68|0x200U, /**< XBARB2_IN68 input is reserved. */
kXBARB2_InputRESERVED69 = 69|0x200U, /**< XBARB2_IN69 input is reserved. */
kXBARB2_InputRESERVED70 = 70|0x200U, /**< XBARB2_IN70 input is reserved. */
kXBARB2_InputRESERVED71 = 71|0x200U, /**< XBARB2_IN71 input is reserved. */
kXBARB2_InputRESERVED72 = 72|0x200U, /**< XBARB2_IN72 input is reserved. */
kXBARB2_InputRESERVED73 = 73|0x200U, /**< XBARB2_IN73 input is reserved. */
kXBARB2_InputRESERVED74 = 74|0x200U, /**< XBARB2_IN74 input is reserved. */
kXBARB2_InputRESERVED75 = 75|0x200U, /**< XBARB2_IN75 input is reserved. */
kXBARB2_InputDec1PosMatch = 76|0x200U, /**< DEC1_POS_MATCH output assigned to XBARB2_IN76 input. */
kXBARB2_InputDec2PosMatch = 77|0x200U, /**< DEC2_POS_MATCH output assigned to XBARB2_IN77 input. */
kXBARB2_InputDec3PosMatch = 78|0x200U, /**< DEC3_POS_MATCH output assigned to XBARB2_IN78 input. */
kXBARB2_InputDec4PosMatch = 79|0x200U, /**< DEC4_POS_MATCH output assigned to XBARB2_IN79 input. */
kXBARB2_InputRESERVED80 = 80|0x200U, /**< XBARB2_IN80 input is reserved. */
kXBARB2_InputRESERVED81 = 81|0x200U, /**< XBARB2_IN81 input is reserved. */
kXBARB2_InputDmaDone0 = 82|0x200U, /**< DMA_DONE0 output assigned to XBARB2_IN82 input. */
kXBARB2_InputDmaDone1 = 83|0x200U, /**< DMA_DONE1 output assigned to XBARB2_IN83 input. */
kXBARB2_InputDmaDone2 = 84|0x200U, /**< DMA_DONE2 output assigned to XBARB2_IN84 input. */
kXBARB2_InputDmaDone3 = 85|0x200U, /**< DMA_DONE3 output assigned to XBARB2_IN85 input. */
kXBARB2_InputDmaDone4 = 86|0x200U, /**< DMA_DONE4 output assigned to XBARB2_IN86 input. */
kXBARB2_InputDmaDone5 = 87|0x200U, /**< DMA_DONE5 output assigned to XBARB2_IN87 input. */
kXBARB2_InputDmaDone6 = 88|0x200U, /**< DMA_DONE6 output assigned to XBARB2_IN88 input. */
kXBARB2_InputDmaDone7 = 89|0x200U, /**< DMA_DONE7 output assigned to XBARB2_IN89 input. */
kXBARB2_InputDmaLpsrDone0 = 90|0x200U, /**< DMA_LPSR_DONE0 output assigned to XBARB2_IN90 input. */
kXBARB2_InputDmaLpsrDone1 = 91|0x200U, /**< DMA_LPSR_DONE1 output assigned to XBARB2_IN91 input. */
kXBARB2_InputDmaLpsrDone2 = 92|0x200U, /**< DMA_LPSR_DONE2 output assigned to XBARB2_IN92 input. */
kXBARB2_InputDmaLpsrDone3 = 93|0x200U, /**< DMA_LPSR_DONE3 output assigned to XBARB2_IN93 input. */
kXBARB2_InputDmaLpsrDone4 = 94|0x200U, /**< DMA_LPSR_DONE4 output assigned to XBARB2_IN94 input. */
kXBARB2_InputDmaLpsrDone5 = 95|0x200U, /**< DMA_LPSR_DONE5 output assigned to XBARB2_IN95 input. */
kXBARB2_InputDmaLpsrDone6 = 96|0x200U, /**< DMA_LPSR_DONE6 output assigned to XBARB2_IN96 input. */
kXBARB2_InputDmaLpsrDone7 = 97|0x200U, /**< DMA_LPSR_DONE7 output assigned to XBARB2_IN97 input. */
kXBARB3_InputLogicLow = 0|0x300U, /**< LOGIC_LOW output assigned to XBARB3_IN0 input. */
kXBARB3_InputLogicHigh = 1|0x300U, /**< LOGIC_HIGH output assigned to XBARB3_IN1 input. */
kXBARB3_InputAcmp1Out = 2|0x300U, /**< ACMP1_OUT output assigned to XBARB3_IN2 input. */
kXBARB3_InputAcmp2Out = 3|0x300U, /**< ACMP2_OUT output assigned to XBARB3_IN3 input. */
kXBARB3_InputAcmp3Out = 4|0x300U, /**< ACMP3_OUT output assigned to XBARB3_IN4 input. */
kXBARB3_InputAcmp4Out = 5|0x300U, /**< ACMP4_OUT output assigned to XBARB3_IN5 input. */
kXBARB3_InputRESERVED6 = 6|0x300U, /**< XBARB3_IN6 input is reserved. */
kXBARB3_InputRESERVED7 = 7|0x300U, /**< XBARB3_IN7 input is reserved. */
kXBARB3_InputRESERVED8 = 8|0x300U, /**< XBARB3_IN8 input is reserved. */
kXBARB3_InputRESERVED9 = 9|0x300U, /**< XBARB3_IN9 input is reserved. */
kXBARB3_InputQtimer1Timer0 = 10|0x300U, /**< QTIMER1_TIMER0 output assigned to XBARB3_IN10 input. */
kXBARB3_InputQtimer1Timer1 = 11|0x300U, /**< QTIMER1_TIMER1 output assigned to XBARB3_IN11 input. */
kXBARB3_InputQtimer1Timer2 = 12|0x300U, /**< QTIMER1_TIMER2 output assigned to XBARB3_IN12 input. */
kXBARB3_InputQtimer1Timer3 = 13|0x300U, /**< QTIMER1_TIMER3 output assigned to XBARB3_IN13 input. */
kXBARB3_InputQtimer2Timer0 = 14|0x300U, /**< QTIMER2_TIMER0 output assigned to XBARB3_IN14 input. */
kXBARB3_InputQtimer2Timer1 = 15|0x300U, /**< QTIMER2_TIMER1 output assigned to XBARB3_IN15 input. */
kXBARB3_InputQtimer2Timer2 = 16|0x300U, /**< QTIMER2_TIMER2 output assigned to XBARB3_IN16 input. */
kXBARB3_InputQtimer2Timer3 = 17|0x300U, /**< QTIMER2_TIMER3 output assigned to XBARB3_IN17 input. */
kXBARB3_InputQtimer3Timer0 = 18|0x300U, /**< QTIMER3_TIMER0 output assigned to XBARB3_IN18 input. */
kXBARB3_InputQtimer3Timer1 = 19|0x300U, /**< QTIMER3_TIMER1 output assigned to XBARB3_IN19 input. */
kXBARB3_InputQtimer3Timer2 = 20|0x300U, /**< QTIMER3_TIMER2 output assigned to XBARB3_IN20 input. */
kXBARB3_InputQtimer3Timer3 = 21|0x300U, /**< QTIMER3_TIMER3 output assigned to XBARB3_IN21 input. */
kXBARB3_InputQtimer4Timer0 = 22|0x300U, /**< QTIMER4_TIMER0 output assigned to XBARB3_IN22 input. */
kXBARB3_InputQtimer4Timer1 = 23|0x300U, /**< QTIMER4_TIMER1 output assigned to XBARB3_IN23 input. */
kXBARB3_InputQtimer4Timer2 = 24|0x300U, /**< QTIMER4_TIMER2 output assigned to XBARB3_IN24 input. */
kXBARB3_InputQtimer4Timer3 = 25|0x300U, /**< QTIMER4_TIMER3 output assigned to XBARB3_IN25 input. */
kXBARB3_InputRESERVED26 = 26|0x300U, /**< XBARB3_IN26 input is reserved. */
kXBARB3_InputRESERVED27 = 27|0x300U, /**< XBARB3_IN27 input is reserved. */
kXBARB3_InputRESERVED28 = 28|0x300U, /**< XBARB3_IN28 input is reserved. */
kXBARB3_InputRESERVED29 = 29|0x300U, /**< XBARB3_IN29 input is reserved. */
kXBARB3_InputRESERVED30 = 30|0x300U, /**< XBARB3_IN30 input is reserved. */
kXBARB3_InputRESERVED31 = 31|0x300U, /**< XBARB3_IN31 input is reserved. */
kXBARB3_InputRESERVED32 = 32|0x300U, /**< XBARB3_IN32 input is reserved. */
kXBARB3_InputRESERVED33 = 33|0x300U, /**< XBARB3_IN33 input is reserved. */
kXBARB3_InputFlexpwm1Pwm0OutTrig01 = 34|0x300U, /**< FLEXPWM1_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN34 input. */
kXBARB3_InputFlexpwm1Pwm1OutTrig01 = 35|0x300U, /**< FLEXPWM1_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN35 input. */
kXBARB3_InputFlexpwm1Pwm2OutTrig01 = 36|0x300U, /**< FLEXPWM1_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN36 input. */
kXBARB3_InputFlexpwm1Pwm3OutTrig01 = 37|0x300U, /**< FLEXPWM1_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN37 input. */
kXBARB3_InputFlexpwm2Pwm0OutTrig01 = 38|0x300U, /**< FLEXPWM2_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN38 input. */
kXBARB3_InputFlexpwm2Pwm1OutTrig01 = 39|0x300U, /**< FLEXPWM2_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN39 input. */
kXBARB3_InputFlexpwm2Pwm2OutTrig01 = 40|0x300U, /**< FLEXPWM2_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN40 input. */
kXBARB3_InputFlexpwm2Pwm3OutTrig01 = 41|0x300U, /**< FLEXPWM2_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN41 input. */
kXBARB3_InputFlexpwm3Pwm0OutTrig01 = 42|0x300U, /**< FLEXPWM3_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN42 input. */
kXBARB3_InputFlexpwm3Pwm1OutTrig01 = 43|0x300U, /**< FLEXPWM3_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN43 input. */
kXBARB3_InputFlexpwm3Pwm2OutTrig01 = 44|0x300U, /**< FLEXPWM3_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN44 input. */
kXBARB3_InputFlexpwm3Pwm3OutTrig01 = 45|0x300U, /**< FLEXPWM3_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN45 input. */
kXBARB3_InputFlexpwm4Pwm0OutTrig01 = 46|0x300U, /**< FLEXPWM4_PWM0_OUT_TRIG0_1 output assigned to XBARB3_IN46 input. */
kXBARB3_InputFlexpwm4Pwm1OutTrig01 = 47|0x300U, /**< FLEXPWM4_PWM1_OUT_TRIG0_1 output assigned to XBARB3_IN47 input. */
kXBARB3_InputFlexpwm4Pwm2OutTrig01 = 48|0x300U, /**< FLEXPWM4_PWM2_OUT_TRIG0_1 output assigned to XBARB3_IN48 input. */
kXBARB3_InputFlexpwm4Pwm3OutTrig01 = 49|0x300U, /**< FLEXPWM4_PWM3_OUT_TRIG0_1 output assigned to XBARB3_IN49 input. */
kXBARB3_InputRESERVED50 = 50|0x300U, /**< XBARB3_IN50 input is reserved. */
kXBARB3_InputRESERVED51 = 51|0x300U, /**< XBARB3_IN51 input is reserved. */
kXBARB3_InputRESERVED52 = 52|0x300U, /**< XBARB3_IN52 input is reserved. */
kXBARB3_InputRESERVED53 = 53|0x300U, /**< XBARB3_IN53 input is reserved. */
kXBARB3_InputRESERVED54 = 54|0x300U, /**< XBARB3_IN54 input is reserved. */
kXBARB3_InputRESERVED55 = 55|0x300U, /**< XBARB3_IN55 input is reserved. */
kXBARB3_InputRESERVED56 = 56|0x300U, /**< XBARB3_IN56 input is reserved. */
kXBARB3_InputRESERVED57 = 57|0x300U, /**< XBARB3_IN57 input is reserved. */
kXBARB3_InputPit1Trigger0 = 58|0x300U, /**< PIT1_TRIGGER0 output assigned to XBARB3_IN58 input. */
kXBARB3_InputPit1Trigger1 = 59|0x300U, /**< PIT1_TRIGGER1 output assigned to XBARB3_IN59 input. */
kXBARB3_InputAdcEtc0Coco0 = 60|0x300U, /**< ADC_ETC0_COCO0 output assigned to XBARB3_IN60 input. */
kXBARB3_InputAdcEtc0Coco1 = 61|0x300U, /**< ADC_ETC0_COCO1 output assigned to XBARB3_IN61 input. */
kXBARB3_InputAdcEtc0Coco2 = 62|0x300U, /**< ADC_ETC0_COCO2 output assigned to XBARB3_IN62 input. */
kXBARB3_InputAdcEtc0Coco3 = 63|0x300U, /**< ADC_ETC0_COCO3 output assigned to XBARB3_IN63 input. */
kXBARB3_InputAdcEtc1Coco0 = 64|0x300U, /**< ADC_ETC1_COCO0 output assigned to XBARB3_IN64 input. */
kXBARB3_InputAdcEtc1Coco1 = 65|0x300U, /**< ADC_ETC1_COCO1 output assigned to XBARB3_IN65 input. */
kXBARB3_InputAdcEtc1Coco2 = 66|0x300U, /**< ADC_ETC1_COCO2 output assigned to XBARB3_IN66 input. */
kXBARB3_InputAdcEtc1Coco3 = 67|0x300U, /**< ADC_ETC1_COCO3 output assigned to XBARB3_IN67 input. */
kXBARB3_InputRESERVED68 = 68|0x300U, /**< XBARB3_IN68 input is reserved. */
kXBARB3_InputRESERVED69 = 69|0x300U, /**< XBARB3_IN69 input is reserved. */
kXBARB3_InputRESERVED70 = 70|0x300U, /**< XBARB3_IN70 input is reserved. */
kXBARB3_InputRESERVED71 = 71|0x300U, /**< XBARB3_IN71 input is reserved. */
kXBARB3_InputRESERVED72 = 72|0x300U, /**< XBARB3_IN72 input is reserved. */
kXBARB3_InputRESERVED73 = 73|0x300U, /**< XBARB3_IN73 input is reserved. */
kXBARB3_InputRESERVED74 = 74|0x300U, /**< XBARB3_IN74 input is reserved. */
kXBARB3_InputRESERVED75 = 75|0x300U, /**< XBARB3_IN75 input is reserved. */
kXBARB3_InputDec1PosMatch = 76|0x300U, /**< DEC1_POS_MATCH output assigned to XBARB3_IN76 input. */
kXBARB3_InputDec2PosMatch = 77|0x300U, /**< DEC2_POS_MATCH output assigned to XBARB3_IN77 input. */
kXBARB3_InputDec3PosMatch = 78|0x300U, /**< DEC3_POS_MATCH output assigned to XBARB3_IN78 input. */
kXBARB3_InputDec4PosMatch = 79|0x300U, /**< DEC4_POS_MATCH output assigned to XBARB3_IN79 input. */
kXBARB3_InputRESERVED80 = 80|0x300U, /**< XBARB3_IN80 input is reserved. */
kXBARB3_InputRESERVED81 = 81|0x300U, /**< XBARB3_IN81 input is reserved. */
kXBARB3_InputDmaDone0 = 82|0x300U, /**< DMA_DONE0 output assigned to XBARB3_IN82 input. */
kXBARB3_InputDmaDone1 = 83|0x300U, /**< DMA_DONE1 output assigned to XBARB3_IN83 input. */
kXBARB3_InputDmaDone2 = 84|0x300U, /**< DMA_DONE2 output assigned to XBARB3_IN84 input. */
kXBARB3_InputDmaDone3 = 85|0x300U, /**< DMA_DONE3 output assigned to XBARB3_IN85 input. */
kXBARB3_InputDmaDone4 = 86|0x300U, /**< DMA_DONE4 output assigned to XBARB3_IN86 input. */
kXBARB3_InputDmaDone5 = 87|0x300U, /**< DMA_DONE5 output assigned to XBARB3_IN87 input. */
kXBARB3_InputDmaDone6 = 88|0x300U, /**< DMA_DONE6 output assigned to XBARB3_IN88 input. */
kXBARB3_InputDmaDone7 = 89|0x300U, /**< DMA_DONE7 output assigned to XBARB3_IN89 input. */
kXBARB3_InputDmaLpsrDone0 = 90|0x300U, /**< DMA_LPSR_DONE0 output assigned to XBARB3_IN90 input. */
kXBARB3_InputDmaLpsrDone1 = 91|0x300U, /**< DMA_LPSR_DONE1 output assigned to XBARB3_IN91 input. */
kXBARB3_InputDmaLpsrDone2 = 92|0x300U, /**< DMA_LPSR_DONE2 output assigned to XBARB3_IN92 input. */
kXBARB3_InputDmaLpsrDone3 = 93|0x300U, /**< DMA_LPSR_DONE3 output assigned to XBARB3_IN93 input. */
kXBARB3_InputDmaLpsrDone4 = 94|0x300U, /**< DMA_LPSR_DONE4 output assigned to XBARB3_IN94 input. */
kXBARB3_InputDmaLpsrDone5 = 95|0x300U, /**< DMA_LPSR_DONE5 output assigned to XBARB3_IN95 input. */
kXBARB3_InputDmaLpsrDone6 = 96|0x300U, /**< DMA_LPSR_DONE6 output assigned to XBARB3_IN96 input. */
kXBARB3_InputDmaLpsrDone7 = 97|0x300U, /**< DMA_LPSR_DONE7 output assigned to XBARB3_IN97 input. */
} xbar_input_signal_t;
typedef enum _xbar_output_signal
{
kXBARA1_OutputDmaChMuxReq81 = 0|0x100U, /**< XBARA1_OUT0 output assigned to DMA_CH_MUX_REQ81 */
kXBARA1_OutputDmaChMuxReq82 = 1|0x100U, /**< XBARA1_OUT1 output assigned to DMA_CH_MUX_REQ82 */
kXBARA1_OutputDmaChMuxReq83 = 2|0x100U, /**< XBARA1_OUT2 output assigned to DMA_CH_MUX_REQ83 */
kXBARA1_OutputDmaChMuxReq84 = 3|0x100U, /**< XBARA1_OUT3 output assigned to DMA_CH_MUX_REQ84 */
kXBARA1_OutputIomuxXbarInout04 = 4|0x100U, /**< XBARA1_OUT4 output assigned to IOMUX_XBAR_INOUT04 */
kXBARA1_OutputIomuxXbarInout05 = 5|0x100U, /**< XBARA1_OUT5 output assigned to IOMUX_XBAR_INOUT05 */
kXBARA1_OutputIomuxXbarInout06 = 6|0x100U, /**< XBARA1_OUT6 output assigned to IOMUX_XBAR_INOUT06 */
kXBARA1_OutputIomuxXbarInout07 = 7|0x100U, /**< XBARA1_OUT7 output assigned to IOMUX_XBAR_INOUT07 */
kXBARA1_OutputIomuxXbarInout08 = 8|0x100U, /**< XBARA1_OUT8 output assigned to IOMUX_XBAR_INOUT08 */
kXBARA1_OutputIomuxXbarInout09 = 9|0x100U, /**< XBARA1_OUT9 output assigned to IOMUX_XBAR_INOUT09 */
kXBARA1_OutputIomuxXbarInout10 = 10|0x100U, /**< XBARA1_OUT10 output assigned to IOMUX_XBAR_INOUT10 */
kXBARA1_OutputIomuxXbarInout11 = 11|0x100U, /**< XBARA1_OUT11 output assigned to IOMUX_XBAR_INOUT11 */
kXBARA1_OutputIomuxXbarInout12 = 12|0x100U, /**< XBARA1_OUT12 output assigned to IOMUX_XBAR_INOUT12 */
kXBARA1_OutputIomuxXbarInout13 = 13|0x100U, /**< XBARA1_OUT13 output assigned to IOMUX_XBAR_INOUT13 */
kXBARA1_OutputIomuxXbarInout14 = 14|0x100U, /**< XBARA1_OUT14 output assigned to IOMUX_XBAR_INOUT14 */
kXBARA1_OutputIomuxXbarInout15 = 15|0x100U, /**< XBARA1_OUT15 output assigned to IOMUX_XBAR_INOUT15 */
kXBARA1_OutputIomuxXbarInout16 = 16|0x100U, /**< XBARA1_OUT16 output assigned to IOMUX_XBAR_INOUT16 */
kXBARA1_OutputIomuxXbarInout17 = 17|0x100U, /**< XBARA1_OUT17 output assigned to IOMUX_XBAR_INOUT17 */
kXBARA1_OutputIomuxXbarInout18 = 18|0x100U, /**< XBARA1_OUT18 output assigned to IOMUX_XBAR_INOUT18 */
kXBARA1_OutputIomuxXbarInout19 = 19|0x100U, /**< XBARA1_OUT19 output assigned to IOMUX_XBAR_INOUT19 */
kXBARA1_OutputIomuxXbarInout20 = 20|0x100U, /**< XBARA1_OUT20 output assigned to IOMUX_XBAR_INOUT20 */
kXBARA1_OutputIomuxXbarInout21 = 21|0x100U, /**< XBARA1_OUT21 output assigned to IOMUX_XBAR_INOUT21 */
kXBARA1_OutputIomuxXbarInout22 = 22|0x100U, /**< XBARA1_OUT22 output assigned to IOMUX_XBAR_INOUT22 */
kXBARA1_OutputIomuxXbarInout23 = 23|0x100U, /**< XBARA1_OUT23 output assigned to IOMUX_XBAR_INOUT23 */
kXBARA1_OutputIomuxXbarInout24 = 24|0x100U, /**< XBARA1_OUT24 output assigned to IOMUX_XBAR_INOUT24 */
kXBARA1_OutputIomuxXbarInout25 = 25|0x100U, /**< XBARA1_OUT25 output assigned to IOMUX_XBAR_INOUT25 */
kXBARA1_OutputIomuxXbarInout26 = 26|0x100U, /**< XBARA1_OUT26 output assigned to IOMUX_XBAR_INOUT26 */
kXBARA1_OutputIomuxXbarInout27 = 27|0x100U, /**< XBARA1_OUT27 output assigned to IOMUX_XBAR_INOUT27 */
kXBARA1_OutputIomuxXbarInout28 = 28|0x100U, /**< XBARA1_OUT28 output assigned to IOMUX_XBAR_INOUT28 */
kXBARA1_OutputIomuxXbarInout29 = 29|0x100U, /**< XBARA1_OUT29 output assigned to IOMUX_XBAR_INOUT29 */
kXBARA1_OutputIomuxXbarInout30 = 30|0x100U, /**< XBARA1_OUT30 output assigned to IOMUX_XBAR_INOUT30 */
kXBARA1_OutputIomuxXbarInout31 = 31|0x100U, /**< XBARA1_OUT31 output assigned to IOMUX_XBAR_INOUT31 */
kXBARA1_OutputIomuxXbarInout32 = 32|0x100U, /**< XBARA1_OUT32 output assigned to IOMUX_XBAR_INOUT32 */
kXBARA1_OutputIomuxXbarInout33 = 33|0x100U, /**< XBARA1_OUT33 output assigned to IOMUX_XBAR_INOUT33 */
kXBARA1_OutputIomuxXbarInout34 = 34|0x100U, /**< XBARA1_OUT34 output assigned to IOMUX_XBAR_INOUT34 */
kXBARA1_OutputIomuxXbarInout35 = 35|0x100U, /**< XBARA1_OUT35 output assigned to IOMUX_XBAR_INOUT35 */
kXBARA1_OutputIomuxXbarInout36 = 36|0x100U, /**< XBARA1_OUT36 output assigned to IOMUX_XBAR_INOUT36 */
kXBARA1_OutputIomuxXbarInout37 = 37|0x100U, /**< XBARA1_OUT37 output assigned to IOMUX_XBAR_INOUT37 */
kXBARA1_OutputIomuxXbarInout38 = 38|0x100U, /**< XBARA1_OUT38 output assigned to IOMUX_XBAR_INOUT38 */
kXBARA1_OutputIomuxXbarInout39 = 39|0x100U, /**< XBARA1_OUT39 output assigned to IOMUX_XBAR_INOUT39 */
kXBARA1_OutputIomuxXbarInout40 = 40|0x100U, /**< XBARA1_OUT40 output assigned to IOMUX_XBAR_INOUT40 */
kXBARA1_OutputAcmp1Sample = 41|0x100U, /**< XBARA1_OUT41 output assigned to ACMP1_SAMPLE */
kXBARA1_OutputAcmp2Sample = 42|0x100U, /**< XBARA1_OUT42 output assigned to ACMP2_SAMPLE */
kXBARA1_OutputAcmp3Sample = 43|0x100U, /**< XBARA1_OUT43 output assigned to ACMP3_SAMPLE */
kXBARA1_OutputAcmp4Sample = 44|0x100U, /**< XBARA1_OUT44 output assigned to ACMP4_SAMPLE */
kXBARA1_OutputRESERVED45 = 45|0x100U, /**< XBARA1_OUT45 output is reserved. */
kXBARA1_OutputRESERVED46 = 46|0x100U, /**< XBARA1_OUT46 output is reserved. */
kXBARA1_OutputRESERVED47 = 47|0x100U, /**< XBARA1_OUT47 output is reserved. */
kXBARA1_OutputRESERVED48 = 48|0x100U, /**< XBARA1_OUT48 output is reserved. */
kXBARA1_OutputFlexpwm1Pwm0Exta = 49|0x100U, /**< XBARA1_OUT49 output assigned to FLEXPWM1_PWM0_EXTA */
kXBARA1_OutputFlexpwm1Pwm1Exta = 50|0x100U, /**< XBARA1_OUT50 output assigned to FLEXPWM1_PWM1_EXTA */
kXBARA1_OutputFlexpwm1Pwm2Exta = 51|0x100U, /**< XBARA1_OUT51 output assigned to FLEXPWM1_PWM2_EXTA */
kXBARA1_OutputFlexpwm1Pwm3Exta = 52|0x100U, /**< XBARA1_OUT52 output assigned to FLEXPWM1_PWM3_EXTA */
kXBARA1_OutputFlexpwm1Pwm0ExtSync = 53|0x100U, /**< XBARA1_OUT53 output assigned to FLEXPWM1_PWM0_EXT_SYNC */
kXBARA1_OutputFlexpwm1Pwm1ExtSync = 54|0x100U, /**< XBARA1_OUT54 output assigned to FLEXPWM1_PWM1_EXT_SYNC */
kXBARA1_OutputFlexpwm1Pwm2ExtSync = 55|0x100U, /**< XBARA1_OUT55 output assigned to FLEXPWM1_PWM2_EXT_SYNC */
kXBARA1_OutputFlexpwm1Pwm3ExtSync = 56|0x100U, /**< XBARA1_OUT56 output assigned to FLEXPWM1_PWM3_EXT_SYNC */
kXBARA1_OutputFlexpwm1ExtClk = 57|0x100U, /**< XBARA1_OUT57 output assigned to FLEXPWM1_EXT_CLK */
kXBARA1_OutputFlexpwm1Fault0 = 58|0x100U, /**< XBARA1_OUT58 output assigned to FLEXPWM1_FAULT0 */
kXBARA1_OutputFlexpwm1Fault1 = 59|0x100U, /**< XBARA1_OUT59 output assigned to FLEXPWM1_FAULT1 */
kXBARA1_OutputFlexpwm1234Fault2 = 60|0x100U, /**< XBARA1_OUT60 output assigned to FLEXPWM1_2_3_4_FAULT2 */
kXBARA1_OutputFlexpwm1234Fault3 = 61|0x100U, /**< XBARA1_OUT61 output assigned to FLEXPWM1_2_3_4_FAULT3 */
kXBARA1_OutputFlexpwm1ExtForce = 62|0x100U, /**< XBARA1_OUT62 output assigned to FLEXPWM1_EXT_FORCE */
kXBARA1_OutputFlexpwm2Pwm0Exta = 63|0x100U, /**< XBARA1_OUT63 output assigned to FLEXPWM2_PWM0_EXTA */
kXBARA1_OutputFlexpwm2Pwm1Exta = 64|0x100U, /**< XBARA1_OUT64 output assigned to FLEXPWM2_PWM1_EXTA */
kXBARA1_OutputFlexpwm2Pwm2Exta = 65|0x100U, /**< XBARA1_OUT65 output assigned to FLEXPWM2_PWM2_EXTA */
kXBARA1_OutputFlexpwm2Pwm3Exta = 66|0x100U, /**< XBARA1_OUT66 output assigned to FLEXPWM2_PWM3_EXTA */
kXBARA1_OutputFlexpwm2Pwm0ExtSync = 67|0x100U, /**< XBARA1_OUT67 output assigned to FLEXPWM2_PWM0_EXT_SYNC */
kXBARA1_OutputFlexpwm2Pwm1ExtSync = 68|0x100U, /**< XBARA1_OUT68 output assigned to FLEXPWM2_PWM1_EXT_SYNC */
kXBARA1_OutputFlexpwm2Pwm2ExtSync = 69|0x100U, /**< XBARA1_OUT69 output assigned to FLEXPWM2_PWM2_EXT_SYNC */
kXBARA1_OutputFlexpwm2Pwm3ExtSync = 70|0x100U, /**< XBARA1_OUT70 output assigned to FLEXPWM2_PWM3_EXT_SYNC */
kXBARA1_OutputFlexpwm2ExtClk = 71|0x100U, /**< XBARA1_OUT71 output assigned to FLEXPWM2_EXT_CLK */
kXBARA1_OutputFlexpwm2Fault0 = 72|0x100U, /**< XBARA1_OUT72 output assigned to FLEXPWM2_FAULT0 */
kXBARA1_OutputFlexpwm2Fault1 = 73|0x100U, /**< XBARA1_OUT73 output assigned to FLEXPWM2_FAULT1 */
kXBARA1_OutputFlexpwm2ExtForce = 74|0x100U, /**< XBARA1_OUT74 output assigned to FLEXPWM2_EXT_FORCE */
kXBARA1_OutputFlexpwm34Pwm0Exta = 75|0x100U, /**< XBARA1_OUT75 output assigned to FLEXPWM3_4_PWM0_EXTA */
kXBARA1_OutputFlexpwm34Pwm1Exta = 76|0x100U, /**< XBARA1_OUT76 output assigned to FLEXPWM3_4_PWM1_EXTA */
kXBARA1_OutputFlexpwm34Pwm2Exta = 77|0x100U, /**< XBARA1_OUT77 output assigned to FLEXPWM3_4_PWM2_EXTA */
kXBARA1_OutputFlexpwm34Pwm3Exta = 78|0x100U, /**< XBARA1_OUT78 output assigned to FLEXPWM3_4_PWM3_EXTA */
kXBARA1_OutputFlexpwm34ExtClk = 79|0x100U, /**< XBARA1_OUT79 output assigned to FLEXPWM3_4_EXT_CLK */
kXBARA1_OutputFlexpwm3Pwm0ExtSync = 80|0x100U, /**< XBARA1_OUT80 output assigned to FLEXPWM3_PWM0_EXT_SYNC */
kXBARA1_OutputFlexpwm3Pwm1ExtSync = 81|0x100U, /**< XBARA1_OUT81 output assigned to FLEXPWM3_PWM1_EXT_SYNC */
kXBARA1_OutputFlexpwm3Pwm2ExtSync = 82|0x100U, /**< XBARA1_OUT82 output assigned to FLEXPWM3_PWM2_EXT_SYNC */
kXBARA1_OutputFlexpwm3Pwm3ExtSync = 83|0x100U, /**< XBARA1_OUT83 output assigned to FLEXPWM3_PWM3_EXT_SYNC */
kXBARA1_OutputFlexpwm3Fault0 = 84|0x100U, /**< XBARA1_OUT84 output assigned to FLEXPWM3_FAULT0 */
kXBARA1_OutputFlexpwm3Fault1 = 85|0x100U, /**< XBARA1_OUT85 output assigned to FLEXPWM3_FAULT1 */
kXBARA1_OutputFlexpwm3ExtForce = 86|0x100U, /**< XBARA1_OUT86 output assigned to FLEXPWM3_EXT_FORCE */
kXBARA1_OutputFlexpwm4Pwm0ExtSync = 87|0x100U, /**< XBARA1_OUT87 output assigned to FLEXPWM4_PWM0_EXT_SYNC */
kXBARA1_OutputFlexpwm4Pwm1ExtSync = 88|0x100U, /**< XBARA1_OUT88 output assigned to FLEXPWM4_PWM1_EXT_SYNC */
kXBARA1_OutputFlexpwm4Pwm2ExtSync = 89|0x100U, /**< XBARA1_OUT89 output assigned to FLEXPWM4_PWM2_EXT_SYNC */
kXBARA1_OutputFlexpwm4Pwm3ExtSync = 90|0x100U, /**< XBARA1_OUT90 output assigned to FLEXPWM4_PWM3_EXT_SYNC */
kXBARA1_OutputFlexpwm4Fault0 = 91|0x100U, /**< XBARA1_OUT91 output assigned to FLEXPWM4_FAULT0 */
kXBARA1_OutputFlexpwm4Fault1 = 92|0x100U, /**< XBARA1_OUT92 output assigned to FLEXPWM4_FAULT1 */
kXBARA1_OutputFlexpwm4ExtForce = 93|0x100U, /**< XBARA1_OUT93 output assigned to FLEXPWM4_EXT_FORCE */
kXBARA1_OutputRESERVED94 = 94|0x100U, /**< XBARA1_OUT94 output is reserved. */
kXBARA1_OutputRESERVED95 = 95|0x100U, /**< XBARA1_OUT95 output is reserved. */
kXBARA1_OutputRESERVED96 = 96|0x100U, /**< XBARA1_OUT96 output is reserved. */
kXBARA1_OutputRESERVED97 = 97|0x100U, /**< XBARA1_OUT97 output is reserved. */
kXBARA1_OutputRESERVED98 = 98|0x100U, /**< XBARA1_OUT98 output is reserved. */
kXBARA1_OutputRESERVED99 = 99|0x100U, /**< XBARA1_OUT99 output is reserved. */
kXBARA1_OutputRESERVED100 = 100|0x100U, /**< XBARA1_OUT100 output is reserved. */
kXBARA1_OutputRESERVED101 = 101|0x100U, /**< XBARA1_OUT101 output is reserved. */
kXBARA1_OutputRESERVED102 = 102|0x100U, /**< XBARA1_OUT102 output is reserved. */
kXBARA1_OutputRESERVED103 = 103|0x100U, /**< XBARA1_OUT103 output is reserved. */
kXBARA1_OutputRESERVED104 = 104|0x100U, /**< XBARA1_OUT104 output is reserved. */
kXBARA1_OutputRESERVED105 = 105|0x100U, /**< XBARA1_OUT105 output is reserved. */
kXBARA1_OutputRESERVED106 = 106|0x100U, /**< XBARA1_OUT106 output is reserved. */
kXBARA1_OutputRESERVED107 = 107|0x100U, /**< XBARA1_OUT107 output is reserved. */
kXBARA1_OutputDec1Phasea = 108|0x100U, /**< XBARA1_OUT108 output assigned to DEC1_PHASEA */
kXBARA1_OutputDec1Phaseb = 109|0x100U, /**< XBARA1_OUT109 output assigned to DEC1_PHASEB */
kXBARA1_OutputDec1Index = 110|0x100U, /**< XBARA1_OUT110 output assigned to DEC1_INDEX */
kXBARA1_OutputDec1Home = 111|0x100U, /**< XBARA1_OUT111 output assigned to DEC1_HOME */
kXBARA1_OutputDec1Trigger = 112|0x100U, /**< XBARA1_OUT112 output assigned to DEC1_TRIGGER */
kXBARA1_OutputDec2Phasea = 113|0x100U, /**< XBARA1_OUT113 output assigned to DEC2_PHASEA */
kXBARA1_OutputDec2Phaseb = 114|0x100U, /**< XBARA1_OUT114 output assigned to DEC2_PHASEB */
kXBARA1_OutputDec2Index = 115|0x100U, /**< XBARA1_OUT115 output assigned to DEC2_INDEX */
kXBARA1_OutputDec2Home = 116|0x100U, /**< XBARA1_OUT116 output assigned to DEC2_HOME */
kXBARA1_OutputDec2Trigger = 117|0x100U, /**< XBARA1_OUT117 output assigned to DEC2_TRIGGER */
kXBARA1_OutputDec3Phasea = 118|0x100U, /**< XBARA1_OUT118 output assigned to DEC3_PHASEA */
kXBARA1_OutputDec3Phaseb = 119|0x100U, /**< XBARA1_OUT119 output assigned to DEC3_PHASEB */
kXBARA1_OutputDec3Index = 120|0x100U, /**< XBARA1_OUT120 output assigned to DEC3_INDEX */
kXBARA1_OutputDec3Home = 121|0x100U, /**< XBARA1_OUT121 output assigned to DEC3_HOME */
kXBARA1_OutputDec3Trigger = 122|0x100U, /**< XBARA1_OUT122 output assigned to DEC3_TRIGGER */
kXBARA1_OutputDec4Phasea = 123|0x100U, /**< XBARA1_OUT123 output assigned to DEC4_PHASEA */
kXBARA1_OutputDec4Phaseb = 124|0x100U, /**< XBARA1_OUT124 output assigned to DEC4_PHASEB */
kXBARA1_OutputDec4Index = 125|0x100U, /**< XBARA1_OUT125 output assigned to DEC4_INDEX */
kXBARA1_OutputDec4Home = 126|0x100U, /**< XBARA1_OUT126 output assigned to DEC4_HOME */
kXBARA1_OutputDec4Trigger = 127|0x100U, /**< XBARA1_OUT127 output assigned to DEC4_TRIGGER */
kXBARA1_OutputRESERVED128 = 128|0x100U, /**< XBARA1_OUT128 output is reserved. */
kXBARA1_OutputRESERVED129 = 129|0x100U, /**< XBARA1_OUT129 output is reserved. */
kXBARA1_OutputRESERVED130 = 130|0x100U, /**< XBARA1_OUT130 output is reserved. */
kXBARA1_OutputRESERVED131 = 131|0x100U, /**< XBARA1_OUT131 output is reserved. */
kXBARA1_OutputCan1 = 132|0x100U, /**< XBARA1_OUT132 output assigned to CAN1 */
kXBARA1_OutputCan2 = 133|0x100U, /**< XBARA1_OUT133 output assigned to CAN2 */
kXBARA1_OutputRESERVED134 = 134|0x100U, /**< XBARA1_OUT134 output is reserved. */
kXBARA1_OutputRESERVED135 = 135|0x100U, /**< XBARA1_OUT135 output is reserved. */
kXBARA1_OutputRESERVED136 = 136|0x100U, /**< XBARA1_OUT136 output is reserved. */
kXBARA1_OutputRESERVED137 = 137|0x100U, /**< XBARA1_OUT137 output is reserved. */
kXBARA1_OutputQtimer1Timer0 = 138|0x100U, /**< XBARA1_OUT138 output assigned to QTIMER1_TIMER0 */
kXBARA1_OutputQtimer1Timer1 = 139|0x100U, /**< XBARA1_OUT139 output assigned to QTIMER1_TIMER1 */
kXBARA1_OutputQtimer1Timer2 = 140|0x100U, /**< XBARA1_OUT140 output assigned to QTIMER1_TIMER2 */
kXBARA1_OutputQtimer1Timer3 = 141|0x100U, /**< XBARA1_OUT141 output assigned to QTIMER1_TIMER3 */
kXBARA1_OutputQtimer2Timer0 = 142|0x100U, /**< XBARA1_OUT142 output assigned to QTIMER2_TIMER0 */
kXBARA1_OutputQtimer2Timer1 = 143|0x100U, /**< XBARA1_OUT143 output assigned to QTIMER2_TIMER1 */
kXBARA1_OutputQtimer2Timer2 = 144|0x100U, /**< XBARA1_OUT144 output assigned to QTIMER2_TIMER2 */
kXBARA1_OutputQtimer2Timer3 = 145|0x100U, /**< XBARA1_OUT145 output assigned to QTIMER2_TIMER3 */
kXBARA1_OutputQtimer3Timer0 = 146|0x100U, /**< XBARA1_OUT146 output assigned to QTIMER3_TIMER0 */
kXBARA1_OutputQtimer3Timer1 = 147|0x100U, /**< XBARA1_OUT147 output assigned to QTIMER3_TIMER1 */
kXBARA1_OutputQtimer3Timer2 = 148|0x100U, /**< XBARA1_OUT148 output assigned to QTIMER3_TIMER2 */
kXBARA1_OutputQtimer3Timer3 = 149|0x100U, /**< XBARA1_OUT149 output assigned to QTIMER3_TIMER3 */
kXBARA1_OutputQtimer4Timer0 = 150|0x100U, /**< XBARA1_OUT150 output assigned to QTIMER4_TIMER0 */
kXBARA1_OutputQtimer4Timer1 = 151|0x100U, /**< XBARA1_OUT151 output assigned to QTIMER4_TIMER1 */
kXBARA1_OutputQtimer4Timer2 = 152|0x100U, /**< XBARA1_OUT152 output assigned to QTIMER4_TIMER2 */
kXBARA1_OutputQtimer4Timer3 = 153|0x100U, /**< XBARA1_OUT153 output assigned to QTIMER4_TIMER3 */
kXBARA1_OutputEwmEwmIn = 154|0x100U, /**< XBARA1_OUT154 output assigned to EWM_EWM_IN */
kXBARA1_OutputAdcEtc0Coco0 = 155|0x100U, /**< XBARA1_OUT155 output assigned to ADC_ETC0_COCO0 */
kXBARA1_OutputAdcEtc0Coco1 = 156|0x100U, /**< XBARA1_OUT156 output assigned to ADC_ETC0_COCO1 */
kXBARA1_OutputAdcEtc0Coco2 = 157|0x100U, /**< XBARA1_OUT157 output assigned to ADC_ETC0_COCO2 */
kXBARA1_OutputAdcEtc0Coco3 = 158|0x100U, /**< XBARA1_OUT158 output assigned to ADC_ETC0_COCO3 */
kXBARA1_OutputAdcEtc1Coco0 = 159|0x100U, /**< XBARA1_OUT159 output assigned to ADC_ETC1_COCO0 */
kXBARA1_OutputAdcEtc1Coco1 = 160|0x100U, /**< XBARA1_OUT160 output assigned to ADC_ETC1_COCO1 */
kXBARA1_OutputAdcEtc1Coco2 = 161|0x100U, /**< XBARA1_OUT161 output assigned to ADC_ETC1_COCO2 */
kXBARA1_OutputAdcEtc1Coco3 = 162|0x100U, /**< XBARA1_OUT162 output assigned to ADC_ETC1_COCO3 */
kXBARA1_OutputRESERVED163 = 163|0x100U, /**< XBARA1_OUT163 output is reserved. */
kXBARA1_OutputRESERVED164 = 164|0x100U, /**< XBARA1_OUT164 output is reserved. */
kXBARA1_OutputRESERVED165 = 165|0x100U, /**< XBARA1_OUT165 output is reserved. */
kXBARA1_OutputRESERVED166 = 166|0x100U, /**< XBARA1_OUT166 output is reserved. */
kXBARA1_OutputRESERVED167 = 167|0x100U, /**< XBARA1_OUT167 output is reserved. */
kXBARA1_OutputRESERVED168 = 168|0x100U, /**< XBARA1_OUT168 output is reserved. */
kXBARA1_OutputRESERVED169 = 169|0x100U, /**< XBARA1_OUT169 output is reserved. */
kXBARA1_OutputRESERVED170 = 170|0x100U, /**< XBARA1_OUT170 output is reserved. */
kXBARA1_OutputFlexio1TrigIn0 = 171|0x100U, /**< XBARA1_OUT171 output assigned to FLEXIO1_TRIG_IN0 */
kXBARA1_OutputFlexio1TrigIn1 = 172|0x100U, /**< XBARA1_OUT172 output assigned to FLEXIO1_TRIG_IN1 */
kXBARA1_OutputFlexio2TrigIn0 = 173|0x100U, /**< XBARA1_OUT173 output assigned to FLEXIO2_TRIG_IN0 */
kXBARA1_OutputFlexio2TrigIn1 = 174|0x100U, /**< XBARA1_OUT174 output assigned to FLEXIO2_TRIG_IN1 */
kXBARB2_OutputAoi1In00 = 0|0x200U, /**< XBARB2_OUT0 output assigned to AOI1_IN00 */
kXBARB2_OutputAoi1In01 = 1|0x200U, /**< XBARB2_OUT1 output assigned to AOI1_IN01 */
kXBARB2_OutputAoi1In02 = 2|0x200U, /**< XBARB2_OUT2 output assigned to AOI1_IN02 */
kXBARB2_OutputAoi1In03 = 3|0x200U, /**< XBARB2_OUT3 output assigned to AOI1_IN03 */
kXBARB2_OutputAoi1In04 = 4|0x200U, /**< XBARB2_OUT4 output assigned to AOI1_IN04 */
kXBARB2_OutputAoi1In05 = 5|0x200U, /**< XBARB2_OUT5 output assigned to AOI1_IN05 */
kXBARB2_OutputAoi1In06 = 6|0x200U, /**< XBARB2_OUT6 output assigned to AOI1_IN06 */
kXBARB2_OutputAoi1In07 = 7|0x200U, /**< XBARB2_OUT7 output assigned to AOI1_IN07 */
kXBARB2_OutputAoi1In08 = 8|0x200U, /**< XBARB2_OUT8 output assigned to AOI1_IN08 */
kXBARB2_OutputAoi1In09 = 9|0x200U, /**< XBARB2_OUT9 output assigned to AOI1_IN09 */
kXBARB2_OutputAoi1In10 = 10|0x200U, /**< XBARB2_OUT10 output assigned to AOI1_IN10 */
kXBARB2_OutputAoi1In11 = 11|0x200U, /**< XBARB2_OUT11 output assigned to AOI1_IN11 */
kXBARB2_OutputAoi1In12 = 12|0x200U, /**< XBARB2_OUT12 output assigned to AOI1_IN12 */
kXBARB2_OutputAoi1In13 = 13|0x200U, /**< XBARB2_OUT13 output assigned to AOI1_IN13 */
kXBARB2_OutputAoi1In14 = 14|0x200U, /**< XBARB2_OUT14 output assigned to AOI1_IN14 */
kXBARB2_OutputAoi1In15 = 15|0x200U, /**< XBARB2_OUT15 output assigned to AOI1_IN15 */
kXBARB3_OutputAoi2In00 = 0|0x300U, /**< XBARB3_OUT0 output assigned to AOI2_IN00 */
kXBARB3_OutputAoi2In01 = 1|0x300U, /**< XBARB3_OUT1 output assigned to AOI2_IN01 */
kXBARB3_OutputAoi2In02 = 2|0x300U, /**< XBARB3_OUT2 output assigned to AOI2_IN02 */
kXBARB3_OutputAoi2In03 = 3|0x300U, /**< XBARB3_OUT3 output assigned to AOI2_IN03 */
kXBARB3_OutputAoi2In04 = 4|0x300U, /**< XBARB3_OUT4 output assigned to AOI2_IN04 */
kXBARB3_OutputAoi2In05 = 5|0x300U, /**< XBARB3_OUT5 output assigned to AOI2_IN05 */
kXBARB3_OutputAoi2In06 = 6|0x300U, /**< XBARB3_OUT6 output assigned to AOI2_IN06 */
kXBARB3_OutputAoi2In07 = 7|0x300U, /**< XBARB3_OUT7 output assigned to AOI2_IN07 */
kXBARB3_OutputAoi2In08 = 8|0x300U, /**< XBARB3_OUT8 output assigned to AOI2_IN08 */
kXBARB3_OutputAoi2In09 = 9|0x300U, /**< XBARB3_OUT9 output assigned to AOI2_IN09 */
kXBARB3_OutputAoi2In10 = 10|0x300U, /**< XBARB3_OUT10 output assigned to AOI2_IN10 */
kXBARB3_OutputAoi2In11 = 11|0x300U, /**< XBARB3_OUT11 output assigned to AOI2_IN11 */
kXBARB3_OutputAoi2In12 = 12|0x300U, /**< XBARB3_OUT12 output assigned to AOI2_IN12 */
kXBARB3_OutputAoi2In13 = 13|0x300U, /**< XBARB3_OUT13 output assigned to AOI2_IN13 */
kXBARB3_OutputAoi2In14 = 14|0x300U, /**< XBARB3_OUT14 output assigned to AOI2_IN14 */
kXBARB3_OutputAoi2In15 = 15|0x300U, /**< XBARB3_OUT15 output assigned to AOI2_IN15 */
} xbar_output_signal_t;
/*!
* @addtogroup iomuxc_lpsr_pads
* @{ */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @brief Enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD
*
* Defines the enumeration for the IOMUXC_LPSR SW_MUX_CTL_PAD collections.
*/
typedef enum _iomuxc_lpsr_sw_mux_ctl_pad
{
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_LPSR_SW_MUX_CTL_PAD_GPIO_LPSR_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
} iomuxc_lpsr_sw_mux_ctl_pad_t;
/* @} */
/*!
* @addtogroup iomuxc_lpsr_pads
* @{ */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @brief Enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD
*
* Defines the enumeration for the IOMUXC_LPSR SW_PAD_CTL_PAD collections.
*/
typedef enum _iomuxc_lpsr_sw_pad_ctl_pad
{
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_LPSR_SW_PAD_CTL_PAD_GPIO_LPSR_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
} iomuxc_lpsr_sw_pad_ctl_pad_t;
/* @} */
/*!
* @brief Enumeration for the IOMUXC_LPSR select input
*
* Defines the enumeration for the IOMUXC_LPSR select input collections.
*/
typedef enum _iomuxc_lpsr_select_input
{
kIOMUXC_LPSR_CAN3_IPP_IND_CANRX_SELECT_INPUT = 0U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SCL_SELECT_INPUT = 1U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPI2C5_IPP_IND_LPI2C_SDA_SELECT_INPUT = 2U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SCL_SELECT_INPUT = 3U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPI2C6_IPP_IND_LPI2C_SDA_SELECT_INPUT = 4U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_PCS_SELECT_INPUT_0 = 5U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SCK_SELECT_INPUT = 6U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDI_SELECT_INPUT = 7U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPSPI5_IPP_IND_LPSPI_SDO_SELECT_INPUT = 8U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_RXD_SELECT_INPUT = 9U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPUART11_IPP_IND_LPUART_TXD_SELECT_INPUT = 10U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_RXD_SELECT_INPUT = 11U, /**< IOMUXC select input index */
kIOMUXC_LPSR_LPUART12_IPP_IND_LPUART_TXD_SELECT_INPUT = 12U, /**< IOMUXC select input index */
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_0 = 13U, /**< IOMUXC select input index */
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_1 = 14U, /**< IOMUXC select input index */
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_2 = 15U, /**< IOMUXC select input index */
kIOMUXC_LPSR_MIC_IPP_IND_MIC_PDM_BITSTREAM_SELECT_INPUT_3 = 16U, /**< IOMUXC select input index */
kIOMUXC_LPSR_NMI_GLUE_IPP_IND_NMI_SELECT_INPUT = 17U, /**< IOMUXC select input index */
kIOMUXC_LPSR_SAI4_IPG_CLK_SAI_MCLK_SELECT_INPUT = 18U, /**< IOMUXC select input index */
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXBCLK_SELECT_INPUT = 19U, /**< IOMUXC select input index */
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXDATA_SELECT_INPUT_0 = 20U, /**< IOMUXC select input index */
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_RXSYNC_SELECT_INPUT = 21U, /**< IOMUXC select input index */
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXBCLK_SELECT_INPUT = 22U, /**< IOMUXC select input index */
kIOMUXC_LPSR_SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT = 23U, /**< IOMUXC select input index */
} iomuxc_lpsr_select_input_t;
/*!
* @addtogroup ssarc_mapping
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @brief Structure for the SSARC mapping
*
* The name of power domain.
*/
typedef enum _ssarc_power_domain_name
{
kSSARC_MEGAMIXPowerDomain = 0U, /**< MEGAMIX Power Domain, request from BPC0. */
kSSARC_DISPLAYMIXPowerDomain = 1U, /**< DISPLAYMIX Power Domain, request from BPC1. */
kSSARC_WAKEUPMIXPowerDomain = 2U, /**< WAKEUPMIX Power Domain, request from BPC2. */
kSSARC_LPSRMIXPowerDomain = 3U, /**< LPSRMIX Power Domain, request from BPC3. */
kSSARC_PowerDomain4 = 4U, /**< MIPI PHY Power Domain, request from BPC4. */
kSSARC_PowerDomain5 = 5U, /**< Virtual power domain, request from BPC5. */
kSSARC_PowerDomain6 = 6U, /**< Virtual power domain, request from BPC6. */
kSSARC_PowerDomain7 = 7U, /**< Virtual power domain, request from BPC7. */
} ssarc_power_domain_name_t;
/*
* @brief The name of cpu domain.
*/
typedef enum _ssarc_cpu_domain_name
{
kSSARC_CM7Core = 0U, /**< CM7 Core domain. */
kSSARC_CM4Core = 1U, /**< CM4 Core domain. */
} ssarc_cpu_domain_name_t;
/* @} */
/*!
* @addtogroup xrdc2_mapping
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @brief Structure for the XRDC2 mapping
*
* Defines the structure for the XRDC2 resource collections.
*/
typedef enum _xrdc2_master
{
kXRDC2_Master_M7_AHB = 0U, /**< M7 AHB */
kXRDC2_Master_M4_AHBC = 0U, /**< M4 AHBC */
kXRDC2_Master_M7_AXI = 1U, /**< M7 AXI */
kXRDC2_Master_M4_AHBS = 1U, /**< M4 AHBS */
kXRDC2_Master_CAAM = 2U, /**< CAAM */
kXRDC2_Master_CSI = 3U, /**< CSI */
kXRDC2_Master_M7_EDMA = 4U, /**< M7 EDMA */
kXRDC2_Master_M4_EDMA = 4U, /**< M4 EDMA */
kXRDC2_Master_ENET = 5U, /**< ENET */
kXRDC2_Master_ENET_1G_RX = 6U, /**< ENET_1G_RX */
kXRDC2_Master_ENET_1G_TX = 7U, /**< ENET_1G_TX */
kXRDC2_Master_ENET_QOS = 8U, /**< ENET_QOS */
kXRDC2_Master_GPU = 9U, /**< GPU */
kXRDC2_Master_LCDIF = 10U, /**< LCDIF */
kXRDC2_Master_LCDIFV2 = 11U, /**< LCDIFV2 */
kXRDC2_Master_PXP = 12U, /**< PXP */
kXRDC2_Master_SSARC = 14U, /**< SSARC */
kXRDC2_Master_USB = 15U, /**< USB */
kXRDC2_Master_USDHC1 = 16U, /**< USDHC1 */
kXRDC2_Master_USDHC2 = 17U, /**< USDHC2 */
} xrdc2_master_t;
typedef enum _xrdc2_mem
{
kXRDC2_Mem_CAAM_Region0 = XRDC2_MAKE_MEM(0, 0), /**< MRC0 Memory 0 */
kXRDC2_Mem_CAAM_Region1 = XRDC2_MAKE_MEM(0, 1), /**< MRC0 Memory 1 */
kXRDC2_Mem_CAAM_Region2 = XRDC2_MAKE_MEM(0, 2), /**< MRC0 Memory 2 */
kXRDC2_Mem_CAAM_Region3 = XRDC2_MAKE_MEM(0, 3), /**< MRC0 Memory 3 */
kXRDC2_Mem_CAAM_Region4 = XRDC2_MAKE_MEM(0, 4), /**< MRC0 Memory 4 */
kXRDC2_Mem_CAAM_Region5 = XRDC2_MAKE_MEM(0, 5), /**< MRC0 Memory 5 */
kXRDC2_Mem_CAAM_Region6 = XRDC2_MAKE_MEM(0, 6), /**< MRC0 Memory 6 */
kXRDC2_Mem_CAAM_Region7 = XRDC2_MAKE_MEM(0, 7), /**< MRC0 Memory 7 */
kXRDC2_Mem_CAAM_Region8 = XRDC2_MAKE_MEM(0, 8), /**< MRC0 Memory 8 */
kXRDC2_Mem_CAAM_Region9 = XRDC2_MAKE_MEM(0, 9), /**< MRC0 Memory 9 */
kXRDC2_Mem_CAAM_Region10 = XRDC2_MAKE_MEM(0, 10), /**< MRC0 Memory 10 */
kXRDC2_Mem_CAAM_Region11 = XRDC2_MAKE_MEM(0, 11), /**< MRC0 Memory 11 */
kXRDC2_Mem_CAAM_Region12 = XRDC2_MAKE_MEM(0, 12), /**< MRC0 Memory 12 */
kXRDC2_Mem_CAAM_Region13 = XRDC2_MAKE_MEM(0, 13), /**< MRC0 Memory 13 */
kXRDC2_Mem_CAAM_Region14 = XRDC2_MAKE_MEM(0, 14), /**< MRC0 Memory 14 */
kXRDC2_Mem_CAAM_Region15 = XRDC2_MAKE_MEM(0, 15), /**< MRC0 Memory 15 */
kXRDC2_Mem_FLEXSPI1_Region0 = XRDC2_MAKE_MEM(1, 0), /**< MRC1 Memory 0 */
kXRDC2_Mem_FLEXSPI1_Region1 = XRDC2_MAKE_MEM(1, 1), /**< MRC1 Memory 1 */
kXRDC2_Mem_FLEXSPI1_Region2 = XRDC2_MAKE_MEM(1, 2), /**< MRC1 Memory 2 */
kXRDC2_Mem_FLEXSPI1_Region3 = XRDC2_MAKE_MEM(1, 3), /**< MRC1 Memory 3 */
kXRDC2_Mem_FLEXSPI1_Region4 = XRDC2_MAKE_MEM(1, 4), /**< MRC1 Memory 4 */
kXRDC2_Mem_FLEXSPI1_Region5 = XRDC2_MAKE_MEM(1, 5), /**< MRC1 Memory 5 */
kXRDC2_Mem_FLEXSPI1_Region6 = XRDC2_MAKE_MEM(1, 6), /**< MRC1 Memory 6 */
kXRDC2_Mem_FLEXSPI1_Region7 = XRDC2_MAKE_MEM(1, 7), /**< MRC1 Memory 7 */
kXRDC2_Mem_FLEXSPI1_Region8 = XRDC2_MAKE_MEM(1, 8), /**< MRC1 Memory 8 */
kXRDC2_Mem_FLEXSPI1_Region9 = XRDC2_MAKE_MEM(1, 9), /**< MRC1 Memory 9 */
kXRDC2_Mem_FLEXSPI1_Region10 = XRDC2_MAKE_MEM(1, 10), /**< MRC1 Memory 10 */
kXRDC2_Mem_FLEXSPI1_Region11 = XRDC2_MAKE_MEM(1, 11), /**< MRC1 Memory 11 */
kXRDC2_Mem_FLEXSPI1_Region12 = XRDC2_MAKE_MEM(1, 12), /**< MRC1 Memory 12 */
kXRDC2_Mem_FLEXSPI1_Region13 = XRDC2_MAKE_MEM(1, 13), /**< MRC1 Memory 13 */
kXRDC2_Mem_FLEXSPI1_Region14 = XRDC2_MAKE_MEM(1, 14), /**< MRC1 Memory 14 */
kXRDC2_Mem_FLEXSPI1_Region15 = XRDC2_MAKE_MEM(1, 15), /**< MRC1 Memory 15 */
kXRDC2_Mem_FLEXSPI2_Region0 = XRDC2_MAKE_MEM(2, 0), /**< MRC2 Memory 0 */
kXRDC2_Mem_FLEXSPI2_Region1 = XRDC2_MAKE_MEM(2, 1), /**< MRC2 Memory 1 */
kXRDC2_Mem_FLEXSPI2_Region2 = XRDC2_MAKE_MEM(2, 2), /**< MRC2 Memory 2 */
kXRDC2_Mem_FLEXSPI2_Region3 = XRDC2_MAKE_MEM(2, 3), /**< MRC2 Memory 3 */
kXRDC2_Mem_FLEXSPI2_Region4 = XRDC2_MAKE_MEM(2, 4), /**< MRC2 Memory 4 */
kXRDC2_Mem_FLEXSPI2_Region5 = XRDC2_MAKE_MEM(2, 5), /**< MRC2 Memory 5 */
kXRDC2_Mem_FLEXSPI2_Region6 = XRDC2_MAKE_MEM(2, 6), /**< MRC2 Memory 6 */
kXRDC2_Mem_FLEXSPI2_Region7 = XRDC2_MAKE_MEM(2, 7), /**< MRC2 Memory 7 */
kXRDC2_Mem_FLEXSPI2_Region8 = XRDC2_MAKE_MEM(2, 8), /**< MRC2 Memory 8 */
kXRDC2_Mem_FLEXSPI2_Region9 = XRDC2_MAKE_MEM(2, 9), /**< MRC2 Memory 9 */
kXRDC2_Mem_FLEXSPI2_Region10 = XRDC2_MAKE_MEM(2, 10), /**< MRC2 Memory 10 */
kXRDC2_Mem_FLEXSPI2_Region11 = XRDC2_MAKE_MEM(2, 11), /**< MRC2 Memory 11 */
kXRDC2_Mem_FLEXSPI2_Region12 = XRDC2_MAKE_MEM(2, 12), /**< MRC2 Memory 12 */
kXRDC2_Mem_FLEXSPI2_Region13 = XRDC2_MAKE_MEM(2, 13), /**< MRC2 Memory 13 */
kXRDC2_Mem_FLEXSPI2_Region14 = XRDC2_MAKE_MEM(2, 14), /**< MRC2 Memory 14 */
kXRDC2_Mem_FLEXSPI2_Region15 = XRDC2_MAKE_MEM(2, 15), /**< MRC2 Memory 15 */
kXRDC2_Mem_M4LMEM_Region0 = XRDC2_MAKE_MEM(3, 0), /**< MRC3 Memory 0 */
kXRDC2_Mem_M4LMEM_Region1 = XRDC2_MAKE_MEM(3, 1), /**< MRC3 Memory 1 */
kXRDC2_Mem_M4LMEM_Region2 = XRDC2_MAKE_MEM(3, 2), /**< MRC3 Memory 2 */
kXRDC2_Mem_M4LMEM_Region3 = XRDC2_MAKE_MEM(3, 3), /**< MRC3 Memory 3 */
kXRDC2_Mem_M4LMEM_Region4 = XRDC2_MAKE_MEM(3, 4), /**< MRC3 Memory 4 */
kXRDC2_Mem_M4LMEM_Region5 = XRDC2_MAKE_MEM(3, 5), /**< MRC3 Memory 5 */
kXRDC2_Mem_M4LMEM_Region6 = XRDC2_MAKE_MEM(3, 6), /**< MRC3 Memory 6 */
kXRDC2_Mem_M4LMEM_Region7 = XRDC2_MAKE_MEM(3, 7), /**< MRC3 Memory 7 */
kXRDC2_Mem_M4LMEM_Region8 = XRDC2_MAKE_MEM(3, 8), /**< MRC3 Memory 8 */
kXRDC2_Mem_M4LMEM_Region9 = XRDC2_MAKE_MEM(3, 9), /**< MRC3 Memory 9 */
kXRDC2_Mem_M4LMEM_Region10 = XRDC2_MAKE_MEM(3, 10), /**< MRC3 Memory 10 */
kXRDC2_Mem_M4LMEM_Region11 = XRDC2_MAKE_MEM(3, 11), /**< MRC3 Memory 11 */
kXRDC2_Mem_M4LMEM_Region12 = XRDC2_MAKE_MEM(3, 12), /**< MRC3 Memory 12 */
kXRDC2_Mem_M4LMEM_Region13 = XRDC2_MAKE_MEM(3, 13), /**< MRC3 Memory 13 */
kXRDC2_Mem_M4LMEM_Region14 = XRDC2_MAKE_MEM(3, 14), /**< MRC3 Memory 14 */
kXRDC2_Mem_M4LMEM_Region15 = XRDC2_MAKE_MEM(3, 15), /**< MRC3 Memory 15 */
kXRDC2_Mem_M7OC_Region0 = XRDC2_MAKE_MEM(4, 0), /**< MRC4 Memory 0 */
kXRDC2_Mem_M7OC_Region1 = XRDC2_MAKE_MEM(4, 1), /**< MRC4 Memory 1 */
kXRDC2_Mem_M7OC_Region2 = XRDC2_MAKE_MEM(4, 2), /**< MRC4 Memory 2 */
kXRDC2_Mem_M7OC_Region3 = XRDC2_MAKE_MEM(4, 3), /**< MRC4 Memory 3 */
kXRDC2_Mem_M7OC_Region4 = XRDC2_MAKE_MEM(4, 4), /**< MRC4 Memory 4 */
kXRDC2_Mem_M7OC_Region5 = XRDC2_MAKE_MEM(4, 5), /**< MRC4 Memory 5 */
kXRDC2_Mem_M7OC_Region6 = XRDC2_MAKE_MEM(4, 6), /**< MRC4 Memory 6 */
kXRDC2_Mem_M7OC_Region7 = XRDC2_MAKE_MEM(4, 7), /**< MRC4 Memory 7 */
kXRDC2_Mem_M7OC_Region8 = XRDC2_MAKE_MEM(4, 8), /**< MRC4 Memory 8 */
kXRDC2_Mem_M7OC_Region9 = XRDC2_MAKE_MEM(4, 9), /**< MRC4 Memory 9 */
kXRDC2_Mem_M7OC_Region10 = XRDC2_MAKE_MEM(4, 10), /**< MRC4 Memory 10 */
kXRDC2_Mem_M7OC_Region11 = XRDC2_MAKE_MEM(4, 11), /**< MRC4 Memory 11 */
kXRDC2_Mem_M7OC_Region12 = XRDC2_MAKE_MEM(4, 12), /**< MRC4 Memory 12 */
kXRDC2_Mem_M7OC_Region13 = XRDC2_MAKE_MEM(4, 13), /**< MRC4 Memory 13 */
kXRDC2_Mem_M7OC_Region14 = XRDC2_MAKE_MEM(4, 14), /**< MRC4 Memory 14 */
kXRDC2_Mem_M7OC_Region15 = XRDC2_MAKE_MEM(4, 15), /**< MRC4 Memory 15 */
kXRDC2_Mem_MECC1_Region0 = XRDC2_MAKE_MEM(5, 0), /**< MRC5 Memory 0 */
kXRDC2_Mem_MECC1_Region1 = XRDC2_MAKE_MEM(5, 1), /**< MRC5 Memory 1 */
kXRDC2_Mem_MECC1_Region2 = XRDC2_MAKE_MEM(5, 2), /**< MRC5 Memory 2 */
kXRDC2_Mem_MECC1_Region3 = XRDC2_MAKE_MEM(5, 3), /**< MRC5 Memory 3 */
kXRDC2_Mem_MECC1_Region4 = XRDC2_MAKE_MEM(5, 4), /**< MRC5 Memory 4 */
kXRDC2_Mem_MECC1_Region5 = XRDC2_MAKE_MEM(5, 5), /**< MRC5 Memory 5 */
kXRDC2_Mem_MECC1_Region6 = XRDC2_MAKE_MEM(5, 6), /**< MRC5 Memory 6 */
kXRDC2_Mem_MECC1_Region7 = XRDC2_MAKE_MEM(5, 7), /**< MRC5 Memory 7 */
kXRDC2_Mem_MECC1_Region8 = XRDC2_MAKE_MEM(5, 8), /**< MRC5 Memory 8 */
kXRDC2_Mem_MECC1_Region9 = XRDC2_MAKE_MEM(5, 9), /**< MRC5 Memory 9 */
kXRDC2_Mem_MECC1_Region10 = XRDC2_MAKE_MEM(5, 10), /**< MRC5 Memory 10 */
kXRDC2_Mem_MECC1_Region11 = XRDC2_MAKE_MEM(5, 11), /**< MRC5 Memory 11 */
kXRDC2_Mem_MECC1_Region12 = XRDC2_MAKE_MEM(5, 12), /**< MRC5 Memory 12 */
kXRDC2_Mem_MECC1_Region13 = XRDC2_MAKE_MEM(5, 13), /**< MRC5 Memory 13 */
kXRDC2_Mem_MECC1_Region14 = XRDC2_MAKE_MEM(5, 14), /**< MRC5 Memory 14 */
kXRDC2_Mem_MECC1_Region15 = XRDC2_MAKE_MEM(5, 15), /**< MRC5 Memory 15 */
kXRDC2_Mem_MECC2_Region0 = XRDC2_MAKE_MEM(6, 0), /**< MRC6 Memory 0 */
kXRDC2_Mem_MECC2_Region1 = XRDC2_MAKE_MEM(6, 1), /**< MRC6 Memory 1 */
kXRDC2_Mem_MECC2_Region2 = XRDC2_MAKE_MEM(6, 2), /**< MRC6 Memory 2 */
kXRDC2_Mem_MECC2_Region3 = XRDC2_MAKE_MEM(6, 3), /**< MRC6 Memory 3 */
kXRDC2_Mem_MECC2_Region4 = XRDC2_MAKE_MEM(6, 4), /**< MRC6 Memory 4 */
kXRDC2_Mem_MECC2_Region5 = XRDC2_MAKE_MEM(6, 5), /**< MRC6 Memory 5 */
kXRDC2_Mem_MECC2_Region6 = XRDC2_MAKE_MEM(6, 6), /**< MRC6 Memory 6 */
kXRDC2_Mem_MECC2_Region7 = XRDC2_MAKE_MEM(6, 7), /**< MRC6 Memory 7 */
kXRDC2_Mem_MECC2_Region8 = XRDC2_MAKE_MEM(6, 8), /**< MRC6 Memory 8 */
kXRDC2_Mem_MECC2_Region9 = XRDC2_MAKE_MEM(6, 9), /**< MRC6 Memory 9 */
kXRDC2_Mem_MECC2_Region10 = XRDC2_MAKE_MEM(6, 10), /**< MRC6 Memory 10 */
kXRDC2_Mem_MECC2_Region11 = XRDC2_MAKE_MEM(6, 11), /**< MRC6 Memory 11 */
kXRDC2_Mem_MECC2_Region12 = XRDC2_MAKE_MEM(6, 12), /**< MRC6 Memory 12 */
kXRDC2_Mem_MECC2_Region13 = XRDC2_MAKE_MEM(6, 13), /**< MRC6 Memory 13 */
kXRDC2_Mem_MECC2_Region14 = XRDC2_MAKE_MEM(6, 14), /**< MRC6 Memory 14 */
kXRDC2_Mem_MECC2_Region15 = XRDC2_MAKE_MEM(6, 15), /**< MRC6 Memory 15 */
kXRDC2_Mem_SEMC_Region0 = XRDC2_MAKE_MEM(7, 0), /**< MRC7 Memory 0 */
kXRDC2_Mem_SEMC_Region1 = XRDC2_MAKE_MEM(7, 1), /**< MRC7 Memory 1 */
kXRDC2_Mem_SEMC_Region2 = XRDC2_MAKE_MEM(7, 2), /**< MRC7 Memory 2 */
kXRDC2_Mem_SEMC_Region3 = XRDC2_MAKE_MEM(7, 3), /**< MRC7 Memory 3 */
kXRDC2_Mem_SEMC_Region4 = XRDC2_MAKE_MEM(7, 4), /**< MRC7 Memory 4 */
kXRDC2_Mem_SEMC_Region5 = XRDC2_MAKE_MEM(7, 5), /**< MRC7 Memory 5 */
kXRDC2_Mem_SEMC_Region6 = XRDC2_MAKE_MEM(7, 6), /**< MRC7 Memory 6 */
kXRDC2_Mem_SEMC_Region7 = XRDC2_MAKE_MEM(7, 7), /**< MRC7 Memory 7 */
kXRDC2_Mem_SEMC_Region8 = XRDC2_MAKE_MEM(7, 8), /**< MRC7 Memory 8 */
kXRDC2_Mem_SEMC_Region9 = XRDC2_MAKE_MEM(7, 9), /**< MRC7 Memory 9 */
kXRDC2_Mem_SEMC_Region10 = XRDC2_MAKE_MEM(7, 10), /**< MRC7 Memory 10 */
kXRDC2_Mem_SEMC_Region11 = XRDC2_MAKE_MEM(7, 11), /**< MRC7 Memory 11 */
kXRDC2_Mem_SEMC_Region12 = XRDC2_MAKE_MEM(7, 12), /**< MRC7 Memory 12 */
kXRDC2_Mem_SEMC_Region13 = XRDC2_MAKE_MEM(7, 13), /**< MRC7 Memory 13 */
kXRDC2_Mem_SEMC_Region14 = XRDC2_MAKE_MEM(7, 14), /**< MRC7 Memory 14 */
kXRDC2_Mem_SEMC_Region15 = XRDC2_MAKE_MEM(7, 15), /**< MRC7 Memory 15 */
} xrdc2_mem_t;
typedef enum _xrdc2_mem_slot
{
kXRDC2_MemSlot_GPV0 = 0U, /**< GPV0 */
kXRDC2_MemSlot_GPV1 = 1U, /**< GPV1 */
kXRDC2_MemSlot_GPV2 = 2U, /**< GPV2 */
kXRDC2_MemSlot_ROMCP = 3U, /**< ROMCP */
} xrdc2_mem_slot_t;
typedef enum _xrdc2_periph
{
kXRDC2_Periph_ACMP4 = XRDC2_MAKE_PERIPH(0, 108), /**< ACMP4 */
kXRDC2_Periph_ACMP3 = XRDC2_MAKE_PERIPH(0, 107), /**< ACMP3 */
kXRDC2_Periph_ACMP2 = XRDC2_MAKE_PERIPH(0, 106), /**< ACMP2 */
kXRDC2_Periph_ACMP1 = XRDC2_MAKE_PERIPH(0, 105), /**< ACMP1 */
kXRDC2_Periph_FLEXPWM4 = XRDC2_MAKE_PERIPH(0, 102), /**< FLEXPWM4 */
kXRDC2_Periph_FLEXPWM3 = XRDC2_MAKE_PERIPH(0, 101), /**< FLEXPWM3 */
kXRDC2_Periph_FLEXPWM2 = XRDC2_MAKE_PERIPH(0, 100), /**< FLEXPWM2 */
kXRDC2_Periph_FLEXPWM1 = XRDC2_MAKE_PERIPH(0, 99 ), /**< FLEXPWM1 */
kXRDC2_Periph_ENC4 = XRDC2_MAKE_PERIPH(0, 96 ), /**< ENC4 */
kXRDC2_Periph_ENC3 = XRDC2_MAKE_PERIPH(0, 95 ), /**< ENC3 */
kXRDC2_Periph_ENC2 = XRDC2_MAKE_PERIPH(0, 94 ), /**< ENC2 */
kXRDC2_Periph_ENC1 = XRDC2_MAKE_PERIPH(0, 93 ), /**< ENC1 */
kXRDC2_Periph_QTIMER4 = XRDC2_MAKE_PERIPH(0, 90 ), /**< QTIMER4 */
kXRDC2_Periph_QTIMER3 = XRDC2_MAKE_PERIPH(0, 89 ), /**< QTIMER3 */
kXRDC2_Periph_QTIMER2 = XRDC2_MAKE_PERIPH(0, 88 ), /**< QTIMER2 */
kXRDC2_Periph_QTIMER1 = XRDC2_MAKE_PERIPH(0, 87 ), /**< QTIMER1 */
kXRDC2_Periph_SIM2 = XRDC2_MAKE_PERIPH(0, 86 ), /**< SIM2 */
kXRDC2_Periph_SIM1 = XRDC2_MAKE_PERIPH(0, 85 ), /**< SIM1 */
kXRDC2_Periph_CCM_OBS = XRDC2_MAKE_PERIPH(0, 84 ), /**< CCM_OBS */
kXRDC2_Periph_GPIO6 = XRDC2_MAKE_PERIPH(0, 80 ), /**< GPIO6 */
kXRDC2_Periph_GPIO5 = XRDC2_MAKE_PERIPH(0, 79 ), /**< GPIO5 */
kXRDC2_Periph_GPIO4 = XRDC2_MAKE_PERIPH(0, 78 ), /**< GPIO4 */
kXRDC2_Periph_GPIO3 = XRDC2_MAKE_PERIPH(0, 77 ), /**< GPIO3 */
kXRDC2_Periph_GPIO2 = XRDC2_MAKE_PERIPH(0, 76 ), /**< GPIO2 */
kXRDC2_Periph_GPIO1 = XRDC2_MAKE_PERIPH(0, 75 ), /**< GPIO1 */
kXRDC2_Periph_LPSPI4 = XRDC2_MAKE_PERIPH(0, 72 ), /**< LPSPI4 */
kXRDC2_Periph_LPSPI3 = XRDC2_MAKE_PERIPH(0, 71 ), /**< LPSPI3 */
kXRDC2_Periph_LPSPI2 = XRDC2_MAKE_PERIPH(0, 70 ), /**< LPSPI2 */
kXRDC2_Periph_LPSPI1 = XRDC2_MAKE_PERIPH(0, 69 ), /**< LPSPI1 */
kXRDC2_Periph_LPI2C4 = XRDC2_MAKE_PERIPH(0, 68 ), /**< LPI2C4 */
kXRDC2_Periph_LPI2C3 = XRDC2_MAKE_PERIPH(0, 67 ), /**< LPI2C3 */
kXRDC2_Periph_LPI2C2 = XRDC2_MAKE_PERIPH(0, 66 ), /**< LPI2C2 */
kXRDC2_Periph_LPI2C1 = XRDC2_MAKE_PERIPH(0, 65 ), /**< LPI2C1 */
kXRDC2_Periph_GPT6 = XRDC2_MAKE_PERIPH(0, 64 ), /**< GPT6 */
kXRDC2_Periph_GPT5 = XRDC2_MAKE_PERIPH(0, 63 ), /**< GPT5 */
kXRDC2_Periph_GPT4 = XRDC2_MAKE_PERIPH(0, 62 ), /**< GPT4 */
kXRDC2_Periph_GPT3 = XRDC2_MAKE_PERIPH(0, 61 ), /**< GPT3 */
kXRDC2_Periph_GPT2 = XRDC2_MAKE_PERIPH(0, 60 ), /**< GPT2 */
kXRDC2_Periph_GPT1 = XRDC2_MAKE_PERIPH(0, 59 ), /**< GPT1 */
kXRDC2_Periph_IOMUXC = XRDC2_MAKE_PERIPH(0, 58 ), /**< IOMUXC */
kXRDC2_Periph_IOMUXC_GPR = XRDC2_MAKE_PERIPH(0, 57 ), /**< IOMUXC_GPR */
kXRDC2_Periph_KPP = XRDC2_MAKE_PERIPH(0, 56 ), /**< KPP */
kXRDC2_Periph_PIT1 = XRDC2_MAKE_PERIPH(0, 54 ), /**< PIT1 */
kXRDC2_Periph_SEMC = XRDC2_MAKE_PERIPH(0, 53 ), /**< SEMC */
kXRDC2_Periph_FLEXSPI2 = XRDC2_MAKE_PERIPH(0, 52 ), /**< FLEXSPI2 */
kXRDC2_Periph_FLEXSPI1 = XRDC2_MAKE_PERIPH(0, 51 ), /**< FLEXSPI1 */
kXRDC2_Periph_CAN2 = XRDC2_MAKE_PERIPH(0, 50 ), /**< CAN2 */
kXRDC2_Periph_CAN1 = XRDC2_MAKE_PERIPH(0, 49 ), /**< CAN1 */
kXRDC2_Periph_AOI2 = XRDC2_MAKE_PERIPH(0, 47 ), /**< AOI2 */
kXRDC2_Periph_AOI1 = XRDC2_MAKE_PERIPH(0, 46 ), /**< AOI1 */
kXRDC2_Periph_FLEXIO2 = XRDC2_MAKE_PERIPH(0, 44 ), /**< FLEXIO2 */
kXRDC2_Periph_FLEXIO1 = XRDC2_MAKE_PERIPH(0, 43 ), /**< FLEXIO1 */
kXRDC2_Periph_LPUART10 = XRDC2_MAKE_PERIPH(0, 40 ), /**< LPUART10 */
kXRDC2_Periph_LPUART9 = XRDC2_MAKE_PERIPH(0, 39 ), /**< LPUART9 */
kXRDC2_Periph_LPUART8 = XRDC2_MAKE_PERIPH(0, 38 ), /**< LPUART8 */
kXRDC2_Periph_LPUART7 = XRDC2_MAKE_PERIPH(0, 37 ), /**< LPUART7 */
kXRDC2_Periph_LPUART6 = XRDC2_MAKE_PERIPH(0, 36 ), /**< LPUART6 */
kXRDC2_Periph_LPUART5 = XRDC2_MAKE_PERIPH(0, 35 ), /**< LPUART5 */
kXRDC2_Periph_LPUART4 = XRDC2_MAKE_PERIPH(0, 34 ), /**< LPUART4 */
kXRDC2_Periph_LPUART3 = XRDC2_MAKE_PERIPH(0, 33 ), /**< LPUART3 */
kXRDC2_Periph_LPUART2 = XRDC2_MAKE_PERIPH(0, 32 ), /**< LPUART2 */
kXRDC2_Periph_LPUART1 = XRDC2_MAKE_PERIPH(0, 31 ), /**< LPUART1 */
kXRDC2_Periph_DMA_CH_MUX = XRDC2_MAKE_PERIPH(0, 29 ), /**< DMA_CH_MUX */
kXRDC2_Periph_EDMA = XRDC2_MAKE_PERIPH(0, 28 ), /**< EDMA */
kXRDC2_Periph_IEE = XRDC2_MAKE_PERIPH(0, 27 ), /**< IEE */
kXRDC2_Periph_DAC = XRDC2_MAKE_PERIPH(0, 25 ), /**< DAC */
kXRDC2_Periph_TSC_DIG = XRDC2_MAKE_PERIPH(0, 23 ), /**< TSC_DIG */
kXRDC2_Periph_ADC2 = XRDC2_MAKE_PERIPH(0, 21 ), /**< ADC2 */
kXRDC2_Periph_ADC1 = XRDC2_MAKE_PERIPH(0, 20 ), /**< ADC1 */
kXRDC2_Periph_ADC_ETC = XRDC2_MAKE_PERIPH(0, 18 ), /**< ADC_ETC */
kXRDC2_Periph_XBAR3 = XRDC2_MAKE_PERIPH(0, 17 ), /**< XBAR3 */
kXRDC2_Periph_XBAR2 = XRDC2_MAKE_PERIPH(0, 16 ), /**< XBAR2 */
kXRDC2_Periph_XBAR1 = XRDC2_MAKE_PERIPH(0, 15 ), /**< XBAR1 */
kXRDC2_Periph_WDOG3 = XRDC2_MAKE_PERIPH(0, 14 ), /**< WDOG3 */
kXRDC2_Periph_WDOG2 = XRDC2_MAKE_PERIPH(0, 13 ), /**< WDOG2 */
kXRDC2_Periph_WDOG1 = XRDC2_MAKE_PERIPH(0, 12 ), /**< WDOG1 */
kXRDC2_Periph_EWM = XRDC2_MAKE_PERIPH(0, 11 ), /**< EWM */
kXRDC2_Periph_FLEXRAM = XRDC2_MAKE_PERIPH(0, 10 ), /**< FLEXRAM */
kXRDC2_Periph_XECC_SEMC = XRDC2_MAKE_PERIPH(0, 9 ), /**< XECC_SEMC */
kXRDC2_Periph_XECC_FLEXSPI2 = XRDC2_MAKE_PERIPH(0, 8 ), /**< XECC_FLEXSPI2 */
kXRDC2_Periph_XECC_FLEXSPI1 = XRDC2_MAKE_PERIPH(0, 7 ), /**< XECC_FLEXSPI1 */
kXRDC2_Periph_MECC2 = XRDC2_MAKE_PERIPH(0, 6 ), /**< MECC2 */
kXRDC2_Periph_MECC1 = XRDC2_MAKE_PERIPH(0, 5 ), /**< MECC1 */
kXRDC2_Periph_MTR = XRDC2_MAKE_PERIPH(0, 4 ), /**< MTR */
kXRDC2_Periph_SFA = XRDC2_MAKE_PERIPH(0, 3 ), /**< SFA */
kXRDC2_Periph_CAAM_DEBUG_3 = XRDC2_MAKE_PERIPH(1, 51 ), /**< CAAM_DEBUG_3 */
kXRDC2_Periph_CAAM_DEBUG_2 = XRDC2_MAKE_PERIPH(1, 50 ), /**< CAAM_DEBUG_2 */
kXRDC2_Periph_CAAM_DEBUG_1 = XRDC2_MAKE_PERIPH(1, 49 ), /**< CAAM_DEBUG_1 */
kXRDC2_Periph_CAAM_DEBUG_0 = XRDC2_MAKE_PERIPH(1, 48 ), /**< CAAM_DEBUG_0 */
kXRDC2_Periph_CAAM_RTIC_3 = XRDC2_MAKE_PERIPH(1, 43 ), /**< CAAM_RTIC_3 */
kXRDC2_Periph_CAAM_RTIC_2 = XRDC2_MAKE_PERIPH(1, 42 ), /**< CAAM_RTIC_2 */
kXRDC2_Periph_CAAM_RTIC_1 = XRDC2_MAKE_PERIPH(1, 41 ), /**< CAAM_RTIC_1 */
kXRDC2_Periph_CAAM_RTIC_0 = XRDC2_MAKE_PERIPH(1, 40 ), /**< CAAM_RTIC_0 */
kXRDC2_Periph_CAAM_JR3_3 = XRDC2_MAKE_PERIPH(1, 35 ), /**< CAAM_JR3_3 */
kXRDC2_Periph_CAAM_JR3_2 = XRDC2_MAKE_PERIPH(1, 34 ), /**< CAAM_JR3_2 */
kXRDC2_Periph_CAAM_JR3_1 = XRDC2_MAKE_PERIPH(1, 33 ), /**< CAAM_JR3_1 */
kXRDC2_Periph_CAAM_JR3_0 = XRDC2_MAKE_PERIPH(1, 32 ), /**< CAAM_JR3_0 */
kXRDC2_Periph_CAAM_JR2_3 = XRDC2_MAKE_PERIPH(1, 31 ), /**< CAAM_JR2_3 */
kXRDC2_Periph_CAAM_JR2_2 = XRDC2_MAKE_PERIPH(1, 30 ), /**< CAAM_JR2_2 */
kXRDC2_Periph_CAAM_JR2_1 = XRDC2_MAKE_PERIPH(1, 29 ), /**< CAAM_JR2_1 */
kXRDC2_Periph_CAAM_JR2_0 = XRDC2_MAKE_PERIPH(1, 28 ), /**< CAAM_JR2_0 */
kXRDC2_Periph_CAAM_JR1_3 = XRDC2_MAKE_PERIPH(1, 27 ), /**< CAAM_JR1_3 */
kXRDC2_Periph_CAAM_JR1_2 = XRDC2_MAKE_PERIPH(1, 26 ), /**< CAAM_JR1_2 */
kXRDC2_Periph_CAAM_JR1_1 = XRDC2_MAKE_PERIPH(1, 25 ), /**< CAAM_JR1_1 */
kXRDC2_Periph_CAAM_JR1_0 = XRDC2_MAKE_PERIPH(1, 24 ), /**< CAAM_JR1_0 */
kXRDC2_Periph_CAAM_JR0_3 = XRDC2_MAKE_PERIPH(1, 23 ), /**< CAAM_JR0_3 */
kXRDC2_Periph_CAAM_JR0_2 = XRDC2_MAKE_PERIPH(1, 22 ), /**< CAAM_JR0_2 */
kXRDC2_Periph_CAAM_JR0_1 = XRDC2_MAKE_PERIPH(1, 21 ), /**< CAAM_JR0_1 */
kXRDC2_Periph_CAAM_JR0_0 = XRDC2_MAKE_PERIPH(1, 20 ), /**< CAAM_JR0_0 */
kXRDC2_Periph_CAAM_GENERAL_3 = XRDC2_MAKE_PERIPH(1, 19 ), /**< CAAM_GENERAL_3 */
kXRDC2_Periph_CAAM_GENERAL_2 = XRDC2_MAKE_PERIPH(1, 18 ), /**< CAAM_GENERAL_2 */
kXRDC2_Periph_CAAM_GENERAL_1 = XRDC2_MAKE_PERIPH(1, 17 ), /**< CAAM_GENERAL_1 */
kXRDC2_Periph_CAAM_GENERAL_0 = XRDC2_MAKE_PERIPH(1, 16 ), /**< CAAM_GENERAL_0 */
kXRDC2_Periph_ENET_QOS = XRDC2_MAKE_PERIPH(1, 15 ), /**< ENET_QOS */
kXRDC2_Periph_USBPHY2 = XRDC2_MAKE_PERIPH(1, 14 ), /**< USBPHY2 */
kXRDC2_Periph_USBPHY1 = XRDC2_MAKE_PERIPH(1, 13 ), /**< USBPHY1 */
kXRDC2_Periph_USB_OTG = XRDC2_MAKE_PERIPH(1, 12 ), /**< USB_OTG */
kXRDC2_Periph_USB_OTG2 = XRDC2_MAKE_PERIPH(1, 11 ), /**< USB_OTG2 */
kXRDC2_Periph_USB_PL301 = XRDC2_MAKE_PERIPH(1, 10 ), /**< USB_PL301 */
kXRDC2_Periph_ENET = XRDC2_MAKE_PERIPH(1, 9 ), /**< ENET */
kXRDC2_Periph_ENET_1G = XRDC2_MAKE_PERIPH(1, 8 ), /**< ENET_1G */
kXRDC2_Periph_USDHC2 = XRDC2_MAKE_PERIPH(1, 7 ), /**< USDHC2 */
kXRDC2_Periph_USDHC1 = XRDC2_MAKE_PERIPH(1, 6 ), /**< USDHC1 */
kXRDC2_Periph_ASRC = XRDC2_MAKE_PERIPH(1, 5 ), /**< ASRC */
kXRDC2_Periph_SAI3 = XRDC2_MAKE_PERIPH(1, 3 ), /**< SAI3 */
kXRDC2_Periph_SAI2 = XRDC2_MAKE_PERIPH(1, 2 ), /**< SAI2 */
kXRDC2_Periph_SAI1 = XRDC2_MAKE_PERIPH(1, 1 ), /**< SAI1 */
kXRDC2_Periph_SPDIF = XRDC2_MAKE_PERIPH(1, 0 ), /**< SPDIF */
kXRDC2_Periph_VIDEO_MUX = XRDC2_MAKE_PERIPH(2, 6 ), /**< VIDEO_MUX */
kXRDC2_Periph_PXP = XRDC2_MAKE_PERIPH(2, 5 ), /**< PXP */
kXRDC2_Periph_MIPI_CSI = XRDC2_MAKE_PERIPH(2, 4 ), /**< MIPI_CSI */
kXRDC2_Periph_MIPI_DSI = XRDC2_MAKE_PERIPH(2, 3 ), /**< MIPI_DSI */
kXRDC2_Periph_LCDIFV2 = XRDC2_MAKE_PERIPH(2, 2 ), /**< LCDIFV2 */
kXRDC2_Periph_LCDIF = XRDC2_MAKE_PERIPH(2, 1 ), /**< LCDIF */
kXRDC2_Periph_CSI = XRDC2_MAKE_PERIPH(2, 0 ), /**< CSI */
kXRDC2_Periph_XRDC2_MGR_M7_3 = XRDC2_MAKE_PERIPH(3, 59 ), /**< XRDC2_MGR_M7_3 */
kXRDC2_Periph_XRDC2_MGR_M7_2 = XRDC2_MAKE_PERIPH(3, 58 ), /**< XRDC2_MGR_M7_2 */
kXRDC2_Periph_XRDC2_MGR_M7_1 = XRDC2_MAKE_PERIPH(3, 57 ), /**< XRDC2_MGR_M7_1 */
kXRDC2_Periph_XRDC2_MGR_M7_0 = XRDC2_MAKE_PERIPH(3, 56 ), /**< XRDC2_MGR_M7_0 */
kXRDC2_Periph_XRDC2_MGR_M4_3 = XRDC2_MAKE_PERIPH(3, 55 ), /**< XRDC2_MGR_M4_3 */
kXRDC2_Periph_XRDC2_MGR_M4_2 = XRDC2_MAKE_PERIPH(3, 54 ), /**< XRDC2_MGR_M4_2 */
kXRDC2_Periph_XRDC2_MGR_M4_1 = XRDC2_MAKE_PERIPH(3, 53 ), /**< XRDC2_MGR_M4_1 */
kXRDC2_Periph_XRDC2_MGR_M4_0 = XRDC2_MAKE_PERIPH(3, 52 ), /**< XRDC2_MGR_M4_0 */
kXRDC2_Periph_SEMA2 = XRDC2_MAKE_PERIPH(3, 51 ), /**< SEMA2 */
kXRDC2_Periph_SEMA_HS = XRDC2_MAKE_PERIPH(3, 50 ), /**< SEMA_HS */
kXRDC2_Periph_CCM_1 = XRDC2_MAKE_PERIPH(3, 49 ), /**< CCM_1 */
kXRDC2_Periph_CCM_0 = XRDC2_MAKE_PERIPH(3, 48 ), /**< CCM_0 */
kXRDC2_Periph_SSARC_LP = XRDC2_MAKE_PERIPH(3, 46 ), /**< SSARC_LP */
kXRDC2_Periph_SSARC_HP = XRDC2_MAKE_PERIPH(3, 45 ), /**< SSARC_HP */
kXRDC2_Periph_PIT2 = XRDC2_MAKE_PERIPH(3, 44 ), /**< PIT2 */
kXRDC2_Periph_OCOTP_CTRL_WRAPPER = XRDC2_MAKE_PERIPH(3, 43 ), /**< OCOTP_CTRL_WRAPPER */
kXRDC2_Periph_DCDC = XRDC2_MAKE_PERIPH(3, 42 ), /**< DCDC */
kXRDC2_Periph_ROMCP = XRDC2_MAKE_PERIPH(3, 41 ), /**< ROMCP */
kXRDC2_Periph_GPIO13 = XRDC2_MAKE_PERIPH(3, 40 ), /**< GPIO13 */
kXRDC2_Periph_SNVS_SRAM = XRDC2_MAKE_PERIPH(3, 39 ), /**< SNVS_SRAM */
kXRDC2_Periph_IOMUXC_SNVS_GPR = XRDC2_MAKE_PERIPH(3, 38 ), /**< IOMUXC_SNVS_GPR */
kXRDC2_Periph_IOMUXC_SNVS = XRDC2_MAKE_PERIPH(3, 37 ), /**< IOMUXC_SNVS */
kXRDC2_Periph_SNVS_HP_WRAPPER = XRDC2_MAKE_PERIPH(3, 36 ), /**< SNVS_HP_WRAPPER */
kXRDC2_Periph_PGMC = XRDC2_MAKE_PERIPH(3, 34 ), /**< PGMC */
kXRDC2_Periph_ANATOP = XRDC2_MAKE_PERIPH(3, 33 ), /**< ANATOP */
kXRDC2_Periph_KEY_MANAGER = XRDC2_MAKE_PERIPH(3, 32 ), /**< KEY_MANAGER */
kXRDC2_Periph_RDC = XRDC2_MAKE_PERIPH(3, 30 ), /**< RDC */
kXRDC2_Periph_GPIO12 = XRDC2_MAKE_PERIPH(3, 28 ), /**< GPIO12 */
kXRDC2_Periph_GPIO11 = XRDC2_MAKE_PERIPH(3, 27 ), /**< GPIO11 */
kXRDC2_Periph_GPIO10 = XRDC2_MAKE_PERIPH(3, 26 ), /**< GPIO10 */
kXRDC2_Periph_GPIO9 = XRDC2_MAKE_PERIPH(3, 25 ), /**< GPIO9 */
kXRDC2_Periph_GPIO8 = XRDC2_MAKE_PERIPH(3, 24 ), /**< GPIO8 */
kXRDC2_Periph_GPIO7 = XRDC2_MAKE_PERIPH(3, 23 ), /**< GPIO7 */
kXRDC2_Periph_MU_B = XRDC2_MAKE_PERIPH(3, 19 ), /**< MU_B */
kXRDC2_Periph_MU_A = XRDC2_MAKE_PERIPH(3, 18 ), /**< MU_A */
kXRDC2_Periph_SEMA1 = XRDC2_MAKE_PERIPH(3, 17 ), /**< SEMA1 */
kXRDC2_Periph_SAI4 = XRDC2_MAKE_PERIPH(3, 16 ), /**< SAI4 */
kXRDC2_Periph_CAN3 = XRDC2_MAKE_PERIPH(3, 15 ), /**< CAN3 */
kXRDC2_Periph_LPI2C6 = XRDC2_MAKE_PERIPH(3, 14 ), /**< LPI2C6 */
kXRDC2_Periph_LPI2C5 = XRDC2_MAKE_PERIPH(3, 13 ), /**< LPI2C5 */
kXRDC2_Periph_LPSPI6 = XRDC2_MAKE_PERIPH(3, 12 ), /**< LPSPI6 */
kXRDC2_Periph_LPSPI5 = XRDC2_MAKE_PERIPH(3, 11 ), /**< LPSPI5 */
kXRDC2_Periph_LPUART12 = XRDC2_MAKE_PERIPH(3, 10 ), /**< LPUART12 */
kXRDC2_Periph_LPUART11 = XRDC2_MAKE_PERIPH(3, 9 ), /**< LPUART11 */
kXRDC2_Periph_MIC = XRDC2_MAKE_PERIPH(3, 8 ), /**< MIC */
kXRDC2_Periph_DMA_CH_MUX_LPSR = XRDC2_MAKE_PERIPH(3, 6 ), /**< DMA_CH_MUX_LPSR */
kXRDC2_Periph_EDMA_LPSR = XRDC2_MAKE_PERIPH(3, 5 ), /**< EDMA_LPSR */
kXRDC2_Periph_WDOG4 = XRDC2_MAKE_PERIPH(3, 4 ), /**< WDOG4 */
kXRDC2_Periph_IOMUXC_LPSR_GPR = XRDC2_MAKE_PERIPH(3, 3 ), /**< IOMUXC_LPSR_GPR */
kXRDC2_Periph_IOMUXC_LPSR = XRDC2_MAKE_PERIPH(3, 2 ), /**< IOMUXC_LPSR */
kXRDC2_Periph_SRC = XRDC2_MAKE_PERIPH(3, 1 ), /**< SRC */
kXRDC2_Periph_GPC = XRDC2_MAKE_PERIPH(3, 0 ), /**< GPC */
kXRDC2_Periph_GPU = XRDC2_MAKE_PERIPH(4, 0 ), /**< GPU */
} xrdc2_periph_t;
/* @} */
/*!
* @addtogroup asrc_clock_source
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @brief The ASRC clock source
*/
typedef enum _asrc_clock_source
{
kASRC_ClockSourceNotAvalible = -1U, /**< not avalible */
kASRC_ClockSourceBitClock0_SAI1_TX = 0U, /**< SAI1 TX */
kASRC_ClockSourceBitClock1_SAI1_RX = 1U, /**< SAI1 RX */
kASRC_ClockSourceBitClock2_SAI2_TX = 2U, /**< SAI2 TX */
kASRC_ClockSourceBitClock3_SAI2_RX = 3U, /**< SAI2 RX */
kASRC_ClockSourceBitClock4_SAI3_TX = 4U, /**< SAI3 TX */
kASRC_ClockSourceBitClock5_SAI3_RX = 5U, /**< SAI3 RX */
kASRC_ClockSourceBitClock6_SAI4_TX = 6U, /**< SAI4 TX */
kASRC_ClockSourceBitClock7_SAI4_RX = 7U, /**< SAI4 RX */
kASRC_ClockSourceBitClock8_SPDIF_TX = 8U, /**< SPDIF TX */
kASRC_ClockSourceBitClock9_SPDIF_RX = 9U, /**< SPDIF RX */
kASRC_ClockSourceBitClocka_SAI2_CLOCK_ROOT = 10U, /**< SAI2 CLOCK ROOT */
kASRC_ClockSourceBitClockb_SAI3_CLOCK_ROOT = 11U, /**< SAI3 CLOCK ROOT */
kASRC_ClockSourceBitClockc_SAI4_CLOCK_ROOT = 12U, /**< SAI4 CLOCK ROOT */
kASRC_ClockSourceBitClockd_MIC_CLOCK_ROOT = 13U, /**< MIC CLOCK ROOT */
kASRC_ClockSourceBitClocke_MQS_CLOCK_ROOT = 14U, /**< MQS CLOCK ROOT */
} asrc_clock_source_t;
/*!
* @addtogroup edma_request
* @{
*/
/*******************************************************************************
* Definitions
******************************************************************************/
/*!
* @brief Structure for the DMA hardware request
*
* Defines the structure for the DMA hardware request collections. The user can configure the
* hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
* of the hardware request varies according to the to SoC.
*/
typedef enum _dma_request_source
{
kDmaRequestMuxFlexIO1Request2Request3 = 1|0x100U, /**< FlexIO1 Request2 and Request3 */
kDmaRequestMuxFlexIO1Request4Request5 = 2|0x100U, /**< FlexIO1 Request4 and Request5 */
kDmaRequestMuxFlexIO1Request6Request7 = 3|0x100U, /**< FlexIO1 Request6 and Request7 */
kDmaRequestMuxFlexIO2Request0Request1 = 4|0x100U, /**< FlexIO2 Request0 and Request1 */
kDmaRequestMuxFlexIO2Request2Request3 = 5|0x100U, /**< FlexIO2 Request2 and Request3 */
kDmaRequestMuxFlexIO2Request4Request5 = 6|0x100U, /**< FlexIO2 Request4 and Request5 */
kDmaRequestMuxFlexIO2Request6Request7 = 7|0x100U, /**< FlexIO2 Request6 and Request7 */
kDmaRequestMuxLPUART1Tx = 8|0x100U, /**< LPUART1 Transmit */
kDmaRequestMuxLPUART1Rx = 9|0x100U, /**< LPUART1 Receive */
kDmaRequestMuxLPUART2Tx = 10|0x100U, /**< LPUART2 Transmit */
kDmaRequestMuxLPUART2Rx = 11|0x100U, /**< LPUART2 Receive */
kDmaRequestMuxLPUART3Tx = 12|0x100U, /**< LPUART3 Transmit */
kDmaRequestMuxLPUART3Rx = 13|0x100U, /**< LPUART3 Receive */
kDmaRequestMuxLPUART4Tx = 14|0x100U, /**< LPUART4 Transmit */
kDmaRequestMuxLPUART4Rx = 15|0x100U, /**< LPUART4 Receive */
kDmaRequestMuxLPUART5Tx = 16|0x100U, /**< LPUART5 Transmit */
kDmaRequestMuxLPUART5Rx = 17|0x100U, /**< LPUART5 Receive */
kDmaRequestMuxLPUART6Tx = 18|0x100U, /**< LPUART6 Transmit */
kDmaRequestMuxLPUART6Rx = 19|0x100U, /**< LPUART6 Receive */
kDmaRequestMuxLPUART7Tx = 20|0x100U, /**< LPUART7 Transmit */
kDmaRequestMuxLPUART7Rx = 21|0x100U, /**< LPUART7 Receive */
kDmaRequestMuxLPUART8Tx = 22|0x100U, /**< LPUART8 Transmit */
kDmaRequestMuxLPUART8Rx = 23|0x100U, /**< LPUART8 Receive */
kDmaRequestMuxLPUART9Tx = 24|0x100U, /**< LPUART9 Transmit */
kDmaRequestMuxLPUART9Rx = 25|0x100U, /**< LPUART9 Receive */
kDmaRequestMuxLPUART10Tx = 26|0x100U, /**< LPUART10 Transmit */
kDmaRequestMuxLPUART10Rx = 27|0x100U, /**< LPUART10 Receive */
kDmaRequestMuxLPUART11Tx = 28|0x100U, /**< LPUART11 Transmit */
kDmaRequestMuxLPUART11Rx = 29|0x100U, /**< LPUART11 Receive */
kDmaRequestMuxLPUART12Tx = 30|0x100U, /**< LPUART12 Transmit */
kDmaRequestMuxLPUART12Rx = 31|0x100U, /**< LPUART12 Receive */
kDmaRequestMuxCSI = 32|0x100U, /**< CSI */
kDmaRequestMuxPxp = 33|0x100U, /**< PXP */
kDmaRequestMuxeLCDIF = 34|0x100U, /**< eLCDIF */
kDmaRequestMuxLCDIFv2 = 35|0x100U, /**< LCDIFv2 */
kDmaRequestMuxLPSPI1Rx = 36|0x100U, /**< LPSPI1 Receive */
kDmaRequestMuxLPSPI1Tx = 37|0x100U, /**< LPSPI1 Transmit */
kDmaRequestMuxLPSPI2Rx = 38|0x100U, /**< LPSPI2 Receive */
kDmaRequestMuxLPSPI2Tx = 39|0x100U, /**< LPSPI2 Transmit */
kDmaRequestMuxLPSPI3Rx = 40|0x100U, /**< LPSPI3 Receive */
kDmaRequestMuxLPSPI3Tx = 41|0x100U, /**< LPSPI3 Transmit */
kDmaRequestMuxLPSPI4Rx = 42|0x100U, /**< LPSPI4 Receive */
kDmaRequestMuxLPSPI4Tx = 43|0x100U, /**< LPSPI4 Transmit */
kDmaRequestMuxLPSPI5Rx = 44|0x100U, /**< LPSPI5 Receive */
kDmaRequestMuxLPSPI5Tx = 45|0x100U, /**< LPSPI5 Transmit */
kDmaRequestMuxLPSPI6Rx = 46|0x100U, /**< LPSPI6 Receive */
kDmaRequestMuxLPSPI6Tx = 47|0x100U, /**< LPSPI6 Transmit */
kDmaRequestMuxLPI2C1 = 48|0x100U, /**< LPI2C1 */
kDmaRequestMuxLPI2C2 = 49|0x100U, /**< LPI2C2 */
kDmaRequestMuxLPI2C3 = 50|0x100U, /**< LPI2C3 */
kDmaRequestMuxLPI2C4 = 51|0x100U, /**< LPI2C4 */
kDmaRequestMuxLPI2C5 = 52|0x100U, /**< LPI2C5 */
kDmaRequestMuxLPI2C6 = 53|0x100U, /**< LPI2C6 */
kDmaRequestMuxSai1Rx = 54|0x100U, /**< SAI1 Receive */
kDmaRequestMuxSai1Tx = 55|0x100U, /**< SAI1 Transmit */
kDmaRequestMuxSai2Rx = 56|0x100U, /**< SAI2 Receive */
kDmaRequestMuxSai2Tx = 57|0x100U, /**< SAI2 Transmit */
kDmaRequestMuxSai3Rx = 58|0x100U, /**< SAI3 Receive */
kDmaRequestMuxSai3Tx = 59|0x100U, /**< SAI3 Transmit */
kDmaRequestMuxSai4Rx = 60|0x100U, /**< SAI4 Receive */
kDmaRequestMuxSai4Tx = 61|0x100U, /**< SAI4 Transmit */
kDmaRequestMuxSpdifRx = 62|0x100U, /**< SPDIF Receive */
kDmaRequestMuxSpdifTx = 63|0x100U, /**< SPDIF Transmit */
kDmaRequestMuxADC_ETC = 64|0x100U, /**< ADC_ETC */
kDmaRequestMuxFlexIO1Request0Request1 = 65|0x100U, /**< FlexIO1 Request0 and Request1 */
kDmaRequestMuxADC1 = 66|0x100U, /**< ADC1 */
kDmaRequestMuxADC2 = 67|0x100U, /**< ADC2 */
kDmaRequestMuxACMP1 = 69|0x100U, /**< ACMP1 */
kDmaRequestMuxACMP2 = 70|0x100U, /**< ACMP2 */
kDmaRequestMuxACMP3 = 71|0x100U, /**< ACMP3 */
kDmaRequestMuxACMP4 = 72|0x100U, /**< ACMP4 */
kDmaRequestMuxFlexSPI1Rx = 77|0x100U, /**< FlexSPI1 Receive */
kDmaRequestMuxFlexSPI1Tx = 78|0x100U, /**< FlexSPI1 Transmit */
kDmaRequestMuxFlexSPI2Rx = 79|0x100U, /**< FlexSPI2 Receive */
kDmaRequestMuxFlexSPI2Tx = 80|0x100U, /**< FlexSPI2 Transmit */
kDmaRequestMuxXBAR1Request0 = 81|0x100U, /**< XBAR1 Request 0 */
kDmaRequestMuxXBAR1Request1 = 82|0x100U, /**< XBAR1 Request 1 */
kDmaRequestMuxXBAR1Request2 = 83|0x100U, /**< XBAR1 Request 2 */
kDmaRequestMuxXBAR1Request3 = 84|0x100U, /**< XBAR1 Request 3 */
kDmaRequestMuxFlexPWM1CaptureSub0 = 85|0x100U, /**< FlexPWM1 Capture sub-module0 */
kDmaRequestMuxFlexPWM1CaptureSub1 = 86|0x100U, /**< FlexPWM1 Capture sub-module1 */
kDmaRequestMuxFlexPWM1CaptureSub2 = 87|0x100U, /**< FlexPWM1 Capture sub-module2 */
kDmaRequestMuxFlexPWM1CaptureSub3 = 88|0x100U, /**< FlexPWM1 Capture sub-module3 */
kDmaRequestMuxFlexPWM1ValueSub0 = 89|0x100U, /**< FlexPWM1 Value sub-module 0 */
kDmaRequestMuxFlexPWM1ValueSub1 = 90|0x100U, /**< FlexPWM1 Value sub-module 1 */
kDmaRequestMuxFlexPWM1ValueSub2 = 91|0x100U, /**< FlexPWM1 Value sub-module 2 */
kDmaRequestMuxFlexPWM1ValueSub3 = 92|0x100U, /**< FlexPWM1 Value sub-module 3 */
kDmaRequestMuxFlexPWM2CaptureSub0 = 93|0x100U, /**< FlexPWM2 Capture sub-module0 */
kDmaRequestMuxFlexPWM2CaptureSub1 = 94|0x100U, /**< FlexPWM2 Capture sub-module1 */
kDmaRequestMuxFlexPWM2CaptureSub2 = 95|0x100U, /**< FlexPWM2 Capture sub-module2 */
kDmaRequestMuxFlexPWM2CaptureSub3 = 96|0x100U, /**< FlexPWM2 Capture sub-module3 */
kDmaRequestMuxFlexPWM2ValueSub0 = 97|0x100U, /**< FlexPWM2 Value sub-module 0 */
kDmaRequestMuxFlexPWM2ValueSub1 = 98|0x100U, /**< FlexPWM2 Value sub-module 1 */
kDmaRequestMuxFlexPWM2ValueSub2 = 99|0x100U, /**< FlexPWM2 Value sub-module 2 */
kDmaRequestMuxFlexPWM2ValueSub3 = 100|0x100U, /**< FlexPWM2 Value sub-module 3 */
kDmaRequestMuxFlexPWM3CaptureSub0 = 101|0x100U, /**< FlexPWM3 Capture sub-module0 */
kDmaRequestMuxFlexPWM3CaptureSub1 = 102|0x100U, /**< FlexPWM3 Capture sub-module1 */
kDmaRequestMuxFlexPWM3CaptureSub2 = 103|0x100U, /**< FlexPWM3 Capture sub-module2 */
kDmaRequestMuxFlexPWM3CaptureSub3 = 104|0x100U, /**< FlexPWM3 Capture sub-module3 */
kDmaRequestMuxFlexPWM3ValueSub0 = 105|0x100U, /**< FlexPWM3 Value sub-module 0 */
kDmaRequestMuxFlexPWM3ValueSub1 = 106|0x100U, /**< FlexPWM3 Value sub-module 1 */
kDmaRequestMuxFlexPWM3ValueSub2 = 107|0x100U, /**< FlexPWM3 Value sub-module 2 */
kDmaRequestMuxFlexPWM3ValueSub3 = 108|0x100U, /**< FlexPWM3 Value sub-module 3 */
kDmaRequestMuxFlexPWM4CaptureSub0 = 109|0x100U, /**< FlexPWM4 Capture sub-module0 */
kDmaRequestMuxFlexPWM4CaptureSub1 = 110|0x100U, /**< FlexPWM4 Capture sub-module1 */
kDmaRequestMuxFlexPWM4CaptureSub2 = 111|0x100U, /**< FlexPWM4 Capture sub-module2 */
kDmaRequestMuxFlexPWM4CaptureSub3 = 112|0x100U, /**< FlexPWM4 Capture sub-module3 */
kDmaRequestMuxFlexPWM4ValueSub0 = 113|0x100U, /**< FlexPWM4 Value sub-module 0 */
kDmaRequestMuxFlexPWM4ValueSub1 = 114|0x100U, /**< FlexPWM4 Value sub-module 1 */
kDmaRequestMuxFlexPWM4ValueSub2 = 115|0x100U, /**< FlexPWM4 Value sub-module 2 */
kDmaRequestMuxFlexPWM4ValueSub3 = 116|0x100U, /**< FlexPWM4 Value sub-module 3 */
kDmaRequestMuxQTIMER1CaptTimer0 = 133|0x100U, /**< TMR1 Capture timer 0 */
kDmaRequestMuxQTIMER1CaptTimer1 = 134|0x100U, /**< TMR1 Capture timer 1 */
kDmaRequestMuxQTIMER1CaptTimer2 = 135|0x100U, /**< TMR1 Capture timer 2 */
kDmaRequestMuxQTIMER1CaptTimer3 = 136|0x100U, /**< TMR1 Capture timer 3 */
kDmaRequestMuxQTIMER1Cmpld1Timer0Cmpld2Timer1 = 137|0x100U, /**< TMR1 cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER1Cmpld1Timer1Cmpld2Timer0 = 138|0x100U, /**< TMR1 cmpld1 in timer 1 or cmpld2 in timer 0 */
kDmaRequestMuxQTIMER1Cmpld1Timer2Cmpld2Timer3 = 139|0x100U, /**< TMR1 cmpld1 in timer 2 or cmpld2 in timer 3 */
kDmaRequestMuxQTIMER1Cmpld1Timer3Cmpld2Timer2 = 140|0x100U, /**< TMR1 cmpld1 in timer 3 or cmpld2 in timer 2 */
kDmaRequestMuxQTIMER2CaptTimer0 = 141|0x100U, /**< TMR2 Capture timer 0 */
kDmaRequestMuxQTIMER2CaptTimer1 = 142|0x100U, /**< TMR2 Capture timer 1 */
kDmaRequestMuxQTIMER2CaptTimer2 = 143|0x100U, /**< TMR2 Capture timer 2 */
kDmaRequestMuxQTIMER2CaptTimer3 = 144|0x100U, /**< TMR2 Capture timer 3 */
kDmaRequestMuxQTIMER2Cmpld1Timer0Cmpld2Timer1 = 145|0x100U, /**< TMR2 cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER2Cmpld1Timer1Cmpld2Timer0 = 146|0x100U, /**< TMR2 cmpld1 in timer 1 or cmpld2 in timer 0 */
kDmaRequestMuxQTIMER2Cmpld1Timer2Cmpld2Timer3 = 147|0x100U, /**< TMR2 cmpld1 in timer 2 or cmpld2 in timer 3 */
kDmaRequestMuxQTIMER2Cmpld1Timer3Cmpld2Timer2 = 148|0x100U, /**< TMR2 cmpld1 in timer 3 or cmpld2 in timer 2 */
kDmaRequestMuxQTIMER3CaptTimer0 = 149|0x100U, /**< TMR3 Capture timer 0 */
kDmaRequestMuxQTIMER3CaptTimer1 = 150|0x100U, /**< TMR3 Capture timer 1 */
kDmaRequestMuxQTIMER3CaptTimer2 = 151|0x100U, /**< TMR3 Capture timer 2 */
kDmaRequestMuxQTIMER3CaptTimer3 = 152|0x100U, /**< TMR3 Capture timer 3 */
kDmaRequestMuxQTIMER3Cmpld1Timer0Cmpld2Timer1 = 153|0x100U, /**< TMR3 cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER3Cmpld1Timer1Cmpld2Timer0 = 154|0x100U, /**< TMR3 cmpld1 in timer 1 or cmpld2 in timer 0 */
kDmaRequestMuxQTIMER3Cmpld1Timer2Cmpld2Timer3 = 155|0x100U, /**< TMR3 cmpld1 in timer 2 or cmpld2 in timer 3 */
kDmaRequestMuxQTIMER3Cmpld1Timer3Cmpld2Timer2 = 156|0x100U, /**< TMR3 cmpld1 in timer 3 or cmpld2 in timer 2 */
kDmaRequestMuxQTIMER4CaptTimer0 = 157|0x100U, /**< TMR4 Capture timer 0 */
kDmaRequestMuxQTIMER4CaptTimer1 = 158|0x100U, /**< TMR4 Capture timer 1 */
kDmaRequestMuxQTIMER4CaptTimer2 = 159|0x100U, /**< TMR4 Capture timer 2 */
kDmaRequestMuxQTIMER4CaptTimer3 = 160|0x100U, /**< TMR4 Capture timer 3 */
kDmaRequestMuxQTIMER4Cmpld1Timer0Cmpld2Timer1 = 161|0x100U, /**< TMR4 cmpld1 in timer 0 or cmpld2 in timer 1 */
kDmaRequestMuxQTIMER4Cmpld1Timer1Cmpld2Timer0 = 162|0x100U, /**< TMR4 cmpld1 in timer 1 or cmpld2 in timer 0 */
kDmaRequestMuxQTIMER4Cmpld1Timer2Cmpld2Timer3 = 163|0x100U, /**< TMR4 cmpld1 in timer 2 or cmpld2 in timer 3 */
kDmaRequestMuxQTIMER4Cmpld1Timer3Cmpld2Timer2 = 164|0x100U, /**< TMR4 cmpld1 in timer 3 or cmpld2 in timer 2 */
kDmaRequestMuxPdm = 181|0x100U, /**< PDM */
kDmaRequestMuxEnetTimer0 = 182|0x100U, /**< ENET Timer0 */
kDmaRequestMuxEnetTimer1 = 183|0x100U, /**< ENET Timer1 */
kDmaRequestMuxEnet1GTimer0 = 184|0x100U, /**< ENET 1G Timer0 */
kDmaRequestMuxEnet1GTimer1 = 185|0x100U, /**< ENET 1G Timer1 */
kDmaRequestMuxCAN1 = 186|0x100U, /**< CAN1 */
kDmaRequestMuxCAN2 = 187|0x100U, /**< CAN2 */
kDmaRequestMuxCAN3 = 188|0x100U, /**< CAN3 */
kDmaRequestMuxDAC = 189|0x100U, /**< DAC */
kDmaRequestMuxASRCRequest1 = 191|0x100U, /**< ASRC request 1 pair A input request */
kDmaRequestMuxASRCRequest2 = 192|0x100U, /**< ASRC request 2 pair B input request */
kDmaRequestMuxASRCRequest3 = 193|0x100U, /**< ASRC request 3 pair C input request */
kDmaRequestMuxASRCRequest4 = 194|0x100U, /**< ASRC request 4 pair A output request */
kDmaRequestMuxASRCRequest5 = 195|0x100U, /**< ASRC request 5 pair B output request */
kDmaRequestMuxASRCRequest6 = 196|0x100U, /**< ASRC request 6 pair C output request */
kDmaRequestMuxEmvsim1Tx = 197|0x100U, /**< Emvsim1 Transmit */
kDmaRequestMuxEmvsim1Rx = 198|0x100U, /**< Emvsim1 Receive */
kDmaRequestMuxEmvsim2Tx = 199|0x100U, /**< Emvsim2 Transmit */
kDmaRequestMuxEmvsim2Rx = 200|0x100U, /**< Emvsim2 Receive */
kDmaRequestMuxEnetQosTimer0 = 201|0x100U, /**< ENET_QOS Timer0 */
kDmaRequestMuxEnetQosTimer1 = 202|0x100U, /**< ENET_QOS Timer1 */
} dma_request_source_t;
/* @} */
/*!
* @addtogroup iomuxc_pads
* @{ */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @brief Enumeration for the IOMUXC SW_MUX_CTL_PAD
*
* Defines the enumeration for the IOMUXC SW_MUX_CTL_PAD collections.
*/
typedef enum _iomuxc_sw_mux_ctl_pad
{
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_00 = 0U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_01 = 1U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_02 = 2U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_03 = 3U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_04 = 4U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_05 = 5U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_06 = 6U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_07 = 7U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_08 = 8U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_09 = 9U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_10 = 10U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_11 = 11U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_12 = 12U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_13 = 13U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_14 = 14U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_15 = 15U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_16 = 16U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_17 = 17U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_18 = 18U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_19 = 19U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_20 = 20U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_21 = 21U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_22 = 22U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_23 = 23U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_24 = 24U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_25 = 25U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_26 = 26U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_27 = 27U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_28 = 28U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_29 = 29U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_30 = 30U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_31 = 31U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_32 = 32U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_33 = 33U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_34 = 34U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_35 = 35U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_36 = 36U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_37 = 37U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_38 = 38U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_39 = 39U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_40 = 40U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B1_41 = 41U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_00 = 42U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_01 = 43U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_02 = 44U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_03 = 45U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_04 = 46U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_05 = 47U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_06 = 48U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_07 = 49U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_08 = 50U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_09 = 51U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_10 = 52U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_11 = 53U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_12 = 54U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_13 = 55U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_14 = 56U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_15 = 57U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_16 = 58U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_17 = 59U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_18 = 60U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_19 = 61U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_EMC_B2_20 = 62U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_00 = 63U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_01 = 64U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_02 = 65U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_03 = 66U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_04 = 67U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_05 = 68U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_06 = 69U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_07 = 70U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_08 = 71U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_09 = 72U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_10 = 73U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_11 = 74U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_12 = 75U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_13 = 76U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_14 = 77U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_15 = 78U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_16 = 79U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_17 = 80U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_18 = 81U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_19 = 82U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_20 = 83U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_21 = 84U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_22 = 85U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_23 = 86U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_24 = 87U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_25 = 88U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_26 = 89U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_27 = 90U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_28 = 91U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_29 = 92U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_30 = 93U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_31 = 94U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_32 = 95U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_33 = 96U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_34 = 97U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_AD_35 = 98U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_00 = 99U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_01 = 100U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_02 = 101U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_03 = 102U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_04 = 103U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B1_05 = 104U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_00 = 105U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_01 = 106U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_02 = 107U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_03 = 108U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_04 = 109U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_05 = 110U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_06 = 111U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_07 = 112U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_08 = 113U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_09 = 114U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_10 = 115U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_SD_B2_11 = 116U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_00 = 117U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_01 = 118U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_02 = 119U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_03 = 120U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_04 = 121U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_05 = 122U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_06 = 123U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_07 = 124U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_08 = 125U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_09 = 126U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_10 = 127U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B1_11 = 128U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_00 = 129U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_01 = 130U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_02 = 131U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_03 = 132U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_04 = 133U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_05 = 134U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_06 = 135U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_07 = 136U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_08 = 137U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_09 = 138U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_10 = 139U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_11 = 140U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_12 = 141U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_13 = 142U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_14 = 143U, /**< IOMUXC SW_MUX_CTL_PAD index */
kIOMUXC_SW_MUX_CTL_PAD_GPIO_DISP_B2_15 = 144U, /**< IOMUXC SW_MUX_CTL_PAD index */
} iomuxc_sw_mux_ctl_pad_t;
/* @} */
/*!
* @addtogroup iomuxc_pads
* @{ */
/*******************************************************************************
* Definitions
*******************************************************************************/
/*!
* @brief Enumeration for the IOMUXC SW_PAD_CTL_PAD
*
* Defines the enumeration for the IOMUXC SW_PAD_CTL_PAD collections.
*/
typedef enum _iomuxc_sw_pad_ctl_pad
{
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_00 = 0U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_01 = 1U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_02 = 2U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_03 = 3U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_04 = 4U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_05 = 5U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_06 = 6U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_07 = 7U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_08 = 8U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_09 = 9U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_10 = 10U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_11 = 11U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_12 = 12U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_13 = 13U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_14 = 14U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_15 = 15U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_16 = 16U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_17 = 17U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_18 = 18U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_19 = 19U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_20 = 20U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_21 = 21U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_22 = 22U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_23 = 23U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_24 = 24U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_25 = 25U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_26 = 26U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_27 = 27U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_28 = 28U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_29 = 29U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_30 = 30U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_31 = 31U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_32 = 32U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_33 = 33U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_34 = 34U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_35 = 35U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_36 = 36U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_37 = 37U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_38 = 38U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_39 = 39U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_40 = 40U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B1_41 = 41U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_00 = 42U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_01 = 43U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_02 = 44U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_03 = 45U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_04 = 46U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_05 = 47U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_06 = 48U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_07 = 49U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_08 = 50U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_09 = 51U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_10 = 52U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_11 = 53U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_12 = 54U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_13 = 55U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_14 = 56U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_15 = 57U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_16 = 58U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_17 = 59U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_18 = 60U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_19 = 61U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_EMC_B2_20 = 62U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_00 = 63U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_01 = 64U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_02 = 65U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_03 = 66U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_04 = 67U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_05 = 68U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_06 = 69U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_07 = 70U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_08 = 71U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_09 = 72U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_10 = 73U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_11 = 74U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_12 = 75U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_13 = 76U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_14 = 77U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_15 = 78U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_16 = 79U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_17 = 80U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_18 = 81U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_19 = 82U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_20 = 83U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_21 = 84U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_22 = 85U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_23 = 86U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_24 = 87U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_25 = 88U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_26 = 89U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_27 = 90U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_28 = 91U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_29 = 92U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_30 = 93U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_31 = 94U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_32 = 95U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_33 = 96U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_34 = 97U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_AD_35 = 98U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_00 = 99U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_01 = 100U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_02 = 101U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_03 = 102U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_04 = 103U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B1_05 = 104U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_00 = 105U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_01 = 106U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_02 = 107U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_03 = 108U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_04 = 109U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_05 = 110U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_06 = 111U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_07 = 112U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_08 = 113U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_09 = 114U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_10 = 115U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_SD_B2_11 = 116U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_00 = 117U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_01 = 118U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_02 = 119U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_03 = 120U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_04 = 121U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_05 = 122U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_06 = 123U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_07 = 124U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_08 = 125U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_09 = 126U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_10 = 127U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B1_11 = 128U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_00 = 129U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_01 = 130U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_02 = 131U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_03 = 132U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_04 = 133U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_05 = 134U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_06 = 135U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_07 = 136U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_08 = 137U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_09 = 138U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_10 = 139U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_11 = 140U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_12 = 141U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_13 = 142U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_14 = 143U, /**< IOMUXC SW_PAD_CTL_PAD index */
kIOMUXC_SW_PAD_CTL_PAD_GPIO_DISP_B2_15 = 144U, /**< IOMUXC SW_PAD_CTL_PAD index */
} iomuxc_sw_pad_ctl_pad_t;
/* @} */
/*!
* @brief Enumeration for the IOMUXC select input
*
* Defines the enumeration for the IOMUXC select input collections.
*/
typedef enum _iomuxc_select_input
{
kIOMUXC_FLEXCAN1_RX_SELECT_INPUT = 0U, /**< IOMUXC select input index */
kIOMUXC_FLEXCAN2_RX_SELECT_INPUT = 1U, /**< IOMUXC select input index */
kIOMUXC_CCM_ENET_QOS_REF_CLK_SELECT_INPUT = 2U, /**< IOMUXC select input index */
kIOMUXC_CCM_ENET_QOS_TX_CLK_SELECT_INPUT = 3U, /**< IOMUXC select input index */
kIOMUXC_ENET_IPG_CLK_RMII_SELECT_INPUT = 4U, /**< IOMUXC select input index */
kIOMUXC_ENET_MAC0_MDIO_SELECT_INPUT = 5U, /**< IOMUXC select input index */
kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_0 = 6U, /**< IOMUXC select input index */
kIOMUXC_ENET_MAC0_RXDATA_SELECT_INPUT_1 = 7U, /**< IOMUXC select input index */
kIOMUXC_ENET_MAC0_RXEN_SELECT_INPUT = 8U, /**< IOMUXC select input index */
kIOMUXC_ENET_MAC0_RXERR_SELECT_INPUT = 9U, /**< IOMUXC select input index */
kIOMUXC_ENET_MAC0_TXCLK_SELECT_INPUT = 10U, /**< IOMUXC select input index */
kIOMUXC_ENET_1G_IPG_CLK_RMII_SELECT_INPUT = 11U, /**< IOMUXC select input index */
kIOMUXC_ENET_1G_MAC0_MDIO_SELECT_INPUT = 12U, /**< IOMUXC select input index */
kIOMUXC_ENET_1G_MAC0_RXCLK_SELECT_INPUT = 13U, /**< IOMUXC select input index */
kIOMUXC_ENET_1G_MAC0_RXDATA_0_SELECT_INPUT = 14U, /**< IOMUXC select input index */
kIOMUXC_ENET_1G_MAC0_RXDATA_1_SELECT_INPUT = 15U, /**< IOMUXC select input index */
kIOMUXC_ENET_1G_MAC0_RXDATA_2_SELECT_INPUT = 16U, /**< IOMUXC select input index */
kIOMUXC_ENET_1G_MAC0_RXDATA_3_SELECT_INPUT = 17U, /**< IOMUXC select input index */
kIOMUXC_ENET_1G_MAC0_RXEN_SELECT_INPUT = 18U, /**< IOMUXC select input index */
kIOMUXC_ENET_1G_MAC0_RXERR_SELECT_INPUT = 19U, /**< IOMUXC select input index */
kIOMUXC_ENET_1G_MAC0_TXCLK_SELECT_INPUT = 20U, /**< IOMUXC select input index */
kIOMUXC_ENET_QOS_GMII_MDI_I_SELECT_INPUT = 21U, /**< IOMUXC select input index */
kIOMUXC_ENET_QOS_PHY_RXD_I_SELECT_INPUT_0 = 22U, /**< IOMUXC select input index */
kIOMUXC_ENET_QOS_PHY_RXD_I_SELECT_INPUT_1 = 23U, /**< IOMUXC select input index */
kIOMUXC_ENET_QOS_PHY_RXDV_I_SELECT_INPUT = 24U, /**< IOMUXC select input index */
kIOMUXC_ENET_QOS_PHY_RXER_I_SELECT_INPUT = 25U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_0 = 26U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_1 = 27U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMA_SELECT_INPUT_2 = 28U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_0 = 29U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_1 = 30U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM1_PWMB_SELECT_INPUT_2 = 31U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_0 = 32U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_1 = 33U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMA_SELECT_INPUT_2 = 34U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_0 = 35U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_1 = 36U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM2_PWMB_SELECT_INPUT_2 = 37U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_0 = 38U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_1 = 39U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_2 = 40U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM3_PWMA_SELECT_INPUT_3 = 41U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_0 = 42U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_1 = 43U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_2 = 44U, /**< IOMUXC select input index */
kIOMUXC_FLEXPWM3_PWMB_SELECT_INPUT_3 = 45U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_DQS_FA_SELECT_INPUT = 46U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_0 = 47U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_1 = 48U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_2 = 49U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_IO_FA_SELECT_INPUT_3 = 50U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_0 = 51U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_1 = 52U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_2 = 53U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_IO_FB_SELECT_INPUT_3 = 54U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_SCK_FA_SELECT_INPUT = 55U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI1_I_SCK_FB_SELECT_INPUT = 56U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_0 = 57U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_1 = 58U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_2 = 59U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI2_I_IO_FA_SELECT_INPUT_3 = 60U, /**< IOMUXC select input index */
kIOMUXC_FLEXSPI2_I_SCK_FA_SELECT_INPUT = 61U, /**< IOMUXC select input index */
kIOMUXC_GPT3_CAPIN1_SELECT_INPUT = 62U, /**< IOMUXC select input index */
kIOMUXC_GPT3_CAPIN2_SELECT_INPUT = 63U, /**< IOMUXC select input index */
kIOMUXC_GPT3_CLKIN_SELECT_INPUT = 64U, /**< IOMUXC select input index */
kIOMUXC_KPP_COL_SELECT_INPUT_6 = 65U, /**< IOMUXC select input index */
kIOMUXC_KPP_COL_SELECT_INPUT_7 = 66U, /**< IOMUXC select input index */
kIOMUXC_KPP_ROW_SELECT_INPUT_6 = 67U, /**< IOMUXC select input index */
kIOMUXC_KPP_ROW_SELECT_INPUT_7 = 68U, /**< IOMUXC select input index */
kIOMUXC_LPI2C1_LPI2C_SCL_SELECT_INPUT = 69U, /**< IOMUXC select input index */
kIOMUXC_LPI2C1_LPI2C_SDA_SELECT_INPUT = 70U, /**< IOMUXC select input index */
kIOMUXC_LPI2C2_LPI2C_SCL_SELECT_INPUT = 71U, /**< IOMUXC select input index */
kIOMUXC_LPI2C2_LPI2C_SDA_SELECT_INPUT = 72U, /**< IOMUXC select input index */
kIOMUXC_LPI2C3_LPI2C_SCL_SELECT_INPUT = 73U, /**< IOMUXC select input index */
kIOMUXC_LPI2C3_LPI2C_SDA_SELECT_INPUT = 74U, /**< IOMUXC select input index */
kIOMUXC_LPI2C4_LPI2C_SCL_SELECT_INPUT = 75U, /**< IOMUXC select input index */
kIOMUXC_LPI2C4_LPI2C_SDA_SELECT_INPUT = 76U, /**< IOMUXC select input index */
kIOMUXC_LPSPI1_LPSPI_PCS_SELECT_INPUT_0 = 77U, /**< IOMUXC select input index */
kIOMUXC_LPSPI1_LPSPI_SCK_SELECT_INPUT = 78U, /**< IOMUXC select input index */
kIOMUXC_LPSPI1_LPSPI_SDI_SELECT_INPUT = 79U, /**< IOMUXC select input index */
kIOMUXC_LPSPI1_LPSPI_SDO_SELECT_INPUT = 80U, /**< IOMUXC select input index */
kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_0 = 81U, /**< IOMUXC select input index */
kIOMUXC_LPSPI2_LPSPI_PCS_SELECT_INPUT_1 = 82U, /**< IOMUXC select input index */
kIOMUXC_LPSPI2_LPSPI_SCK_SELECT_INPUT = 83U, /**< IOMUXC select input index */
kIOMUXC_LPSPI2_LPSPI_SDI_SELECT_INPUT = 84U, /**< IOMUXC select input index */
kIOMUXC_LPSPI2_LPSPI_SDO_SELECT_INPUT = 85U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_0 = 86U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_1 = 87U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_2 = 88U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_LPSPI_PCS_SELECT_INPUT_3 = 89U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_LPSPI_SCK_SELECT_INPUT = 90U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_LPSPI_SDI_SELECT_INPUT = 91U, /**< IOMUXC select input index */
kIOMUXC_LPSPI3_LPSPI_SDO_SELECT_INPUT = 92U, /**< IOMUXC select input index */
kIOMUXC_LPSPI4_LPSPI_PCS_SELECT_INPUT_0 = 93U, /**< IOMUXC select input index */
kIOMUXC_LPSPI4_LPSPI_SCK_SELECT_INPUT = 94U, /**< IOMUXC select input index */
kIOMUXC_LPSPI4_LPSPI_SDI_SELECT_INPUT = 95U, /**< IOMUXC select input index */
kIOMUXC_LPSPI4_LPSPI_SDO_SELECT_INPUT = 96U, /**< IOMUXC select input index */
kIOMUXC_LPUART1_LPUART_RXD_SELECT_INPUT = 97U, /**< IOMUXC select input index */
kIOMUXC_LPUART1_LPUART_TXD_SELECT_INPUT = 98U, /**< IOMUXC select input index */
kIOMUXC_LPUART10_LPUART_RXD_SELECT_INPUT = 99U, /**< IOMUXC select input index */
kIOMUXC_LPUART10_LPUART_TXD_SELECT_INPUT = 100U, /**< IOMUXC select input index */
kIOMUXC_LPUART7_LPUART_RXD_SELECT_INPUT = 101U, /**< IOMUXC select input index */
kIOMUXC_LPUART7_LPUART_TXD_SELECT_INPUT = 102U, /**< IOMUXC select input index */
kIOMUXC_LPUART8_LPUART_RXD_SELECT_INPUT = 103U, /**< IOMUXC select input index */
kIOMUXC_LPUART8_LPUART_TXD_SELECT_INPUT = 104U, /**< IOMUXC select input index */
kIOMUXC_QTIMER1_TMR0_INPUT_SELECT_INPUT = 105U, /**< IOMUXC select input index */
kIOMUXC_QTIMER1_TMR1_INPUT_SELECT_INPUT = 106U, /**< IOMUXC select input index */
kIOMUXC_QTIMER1_TMR2_INPUT_SELECT_INPUT = 107U, /**< IOMUXC select input index */
kIOMUXC_QTIMER2_TMR0_INPUT_SELECT_INPUT = 108U, /**< IOMUXC select input index */
kIOMUXC_QTIMER2_TMR1_INPUT_SELECT_INPUT = 109U, /**< IOMUXC select input index */
kIOMUXC_QTIMER2_TMR2_INPUT_SELECT_INPUT = 110U, /**< IOMUXC select input index */
kIOMUXC_QTIMER3_TMR0_INPUT_SELECT_INPUT = 111U, /**< IOMUXC select input index */
kIOMUXC_QTIMER3_TMR1_INPUT_SELECT_INPUT = 112U, /**< IOMUXC select input index */
kIOMUXC_QTIMER3_TMR2_INPUT_SELECT_INPUT = 113U, /**< IOMUXC select input index */
kIOMUXC_QTIMER4_TMR0_INPUT_SELECT_INPUT = 114U, /**< IOMUXC select input index */
kIOMUXC_QTIMER4_TMR1_INPUT_SELECT_INPUT = 115U, /**< IOMUXC select input index */
kIOMUXC_QTIMER4_TMR2_INPUT_SELECT_INPUT = 116U, /**< IOMUXC select input index */
kIOMUXC_SAI1_IPG_CLK_SAI_MCLK_SELECT_INPUT = 117U, /**< IOMUXC select input index */
kIOMUXC_SAI1_SAI_RXBCLK_SELECT_INPUT = 118U, /**< IOMUXC select input index */
kIOMUXC_SAI1_SAI_RXDATA_SELECT_INPUT_0 = 119U, /**< IOMUXC select input index */
kIOMUXC_SAI1_SAI_RXSYNC_SELECT_INPUT = 120U, /**< IOMUXC select input index */
kIOMUXC_SAI1_SAI_TXBCLK_SELECT_INPUT = 121U, /**< IOMUXC select input index */
kIOMUXC_SAI1_SAI_TXSYNC_SELECT_INPUT = 122U, /**< IOMUXC select input index */
kIOMUXC_EMVSIM1_SIO_SELECT_INPUT = 129U, /**< IOMUXC select input index */
kIOMUXC_EMVSIM1_IPP_SIMPD_SELECT_INPUT = 130U, /**< IOMUXC select input index */
kIOMUXC_EMVSIM1_POWER_FAIL_SELECT_INPUT = 131U, /**< IOMUXC select input index */
kIOMUXC_EMVSIM2_SIO_SELECT_INPUT = 132U, /**< IOMUXC select input index */
kIOMUXC_EMVSIM2_IPP_SIMPD_SELECT_INPUT = 133U, /**< IOMUXC select input index */
kIOMUXC_EMVSIM2_POWER_FAIL_SELECT_INPUT = 134U, /**< IOMUXC select input index */
kIOMUXC_SPDIF_SPDIF_IN1_SELECT_INPUT = 135U, /**< IOMUXC select input index */
kIOMUXC_USB_OTG2_OC_SELECT_INPUT = 136U, /**< IOMUXC select input index */
kIOMUXC_USB_OTG_OC_SELECT_INPUT = 137U, /**< IOMUXC select input index */
kIOMUXC_USBPHY1_USB_ID_SELECT_INPUT = 138U, /**< IOMUXC select input index */
kIOMUXC_USBPHY2_USB_ID_SELECT_INPUT = 139U, /**< IOMUXC select input index */
kIOMUXC_USDHC1_IPP_CARD_DET_SELECT_INPUT = 140U, /**< IOMUXC select input index */
kIOMUXC_USDHC1_IPP_WP_ON_SELECT_INPUT = 141U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_IPP_CARD_DET_SELECT_INPUT = 142U, /**< IOMUXC select input index */
kIOMUXC_USDHC2_IPP_WP_ON_SELECT_INPUT = 143U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_20 = 144U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_21 = 145U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_22 = 146U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_23 = 147U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_24 = 148U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_25 = 149U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_26 = 150U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_27 = 151U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_28 = 152U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_29 = 153U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_30 = 154U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_31 = 155U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_32 = 156U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_33 = 157U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_34 = 158U, /**< IOMUXC select input index */
kIOMUXC_XBAR1_IN_SELECT_INPUT_35 = 159U, /**< IOMUXC select input index */
} iomuxc_select_input_t;
/*!
* @}
*/ /* end of group Mapping_Information */
/* ----------------------------------------------------------------------------
-- Device Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup Peripheral_access_layer Device Peripheral Access Layer
* @{
*/
/*
** Start of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic push
#else
#pragma push
#pragma anon_unions
#endif
#elif defined(__CWCC__)
#pragma push
#pragma cpp_extensions on
#elif defined(__GNUC__)
/* anonymous unions are enabled by default */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=extended
#else
#error Not supported compiler type
#endif
/* ----------------------------------------------------------------------------
-- ADC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
* @{
*/
/** ADC - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t CTRL; /**< LPADC Control Register, offset: 0x10 */
__IO uint32_t STAT; /**< LPADC Status Register, offset: 0x14 */
__IO uint32_t IE; /**< Interrupt Enable Register, offset: 0x18 */
__IO uint32_t DE; /**< DMA Enable Register, offset: 0x1C */
__IO uint32_t CFG; /**< LPADC Configuration Register, offset: 0x20 */
__IO uint32_t PAUSE; /**< LPADC Pause Register, offset: 0x24 */
uint8_t RESERVED_1[8];
__IO uint32_t FCTRL; /**< LPADC FIFO Control Register, offset: 0x30 */
__O uint32_t SWTRIG; /**< Software Trigger Register, offset: 0x34 */
uint8_t RESERVED_2[136];
__IO uint32_t TCTRL[8]; /**< Trigger Control Register, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_3[32];
struct { /* offset: 0x100, array step: 0x8 */
__IO uint32_t CMDL; /**< LPADC Command Low Buffer Register, array offset: 0x100, array step: 0x8 */
__IO uint32_t CMDH; /**< LPADC Command High Buffer Register, array offset: 0x104, array step: 0x8 */
} CMD[15];
uint8_t RESERVED_4[136];
__IO uint32_t CV[4]; /**< Compare Value Register, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_5[240];
__I uint32_t RESFIFO; /**< LPADC Data Result FIFO Register, offset: 0x300 */
} ADC_Type;
/* ----------------------------------------------------------------------------
-- ADC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_Register_Masks ADC Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
/*! @{ */
#define ADC_VERID_RES_MASK (0x1U)
#define ADC_VERID_RES_SHIFT (0U)
/*! RES - Resolution
* 0b0..Up to 13-bit differential/12-bit single ended resolution supported.
* 0b1..Up to 16-bit differential/15-bit single ended resolution supported.
*/
#define ADC_VERID_RES(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_RES_SHIFT)) & ADC_VERID_RES_MASK)
#define ADC_VERID_DIFFEN_MASK (0x2U)
#define ADC_VERID_DIFFEN_SHIFT (1U)
/*! DIFFEN - Differential Supported
* 0b0..Differential operation not supported.
* 0b1..Differential operation supported. CMDLa[DIFF] and CMDLa[ABSEL] control fields implemented.
*/
#define ADC_VERID_DIFFEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_DIFFEN_SHIFT)) & ADC_VERID_DIFFEN_MASK)
#define ADC_VERID_MVI_MASK (0x8U)
#define ADC_VERID_MVI_SHIFT (3U)
/*! MVI - Multi Vref Implemented
* 0b0..Single voltage reference input supported.
* 0b1..Multiple voltage reference inputs supported.
*/
#define ADC_VERID_MVI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MVI_SHIFT)) & ADC_VERID_MVI_MASK)
#define ADC_VERID_CSW_MASK (0x70U)
#define ADC_VERID_CSW_SHIFT (4U)
/*! CSW - Channel Scale Width
* 0b000..Channel scaling not supported.
* 0b001..Channel scaling supported. 1-bit CSCALE control field.
* 0b110..Channel scaling supported. 6-bit CSCALE control field.
*/
#define ADC_VERID_CSW(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CSW_SHIFT)) & ADC_VERID_CSW_MASK)
#define ADC_VERID_VR1RNGI_MASK (0x100U)
#define ADC_VERID_VR1RNGI_SHIFT (8U)
/*! VR1RNGI - Voltage Reference 1 Range Control Bit Implemented
* 0b0..Range control not required. CFG[VREF1RNG] is not implemented.
* 0b1..Range control required. CFG[VREF1RNG] is implemented.
*/
#define ADC_VERID_VR1RNGI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_VR1RNGI_SHIFT)) & ADC_VERID_VR1RNGI_MASK)
#define ADC_VERID_IADCKI_MASK (0x200U)
#define ADC_VERID_IADCKI_SHIFT (9U)
/*! IADCKI - Internal LPADC Clock implemented
* 0b0..Internal clock source not implemented.
* 0b1..Internal clock source (and CFG[ADCKEN]) implemented.
*/
#define ADC_VERID_IADCKI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_IADCKI_SHIFT)) & ADC_VERID_IADCKI_MASK)
#define ADC_VERID_CALOFSI_MASK (0x400U)
#define ADC_VERID_CALOFSI_SHIFT (10U)
/*! CALOFSI - Calibration Offset Function Implemented
* 0b0..Offset calibration and offset trimming not implemented.
* 0b1..Offset calibration and offset trimming implemented.
*/
#define ADC_VERID_CALOFSI(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_CALOFSI_SHIFT)) & ADC_VERID_CALOFSI_MASK)
#define ADC_VERID_MINOR_MASK (0xFF0000U)
#define ADC_VERID_MINOR_SHIFT (16U)
/*! MINOR - Minor Version Number
*/
#define ADC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MINOR_SHIFT)) & ADC_VERID_MINOR_MASK)
#define ADC_VERID_MAJOR_MASK (0xFF000000U)
#define ADC_VERID_MAJOR_SHIFT (24U)
/*! MAJOR - Major Version Number
*/
#define ADC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << ADC_VERID_MAJOR_SHIFT)) & ADC_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define ADC_PARAM_TRIG_NUM_MASK (0xFFU)
#define ADC_PARAM_TRIG_NUM_SHIFT (0U)
/*! TRIG_NUM - Trigger Number
* 0b00001000..8 hardware triggers implemented
*/
#define ADC_PARAM_TRIG_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_TRIG_NUM_SHIFT)) & ADC_PARAM_TRIG_NUM_MASK)
#define ADC_PARAM_FIFOSIZE_MASK (0xFF00U)
#define ADC_PARAM_FIFOSIZE_SHIFT (8U)
/*! FIFOSIZE - Result FIFO Depth
* 0b00010000..Result FIFO depth = 16 datawords.
*/
#define ADC_PARAM_FIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_FIFOSIZE_SHIFT)) & ADC_PARAM_FIFOSIZE_MASK)
#define ADC_PARAM_CV_NUM_MASK (0xFF0000U)
#define ADC_PARAM_CV_NUM_SHIFT (16U)
/*! CV_NUM - Compare Value Number
* 0b00000100..4 compare value registers implemented
*/
#define ADC_PARAM_CV_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CV_NUM_SHIFT)) & ADC_PARAM_CV_NUM_MASK)
#define ADC_PARAM_CMD_NUM_MASK (0xFF000000U)
#define ADC_PARAM_CMD_NUM_SHIFT (24U)
/*! CMD_NUM - Command Buffer Number
* 0b00001111..15 command buffers implemented
*/
#define ADC_PARAM_CMD_NUM(x) (((uint32_t)(((uint32_t)(x)) << ADC_PARAM_CMD_NUM_SHIFT)) & ADC_PARAM_CMD_NUM_MASK)
/*! @} */
/*! @name CTRL - LPADC Control Register */
/*! @{ */
#define ADC_CTRL_ADCEN_MASK (0x1U)
#define ADC_CTRL_ADCEN_SHIFT (0U)
/*! ADCEN - LPADC Enable
* 0b0..LPADC is disabled.
* 0b1..LPADC is enabled.
*/
#define ADC_CTRL_ADCEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ADCEN_SHIFT)) & ADC_CTRL_ADCEN_MASK)
#define ADC_CTRL_RST_MASK (0x2U)
#define ADC_CTRL_RST_SHIFT (1U)
/*! RST - Software Reset
* 0b0..LPADC logic is not reset.
* 0b1..LPADC logic is reset.
*/
#define ADC_CTRL_RST(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RST_SHIFT)) & ADC_CTRL_RST_MASK)
#define ADC_CTRL_DOZEN_MASK (0x4U)
#define ADC_CTRL_DOZEN_SHIFT (2U)
/*! DOZEN - Doze Enable
* 0b0..LPADC is enabled in Doze mode.
* 0b1..LPADC is disabled in Doze mode.
*/
#define ADC_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_DOZEN_SHIFT)) & ADC_CTRL_DOZEN_MASK)
#define ADC_CTRL_TRIG_SRC_MASK (0x18U)
#define ADC_CTRL_TRIG_SRC_SHIFT (3U)
/*! TRIG_SRC - Hardware trigger source selection
* 0b00..ADC_ETC hw trigger , and HW trigger are enabled
* 0b01..ADC_ETC hw trigger is enabled
* 0b10..HW trigger is enabled
* 0b11..Reserved
*/
#define ADC_CTRL_TRIG_SRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TRIG_SRC_SHIFT)) & ADC_CTRL_TRIG_SRC_MASK)
#define ADC_CTRL_RSTFIFO_MASK (0x100U)
#define ADC_CTRL_RSTFIFO_SHIFT (8U)
/*! RSTFIFO - Reset FIFO
* 0b0..No effect.
* 0b1..FIFO is reset.
*/
#define ADC_CTRL_RSTFIFO(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RSTFIFO_SHIFT)) & ADC_CTRL_RSTFIFO_MASK)
/*! @} */
/*! @name STAT - LPADC Status Register */
/*! @{ */
#define ADC_STAT_RDY_MASK (0x1U)
#define ADC_STAT_RDY_SHIFT (0U)
/*! RDY - Result FIFO Ready Flag
* 0b0..Result FIFO data level not above watermark level.
* 0b1..Result FIFO holding data above watermark level.
*/
#define ADC_STAT_RDY(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_RDY_SHIFT)) & ADC_STAT_RDY_MASK)
#define ADC_STAT_FOF_MASK (0x2U)
#define ADC_STAT_FOF_SHIFT (1U)
/*! FOF - Result FIFO Overflow Flag
* 0b0..No result FIFO overflow has occurred since the last time the flag was cleared.
* 0b1..At least one result FIFO overflow has occurred since the last time the flag was cleared.
*/
#define ADC_STAT_FOF(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_FOF_SHIFT)) & ADC_STAT_FOF_MASK)
#define ADC_STAT_ADC_ACTIVE_MASK (0x100U)
#define ADC_STAT_ADC_ACTIVE_SHIFT (8U)
/*! ADC_ACTIVE - ADC Active
* 0b0..The LPADC is IDLE. There are no pending triggers to service and no active commands are being processed.
* 0b1..The LPADC is processing a conversion, running through the power up delay, or servicing a trigger.
*/
#define ADC_STAT_ADC_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_ADC_ACTIVE_SHIFT)) & ADC_STAT_ADC_ACTIVE_MASK)
#define ADC_STAT_TRGACT_MASK (0x70000U)
#define ADC_STAT_TRGACT_SHIFT (16U)
/*! TRGACT - Trigger Active
* 0b000..Command (sequence) associated with Trigger 0 currently being executed.
* 0b001..Command (sequence) associated with Trigger 1 currently being executed.
* 0b010..Command (sequence) associated with Trigger 2 currently being executed.
* 0b011-0b111..Command (sequence) from the associated Trigger number is currently being executed.
*/
#define ADC_STAT_TRGACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_TRGACT_SHIFT)) & ADC_STAT_TRGACT_MASK)
#define ADC_STAT_CMDACT_MASK (0xF000000U)
#define ADC_STAT_CMDACT_SHIFT (24U)
/*! CMDACT - Command Active
* 0b0000..No command is currently in progress.
* 0b0001..Command 1 currently being executed.
* 0b0010..Command 2 currently being executed.
* 0b0011-0b1111..Associated command number is currently being executed.
*/
#define ADC_STAT_CMDACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STAT_CMDACT_SHIFT)) & ADC_STAT_CMDACT_MASK)
/*! @} */
/*! @name IE - Interrupt Enable Register */
/*! @{ */
#define ADC_IE_FWMIE_MASK (0x1U)
#define ADC_IE_FWMIE_SHIFT (0U)
/*! FWMIE - FIFO Watermark Interrupt Enable
* 0b0..FIFO watermark interrupts are not enabled.
* 0b1..FIFO watermark interrupts are enabled.
*/
#define ADC_IE_FWMIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FWMIE_SHIFT)) & ADC_IE_FWMIE_MASK)
#define ADC_IE_FOFIE_MASK (0x2U)
#define ADC_IE_FOFIE_SHIFT (1U)
/*! FOFIE - Result FIFO Overflow Interrupt Enable
* 0b0..FIFO overflow interrupts are not enabled.
* 0b1..FIFO overflow interrupts are enabled.
*/
#define ADC_IE_FOFIE(x) (((uint32_t)(((uint32_t)(x)) << ADC_IE_FOFIE_SHIFT)) & ADC_IE_FOFIE_MASK)
/*! @} */
/*! @name DE - DMA Enable Register */
/*! @{ */
#define ADC_DE_FWMDE_MASK (0x1U)
#define ADC_DE_FWMDE_SHIFT (0U)
/*! FWMDE - FIFO Watermark DMA Enable
* 0b0..DMA request disabled.
* 0b1..DMA request enabled.
*/
#define ADC_DE_FWMDE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DE_FWMDE_SHIFT)) & ADC_DE_FWMDE_MASK)
/*! @} */
/*! @name CFG - LPADC Configuration Register */
/*! @{ */
#define ADC_CFG_TPRICTRL_MASK (0x1U)
#define ADC_CFG_TPRICTRL_SHIFT (0U)
/*! TPRICTRL - LPADC trigger priority control
* 0b0..If a higher priority trigger is detected during command processing, the current conversion is aborted and
* the new command specified by the trigger is started.
* 0b1..If a higher priority trigger is received during command processing, the current conversion is completed
* (including averaging iterations if enabled) and stored to the RESFIFO before the higher priority
* trigger/command is initiated. Note that compare until true commands can be interrupted prior to resulting in a true
* conversion.
*/
#define ADC_CFG_TPRICTRL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_TPRICTRL_SHIFT)) & ADC_CFG_TPRICTRL_MASK)
#define ADC_CFG_PWRSEL_MASK (0x30U)
#define ADC_CFG_PWRSEL_SHIFT (4U)
/*! PWRSEL - Power Configuration Select
* 0b00..Level 1 (Lowest power setting)
* 0b01..Level 2
* 0b10..Level 3
* 0b11..Level 4 (Highest power setting)
*/
#define ADC_CFG_PWRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWRSEL_SHIFT)) & ADC_CFG_PWRSEL_MASK)
#define ADC_CFG_REFSEL_MASK (0xC0U)
#define ADC_CFG_REFSEL_SHIFT (6U)
/*! REFSEL - Voltage Reference Selection
* 0b00..(Default) Option 1 setting.
* 0b01..Option 2 setting.
* 0b10..Option 3 setting.
* 0b11..Reserved
*/
#define ADC_CFG_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_REFSEL_SHIFT)) & ADC_CFG_REFSEL_MASK)
#define ADC_CFG_PUDLY_MASK (0xFF0000U)
#define ADC_CFG_PUDLY_SHIFT (16U)
/*! PUDLY - Power Up Delay
*/
#define ADC_CFG_PUDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PUDLY_SHIFT)) & ADC_CFG_PUDLY_MASK)
#define ADC_CFG_PWREN_MASK (0x10000000U)
#define ADC_CFG_PWREN_SHIFT (28U)
/*! PWREN - LPADC Analog Pre-Enable
* 0b0..LPADC analog circuits are only enabled while conversions are active. Performance is affected due to analog startup delays.
* 0b1..LPADC analog circuits are pre-enabled and ready to execute conversions without startup delays (at the
* cost of higher DC current consumption). When PWREN is set, the power up delay is enforced such that any
* detected trigger does not begin ADC operation until the power up delay time has passed.
*/
#define ADC_CFG_PWREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG_PWREN_SHIFT)) & ADC_CFG_PWREN_MASK)
/*! @} */
/*! @name PAUSE - LPADC Pause Register */
/*! @{ */
#define ADC_PAUSE_PAUSEDLY_MASK (0x1FFU)
#define ADC_PAUSE_PAUSEDLY_SHIFT (0U)
/*! PAUSEDLY - Pause Delay
*/
#define ADC_PAUSE_PAUSEDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEDLY_SHIFT)) & ADC_PAUSE_PAUSEDLY_MASK)
#define ADC_PAUSE_PAUSEEN_MASK (0x80000000U)
#define ADC_PAUSE_PAUSEEN_SHIFT (31U)
/*! PAUSEEN - PAUSE Option Enable
* 0b0..Pause operation disabled
* 0b1..Pause operation enabled
*/
#define ADC_PAUSE_PAUSEEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_PAUSE_PAUSEEN_SHIFT)) & ADC_PAUSE_PAUSEEN_MASK)
/*! @} */
/*! @name FCTRL - LPADC FIFO Control Register */
/*! @{ */
#define ADC_FCTRL_FCOUNT_MASK (0x1FU)
#define ADC_FCTRL_FCOUNT_SHIFT (0U)
/*! FCOUNT - Result FIFO counter
* 0b00000..No data stored in FIFO
* 0b00001..1 dataword stored in FIFO
* 0b00010..2 datawords stored in FIFO
* 0b00100..4 datawords stored in FIFO
* 0b01000..8 datawords stored in FIFO
* 0b10000..16 datawords stored in FIFO
*/
#define ADC_FCTRL_FCOUNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FCOUNT_SHIFT)) & ADC_FCTRL_FCOUNT_MASK)
#define ADC_FCTRL_FWMARK_MASK (0xF0000U)
#define ADC_FCTRL_FWMARK_SHIFT (16U)
/*! FWMARK - Watermark level selection
* 0b0000..Generates STAT[RDY] flag after 1st successful conversion - single conversion
* 0b0001..Generates STAT[RDY] flag after 2nd successful conversion
* 0b0010..Generates STAT[RDY] flag after 3rd successful conversion
* 0b0011..Generates STAT[RDY] flag after 4th successful conversion
* 0b0100..Generates STAT[RDY] flag after 5th successful conversion
* 0b0101..Generates STAT[RDY] flag after 6th successful conversion
* 0b0110..Generates STAT[RDY] flag after 7th successful conversion
* 0b0111..Generates STAT[RDY] flag after 8th successful conversion
* 0b1000..Generates STAT[RDY] flag after 9th successful conversion
* 0b1001..Generates STAT[RDY] flag after 10th successful conversion
* 0b1010..Generates STAT[RDY] flag after 11th successful conversion
* 0b1011..Generates STAT[RDY] flag after 12th successful conversion
* 0b1100..Generates STAT[RDY] flag after 13th successful conversion
* 0b1101..Generates STAT[RDY] flag after 14th successful conversion
* 0b1110..Generates STAT[RDY] flag after 15th successful conversion
* 0b1111..Generates STAT[RDY] flag after 16th successful conversion
*/
#define ADC_FCTRL_FWMARK(x) (((uint32_t)(((uint32_t)(x)) << ADC_FCTRL_FWMARK_SHIFT)) & ADC_FCTRL_FWMARK_MASK)
/*! @} */
/*! @name SWTRIG - Software Trigger Register */
/*! @{ */
#define ADC_SWTRIG_SWT0_MASK (0x1U)
#define ADC_SWTRIG_SWT0_SHIFT (0U)
/*! SWT0 - Software trigger 0 event
* 0b0..No trigger 0 event generated.
* 0b1..Trigger 0 event generated.
*/
#define ADC_SWTRIG_SWT0(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT0_SHIFT)) & ADC_SWTRIG_SWT0_MASK)
#define ADC_SWTRIG_SWT1_MASK (0x2U)
#define ADC_SWTRIG_SWT1_SHIFT (1U)
/*! SWT1 - Software trigger 1 event
* 0b0..No trigger 1 event generated.
* 0b1..Trigger 1 event generated.
*/
#define ADC_SWTRIG_SWT1(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT1_SHIFT)) & ADC_SWTRIG_SWT1_MASK)
#define ADC_SWTRIG_SWT2_MASK (0x4U)
#define ADC_SWTRIG_SWT2_SHIFT (2U)
/*! SWT2 - Software trigger 2 event
* 0b0..No trigger 2 event generated.
* 0b1..Trigger 2 event generated.
*/
#define ADC_SWTRIG_SWT2(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT2_SHIFT)) & ADC_SWTRIG_SWT2_MASK)
#define ADC_SWTRIG_SWT3_MASK (0x8U)
#define ADC_SWTRIG_SWT3_SHIFT (3U)
/*! SWT3 - Software trigger 3 event
* 0b0..No trigger 3 event generated.
* 0b1..Trigger 3 event generated.
*/
#define ADC_SWTRIG_SWT3(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT3_SHIFT)) & ADC_SWTRIG_SWT3_MASK)
#define ADC_SWTRIG_SWT4_MASK (0x10U)
#define ADC_SWTRIG_SWT4_SHIFT (4U)
/*! SWT4 - Software trigger 4 event
* 0b0..No trigger 4 event generated.
* 0b1..Trigger 4 event generated.
*/
#define ADC_SWTRIG_SWT4(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT4_SHIFT)) & ADC_SWTRIG_SWT4_MASK)
#define ADC_SWTRIG_SWT5_MASK (0x20U)
#define ADC_SWTRIG_SWT5_SHIFT (5U)
/*! SWT5 - Software trigger 5 event
* 0b0..No trigger 5 event generated.
* 0b1..Trigger 5 event generated.
*/
#define ADC_SWTRIG_SWT5(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT5_SHIFT)) & ADC_SWTRIG_SWT5_MASK)
#define ADC_SWTRIG_SWT6_MASK (0x40U)
#define ADC_SWTRIG_SWT6_SHIFT (6U)
/*! SWT6 - Software trigger 6 event
* 0b0..No trigger 6 event generated.
* 0b1..Trigger 6 event generated.
*/
#define ADC_SWTRIG_SWT6(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT6_SHIFT)) & ADC_SWTRIG_SWT6_MASK)
#define ADC_SWTRIG_SWT7_MASK (0x80U)
#define ADC_SWTRIG_SWT7_SHIFT (7U)
/*! SWT7 - Software trigger 7 event
* 0b0..No trigger 7 event generated.
* 0b1..Trigger 7 event generated.
*/
#define ADC_SWTRIG_SWT7(x) (((uint32_t)(((uint32_t)(x)) << ADC_SWTRIG_SWT7_SHIFT)) & ADC_SWTRIG_SWT7_MASK)
/*! @} */
/*! @name TCTRL - Trigger Control Register */
/*! @{ */
#define ADC_TCTRL_HTEN_MASK (0x1U)
#define ADC_TCTRL_HTEN_SHIFT (0U)
/*! HTEN - Trigger enable
* 0b0..Hardware trigger source disabled
* 0b1..Hardware trigger source enabled
*/
#define ADC_TCTRL_HTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_HTEN_SHIFT)) & ADC_TCTRL_HTEN_MASK)
#define ADC_TCTRL_CMD_SEL_MASK (0x2U)
#define ADC_TCTRL_CMD_SEL_SHIFT (1U)
/*! CMD_SEL
* 0b0..TCTRLa[TCMD] will determine the command
* 0b1..Software TCDM is bypassed , and hardware TCMD from ADC_ETC module will be used. The trigger command is
* then defined by ADC hardware trigger command selection field in ADC_ETC->TRIGx_CHAINy_z_n[CSEL].
*/
#define ADC_TCTRL_CMD_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_CMD_SEL_SHIFT)) & ADC_TCTRL_CMD_SEL_MASK)
#define ADC_TCTRL_TPRI_MASK (0x700U)
#define ADC_TCTRL_TPRI_SHIFT (8U)
/*! TPRI - Trigger priority setting
* 0b000..Set to highest priority, Level 1
* 0b001-0b110..Set to corresponding priority level
* 0b111..Set to lowest priority, Level 8
*/
#define ADC_TCTRL_TPRI(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TPRI_SHIFT)) & ADC_TCTRL_TPRI_MASK)
#define ADC_TCTRL_TDLY_MASK (0xF0000U)
#define ADC_TCTRL_TDLY_SHIFT (16U)
/*! TDLY - Trigger delay select
*/
#define ADC_TCTRL_TDLY(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TDLY_SHIFT)) & ADC_TCTRL_TDLY_MASK)
#define ADC_TCTRL_TCMD_MASK (0xF000000U)
#define ADC_TCTRL_TCMD_SHIFT (24U)
/*! TCMD - Trigger command select
* 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
* 0b0001..CMD1 is executed
* 0b0010-0b1110..Corresponding CMD is executed
* 0b1111..CMD15 is executed
*/
#define ADC_TCTRL_TCMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_TCTRL_TCMD_SHIFT)) & ADC_TCTRL_TCMD_MASK)
/*! @} */
/* The count of ADC_TCTRL */
#define ADC_TCTRL_COUNT (8U)
/*! @name CMDL - LPADC Command Low Buffer Register */
/*! @{ */
#define ADC_CMDL_ADCH_MASK (0x1FU)
#define ADC_CMDL_ADCH_SHIFT (0U)
/*! ADCH - Input channel select
* 0b00000..Select CH0A or CH0B or CH0A/CH0B pair.
* 0b00001..Select CH1A or CH1B or CH1A/CH1B pair.
* 0b00010..Select CH2A or CH2B or CH2A/CH2B pair.
* 0b00011..Select CH3A or CH3B or CH3A/CH3B pair.
* 0b00100-0b11101..Select corresponding channel CHnA or CHnB or CHnA/CHnB pair.
* 0b11110..Select CH30A or CH30B or CH30A/CH30B pair.
* 0b11111..Select CH31A or CH31B or CH31A/CH31B pair.
*/
#define ADC_CMDL_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ADCH_SHIFT)) & ADC_CMDL_ADCH_MASK)
#define ADC_CMDL_ABSEL_MASK (0x20U)
#define ADC_CMDL_ABSEL_SHIFT (5U)
/*! ABSEL - A-side vs. B-side Select
* 0b0..When DIFF=0b0, the associated A-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnA-CHnB).
* 0b1..When DIFF=0b0, the associated B-side channel is converted as single-ended. When DIFF=0b1, the ADC result is (CHnB-CHnA).
*/
#define ADC_CMDL_ABSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_ABSEL_SHIFT)) & ADC_CMDL_ABSEL_MASK)
#define ADC_CMDL_DIFF_MASK (0x40U)
#define ADC_CMDL_DIFF_SHIFT (6U)
/*! DIFF - Differential Mode Enable
* 0b0..Single-ended mode.
* 0b1..Differential mode.
*/
#define ADC_CMDL_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_DIFF_SHIFT)) & ADC_CMDL_DIFF_MASK)
#define ADC_CMDL_CSCALE_MASK (0x2000U)
#define ADC_CMDL_CSCALE_SHIFT (13U)
/*! CSCALE - Channel Scale
* 0b0..Scale selected analog channel (Factor of 30/64)
* 0b1..(Default) Full scale (Factor of 1)
*/
#define ADC_CMDL_CSCALE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDL_CSCALE_SHIFT)) & ADC_CMDL_CSCALE_MASK)
/*! @} */
/* The count of ADC_CMDL */
#define ADC_CMDL_COUNT (15U)
/*! @name CMDH - LPADC Command High Buffer Register */
/*! @{ */
#define ADC_CMDH_CMPEN_MASK (0x3U)
#define ADC_CMDH_CMPEN_SHIFT (0U)
/*! CMPEN - Compare Function Enable
* 0b00..Compare disabled.
* 0b01..Reserved
* 0b10..Compare enabled. Store on true.
* 0b11..Compare enabled. Repeat channel acquisition (sample/convert/compare) until true.
*/
#define ADC_CMDH_CMPEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_CMPEN_SHIFT)) & ADC_CMDH_CMPEN_MASK)
#define ADC_CMDH_LWI_MASK (0x80U)
#define ADC_CMDH_LWI_SHIFT (7U)
/*! LWI - Loop with Increment
* 0b0..Auto channel increment disabled
* 0b1..Auto channel increment enabled
*/
#define ADC_CMDH_LWI(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LWI_SHIFT)) & ADC_CMDH_LWI_MASK)
#define ADC_CMDH_STS_MASK (0x700U)
#define ADC_CMDH_STS_SHIFT (8U)
/*! STS - Sample Time Select
* 0b000..Minimum sample time of 3 ADCK cycles.
* 0b001..3 + 21 ADCK cycles; 5 ADCK cycles total sample time.
* 0b010..3 + 22 ADCK cycles; 7 ADCK cycles total sample time.
* 0b011..3 + 23 ADCK cycles; 11 ADCK cycles total sample time.
* 0b100..3 + 24 ADCK cycles; 19 ADCK cycles total sample time.
* 0b101..3 + 25 ADCK cycles; 35 ADCK cycles total sample time.
* 0b110..3 + 26 ADCK cycles; 67 ADCK cycles total sample time.
* 0b111..3 + 27 ADCK cycles; 131 ADCK cycles total sample time.
*/
#define ADC_CMDH_STS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_STS_SHIFT)) & ADC_CMDH_STS_MASK)
#define ADC_CMDH_AVGS_MASK (0x7000U)
#define ADC_CMDH_AVGS_SHIFT (12U)
/*! AVGS - Hardware Average Select
* 0b000..Single conversion.
* 0b001..2 conversions averaged.
* 0b010..4 conversions averaged.
* 0b011..8 conversions averaged.
* 0b100..16 conversions averaged.
* 0b101..32 conversions averaged.
* 0b110..64 conversions averaged.
* 0b111..128 conversions averaged.
*/
#define ADC_CMDH_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_AVGS_SHIFT)) & ADC_CMDH_AVGS_MASK)
#define ADC_CMDH_LOOP_MASK (0xF0000U)
#define ADC_CMDH_LOOP_SHIFT (16U)
/*! LOOP - Loop Count Select
* 0b0000..Looping not enabled. Command executes 1 time.
* 0b0001..Loop 1 time. Command executes 2 times.
* 0b0010..Loop 2 times. Command executes 3 times.
* 0b0011-0b1110..Loop corresponding number of times. Command executes LOOP+1 times.
* 0b1111..Loop 15 times. Command executes 16 times.
*/
#define ADC_CMDH_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_LOOP_SHIFT)) & ADC_CMDH_LOOP_MASK)
#define ADC_CMDH_NEXT_MASK (0xF000000U)
#define ADC_CMDH_NEXT_SHIFT (24U)
/*! NEXT - Next Command Select
* 0b0000..No next command defined. Terminate conversions at completion of current command. If lower priority
* trigger pending, begin command associated with lower priority trigger.
* 0b0001..Select CMD1 command buffer register as next command.
* 0b0010-0b1110..Select corresponding CMD command buffer register as next command
* 0b1111..Select CMD15 command buffer register as next command.
*/
#define ADC_CMDH_NEXT(x) (((uint32_t)(((uint32_t)(x)) << ADC_CMDH_NEXT_SHIFT)) & ADC_CMDH_NEXT_MASK)
/*! @} */
/* The count of ADC_CMDH */
#define ADC_CMDH_COUNT (15U)
/*! @name CV - Compare Value Register */
/*! @{ */
#define ADC_CV_CVL_MASK (0xFFFFU)
#define ADC_CV_CVL_SHIFT (0U)
/*! CVL - Compare Value Low
*/
#define ADC_CV_CVL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVL_SHIFT)) & ADC_CV_CVL_MASK)
#define ADC_CV_CVH_MASK (0xFFFF0000U)
#define ADC_CV_CVH_SHIFT (16U)
/*! CVH - Compare Value High.
*/
#define ADC_CV_CVH(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV_CVH_SHIFT)) & ADC_CV_CVH_MASK)
/*! @} */
/* The count of ADC_CV */
#define ADC_CV_COUNT (4U)
/*! @name RESFIFO - LPADC Data Result FIFO Register */
/*! @{ */
#define ADC_RESFIFO_D_MASK (0xFFFFU)
#define ADC_RESFIFO_D_SHIFT (0U)
/*! D - Data result
*/
#define ADC_RESFIFO_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_D_SHIFT)) & ADC_RESFIFO_D_MASK)
#define ADC_RESFIFO_TSRC_MASK (0x70000U)
#define ADC_RESFIFO_TSRC_SHIFT (16U)
/*! TSRC - Trigger Source
* 0b000..Trigger source 0 initiated this conversion.
* 0b001..Trigger source 1 initiated this conversion.
* 0b010-0b110..Corresponding trigger source initiated this conversion.
* 0b111..Trigger source 7 initiated this conversion.
*/
#define ADC_RESFIFO_TSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_TSRC_SHIFT)) & ADC_RESFIFO_TSRC_MASK)
#define ADC_RESFIFO_LOOPCNT_MASK (0xF00000U)
#define ADC_RESFIFO_LOOPCNT_SHIFT (20U)
/*! LOOPCNT - Loop count value
* 0b0000..Result is from initial conversion in command.
* 0b0001..Result is from second conversion in command.
* 0b0010-0b1110..Result is from LOOPCNT+1 conversion in command.
* 0b1111..Result is from 16th conversion in command.
*/
#define ADC_RESFIFO_LOOPCNT(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_LOOPCNT_SHIFT)) & ADC_RESFIFO_LOOPCNT_MASK)
#define ADC_RESFIFO_CMDSRC_MASK (0xF000000U)
#define ADC_RESFIFO_CMDSRC_SHIFT (24U)
/*! CMDSRC - Command Buffer Source
* 0b0000..Not a valid value CMDSRC value for a dataword in RESFIFO. 0x0 is only found in initial FIFO state
* prior to an ADC conversion result dataword being stored to a RESFIFO buffer.
* 0b0001..CMD1 buffer used as control settings for this conversion.
* 0b0010-0b1110..Corresponding command buffer used as control settings for this conversion.
* 0b1111..CMD15 buffer used as control settings for this conversion.
*/
#define ADC_RESFIFO_CMDSRC(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_CMDSRC_SHIFT)) & ADC_RESFIFO_CMDSRC_MASK)
#define ADC_RESFIFO_VALID_MASK (0x80000000U)
#define ADC_RESFIFO_VALID_SHIFT (31U)
/*! VALID - FIFO entry is valid
* 0b0..FIFO is empty. Discard any read from RESFIFO.
* 0b1..FIFO record read from RESFIFO is valid.
*/
#define ADC_RESFIFO_VALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_RESFIFO_VALID_SHIFT)) & ADC_RESFIFO_VALID_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ADC_Register_Masks */
/* ADC - Peripheral instance base addresses */
/** Peripheral LPADC1 base address */
#define LPADC1_BASE (0x40050000u)
/** Peripheral LPADC1 base pointer */
#define LPADC1 ((ADC_Type *)LPADC1_BASE)
/** Peripheral LPADC2 base address */
#define LPADC2_BASE (0x40054000u)
/** Peripheral LPADC2 base pointer */
#define LPADC2 ((ADC_Type *)LPADC2_BASE)
/** Array initializer of ADC peripheral base addresses */
#define ADC_BASE_ADDRS { 0u, LPADC1_BASE, LPADC2_BASE }
/** Array initializer of ADC peripheral base pointers */
#define ADC_BASE_PTRS { (ADC_Type *)0u, LPADC1, LPADC2 }
/** Interrupt vectors for the ADC peripheral type */
#define ADC_IRQS { NotAvail_IRQn, ADC1_IRQn, ADC2_IRQn }
/*!
* @}
*/ /* end of group ADC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ADC_ETC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_ETC_Peripheral_Access_Layer ADC_ETC Peripheral Access Layer
* @{
*/
/** ADC_ETC - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< ADC_ETC Global Control Register, offset: 0x0 */
__IO uint32_t DONE0_1_IRQ; /**< ETC DONE0 and DONE1 IRQ State Register, offset: 0x4 */
__IO uint32_t DONE2_3_ERR_IRQ; /**< ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register, offset: 0x8 */
__IO uint32_t DMA_CTRL; /**< ETC DMA control Register, offset: 0xC */
struct { /* offset: 0x10, array step: 0x28 */
__IO uint32_t TRIGn_CTRL; /**< ETC_TRIG Control Register, array offset: 0x10, array step: 0x28 */
__IO uint32_t TRIGn_COUNTER; /**< ETC_TRIG Counter Register, array offset: 0x14, array step: 0x28 */
__IO uint32_t TRIGn_CHAIN_1_0; /**< ETC_TRIG Chain 0/1 Register, array offset: 0x18, array step: 0x28 */
__IO uint32_t TRIGn_CHAIN_3_2; /**< ETC_TRIG Chain 2/3 Register, array offset: 0x1C, array step: 0x28 */
__IO uint32_t TRIGn_CHAIN_5_4; /**< ETC_TRIG Chain 4/5 Register, array offset: 0x20, array step: 0x28 */
__IO uint32_t TRIGn_CHAIN_7_6; /**< ETC_TRIG Chain 6/7 Register, array offset: 0x24, array step: 0x28 */
__I uint32_t TRIGn_RESULT_1_0; /**< ETC_TRIG Result Data 1/0 Register, array offset: 0x28, array step: 0x28 */
__I uint32_t TRIGn_RESULT_3_2; /**< ETC_TRIG Result Data 3/2 Register, array offset: 0x2C, array step: 0x28 */
__I uint32_t TRIGn_RESULT_5_4; /**< ETC_TRIG Result Data 5/4 Register, array offset: 0x30, array step: 0x28 */
__I uint32_t TRIGn_RESULT_7_6; /**< ETC_TRIG Result Data 7/6 Register, array offset: 0x34, array step: 0x28 */
} TRIG[8];
} ADC_ETC_Type;
/* ----------------------------------------------------------------------------
-- ADC_ETC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ADC_ETC_Register_Masks ADC_ETC Register Masks
* @{
*/
/*! @name CTRL - ADC_ETC Global Control Register */
/*! @{ */
#define ADC_ETC_CTRL_TRIG_ENABLE_MASK (0xFFU)
#define ADC_ETC_CTRL_TRIG_ENABLE_SHIFT (0U)
/*! TRIG_ENABLE
* 0b00000000..disable all 8 external XBAR triggers.
* 0b00000001..enable external XBAR trigger0.
* 0b00000010..enable external XBAR trigger1.
* 0b00000011..enable external XBAR trigger0 and trigger1.
* 0b11111111..enable all 8 external XBAR triggers.
*/
#define ADC_ETC_CTRL_TRIG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_TRIG_ENABLE_SHIFT)) & ADC_ETC_CTRL_TRIG_ENABLE_MASK)
#define ADC_ETC_CTRL_PRE_DIVIDER_MASK (0xFF0000U)
#define ADC_ETC_CTRL_PRE_DIVIDER_SHIFT (16U)
#define ADC_ETC_CTRL_PRE_DIVIDER(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_PRE_DIVIDER_SHIFT)) & ADC_ETC_CTRL_PRE_DIVIDER_MASK)
#define ADC_ETC_CTRL_DMA_MODE_SEL_MASK (0x20000000U)
#define ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT (29U)
/*! DMA_MODE_SEL
* 0b0..Trig DMA_REQ with latched signal, REQ will be cleared when ACK and source request cleared.
* 0b1..Trig DMA_REQ with pulsed signal, REQ will be cleared by ACK only.
*/
#define ADC_ETC_CTRL_DMA_MODE_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_DMA_MODE_SEL_SHIFT)) & ADC_ETC_CTRL_DMA_MODE_SEL_MASK)
#define ADC_ETC_CTRL_SOFTRST_MASK (0x80000000U)
#define ADC_ETC_CTRL_SOFTRST_SHIFT (31U)
/*! SOFTRST
* 0b0..ADC_ETC works normally.
* 0b1..All registers inside ADC_ETC will be reset to the default value.
*/
#define ADC_ETC_CTRL_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_CTRL_SOFTRST_SHIFT)) & ADC_ETC_CTRL_SOFTRST_MASK)
/*! @} */
/*! @name DONE0_1_IRQ - ETC DONE0 and DONE1 IRQ State Register */
/*! @{ */
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK (0x1U)
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT (0U)
/*! TRIG0_DONE0
* 0b0..No TRIG0_DONE0 interrupt detected
* 0b1..TRIG0_DONE0 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK (0x2U)
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT (1U)
/*! TRIG1_DONE0
* 0b0..No TRIG1_DONE0 interrupt detected
* 0b1..TRIG1_DONE0 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK (0x4U)
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT (2U)
/*! TRIG2_DONE0
* 0b0..No TRIG2_DONE0 interrupt detected
* 0b1..TRIG2_DONE0 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK (0x8U)
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT (3U)
/*! TRIG3_DONE0
* 0b0..No TRIG3_DONE0 interrupt detected
* 0b1..TRIG3_DONE0 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK (0x10U)
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT (4U)
/*! TRIG4_DONE0
* 0b0..No TRIG4_DONE0 interrupt detected
* 0b1..TRIG4_DONE0 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK (0x20U)
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT (5U)
/*! TRIG5_DONE0
* 0b0..No TRIG5_DONE0 interrupt detected
* 0b1..TRIG5_DONE0 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK (0x40U)
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT (6U)
/*! TRIG6_DONE0
* 0b0..No TRIG6_DONE0 interrupt detected
* 0b1..TRIG6_DONE0 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK (0x80U)
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT (7U)
/*! TRIG7_DONE0
* 0b0..No TRIG7_DONE0 interrupt detected
* 0b1..TRIG7_DONE0 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE0_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK (0x10000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT (16U)
/*! TRIG0_DONE1
* 0b0..No TRIG0_DONE1 interrupt detected
* 0b1..TRIG0_DONE1 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG0_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK (0x20000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT (17U)
/*! TRIG1_DONE1
* 0b0..No TRIG1_DONE1 interrupt detected
* 0b1..TRIG1_DONE1 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG1_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK (0x40000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT (18U)
/*! TRIG2_DONE1
* 0b0..No TRIG2_DONE1 interrupt detected
* 0b1..TRIG2_DONE1 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG2_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK (0x80000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT (19U)
/*! TRIG3_DONE1
* 0b0..No TRIG3_DONE1 interrupt detected
* 0b1..TRIG3_DONE1 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG3_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK (0x100000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT (20U)
/*! TRIG4_DONE1
* 0b0..No TRIG4_DONE1 interrupt detected
* 0b1..TRIG4_DONE1 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG4_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK (0x200000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT (21U)
/*! TRIG5_DONE1
* 0b0..No TRIG5_DONE1 interrupt detected
* 0b1..TRIG5_DONE1 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG5_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK (0x400000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT (22U)
/*! TRIG6_DONE1
* 0b0..No TRIG6_DONE1 interrupt detected
* 0b1..TRIG6_DONE1 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG6_DONE1_MASK)
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK (0x800000U)
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT (23U)
/*! TRIG7_DONE1
* 0b0..No TRIG7_DONE1 interrupt detected
* 0b1..TRIG7_DONE1 interrupt detected
*/
#define ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_SHIFT)) & ADC_ETC_DONE0_1_IRQ_TRIG7_DONE1_MASK)
/*! @} */
/*! @name DONE2_3_ERR_IRQ - ETC DONE_2, DONE_3 and DONE_ERR IRQ State Register */
/*! @{ */
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK (0x1U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT (0U)
/*! TRIG0_DONE2
* 0b0..No TRIG0_DONE2 interrupt detected
* 0b1..TRIG0_DONE2 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE2_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK (0x2U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT (1U)
/*! TRIG1_DONE2
* 0b0..No TRIG1_DONE2 interrupt detected
* 0b1..TRIG1_DONE2 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE2_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK (0x4U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT (2U)
/*! TRIG2_DONE2
* 0b0..No TRIG2_DONE2 interrupt detected
* 0b1..TRIG2_DONE2 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE2_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK (0x8U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT (3U)
/*! TRIG3_DONE2
* 0b0..No TRIG3_DONE2 interrupt detected
* 0b1..TRIG3_DONE2 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE2_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK (0x10U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT (4U)
/*! TRIG4_DONE2
* 0b0..No TRIG4_DONE2 interrupt detected
* 0b1..TRIG4_DONE2 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE2_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK (0x20U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT (5U)
/*! TRIG5_DONE2
* 0b0..No TRIG5_DONE2 interrupt detected
* 0b1..TRIG5_DONE2 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE2_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK (0x40U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT (6U)
/*! TRIG6_DONE2
* 0b0..No TRIG6_DONE2 interrupt detected
* 0b1..TRIG6_DONE2 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE2_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK (0x80U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT (7U)
/*! TRIG7_DONE2
* 0b0..No TRIG7_DONE2 interrupt detected
* 0b1..TRIG7_DONE2 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE2_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK (0x100U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT (8U)
/*! TRIG0_DONE3
* 0b0..No TRIG0_DONE3 interrupt detected
* 0b1..TRIG0_DONE3 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_DONE3_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK (0x200U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT (9U)
/*! TRIG1_DONE3
* 0b0..No TRIG1_DONE3 interrupt detected
* 0b1..TRIG1_DONE3 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_DONE3_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK (0x400U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT (10U)
/*! TRIG2_DONE3
* 0b0..No TRIG2_DONE3 interrupt detected
* 0b1..TRIG2_DONE3 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_DONE3_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK (0x800U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT (11U)
/*! TRIG3_DONE3
* 0b0..No TRIG3_DONE3 interrupt detected
* 0b1..TRIG3_DONE3 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_DONE3_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK (0x1000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT (12U)
/*! TRIG4_DONE3
* 0b0..No TRIG4_DONE3 interrupt detected
* 0b1..TRIG4_DONE3 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_DONE3_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK (0x2000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT (13U)
/*! TRIG5_DONE3
* 0b0..No TRIG5_DONE3 interrupt detected
* 0b1..TRIG5_DONE3 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_DONE3_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK (0x4000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT (14U)
/*! TRIG6_DONE3
* 0b0..No TRIG6_DONE3 interrupt detected
* 0b1..TRIG6_DONE3 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_DONE3_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK (0x8000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT (15U)
/*! TRIG7_DONE3
* 0b0..No TRIG7_DONE3 interrupt detected
* 0b1..TRIG7_DONE3 interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_DONE3_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK (0x10000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT (16U)
/*! TRIG0_ERR
* 0b0..No TRIG0_ERR interrupt detected
* 0b1..TRIG0_ERR interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG0_ERR_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK (0x20000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT (17U)
/*! TRIG1_ERR
* 0b0..No TRIG1_ERR interrupt detected
* 0b1..TRIG1_ERR interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG1_ERR_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK (0x40000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT (18U)
/*! TRIG2_ERR
* 0b0..No TRIG2_ERR interrupt detected
* 0b1..TRIG2_ERR interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG2_ERR_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK (0x80000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT (19U)
/*! TRIG3_ERR
* 0b0..No TRIG3_ERR interrupt detected
* 0b1..TRIG3_ERR interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG3_ERR_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK (0x100000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT (20U)
/*! TRIG4_ERR
* 0b0..No TRIG4_ERR interrupt detected
* 0b1..TRIG4_ERR interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG4_ERR_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK (0x200000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT (21U)
/*! TRIG5_ERR
* 0b0..No TRIG5_ERR interrupt detected
* 0b1..TRIG5_ERR interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG5_ERR_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK (0x400000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT (22U)
/*! TRIG6_ERR
* 0b0..No TRIG6_ERR interrupt detected
* 0b1..TRIG6_ERR interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG6_ERR_MASK)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK (0x800000U)
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT (23U)
/*! TRIG7_ERR
* 0b0..No TRIG7_ERR interrupt detected
* 0b1..TRIG7_ERR interrupt detected
*/
#define ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_SHIFT)) & ADC_ETC_DONE2_3_ERR_IRQ_TRIG7_ERR_MASK)
/*! @} */
/*! @name DMA_CTRL - ETC DMA control Register */
/*! @{ */
#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK (0x1U)
#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT (0U)
/*! TRIG0_ENABLE
* 0b0..TRIG0 DMA request disabled.
* 0b1..TRIG0 DMA request enabled.
*/
#define ADC_ETC_DMA_CTRL_TRIG0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK (0x2U)
#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT (1U)
/*! TRIG1_ENABLE
* 0b0..TRIG1 DMA request disabled.
* 0b1..TRIG1 DMA request enabled.
*/
#define ADC_ETC_DMA_CTRL_TRIG1_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK (0x4U)
#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT (2U)
/*! TRIG2_ENABLE
* 0b0..TRIG2 DMA request disabled.
* 0b1..TRIG2 DMA request enabled.
*/
#define ADC_ETC_DMA_CTRL_TRIG2_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK (0x8U)
#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT (3U)
/*! TRIG3_ENABLE
* 0b0..TRIG3 DMA request disabled.
* 0b1..TRIG3 DMA request enabled.
*/
#define ADC_ETC_DMA_CTRL_TRIG3_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK (0x10U)
#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT (4U)
/*! TRIG4_ENABLE
* 0b0..TRIG4 DMA request disabled.
* 0b1..TRIG4 DMA request enabled.
*/
#define ADC_ETC_DMA_CTRL_TRIG4_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK (0x20U)
#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT (5U)
/*! TRIG5_ENABLE
* 0b0..TRIG5 DMA request disabled.
* 0b1..TRIG5 DMA request enabled.
*/
#define ADC_ETC_DMA_CTRL_TRIG5_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK (0x40U)
#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT (6U)
/*! TRIG6_ENABLE
* 0b0..TRIG6 DMA request disabled.
* 0b1..TRIG6 DMA request enabled.
*/
#define ADC_ETC_DMA_CTRL_TRIG6_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK (0x80U)
#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT (7U)
/*! TRIG7_ENABLE
* 0b0..TRIG7 DMA request disabled.
* 0b1..TRIG7 DMA request enabled.
*/
#define ADC_ETC_DMA_CTRL_TRIG7_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_ENABLE_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_ENABLE_MASK)
#define ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK (0x10000U)
#define ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT (16U)
/*! TRIG0_REQ
* 0b0..TRIG0_REQ not detected.
* 0b1..TRIG0_REQ detected.
*/
#define ADC_ETC_DMA_CTRL_TRIG0_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG0_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG0_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK (0x20000U)
#define ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT (17U)
/*! TRIG1_REQ
* 0b0..TRIG1_REQ not detected.
* 0b1..TRIG1_REQ detected.
*/
#define ADC_ETC_DMA_CTRL_TRIG1_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG1_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG1_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK (0x40000U)
#define ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT (18U)
/*! TRIG2_REQ
* 0b0..TRIG2_REQ not detected.
* 0b1..TRIG2_REQ detected.
*/
#define ADC_ETC_DMA_CTRL_TRIG2_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG2_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG2_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK (0x80000U)
#define ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT (19U)
/*! TRIG3_REQ
* 0b0..TRIG3_REQ not detected.
* 0b1..TRIG3_REQ detected.
*/
#define ADC_ETC_DMA_CTRL_TRIG3_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG3_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG3_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK (0x100000U)
#define ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT (20U)
/*! TRIG4_REQ
* 0b0..TRIG4_REQ not detected.
* 0b1..TRIG4_REQ detected.
*/
#define ADC_ETC_DMA_CTRL_TRIG4_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG4_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG4_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK (0x200000U)
#define ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT (21U)
/*! TRIG5_REQ
* 0b0..TRIG5_REQ not detected.
* 0b1..TRIG5_REQ detected.
*/
#define ADC_ETC_DMA_CTRL_TRIG5_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG5_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG5_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK (0x400000U)
#define ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT (22U)
/*! TRIG6_REQ
* 0b0..TRIG6_REQ not detected.
* 0b1..TRIG6_REQ detected.
*/
#define ADC_ETC_DMA_CTRL_TRIG6_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG6_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG6_REQ_MASK)
#define ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK (0x800000U)
#define ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT (23U)
/*! TRIG7_REQ
* 0b0..TRIG7_REQ not detected.
* 0b1..TRIG7_REQ detected.
*/
#define ADC_ETC_DMA_CTRL_TRIG7_REQ(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_DMA_CTRL_TRIG7_REQ_SHIFT)) & ADC_ETC_DMA_CTRL_TRIG7_REQ_MASK)
/*! @} */
/*! @name TRIGn_CTRL - ETC_TRIG Control Register */
/*! @{ */
#define ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK (0x1U)
#define ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT (0U)
/*! SW_TRIG
* 0b0..No software trigger event generated.
* 0b1..Software trigger event generated.
*/
#define ADC_ETC_TRIGn_CTRL_SW_TRIG(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SW_TRIG_SHIFT)) & ADC_ETC_TRIGn_CTRL_SW_TRIG_MASK)
#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK (0x10U)
#define ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT (4U)
/*! TRIG_MODE
* 0b0..Hardware trigger. The softerware trigger will be ignored.
* 0b1..Software trigger. The hardware trigger will be ignored.
*/
#define ADC_ETC_TRIGn_CTRL_TRIG_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_MODE_MASK)
#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK (0x700U)
#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT (8U)
/*! TRIG_CHAIN
* 0b000..Trigger chain length is 1
* 0b001..Trigger chain length is 2
* 0b010..Trigger chain length is 3
* 0b011..Trigger chain length is 4
* 0b100..Trigger chain length is 5
* 0b101..Trigger chain length is 6
* 0b110..Trigger chain length is 7
* 0b111..Trigger chain length is 8
*/
#define ADC_ETC_TRIGn_CTRL_TRIG_CHAIN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_CHAIN_MASK)
#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK (0x7000U)
#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT (12U)
#define ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_SHIFT)) & ADC_ETC_TRIGn_CTRL_TRIG_PRIORITY_MASK)
#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK (0x10000U)
#define ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT (16U)
/*! SYNC_MODE
* 0b0..Synchronization mode disabled, TRIGa and TRIG(a+4) are triggered independently.
* 0b1..Synchronization mode enabled, TRIGa and TRIG(a+4) are triggered by TRIGa source synchronously.
*/
#define ADC_ETC_TRIGn_CTRL_SYNC_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_SYNC_MODE_SHIFT)) & ADC_ETC_TRIGn_CTRL_SYNC_MODE_MASK)
#define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK (0xFF000000U)
#define ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT (24U)
/*! CHAINx_DONE
* 0b00000000..segment x done not detected.
* 0b00000001..segment x done detected.
*/
#define ADC_ETC_TRIGn_CTRL_CHAINx_DONE(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CTRL_CHAINx_DONE_SHIFT)) & ADC_ETC_TRIGn_CTRL_CHAINx_DONE_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_CTRL */
#define ADC_ETC_TRIGn_CTRL_COUNT (8U)
/*! @name TRIGn_COUNTER - ETC_TRIG Counter Register */
/*! @{ */
#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK (0xFFFFU)
#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT (0U)
#define ADC_ETC_TRIGn_COUNTER_INIT_DELAY(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_INIT_DELAY_SHIFT)) & ADC_ETC_TRIGn_COUNTER_INIT_DELAY_MASK)
#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK (0xFFFF0000U)
#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT (16U)
#define ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_SHIFT)) & ADC_ETC_TRIGn_COUNTER_SAMPLE_INTERVAL_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_COUNTER */
#define ADC_ETC_TRIGn_COUNTER_COUNT (8U)
/*! @name TRIGn_CHAIN_1_0 - ETC_TRIG Chain 0/1 Register */
/*! @{ */
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK (0xFU)
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT (0U)
/*! CSEL0
* 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
* 0b0001..ADC CMD1 selected.
* 0b0010..ADC CMD2 selected.
* 0b0011..ADC CMD3 selected.
* 0b0100..ADC CMD4 selected.
* 0b0101..ADC CMD5 selected.
* 0b0110..ADC CMD6 selected.
* 0b0111..ADC CMD7 selected.
* 0b1000..ADC CMD8 selected.
* 0b1001..ADC CMD9 selected.
* 0b1010..ADC CMD10 selected.
* 0b1011..ADC CMD11 selected.
* 0b1100..ADC CMD12 selected.
* 0b1101..ADC CMD13 selected.
* 0b1110..ADC CMD14 selected.
* 0b1111..ADC CMD15 selected.
*/
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL0_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK (0xFF0U)
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT (4U)
/*! HWTS0
* 0b00000000..no trigger selected
* 0b00000001..ADC TRIG0 selected
* 0b00000010..ADC TRIG1 selected
* 0b00000100..ADC TRIG2 selected
* 0b00001000..ADC TRIG3 selected
* 0b00010000..ADC TRIG4 selected
* 0b00100000..ADC TRIG5 selected
* 0b01000000..ADC TRIG6 selected
* 0b10000000..ADC TRIG7 selected
*/
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS0_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK (0x1000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT (12U)
/*! B2B0
* 0b0..Disable B2B. Wait until delay value defined by TRIG0_COUNTER[SAMPLE_INTERVAL] is reached
* 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
*/
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B0_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK (0x6000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT (13U)
/*! IE0
* 0b00..Generate interrupt on Done0 when segment 0 finish.
* 0b01..Generate interrupt on Done1 when segment 0 finish.
* 0b10..Generate interrupt on Done2 when segment 0 finish.
* 0b11..Generate interrupt on Done3 when segment 0 finish.
*/
#define ADC_ETC_TRIGn_CHAIN_1_0_IE0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK (0x8000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT (15U)
/*! IE0_EN
* 0b0..Interrupt DONE disabled.
* 0b1..Interrupt DONE enabled. When segment 0 finish, an interrupt will be generated on the specific port configured by the IE0.
*/
#define ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE0_EN_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK (0xF0000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT (16U)
/*! CSEL1
* 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
* 0b0001..ADC CMD1 selected.
* 0b0010..ADC CMD2 selected.
* 0b0011..ADC CMD3 selected.
* 0b0100..ADC CMD4 selected.
* 0b0101..ADC CMD5 selected.
* 0b0110..ADC CMD6 selected.
* 0b0111..ADC CMD7 selected.
* 0b1000..ADC CMD8 selected.
* 0b1001..ADC CMD9 selected.
* 0b1010..ADC CMD10 selected.
* 0b1011..ADC CMD11 selected.
* 0b1100..ADC CMD12 selected.
* 0b1101..ADC CMD13 selected.
* 0b1110..ADC CMD14 selected.
* 0b1111..ADC CMD15 selected.
*/
#define ADC_ETC_TRIGn_CHAIN_1_0_CSEL1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_CSEL1_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK (0xFF00000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT (20U)
/*! HWTS1
* 0b00000000..no trigger selected
* 0b00000001..ADC TRIG0 selected
* 0b00000010..ADC TRIG1 selected
* 0b00000100..ADC TRIG2 selected
* 0b00001000..ADC TRIG3 selected
* 0b00010000..ADC TRIG4 selected
* 0b00100000..ADC TRIG5 selected
* 0b01000000..ADC TRIG6 selected
* 0b10000000..ADC TRIG7 selected
*/
#define ADC_ETC_TRIGn_CHAIN_1_0_HWTS1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_HWTS1_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK (0x10000000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT (28U)
/*! B2B1
* 0b0..Disable B2B. Wait until delay value defined by TRIG1_COUNTER[SAMPLE_INTERVAL] is reached
* 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
*/
#define ADC_ETC_TRIGn_CHAIN_1_0_B2B1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_B2B1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_B2B1_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK (0x60000000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT (29U)
/*! IE1
* 0b00..Generate interrupt on Done0 when Segment 1 finish.
* 0b01..Generate interrupt on Done1 when Segment 1 finish.
* 0b10..Generate interrupt on Done2 when Segment 1 finish.
* 0b11..Generate interrupt on Done3 when Segment 1 finish.
*/
#define ADC_ETC_TRIGn_CHAIN_1_0_IE1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_MASK)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK (0x80000000U)
#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT (31U)
/*! IE1_EN
* 0b0..Interrupt DONE disabled.
* 0b1..Interrupt DONE enabled. When segment 1 finish, an interrupt will be generated on the specific port configured by the IE1.
*/
#define ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_1_0_IE1_EN_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_CHAIN_1_0 */
#define ADC_ETC_TRIGn_CHAIN_1_0_COUNT (8U)
/*! @name TRIGn_CHAIN_3_2 - ETC_TRIG Chain 2/3 Register */
/*! @{ */
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK (0xFU)
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT (0U)
/*! CSEL2
* 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
* 0b0001..ADC CMD1 selected.
* 0b0010..ADC CMD2 selected.
* 0b0011..ADC CMD3 selected.
* 0b0100..ADC CMD4 selected.
* 0b0101..ADC CMD5 selected.
* 0b0110..ADC CMD6 selected.
* 0b0111..ADC CMD7 selected.
* 0b1000..ADC CMD8 selected.
* 0b1001..ADC CMD9 selected.
* 0b1010..ADC CMD10 selected.
* 0b1011..ADC CMD11 selected.
* 0b1100..ADC CMD12 selected.
* 0b1101..ADC CMD13 selected.
* 0b1110..ADC CMD14 selected.
* 0b1111..ADC CMD15 selected.
*/
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL2_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK (0xFF0U)
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT (4U)
/*! HWTS2
* 0b00000000..no trigger selected
* 0b00000001..ADC TRIG0 selected
* 0b00000010..ADC TRIG1 selected
* 0b00000100..ADC TRIG2 selected
* 0b00001000..ADC TRIG3 selected
* 0b00010000..ADC TRIG4 selected
* 0b00100000..ADC TRIG5 selected
* 0b01000000..ADC TRIG6 selected
* 0b10000000..ADC TRIG7 selected
*/
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS2_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK (0x1000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT (12U)
/*! B2B2
* 0b0..Disable B2B. Wait until delay value defined by TRIG2_COUNTER[SAMPLE_INTERVAL] is reached
* 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
*/
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B2_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK (0x6000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT (13U)
/*! IE2
* 0b00..Generate interrupt on Done0 when segment 2 finish.
* 0b01..Generate interrupt on Done1 when segment 2 finish.
* 0b10..Generate interrupt on Done2 when segment 2 finish.
* 0b11..Generate interrupt on Done3 when segment 2 finish.
*/
#define ADC_ETC_TRIGn_CHAIN_3_2_IE2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK (0x8000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT (15U)
/*! IE2_EN
* 0b0..Interrupt DONE disabled.
* 0b1..Interrupt DONE enabled. When segment 2 finish, an interrupt will be generated on the specific port configured by the IE2.
*/
#define ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE2_EN_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK (0xF0000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT (16U)
/*! CSEL3
* 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
* 0b0001..ADC CMD1 selected.
* 0b0010..ADC CMD2 selected.
* 0b0011..ADC CMD3 selected.
* 0b0100..ADC CMD4 selected.
* 0b0101..ADC CMD5 selected.
* 0b0110..ADC CMD6 selected.
* 0b0111..ADC CMD7 selected.
* 0b1000..ADC CMD8 selected.
* 0b1001..ADC CMD9 selected.
* 0b1010..ADC CMD10 selected.
* 0b1011..ADC CMD11 selected.
* 0b1100..ADC CMD12 selected.
* 0b1101..ADC CMD13 selected.
* 0b1110..ADC CMD14 selected.
* 0b1111..ADC CMD15 selected.
*/
#define ADC_ETC_TRIGn_CHAIN_3_2_CSEL3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_CSEL3_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK (0xFF00000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT (20U)
/*! HWTS3
* 0b00000000..no trigger selected
* 0b00000001..ADC TRIG0 selected
* 0b00000010..ADC TRIG1 selected
* 0b00000100..ADC TRIG2 selected
* 0b00001000..ADC TRIG3 selected
* 0b00010000..ADC TRIG4 selected
* 0b00100000..ADC TRIG5 selected
* 0b01000000..ADC TRIG6 selected
* 0b10000000..ADC TRIG7 selected
*/
#define ADC_ETC_TRIGn_CHAIN_3_2_HWTS3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_HWTS3_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK (0x10000000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT (28U)
/*! B2B3
* 0b0..Disable B2B. Wait until delay value defined by TRIG3_COUNTER[SAMPLE_INTERVAL] is reached
* 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
*/
#define ADC_ETC_TRIGn_CHAIN_3_2_B2B3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_B2B3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_B2B3_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK (0x60000000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT (29U)
/*! IE3
* 0b00..Generate interrupt on Done0 when segment 3 finish.
* 0b01..Generate interrupt on Done1 when segment 3 finish.
* 0b10..Generate interrupt on Done2 when segment 3 finish.
* 0b11..Generate interrupt on Done3 when segment 3 finish.
*/
#define ADC_ETC_TRIGn_CHAIN_3_2_IE3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_MASK)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK (0x80000000U)
#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT (31U)
/*! IE3_EN
* 0b0..Interrupt DONE disabled.
* 0b1..Interrupt DONE enabled. When segment 3 finish, an interrupt will be generated on the specific port configured by the IE3.
*/
#define ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_3_2_IE3_EN_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_CHAIN_3_2 */
#define ADC_ETC_TRIGn_CHAIN_3_2_COUNT (8U)
/*! @name TRIGn_CHAIN_5_4 - ETC_TRIG Chain 4/5 Register */
/*! @{ */
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK (0xFU)
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT (0U)
/*! CSEL4
* 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
* 0b0001..ADC CMD1 selected.
* 0b0010..ADC CMD2 selected.
* 0b0011..ADC CMD3 selected.
* 0b0100..ADC CMD4 selected.
* 0b0101..ADC CMD5 selected.
* 0b0110..ADC CMD6 selected.
* 0b0111..ADC CMD7 selected.
* 0b1000..ADC CMD8 selected.
* 0b1001..ADC CMD9 selected.
* 0b1010..ADC CMD10 selected.
* 0b1011..ADC CMD11 selected.
* 0b1100..ADC CMD12 selected.
* 0b1101..ADC CMD13 selected.
* 0b1110..ADC CMD14 selected.
* 0b1111..ADC CMD15 selected.
*/
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL4_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK (0xFF0U)
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT (4U)
/*! HWTS4
* 0b00000000..no trigger selected
* 0b00000001..ADC TRIG0 selected
* 0b00000010..ADC TRIG1 selected
* 0b00000100..ADC TRIG2 selected
* 0b00001000..ADC TRIG3 selected
* 0b00010000..ADC TRIG4 selected
* 0b00100000..ADC TRIG5 selected
* 0b01000000..ADC TRIG6 selected
* 0b10000000..ADC TRIG7 selected
*/
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS4_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK (0x1000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT (12U)
/*! B2B4
* 0b0..Disable B2B. Wait until delay value defined by TRIG4_COUNTER[SAMPLE_INTERVAL] is reached
* 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
*/
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B4_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK (0x6000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT (13U)
/*! IE4
* 0b00..Generate interrupt on Done0 when segment 4 finish.
* 0b01..Generate interrupt on Done1 when segment 4 finish.
* 0b10..Generate interrupt on Done2 when segment 4 finish.
* 0b11..Generate interrupt on Done3 when segment 4 finish.
*/
#define ADC_ETC_TRIGn_CHAIN_5_4_IE4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK (0x8000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT (15U)
/*! IE4_EN
* 0b0..Interrupt DONE disabled.
* 0b1..Interrupt DONE enabled. When segment 4 finish, an interrupt will be generated on the specific port configured by the IE4.
*/
#define ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE4_EN_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK (0xF0000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT (16U)
/*! CSEL5
* 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
* 0b0001..ADC CMD1 selected.
* 0b0010..ADC CMD2 selected.
* 0b0011..ADC CMD3 selected.
* 0b0100..ADC CMD4 selected.
* 0b0101..ADC CMD5 selected.
* 0b0110..ADC CMD6 selected.
* 0b0111..ADC CMD7 selected.
* 0b1000..ADC CMD8 selected.
* 0b1001..ADC CMD9 selected.
* 0b1010..ADC CMD10 selected.
* 0b1011..ADC CMD11 selected.
* 0b1100..ADC CMD12 selected.
* 0b1101..ADC CMD13 selected.
* 0b1110..ADC CMD14 selected.
* 0b1111..ADC CMD15 selected.
*/
#define ADC_ETC_TRIGn_CHAIN_5_4_CSEL5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_CSEL5_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK (0xFF00000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT (20U)
/*! HWTS5
* 0b00000000..no trigger selected
* 0b00000001..ADC TRIG0 selected
* 0b00000010..ADC TRIG1 selected
* 0b00000100..ADC TRIG2 selected
* 0b00001000..ADC TRIG3 selected
* 0b00010000..ADC TRIG4 selected
* 0b00100000..ADC TRIG5 selected
* 0b01000000..ADC TRIG6 selected
* 0b10000000..ADC TRIG7 selected
*/
#define ADC_ETC_TRIGn_CHAIN_5_4_HWTS5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_HWTS5_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK (0x10000000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT (28U)
/*! B2B5
* 0b0..Disable B2B. Wait until delay value defined by TRIG5_COUNTER[SAMPLE_INTERVAL] is reached
* 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
*/
#define ADC_ETC_TRIGn_CHAIN_5_4_B2B5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_B2B5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_B2B5_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK (0x60000000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT (29U)
/*! IE5
* 0b00..Generate interrupt on Done0 when segment 5 finish.
* 0b01..Generate interrupt on Done1 when segment 5 finish.
* 0b10..Generate interrupt on Done2 when segment 5 finish.
* 0b11..Generate interrupt on Done3 when segment 5 finish.
*/
#define ADC_ETC_TRIGn_CHAIN_5_4_IE5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_MASK)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK (0x80000000U)
#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT (31U)
/*! IE5_EN
* 0b0..Interrupt DONE disabled.
* 0b1..Interrupt DONE enabled. When segment 5 finish, an interrupt will be generated on the specific port configured by the IE5.
*/
#define ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_5_4_IE5_EN_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_CHAIN_5_4 */
#define ADC_ETC_TRIGn_CHAIN_5_4_COUNT (8U)
/*! @name TRIGn_CHAIN_7_6 - ETC_TRIG Chain 6/7 Register */
/*! @{ */
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK (0xFU)
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT (0U)
/*! CSEL6
* 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
* 0b0001..ADC CMD1 selected.
* 0b0010..ADC CMD2 selected.
* 0b0011..ADC CMD3 selected.
* 0b0100..ADC CMD4 selected.
* 0b0101..ADC CMD5 selected.
* 0b0110..ADC CMD6 selected.
* 0b0111..ADC CMD7 selected.
* 0b1000..ADC CMD8 selected.
* 0b1001..ADC CMD9 selected.
* 0b1010..ADC CMD10 selected.
* 0b1011..ADC CMD11 selected.
* 0b1100..ADC CMD12 selected.
* 0b1101..ADC CMD13 selected.
* 0b1110..ADC CMD14 selected.
* 0b1111..ADC CMD15 selected.
*/
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL6_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK (0xFF0U)
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT (4U)
/*! HWTS6
* 0b00000000..no trigger selected
* 0b00000001..ADC TRIG0 selected
* 0b00000010..ADC TRIG1 selected
* 0b00000100..ADC TRIG2 selected
* 0b00001000..ADC TRIG3 selected
* 0b00010000..ADC TRIG4 selected
* 0b00100000..ADC TRIG5 selected
* 0b01000000..ADC TRIG6 selected
* 0b10000000..ADC TRIG7 selected
*/
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS6_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK (0x1000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT (12U)
/*! B2B6
* 0b0..Disable B2B. Wait until delay value defined by TRIG6_COUNTER[SAMPLE_INTERVAL] is reached
* 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
*/
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B6_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK (0x6000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT (13U)
/*! IE6
* 0b00..Generate interrupt on Done0 when segment 6 finish.
* 0b01..Generate interrupt on Done1 when segment 6 finish.
* 0b10..Generate interrupt on Done2 when segment 6 finish.
* 0b11..Generate interrupt on Done3 when segment 6 finish.
*/
#define ADC_ETC_TRIGn_CHAIN_7_6_IE6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK (0x8000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT (15U)
/*! IE6_EN
* 0b0..Interrupt DONE disabled.
* 0b1..Interrupt DONE enabled. When segment 6 finish, an interrupt will be generated on the specific port configured by the IE6.
*/
#define ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE6_EN_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK (0xF0000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT (16U)
/*! CSEL7
* 0b0000..Not a valid selection from the command buffer. Trigger event is ignored.
* 0b0001..ADC CMD1 selected.
* 0b0010..ADC CMD2 selected.
* 0b0011..ADC CMD3 selected.
* 0b0100..ADC CMD4 selected.
* 0b0101..ADC CMD5 selected.
* 0b0110..ADC CMD6 selected.
* 0b0111..ADC CMD7 selected.
* 0b1000..ADC CMD8 selected.
* 0b1001..ADC CMD9 selected.
* 0b1010..ADC CMD10 selected.
* 0b1011..ADC CMD11 selected.
* 0b1100..ADC CMD12 selected.
* 0b1101..ADC CMD13 selected.
* 0b1110..ADC CMD14 selected.
* 0b1111..ADC CMD15 selected.
*/
#define ADC_ETC_TRIGn_CHAIN_7_6_CSEL7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_CSEL7_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK (0xFF00000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT (20U)
/*! HWTS7
* 0b00000000..no trigger selected
* 0b00000001..ADC TRIG0 selected
* 0b00000010..ADC TRIG1 selected
* 0b00000100..ADC TRIG2 selected
* 0b00001000..ADC TRIG3 selected
* 0b00010000..ADC TRIG4 selected
* 0b00100000..ADC TRIG5 selected
* 0b01000000..ADC TRIG6 selected
* 0b10000000..ADC TRIG7 selected
*/
#define ADC_ETC_TRIGn_CHAIN_7_6_HWTS7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_HWTS7_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK (0x10000000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT (28U)
/*! B2B7
* 0b0..Disable B2B. Wait until delay value defined by TRIG7_COUNTER[SAMPLE_INTERVAL] is reached
* 0b1..Enable B2B. When Segment 0 finished (ADC COCO) then automatically trigger next ADC conversion, no need to wait until interval delay reached.
*/
#define ADC_ETC_TRIGn_CHAIN_7_6_B2B7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_B2B7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_B2B7_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK (0x60000000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT (29U)
/*! IE7
* 0b00..Generate interrupt on Done0 when segment 7 finish.
* 0b01..Generate interrupt on Done1 when segment 7 finish.
* 0b10..Generate interrupt on Done2 when segment 7 finish.
* 0b11..Generate interrupt on Done3 when segment 7 finish.
*/
#define ADC_ETC_TRIGn_CHAIN_7_6_IE7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_MASK)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK (0x80000000U)
#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT (31U)
/*! IE7_EN
* 0b0..Interrupt DONE disabled.
* 0b1..Interrupt DONE enabled. When segment 7 finish, an interrupt will be generated on the specific port configured by the IE7.
*/
#define ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_SHIFT)) & ADC_ETC_TRIGn_CHAIN_7_6_IE7_EN_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_CHAIN_7_6 */
#define ADC_ETC_TRIGn_CHAIN_7_6_COUNT (8U)
/*! @name TRIGn_RESULT_1_0 - ETC_TRIG Result Data 1/0 Register */
/*! @{ */
#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK (0xFFFU)
#define ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT (0U)
#define ADC_ETC_TRIGn_RESULT_1_0_DATA0(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA0_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA0_MASK)
#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK (0xFFF0000U)
#define ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT (16U)
#define ADC_ETC_TRIGn_RESULT_1_0_DATA1(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_1_0_DATA1_SHIFT)) & ADC_ETC_TRIGn_RESULT_1_0_DATA1_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_RESULT_1_0 */
#define ADC_ETC_TRIGn_RESULT_1_0_COUNT (8U)
/*! @name TRIGn_RESULT_3_2 - ETC_TRIG Result Data 3/2 Register */
/*! @{ */
#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK (0xFFFU)
#define ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT (0U)
#define ADC_ETC_TRIGn_RESULT_3_2_DATA2(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA2_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA2_MASK)
#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK (0xFFF0000U)
#define ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT (16U)
#define ADC_ETC_TRIGn_RESULT_3_2_DATA3(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_3_2_DATA3_SHIFT)) & ADC_ETC_TRIGn_RESULT_3_2_DATA3_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_RESULT_3_2 */
#define ADC_ETC_TRIGn_RESULT_3_2_COUNT (8U)
/*! @name TRIGn_RESULT_5_4 - ETC_TRIG Result Data 5/4 Register */
/*! @{ */
#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK (0xFFFU)
#define ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT (0U)
#define ADC_ETC_TRIGn_RESULT_5_4_DATA4(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA4_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA4_MASK)
#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK (0xFFF0000U)
#define ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT (16U)
#define ADC_ETC_TRIGn_RESULT_5_4_DATA5(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_5_4_DATA5_SHIFT)) & ADC_ETC_TRIGn_RESULT_5_4_DATA5_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_RESULT_5_4 */
#define ADC_ETC_TRIGn_RESULT_5_4_COUNT (8U)
/*! @name TRIGn_RESULT_7_6 - ETC_TRIG Result Data 7/6 Register */
/*! @{ */
#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK (0xFFFU)
#define ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT (0U)
#define ADC_ETC_TRIGn_RESULT_7_6_DATA6(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA6_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA6_MASK)
#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK (0xFFF0000U)
#define ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT (16U)
#define ADC_ETC_TRIGn_RESULT_7_6_DATA7(x) (((uint32_t)(((uint32_t)(x)) << ADC_ETC_TRIGn_RESULT_7_6_DATA7_SHIFT)) & ADC_ETC_TRIGn_RESULT_7_6_DATA7_MASK)
/*! @} */
/* The count of ADC_ETC_TRIGn_RESULT_7_6 */
#define ADC_ETC_TRIGn_RESULT_7_6_COUNT (8U)
/*!
* @}
*/ /* end of group ADC_ETC_Register_Masks */
/* ADC_ETC - Peripheral instance base addresses */
/** Peripheral ADC_ETC base address */
#define ADC_ETC_BASE (0x40048000u)
/** Peripheral ADC_ETC base pointer */
#define ADC_ETC ((ADC_ETC_Type *)ADC_ETC_BASE)
/** Array initializer of ADC_ETC peripheral base addresses */
#define ADC_ETC_BASE_ADDRS { ADC_ETC_BASE }
/** Array initializer of ADC_ETC peripheral base pointers */
#define ADC_ETC_BASE_PTRS { ADC_ETC }
/** Interrupt vectors for the ADC_ETC peripheral type */
#define ADC_ETC_IRQS { { ADC_ETC_IRQ0_IRQn, ADC_ETC_IRQ1_IRQn, ADC_ETC_IRQ2_IRQn, ADC_ETC_IRQ3_IRQn } }
#define ADC_ETC_FAULT_IRQS { ADC_ETC_ERROR_IRQ_IRQn }
/*!
* @}
*/ /* end of group ADC_ETC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ANADIG_LDO_SNVS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_LDO_SNVS_Peripheral_Access_Layer ANADIG_LDO_SNVS Peripheral Access Layer
* @{
*/
/** ANADIG_LDO_SNVS - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[1296];
__IO uint32_t PMU_LDO_LPSR_ANA; /**< PMU_LDO_LPSR_ANA_REGISTER, offset: 0x510 */
uint8_t RESERVED_1[12];
__IO uint32_t PMU_LDO_LPSR_DIG_2; /**< PMU_LDO_LPSR_DIG_2_REGISTER, offset: 0x520 */
uint8_t RESERVED_2[12];
__IO uint32_t PMU_LDO_LPSR_DIG; /**< PMU_LDO_LPSR_DIG_REGISTER, offset: 0x530 */
} ANADIG_LDO_SNVS_Type;
/* ----------------------------------------------------------------------------
-- ANADIG_LDO_SNVS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_LDO_SNVS_Register_Masks ANADIG_LDO_SNVS Register Masks
* @{
*/
/*! @name PMU_LDO_LPSR_ANA - PMU_LDO_LPSR_ANA_REGISTER */
/*! @{ */
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK (0x1U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT (0U)
/*! REG_LP_EN - reg_lp_en
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_LP_EN_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK (0x4U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT (2U)
/*! REG_DISABLE - reg_disable
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_REG_DISABLE_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK (0x8U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT (3U)
/*! PULL_DOWN_2MA_EN - pull_down_2ma_en
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_2MA_EN_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK (0x10U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT (4U)
/*! LPSR_ANA_CONTROL_MODE - LPSR_ANA_CONTROL_MODE
* 0b0..SW Control
* 0b1..HW Control
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_LPSR_ANA_CONTROL_MODE_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK (0x20U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT (5U)
/*! BYPASS_MODE_EN - bypass_mode_en
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_BYPASS_MODE_EN_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK (0x40U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT (6U)
/*! STANDBY_EN - standby_en
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_STANDBY_EN_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK (0x100U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT (8U)
/*! ALWAYS_4MA_PULLDOWN_EN - always_4ma_pulldown_en
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_ALWAYS_4MA_PULLDOWN_EN_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK (0x80000U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT (19U)
/*! TRACK_MODE_EN - Track Mode Enable
* 0b0..Normal use
* 0b1..Switch preparation
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_TRACK_MODE_EN_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK (0x100000U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT (20U)
/*! PULL_DOWN_20UA_EN - pull_down_20ua_en
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_ANA_PULL_DOWN_20UA_EN_MASK)
/*! @} */
/*! @name PMU_LDO_LPSR_DIG_2 - PMU_LDO_LPSR_DIG_2_REGISTER */
/*! @{ */
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK (0x3U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT (0U)
/*! VOLTAGE_STEP_INC - voltage_step_inc
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_2_VOLTAGE_STEP_INC_MASK)
/*! @} */
/*! @name PMU_LDO_LPSR_DIG - PMU_LDO_LPSR_DIG_REGISTER */
/*! @{ */
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK (0x4U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT (2U)
/*! REG_EN - ENABLE_ILIMIT
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_REG_EN_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK (0x20U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT (5U)
/*! LPSR_DIG_CONTROL_MODE - LPSR_DIG_CONTROL_MODE
* 0b0..SW Control
* 0b1..HW Control
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_LPSR_DIG_CONTROL_MODE_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK (0x40U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT (6U)
/*! STANDBY_EN - standby_en
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_STANDBY_EN_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK (0x20000U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT (17U)
/*! TRACKING_MODE - tracking_mode
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_TRACKING_MODE_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK (0x40000U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT (18U)
/*! BYPASS_MODE - bypass_mode
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_BYPASS_MODE_MASK)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK (0x1F00000U)
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT (20U)
/*! VOLTAGE_SELECT - VOLTAGE_SELECT
* 0b00000..Stable Voltage (range)
* 0b00001..Stable Voltage (range)
* 0b00010..Stable Voltage (range)
* 0b00011..Stable Voltage (range)
* 0b00100..Stable Voltage (range)
* 0b00101..Stable Voltage (range)
* 0b00110..Stable Voltage (range)
* 0b00111..Stable Voltage (range)
* 0b01000..Stable Voltage (range)
* 0b01001..Stable Voltage (range)
* 0b01010..Stable Voltage (range)
* 0b01011..Stable Voltage (range)
* 0b01100..Stable Voltage (range)
* 0b01101..Stable Voltage (range)
* 0b01110..Stable Voltage (range)
* 0b01111..Stable Voltage (range)
* 0b10000..Stable Voltage (range)
* 0b10001..Stable Voltage (range)
* 0b10010..Stable Voltage (range)
* 0b10011..Stable Voltage (range)
* 0b10100..Stable Voltage (range)
* 0b10101..Stable Voltage (range)
* 0b10110..Stable Voltage (range)
* 0b10111..Stable Voltage (range)
* 0b11000..Stable Voltage (range)
* 0b11001..Stable Voltage (range)
* 0b11010..Stable Voltage (range)
* 0b11011..Stable Voltage (range)
* 0b11100..Stable Voltage (range)
* 0b11101..Stable Voltage (range)
* 0b11110..Stable Voltage (range)
* 0b11111..Stable Voltage (range)
*/
#define ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_SHIFT)) & ANADIG_LDO_SNVS_PMU_LDO_LPSR_DIG_VOLTAGE_SELECT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ANADIG_LDO_SNVS_Register_Masks */
/* ANADIG_LDO_SNVS - Peripheral instance base addresses */
/** Peripheral ANADIG_LDO_SNVS base address */
#define ANADIG_LDO_SNVS_BASE (0x40C84000u)
/** Peripheral ANADIG_LDO_SNVS base pointer */
#define ANADIG_LDO_SNVS ((ANADIG_LDO_SNVS_Type *)ANADIG_LDO_SNVS_BASE)
/** Array initializer of ANADIG_LDO_SNVS peripheral base addresses */
#define ANADIG_LDO_SNVS_BASE_ADDRS { ANADIG_LDO_SNVS_BASE }
/** Array initializer of ANADIG_LDO_SNVS peripheral base pointers */
#define ANADIG_LDO_SNVS_BASE_PTRS { ANADIG_LDO_SNVS }
/*!
* @}
*/ /* end of group ANADIG_LDO_SNVS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ANADIG_LDO_SNVS_DIG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_LDO_SNVS_DIG_Peripheral_Access_Layer ANADIG_LDO_SNVS_DIG Peripheral Access Layer
* @{
*/
/** ANADIG_LDO_SNVS_DIG - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[1344];
__IO uint32_t PMU_LDO_SNVS_DIG; /**< PMU_LDO_SNVS_DIG_REGISTER, offset: 0x540 */
} ANADIG_LDO_SNVS_DIG_Type;
/* ----------------------------------------------------------------------------
-- ANADIG_LDO_SNVS_DIG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_LDO_SNVS_DIG_Register_Masks ANADIG_LDO_SNVS_DIG Register Masks
* @{
*/
/*! @name PMU_LDO_SNVS_DIG - PMU_LDO_SNVS_DIG_REGISTER */
/*! @{ */
#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK (0x1U)
#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT (0U)
/*! REG_LP_EN - REG_LP_EN
*/
#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_LP_EN_MASK)
#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK (0x2U)
#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT (1U)
/*! TEST_OVERRIDE - test_override
*/
#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_TEST_OVERRIDE_MASK)
#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK (0x4U)
#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT (2U)
/*! REG_EN - REG_EN
*/
#define ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_SHIFT)) & ANADIG_LDO_SNVS_DIG_PMU_LDO_SNVS_DIG_REG_EN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ANADIG_LDO_SNVS_DIG_Register_Masks */
/* ANADIG_LDO_SNVS_DIG - Peripheral instance base addresses */
/** Peripheral ANADIG_LDO_SNVS_DIG base address */
#define ANADIG_LDO_SNVS_DIG_BASE (0x40C84000u)
/** Peripheral ANADIG_LDO_SNVS_DIG base pointer */
#define ANADIG_LDO_SNVS_DIG ((ANADIG_LDO_SNVS_DIG_Type *)ANADIG_LDO_SNVS_DIG_BASE)
/** Array initializer of ANADIG_LDO_SNVS_DIG peripheral base addresses */
#define ANADIG_LDO_SNVS_DIG_BASE_ADDRS { ANADIG_LDO_SNVS_DIG_BASE }
/** Array initializer of ANADIG_LDO_SNVS_DIG peripheral base pointers */
#define ANADIG_LDO_SNVS_DIG_BASE_PTRS { ANADIG_LDO_SNVS_DIG }
/*!
* @}
*/ /* end of group ANADIG_LDO_SNVS_DIG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ANADIG_MISC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_MISC_Peripheral_Access_Layer ANADIG_MISC Peripheral Access Layer
* @{
*/
/** ANADIG_MISC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[2048];
__I uint32_t MISC_DIFPROG; /**< Chip Silicon Version Register, offset: 0x800 */
uint8_t RESERVED_1[28];
__IO uint32_t VDDSOC_AI_CTRL; /**< VDDSOC_AI_CTRL_REGISTER, offset: 0x820 */
uint8_t RESERVED_2[12];
__IO uint32_t VDDSOC_AI_WDATA; /**< VDDSOC_AI_WDATA_REGISTER, offset: 0x830 */
uint8_t RESERVED_3[12];
__I uint32_t VDDSOC_AI_RDATA; /**< VDDSOC_AI_RDATA_REGISTER, offset: 0x840 */
uint8_t RESERVED_4[12];
__IO uint32_t VDDSOC2PLL_AI_CTRL_1G; /**< VDDSOC2PLL_AI_CTRL_1G_REGISTER, offset: 0x850 */
uint8_t RESERVED_5[12];
__IO uint32_t VDDSOC2PLL_AI_WDATA_1G; /**< VDDSOC2PLL_AI_WDATA_1G_REGISTER, offset: 0x860 */
uint8_t RESERVED_6[12];
__I uint32_t VDDSOC2PLL_AI_RDATA_1G; /**< VDDSOC2PLL_AI_RDATA_1G_REGISTER, offset: 0x870 */
uint8_t RESERVED_7[12];
__IO uint32_t VDDSOC2PLL_AI_CTRL_AUDIO; /**< VDDSOC_AI_CTRL_AUDIO_REGISTER, offset: 0x880 */
uint8_t RESERVED_8[12];
__IO uint32_t VDDSOC2PLL_AI_WDATA_AUDIO; /**< VDDSOC_AI_WDATA_AUDIO_REGISTER, offset: 0x890 */
uint8_t RESERVED_9[12];
__I uint32_t VDDSOC2PLL_AI_RDATA_AUDIO; /**< VDDSOC2PLL_AI_RDATA_REGISTER, offset: 0x8A0 */
uint8_t RESERVED_10[12];
__IO uint32_t VDDSOC2PLL_AI_CTRL_VIDEO; /**< VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER, offset: 0x8B0 */
uint8_t RESERVED_11[12];
__IO uint32_t VDDSOC2PLL_AI_WDATA_VIDEO; /**< VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER, offset: 0x8C0 */
uint8_t RESERVED_12[12];
__I uint32_t VDDSOC2PLL_AI_RDATA_VIDEO; /**< VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER, offset: 0x8D0 */
uint8_t RESERVED_13[12];
__IO uint32_t VDDLPSR_AI_CTRL; /**< VDDSOC_AI_CTRL_REGISTER, offset: 0x8E0 */
uint8_t RESERVED_14[12];
__IO uint32_t VDDLPSR_AI_WDATA; /**< VDDLPSR_AI_WDATA_REGISTER, offset: 0x8F0 */
uint8_t RESERVED_15[12];
__I uint32_t VDDLPSR_AI_RDATA_REFTOP; /**< VDDLPSR_AI_RDATA_REFTOP_REGISTER, offset: 0x900 */
uint8_t RESERVED_16[12];
__I uint32_t VDDLPSR_AI_RDATA_TMPSNS; /**< VDDLPSR_AI_RDATA_TMPSNS_REGISTER, offset: 0x910 */
uint8_t RESERVED_17[12];
__IO uint32_t VDDLPSR_AI400M_CTRL; /**< VDDLPSR_AI400M_CTRL_REGISTER, offset: 0x920 */
uint8_t RESERVED_18[12];
__IO uint32_t VDDLPSR_AI400M_WDATA; /**< VDDLPSR_AI400M_WDATA_REGISTER, offset: 0x930 */
uint8_t RESERVED_19[12];
__I uint32_t VDDLPSR_AI400M_RDATA; /**< VDDLPSR_AI400M_RDATA_REGISTER, offset: 0x940 */
} ANADIG_MISC_Type;
/* ----------------------------------------------------------------------------
-- ANADIG_MISC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_MISC_Register_Masks ANADIG_MISC Register Masks
* @{
*/
/*! @name MISC_DIFPROG - Chip Silicon Version Register */
/*! @{ */
#define ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT (0U)
/*! CHIPID - Chip ID
*/
#define ANADIG_MISC_MISC_DIFPROG_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_MISC_DIFPROG_CHIPID_SHIFT)) & ANADIG_MISC_MISC_DIFPROG_CHIPID_MASK)
/*! @} */
/*! @name VDDSOC_AI_CTRL - VDDSOC_AI_CTRL_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK (0xFFU)
#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT (0U)
/*! VDDSOC_AI_ADDR - VDDSOC_AI_ADDR
*/
#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AI_ADDR_MASK)
#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK (0x10000U)
#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT (16U)
/*! VDDSOC_AIRWB - VDDSOC_AIRWB
*/
#define ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_SHIFT)) & ANADIG_MISC_VDDSOC_AI_CTRL_VDDSOC_AIRWB_MASK)
/*! @} */
/*! @name VDDSOC_AI_WDATA - VDDSOC_AI_WDATA_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT (0U)
/*! VDDSOC_AI_WDATA - VDDSOC_AI_WDATA
*/
#define ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_WDATA_VDDSOC_AI_WDATA_MASK)
/*! @} */
/*! @name VDDSOC_AI_RDATA - VDDSOC_AI_RDATA_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT (0U)
/*! VDDSOC_AI_RDATA - VDDSOC_AI_RDATA
*/
#define ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_SHIFT)) & ANADIG_MISC_VDDSOC_AI_RDATA_VDDSOC_AI_RDATA_MASK)
/*! @} */
/*! @name VDDSOC2PLL_AI_CTRL_1G - VDDSOC2PLL_AI_CTRL_1G_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK (0xFFU)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT (0U)
/*! VDDSOC2PLL_AIADDR_1G - VDDSOC2PLL_AIADDR_1G
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIADDR_1G_MASK)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK (0x100U)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT (8U)
/*! VDDSOC2PLL_AITOGGLE_1G - VDDSOC2PLL_AITOGGLE_1G
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_1G_MASK)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK (0x200U)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT (9U)
/*! VDDSOC2PLL_AITOGGLE_DONE_1G - VDDSOC2PLL_AITOGGLE_DONE_1G
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AITOGGLE_DONE_1G_MASK)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK (0x10000U)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT (16U)
/*! VDDSOC2PLL_AIRWB_1G - VDDSOC2PLL_AIRWB_1G
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_1G_VDDSOC2PLL_AIRWB_1G_MASK)
/*! @} */
/*! @name VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT (0U)
/*! VDDSOC2PLL_AI_WDATA_1G - VDDSOC2PLL_AI_WDATA_1G
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_1G_VDDSOC2PLL_AI_WDATA_1G_MASK)
/*! @} */
/*! @name VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT (0U)
/*! VDDSOC2PLL_AI_RDATA_1G - VDDSOC2PLL_AI_RDATA_1G
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_1G_VDDSOC2PLL_AI_RDATA_1G_MASK)
/*! @} */
/*! @name VDDSOC2PLL_AI_CTRL_AUDIO - VDDSOC_AI_CTRL_AUDIO_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK (0xFFU)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT (0U)
/*! VDDSOC2PLL_AI_ADDR_AUDIO - VDDSOC2PLL_AI_ADDR_AUDIO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AI_ADDR_AUDIO_MASK)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK (0x100U)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT (8U)
/*! VDDSOC2PLL_AITOGGLE_AUDIO - VDDSOC2PLL_AITOGGLE_AUDIO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_AUDIO_MASK)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK (0x200U)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT (9U)
/*! VDDSOC2PLL_AITOGGLE_DONE_AUDIO - VDDSOC2PLL_AITOGGLE_DONE_AUDIO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AITOGGLE_DONE_AUDIO_MASK)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK (0x10000U)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT (16U)
/*! VDDSOC2PLL_AIRWB_AUDIO - VDDSOC_AIRWB
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_AUDIO_VDDSOC2PLL_AIRWB_AUDIO_MASK)
/*! @} */
/*! @name VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC_AI_WDATA_AUDIO_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT (0U)
/*! VDDSOC2PLL_AI_WDATA_AUDIO - VDDSOC2PLL_AI_WDATA_AUDIO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_AUDIO_VDDSOC2PLL_AI_WDATA_AUDIO_MASK)
/*! @} */
/*! @name VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT (0U)
/*! VDDSOC2PLL_AI_RDATA_AUDIO - VDDSOC2PLL_AI_RDATA_AUDIO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_AUDIO_VDDSOC2PLL_AI_RDATA_AUDIO_MASK)
/*! @} */
/*! @name VDDSOC2PLL_AI_CTRL_VIDEO - VDDSOC2PLL_AI_CTRL_VIDEO_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK (0xFFU)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT (0U)
/*! VDDSOC2PLL_AIADDR_VIDEO - VDDSOC2PLL_AIADDR_VIDEO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIADDR_VIDEO_MASK)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK (0x100U)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT (8U)
/*! VDDSOC2PLL_AITOGGLE_VIDEO - VDDSOC2PLL_AITOGGLE_VIDEO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_VIDEO_MASK)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK (0x200U)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT (9U)
/*! VDDSOC2PLL_AITOGGLE_DONE_VIDEO - VDDSOC2PLL_AITOGGLE_DONE_VIDEO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AITOGGLE_DONE_VIDEO_MASK)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK (0x10000U)
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT (16U)
/*! VDDSOC2PLL_AIRWB_VIDEO - VDDSOC2PLL_AIRWB_VIDEO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_CTRL_VIDEO_VDDSOC2PLL_AIRWB_VIDEO_MASK)
/*! @} */
/*! @name VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT (0U)
/*! VDDSOC2PLL_AI_WDATA_VIDEO - VDDSOC2PLL_AI_WDATA_VIDEO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_WDATA_VIDEO_VDDSOC2PLL_AI_WDATA_VIDEO_MASK)
/*! @} */
/*! @name VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT (0U)
/*! VDDSOC2PLL_AI_RDATA_VIDEO - VDDSOC2PLL_AI_RDATA_VIDEO
*/
#define ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_SHIFT)) & ANADIG_MISC_VDDSOC2PLL_AI_RDATA_VIDEO_VDDSOC2PLL_AI_RDATA_VIDEO_MASK)
/*! @} */
/*! @name VDDLPSR_AI_CTRL - VDDSOC_AI_CTRL_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK (0xFFU)
#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT (0U)
/*! VDDLPSR_AI_ADDR - VDDLPSR_AI_ADDR
*/
#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AI_ADDR_MASK)
#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK (0x10000U)
#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT (16U)
/*! VDDLPSR_AIRWB - VDDLPSR_AIRWB
*/
#define ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_CTRL_VDDLPSR_AIRWB_MASK)
/*! @} */
/*! @name VDDLPSR_AI_WDATA - VDDLPSR_AI_WDATA_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT (0U)
/*! VDDLPSR_AI_WDATA - VDD_LPSR_AI_WDATA
*/
#define ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_WDATA_VDDLPSR_AI_WDATA_MASK)
/*! @} */
/*! @name VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT (0U)
/*! VDDLPSR_AI_RDATA_REFTOP - VDDLPSR_AI_RDATA_REFTOP
*/
#define ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_REFTOP_VDDLPSR_AI_RDATA_REFTOP_MASK)
/*! @} */
/*! @name VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT (0U)
/*! VDDLPSR_AI_RDATA_TMPSNS - VDDLPSR_AI_RDATA_TMPSNS
*/
#define ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_SHIFT)) & ANADIG_MISC_VDDLPSR_AI_RDATA_TMPSNS_VDDLPSR_AI_RDATA_TMPSNS_MASK)
/*! @} */
/*! @name VDDLPSR_AI400M_CTRL - VDDLPSR_AI400M_CTRL_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK (0xFFU)
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT (0U)
/*! VDDLPSR_AI400M_ADDR - VDDLPSR_AI400M_ADDR
*/
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_ADDR_MASK)
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK (0x100U)
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT (8U)
/*! VDDLPSR_AITOGGLE_400M - VDDLPSR_AITOGGLE_400M
*/
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_400M_MASK)
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK (0x200U)
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT (9U)
/*! VDDLPSR_AITOGGLE_DONE_400M - VDDLPSR_AITOGGLE_DONE_400M
*/
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AITOGGLE_DONE_400M_MASK)
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK (0x10000U)
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT (16U)
/*! VDDLPSR_AI400M_RWB - VDDLPSR_AI400M_RWB
*/
#define ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_CTRL_VDDLPSR_AI400M_RWB_MASK)
/*! @} */
/*! @name VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT (0U)
/*! VDDLPSR_AI400M_WDATA - VDDLPSR_AI400M_WDATA
*/
#define ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_WDATA_VDDLPSR_AI400M_WDATA_MASK)
/*! @} */
/*! @name VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA_REGISTER */
/*! @{ */
#define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK (0xFFFFFFFFU)
#define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT (0U)
/*! VDDLPSR_AI400M_RDATA - VDDLPSR_AI400M_RDATA
*/
#define ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_SHIFT)) & ANADIG_MISC_VDDLPSR_AI400M_RDATA_VDDLPSR_AI400M_RDATA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ANADIG_MISC_Register_Masks */
/* ANADIG_MISC - Peripheral instance base addresses */
/** Peripheral ANADIG_MISC base address */
#define ANADIG_MISC_BASE (0x40C84000u)
/** Peripheral ANADIG_MISC base pointer */
#define ANADIG_MISC ((ANADIG_MISC_Type *)ANADIG_MISC_BASE)
/** Array initializer of ANADIG_MISC peripheral base addresses */
#define ANADIG_MISC_BASE_ADDRS { ANADIG_MISC_BASE }
/** Array initializer of ANADIG_MISC peripheral base pointers */
#define ANADIG_MISC_BASE_PTRS { ANADIG_MISC }
/*!
* @}
*/ /* end of group ANADIG_MISC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ANADIG_OSC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_OSC_Peripheral_Access_Layer ANADIG_OSC Peripheral Access Layer
* @{
*/
/** ANADIG_OSC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[16];
__IO uint32_t OSC_48M_CTRL; /**< 48MHz RCOSC Control Register, offset: 0x10 */
uint8_t RESERVED_1[12];
__IO uint32_t OSC_24M_CTRL; /**< 24MHz OSC Control Register, offset: 0x20 */
uint8_t RESERVED_2[28];
__I uint32_t OSC_400M_CTRL0; /**< 400MHz RCOSC Control0 Register, offset: 0x40 */
uint8_t RESERVED_3[12];
__IO uint32_t OSC_400M_CTRL1; /**< 400MHz RCOSC Control1 Register, offset: 0x50 */
uint8_t RESERVED_4[12];
__IO uint32_t OSC_400M_CTRL2; /**< 400MHz RCOSC Control2 Register, offset: 0x60 */
uint8_t RESERVED_5[92];
__IO uint32_t OSC_16M_CTRL; /**< 16MHz RCOSC Control Register, offset: 0xC0 */
} ANADIG_OSC_Type;
/* ----------------------------------------------------------------------------
-- ANADIG_OSC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_OSC_Register_Masks ANADIG_OSC Register Masks
* @{
*/
/*! @name OSC_48M_CTRL - 48MHz RCOSC Control Register */
/*! @{ */
#define ANADIG_OSC_OSC_48M_CTRL_TEN_MASK (0x2U)
#define ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT (1U)
/*! TEN - 48MHz RCOSC Enable
* 0b0..Power down
* 0b1..Power up
*/
#define ANADIG_OSC_OSC_48M_CTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_TEN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_TEN_MASK)
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK (0x1000000U)
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT (24U)
/*! RC_48M_DIV2_EN - RCOSC_48M_DIV2 Enable
* 0b0..Disable
* 0b1..Enable
*/
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_EN_MASK)
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK (0x40000000U)
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT (30U)
/*! RC_48M_DIV2_CONTROL_MODE - RCOSC_48M_DIV2 Control Mode
* 0b0..Software mode (default)
* 0b1..GPC mode (Setpoint)
*/
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_DIV2_CONTROL_MODE_MASK)
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK (0x80000000U)
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT (31U)
/*! RC_48M_CONTROL_MODE - 48MHz RCOSC Control Mode
* 0b0..Software mode (default)
* 0b1..GPC mode (Setpoint)
*/
#define ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_48M_CTRL_RC_48M_CONTROL_MODE_MASK)
/*! @} */
/*! @name OSC_24M_CTRL - 24MHz OSC Control Register */
/*! @{ */
#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK (0x1U)
#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT (0U)
/*! BYPASS_CLK - 24MHz OSC Bypass Clock
*/
#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_CLK_MASK)
#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK (0x2U)
#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT (1U)
/*! BYPASS_EN - 24MHz OSC Bypass Enable
* 0b0..Disable
* 0b1..Enable
*/
#define ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_BYPASS_EN_MASK)
#define ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK (0x4U)
#define ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT (2U)
/*! LP_EN - 24MHz OSC Low-Power Mode Enable
* 0b0..High Gain mode (HP)
* 0b1..Low-power mode (LP)
*/
#define ANADIG_OSC_OSC_24M_CTRL_LP_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_LP_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_LP_EN_MASK)
#define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK (0x8U)
#define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT (3U)
/*! OSC_COMP_MODE - 24MHz OSC Comparator Mode
* 0b0..Single-ended mode (default)
* 0b1..Differential mode (test mode)
*/
#define ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_COMP_MODE_MASK)
#define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK (0x10U)
#define ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT (4U)
/*! OSC_EN - 24MHz OSC Enable
* 0b0..Disable
* 0b1..Enable
*/
#define ANADIG_OSC_OSC_24M_CTRL_OSC_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_EN_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_EN_MASK)
#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK (0x80U)
#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT (7U)
/*! OSC_24M_GATE - 24MHz OSC Gate Control
* 0b0..Not Gated
* 0b1..Gated
*/
#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_GATE_MASK)
#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK (0x40000000U)
#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT (30U)
/*! OSC_24M_STABLE - 24MHz OSC Stable
* 0b0..Not Stable
* 0b1..Stable
*/
#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_STABLE_MASK)
#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK (0x80000000U)
#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT (31U)
/*! OSC_24M_CONTROL_MODE - 24MHz OSC Control Mode
* 0b0..Software mode (default)
* 0b1..GPC mode (Setpoint)
*/
#define ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_24M_CTRL_OSC_24M_CONTROL_MODE_MASK)
/*! @} */
/*! @name OSC_400M_CTRL0 - 400MHz RCOSC Control0 Register */
/*! @{ */
#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK (0x80000000U)
#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT (31U)
/*! OSC400M_AI_BUSY - 400MHz OSC AI BUSY
*/
#define ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL0_OSC400M_AI_BUSY_MASK)
/*! @} */
/*! @name OSC_400M_CTRL1 - 400MHz RCOSC Control1 Register */
/*! @{ */
#define ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK (0x1U)
#define ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT (0U)
/*! PWD - Power down control for 400MHz RCOSC
* 0b0..No Power down
* 0b1..Power down
*/
#define ANADIG_OSC_OSC_400M_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_PWD_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_PWD_MASK)
#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK (0x2U)
#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT (1U)
/*! CLKGATE_400MEG - Clock gate control for 400MHz RCOSC
* 0b0..Not Gated
* 0b1..Gated
*/
#define ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_CLKGATE_400MEG_MASK)
#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK (0x80000000U)
#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT (31U)
/*! RC_400M_CONTROL_MODE - 400MHz RCOSC Control mode
* 0b0..Software mode (default)
* 0b1..GPC mode (Setpoint)
*/
#define ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL1_RC_400M_CONTROL_MODE_MASK)
/*! @} */
/*! @name OSC_400M_CTRL2 - 400MHz RCOSC Control2 Register */
/*! @{ */
#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK (0x1U)
#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT (0U)
/*! ENABLE_CLK - Clock enable
* 0b0..Clock is disabled before entering GPC mode
* 0b1..Clock is enabled before entering GPC mode
*/
#define ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_ENABLE_CLK_MASK)
#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK (0x400U)
#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT (10U)
/*! TUNE_BYP - Bypass tuning logic
* 0b0..Use the output of tuning logic to run the oscillator
* 0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator
*/
#define ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_TUNE_BYP_MASK)
#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U)
#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U)
/*! OSC_TUNE_VAL - Oscillator Tune Value
*/
#define ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & ANADIG_OSC_OSC_400M_CTRL2_OSC_TUNE_VAL_MASK)
/*! @} */
/*! @name OSC_16M_CTRL - 16MHz RCOSC Control Register */
/*! @{ */
#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK (0x2U)
#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT (1U)
/*! EN_IRC4M16M - Enable Clock Output
* 0b0..Disable
* 0b1..Enable
*/
#define ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_IRC4M16M_MASK)
#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK (0x8U)
#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT (3U)
/*! EN_POWER_SAVE - Power Save Enable
* 0b0..Disable
* 0b1..Enable
*/
#define ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_EN_POWER_SAVE_MASK)
#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK (0x100U)
#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT (8U)
/*! SOURCE_SEL_16M - Source select
* 0b0..16MHz Oscillator
* 0b1..24MHz Oscillator
*/
#define ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_SOURCE_SEL_16M_MASK)
#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK (0x80000000U)
#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT (31U)
/*! RC_16M_CONTROL_MODE - Control Mode for 16MHz Oscillator
* 0b0..Software mode (default)
* 0b1..GPC mode (Setpoint)
*/
#define ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_SHIFT)) & ANADIG_OSC_OSC_16M_CTRL_RC_16M_CONTROL_MODE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ANADIG_OSC_Register_Masks */
/* ANADIG_OSC - Peripheral instance base addresses */
/** Peripheral ANADIG_OSC base address */
#define ANADIG_OSC_BASE (0x40C84000u)
/** Peripheral ANADIG_OSC base pointer */
#define ANADIG_OSC ((ANADIG_OSC_Type *)ANADIG_OSC_BASE)
/** Array initializer of ANADIG_OSC peripheral base addresses */
#define ANADIG_OSC_BASE_ADDRS { ANADIG_OSC_BASE }
/** Array initializer of ANADIG_OSC peripheral base pointers */
#define ANADIG_OSC_BASE_PTRS { ANADIG_OSC }
/*!
* @}
*/ /* end of group ANADIG_OSC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ANADIG_PLL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_PLL_Peripheral_Access_Layer ANADIG_PLL Peripheral Access Layer
* @{
*/
/** ANADIG_PLL - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[512];
__IO uint32_t ARM_PLL_CTRL; /**< ARM_PLL_CTRL_REGISTER, offset: 0x200 */
uint8_t RESERVED_1[12];
__IO uint32_t SYS_PLL3_CTRL; /**< SYS_PLL3_CTRL_REGISTER, offset: 0x210 */
uint8_t RESERVED_2[12];
__IO uint32_t SYS_PLL3_UPDATE; /**< SYS_PLL3_UPDATE_REGISTER, offset: 0x220 */
uint8_t RESERVED_3[12];
__IO uint32_t SYS_PLL3_PFD; /**< SYS_PLL3_PFD_REGISTER, offset: 0x230 */
uint8_t RESERVED_4[12];
__IO uint32_t SYS_PLL2_CTRL; /**< SYS_PLL2_CTRL_REGISTER, offset: 0x240 */
uint8_t RESERVED_5[12];
__IO uint32_t SYS_PLL2_UPDATE; /**< SYS_PLL2_UPDATE_REGISTER, offset: 0x250 */
uint8_t RESERVED_6[12];
__IO uint32_t SYS_PLL2_SS; /**< SYS_PLL2_SS_REGISTER, offset: 0x260 */
uint8_t RESERVED_7[12];
__IO uint32_t SYS_PLL2_PFD; /**< SYS_PLL2_PFD_REGISTER, offset: 0x270 */
uint8_t RESERVED_8[44];
__IO uint32_t SYS_PLL2_MFD; /**< SYS_PLL2_MFD_REGISTER, offset: 0x2A0 */
uint8_t RESERVED_9[12];
__IO uint32_t SYS_PLL1_SS; /**< SYS_PLL1_SS_REGISTER, offset: 0x2B0 */
uint8_t RESERVED_10[12];
__IO uint32_t SYS_PLL1_CTRL; /**< SYS_PLL1_CTRL_REGISTER, offset: 0x2C0 */
uint8_t RESERVED_11[12];
__IO uint32_t SYS_PLL1_DENOMINATOR; /**< SYS_PLL1_DENOMINATOR_REGISTER, offset: 0x2D0 */
uint8_t RESERVED_12[12];
__IO uint32_t SYS_PLL1_NUMERATOR; /**< SYS_PLL1_NUMERATOR_REGISTER, offset: 0x2E0 */
uint8_t RESERVED_13[12];
__IO uint32_t SYS_PLL1_DIV_SELECT; /**< SYS_PLL1_DIV_SELECT_REGISTER, offset: 0x2F0 */
uint8_t RESERVED_14[12];
__IO uint32_t PLL_AUDIO_CTRL; /**< PLL_AUDIO_CTRL_REGISTER, offset: 0x300 */
uint8_t RESERVED_15[12];
__IO uint32_t PLL_AUDIO_SS; /**< PLL_AUDIO_SS_REGISTER, offset: 0x310 */
uint8_t RESERVED_16[12];
__IO uint32_t PLL_AUDIO_DENOMINATOR; /**< PLL_AUDIO_DENOMINATOR_REGISTER, offset: 0x320 */
uint8_t RESERVED_17[12];
__IO uint32_t PLL_AUDIO_NUMERATOR; /**< PLL_AUDIO_NUMERATOR_REGISTER, offset: 0x330 */
uint8_t RESERVED_18[12];
__IO uint32_t PLL_AUDIO_DIV_SELECT; /**< PLL_AUDIO_DIV_SELECT_REGISTER, offset: 0x340 */
uint8_t RESERVED_19[12];
__IO uint32_t PLL_VIDEO_CTRL; /**< PLL_VIDEO_CTRL_REGISTER, offset: 0x350 */
uint8_t RESERVED_20[12];
__IO uint32_t PLL_VIDEO_SS; /**< PLL_VIDEO_SS_REGISTER, offset: 0x360 */
uint8_t RESERVED_21[12];
__IO uint32_t PLL_VIDEO_DENOMINATOR; /**< PLL_VIDEO_DENOMINATOR_REGISTER, offset: 0x370 */
uint8_t RESERVED_22[12];
__IO uint32_t PLL_VIDEO_NUMERATOR; /**< PLL_VIDEO_NUMERATOR_REGISTER, offset: 0x380 */
uint8_t RESERVED_23[12];
__IO uint32_t PLL_VIDEO_DIV_SELECT; /**< PLL_VIDEO_DIV_SELECT_REGISTER, offset: 0x390 */
} ANADIG_PLL_Type;
/* ----------------------------------------------------------------------------
-- ANADIG_PLL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_PLL_Register_Masks ANADIG_PLL Register Masks
* @{
*/
/*! @name ARM_PLL_CTRL - ARM_PLL_CTRL_REGISTER */
/*! @{ */
#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK (0xFFU)
#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT (0U)
/*! DIV_SELECT - DIV_SELECT
*/
#define ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_DIV_SELECT_MASK)
#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK (0x1000U)
#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT (12U)
/*! HOLD_RING_OFF - PLL Start up initialization
* 0b0..Normal operation
* 0b1..Initialize PLL start up
*/
#define ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_HOLD_RING_OFF_MASK)
#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK (0x2000U)
#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT (13U)
/*! POWERUP - Powers up the PLL.
* 0b1..Power Up the PLL
* 0b0..Power down the PLL
*/
#define ANADIG_PLL_ARM_PLL_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POWERUP_MASK)
#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK (0x4000U)
#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT (14U)
/*! ENABLE_CLK - Enable the clock output.
* 0b0..Disable the clock
* 0b1..Enable the clock
*/
#define ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ENABLE_CLK_MASK)
#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK (0x18000U)
#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT (15U)
/*! POST_DIV_SEL - POST_DIV_SEL
* 0b00..Divide by 2
* 0b01..Divide by 4
* 0b10..Divide by 8
* 0b11..Divide by 1
*/
#define ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_POST_DIV_SEL_MASK)
#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK (0x20000U)
#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT (17U)
/*! BYPASS - Bypass the pll.
* 0b1..Bypass Mode
* 0b0..Function mode
*/
#define ANADIG_PLL_ARM_PLL_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_BYPASS_MASK)
#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK (0x20000000U)
#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT (29U)
/*! ARM_PLL_STABLE - ARM_PLL_STABLE
* 0b1..ARM PLL is stable
* 0b0..ARM PLL is not stable
*/
#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_STABLE_MASK)
#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK (0x40000000U)
#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT (30U)
/*! ARM_PLL_GATE - ARM_PLL_GATE
* 0b1..Clock is gated
* 0b0..Clock is not gated
*/
#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_GATE_MASK)
#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK (0x80000000U)
#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT (31U)
/*! ARM_PLL_CONTROL_MODE - pll_arm_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PLL_ARM_PLL_CTRL_ARM_PLL_CONTROL_MODE_MASK)
/*! @} */
/*! @name SYS_PLL3_CTRL - SYS_PLL3_CTRL_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK (0x8U)
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT (3U)
/*! SYS_PLL3_DIV2 - SYS PLL3 DIV2 gate
*/
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_MASK)
#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK (0x10U)
#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT (4U)
/*! PLL_REG_EN - Enable Internal PLL Regulator
*/
#define ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_PLL_REG_EN_MASK)
#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK (0x800U)
#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT (11U)
/*! HOLD_RING_OFF - PLL Start up initialization
* 0b0..Normal operation
* 0b1..Initialize PLL start up
*/
#define ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_HOLD_RING_OFF_MASK)
#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK (0x2000U)
#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT (13U)
/*! ENABLE_CLK - Enable the clock output.
* 0b0..Disable the clock
* 0b1..Enable the clock
*/
#define ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_ENABLE_CLK_MASK)
#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK (0x10000U)
#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT (16U)
/*! BYPASS - BYPASS
* 0b1..Bypass Mode
* 0b0..Function mode
*/
#define ANADIG_PLL_SYS_PLL3_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_BYPASS_MASK)
#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK (0x200000U)
#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT (21U)
/*! POWERUP - Powers up the PLL.
* 0b1..Power Up the PLL
* 0b0..Power down the PLL
*/
#define ANADIG_PLL_SYS_PLL3_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_POWERUP_MASK)
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK (0x10000000U)
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT (28U)
/*! SYS_PLL3_DIV2_CONTROL_MODE - SYS_PLL3_DIV2_CONTROL_MODE
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_DIV2_CONTROL_MODE_MASK)
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK (0x20000000U)
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT (29U)
/*! SYS_PLL3_STABLE - SYS_PLL3_STABLE
*/
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK (0x40000000U)
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT (30U)
/*! SYS_PLL3_GATE - SYS_PLL3_GATE
* 0b1..Clock is gated
* 0b0..Clock is not gated
*/
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_GATE_MASK)
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK (0x80000000U)
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT (31U)
/*! SYS_PLL3_CONTROL_MODE - SYS_PLL3_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_CTRL_SYS_PLL3_CONTROL_MODE_MASK)
/*! @} */
/*! @name SYS_PLL3_UPDATE - SYS_PLL3_UPDATE_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK (0x2U)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT (1U)
/*! PFD0_UPDATE - PFD0_OVERRIDE
*/
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_UPDATE_MASK)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK (0x4U)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT (2U)
/*! PFD1_UPDATE - PFD1_OVERRIDE
*/
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_UPDATE_MASK)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK (0x8U)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT (3U)
/*! PFD2_UPDATE - PFD2_OVERRIDE
*/
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD2_UPDATE_MASK)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK (0x10U)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT (4U)
/*! PFD3_UPDATE - PFD3_UPDATE
*/
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_UPDATE_MASK)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
/*! PFD0_CONTROL_MODE - pfd0_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD0_CONTROL_MODE_MASK)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
/*! PFD1_CONTROL_MODE - pfd1_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD1_CONTROL_MODE_MASK)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK (0x80U)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT (7U)
/*! PDF2_CONTROL_MODE - pdf2_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PDF2_CONTROL_MODE_MASK)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
/*! PFD3_CONTROL_MODE - pfd3_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL3_UPDATE_PFD3_CONTROL_MODE_MASK)
/*! @} */
/*! @name SYS_PLL3_PFD - SYS_PLL3_PFD_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK (0x3FU)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT (0U)
/*! PFD0_FRAC - PFD0_FRAC
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_FRAC_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK (0x40U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT (6U)
/*! PFD0_STABLE - PFD0_STABLE
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
/*! PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE
* 0b1..Fractional divider clock (reference ref_pfd0) is off (power savings
* 0b0..ref_pfd0 fractional divider clock is enabled
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD0_DIV1_CLKGATE_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK (0x3F00U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT (8U)
/*! PFD1_FRAC - PFD1_FRAC
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_FRAC_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK (0x4000U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT (14U)
/*! PFD1_STABLE - PFD1_STABLE
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
/*! PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE
* 0b1..Fractional divider clock (reference ref_pfd1) is off (power savings)
* 0b0..ref_pfd1 fractional divider clock is enabled
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD1_DIV1_CLKGATE_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK (0x3F0000U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT (16U)
/*! PFD2_FRAC - PFD2_FRAC
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_FRAC_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK (0x400000U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT (22U)
/*! PFD2_STABLE - PFD2_STABLE
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
/*! PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE
* 0b1..Fractional divider clock (reference ref_pfd2) is off (power savings)
* 0b0..ref_pfd2 fractional divider clock is enabled
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD2_DIV1_CLKGATE_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK (0x3F000000U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT (24U)
/*! PFD3_FRAC - PFD3_FRAC
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_FRAC_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK (0x40000000U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT (30U)
/*! PFD3_STABLE - PFD3_STABLE
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
/*! PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE
* 0b1..Fractional divider clock (reference ref_pfd3) is off (power savings)
* 0b0..ref_pfd3 fractional divider clock is enabled
*/
#define ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL3_PFD_PFD3_DIV1_CLKGATE_MASK)
/*! @} */
/*! @name SYS_PLL2_CTRL - SYS_PLL2_CTRL_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK (0x8U)
#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT (3U)
/*! PLL_REG_EN - Enable Internal PLL Regulator
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_REG_EN_MASK)
#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK (0x800U)
#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT (11U)
/*! HOLD_RING_OFF - PLL Start up initialization
* 0b0..Normal operation
* 0b1..Initialize PLL start up
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_HOLD_RING_OFF_MASK)
#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK (0x2000U)
#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT (13U)
/*! ENABLE_CLK - Enable the clock output.
* 0b0..Disable the clock
* 0b1..Enable the clock
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_ENABLE_CLK_MASK)
#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK (0x10000U)
#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT (16U)
/*! BYPASS - Bypass the pll.
* 0b1..Bypass Mode
* 0b0..Function mode
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_BYPASS_MASK)
#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK (0x20000U)
#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT (17U)
/*! DITHER_ENABLE - DITHER_ENABLE
* 0b0..Disable Dither
* 0b1..Enable Dither
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_DITHER_ENABLE_MASK)
#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK (0x40000U)
#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT (18U)
/*! PFD_OFFSET_EN - PFD_OFFSET_EN
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PFD_OFFSET_EN_MASK)
#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK (0x80000U)
#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT (19U)
/*! PLL_DDR_OVERRIDE - PLL_DDR_OVERRIDE
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_PLL_DDR_OVERRIDE_MASK)
#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK (0x800000U)
#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT (23U)
/*! POWERUP - Powers up the PLL.
* 0b1..Power Up the PLL
* 0b0..Power down the PLL
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_POWERUP_MASK)
#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK (0x20000000U)
#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT (29U)
/*! SYS_PLL2_STABLE - SYS_PLL2_STABLE
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK (0x40000000U)
#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT (30U)
/*! SYS_PLL2_GATE - SYS_PLL2_GATE
* 0b1..Clock is gated
* 0b0..Clock is not gated
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_GATE_MASK)
#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK (0x80000000U)
#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT (31U)
/*! SYS_PLL2_CONTROL_MODE - SYS_PLL2_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_CTRL_SYS_PLL2_CONTROL_MODE_MASK)
/*! @} */
/*! @name SYS_PLL2_UPDATE - SYS_PLL2_UPDATE_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK (0x2U)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT (1U)
/*! PFD0_UPDATE - PFD0_UPDATE
*/
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_UPDATE_MASK)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK (0x4U)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT (2U)
/*! PFD1_UPDATE - PFD1_UPDATE
*/
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_UPDATE_MASK)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK (0x8U)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT (3U)
/*! PFD2_UPDATE - PFD2_UPDATE
*/
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_UPDATE_MASK)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK (0x10U)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT (4U)
/*! PFD3_UPDATE - PFD3_UPDATE
*/
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_UPDATE_MASK)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK (0x20U)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT (5U)
/*! PFD0_CONTROL_MODE - pfd0_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD0_CONTROL_MODE_MASK)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK (0x40U)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT (6U)
/*! PFD1_CONTROL_MODE - pfd1_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD1_CONTROL_MODE_MASK)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK (0x80U)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT (7U)
/*! PFD2_CONTROL_MODE - pfd2_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD2_CONTROL_MODE_MASK)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK (0x100U)
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT (8U)
/*! PFD3_CONTROL_MODE - pfd3_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL2_UPDATE_PFD3_CONTROL_MODE_MASK)
/*! @} */
/*! @name SYS_PLL2_SS - SYS_PLL2_SS_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL2_SS_STEP_MASK (0x7FFFU)
#define ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT (0U)
/*! STEP - STEP
*/
#define ANADIG_PLL_SYS_PLL2_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STEP_MASK)
#define ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK (0x8000U)
#define ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT (15U)
/*! ENABLE - ENABLE
* 0b1..Enable Spread Spectrum
* 0b0..Disable Spread Spectrum
*/
#define ANADIG_PLL_SYS_PLL2_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_ENABLE_MASK)
#define ANADIG_PLL_SYS_PLL2_SS_STOP_MASK (0xFFFF0000U)
#define ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT (16U)
/*! STOP - STOP
*/
#define ANADIG_PLL_SYS_PLL2_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL2_SS_STOP_MASK)
/*! @} */
/*! @name SYS_PLL2_PFD - SYS_PLL2_PFD_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK (0x3FU)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT (0U)
/*! PFD0_FRAC - PFD0_FRAC
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_FRAC_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK (0x40U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT (6U)
/*! PFD0_STABLE - PFD0_STABLE
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK (0x80U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT (7U)
/*! PFD0_DIV1_CLKGATE - PFD0_DIV1_CLKGATE
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD0_DIV1_CLKGATE_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK (0x3F00U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT (8U)
/*! PFD1_FRAC - PFD1_FRAC
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_FRAC_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK (0x4000U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT (14U)
/*! PFD1_STABLE - PFD1_STABLE
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK (0x8000U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT (15U)
/*! PFD1_DIV1_CLKGATE - PFD1_DIV1_CLKGATE
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD1_DIV1_CLKGATE_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK (0x3F0000U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT (16U)
/*! PFD2_FRAC - PFD2_FRAC
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_FRAC_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK (0x400000U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT (22U)
/*! PFD2_STABLE - PFD2_STABLE
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK (0x800000U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT (23U)
/*! PFD2_DIV1_CLKGATE - PFD2_DIV1_CLKGATE
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD2_DIV1_CLKGATE_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK (0x3F000000U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT (24U)
/*! PFD3_FRAC - PFD3_FRAC
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_FRAC_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK (0x40000000U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT (30U)
/*! PFD3_STABLE - PFD3_STABLE
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK (0x80000000U)
#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT (31U)
/*! PFD3_DIV1_CLKGATE - PFD3_DIV1_CLKGATE
*/
#define ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_SHIFT)) & ANADIG_PLL_SYS_PLL2_PFD_PFD3_DIV1_CLKGATE_MASK)
/*! @} */
/*! @name SYS_PLL2_MFD - SYS_PLL2_MFD_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK (0x3FFFFFFFU)
#define ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT (0U)
/*! MFD - Denominator
*/
#define ANADIG_PLL_SYS_PLL2_MFD_MFD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL2_MFD_MFD_SHIFT)) & ANADIG_PLL_SYS_PLL2_MFD_MFD_MASK)
/*! @} */
/*! @name SYS_PLL1_SS - SYS_PLL1_SS_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL1_SS_STEP_MASK (0x7FFFU)
#define ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT (0U)
/*! STEP - STEP
*/
#define ANADIG_PLL_SYS_PLL1_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STEP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STEP_MASK)
#define ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK (0x8000U)
#define ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT (15U)
/*! ENABLE - ENABLE
* 0b1..Enable Spread Spectrum
* 0b0..Disable Spread Spectrum
*/
#define ANADIG_PLL_SYS_PLL1_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_ENABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_ENABLE_MASK)
#define ANADIG_PLL_SYS_PLL1_SS_STOP_MASK (0xFFFF0000U)
#define ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT (16U)
/*! STOP - STOP
*/
#define ANADIG_PLL_SYS_PLL1_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_SS_STOP_SHIFT)) & ANADIG_PLL_SYS_PLL1_SS_STOP_MASK)
/*! @} */
/*! @name SYS_PLL1_CTRL - SYS_PLL1_CTRL_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK (0x2000U)
#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT (13U)
/*! ENABLE_CLK - ENABLE_CLK
*/
#define ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_ENABLE_CLK_MASK)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK (0x4000U)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT (14U)
/*! SYS_PLL1_GATE - SYS_PLL1_GATE
* 0b1..Gate the output
* 0b0..No gate
*/
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_GATE_MASK)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK (0x2000000U)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT (25U)
/*! SYS_PLL1_DIV2 - SYS_PLL1_DIV2
*/
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_MASK)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK (0x4000000U)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT (26U)
/*! SYS_PLL1_DIV5 - SYS_PLL1_DIV5
*/
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_MASK)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK (0x8000000U)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT (27U)
/*! SYS_PLL1_DIV5_CONTROL_MODE - SYS_PLL1_DIV5_CONTROL_MODE
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV5_CONTROL_MODE_MASK)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK (0x10000000U)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT (28U)
/*! SYS_PLL1_DIV2_CONTROL_MODE - SYS_PLL1_DIV2_CONTROL_MODE
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_DIV2_CONTROL_MODE_MASK)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK (0x20000000U)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT (29U)
/*! SYS_PLL1_STABLE - SYS_PLL1_STABLE
*/
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_STABLE_MASK)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK (0x40000000U)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT (30U)
/*! SYS_PLL1_AI_BUSY - SYS_PLL1_AI_BUSY
*/
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_AI_BUSY_MASK)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK (0x80000000U)
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT (31U)
/*! SYS_PLL1_CONTROL_MODE - SYS_PLL1_CONTROL_MODE
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_SHIFT)) & ANADIG_PLL_SYS_PLL1_CTRL_SYS_PLL1_CONTROL_MODE_MASK)
/*! @} */
/*! @name SYS_PLL1_DENOMINATOR - SYS_PLL1_DENOMINATOR_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT (0U)
/*! DENOM - DENOM
*/
#define ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_SYS_PLL1_DENOMINATOR_DENOM_MASK)
/*! @} */
/*! @name SYS_PLL1_NUMERATOR - SYS_PLL1_NUMERATOR_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT (0U)
/*! NUM - NUM
*/
#define ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_SYS_PLL1_NUMERATOR_NUM_MASK)
/*! @} */
/*! @name SYS_PLL1_DIV_SELECT - SYS_PLL1_DIV_SELECT_REGISTER */
/*! @{ */
#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT (0U)
/*! DIV_SELECT - DIV_SELECT
*/
#define ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_SYS_PLL1_DIV_SELECT_DIV_SELECT_MASK)
/*! @} */
/*! @name PLL_AUDIO_CTRL - PLL_AUDIO_CTRL_REGISTER */
/*! @{ */
#define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK (0x2000U)
#define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT (13U)
/*! ENABLE_CLK - ENABLE_CLK
*/
#define ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_ENABLE_CLK_MASK)
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK (0x4000U)
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT (14U)
/*! PLL_AUDIO_GATE - PLL_AUDIO_GATE
* 0b1..Gate the output
* 0b0..No gate
*/
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_GATE_MASK)
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK (0x20000000U)
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT (29U)
/*! PLL_AUDIO_STABLE - PLL_AUDIO_STABLE
*/
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_STABLE_MASK)
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK (0x40000000U)
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT (30U)
/*! PLL_AUDIO_AI_BUSY - pll_audio_ai_busy
*/
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_AI_BUSY_MASK)
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK (0x80000000U)
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT (31U)
/*! PLL_AUDIO_CONTROL_MODE - pll_audio_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_CTRL_PLL_AUDIO_CONTROL_MODE_MASK)
/*! @} */
/*! @name PLL_AUDIO_SS - PLL_AUDIO_SS_REGISTER */
/*! @{ */
#define ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK (0x7FFFU)
#define ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT (0U)
/*! STEP - STEP
*/
#define ANADIG_PLL_PLL_AUDIO_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STEP_MASK)
#define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK (0x8000U)
#define ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT (15U)
/*! ENABLE - ENABLE
* 0b1..Enable Spread Spectrum
* 0b0..Disable Spread Spectrum
*/
#define ANADIG_PLL_PLL_AUDIO_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_ENABLE_MASK)
#define ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK (0xFFFF0000U)
#define ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT (16U)
/*! STOP - STOP
*/
#define ANADIG_PLL_PLL_AUDIO_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_AUDIO_SS_STOP_MASK)
/*! @} */
/*! @name PLL_AUDIO_DENOMINATOR - PLL_AUDIO_DENOMINATOR_REGISTER */
/*! @{ */
#define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT (0U)
/*! DENOM - DENOM
*/
#define ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DENOMINATOR_DENOM_MASK)
/*! @} */
/*! @name PLL_AUDIO_NUMERATOR - PLL_AUDIO_NUMERATOR_REGISTER */
/*! @{ */
#define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT (0U)
/*! NUM - NUM
*/
#define ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_AUDIO_NUMERATOR_NUM_MASK)
/*! @} */
/*! @name PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT_REGISTER */
/*! @{ */
#define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK (0x7FU)
#define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT (0U)
/*! PLL_AUDIO_DIV_SELECT - PLL_AUDIO_DIV_SELECT
*/
#define ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_AUDIO_DIV_SELECT_PLL_AUDIO_DIV_SELECT_MASK)
/*! @} */
/*! @name PLL_VIDEO_CTRL - PLL_VIDEO_CTRL_REGISTER */
/*! @{ */
#define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK (0x2000U)
#define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT (13U)
/*! ENABLE_CLK - ENABLE_CLK
*/
#define ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_ENABLE_CLK_MASK)
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK (0x4000U)
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT (14U)
/*! PLL_VIDEO_GATE - PLL_VIDEO_GATE
* 0b1..Gate the output
* 0b0..No gate
*/
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_GATE_MASK)
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK (0x1000000U)
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT (24U)
/*! PLL_VIDEO_COUNTER_CLR - pll_video_counter_clr
*/
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_COUNTER_CLR_MASK)
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK (0x20000000U)
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT (29U)
/*! PLL_VIDEO_STABLE - PLL_VIDEO_STABLE
*/
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_STABLE_MASK)
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK (0x40000000U)
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT (30U)
/*! PLL_VIDEO_AI_BUSY - pll_video_ai_busy
*/
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_AI_BUSY_MASK)
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK (0x80000000U)
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT (31U)
/*! PLL_VIDEO_CONTROL_MODE - pll_video_control_mode
* 0b0..Software Mode (Default)
* 0b1..GPC Mode
*/
#define ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_CTRL_PLL_VIDEO_CONTROL_MODE_MASK)
/*! @} */
/*! @name PLL_VIDEO_SS - PLL_VIDEO_SS_REGISTER */
/*! @{ */
#define ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK (0x7FFFU)
#define ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT (0U)
/*! STEP - STEP
*/
#define ANADIG_PLL_PLL_VIDEO_SS_STEP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STEP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STEP_MASK)
#define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK (0x8000U)
#define ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT (15U)
/*! ENABLE - ENABLE
* 0b1..Enable Spread Spectrum
* 0b0..Disable Spread Spectrum
*/
#define ANADIG_PLL_PLL_VIDEO_SS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_ENABLE_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_ENABLE_MASK)
#define ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK (0xFFFF0000U)
#define ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT (16U)
/*! STOP - STOP
*/
#define ANADIG_PLL_PLL_VIDEO_SS_STOP(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_SS_STOP_SHIFT)) & ANADIG_PLL_PLL_VIDEO_SS_STOP_MASK)
/*! @} */
/*! @name PLL_VIDEO_DENOMINATOR - PLL_VIDEO_DENOMINATOR_REGISTER */
/*! @{ */
#define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT (0U)
/*! DENOM - DENOM
*/
#define ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DENOMINATOR_DENOM_MASK)
/*! @} */
/*! @name PLL_VIDEO_NUMERATOR - PLL_VIDEO_NUMERATOR_REGISTER */
/*! @{ */
#define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT (0U)
/*! NUM - NUM
*/
#define ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_SHIFT)) & ANADIG_PLL_PLL_VIDEO_NUMERATOR_NUM_MASK)
/*! @} */
/*! @name PLL_VIDEO_DIV_SELECT - PLL_VIDEO_DIV_SELECT_REGISTER */
/*! @{ */
#define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK (0x7FU)
#define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT (0U)
/*! DIV_SELECT - DIV_SELECT
*/
#define ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_SHIFT)) & ANADIG_PLL_PLL_VIDEO_DIV_SELECT_DIV_SELECT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ANADIG_PLL_Register_Masks */
/* ANADIG_PLL - Peripheral instance base addresses */
/** Peripheral ANADIG_PLL base address */
#define ANADIG_PLL_BASE (0x40C84000u)
/** Peripheral ANADIG_PLL base pointer */
#define ANADIG_PLL ((ANADIG_PLL_Type *)ANADIG_PLL_BASE)
/** Array initializer of ANADIG_PLL peripheral base addresses */
#define ANADIG_PLL_BASE_ADDRS { ANADIG_PLL_BASE }
/** Array initializer of ANADIG_PLL peripheral base pointers */
#define ANADIG_PLL_BASE_PTRS { ANADIG_PLL }
/*!
* @}
*/ /* end of group ANADIG_PLL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ANADIG_PMU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_PMU_Peripheral_Access_Layer ANADIG_PMU Peripheral Access Layer
* @{
*/
/** ANADIG_PMU - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[1280];
__IO uint32_t PMU_LDO_PLL; /**< PMU_LDO_PLL_REGISTER, offset: 0x500 */
uint8_t RESERVED_1[76];
__IO uint32_t PMU_BIAS_CTRL; /**< PMU_BIAS_CTRL_REGISTER, offset: 0x550 */
uint8_t RESERVED_2[12];
__IO uint32_t PMU_BIAS_CTRL2; /**< PMU_BIAS_CTRL2_REGISTER, offset: 0x560 */
uint8_t RESERVED_3[12];
__IO uint32_t PMU_REF_CTRL; /**< PMU_REF_CTRL_REGISTER, offset: 0x570 */
uint8_t RESERVED_4[12];
__IO uint32_t PMU_POWER_DETECT_CTRL; /**< PMU_POWER_DETECT_CTRL_REGISTER, offset: 0x580 */
uint8_t RESERVED_5[124];
__IO uint32_t LDO_PLL_ENABLE_SP; /**< LDO_PLL_ENABLE_SP_REGISTER, offset: 0x600 */
uint8_t RESERVED_6[12];
__IO uint32_t LDO_LPSR_ANA_ENABLE_SP; /**< LDO_LPSR_ANA_ENABLE_SP_REGISTER, offset: 0x610 */
uint8_t RESERVED_7[12];
__IO uint32_t LDO_LPSR_ANA_LP_MODE_SP; /**< LDO_LPSR_ANA_LP_MODE_SP_REGISTER, offset: 0x620 */
uint8_t RESERVED_8[12];
__IO uint32_t LDO_LPSR_ANA_TRACKING_EN_SP; /**< LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER, offset: 0x630 */
uint8_t RESERVED_9[12];
__IO uint32_t LDO_LPSR_ANA_BYPASS_EN_SP; /**< LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER, offset: 0x640 */
uint8_t RESERVED_10[12];
__IO uint32_t LDO_LPSR_ANA_STBY_EN_SP; /**< LDO_LPSR_ANA_STBY_EN_SP_REGISTER, offset: 0x650 */
uint8_t RESERVED_11[12];
__IO uint32_t LDO_LPSR_DIG_ENABLE_SP; /**< LDO_LPSR_DIG_ENABLE_SP_REGISTER, offset: 0x660 */
uint8_t RESERVED_12[12];
__IO uint32_t LDO_LPSR_DIG_TRG_SP0; /**< LDO_LPSR_DIG_TRG_SP0_REGISTER, offset: 0x670 */
uint8_t RESERVED_13[12];
__IO uint32_t LDO_LPSR_DIG_TRG_SP1; /**< LDO_LPSR_DIG_TRG_SP1_REGISTER, offset: 0x680 */
uint8_t RESERVED_14[12];
__IO uint32_t LDO_LPSR_DIG_TRG_SP2; /**< LDO_LPSR_DIG_TRG_SP2_REGISTER, offset: 0x690 */
uint8_t RESERVED_15[12];
__IO uint32_t LDO_LPSR_DIG_TRG_SP3; /**< LDO_LPSR_DIG_TRG_SP3_REGISTER, offset: 0x6A0 */
uint8_t RESERVED_16[12];
__IO uint32_t LDO_LPSR_DIG_LP_MODE_SP; /**< LDO_LPSR_DIG_LP_MODE_SP_REGISTER, offset: 0x6B0 */
uint8_t RESERVED_17[12];
__IO uint32_t LDO_LPSR_DIG_TRACKING_EN_SP; /**< LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER, offset: 0x6C0 */
uint8_t RESERVED_18[12];
__IO uint32_t LDO_LPSR_DIG_BYPASS_EN_SP; /**< LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER, offset: 0x6D0 */
uint8_t RESERVED_19[12];
__IO uint32_t LDO_LPSR_DIG_STBY_EN_SP; /**< LDO_LPSR_DIG_STBY_EN_SP_REGISTER, offset: 0x6E0 */
uint8_t RESERVED_20[12];
__IO uint32_t BANDGAP_ENABLE_SP; /**< BANDGAP_ENABLE_SP_REGISTER, offset: 0x6F0 */
uint8_t RESERVED_21[12];
__IO uint32_t FBB_M7_ENABLE_SP; /**< FBB_M7_ENABLE_SP_REGISTER, offset: 0x700 */
uint8_t RESERVED_22[12];
__IO uint32_t RBB_SOC_ENABLE_SP; /**< RBB_SOC_ENABLE_SP_REGISTER, offset: 0x710 */
uint8_t RESERVED_23[12];
__IO uint32_t RBB_LPSR_ENABLE_SP; /**< RBB_LPSR_ENABLE_SP_REGISTER, offset: 0x720 */
uint8_t RESERVED_24[12];
__IO uint32_t BANDGAP_STBY_EN_SP; /**< BANDGAP_STBY_EN_SP_REGISTER, offset: 0x730 */
uint8_t RESERVED_25[12];
__IO uint32_t PLL_LDO_STBY_EN_SP; /**< PLL_LDO_STBY_EN_SP_REGISTER, offset: 0x740 */
uint8_t RESERVED_26[12];
__IO uint32_t FBB_M7_STBY_EN_SP; /**< FBB_M7_STBY_EN_SP_REGISTER, offset: 0x750 */
uint8_t RESERVED_27[12];
__IO uint32_t RBB_SOC_STBY_EN_SP; /**< RBB_SOC_STBY_EN_SP_REGISTER, offset: 0x760 */
uint8_t RESERVED_28[12];
__IO uint32_t RBB_LPSR_STBY_EN_SP; /**< RBB_LPSR_STBY_EN_SP_REGISTER, offset: 0x770 */
uint8_t RESERVED_29[12];
__IO uint32_t FBB_M7_CONFIGURE; /**< FBB_M7_CONFIGURE_REGISTER, offset: 0x780 */
uint8_t RESERVED_30[12];
__IO uint32_t RBB_LPSR_CONFIGURE; /**< RBB_LPSR_CONFIGURE_REGISTER, offset: 0x790 */
uint8_t RESERVED_31[12];
__IO uint32_t RBB_SOC_CONFIGURE; /**< RBB_SOC_CONFIGURE_REGISTER, offset: 0x7A0 */
uint8_t RESERVED_32[12];
__I uint32_t REFTOP_OTP_TRIM_VALUE; /**< REFTOP_OTP_TRIM_VALUE_REGISTER, offset: 0x7B0 */
uint8_t RESERVED_33[28];
__I uint32_t LPSR_1P8_LDO_OTP_TRIM_VALUE; /**< LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER, offset: 0x7D0 */
} ANADIG_PMU_Type;
/* ----------------------------------------------------------------------------
-- ANADIG_PMU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_PMU_Register_Masks ANADIG_PMU Register Masks
* @{
*/
/*! @name PMU_LDO_PLL - PMU_LDO_PLL_REGISTER */
/*! @{ */
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK (0x1U)
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT (0U)
/*! LDO_PLL_ENABLE - LDO_PLL_ENABLE
*/
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_ENABLE_MASK)
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK (0x2U)
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT (1U)
/*! LDO_PLL_CONTROL_MODE - LDO_PLL_CONTROL_MODE
* 0b0..SW Control
* 0b1..HW Control
*/
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_CONTROL_MODE_MASK)
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK (0x10000U)
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT (16U)
/*! LDO_PLL_AI_TOGGLE - ldo_pll_ai_toggle
*/
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_TOGGLE_MASK)
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK (0x40000000U)
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT (30U)
/*! LDO_PLL_AI_BUSY - ldo_pll_busy
*/
#define ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_LDO_PLL_LDO_PLL_AI_BUSY_MASK)
/*! @} */
/*! @name PMU_BIAS_CTRL - PMU_BIAS_CTRL_REGISTER */
/*! @{ */
#define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK (0x1FFFU)
#define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT (0U)
/*! WB_CFG_1P8 - wb_cfg_1p8
*/
#define ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_CFG_1P8_MASK)
#define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK (0x4000U)
#define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT (14U)
/*! WB_VDD_SEL_1P8 - wb_vdd_sel_1p8
* 0b0..VDD_LV1
* 0b1..VDD_LV2
*/
#define ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL_WB_VDD_SEL_1P8_MASK)
/*! @} */
/*! @name PMU_BIAS_CTRL2 - PMU_BIAS_CTRL2_REGISTER */
/*! @{ */
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK (0x3FEU)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT (1U)
/*! WB_TST_MD - TMOD_wb_tst_md_1p8
*/
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_MD_MASK)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK (0x1C00U)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT (10U)
/*! WB_PWR_SW_EN_1P8 - MODSEL_wb_tst_md_1p8
* 0b001..No BB
* 0b010..BB
* 0b100..BB
*/
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_PWR_SW_EN_1P8_MASK)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK (0x1FE000U)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT (13U)
/*! WB_ADJ_1P8 - wb_adj_1p8
* 0b00000000..Cref= 0fF Cspl= 0fF DeltaC= 0fF
* 0b00000001..Cref= 0fF Cspl= 30fF DeltaC= -30fF
* 0b00000010..Cref= 0fF Cspl= 43fF DeltaC= -43fF
* 0b00000011..Cref= 0fF Cspl= 62fF DeltaC=-62fF
* 0b00000100..Cref= 0fF Cspl=105fF DeltaC=-105fF
* 0b00000101..Cref= 30fF Cspl= 0fF DeltaC= 30fF
* 0b00000110..Cref= 30fF Cspl= 43fF DeltaC= -12fF
* 0b00000111..Cref= 30fF Cspl=105fF DeltaC= -75fF
* 0b00001000..Cref= 43fF Cspl= 0fF DeltaC= 43fF
* 0b00001001..Cref= 43fF Cspl= 30fF DeltaC= 13fF
* 0b00001010..Cref= 43fF Cspl= 62fF DeltaC= -19fF
* 0b00001011..Cref= 62fF Cspl= 0fF DeltaC= 62fF
* 0b00001100..Cref= 62fF Cspl= 43fF DeltaC= 19fF
* 0b00001101..Cref=105fF Cspl= 0fF DeltaC= 105fF
* 0b00001110..Cref=105fF Cspl=30fF DeltaC= 75fF
* 0b00001111..Cref=0fF Cspl=0fF DeltaC= 0fF
*/
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_ADJ_1P8_MASK)
#define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK (0x200000U)
#define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_SHIFT (21U)
/*! FBB_M7_CONTROL_MODE - FBB_M7_CONTROL_MODE
* 0b0..SW Control
* 0b1..HW Control
*/
#define ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_FBB_M7_CONTROL_MODE_MASK)
#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK (0x400000U)
#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT (22U)
/*! RBB_SOC_CONTROL_MODE - RBB_SOC_CONTROL_MODE
* 0b0..SW Control
* 0b1..HW Control
*/
#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_SOC_CONTROL_MODE_MASK)
#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK (0x800000U)
#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT (23U)
/*! RBB_LPSR_CONTROL_MODE - RBB_LPSR_CONTROL_MODE
* 0b0..SW Control
* 0b1..HW Control
*/
#define ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_RBB_LPSR_CONTROL_MODE_MASK)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK (0x1000000U)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT (24U)
/*! WB_EN - wb_en
*/
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_EN_MASK)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK (0x2000000U)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT (25U)
/*! WB_TST_DIG_OUT - Digital output
*/
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_TST_DIG_OUT_MASK)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK (0x4000000U)
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT (26U)
/*! WB_OK - Digital Output pin.
*/
#define ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_SHIFT)) & ANADIG_PMU_PMU_BIAS_CTRL2_WB_OK_MASK)
/*! @} */
/*! @name PMU_REF_CTRL - PMU_REF_CTRL_REGISTER */
/*! @{ */
#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK (0x1U)
#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT (0U)
/*! REF_AI_TOGGLE - ref_ai_toggle
*/
#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_TOGGLE_MASK)
#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK (0x2U)
#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT (1U)
/*! REF_AI_BUSY - ref_ai_busy
*/
#define ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_AI_BUSY_MASK)
#define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK (0x4U)
#define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT (2U)
/*! REF_ENABLE - REF_ENABLE
*/
#define ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_ENABLE_MASK)
#define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK (0x8U)
#define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT (3U)
/*! REF_CONTROL_MODE - REF_CONTROL_MODE
* 0b0..SW Control
* 0b1..HW Control
*/
#define ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_REF_CONTROL_MODE_MASK)
#define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK (0x10U)
#define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT (4U)
/*! EN_PLL_VOL_REF_BUFFER - en_pll_vol_ref_buffer
*/
#define ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_SHIFT)) & ANADIG_PMU_PMU_REF_CTRL_EN_PLL_VOL_REF_BUFFER_MASK)
/*! @} */
/*! @name PMU_POWER_DETECT_CTRL - PMU_POWER_DETECT_CTRL_REGISTER */
/*! @{ */
#define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK (0x100U)
#define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT (8U)
/*! CKGB_LPSR1P0 - ckgb_lpsr1p0
*/
#define ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_SHIFT)) & ANADIG_PMU_PMU_POWER_DETECT_CTRL_CKGB_LPSR1P0_MASK)
/*! @} */
/*! @name LDO_PLL_ENABLE_SP - LDO_PLL_ENABLE_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
/*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
/*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
/*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
/*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
/*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
/*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
/*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
/*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
/*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
/*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
/*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
/*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
/*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
/*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
/*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
/*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_PLL_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
/*! @} */
/*! @name LDO_LPSR_ANA_ENABLE_SP - LDO_LPSR_ANA_ENABLE_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
/*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
/*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
/*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
/*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
/*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
/*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
/*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
/*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
/*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
/*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
/*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
/*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
/*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
/*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
/*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
/*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
/*! @} */
/*! @name LDO_LPSR_ANA_LP_MODE_SP - LDO_LPSR_ANA_LP_MODE_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U)
/*! LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U)
/*! LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK (0x4U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT (2U)
/*! LP_MODE_SETPONIT2 - LP_MODE_SETPOINT2
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT2_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK (0x8U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT (3U)
/*! LP_MODE_SETPONIT3 - LP_MODE_SETPOINT3
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT3_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK (0x10U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT (4U)
/*! LP_MODE_SETPONIT4 - LP_MODE_SETPOINT4
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT4_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK (0x20U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT (5U)
/*! LP_MODE_SETPONIT5 - LP_MODE_SETPOINT5
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT5_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK (0x40U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT (6U)
/*! LP_MODE_SETPONIT6 - LP_MODE_SETPOINT6
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT6_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK (0x80U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT (7U)
/*! LP_MODE_SETPONIT7 - LP_MODE_SETPOINT7
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT7_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK (0x100U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT (8U)
/*! LP_MODE_SETPONIT8 - LP_MODE_SETPOINT8
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT8_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK (0x200U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT (9U)
/*! LP_MODE_SETPONIT9 - LP_MODE_SETPOINT9
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT9_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK (0x400U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT (10U)
/*! LP_MODE_SETPONIT10 - LP_MODE_SETPOINT10
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT10_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK (0x800U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT (11U)
/*! LP_MODE_SETPONIT11 - LP_MODE_SETPOINT11
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT11_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT (12U)
/*! LP_MODE_SETPONIT12 - LP_MODE_SETPOINT12
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT12_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT (13U)
/*! LP_MODE_SETPONIT13 - LP_MODE_SETPOINT13
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT13_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT (14U)
/*! LP_MODE_SETPONIT14 - LP_MODE_SETPOINT14
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT14_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT (15U)
/*! LP_MODE_SETPONIT15 - LP_MODE_SETPOINT15
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_LP_MODE_SP_LP_MODE_SETPONIT15_MASK)
/*! @} */
/*! @name LDO_LPSR_ANA_TRACKING_EN_SP - LDO_LPSR_ANA_TRACKING_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U)
/*! TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U)
/*! TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U)
/*! TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U)
/*! TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U)
/*! TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U)
/*! TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U)
/*! TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U)
/*! TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U)
/*! TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U)
/*! TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U)
/*! TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U)
/*! TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U)
/*! TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U)
/*! TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U)
/*! TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U)
/*! TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK)
/*! @} */
/*! @name LDO_LPSR_ANA_BYPASS_EN_SP - LDO_LPSR_ANA_BYPASS_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U)
/*! BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U)
/*! BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U)
/*! BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U)
/*! BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U)
/*! BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U)
/*! BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U)
/*! BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U)
/*! BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U)
/*! BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U)
/*! BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U)
/*! BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U)
/*! BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U)
/*! BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U)
/*! BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U)
/*! BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U)
/*! BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK)
/*! @} */
/*! @name LDO_LPSR_ANA_STBY_EN_SP - LDO_LPSR_ANA_STBY_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
/*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
/*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
/*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
/*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
/*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
/*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
/*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
/*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
/*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
/*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
/*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
/*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
/*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
/*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
/*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
/*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_ANA_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
/*! @} */
/*! @name LDO_LPSR_DIG_ENABLE_SP - LDO_LPSR_DIG_ENABLE_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
/*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
/*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
/*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
/*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
/*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
/*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
/*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
/*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
/*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
/*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
/*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
/*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
/*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
/*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
/*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
/*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
/*! @} */
/*! @name LDO_LPSR_DIG_TRG_SP0 - LDO_LPSR_DIG_TRG_SP0_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK (0xFFU)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT (0U)
/*! VOLTAGE_SETPOINT0 - VOLTAGE_SETPOINT0
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK (0xFF00U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT (8U)
/*! VOLTAGE_SETPOINT1 - VOLTAGE_SETPOINT1
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK (0xFF0000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT (16U)
/*! VOLTAGE_SETPOINT2 - VOLTAGE_SETPOINT2
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK (0xFF000000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT (24U)
/*! VOLTAGE_SETPOINT3 - VOLTAGE_SETPOINT3
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP0_VOLTAGE_SETPOINT3_MASK)
/*! @} */
/*! @name LDO_LPSR_DIG_TRG_SP1 - LDO_LPSR_DIG_TRG_SP1_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK (0xFFU)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT (0U)
/*! VOLTAGE_SETPOINT4 - VOLTAGE_SETPOINT4
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK (0xFF00U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT (8U)
/*! VOLTAGE_SETPOINT5 - VOLTAGE_SETPOINT5
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK (0xFF0000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT (16U)
/*! VOLTAGE_SETPOINT6 - VOLTAGE_SETPOINT6
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK (0xFF000000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT (24U)
/*! VOLTAGE_SETPOINT7 - VOLTAGE_SETPOINT7
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP1_VOLTAGE_SETPOINT7_MASK)
/*! @} */
/*! @name LDO_LPSR_DIG_TRG_SP2 - LDO_LPSR_DIG_TRG_SP2_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK (0xFFU)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT (0U)
/*! VOLTAGE_SETPOINT8 - VOLTAGE_SETPOINT8
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK (0xFF00U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT (8U)
/*! VOLTAGE_SETPOINT9 - VOLTAGE_SETPOINT9
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK (0xFF0000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT (16U)
/*! VOLTAGE_SETPOINT10 - VOLTAGE_SETPOINT10
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK (0xFF000000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT (24U)
/*! VOLTAGE_SETPOINT11 - VOLTAGE_SETPOINT11
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP2_VOLTAGE_SETPOINT11_MASK)
/*! @} */
/*! @name LDO_LPSR_DIG_TRG_SP3 - LDO_LPSR_DIG_TRG_SP3_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK (0xFFU)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT (0U)
/*! VOLTAGE_SETPOINT12 - VOLTAGE_SETPOINT12
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK (0xFF00U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT (8U)
/*! VOLTAGE_SETPOINT13 - VOLTAGE_SETPOINT13
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK (0xFF0000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT (16U)
/*! VOLTAGE_SETPOINT14 - VOLTAGE_SETPOINT14
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK (0xFF000000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT (24U)
/*! VOLTAGE_SETPOINT15 - VOLTAGE_SETPOINT15
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRG_SP3_VOLTAGE_SETPOINT15_MASK)
/*! @} */
/*! @name LDO_LPSR_DIG_LP_MODE_SP - LDO_LPSR_DIG_LP_MODE_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT (0U)
/*! LP_MODE_SETPOINT0 - LP_MODE_SETPOINT0
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT (1U)
/*! LP_MODE_SETPOINT1 - LP_MODE_SETPOINT1
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT (2U)
/*! LP_MODE_SETPOINT2 - LP_MODE_SETPOINT2
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT (3U)
/*! LP_MODE_SETPOINT3 - LP_MODE_SETPOINT3
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT3_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT (4U)
/*! LP_MODE_SETPOINT4 - LP_MODE_SETPOINT4
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT (5U)
/*! LP_MODE_SETPOINT5 - LP_MODE_SETPOINT5
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT (6U)
/*! LP_MODE_SETPOINT6 - LP_MODE_SETPOINT6
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT (7U)
/*! LP_MODE_SETPOINT7 - LP_MODE_SETPOINT7
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT7_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT (8U)
/*! LP_MODE_SETPOINT8 - LP_MODE_SETPOINT8
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT (9U)
/*! LP_MODE_SETPOINT9 - LP_MODE_SETPOINT9
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT (10U)
/*! LP_MODE_SETPOINT10 - LP_MODE_SETPOINT10
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT (11U)
/*! LP_MODE_SETPOINT11 - LP_MODE_SETPOINT11
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT11_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT (12U)
/*! LP_MODE_SETPOINT12 - LP_MODE_SETPOINT12
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT (13U)
/*! LP_MODE_SETPOINT13 - LP_MODE_SETPOINT13
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT (14U)
/*! LP_MODE_SETPOINT14 - LP_MODE_SETPOINT14
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT (15U)
/*! LP_MODE_SETPOINT15 - LP_MODE_SETPOINT15
* 0b0..LP
* 0b1..HP
*/
#define ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_LP_MODE_SP_LP_MODE_SETPOINT15_MASK)
/*! @} */
/*! @name LDO_LPSR_DIG_TRACKING_EN_SP - LDO_LPSR_DIG_TRACKING_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT (0U)
/*! TRACKING_EN_SETPOINT0 - TRACKING_EN_SETPOINT0
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT (1U)
/*! TRACKING_EN_SETPOINT1 - TRACKING_EN_SETPOINT1
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT (2U)
/*! TRACKING_EN_SETPOINT2 - TRACKING_EN_SETPOINT2
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT (3U)
/*! TRACKING_EN_SETPOINT3 - TRACKING_EN_SETPOINT3
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT3_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT (4U)
/*! TRACKING_EN_SETPOINT4 - TRACKING_EN_SETPOINT4
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT (5U)
/*! TRACKING_EN_SETPOINT5 - TRACKING_EN_SETPOINT5
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT (6U)
/*! TRACKING_EN_SETPOINT6 - TRACKING_EN_SETPOINT6
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT (7U)
/*! TRACKING_EN_SETPOINT7 - TRACKING_EN_SETPOINT7
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT7_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT (8U)
/*! TRACKING_EN_SETPOINT8 - TRACKING_EN_SETPOINT8
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT (9U)
/*! TRACKING_EN_SETPOINT9 - TRACKING_EN_SETPOINT9
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT (10U)
/*! TRACKING_EN_SETPOINT10 - TRACKING_EN_SETPOINT10
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT (11U)
/*! TRACKING_EN_SETPOINT11 - TRACKING_EN_SETPOINT11
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT11_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT (12U)
/*! TRACKING_EN_SETPOINT12 - TRACKING_EN_SETPOINT12
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT (13U)
/*! TRACKING_EN_SETPOINT13 - TRACKING_EN_SETPOINT13
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT (14U)
/*! TRACKING_EN_SETPOINT14 - TRACKING_EN_SETPOINT14
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT (15U)
/*! TRACKING_EN_SETPOINT15 - TRACKING_EN_SETPOINT15
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_TRACKING_EN_SP_TRACKING_EN_SETPOINT15_MASK)
/*! @} */
/*! @name LDO_LPSR_DIG_BYPASS_EN_SP - LDO_LPSR_DIG_BYPASS_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT (0U)
/*! BYPASS_EN_SETPOINT0 - BYPASS_EN_SETPOINT0
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT (1U)
/*! BYPASS_EN_SETPOINT1 - BYPASS_EN_SETPOINT1
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT (2U)
/*! BYPASS_EN_SETPOINT2 - BYPASS_EN_SETPOINT2
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT (3U)
/*! BYPASS_EN_SETPOINT3 - BYPASS_EN_SETPOINT3
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT3_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT (4U)
/*! BYPASS_EN_SETPOINT4 - BYPASS_EN_SETPOINT4
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT (5U)
/*! BYPASS_EN_SETPOINT5 - BYPASS_EN_SETPOINT5
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT (6U)
/*! BYPASS_EN_SETPOINT6 - BYPASS_EN_SETPOINT6
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT (7U)
/*! BYPASS_EN_SETPOINT7 - BYPASS_EN_SETPOINT7
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT7_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT (8U)
/*! BYPASS_EN_SETPOINT8 - BYPASS_EN_SETPOINT8
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT (9U)
/*! BYPASS_EN_SETPOINT9 - BYPASS_EN_SETPOINT9
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT (10U)
/*! BYPASS_EN_SETPOINT10 - BYPASS_EN_SETPOINT10
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT (11U)
/*! BYPASS_EN_SETPOINT11 - BYPASS_EN_SETPOINT11
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT11_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT (12U)
/*! BYPASS_EN_SETPOINT12 - BYPASS_EN_SETPOINT12
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT (13U)
/*! BYPASS_EN_SETPOINT13 - BYPASS_EN_SETPOINT13
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT (14U)
/*! BYPASS_EN_SETPOINT14 - BYPASS_EN_SETPOINT14
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT (15U)
/*! BYPASS_EN_SETPOINT15 - BYPASS_EN_SETPOINT15
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_BYPASS_EN_SP_BYPASS_EN_SETPOINT15_MASK)
/*! @} */
/*! @name LDO_LPSR_DIG_STBY_EN_SP - LDO_LPSR_DIG_STBY_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
/*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT0
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
/*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT1
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
/*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT2
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
/*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT3
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
/*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT4
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
/*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT5
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
/*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT6
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
/*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT7
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
/*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT8
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
/*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT9
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
/*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT10
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
/*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT11
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
/*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT12
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
/*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT13
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
/*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT14
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
/*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT15
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_LDO_LPSR_DIG_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
/*! @} */
/*! @name BANDGAP_ENABLE_SP - BANDGAP_ENABLE_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
/*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
/*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
/*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
/*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
/*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
/*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
/*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT5
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
/*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
/*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
/*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
/*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
/*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
/*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
/*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
/*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
/*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
/*! @} */
/*! @name FBB_M7_ENABLE_SP - FBB_M7_ENABLE_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
/*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
/*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
/*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
/*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
/*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
/*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
/*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
/*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
/*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
/*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
/*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
/*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
/*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
/*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
/*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
/*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_FBB_M7_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
/*! @} */
/*! @name RBB_SOC_ENABLE_SP - RBB_SOC_ENABLE_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
/*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
/*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
/*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
/*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
/*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
/*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
/*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
/*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
/*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
/*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
/*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
/*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
/*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
/*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
/*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
/*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
/*! @} */
/*! @name RBB_LPSR_ENABLE_SP - RBB_LPSR_ENABLE_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT (0U)
/*! ON_OFF_SETPOINT0 - ON_OFF_SETPOINT0
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT0_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT (1U)
/*! ON_OFF_SETPOINT1 - ON_OFF_SETPOINT1
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT1_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT (2U)
/*! ON_OFF_SETPOINT2 - ON_OFF_SETPOINT2
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT2_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT (3U)
/*! ON_OFF_SETPOINT3 - ON_OFF_SETPOINT3
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT3_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT (4U)
/*! ON_OFF_SETPOINT4 - ON_OFF_SETPOINT4
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT4_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT (5U)
/*! ON_OFF_SETPOINT5 - ON_OFF_SETPOINT5
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT5_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT (6U)
/*! ON_OFF_SETPOINT6 - ON_OFF_SETPOINT6
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT6_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT (7U)
/*! ON_OFF_SETPOINT7 - ON_OFF_SETPOINT7
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT7_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT (8U)
/*! ON_OFF_SETPOINT8 - ON_OFF_SETPOINT8
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT8_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT (9U)
/*! ON_OFF_SETPOINT9 - ON_OFF_SETPOINT9
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT9_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT (10U)
/*! ON_OFF_SETPOINT10 - ON_OFF_SETPOINT10
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT10_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT (11U)
/*! ON_OFF_SETPOINT11 - ON_OFF_SETPOINT11
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT11_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT (12U)
/*! ON_OFF_SETPOINT12 - ON_OFF_SETPOINT12
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT12_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT (13U)
/*! ON_OFF_SETPOINT13 - ON_OFF_SETPOINT13
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT13_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT (14U)
/*! ON_OFF_SETPOINT14 - ON_OFF_SETPOINT14
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT14_MASK)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT (15U)
/*! ON_OFF_SETPOINT15 - ON_OFF_SETPOINT15
* 0b0..ON
* 0b1..OFF
*/
#define ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_ENABLE_SP_ON_OFF_SETPOINT15_MASK)
/*! @} */
/*! @name BANDGAP_STBY_EN_SP - BANDGAP_STBY_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
/*! STBY_EN_SETPOINT0 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
/*! STBY_EN_SETPOINT1 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
/*! STBY_EN_SETPOINT2 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
/*! STBY_EN_SETPOINT3 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
/*! STBY_EN_SETPOINT4 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
/*! STBY_EN_SETPOINT5 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
/*! STBY_EN_SETPOINT6 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
/*! STBY_EN_SETPOINT7 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
/*! STBY_EN_SETPOINT8 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
/*! STBY_EN_SETPOINT9 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
/*! STBY_EN_SETPOINT10 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
/*! STBY_EN_SETPOINT11 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
/*! STBY_EN_SETPOINT12 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
/*! STBY_EN_SETPOINT13 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
/*! STBY_EN_SETPOINT14 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
/*! STBY_EN_SETPOINT15 - STBY_EN_SETPOINT
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_BANDGAP_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
/*! @} */
/*! @name PLL_LDO_STBY_EN_SP - PLL_LDO_STBY_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
/*! STBY_EN_SETPOINT0 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
/*! STBY_EN_SETPOINT1 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
/*! STBY_EN_SETPOINT2 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
/*! STBY_EN_SETPOINT3 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
/*! STBY_EN_SETPOINT4 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
/*! STBY_EN_SETPOINT5 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
/*! STBY_EN_SETPOINT6 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
/*! STBY_EN_SETPOINT7 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
/*! STBY_EN_SETPOINT8 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
/*! STBY_EN_SETPOINT9 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
/*! STBY_EN_SETPOINT10 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
/*! STBY_EN_SETPOINT11 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
/*! STBY_EN_SETPOINT12 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
/*! STBY_EN_SETPOINT13 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
/*! STBY_EN_SETPOINT14 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
/*! STBY_EN_SETPOINT15 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_PLL_LDO_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
/*! @} */
/*! @name FBB_M7_STBY_EN_SP - FBB_M7_STBY_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
/*! STBY_EN_SETPOINT0 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
/*! STBY_EN_SETPOINT1 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
/*! STBY_EN_SETPOINT2 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
/*! STBY_EN_SETPOINT3 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
/*! STBY_EN_SETPOINT4 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
/*! STBY_EN_SETPOINT5 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
/*! STBY_EN_SETPOINT6 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
/*! STBY_EN_SETPOINT7 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
/*! STBY_EN_SETPOINT8 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
/*! STBY_EN_SETPOINT9 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
/*! STBY_EN_SETPOINT10 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
/*! STBY_EN_SETPOINT11 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
/*! STBY_EN_SETPOINT12 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
/*! STBY_EN_SETPOINT13 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
/*! STBY_EN_SETPOINT14 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
/*! STBY_EN_SETPOINT15 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_FBB_M7_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
/*! @} */
/*! @name RBB_SOC_STBY_EN_SP - RBB_SOC_STBY_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
/*! STBY_EN_SETPOINT0 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
/*! STBY_EN_SETPOINT1 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
/*! STBY_EN_SETPOINT2 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
/*! STBY_EN_SETPOINT3 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
/*! STBY_EN_SETPOINT4 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
/*! STBY_EN_SETPOINT5 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
/*! STBY_EN_SETPOINT6 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
/*! STBY_EN_SETPOINT7 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
/*! STBY_EN_SETPOINT8 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
/*! STBY_EN_SETPOINT9 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
/*! STBY_EN_SETPOINT10 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
/*! STBY_EN_SETPOINT11 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
/*! STBY_EN_SETPOINT12 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
/*! STBY_EN_SETPOINT13 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
/*! STBY_EN_SETPOINT14 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
/*! STBY_EN_SETPOINT15 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_SOC_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
/*! @} */
/*! @name RBB_LPSR_STBY_EN_SP - RBB_LPSR_STBY_EN_SP_REGISTER */
/*! @{ */
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK (0x1U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT (0U)
/*! STBY_EN_SETPOINT0 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT0_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK (0x2U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT (1U)
/*! STBY_EN_SETPOINT1 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT1_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK (0x4U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT (2U)
/*! STBY_EN_SETPOINT2 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT2_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK (0x8U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT (3U)
/*! STBY_EN_SETPOINT3 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT3_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK (0x10U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT (4U)
/*! STBY_EN_SETPOINT4 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT4_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK (0x20U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT (5U)
/*! STBY_EN_SETPOINT5 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT5_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK (0x40U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT (6U)
/*! STBY_EN_SETPOINT6 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT6_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK (0x80U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT (7U)
/*! STBY_EN_SETPOINT7 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT7_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK (0x100U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT (8U)
/*! STBY_EN_SETPOINT8 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT8_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK (0x200U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT (9U)
/*! STBY_EN_SETPOINT9 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT9_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK (0x400U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT (10U)
/*! STBY_EN_SETPOINT10 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT10_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK (0x800U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT (11U)
/*! STBY_EN_SETPOINT11 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT11_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK (0x1000U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT (12U)
/*! STBY_EN_SETPOINT12 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT12_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK (0x2000U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT (13U)
/*! STBY_EN_SETPOINT13 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT13_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK (0x4000U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT (14U)
/*! STBY_EN_SETPOINT14 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT14_MASK)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK (0x8000U)
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT (15U)
/*! STBY_EN_SETPOINT15 - Standby mode
* 0b0..Disabled
* 0b1..Enabled
*/
#define ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_SHIFT)) & ANADIG_PMU_RBB_LPSR_STBY_EN_SP_STBY_EN_SETPOINT15_MASK)
/*! @} */
/*! @name FBB_M7_CONFIGURE - FBB_M7_CONFIGURE_REGISTER */
/*! @{ */
#define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_MASK (0xFU)
#define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_SHIFT (0U)
/*! WB_CFG_PW - wb_cfg_pw
*/
#define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_PW_MASK)
#define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
#define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_SHIFT (4U)
/*! WB_CFG_NW - wb_cfg_nw
*/
#define ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_WB_CFG_NW_MASK)
#define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
#define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
/*! OSCILLATOR_BITS - oscillator_bits
*/
#define ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_OSCILLATOR_BITS_MASK)
#define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
#define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
/*! REGULATOR_STRENGTH - regulator_strength
*/
#define ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_FBB_M7_CONFIGURE_REGULATOR_STRENGTH_MASK)
/*! @} */
/*! @name RBB_LPSR_CONFIGURE - RBB_LPSR_CONFIGURE_REGISTER */
/*! @{ */
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK (0xFU)
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT (0U)
/*! WB_CFG_PW - wb_cfg_pw
*/
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_PW_MASK)
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT (4U)
/*! WB_CFG_NW - wb_cfg_nw
*/
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_WB_CFG_NW_MASK)
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
/*! OSCILLATOR_BITS - oscillator_bits
*/
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_OSCILLATOR_BITS_MASK)
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
/*! REGULATOR_STRENGTH - regulator_strength
*/
#define ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_LPSR_CONFIGURE_REGULATOR_STRENGTH_MASK)
/*! @} */
/*! @name RBB_SOC_CONFIGURE - RBB_SOC_CONFIGURE_REGISTER */
/*! @{ */
#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK (0xFU)
#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT (0U)
/*! WB_CFG_PW - wb_cfg_pw
*/
#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_PW_MASK)
#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK (0xF0U)
#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT (4U)
/*! WB_CFG_NW - wb_cfg_nw
*/
#define ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_WB_CFG_NW_MASK)
#define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK (0x700U)
#define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT (8U)
/*! OSCILLATOR_BITS - oscillator_bits
*/
#define ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_OSCILLATOR_BITS_MASK)
#define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK (0x3800U)
#define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT (11U)
/*! REGULATOR_STRENGTH - regulator_strength
*/
#define ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_SHIFT)) & ANADIG_PMU_RBB_SOC_CONFIGURE_REGULATOR_STRENGTH_MASK)
/*! @} */
/*! @name REFTOP_OTP_TRIM_VALUE - REFTOP_OTP_TRIM_VALUE_REGISTER */
/*! @{ */
#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK (0x7U)
#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT (0U)
/*! REFTOP_IBZTCADJ - REFTOP_IBZTCADJ
*/
#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_IBZTCADJ_MASK)
#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK (0x38U)
#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT (3U)
/*! REFTOP_VBGADJ - REFTOP_VBGADJ
*/
#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_VBGADJ_MASK)
#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK (0x40U)
#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT (6U)
/*! REFTOP_TRIM_EN - REFTOP_TRIM_EN
*/
#define ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_SHIFT)) & ANADIG_PMU_REFTOP_OTP_TRIM_VALUE_REFTOP_TRIM_EN_MASK)
/*! @} */
/*! @name LPSR_1P8_LDO_OTP_TRIM_VALUE - LPSR_1P8_LDO_OTP_TRIM_VALUE_REGISTER */
/*! @{ */
#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK (0x3U)
#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT (0U)
/*! LPSR_LDO_1P8_TRIM - LPSR_LDO_1P8_TRIM
*/
#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_MASK)
#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK (0x4U)
#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT (2U)
/*! LPSR_LDO_1P8_TRIM_EN - LPSR_LDO_1P8_TRIM_EN
*/
#define ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_SHIFT)) & ANADIG_PMU_LPSR_1P8_LDO_OTP_TRIM_VALUE_LPSR_LDO_1P8_TRIM_EN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ANADIG_PMU_Register_Masks */
/* ANADIG_PMU - Peripheral instance base addresses */
/** Peripheral ANADIG_PMU base address */
#define ANADIG_PMU_BASE (0x40C84000u)
/** Peripheral ANADIG_PMU base pointer */
#define ANADIG_PMU ((ANADIG_PMU_Type *)ANADIG_PMU_BASE)
/** Array initializer of ANADIG_PMU peripheral base addresses */
#define ANADIG_PMU_BASE_ADDRS { ANADIG_PMU_BASE }
/** Array initializer of ANADIG_PMU peripheral base pointers */
#define ANADIG_PMU_BASE_PTRS { ANADIG_PMU }
/*!
* @}
*/ /* end of group ANADIG_PMU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ANADIG_TEMPSENSOR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_TEMPSENSOR_Peripheral_Access_Layer ANADIG_TEMPSENSOR Peripheral Access Layer
* @{
*/
/** ANADIG_TEMPSENSOR - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[1024];
__IO uint32_t TEMPSENSOR; /**< Tempsensor Register, offset: 0x400 */
uint8_t RESERVED_1[44];
__I uint32_t TEMPSNS_OTP_TRIM_VALUE; /**< TEMPSNS_OTP_TRIM_VALUE_REGISTER, offset: 0x430 */
} ANADIG_TEMPSENSOR_Type;
/* ----------------------------------------------------------------------------
-- ANADIG_TEMPSENSOR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ANADIG_TEMPSENSOR_Register_Masks ANADIG_TEMPSENSOR Register Masks
* @{
*/
/*! @name TEMPSENSOR - Tempsensor Register */
/*! @{ */
#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK (0x8000U)
#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT (15U)
/*! TEMPSNS_AI_TOGGLE - AI toggle
*/
#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_TOGGLE_MASK)
#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK (0x10000U)
#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT (16U)
/*! TEMPSNS_AI_BUSY - AI Busy monitor
*/
#define ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSENSOR_TEMPSNS_AI_BUSY_MASK)
/*! @} */
/*! @name TEMPSNS_OTP_TRIM_VALUE - TEMPSNS_OTP_TRIM_VALUE_REGISTER */
/*! @{ */
#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK (0x3FFC00U)
#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT (10U)
/*! TEMPSNS_TEMP_VAL - Temperature Value at 25C
*/
#define ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_SHIFT)) & ANADIG_TEMPSENSOR_TEMPSNS_OTP_TRIM_VALUE_TEMPSNS_TEMP_VAL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ANADIG_TEMPSENSOR_Register_Masks */
/* ANADIG_TEMPSENSOR - Peripheral instance base addresses */
/** Peripheral ANADIG_TEMPSENSOR base address */
#define ANADIG_TEMPSENSOR_BASE (0x40C84000u)
/** Peripheral ANADIG_TEMPSENSOR base pointer */
#define ANADIG_TEMPSENSOR ((ANADIG_TEMPSENSOR_Type *)ANADIG_TEMPSENSOR_BASE)
/** Array initializer of ANADIG_TEMPSENSOR peripheral base addresses */
#define ANADIG_TEMPSENSOR_BASE_ADDRS { ANADIG_TEMPSENSOR_BASE }
/** Array initializer of ANADIG_TEMPSENSOR peripheral base pointers */
#define ANADIG_TEMPSENSOR_BASE_PTRS { ANADIG_TEMPSENSOR }
/*!
* @}
*/ /* end of group ANADIG_TEMPSENSOR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AOI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AOI_Peripheral_Access_Layer AOI Peripheral Access Layer
* @{
*/
/** AOI - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x4 */
__IO uint16_t BFCRT01; /**< Boolean Function Term 0 and 1 Configuration Register for EVENTn, array offset: 0x0, array step: 0x4 */
__IO uint16_t BFCRT23; /**< Boolean Function Term 2 and 3 Configuration Register for EVENTn, array offset: 0x2, array step: 0x4 */
} BFCRT[4];
} AOI_Type;
/* ----------------------------------------------------------------------------
-- AOI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AOI_Register_Masks AOI Register Masks
* @{
*/
/*! @name BFCRT01 - Boolean Function Term 0 and 1 Configuration Register for EVENTn */
/*! @{ */
#define AOI_BFCRT01_PT1_DC_MASK (0x3U)
#define AOI_BFCRT01_PT1_DC_SHIFT (0U)
/*! PT1_DC - Product term 1, D input configuration
* 0b00..Force the D input in this product term to a logical zero
* 0b01..Pass the D input in this product term
* 0b10..Complement the D input in this product term
* 0b11..Force the D input in this product term to a logical one
*/
#define AOI_BFCRT01_PT1_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_DC_SHIFT)) & AOI_BFCRT01_PT1_DC_MASK)
#define AOI_BFCRT01_PT1_CC_MASK (0xCU)
#define AOI_BFCRT01_PT1_CC_SHIFT (2U)
/*! PT1_CC - Product term 1, C input configuration
* 0b00..Force the C input in this product term to a logical zero
* 0b01..Pass the C input in this product term
* 0b10..Complement the C input in this product term
* 0b11..Force the C input in this product term to a logical one
*/
#define AOI_BFCRT01_PT1_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_CC_SHIFT)) & AOI_BFCRT01_PT1_CC_MASK)
#define AOI_BFCRT01_PT1_BC_MASK (0x30U)
#define AOI_BFCRT01_PT1_BC_SHIFT (4U)
/*! PT1_BC - Product term 1, B input configuration
* 0b00..Force the B input in this product term to a logical zero
* 0b01..Pass the B input in this product term
* 0b10..Complement the B input in this product term
* 0b11..Force the B input in this product term to a logical one
*/
#define AOI_BFCRT01_PT1_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_BC_SHIFT)) & AOI_BFCRT01_PT1_BC_MASK)
#define AOI_BFCRT01_PT1_AC_MASK (0xC0U)
#define AOI_BFCRT01_PT1_AC_SHIFT (6U)
/*! PT1_AC - Product term 1, A input configuration
* 0b00..Force the A input in this product term to a logical zero
* 0b01..Pass the A input in this product term
* 0b10..Complement the A input in this product term
* 0b11..Force the A input in this product term to a logical one
*/
#define AOI_BFCRT01_PT1_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT1_AC_SHIFT)) & AOI_BFCRT01_PT1_AC_MASK)
#define AOI_BFCRT01_PT0_DC_MASK (0x300U)
#define AOI_BFCRT01_PT0_DC_SHIFT (8U)
/*! PT0_DC - Product term 0, D input configuration
* 0b00..Force the D input in this product term to a logical zero
* 0b01..Pass the D input in this product term
* 0b10..Complement the D input in this product term
* 0b11..Force the D input in this product term to a logical one
*/
#define AOI_BFCRT01_PT0_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_DC_SHIFT)) & AOI_BFCRT01_PT0_DC_MASK)
#define AOI_BFCRT01_PT0_CC_MASK (0xC00U)
#define AOI_BFCRT01_PT0_CC_SHIFT (10U)
/*! PT0_CC - Product term 0, C input configuration
* 0b00..Force the C input in this product term to a logical zero
* 0b01..Pass the C input in this product term
* 0b10..Complement the C input in this product term
* 0b11..Force the C input in this product term to a logical one
*/
#define AOI_BFCRT01_PT0_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_CC_SHIFT)) & AOI_BFCRT01_PT0_CC_MASK)
#define AOI_BFCRT01_PT0_BC_MASK (0x3000U)
#define AOI_BFCRT01_PT0_BC_SHIFT (12U)
/*! PT0_BC - Product term 0, B input configuration
* 0b00..Force the B input in this product term to a logical zero
* 0b01..Pass the B input in this product term
* 0b10..Complement the B input in this product term
* 0b11..Force the B input in this product term to a logical one
*/
#define AOI_BFCRT01_PT0_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_BC_SHIFT)) & AOI_BFCRT01_PT0_BC_MASK)
#define AOI_BFCRT01_PT0_AC_MASK (0xC000U)
#define AOI_BFCRT01_PT0_AC_SHIFT (14U)
/*! PT0_AC - Product term 0, A input configuration
* 0b00..Force the A input in this product term to a logical zero
* 0b01..Pass the A input in this product term
* 0b10..Complement the A input in this product term
* 0b11..Force the A input in this product term to a logical one
*/
#define AOI_BFCRT01_PT0_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT01_PT0_AC_SHIFT)) & AOI_BFCRT01_PT0_AC_MASK)
/*! @} */
/* The count of AOI_BFCRT01 */
#define AOI_BFCRT01_COUNT (4U)
/*! @name BFCRT23 - Boolean Function Term 2 and 3 Configuration Register for EVENTn */
/*! @{ */
#define AOI_BFCRT23_PT3_DC_MASK (0x3U)
#define AOI_BFCRT23_PT3_DC_SHIFT (0U)
/*! PT3_DC - Product term 3, D input configuration
* 0b00..Force the D input in this product term to a logical zero
* 0b01..Pass the D input in this product term
* 0b10..Complement the D input in this product term
* 0b11..Force the D input in this product term to a logical one
*/
#define AOI_BFCRT23_PT3_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_DC_SHIFT)) & AOI_BFCRT23_PT3_DC_MASK)
#define AOI_BFCRT23_PT3_CC_MASK (0xCU)
#define AOI_BFCRT23_PT3_CC_SHIFT (2U)
/*! PT3_CC - Product term 3, C input configuration
* 0b00..Force the C input in this product term to a logical zero
* 0b01..Pass the C input in this product term
* 0b10..Complement the C input in this product term
* 0b11..Force the C input in this product term to a logical one
*/
#define AOI_BFCRT23_PT3_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_CC_SHIFT)) & AOI_BFCRT23_PT3_CC_MASK)
#define AOI_BFCRT23_PT3_BC_MASK (0x30U)
#define AOI_BFCRT23_PT3_BC_SHIFT (4U)
/*! PT3_BC - Product term 3, B input configuration
* 0b00..Force the B input in this product term to a logical zero
* 0b01..Pass the B input in this product term
* 0b10..Complement the B input in this product term
* 0b11..Force the B input in this product term to a logical one
*/
#define AOI_BFCRT23_PT3_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_BC_SHIFT)) & AOI_BFCRT23_PT3_BC_MASK)
#define AOI_BFCRT23_PT3_AC_MASK (0xC0U)
#define AOI_BFCRT23_PT3_AC_SHIFT (6U)
/*! PT3_AC - Product term 3, A input configuration
* 0b00..Force the A input in this product term to a logical zero
* 0b01..Pass the A input in this product term
* 0b10..Complement the A input in this product term
* 0b11..Force the A input in this product term to a logical one
*/
#define AOI_BFCRT23_PT3_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT3_AC_SHIFT)) & AOI_BFCRT23_PT3_AC_MASK)
#define AOI_BFCRT23_PT2_DC_MASK (0x300U)
#define AOI_BFCRT23_PT2_DC_SHIFT (8U)
/*! PT2_DC - Product term 2, D input configuration
* 0b00..Force the D input in this product term to a logical zero
* 0b01..Pass the D input in this product term
* 0b10..Complement the D input in this product term
* 0b11..Force the D input in this product term to a logical one
*/
#define AOI_BFCRT23_PT2_DC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_DC_SHIFT)) & AOI_BFCRT23_PT2_DC_MASK)
#define AOI_BFCRT23_PT2_CC_MASK (0xC00U)
#define AOI_BFCRT23_PT2_CC_SHIFT (10U)
/*! PT2_CC - Product term 2, C input configuration
* 0b00..Force the C input in this product term to a logical zero
* 0b01..Pass the C input in this product term
* 0b10..Complement the C input in this product term
* 0b11..Force the C input in this product term to a logical one
*/
#define AOI_BFCRT23_PT2_CC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_CC_SHIFT)) & AOI_BFCRT23_PT2_CC_MASK)
#define AOI_BFCRT23_PT2_BC_MASK (0x3000U)
#define AOI_BFCRT23_PT2_BC_SHIFT (12U)
/*! PT2_BC - Product term 2, B input configuration
* 0b00..Force the B input in this product term to a logical zero
* 0b01..Pass the B input in this product term
* 0b10..Complement the B input in this product term
* 0b11..Force the B input in this product term to a logical one
*/
#define AOI_BFCRT23_PT2_BC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_BC_SHIFT)) & AOI_BFCRT23_PT2_BC_MASK)
#define AOI_BFCRT23_PT2_AC_MASK (0xC000U)
#define AOI_BFCRT23_PT2_AC_SHIFT (14U)
/*! PT2_AC - Product term 2, A input configuration
* 0b00..Force the A input in this product term to a logical zero
* 0b01..Pass the A input in this product term
* 0b10..Complement the A input in this product term
* 0b11..Force the A input in this product term to a logical one
*/
#define AOI_BFCRT23_PT2_AC(x) (((uint16_t)(((uint16_t)(x)) << AOI_BFCRT23_PT2_AC_SHIFT)) & AOI_BFCRT23_PT2_AC_MASK)
/*! @} */
/* The count of AOI_BFCRT23 */
#define AOI_BFCRT23_COUNT (4U)
/*!
* @}
*/ /* end of group AOI_Register_Masks */
/* AOI - Peripheral instance base addresses */
/** Peripheral AOI1 base address */
#define AOI1_BASE (0x400B8000u)
/** Peripheral AOI1 base pointer */
#define AOI1 ((AOI_Type *)AOI1_BASE)
/** Peripheral AOI2 base address */
#define AOI2_BASE (0x400BC000u)
/** Peripheral AOI2 base pointer */
#define AOI2 ((AOI_Type *)AOI2_BASE)
/** Array initializer of AOI peripheral base addresses */
#define AOI_BASE_ADDRS { 0u, AOI1_BASE, AOI2_BASE }
/** Array initializer of AOI peripheral base pointers */
#define AOI_BASE_PTRS { (AOI_Type *)0u, AOI1, AOI2 }
/*!
* @}
*/ /* end of group AOI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ASRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ASRC_Peripheral_Access_Layer ASRC Peripheral Access Layer
* @{
*/
/** ASRC - Register Layout Typedef */
typedef struct {
__IO uint32_t ASRCTR; /**< ASRC Control Register, offset: 0x0 */
__IO uint32_t ASRIER; /**< ASRC Interrupt Enable Register, offset: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t ASRCNCR; /**< ASRC Channel Number Configuration Register, offset: 0xC */
__IO uint32_t ASRCFG; /**< ASRC Filter Configuration Status Register, offset: 0x10 */
__IO uint32_t ASRCSR; /**< ASRC Clock Source Register, offset: 0x14 */
__IO uint32_t ASRCDR1; /**< ASRC Clock Divider Register 1, offset: 0x18 */
__IO uint32_t ASRCDR2; /**< ASRC Clock Divider Register 2, offset: 0x1C */
__I uint32_t ASRSTR; /**< ASRC Status Register, offset: 0x20 */
uint8_t RESERVED_1[28];
__IO uint32_t ASRPM[5]; /**< ASRC Parameter Register n, array offset: 0x40, array step: 0x4 */
__IO uint32_t ASRTFR1; /**< ASRC Task Queue FIFO Register 1, offset: 0x54 */
uint8_t RESERVED_2[4];
__IO uint32_t ASRCCR; /**< ASRC Channel Counter Register, offset: 0x5C */
__O uint32_t ASRDIA; /**< ASRC Data Input Register for Pair x, offset: 0x60 */
__I uint32_t ASRDOA; /**< ASRC Data Output Register for Pair x, offset: 0x64 */
__O uint32_t ASRDIB; /**< ASRC Data Input Register for Pair x, offset: 0x68 */
__I uint32_t ASRDOB; /**< ASRC Data Output Register for Pair x, offset: 0x6C */
__O uint32_t ASRDIC; /**< ASRC Data Input Register for Pair x, offset: 0x70 */
__I uint32_t ASRDOC; /**< ASRC Data Output Register for Pair x, offset: 0x74 */
uint8_t RESERVED_3[8];
__IO uint32_t ASRIDRHA; /**< ASRC Ideal Ratio for Pair A-High Part, offset: 0x80 */
__IO uint32_t ASRIDRLA; /**< ASRC Ideal Ratio for Pair A -Low Part, offset: 0x84 */
__IO uint32_t ASRIDRHB; /**< ASRC Ideal Ratio for Pair B-High Part, offset: 0x88 */
__IO uint32_t ASRIDRLB; /**< ASRC Ideal Ratio for Pair B-Low Part, offset: 0x8C */
__IO uint32_t ASRIDRHC; /**< ASRC Ideal Ratio for Pair C-High Part, offset: 0x90 */
__IO uint32_t ASRIDRLC; /**< ASRC Ideal Ratio for Pair C-Low Part, offset: 0x94 */
__IO uint32_t ASR76K; /**< ASRC 76 kHz Period in terms of ASRC processing clock, offset: 0x98 */
__IO uint32_t ASR56K; /**< ASRC 56 kHz Period in terms of ASRC processing clock, offset: 0x9C */
__IO uint32_t ASRMCRA; /**< ASRC Misc Control Register for Pair A, offset: 0xA0 */
__I uint32_t ASRFSTA; /**< ASRC FIFO Status Register for Pair A, offset: 0xA4 */
__IO uint32_t ASRMCRB; /**< ASRC Misc Control Register for Pair B, offset: 0xA8 */
__I uint32_t ASRFSTB; /**< ASRC FIFO Status Register for Pair B, offset: 0xAC */
__IO uint32_t ASRMCRC; /**< ASRC Misc Control Register for Pair C, offset: 0xB0 */
__I uint32_t ASRFSTC; /**< ASRC FIFO Status Register for Pair C, offset: 0xB4 */
uint8_t RESERVED_4[8];
__IO uint32_t ASRMCR1[3]; /**< ASRC Misc Control Register 1 for Pair X, array offset: 0xC0, array step: 0x4 */
} ASRC_Type;
/* ----------------------------------------------------------------------------
-- ASRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ASRC_Register_Masks ASRC Register Masks
* @{
*/
/*! @name ASRCTR - ASRC Control Register */
/*! @{ */
#define ASRC_ASRCTR_ASRCEN_MASK (0x1U)
#define ASRC_ASRCTR_ASRCEN_SHIFT (0U)
/*! ASRCEN - ASRCEN
* 0b0..operation of ASRC disabled
* 0b1..operation ASRC is enabled
*/
#define ASRC_ASRCTR_ASRCEN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASRCEN_SHIFT)) & ASRC_ASRCTR_ASRCEN_MASK)
#define ASRC_ASRCTR_ASREA_MASK (0x2U)
#define ASRC_ASRCTR_ASREA_SHIFT (1U)
/*! ASREA - ASREA
* 0b0..operation of conversion A is disabled
* 0b1..operation of conversion A is enabled
*/
#define ASRC_ASRCTR_ASREA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREA_SHIFT)) & ASRC_ASRCTR_ASREA_MASK)
#define ASRC_ASRCTR_ASREB_MASK (0x4U)
#define ASRC_ASRCTR_ASREB_SHIFT (2U)
/*! ASREB - ASREB
* 0b0..operation of conversion B is disabled
* 0b1..operation of conversion B is enabled
*/
#define ASRC_ASRCTR_ASREB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREB_SHIFT)) & ASRC_ASRCTR_ASREB_MASK)
#define ASRC_ASRCTR_ASREC_MASK (0x8U)
#define ASRC_ASRCTR_ASREC_SHIFT (3U)
/*! ASREC - ASREC
* 0b0..operation of conversion C is disabled
* 0b1..operation of conversion C is enabled
*/
#define ASRC_ASRCTR_ASREC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ASREC_SHIFT)) & ASRC_ASRCTR_ASREC_MASK)
#define ASRC_ASRCTR_SRST_MASK (0x10U)
#define ASRC_ASRCTR_SRST_SHIFT (4U)
/*! SRST - SRST
* 0b0..ASRC Software reset cleared
* 0b1..ASRC Software reset generated. NOTE: This is a self-clear bit
*/
#define ASRC_ASRCTR_SRST(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_SRST_SHIFT)) & ASRC_ASRCTR_SRST_MASK)
#define ASRC_ASRCTR_IDRA_MASK (0x2000U)
#define ASRC_ASRCTR_IDRA_SHIFT (13U)
/*! IDRA - IDRA
* 0b0..ASRC internal measured ratio is used
* 0b1..Ideal ratio from the interface register ASRIDRHA, ASRIDRLA is used
*/
#define ASRC_ASRCTR_IDRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRA_SHIFT)) & ASRC_ASRCTR_IDRA_MASK)
#define ASRC_ASRCTR_USRA_MASK (0x4000U)
#define ASRC_ASRCTR_USRA_SHIFT (14U)
/*! USRA - USRA
* 0b1..Use ratio as the input to ASRC for pair A
* 0b0..Do not use ratio as the input to ASRC for pair A
*/
#define ASRC_ASRCTR_USRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRA_SHIFT)) & ASRC_ASRCTR_USRA_MASK)
#define ASRC_ASRCTR_IDRB_MASK (0x8000U)
#define ASRC_ASRCTR_IDRB_SHIFT (15U)
/*! IDRB - IDRB
* 0b0..ASRC internal measured ratio is used
* 0b1..Ideal ratio from the interface register ASRIDRHB, ASRIDRLB is used
*/
#define ASRC_ASRCTR_IDRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRB_SHIFT)) & ASRC_ASRCTR_IDRB_MASK)
#define ASRC_ASRCTR_USRB_MASK (0x10000U)
#define ASRC_ASRCTR_USRB_SHIFT (16U)
/*! USRB - USRB
* 0b1..Use ratio as the input to ASRC for pair B
* 0b0..Do not use ratio as the input to ASRC for pair B
*/
#define ASRC_ASRCTR_USRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRB_SHIFT)) & ASRC_ASRCTR_USRB_MASK)
#define ASRC_ASRCTR_IDRC_MASK (0x20000U)
#define ASRC_ASRCTR_IDRC_SHIFT (17U)
/*! IDRC - IDRC
* 0b0..ASRC internal measured ratio is used
* 0b1..Ideal ratio from the interface register ASRIDRHC, ASRIDRLC is used
*/
#define ASRC_ASRCTR_IDRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_IDRC_SHIFT)) & ASRC_ASRCTR_IDRC_MASK)
#define ASRC_ASRCTR_USRC_MASK (0x40000U)
#define ASRC_ASRCTR_USRC_SHIFT (18U)
/*! USRC - USRC
* 0b1..Use ratio as the input to ASRC for pair C
* 0b0..Do not use ratio as the input to ASRC for pair C
*/
#define ASRC_ASRCTR_USRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_USRC_SHIFT)) & ASRC_ASRCTR_USRC_MASK)
#define ASRC_ASRCTR_ATSA_MASK (0x100000U)
#define ASRC_ASRCTR_ATSA_SHIFT (20U)
/*! ATSA - ATSA
* 0b1..Pair A automatically updates its pre-processing and post-processing options
* 0b0..Pair A does not automatically update its pre-processing and post-processing options
*/
#define ASRC_ASRCTR_ATSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSA_SHIFT)) & ASRC_ASRCTR_ATSA_MASK)
#define ASRC_ASRCTR_ATSB_MASK (0x200000U)
#define ASRC_ASRCTR_ATSB_SHIFT (21U)
/*! ATSB - ATSB
* 0b1..Pair B automatically updates its pre-processing and post-processing options
* 0b0..Pair B does not automatically update its pre-processing and post-processing options
*/
#define ASRC_ASRCTR_ATSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSB_SHIFT)) & ASRC_ASRCTR_ATSB_MASK)
#define ASRC_ASRCTR_ATSC_MASK (0x400000U)
#define ASRC_ASRCTR_ATSC_SHIFT (22U)
/*! ATSC - ATSC
* 0b1..Pair C automatically updates its pre-processing and post-processing options
* 0b0..Pair C does not automatically update its pre-processing and post-processing options
*/
#define ASRC_ASRCTR_ATSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCTR_ATSC_SHIFT)) & ASRC_ASRCTR_ATSC_MASK)
/*! @} */
/*! @name ASRIER - ASRC Interrupt Enable Register */
/*! @{ */
#define ASRC_ASRIER_ADIEA_MASK (0x1U)
#define ASRC_ASRIER_ADIEA_SHIFT (0U)
/*! ADIEA - ADIEA
* 0b1..interrupt enabled
* 0b0..interrupt disabled
*/
#define ASRC_ASRIER_ADIEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEA_SHIFT)) & ASRC_ASRIER_ADIEA_MASK)
#define ASRC_ASRIER_ADIEB_MASK (0x2U)
#define ASRC_ASRIER_ADIEB_SHIFT (1U)
/*! ADIEB - ADIEB
* 0b1..interrupt enabled
* 0b0..interrupt disabled
*/
#define ASRC_ASRIER_ADIEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEB_SHIFT)) & ASRC_ASRIER_ADIEB_MASK)
#define ASRC_ASRIER_ADIEC_MASK (0x4U)
#define ASRC_ASRIER_ADIEC_SHIFT (2U)
/*! ADIEC - ADIEC
* 0b1..interrupt enabled
* 0b0..interrupt disabled
*/
#define ASRC_ASRIER_ADIEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADIEC_SHIFT)) & ASRC_ASRIER_ADIEC_MASK)
#define ASRC_ASRIER_ADOEA_MASK (0x8U)
#define ASRC_ASRIER_ADOEA_SHIFT (3U)
/*! ADOEA - ADOEA
* 0b1..interrupt enabled
* 0b0..interrupt disabled
*/
#define ASRC_ASRIER_ADOEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEA_SHIFT)) & ASRC_ASRIER_ADOEA_MASK)
#define ASRC_ASRIER_ADOEB_MASK (0x10U)
#define ASRC_ASRIER_ADOEB_SHIFT (4U)
/*! ADOEB - ADOEB
* 0b1..interrupt enabled
* 0b0..interrupt disabled
*/
#define ASRC_ASRIER_ADOEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEB_SHIFT)) & ASRC_ASRIER_ADOEB_MASK)
#define ASRC_ASRIER_ADOEC_MASK (0x20U)
#define ASRC_ASRIER_ADOEC_SHIFT (5U)
/*! ADOEC - ADOEC
* 0b1..interrupt enabled
* 0b0..interrupt disabled
*/
#define ASRC_ASRIER_ADOEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_ADOEC_SHIFT)) & ASRC_ASRIER_ADOEC_MASK)
#define ASRC_ASRIER_AOLIE_MASK (0x40U)
#define ASRC_ASRIER_AOLIE_SHIFT (6U)
/*! AOLIE - AOLIE
* 0b1..interrupt enabled
* 0b0..interrupt disabled
*/
#define ASRC_ASRIER_AOLIE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AOLIE_SHIFT)) & ASRC_ASRIER_AOLIE_MASK)
#define ASRC_ASRIER_AFPWE_MASK (0x80U)
#define ASRC_ASRIER_AFPWE_SHIFT (7U)
/*! AFPWE - AFPWE
* 0b1..interrupt enabled
* 0b0..interrupt disabled
*/
#define ASRC_ASRIER_AFPWE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIER_AFPWE_SHIFT)) & ASRC_ASRIER_AFPWE_MASK)
/*! @} */
/*! @name ASRCNCR - ASRC Channel Number Configuration Register */
/*! @{ */
#define ASRC_ASRCNCR_ANCA_MASK (0xFU)
#define ASRC_ASRCNCR_ANCA_SHIFT (0U)
/*! ANCA - ANCA
* 0b0000..0 channels in A (Pair A is disabled)
* 0b0001..1 channel in A
* 0b0010..2 channels in A
* 0b0011..3 channels in A
* 0b0100..4 channels in A
* 0b0101..5 channels in A
* 0b0110..6 channels in A
* 0b0111..7 channels in A
* 0b1000..8 channels in A
* 0b1001..9 channels in A
* 0b1010..10 channels in A
* 0b1011-0b1111..Should not be used.
*/
#define ASRC_ASRCNCR_ANCA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCA_SHIFT)) & ASRC_ASRCNCR_ANCA_MASK)
#define ASRC_ASRCNCR_ANCB_MASK (0xF0U)
#define ASRC_ASRCNCR_ANCB_SHIFT (4U)
/*! ANCB - ANCB
* 0b0000..0 channels in B (Pair B is disabled)
* 0b0001..1 channel in B
* 0b0010..2 channels in B
* 0b0011..3 channels in B
* 0b0100..4 channels in B
* 0b0101..5 channels in B
* 0b0110..6 channels in B
* 0b0111..7 channels in B
* 0b1000..8 channels in B
* 0b1001..9 channels in B
* 0b1010..10 channels in B
* 0b1011-0b1111..Should not be used.
*/
#define ASRC_ASRCNCR_ANCB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCB_SHIFT)) & ASRC_ASRCNCR_ANCB_MASK)
#define ASRC_ASRCNCR_ANCC_MASK (0xF00U)
#define ASRC_ASRCNCR_ANCC_SHIFT (8U)
/*! ANCC - ANCC
* 0b0000..0 channels in C (Pair C is disabled)
* 0b0001..1 channel in C
* 0b0010..2 channels in C
* 0b0011..3 channels in C
* 0b0100..4 channels in C
* 0b0101..5 channels in C
* 0b0110..6 channels in C
* 0b0111..7 channels in C
* 0b1000..8 channels in C
* 0b1001..9 channels in C
* 0b1010..10 channels in C
* 0b1011-0b1111..Should not be used.
*/
#define ASRC_ASRCNCR_ANCC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCNCR_ANCC_SHIFT)) & ASRC_ASRCNCR_ANCC_MASK)
/*! @} */
/*! @name ASRCFG - ASRC Filter Configuration Status Register */
/*! @{ */
#define ASRC_ASRCFG_PREMODA_MASK (0xC0U)
#define ASRC_ASRCFG_PREMODA_SHIFT (6U)
/*! PREMODA - PREMODA
* 0b00..Select Upsampling-by-2
* 0b01..Select Direct-Connection
* 0b10..Select Downsampling-by-2
* 0b11..Select passthrough mode. In this case, POSTMODA[1:0] have no use.
*/
#define ASRC_ASRCFG_PREMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODA_SHIFT)) & ASRC_ASRCFG_PREMODA_MASK)
#define ASRC_ASRCFG_POSTMODA_MASK (0x300U)
#define ASRC_ASRCFG_POSTMODA_SHIFT (8U)
/*! POSTMODA - POSTMODA
* 0b00..Select Upsampling-by-2
* 0b01..Select Direct-Connection
* 0b10..Select Downsampling-by-2
* 0b11..Reserved.
*/
#define ASRC_ASRCFG_POSTMODA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODA_SHIFT)) & ASRC_ASRCFG_POSTMODA_MASK)
#define ASRC_ASRCFG_PREMODB_MASK (0xC00U)
#define ASRC_ASRCFG_PREMODB_SHIFT (10U)
/*! PREMODB - PREMODB
* 0b00..Select Upsampling-by-2
* 0b01..Select Direct-Connection
* 0b10..Select Downsampling-by-2
* 0b11..Select passthrough mode. In this case, POSTMODB[1:0] have no use.
*/
#define ASRC_ASRCFG_PREMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODB_SHIFT)) & ASRC_ASRCFG_PREMODB_MASK)
#define ASRC_ASRCFG_POSTMODB_MASK (0x3000U)
#define ASRC_ASRCFG_POSTMODB_SHIFT (12U)
/*! POSTMODB - POSTMODB
* 0b00..Select Upsampling-by-2
* 0b01..Select Direct-Connection
* 0b10..Select Downsampling-by-2
* 0b11..Reserved.
*/
#define ASRC_ASRCFG_POSTMODB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODB_SHIFT)) & ASRC_ASRCFG_POSTMODB_MASK)
#define ASRC_ASRCFG_PREMODC_MASK (0xC000U)
#define ASRC_ASRCFG_PREMODC_SHIFT (14U)
/*! PREMODC - PREMODC
* 0b00..Select Upsampling-by-2
* 0b01..Select Direct-Connection
* 0b10..Select Downsampling-by-2
* 0b11..Select passthrough mode. In this case, POSTMODC[1:0] have no use.
*/
#define ASRC_ASRCFG_PREMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_PREMODC_SHIFT)) & ASRC_ASRCFG_PREMODC_MASK)
#define ASRC_ASRCFG_POSTMODC_MASK (0x30000U)
#define ASRC_ASRCFG_POSTMODC_SHIFT (16U)
/*! POSTMODC - POSTMODC
* 0b00..Select Upsampling-by-2 as defined in Signal Processing Flow.
* 0b01..Select Direct-Connection as defined in Signal Processing Flow.
* 0b10..Select Downsampling-by-2 as defined in Signal Processing Flow.
* 0b11..Reserved.
*/
#define ASRC_ASRCFG_POSTMODC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_POSTMODC_SHIFT)) & ASRC_ASRCFG_POSTMODC_MASK)
#define ASRC_ASRCFG_NDPRA_MASK (0x40000U)
#define ASRC_ASRCFG_NDPRA_SHIFT (18U)
/*! NDPRA - NDPRA
* 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
* 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
*/
#define ASRC_ASRCFG_NDPRA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRA_SHIFT)) & ASRC_ASRCFG_NDPRA_MASK)
#define ASRC_ASRCFG_NDPRB_MASK (0x80000U)
#define ASRC_ASRCFG_NDPRB_SHIFT (19U)
/*! NDPRB - NDPRB
* 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
* 0b1..Don't use default parameters for RAM-stored parameter. Use the parameters already stored in RAM.
*/
#define ASRC_ASRCFG_NDPRB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRB_SHIFT)) & ASRC_ASRCFG_NDPRB_MASK)
#define ASRC_ASRCFG_NDPRC_MASK (0x100000U)
#define ASRC_ASRCFG_NDPRC_SHIFT (20U)
/*! NDPRC - NDPRC
* 0b0..Use default parameters for RAM-stored parameters. Override any parameters already in RAM.
* 0b1..Don't use default parameters for RAM-stored parameters. Use the parameters already stored in RAM.
*/
#define ASRC_ASRCFG_NDPRC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_NDPRC_SHIFT)) & ASRC_ASRCFG_NDPRC_MASK)
#define ASRC_ASRCFG_INIRQA_MASK (0x200000U)
#define ASRC_ASRCFG_INIRQA_SHIFT (21U)
/*! INIRQA - INIRQA
* 0b0..Initialization for Conversion Pair A not served
* 0b1..Initialization for Conversion Pair A served
*/
#define ASRC_ASRCFG_INIRQA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQA_SHIFT)) & ASRC_ASRCFG_INIRQA_MASK)
#define ASRC_ASRCFG_INIRQB_MASK (0x400000U)
#define ASRC_ASRCFG_INIRQB_SHIFT (22U)
/*! INIRQB - INIRQB
* 0b0..Initialization for Conversion Pair B not served
* 0b1..Initialization for Conversion Pair B served
*/
#define ASRC_ASRCFG_INIRQB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQB_SHIFT)) & ASRC_ASRCFG_INIRQB_MASK)
#define ASRC_ASRCFG_INIRQC_MASK (0x800000U)
#define ASRC_ASRCFG_INIRQC_SHIFT (23U)
/*! INIRQC - INIRQC
* 0b0..Initialization for Conversion Pair C not served
* 0b1..Initialization for Conversion Pair C served
*/
#define ASRC_ASRCFG_INIRQC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCFG_INIRQC_SHIFT)) & ASRC_ASRCFG_INIRQC_MASK)
/*! @} */
/*! @name ASRCSR - ASRC Clock Source Register */
/*! @{ */
#define ASRC_ASRCSR_AICSA_MASK (0xFU)
#define ASRC_ASRCSR_AICSA_SHIFT (0U)
/*! AICSA - AICSA
* 0b0000..bit clock 0
* 0b0001..bit clock 1
* 0b0010..bit clock 2
* 0b0011..bit clock 3
* 0b0100..bit clock 4
* 0b0101..bit clock 5
* 0b0110..bit clock 6
* 0b0111..bit clock 7
* 0b1000..bit clock 8
* 0b1001..bit clock 9
* 0b1010..bit clock A
* 0b1011..bit clock B
* 0b1100..bit clock C
* 0b1101..bit clock D
* 0b1110..bit clock E
* 0b1111..clock disabled, connected to zero
*/
#define ASRC_ASRCSR_AICSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSA_SHIFT)) & ASRC_ASRCSR_AICSA_MASK)
#define ASRC_ASRCSR_AICSB_MASK (0xF0U)
#define ASRC_ASRCSR_AICSB_SHIFT (4U)
/*! AICSB - AICSB
* 0b0000..bit clock 0
* 0b0001..bit clock 1
* 0b0010..bit clock 2
* 0b0011..bit clock 3
* 0b0100..bit clock 4
* 0b0101..bit clock 5
* 0b0110..bit clock 6
* 0b0111..bit clock 7
* 0b1000..bit clock 8
* 0b1001..bit clock 9
* 0b1010..bit clock A
* 0b1011..bit clock B
* 0b1100..bit clock C
* 0b1101..bit clock D
* 0b1110..bit clock E
* 0b1111..clock disabled, connected to zero
*/
#define ASRC_ASRCSR_AICSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSB_SHIFT)) & ASRC_ASRCSR_AICSB_MASK)
#define ASRC_ASRCSR_AICSC_MASK (0xF00U)
#define ASRC_ASRCSR_AICSC_SHIFT (8U)
/*! AICSC - AICSC
* 0b0000..bit clock 0
* 0b0001..bit clock 1
* 0b0010..bit clock 2
* 0b0011..bit clock 3
* 0b0100..bit clock 4
* 0b0101..bit clock 5
* 0b0110..bit clock 6
* 0b0111..bit clock 7
* 0b1000..bit clock 8
* 0b1001..bit clock 9
* 0b1010..bit clock A
* 0b1011..bit clock B
* 0b1100..bit clock C
* 0b1101..bit clock D
* 0b1110..bit clock E
* 0b1111..clock disabled, connected to zero
*/
#define ASRC_ASRCSR_AICSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AICSC_SHIFT)) & ASRC_ASRCSR_AICSC_MASK)
#define ASRC_ASRCSR_AOCSA_MASK (0xF000U)
#define ASRC_ASRCSR_AOCSA_SHIFT (12U)
/*! AOCSA - AOCSA
* 0b0000..bit clock 0
* 0b0001..bit clock 1
* 0b0010..bit clock 2
* 0b0011..bit clock 3
* 0b0100..bit clock 4
* 0b0101..bit clock 5
* 0b0110..bit clock 6
* 0b0111..bit clock 7
* 0b1000..bit clock 8
* 0b1001..bit clock 9
* 0b1010..bit clock A
* 0b1011..bit clock B
* 0b1100..bit clock C
* 0b1101..bit clock D
* 0b1110..bit clock E
* 0b1111..clock disabled, connected to zero
*/
#define ASRC_ASRCSR_AOCSA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSA_SHIFT)) & ASRC_ASRCSR_AOCSA_MASK)
#define ASRC_ASRCSR_AOCSB_MASK (0xF0000U)
#define ASRC_ASRCSR_AOCSB_SHIFT (16U)
/*! AOCSB - AOCSB
* 0b0000..bit clock 0
* 0b0001..bit clock 1
* 0b0010..bit clock 2
* 0b0011..bit clock 3
* 0b0100..bit clock 4
* 0b0101..bit clock 5
* 0b0110..bit clock 6
* 0b0111..bit clock 7
* 0b1000..bit clock 8
* 0b1001..bit clock 9
* 0b1010..bit clock A
* 0b1011..bit clock B
* 0b1100..bit clock C
* 0b1101..bit clock D
* 0b1110..bit clock E
* 0b1111..clock disabled, connected to zero
*/
#define ASRC_ASRCSR_AOCSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSB_SHIFT)) & ASRC_ASRCSR_AOCSB_MASK)
#define ASRC_ASRCSR_AOCSC_MASK (0xF00000U)
#define ASRC_ASRCSR_AOCSC_SHIFT (20U)
/*! AOCSC - AOCSC
* 0b0000..bit clock 0
* 0b0001..bit clock 1
* 0b0010..bit clock 2
* 0b0011..bit clock 3
* 0b0100..bit clock 4
* 0b0101..bit clock 5
* 0b0110..bit clock 6
* 0b0111..bit clock 7
* 0b1000..bit clock 8
* 0b1001..bit clock 9
* 0b1010..bit clock A
* 0b1011..bit clock B
* 0b1100..bit clock C
* 0b1101..bit clock D
* 0b1110..bit clock E
* 0b1111..clock disabled, connected to zero
*/
#define ASRC_ASRCSR_AOCSC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCSR_AOCSC_SHIFT)) & ASRC_ASRCSR_AOCSC_MASK)
/*! @} */
/*! @name ASRCDR1 - ASRC Clock Divider Register 1 */
/*! @{ */
#define ASRC_ASRCDR1_AICPA_MASK (0x7U)
#define ASRC_ASRCDR1_AICPA_SHIFT (0U)
/*! AICPA - AICPA
*/
#define ASRC_ASRCDR1_AICPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPA_SHIFT)) & ASRC_ASRCDR1_AICPA_MASK)
#define ASRC_ASRCDR1_AICDA_MASK (0x38U)
#define ASRC_ASRCDR1_AICDA_SHIFT (3U)
/*! AICDA - AICDA
*/
#define ASRC_ASRCDR1_AICDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDA_SHIFT)) & ASRC_ASRCDR1_AICDA_MASK)
#define ASRC_ASRCDR1_AICPB_MASK (0x1C0U)
#define ASRC_ASRCDR1_AICPB_SHIFT (6U)
/*! AICPB - AICPB
*/
#define ASRC_ASRCDR1_AICPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICPB_SHIFT)) & ASRC_ASRCDR1_AICPB_MASK)
#define ASRC_ASRCDR1_AICDB_MASK (0xE00U)
#define ASRC_ASRCDR1_AICDB_SHIFT (9U)
/*! AICDB - AICDB
*/
#define ASRC_ASRCDR1_AICDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AICDB_SHIFT)) & ASRC_ASRCDR1_AICDB_MASK)
#define ASRC_ASRCDR1_AOCPA_MASK (0x7000U)
#define ASRC_ASRCDR1_AOCPA_SHIFT (12U)
/*! AOCPA - AOCPA
*/
#define ASRC_ASRCDR1_AOCPA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPA_SHIFT)) & ASRC_ASRCDR1_AOCPA_MASK)
#define ASRC_ASRCDR1_AOCDA_MASK (0x38000U)
#define ASRC_ASRCDR1_AOCDA_SHIFT (15U)
/*! AOCDA - AOCDA
*/
#define ASRC_ASRCDR1_AOCDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDA_SHIFT)) & ASRC_ASRCDR1_AOCDA_MASK)
#define ASRC_ASRCDR1_AOCPB_MASK (0x1C0000U)
#define ASRC_ASRCDR1_AOCPB_SHIFT (18U)
/*! AOCPB - AOCPB
*/
#define ASRC_ASRCDR1_AOCPB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCPB_SHIFT)) & ASRC_ASRCDR1_AOCPB_MASK)
#define ASRC_ASRCDR1_AOCDB_MASK (0xE00000U)
#define ASRC_ASRCDR1_AOCDB_SHIFT (21U)
/*! AOCDB - AOCDB
*/
#define ASRC_ASRCDR1_AOCDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR1_AOCDB_SHIFT)) & ASRC_ASRCDR1_AOCDB_MASK)
/*! @} */
/*! @name ASRCDR2 - ASRC Clock Divider Register 2 */
/*! @{ */
#define ASRC_ASRCDR2_AICPC_MASK (0x7U)
#define ASRC_ASRCDR2_AICPC_SHIFT (0U)
/*! AICPC - AICPC
*/
#define ASRC_ASRCDR2_AICPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICPC_SHIFT)) & ASRC_ASRCDR2_AICPC_MASK)
#define ASRC_ASRCDR2_AICDC_MASK (0x38U)
#define ASRC_ASRCDR2_AICDC_SHIFT (3U)
/*! AICDC - AICDC
*/
#define ASRC_ASRCDR2_AICDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AICDC_SHIFT)) & ASRC_ASRCDR2_AICDC_MASK)
#define ASRC_ASRCDR2_AOCPC_MASK (0x1C0U)
#define ASRC_ASRCDR2_AOCPC_SHIFT (6U)
/*! AOCPC - AOCPC
*/
#define ASRC_ASRCDR2_AOCPC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCPC_SHIFT)) & ASRC_ASRCDR2_AOCPC_MASK)
#define ASRC_ASRCDR2_AOCDC_MASK (0xE00U)
#define ASRC_ASRCDR2_AOCDC_SHIFT (9U)
/*! AOCDC - AOCDC
*/
#define ASRC_ASRCDR2_AOCDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCDR2_AOCDC_SHIFT)) & ASRC_ASRCDR2_AOCDC_MASK)
/*! @} */
/*! @name ASRSTR - ASRC Status Register */
/*! @{ */
#define ASRC_ASRSTR_AIDEA_MASK (0x1U)
#define ASRC_ASRSTR_AIDEA_SHIFT (0U)
/*! AIDEA - AIDEA
* 0b1..When AIDEA is set, the ASRC generates data input A interrupt request to the processor if ASRIER[AIDEA] = 1
* 0b0..The threshold has been met and no data input A interrupt is generated
*/
#define ASRC_ASRSTR_AIDEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEA_SHIFT)) & ASRC_ASRSTR_AIDEA_MASK)
#define ASRC_ASRSTR_AIDEB_MASK (0x2U)
#define ASRC_ASRSTR_AIDEB_SHIFT (1U)
/*! AIDEB - AIDEB
* 0b1..When AIDEB is set, the ASRC generates data input B interrupt request to the processor if ASRIER[AIDEB] = 1
* 0b0..The threshold has been met and no data input B interrupt is generated
*/
#define ASRC_ASRSTR_AIDEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEB_SHIFT)) & ASRC_ASRSTR_AIDEB_MASK)
#define ASRC_ASRSTR_AIDEC_MASK (0x4U)
#define ASRC_ASRSTR_AIDEC_SHIFT (2U)
/*! AIDEC - AIDEC
* 0b1..When AIDEC is set, the ASRC generates data input C interrupt request to the processor if ASRIER[AIDEC] = 1
* 0b0..The threshold has been met and no data input C interrupt is generated
*/
#define ASRC_ASRSTR_AIDEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDEC_SHIFT)) & ASRC_ASRSTR_AIDEC_MASK)
#define ASRC_ASRSTR_AODFA_MASK (0x8U)
#define ASRC_ASRSTR_AODFA_SHIFT (3U)
/*! AODFA - AODFA
* 0b1..When AODFA is set, the ASRC generates data output A interrupt request to the processor if ASRIER[ADOEA] = 1
* 0b0..The threshold has not yet been met and no data output A interrupt is generated
*/
#define ASRC_ASRSTR_AODFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFA_SHIFT)) & ASRC_ASRSTR_AODFA_MASK)
#define ASRC_ASRSTR_AODFB_MASK (0x10U)
#define ASRC_ASRSTR_AODFB_SHIFT (4U)
/*! AODFB - AODFB
* 0b1..When AODFB is set, the ASRC generates data output B interrupt request to the processor if ASRIER[ADOEB] = 1
* 0b0..The threshold has not yet been met and no data output B interrupt is generated
*/
#define ASRC_ASRSTR_AODFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFB_SHIFT)) & ASRC_ASRSTR_AODFB_MASK)
#define ASRC_ASRSTR_AODFC_MASK (0x20U)
#define ASRC_ASRSTR_AODFC_SHIFT (5U)
/*! AODFC - AODFC
* 0b1..When AODFC is set, the ASRC generates data output C interrupt request to the processor if ASRIER[ADOEC] = 1
* 0b0..The threshold has not yet been met and no data output C interrupt is generated
*/
#define ASRC_ASRSTR_AODFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODFC_SHIFT)) & ASRC_ASRSTR_AODFC_MASK)
#define ASRC_ASRSTR_AOLE_MASK (0x40U)
#define ASRC_ASRSTR_AOLE_SHIFT (6U)
/*! AOLE - AOLE
* 0b1..Task rate is too high
* 0b0..No overload
*/
#define ASRC_ASRSTR_AOLE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOLE_SHIFT)) & ASRC_ASRSTR_AOLE_MASK)
#define ASRC_ASRSTR_FPWT_MASK (0x80U)
#define ASRC_ASRSTR_FPWT_SHIFT (7U)
/*! FPWT - FPWT
* 0b0..ASRC is not in wait state
* 0b1..ASRC is in wait state
*/
#define ASRC_ASRSTR_FPWT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_FPWT_SHIFT)) & ASRC_ASRSTR_FPWT_MASK)
#define ASRC_ASRSTR_AIDUA_MASK (0x100U)
#define ASRC_ASRSTR_AIDUA_SHIFT (8U)
/*! AIDUA - AIDUA
* 0b0..No Underflow in Input data buffer A
* 0b1..Underflow in Input data buffer A
*/
#define ASRC_ASRSTR_AIDUA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUA_SHIFT)) & ASRC_ASRSTR_AIDUA_MASK)
#define ASRC_ASRSTR_AIDUB_MASK (0x200U)
#define ASRC_ASRSTR_AIDUB_SHIFT (9U)
/*! AIDUB - AIDUB
* 0b0..No Underflow in Input data buffer B
* 0b1..Underflow in Input data buffer B
*/
#define ASRC_ASRSTR_AIDUB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUB_SHIFT)) & ASRC_ASRSTR_AIDUB_MASK)
#define ASRC_ASRSTR_AIDUC_MASK (0x400U)
#define ASRC_ASRSTR_AIDUC_SHIFT (10U)
/*! AIDUC - AIDUC
* 0b0..No Underflow in Input data buffer C
* 0b1..Underflow in Input data buffer C
*/
#define ASRC_ASRSTR_AIDUC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIDUC_SHIFT)) & ASRC_ASRSTR_AIDUC_MASK)
#define ASRC_ASRSTR_AODOA_MASK (0x800U)
#define ASRC_ASRSTR_AODOA_SHIFT (11U)
/*! AODOA - AODOA
* 0b0..No Overflow in Output data buffer A
* 0b1..Overflow in Output data buffer A
*/
#define ASRC_ASRSTR_AODOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOA_SHIFT)) & ASRC_ASRSTR_AODOA_MASK)
#define ASRC_ASRSTR_AODOB_MASK (0x1000U)
#define ASRC_ASRSTR_AODOB_SHIFT (12U)
/*! AODOB - AODOB
* 0b0..No Overflow in Output data buffer B
* 0b1..Overflow in Output data buffer B
*/
#define ASRC_ASRSTR_AODOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOB_SHIFT)) & ASRC_ASRSTR_AODOB_MASK)
#define ASRC_ASRSTR_AODOC_MASK (0x2000U)
#define ASRC_ASRSTR_AODOC_SHIFT (13U)
/*! AODOC - AODOC
* 0b0..No Overflow in Output data buffer C
* 0b1..Overflow in Output data buffer C
*/
#define ASRC_ASRSTR_AODOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AODOC_SHIFT)) & ASRC_ASRSTR_AODOC_MASK)
#define ASRC_ASRSTR_AIOLA_MASK (0x4000U)
#define ASRC_ASRSTR_AIOLA_SHIFT (14U)
/*! AIOLA - AIOLA
* 0b0..Pair A input task is not oveloaded
* 0b1..Pair A input task is oveloaded
*/
#define ASRC_ASRSTR_AIOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLA_SHIFT)) & ASRC_ASRSTR_AIOLA_MASK)
#define ASRC_ASRSTR_AIOLB_MASK (0x8000U)
#define ASRC_ASRSTR_AIOLB_SHIFT (15U)
/*! AIOLB - AIOLB
* 0b0..Pair B input task is not oveloaded
* 0b1..Pair B input task is oveloaded
*/
#define ASRC_ASRSTR_AIOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLB_SHIFT)) & ASRC_ASRSTR_AIOLB_MASK)
#define ASRC_ASRSTR_AIOLC_MASK (0x10000U)
#define ASRC_ASRSTR_AIOLC_SHIFT (16U)
/*! AIOLC - AIOLC
* 0b0..Pair C input task is not oveloaded
* 0b1..Pair C input task is oveloaded
*/
#define ASRC_ASRSTR_AIOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AIOLC_SHIFT)) & ASRC_ASRSTR_AIOLC_MASK)
#define ASRC_ASRSTR_AOOLA_MASK (0x20000U)
#define ASRC_ASRSTR_AOOLA_SHIFT (17U)
/*! AOOLA - AOOLA
* 0b0..Pair A output task is not oveloaded
* 0b1..Pair A output task is oveloaded
*/
#define ASRC_ASRSTR_AOOLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLA_SHIFT)) & ASRC_ASRSTR_AOOLA_MASK)
#define ASRC_ASRSTR_AOOLB_MASK (0x40000U)
#define ASRC_ASRSTR_AOOLB_SHIFT (18U)
/*! AOOLB - AOOLB
* 0b0..Pair B output task is not oveloaded
* 0b1..Pair B output task is oveloaded
*/
#define ASRC_ASRSTR_AOOLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLB_SHIFT)) & ASRC_ASRSTR_AOOLB_MASK)
#define ASRC_ASRSTR_AOOLC_MASK (0x80000U)
#define ASRC_ASRSTR_AOOLC_SHIFT (19U)
/*! AOOLC - AOOLC
* 0b0..Pair C output task is not oveloaded
* 0b1..Pair C output task is oveloaded
*/
#define ASRC_ASRSTR_AOOLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_AOOLC_SHIFT)) & ASRC_ASRSTR_AOOLC_MASK)
#define ASRC_ASRSTR_ATQOL_MASK (0x100000U)
#define ASRC_ASRSTR_ATQOL_SHIFT (20U)
/*! ATQOL - ATQOL
* 0b0..Task queue FIFO logic is not oveloaded
* 0b1..Task queue FIFO logic is oveloaded
*/
#define ASRC_ASRSTR_ATQOL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_ATQOL_SHIFT)) & ASRC_ASRSTR_ATQOL_MASK)
#define ASRC_ASRSTR_DSLCNT_MASK (0x200000U)
#define ASRC_ASRSTR_DSLCNT_SHIFT (21U)
/*! DSLCNT - DSLCNT
* 0b0..New DSL counter information is in the process of storage into the internal ASRC FIFO
* 0b1..New DSL counter information is stored in the internal ASRC FIFO
*/
#define ASRC_ASRSTR_DSLCNT(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRSTR_DSLCNT_SHIFT)) & ASRC_ASRSTR_DSLCNT_MASK)
/*! @} */
/*! @name ASRPM - ASRC Parameter Register n */
/*! @{ */
#define ASRC_ASRPM_PARAMETER_VALUE_MASK (0xFFFFFFU)
#define ASRC_ASRPM_PARAMETER_VALUE_SHIFT (0U)
/*! PARAMETER_VALUE - PARAMETER_VALUE
*/
#define ASRC_ASRPM_PARAMETER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRPM_PARAMETER_VALUE_SHIFT)) & ASRC_ASRPM_PARAMETER_VALUE_MASK)
/*! @} */
/* The count of ASRC_ASRPM */
#define ASRC_ASRPM_COUNT (5U)
/*! @name ASRTFR1 - ASRC Task Queue FIFO Register 1 */
/*! @{ */
#define ASRC_ASRTFR1_TF_BASE_MASK (0x1FC0U)
#define ASRC_ASRTFR1_TF_BASE_SHIFT (6U)
/*! TF_BASE - TF_BASE
*/
#define ASRC_ASRTFR1_TF_BASE(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_BASE_SHIFT)) & ASRC_ASRTFR1_TF_BASE_MASK)
#define ASRC_ASRTFR1_TF_FILL_MASK (0xFE000U)
#define ASRC_ASRTFR1_TF_FILL_SHIFT (13U)
/*! TF_FILL - TF_FILL
*/
#define ASRC_ASRTFR1_TF_FILL(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRTFR1_TF_FILL_SHIFT)) & ASRC_ASRTFR1_TF_FILL_MASK)
/*! @} */
/*! @name ASRCCR - ASRC Channel Counter Register */
/*! @{ */
#define ASRC_ASRCCR_ACIA_MASK (0xFU)
#define ASRC_ASRCCR_ACIA_SHIFT (0U)
/*! ACIA - ACIA
*/
#define ASRC_ASRCCR_ACIA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIA_SHIFT)) & ASRC_ASRCCR_ACIA_MASK)
#define ASRC_ASRCCR_ACIB_MASK (0xF0U)
#define ASRC_ASRCCR_ACIB_SHIFT (4U)
/*! ACIB - ACIB
*/
#define ASRC_ASRCCR_ACIB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIB_SHIFT)) & ASRC_ASRCCR_ACIB_MASK)
#define ASRC_ASRCCR_ACIC_MASK (0xF00U)
#define ASRC_ASRCCR_ACIC_SHIFT (8U)
/*! ACIC - ACIC
*/
#define ASRC_ASRCCR_ACIC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACIC_SHIFT)) & ASRC_ASRCCR_ACIC_MASK)
#define ASRC_ASRCCR_ACOA_MASK (0xF000U)
#define ASRC_ASRCCR_ACOA_SHIFT (12U)
/*! ACOA - ACOA
*/
#define ASRC_ASRCCR_ACOA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOA_SHIFT)) & ASRC_ASRCCR_ACOA_MASK)
#define ASRC_ASRCCR_ACOB_MASK (0xF0000U)
#define ASRC_ASRCCR_ACOB_SHIFT (16U)
/*! ACOB - ACOB
*/
#define ASRC_ASRCCR_ACOB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOB_SHIFT)) & ASRC_ASRCCR_ACOB_MASK)
#define ASRC_ASRCCR_ACOC_MASK (0xF00000U)
#define ASRC_ASRCCR_ACOC_SHIFT (20U)
/*! ACOC - ACOC
*/
#define ASRC_ASRCCR_ACOC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRCCR_ACOC_SHIFT)) & ASRC_ASRCCR_ACOC_MASK)
/*! @} */
/*! @name ASRDIA - ASRC Data Input Register for Pair x */
/*! @{ */
#define ASRC_ASRDIA_DATA_MASK (0xFFFFFFU)
#define ASRC_ASRDIA_DATA_SHIFT (0U)
/*! DATA - DATA
*/
#define ASRC_ASRDIA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIA_DATA_SHIFT)) & ASRC_ASRDIA_DATA_MASK)
/*! @} */
/*! @name ASRDOA - ASRC Data Output Register for Pair x */
/*! @{ */
#define ASRC_ASRDOA_DATA_MASK (0xFFFFFFU)
#define ASRC_ASRDOA_DATA_SHIFT (0U)
/*! DATA - DATA
*/
#define ASRC_ASRDOA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOA_DATA_SHIFT)) & ASRC_ASRDOA_DATA_MASK)
/*! @} */
/*! @name ASRDIB - ASRC Data Input Register for Pair x */
/*! @{ */
#define ASRC_ASRDIB_DATA_MASK (0xFFFFFFU)
#define ASRC_ASRDIB_DATA_SHIFT (0U)
/*! DATA - DATA
*/
#define ASRC_ASRDIB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIB_DATA_SHIFT)) & ASRC_ASRDIB_DATA_MASK)
/*! @} */
/*! @name ASRDOB - ASRC Data Output Register for Pair x */
/*! @{ */
#define ASRC_ASRDOB_DATA_MASK (0xFFFFFFU)
#define ASRC_ASRDOB_DATA_SHIFT (0U)
/*! DATA - DATA
*/
#define ASRC_ASRDOB_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOB_DATA_SHIFT)) & ASRC_ASRDOB_DATA_MASK)
/*! @} */
/*! @name ASRDIC - ASRC Data Input Register for Pair x */
/*! @{ */
#define ASRC_ASRDIC_DATA_MASK (0xFFFFFFU)
#define ASRC_ASRDIC_DATA_SHIFT (0U)
/*! DATA - DATA
*/
#define ASRC_ASRDIC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDIC_DATA_SHIFT)) & ASRC_ASRDIC_DATA_MASK)
/*! @} */
/*! @name ASRDOC - ASRC Data Output Register for Pair x */
/*! @{ */
#define ASRC_ASRDOC_DATA_MASK (0xFFFFFFU)
#define ASRC_ASRDOC_DATA_SHIFT (0U)
/*! DATA - DATA
*/
#define ASRC_ASRDOC_DATA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRDOC_DATA_SHIFT)) & ASRC_ASRDOC_DATA_MASK)
/*! @} */
/*! @name ASRIDRHA - ASRC Ideal Ratio for Pair A-High Part */
/*! @{ */
#define ASRC_ASRIDRHA_IDRATIOA_H_MASK (0xFFU)
#define ASRC_ASRIDRHA_IDRATIOA_H_SHIFT (0U)
/*! IDRATIOA_H - IDRATIOA_H
*/
#define ASRC_ASRIDRHA_IDRATIOA_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHA_IDRATIOA_H_SHIFT)) & ASRC_ASRIDRHA_IDRATIOA_H_MASK)
/*! @} */
/*! @name ASRIDRLA - ASRC Ideal Ratio for Pair A -Low Part */
/*! @{ */
#define ASRC_ASRIDRLA_IDRATIOA_L_MASK (0xFFFFFFU)
#define ASRC_ASRIDRLA_IDRATIOA_L_SHIFT (0U)
/*! IDRATIOA_L - IDRATIOA_L
*/
#define ASRC_ASRIDRLA_IDRATIOA_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLA_IDRATIOA_L_SHIFT)) & ASRC_ASRIDRLA_IDRATIOA_L_MASK)
/*! @} */
/*! @name ASRIDRHB - ASRC Ideal Ratio for Pair B-High Part */
/*! @{ */
#define ASRC_ASRIDRHB_IDRATIOB_H_MASK (0xFFU)
#define ASRC_ASRIDRHB_IDRATIOB_H_SHIFT (0U)
/*! IDRATIOB_H - IDRATIOB_H
*/
#define ASRC_ASRIDRHB_IDRATIOB_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHB_IDRATIOB_H_SHIFT)) & ASRC_ASRIDRHB_IDRATIOB_H_MASK)
/*! @} */
/*! @name ASRIDRLB - ASRC Ideal Ratio for Pair B-Low Part */
/*! @{ */
#define ASRC_ASRIDRLB_IDRATIOB_L_MASK (0xFFFFFFU)
#define ASRC_ASRIDRLB_IDRATIOB_L_SHIFT (0U)
/*! IDRATIOB_L - IDRATIOB_L
*/
#define ASRC_ASRIDRLB_IDRATIOB_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLB_IDRATIOB_L_SHIFT)) & ASRC_ASRIDRLB_IDRATIOB_L_MASK)
/*! @} */
/*! @name ASRIDRHC - ASRC Ideal Ratio for Pair C-High Part */
/*! @{ */
#define ASRC_ASRIDRHC_IDRATIOC_H_MASK (0xFFU)
#define ASRC_ASRIDRHC_IDRATIOC_H_SHIFT (0U)
/*! IDRATIOC_H - IDRATIOC_H
*/
#define ASRC_ASRIDRHC_IDRATIOC_H(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRHC_IDRATIOC_H_SHIFT)) & ASRC_ASRIDRHC_IDRATIOC_H_MASK)
/*! @} */
/*! @name ASRIDRLC - ASRC Ideal Ratio for Pair C-Low Part */
/*! @{ */
#define ASRC_ASRIDRLC_IDRATIOC_L_MASK (0xFFFFFFU)
#define ASRC_ASRIDRLC_IDRATIOC_L_SHIFT (0U)
/*! IDRATIOC_L - IDRATIOC_L
*/
#define ASRC_ASRIDRLC_IDRATIOC_L(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRIDRLC_IDRATIOC_L_SHIFT)) & ASRC_ASRIDRLC_IDRATIOC_L_MASK)
/*! @} */
/*! @name ASR76K - ASRC 76 kHz Period in terms of ASRC processing clock */
/*! @{ */
#define ASRC_ASR76K_ASR76K_MASK (0x1FFFFU)
#define ASRC_ASR76K_ASR76K_SHIFT (0U)
/*! ASR76K - ASR76K
*/
#define ASRC_ASR76K_ASR76K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR76K_ASR76K_SHIFT)) & ASRC_ASR76K_ASR76K_MASK)
/*! @} */
/*! @name ASR56K - ASRC 56 kHz Period in terms of ASRC processing clock */
/*! @{ */
#define ASRC_ASR56K_ASR56K_MASK (0x1FFFFU)
#define ASRC_ASR56K_ASR56K_SHIFT (0U)
/*! ASR56K - ASR56K
*/
#define ASRC_ASR56K_ASR56K(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASR56K_ASR56K_SHIFT)) & ASRC_ASR56K_ASR56K_MASK)
/*! @} */
/*! @name ASRMCRA - ASRC Misc Control Register for Pair A */
/*! @{ */
#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK (0x3FU)
#define ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT (0U)
/*! INFIFO_THRESHOLDA - INFIFO_THRESHOLDA
*/
#define ASRC_ASRMCRA_INFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_INFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_INFIFO_THRESHOLDA_MASK)
#define ASRC_ASRMCRA_RSYNOFA_MASK (0x400U)
#define ASRC_ASRMCRA_RSYNOFA_SHIFT (10U)
/*! RSYNOFA - RSYNOFA
* 0b1..Force ASRCCR[ACOA]=0
* 0b0..Do not touch ASRCCR[ACOA]
*/
#define ASRC_ASRMCRA_RSYNOFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNOFA_SHIFT)) & ASRC_ASRMCRA_RSYNOFA_MASK)
#define ASRC_ASRMCRA_RSYNIFA_MASK (0x800U)
#define ASRC_ASRMCRA_RSYNIFA_SHIFT (11U)
/*! RSYNIFA - RSYNIFA
* 0b1..Force ASRCCR[ACIA]=0
* 0b0..Do not touch ASRCCR[ACIA]
*/
#define ASRC_ASRMCRA_RSYNIFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_RSYNIFA_SHIFT)) & ASRC_ASRMCRA_RSYNIFA_MASK)
#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK (0x3F000U)
#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT (12U)
/*! OUTFIFO_THRESHOLDA - OUTFIFO_THRESHOLDA
*/
#define ASRC_ASRMCRA_OUTFIFO_THRESHOLDA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_SHIFT)) & ASRC_ASRMCRA_OUTFIFO_THRESHOLDA_MASK)
#define ASRC_ASRMCRA_BYPASSPOLYA_MASK (0x100000U)
#define ASRC_ASRMCRA_BYPASSPOLYA_SHIFT (20U)
/*! BYPASSPOLYA - BYPASSPOLYA
* 0b1..Bypass polyphase filtering.
* 0b0..Don't bypass polyphase filtering.
*/
#define ASRC_ASRMCRA_BYPASSPOLYA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BYPASSPOLYA_SHIFT)) & ASRC_ASRMCRA_BYPASSPOLYA_MASK)
#define ASRC_ASRMCRA_BUFSTALLA_MASK (0x200000U)
#define ASRC_ASRMCRA_BUFSTALLA_SHIFT (21U)
/*! BUFSTALLA - BUFSTALLA
* 0b1..Stall Pair A conversion in case of near empty/full FIFO conditions.
* 0b0..Don't stall Pair A conversion even in case of near empty/full FIFO conditions.
*/
#define ASRC_ASRMCRA_BUFSTALLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_BUFSTALLA_SHIFT)) & ASRC_ASRMCRA_BUFSTALLA_MASK)
#define ASRC_ASRMCRA_EXTTHRSHA_MASK (0x400000U)
#define ASRC_ASRMCRA_EXTTHRSHA_SHIFT (22U)
/*! EXTTHRSHA - EXTTHRSHA
* 0b1..Use external defined thresholds.
* 0b0..Use default thresholds.
*/
#define ASRC_ASRMCRA_EXTTHRSHA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_EXTTHRSHA_SHIFT)) & ASRC_ASRMCRA_EXTTHRSHA_MASK)
#define ASRC_ASRMCRA_ZEROBUFA_MASK (0x800000U)
#define ASRC_ASRMCRA_ZEROBUFA_SHIFT (23U)
/*! ZEROBUFA - ZEROBUFA
* 0b1..Don't zeroize the buffer
* 0b0..Zeroize the buffer
*/
#define ASRC_ASRMCRA_ZEROBUFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRA_ZEROBUFA_SHIFT)) & ASRC_ASRMCRA_ZEROBUFA_MASK)
/*! @} */
/*! @name ASRFSTA - ASRC FIFO Status Register for Pair A */
/*! @{ */
#define ASRC_ASRFSTA_INFIFO_FILLA_MASK (0x7FU)
#define ASRC_ASRFSTA_INFIFO_FILLA_SHIFT (0U)
/*! INFIFO_FILLA - INFIFO_FILLA
*/
#define ASRC_ASRFSTA_INFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_INFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_INFIFO_FILLA_MASK)
#define ASRC_ASRFSTA_IAEA_MASK (0x800U)
#define ASRC_ASRFSTA_IAEA_SHIFT (11U)
/*! IAEA - IAEA
* 0b1..Input FIFO is near empty for Pair A
* 0b0..Input FIFO is not near empty for Pair A
*/
#define ASRC_ASRFSTA_IAEA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_IAEA_SHIFT)) & ASRC_ASRFSTA_IAEA_MASK)
#define ASRC_ASRFSTA_OUTFIFO_FILLA_MASK (0x7F000U)
#define ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT (12U)
/*! OUTFIFO_FILLA - OUTFIFO_FILLA
*/
#define ASRC_ASRFSTA_OUTFIFO_FILLA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OUTFIFO_FILLA_SHIFT)) & ASRC_ASRFSTA_OUTFIFO_FILLA_MASK)
#define ASRC_ASRFSTA_OAFA_MASK (0x800000U)
#define ASRC_ASRFSTA_OAFA_SHIFT (23U)
/*! OAFA - OAFA
* 0b1..Output FIFO is near full for Pair A
* 0b0..Output FIFO is not near full for Pair A
*/
#define ASRC_ASRFSTA_OAFA(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTA_OAFA_SHIFT)) & ASRC_ASRFSTA_OAFA_MASK)
/*! @} */
/*! @name ASRMCRB - ASRC Misc Control Register for Pair B */
/*! @{ */
#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK (0x3FU)
#define ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT (0U)
/*! INFIFO_THRESHOLDB - INFIFO_THRESHOLDB
*/
#define ASRC_ASRMCRB_INFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_INFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_INFIFO_THRESHOLDB_MASK)
#define ASRC_ASRMCRB_RSYNOFB_MASK (0x400U)
#define ASRC_ASRMCRB_RSYNOFB_SHIFT (10U)
/*! RSYNOFB - RSYNOFB
* 0b1..Force ASRCCR[ACOB]=0
* 0b0..Do not touch ASRCCR[ACOB]
*/
#define ASRC_ASRMCRB_RSYNOFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNOFB_SHIFT)) & ASRC_ASRMCRB_RSYNOFB_MASK)
#define ASRC_ASRMCRB_RSYNIFB_MASK (0x800U)
#define ASRC_ASRMCRB_RSYNIFB_SHIFT (11U)
/*! RSYNIFB - RSYNIFB
* 0b1..Force ASRCCR[ACIB]=0
* 0b0..Do not touch ASRCCR[ACIB]
*/
#define ASRC_ASRMCRB_RSYNIFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_RSYNIFB_SHIFT)) & ASRC_ASRMCRB_RSYNIFB_MASK)
#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK (0x3F000U)
#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT (12U)
/*! OUTFIFO_THRESHOLDB - OUTFIFO_THRESHOLDB
*/
#define ASRC_ASRMCRB_OUTFIFO_THRESHOLDB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_SHIFT)) & ASRC_ASRMCRB_OUTFIFO_THRESHOLDB_MASK)
#define ASRC_ASRMCRB_BYPASSPOLYB_MASK (0x100000U)
#define ASRC_ASRMCRB_BYPASSPOLYB_SHIFT (20U)
/*! BYPASSPOLYB - BYPASSPOLYB
* 0b1..Bypass polyphase filtering.
* 0b0..Don't bypass polyphase filtering.
*/
#define ASRC_ASRMCRB_BYPASSPOLYB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BYPASSPOLYB_SHIFT)) & ASRC_ASRMCRB_BYPASSPOLYB_MASK)
#define ASRC_ASRMCRB_BUFSTALLB_MASK (0x200000U)
#define ASRC_ASRMCRB_BUFSTALLB_SHIFT (21U)
/*! BUFSTALLB - BUFSTALLB
* 0b1..Stall Pair B conversion in case of near empty/full FIFO conditions.
* 0b0..Don't stall Pair B conversion even in case of near empty/full FIFO conditions.
*/
#define ASRC_ASRMCRB_BUFSTALLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_BUFSTALLB_SHIFT)) & ASRC_ASRMCRB_BUFSTALLB_MASK)
#define ASRC_ASRMCRB_EXTTHRSHB_MASK (0x400000U)
#define ASRC_ASRMCRB_EXTTHRSHB_SHIFT (22U)
/*! EXTTHRSHB - EXTTHRSHB
* 0b1..Use external defined thresholds.
* 0b0..Use default thresholds.
*/
#define ASRC_ASRMCRB_EXTTHRSHB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_EXTTHRSHB_SHIFT)) & ASRC_ASRMCRB_EXTTHRSHB_MASK)
#define ASRC_ASRMCRB_ZEROBUFB_MASK (0x800000U)
#define ASRC_ASRMCRB_ZEROBUFB_SHIFT (23U)
/*! ZEROBUFB - ZEROBUFB
* 0b1..Don't zeroize the buffer
* 0b0..Zeroize the buffer
*/
#define ASRC_ASRMCRB_ZEROBUFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRB_ZEROBUFB_SHIFT)) & ASRC_ASRMCRB_ZEROBUFB_MASK)
/*! @} */
/*! @name ASRFSTB - ASRC FIFO Status Register for Pair B */
/*! @{ */
#define ASRC_ASRFSTB_INFIFO_FILLB_MASK (0x7FU)
#define ASRC_ASRFSTB_INFIFO_FILLB_SHIFT (0U)
/*! INFIFO_FILLB - INFIFO_FILLB
*/
#define ASRC_ASRFSTB_INFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_INFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_INFIFO_FILLB_MASK)
#define ASRC_ASRFSTB_IAEB_MASK (0x800U)
#define ASRC_ASRFSTB_IAEB_SHIFT (11U)
/*! IAEB - IAEB
* 0b1..Input FIFO is near empty for Pair B
* 0b0..Input FIFO is not near empty for Pair B
*/
#define ASRC_ASRFSTB_IAEB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_IAEB_SHIFT)) & ASRC_ASRFSTB_IAEB_MASK)
#define ASRC_ASRFSTB_OUTFIFO_FILLB_MASK (0x7F000U)
#define ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT (12U)
/*! OUTFIFO_FILLB - OUTFIFO_FILLB
*/
#define ASRC_ASRFSTB_OUTFIFO_FILLB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OUTFIFO_FILLB_SHIFT)) & ASRC_ASRFSTB_OUTFIFO_FILLB_MASK)
#define ASRC_ASRFSTB_OAFB_MASK (0x800000U)
#define ASRC_ASRFSTB_OAFB_SHIFT (23U)
/*! OAFB - OAFB
* 0b1..Output FIFO is near full for Pair B
* 0b0..Output FIFO is not near full for Pair B
*/
#define ASRC_ASRFSTB_OAFB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTB_OAFB_SHIFT)) & ASRC_ASRFSTB_OAFB_MASK)
/*! @} */
/*! @name ASRMCRC - ASRC Misc Control Register for Pair C */
/*! @{ */
#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK (0x3FU)
#define ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT (0U)
/*! INFIFO_THRESHOLDC - INFIFO_THRESHOLDC
*/
#define ASRC_ASRMCRC_INFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_INFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_INFIFO_THRESHOLDC_MASK)
#define ASRC_ASRMCRC_RSYNOFC_MASK (0x400U)
#define ASRC_ASRMCRC_RSYNOFC_SHIFT (10U)
/*! RSYNOFC - RSYNOFC
* 0b1..Force ASRCCR[ACOC]=0
* 0b0..Do not touch ASRCCR[ACOC]
*/
#define ASRC_ASRMCRC_RSYNOFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNOFC_SHIFT)) & ASRC_ASRMCRC_RSYNOFC_MASK)
#define ASRC_ASRMCRC_RSYNIFC_MASK (0x800U)
#define ASRC_ASRMCRC_RSYNIFC_SHIFT (11U)
/*! RSYNIFC - RSYNIFC
* 0b1..Force ASRCCR[ACIC]=0
* 0b0..Do not touch ASRCCR[ACIC]
*/
#define ASRC_ASRMCRC_RSYNIFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_RSYNIFC_SHIFT)) & ASRC_ASRMCRC_RSYNIFC_MASK)
#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK (0x3F000U)
#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT (12U)
/*! OUTFIFO_THRESHOLDC - OUTFIFO_THRESHOLDC
*/
#define ASRC_ASRMCRC_OUTFIFO_THRESHOLDC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_SHIFT)) & ASRC_ASRMCRC_OUTFIFO_THRESHOLDC_MASK)
#define ASRC_ASRMCRC_BYPASSPOLYC_MASK (0x100000U)
#define ASRC_ASRMCRC_BYPASSPOLYC_SHIFT (20U)
/*! BYPASSPOLYC - BYPASSPOLYC
* 0b1..Bypass polyphase filtering.
* 0b0..Don't bypass polyphase filtering.
*/
#define ASRC_ASRMCRC_BYPASSPOLYC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BYPASSPOLYC_SHIFT)) & ASRC_ASRMCRC_BYPASSPOLYC_MASK)
#define ASRC_ASRMCRC_BUFSTALLC_MASK (0x200000U)
#define ASRC_ASRMCRC_BUFSTALLC_SHIFT (21U)
/*! BUFSTALLC - BUFSTALLC
* 0b1..Stall Pair C conversion in case of near empty/full FIFO conditions.
* 0b0..Don't stall Pair C conversion even in case of near empty/full FIFO conditions.
*/
#define ASRC_ASRMCRC_BUFSTALLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_BUFSTALLC_SHIFT)) & ASRC_ASRMCRC_BUFSTALLC_MASK)
#define ASRC_ASRMCRC_EXTTHRSHC_MASK (0x400000U)
#define ASRC_ASRMCRC_EXTTHRSHC_SHIFT (22U)
/*! EXTTHRSHC - EXTTHRSHC
* 0b1..Use external defined thresholds.
* 0b0..Use default thresholds.
*/
#define ASRC_ASRMCRC_EXTTHRSHC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_EXTTHRSHC_SHIFT)) & ASRC_ASRMCRC_EXTTHRSHC_MASK)
#define ASRC_ASRMCRC_ZEROBUFC_MASK (0x800000U)
#define ASRC_ASRMCRC_ZEROBUFC_SHIFT (23U)
/*! ZEROBUFC - ZEROBUFC
* 0b1..Don't zeroize the buffer
* 0b0..Zeroize the buffer
*/
#define ASRC_ASRMCRC_ZEROBUFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCRC_ZEROBUFC_SHIFT)) & ASRC_ASRMCRC_ZEROBUFC_MASK)
/*! @} */
/*! @name ASRFSTC - ASRC FIFO Status Register for Pair C */
/*! @{ */
#define ASRC_ASRFSTC_INFIFO_FILLC_MASK (0x7FU)
#define ASRC_ASRFSTC_INFIFO_FILLC_SHIFT (0U)
/*! INFIFO_FILLC - INFIFO_FILLC
*/
#define ASRC_ASRFSTC_INFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_INFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_INFIFO_FILLC_MASK)
#define ASRC_ASRFSTC_IAEC_MASK (0x800U)
#define ASRC_ASRFSTC_IAEC_SHIFT (11U)
/*! IAEC - IAEC
* 0b1..Input FIFO is near empty for Pair C
* 0b0..Input FIFO is not near empty for Pair C
*/
#define ASRC_ASRFSTC_IAEC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_IAEC_SHIFT)) & ASRC_ASRFSTC_IAEC_MASK)
#define ASRC_ASRFSTC_OUTFIFO_FILLC_MASK (0x7F000U)
#define ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT (12U)
/*! OUTFIFO_FILLC - OUTFIFO_FILLC
*/
#define ASRC_ASRFSTC_OUTFIFO_FILLC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OUTFIFO_FILLC_SHIFT)) & ASRC_ASRFSTC_OUTFIFO_FILLC_MASK)
#define ASRC_ASRFSTC_OAFC_MASK (0x800000U)
#define ASRC_ASRFSTC_OAFC_SHIFT (23U)
/*! OAFC - OAFC
* 0b1..Output FIFO is near full for Pair C
* 0b0..Output FIFO is not near full for Pair C
*/
#define ASRC_ASRFSTC_OAFC(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRFSTC_OAFC_SHIFT)) & ASRC_ASRFSTC_OAFC_MASK)
/*! @} */
/*! @name ASRMCR1 - ASRC Misc Control Register 1 for Pair X */
/*! @{ */
#define ASRC_ASRMCR1_OW16_MASK (0x1U)
#define ASRC_ASRMCR1_OW16_SHIFT (0U)
/*! OW16 - OW16
* 0b1..16-bit output data
* 0b0..24-bit output data.
*/
#define ASRC_ASRMCR1_OW16(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OW16_SHIFT)) & ASRC_ASRMCR1_OW16_MASK)
#define ASRC_ASRMCR1_OSGN_MASK (0x2U)
#define ASRC_ASRMCR1_OSGN_SHIFT (1U)
/*! OSGN - OSGN
* 0b1..Sign extension.
* 0b0..No sign extension.
*/
#define ASRC_ASRMCR1_OSGN(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OSGN_SHIFT)) & ASRC_ASRMCR1_OSGN_MASK)
#define ASRC_ASRMCR1_OMSB_MASK (0x4U)
#define ASRC_ASRMCR1_OMSB_SHIFT (2U)
/*! OMSB - OMSB
* 0b1..MSB aligned.
* 0b0..LSB aligned.
*/
#define ASRC_ASRMCR1_OMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_OMSB_SHIFT)) & ASRC_ASRMCR1_OMSB_MASK)
#define ASRC_ASRMCR1_IMSB_MASK (0x100U)
#define ASRC_ASRMCR1_IMSB_SHIFT (8U)
/*! IMSB - IMSB
* 0b1..MSB aligned.
* 0b0..LSB aligned.
*/
#define ASRC_ASRMCR1_IMSB(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IMSB_SHIFT)) & ASRC_ASRMCR1_IMSB_MASK)
#define ASRC_ASRMCR1_IWD_MASK (0x600U)
#define ASRC_ASRMCR1_IWD_SHIFT (9U)
/*! IWD - IWD
* 0b00..24-bit audio data.
* 0b01..16-bit audio data.
* 0b10..8-bit audio data.
* 0b11..Reserved.
*/
#define ASRC_ASRMCR1_IWD(x) (((uint32_t)(((uint32_t)(x)) << ASRC_ASRMCR1_IWD_SHIFT)) & ASRC_ASRMCR1_IWD_MASK)
/*! @} */
/* The count of ASRC_ASRMCR1 */
#define ASRC_ASRMCR1_COUNT (3U)
/*!
* @}
*/ /* end of group ASRC_Register_Masks */
/* ASRC - Peripheral instance base addresses */
/** Peripheral ASRC base address */
#define ASRC_BASE (0x40414000u)
/** Peripheral ASRC base pointer */
#define ASRC ((ASRC_Type *)ASRC_BASE)
/** Array initializer of ASRC peripheral base addresses */
#define ASRC_BASE_ADDRS { ASRC_BASE }
/** Array initializer of ASRC peripheral base pointers */
#define ASRC_BASE_PTRS { ASRC }
/** Interrupt vectors for the ASRC peripheral type */
#define ASRC_IRQS { ASRC_IRQn }
/*!
* @}
*/ /* end of group ASRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- AUDIO_PLL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup AUDIO_PLL_Peripheral_Access_Layer AUDIO_PLL Peripheral Access Layer
* @{
*/
/** AUDIO_PLL - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0 */
__IO uint32_t RW; /**< Fractional PLL Control Register, offset: 0x0 */
__IO uint32_t SET; /**< Fractional PLL Control Register, offset: 0x4 */
__IO uint32_t CLR; /**< Fractional PLL Control Register, offset: 0x8 */
__IO uint32_t TOG; /**< Fractional PLL Control Register, offset: 0xC */
} CTRL0;
struct { /* offset: 0x10 */
__IO uint32_t RW; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
__IO uint32_t SET; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
__IO uint32_t CLR; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
__IO uint32_t TOG; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
} SPREAD_SPECTRUM;
struct { /* offset: 0x20 */
__IO uint32_t RW; /**< Fractional PLL Numerator Control Register, offset: 0x20 */
__IO uint32_t SET; /**< Fractional PLL Numerator Control Register, offset: 0x24 */
__IO uint32_t CLR; /**< Fractional PLL Numerator Control Register, offset: 0x28 */
__IO uint32_t TOG; /**< Fractional PLL Numerator Control Register, offset: 0x2C */
} NUMERATOR;
struct { /* offset: 0x30 */
__IO uint32_t RW; /**< Fractional PLL Denominator Control Register, offset: 0x30 */
__IO uint32_t SET; /**< Fractional PLL Denominator Control Register, offset: 0x34 */
__IO uint32_t CLR; /**< Fractional PLL Denominator Control Register, offset: 0x38 */
__IO uint32_t TOG; /**< Fractional PLL Denominator Control Register, offset: 0x3C */
} DENOMINATOR;
} AUDIO_PLL_Type;
/* ----------------------------------------------------------------------------
-- AUDIO_PLL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup AUDIO_PLL_Register_Masks AUDIO_PLL Register Masks
* @{
*/
/*! @name CTRL0 - Fractional PLL Control Register */
/*! @{ */
#define AUDIO_PLL_CTRL0_DIV_SELECT_MASK (0x7FU)
#define AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT (0U)
/*! DIV_SELECT - DIV_SELECT
*/
#define AUDIO_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DIV_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_DIV_SELECT_MASK)
#define AUDIO_PLL_CTRL0_ENABLE_ALT_MASK (0x100U)
#define AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT (8U)
/*! ENABLE_ALT - ENABLE_ALT
* 0b0..Disable the alternate clock output
* 0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
*/
#define AUDIO_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_ALT_MASK)
#define AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U)
#define AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U)
/*! HOLD_RING_OFF - PLL Start up initialization
* 0b0..Normal operation
* 0b1..Initialize PLL start up
*/
#define AUDIO_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & AUDIO_PLL_CTRL0_HOLD_RING_OFF_MASK)
#define AUDIO_PLL_CTRL0_POWERUP_MASK (0x4000U)
#define AUDIO_PLL_CTRL0_POWERUP_SHIFT (14U)
/*! POWERUP - POWERUP
* 0b1..Power Up the PLL
* 0b0..Power down the PLL
*/
#define AUDIO_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POWERUP_SHIFT)) & AUDIO_PLL_CTRL0_POWERUP_MASK)
#define AUDIO_PLL_CTRL0_ENABLE_MASK (0x8000U)
#define AUDIO_PLL_CTRL0_ENABLE_SHIFT (15U)
/*! ENABLE - ENABLE
* 0b1..Enable the clock output
* 0b0..Disable the clock output
*/
#define AUDIO_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_ENABLE_SHIFT)) & AUDIO_PLL_CTRL0_ENABLE_MASK)
#define AUDIO_PLL_CTRL0_BYPASS_MASK (0x10000U)
#define AUDIO_PLL_CTRL0_BYPASS_SHIFT (16U)
/*! BYPASS - BYPASS
* 0b1..Bypass the PLL
* 0b0..No Bypass
*/
#define AUDIO_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BYPASS_SHIFT)) & AUDIO_PLL_CTRL0_BYPASS_MASK)
#define AUDIO_PLL_CTRL0_DITHER_EN_MASK (0x20000U)
#define AUDIO_PLL_CTRL0_DITHER_EN_SHIFT (17U)
/*! DITHER_EN - DITHER_EN
* 0b0..Disable Dither
* 0b1..Enable Dither
*/
#define AUDIO_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_DITHER_EN_SHIFT)) & AUDIO_PLL_CTRL0_DITHER_EN_MASK)
#define AUDIO_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U)
#define AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT (19U)
/*! BIAS_TRIM - BIAS_TRIM
*/
#define AUDIO_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_TRIM_MASK)
#define AUDIO_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U)
#define AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT (22U)
/*! PLL_REG_EN - PLL_REG_EN
*/
#define AUDIO_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & AUDIO_PLL_CTRL0_PLL_REG_EN_MASK)
#define AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U)
#define AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U)
/*! POST_DIV_SEL - Post Divide Select
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 4
* 0b011..Divide by 8
* 0b100..Divide by 16
* 0b101..Divide by 32
*/
#define AUDIO_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & AUDIO_PLL_CTRL0_POST_DIV_SEL_MASK)
#define AUDIO_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U)
#define AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT (29U)
/*! BIAS_SELECT - BIAS_SELECT
* 0b0..Used in SoCs with a bias current of 10uA
* 0b1..Used in SoCs with a bias current of 2uA
*/
#define AUDIO_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & AUDIO_PLL_CTRL0_BIAS_SELECT_MASK)
/*! @} */
/*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
/*! @{ */
#define AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU)
#define AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U)
/*! STEP - Step
*/
#define AUDIO_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STEP_MASK)
#define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U)
#define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U)
/*! ENABLE - Enable
*/
#define AUDIO_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
#define AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U)
#define AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U)
/*! STOP - Stop
*/
#define AUDIO_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & AUDIO_PLL_SPREAD_SPECTRUM_STOP_MASK)
/*! @} */
/*! @name NUMERATOR - Fractional PLL Numerator Control Register */
/*! @{ */
#define AUDIO_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define AUDIO_PLL_NUMERATOR_NUM_SHIFT (0U)
/*! NUM - Numerator
*/
#define AUDIO_PLL_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_NUMERATOR_NUM_SHIFT)) & AUDIO_PLL_NUMERATOR_NUM_MASK)
/*! @} */
/*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
/*! @{ */
#define AUDIO_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define AUDIO_PLL_DENOMINATOR_DENOM_SHIFT (0U)
/*! DENOM - Denominator
*/
#define AUDIO_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << AUDIO_PLL_DENOMINATOR_DENOM_SHIFT)) & AUDIO_PLL_DENOMINATOR_DENOM_MASK)
/*! @} */
/*!
* @}
*/ /* end of group AUDIO_PLL_Register_Masks */
/* AUDIO_PLL - Peripheral instance base addresses */
/** Peripheral AUDIO_PLL base address */
#define AUDIO_PLL_BASE (0u)
/** Peripheral AUDIO_PLL base pointer */
#define AUDIO_PLL ((AUDIO_PLL_Type *)AUDIO_PLL_BASE)
/** Array initializer of AUDIO_PLL peripheral base addresses */
#define AUDIO_PLL_BASE_ADDRS { AUDIO_PLL_BASE }
/** Array initializer of AUDIO_PLL peripheral base pointers */
#define AUDIO_PLL_BASE_PTRS { AUDIO_PLL }
/*!
* @}
*/ /* end of group AUDIO_PLL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAAM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAAM_Peripheral_Access_Layer CAAM Peripheral Access Layer
* @{
*/
/** CAAM - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t MCFGR; /**< Master Configuration Register, offset: 0x4 */
__IO uint32_t PAGE0_SDID; /**< Page 0 SDID Register, offset: 0x8 */
__IO uint32_t SCFGR; /**< Security Configuration Register, offset: 0xC */
struct { /* offset: 0x10, array step: 0x8 */
__IO uint32_t JRDID_MS; /**< Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half, array offset: 0x10, array step: 0x8 */
__IO uint32_t JRDID_LS; /**< Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half, array offset: 0x14, array step: 0x8 */
} JRADID[4];
uint8_t RESERVED_1[40];
__IO uint32_t DEBUGCTL; /**< Debug Control Register, offset: 0x58 */
__IO uint32_t JRSTARTR; /**< Job Ring Start Register, offset: 0x5C */
__IO uint32_t RTIC_OWN; /**< RTIC OWN Register, offset: 0x60 */
struct { /* offset: 0x64, array step: 0x8 */
__IO uint32_t RTIC_DID; /**< RTIC DID Register for Block A..RTIC DID Register for Block D, array offset: 0x64, array step: 0x8 */
uint8_t RESERVED_0[4];
} RTICADID[4];
uint8_t RESERVED_2[16];
__IO uint32_t DECORSR; /**< DECO Request Source Register, offset: 0x94 */
uint8_t RESERVED_3[4];
__IO uint32_t DECORR; /**< DECO Request Register, offset: 0x9C */
struct { /* offset: 0xA0, array step: 0x8 */
__IO uint32_t DECODID_MS; /**< DECO0 DID Register - most significant half, array offset: 0xA0, array step: 0x8 */
__IO uint32_t DECODID_LS; /**< DECO0 DID Register - least significant half, array offset: 0xA4, array step: 0x8 */
} DECONDID[1];
uint8_t RESERVED_4[120];
__IO uint32_t DAR; /**< DECO Availability Register, offset: 0x120 */
__O uint32_t DRR; /**< DECO Reset Register, offset: 0x124 */
uint8_t RESERVED_5[92];
struct { /* offset: 0x184, array step: 0x8 */
__IO uint32_t JRSMVBAR; /**< Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register, array offset: 0x184, array step: 0x8 */
uint8_t RESERVED_0[4];
} JRNSMVBAR[4];
uint8_t RESERVED_6[124];
__IO uint32_t PBSL; /**< Peak Bandwidth Smoothing Limit Register, offset: 0x220 */
uint8_t RESERVED_7[28];
struct { /* offset: 0x240, array step: 0x10 */
__I uint32_t DMA_AIDL_MAP_MS; /**< DMA0_AIDL_MAP_MS, array offset: 0x240, array step: 0x10 */
__I uint32_t DMA_AIDL_MAP_LS; /**< DMA0_AIDL_MAP_LS, array offset: 0x244, array step: 0x10 */
__I uint32_t DMA_AIDM_MAP_MS; /**< DMA0_AIDM_MAP_MS, array offset: 0x248, array step: 0x10 */
__I uint32_t DMA_AIDM_MAP_LS; /**< DMA0_AIDM_MAP_LS, array offset: 0x24C, array step: 0x10 */
} AID_CNTS[1];
__I uint32_t DMA0_AID_ENB; /**< DMA0 AXI ID Enable Register, offset: 0x250 */
uint8_t RESERVED_8[12];
__IO uint64_t DMA0_ARD_TC; /**< DMA0 AXI Read Timing Check Register, offset: 0x260 */
uint8_t RESERVED_9[4];
__IO uint32_t DMA0_ARD_LAT; /**< DMA0 Read Timing Check Latency Register, offset: 0x26C */
__IO uint64_t DMA0_AWR_TC; /**< DMA0 AXI Write Timing Check Register, offset: 0x270 */
uint8_t RESERVED_10[4];
__IO uint32_t DMA0_AWR_LAT; /**< DMA0 Write Timing Check Latency Register, offset: 0x27C */
uint8_t RESERVED_11[128];
__IO uint8_t MPPKR[64]; /**< Manufacturing Protection Private Key Register, array offset: 0x300, array step: 0x1 */
uint8_t RESERVED_12[64];
__IO uint8_t MPMR[32]; /**< Manufacturing Protection Message Register, array offset: 0x380, array step: 0x1 */
uint8_t RESERVED_13[32];
__I uint8_t MPTESTR[32]; /**< Manufacturing Protection Test Register, array offset: 0x3C0, array step: 0x1 */
uint8_t RESERVED_14[24];
__I uint32_t MPECC; /**< Manufacturing Protection ECC Register, offset: 0x3F8 */
uint8_t RESERVED_15[4];
__IO uint32_t JDKEKR[8]; /**< Job Descriptor Key Encryption Key Register, array offset: 0x400, array step: 0x4 */
__IO uint32_t TDKEKR[8]; /**< Trusted Descriptor Key Encryption Key Register, array offset: 0x420, array step: 0x4 */
__IO uint32_t TDSKR[8]; /**< Trusted Descriptor Signing Key Register, array offset: 0x440, array step: 0x4 */
uint8_t RESERVED_16[128];
__IO uint64_t SKNR; /**< Secure Key Nonce Register, offset: 0x4E0 */
uint8_t RESERVED_17[36];
__I uint32_t DMA_STA; /**< DMA Status Register, offset: 0x50C */
__I uint32_t DMA_X_AID_7_4_MAP; /**< DMA_X_AID_7_4_MAP, offset: 0x510 */
__I uint32_t DMA_X_AID_3_0_MAP; /**< DMA_X_AID_3_0_MAP, offset: 0x514 */
__I uint32_t DMA_X_AID_15_12_MAP; /**< DMA_X_AID_15_12_MAP, offset: 0x518 */
__I uint32_t DMA_X_AID_11_8_MAP; /**< DMA_X_AID_11_8_MAP, offset: 0x51C */
uint8_t RESERVED_18[4];
__I uint32_t DMA_X_AID_15_0_EN; /**< DMA_X AXI ID Map Enable Register, offset: 0x524 */
uint8_t RESERVED_19[8];
__IO uint32_t DMA_X_ARTC_CTL; /**< DMA_X AXI Read Timing Check Control Register, offset: 0x530 */
__IO uint32_t DMA_X_ARTC_LC; /**< DMA_X AXI Read Timing Check Late Count Register, offset: 0x534 */
__IO uint32_t DMA_X_ARTC_SC; /**< DMA_X AXI Read Timing Check Sample Count Register, offset: 0x538 */
__IO uint32_t DMA_X_ARTC_LAT; /**< DMA_X Read Timing Check Latency Register, offset: 0x53C */
__IO uint32_t DMA_X_AWTC_CTL; /**< DMA_X AXI Write Timing Check Control Register, offset: 0x540 */
__IO uint32_t DMA_X_AWTC_LC; /**< DMA_X AXI Write Timing Check Late Count Register, offset: 0x544 */
__IO uint32_t DMA_X_AWTC_SC; /**< DMA_X AXI Write Timing Check Sample Count Register, offset: 0x548 */
__IO uint32_t DMA_X_AWTC_LAT; /**< DMA_X Write Timing Check Latency Register, offset: 0x54C */
uint8_t RESERVED_20[176];
__IO uint32_t RTMCTL; /**< RNG TRNG Miscellaneous Control Register, offset: 0x600 */
__IO uint32_t RTSCMISC; /**< RNG TRNG Statistical Check Miscellaneous Register, offset: 0x604 */
__IO uint32_t RTPKRRNG; /**< RNG TRNG Poker Range Register, offset: 0x608 */
union { /* offset: 0x60C */
__IO uint32_t RTPKRMAX; /**< RNG TRNG Poker Maximum Limit Register, offset: 0x60C */
__I uint32_t RTPKRSQ; /**< RNG TRNG Poker Square Calculation Result Register, offset: 0x60C */
};
__IO uint32_t RTSDCTL; /**< RNG TRNG Seed Control Register, offset: 0x610 */
union { /* offset: 0x614 */
__IO uint32_t RTSBLIM; /**< RNG TRNG Sparse Bit Limit Register, offset: 0x614 */
__I uint32_t RTTOTSAM; /**< RNG TRNG Total Samples Register, offset: 0x614 */
};
__IO uint32_t RTFRQMIN; /**< RNG TRNG Frequency Count Minimum Limit Register, offset: 0x618 */
union { /* offset: 0x61C */
struct { /* offset: 0x61C */
__I uint32_t RTFRQCNT; /**< RNG TRNG Frequency Count Register, offset: 0x61C */
__I uint32_t RTSCMC; /**< RNG TRNG Statistical Check Monobit Count Register, offset: 0x620 */
__I uint32_t RTSCR1C; /**< RNG TRNG Statistical Check Run Length 1 Count Register, offset: 0x624 */
__I uint32_t RTSCR2C; /**< RNG TRNG Statistical Check Run Length 2 Count Register, offset: 0x628 */
__I uint32_t RTSCR3C; /**< RNG TRNG Statistical Check Run Length 3 Count Register, offset: 0x62C */
__I uint32_t RTSCR4C; /**< RNG TRNG Statistical Check Run Length 4 Count Register, offset: 0x630 */
__I uint32_t RTSCR5C; /**< RNG TRNG Statistical Check Run Length 5 Count Register, offset: 0x634 */
__I uint32_t RTSCR6PC; /**< RNG TRNG Statistical Check Run Length 6+ Count Register, offset: 0x638 */
} COUNT;
struct { /* offset: 0x61C */
__IO uint32_t RTFRQMAX; /**< RNG TRNG Frequency Count Maximum Limit Register, offset: 0x61C */
__IO uint32_t RTSCML; /**< RNG TRNG Statistical Check Monobit Limit Register, offset: 0x620 */
__IO uint32_t RTSCR1L; /**< RNG TRNG Statistical Check Run Length 1 Limit Register, offset: 0x624 */
__IO uint32_t RTSCR2L; /**< RNG TRNG Statistical Check Run Length 2 Limit Register, offset: 0x628 */
__IO uint32_t RTSCR3L; /**< RNG TRNG Statistical Check Run Length 3 Limit Register, offset: 0x62C */
__IO uint32_t RTSCR4L; /**< RNG TRNG Statistical Check Run Length 4 Limit Register, offset: 0x630 */
__IO uint32_t RTSCR5L; /**< RNG TRNG Statistical Check Run Length 5 Limit Register, offset: 0x634 */
__IO uint32_t RTSCR6PL; /**< RNG TRNG Statistical Check Run Length 6+ Limit Register, offset: 0x638 */
} LIMIT;
};
__I uint32_t RTSTATUS; /**< RNG TRNG Status Register, offset: 0x63C */
__I uint32_t RTENT[16]; /**< RNG TRNG Entropy Read Register, array offset: 0x640, array step: 0x4 */
__I uint32_t RTPKRCNT10; /**< RNG TRNG Statistical Check Poker Count 1 and 0 Register, offset: 0x680 */
__I uint32_t RTPKRCNT32; /**< RNG TRNG Statistical Check Poker Count 3 and 2 Register, offset: 0x684 */
__I uint32_t RTPKRCNT54; /**< RNG TRNG Statistical Check Poker Count 5 and 4 Register, offset: 0x688 */
__I uint32_t RTPKRCNT76; /**< RNG TRNG Statistical Check Poker Count 7 and 6 Register, offset: 0x68C */
__I uint32_t RTPKRCNT98; /**< RNG TRNG Statistical Check Poker Count 9 and 8 Register, offset: 0x690 */
__I uint32_t RTPKRCNTBA; /**< RNG TRNG Statistical Check Poker Count B and A Register, offset: 0x694 */
__I uint32_t RTPKRCNTDC; /**< RNG TRNG Statistical Check Poker Count D and C Register, offset: 0x698 */
__I uint32_t RTPKRCNTFE; /**< RNG TRNG Statistical Check Poker Count F and E Register, offset: 0x69C */
uint8_t RESERVED_21[32];
__I uint32_t RDSTA; /**< RNG DRNG Status Register, offset: 0x6C0 */
uint8_t RESERVED_22[12];
__I uint32_t RDINT0; /**< RNG DRNG State Handle 0 Reseed Interval Register, offset: 0x6D0 */
__I uint32_t RDINT1; /**< RNG DRNG State Handle 1 Reseed Interval Register, offset: 0x6D4 */
uint8_t RESERVED_23[8];
__IO uint32_t RDHCNTL; /**< RNG DRNG Hash Control Register, offset: 0x6E0 */
__I uint32_t RDHDIG; /**< RNG DRNG Hash Digest Register, offset: 0x6E4 */
__O uint32_t RDHBUF; /**< RNG DRNG Hash Buffer Register, offset: 0x6E8 */
uint8_t RESERVED_24[788];
struct { /* offset: 0xA00, array step: 0x10 */
__I uint32_t PX_SDID_PG0; /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0xA00, array step: 0x10 */
__IO uint32_t PX_SMAPR_PG0; /**< Secure Memory Access Permissions register, array offset: 0xA04, array step: 0x10 */
__IO uint32_t PX_SMAG2_PG0; /**< Secure Memory Access Group Registers, array offset: 0xA08, array step: 0x10 */
__IO uint32_t PX_SMAG1_PG0; /**< Secure Memory Access Group Registers, array offset: 0xA0C, array step: 0x10 */
} PX_PG0[16];
__IO uint32_t REIS; /**< Recoverable Error Interrupt Status, offset: 0xB00 */
__IO uint32_t REIE; /**< Recoverable Error Interrupt Enable, offset: 0xB04 */
__I uint32_t REIF; /**< Recoverable Error Interrupt Force, offset: 0xB08 */
__IO uint32_t REIH; /**< Recoverable Error Interrupt Halt, offset: 0xB0C */
uint8_t RESERVED_25[192];
__IO uint32_t SMWPJRR[4]; /**< Secure Memory Write Protect Job Ring Register, array offset: 0xBD0, array step: 0x4 */
uint8_t RESERVED_26[4];
__O uint32_t SMCR_PG0; /**< Secure Memory Command Register, offset: 0xBE4 */
uint8_t RESERVED_27[4];
__I uint32_t SMCSR_PG0; /**< Secure Memory Command Status Register, offset: 0xBEC */
uint8_t RESERVED_28[8];
__I uint32_t CAAMVID_MS_TRAD; /**< CAAM Version ID Register, most-significant half, offset: 0xBF8 */
__I uint32_t CAAMVID_LS_TRAD; /**< CAAM Version ID Register, least-significant half, offset: 0xBFC */
struct { /* offset: 0xC00, array step: 0x20 */
__I uint64_t HT_JD_ADDR; /**< Holding Tank 0 Job Descriptor Address, array offset: 0xC00, array step: 0x20 */
__I uint64_t HT_SD_ADDR; /**< Holding Tank 0 Shared Descriptor Address, array offset: 0xC08, array step: 0x20 */
__I uint32_t HT_JQ_CTRL_MS; /**< Holding Tank 0 Job Queue Control, most-significant half, array offset: 0xC10, array step: 0x20 */
__I uint32_t HT_JQ_CTRL_LS; /**< Holding Tank 0 Job Queue Control, least-significant half, array offset: 0xC14, array step: 0x20 */
uint8_t RESERVED_0[4];
__I uint32_t HT_STATUS; /**< Holding Tank Status, array offset: 0xC1C, array step: 0x20 */
} HTA[1];
uint8_t RESERVED_29[4];
__IO uint32_t JQ_DEBUG_SEL; /**< Job Queue Debug Select Register, offset: 0xC24 */
uint8_t RESERVED_30[404];
__I uint32_t JRJIDU_LS; /**< Job Ring Job IDs in Use Register, least-significant half, offset: 0xDBC */
__I uint32_t JRJDJIFBC; /**< Job Ring Job-Done Job ID FIFO BC, offset: 0xDC0 */
__I uint32_t JRJDJIF; /**< Job Ring Job-Done Job ID FIFO, offset: 0xDC4 */
uint8_t RESERVED_31[28];
__I uint32_t JRJDS1; /**< Job Ring Job-Done Source 1, offset: 0xDE4 */
uint8_t RESERVED_32[24];
__I uint64_t JRJDDA[1]; /**< Job Ring Job-Done Descriptor Address 0 Register, array offset: 0xE00, array step: 0x8 */
uint8_t RESERVED_33[408];
__I uint32_t CRNR_MS; /**< CHA Revision Number Register, most-significant half, offset: 0xFA0 */
__I uint32_t CRNR_LS; /**< CHA Revision Number Register, least-significant half, offset: 0xFA4 */
__I uint32_t CTPR_MS; /**< Compile Time Parameters Register, most-significant half, offset: 0xFA8 */
__I uint32_t CTPR_LS; /**< Compile Time Parameters Register, least-significant half, offset: 0xFAC */
uint8_t RESERVED_34[4];
__I uint32_t SMSTA; /**< Secure Memory Status Register, offset: 0xFB4 */
uint8_t RESERVED_35[4];
__I uint32_t SMPO; /**< Secure Memory Partition Owners Register, offset: 0xFBC */
__I uint64_t FAR; /**< Fault Address Register, offset: 0xFC0 */
__I uint32_t FADID; /**< Fault Address DID Register, offset: 0xFC8 */
__I uint32_t FADR; /**< Fault Address Detail Register, offset: 0xFCC */
uint8_t RESERVED_36[4];
__I uint32_t CSTA; /**< CAAM Status Register, offset: 0xFD4 */
__I uint32_t SMVID_MS; /**< Secure Memory Version ID Register, most-significant half, offset: 0xFD8 */
__I uint32_t SMVID_LS; /**< Secure Memory Version ID Register, least-significant half, offset: 0xFDC */
__I uint32_t RVID; /**< RTIC Version ID Register, offset: 0xFE0 */
__I uint32_t CCBVID; /**< CHA Cluster Block Version ID Register, offset: 0xFE4 */
__I uint32_t CHAVID_MS; /**< CHA Version ID Register, most-significant half, offset: 0xFE8 */
__I uint32_t CHAVID_LS; /**< CHA Version ID Register, least-significant half, offset: 0xFEC */
__I uint32_t CHANUM_MS; /**< CHA Number Register, most-significant half, offset: 0xFF0 */
__I uint32_t CHANUM_LS; /**< CHA Number Register, least-significant half, offset: 0xFF4 */
__I uint32_t CAAMVID_MS; /**< CAAM Version ID Register, most-significant half, offset: 0xFF8 */
__I uint32_t CAAMVID_LS; /**< CAAM Version ID Register, least-significant half, offset: 0xFFC */
uint8_t RESERVED_37[61440];
struct { /* offset: 0x10000, array step: 0x10000 */
__IO uint64_t IRBAR_JR; /**< Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3, array offset: 0x10000, array step: 0x10000 */
uint8_t RESERVED_0[4];
__IO uint32_t IRSR_JR; /**< Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3, array offset: 0x1000C, array step: 0x10000 */
uint8_t RESERVED_1[4];
__IO uint32_t IRSAR_JR; /**< Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3, array offset: 0x10014, array step: 0x10000 */
uint8_t RESERVED_2[4];
__IO uint32_t IRJAR_JR; /**< Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3, array offset: 0x1001C, array step: 0x10000 */
__IO uint64_t ORBAR_JR; /**< Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3, array offset: 0x10020, array step: 0x10000 */
uint8_t RESERVED_3[4];
__IO uint32_t ORSR_JR; /**< Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3, array offset: 0x1002C, array step: 0x10000 */
uint8_t RESERVED_4[4];
__IO uint32_t ORJRR_JR; /**< Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3, array offset: 0x10034, array step: 0x10000 */
uint8_t RESERVED_5[4];
__IO uint32_t ORSFR_JR; /**< Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3, array offset: 0x1003C, array step: 0x10000 */
uint8_t RESERVED_6[4];
__I uint32_t JRSTAR_JR; /**< Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3, array offset: 0x10044, array step: 0x10000 */
uint8_t RESERVED_7[4];
__IO uint32_t JRINTR_JR; /**< Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3, array offset: 0x1004C, array step: 0x10000 */
__IO uint32_t JRCFGR_JR_MS; /**< Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half, array offset: 0x10050, array step: 0x10000 */
__IO uint32_t JRCFGR_JR_LS; /**< Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half, array offset: 0x10054, array step: 0x10000 */
uint8_t RESERVED_8[4];
__IO uint32_t IRRIR_JR; /**< Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3, array offset: 0x1005C, array step: 0x10000 */
uint8_t RESERVED_9[4];
__IO uint32_t ORWIR_JR; /**< Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3, array offset: 0x10064, array step: 0x10000 */
uint8_t RESERVED_10[4];
__O uint32_t JRCR_JR; /**< Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3, array offset: 0x1006C, array step: 0x10000 */
uint8_t RESERVED_11[1684];
__I uint32_t JRAAV; /**< Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register, array offset: 0x10704, array step: 0x10000 */
uint8_t RESERVED_12[248];
__I uint64_t JRAAA[4]; /**< Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register, array offset: 0x10800, array step: index*0x10000, index2*0x8 */
uint8_t RESERVED_13[480];
struct { /* offset: 0x10A00, array step: index*0x10000, index2*0x10 */
__I uint32_t PX_SDID_JR; /**< Partition 0 SDID register..Partition 15 SDID register, array offset: 0x10A00, array step: index*0x10000, index2*0x10 */
__IO uint32_t PX_SMAPR_JR; /**< Secure Memory Access Permissions register, array offset: 0x10A04, array step: index*0x10000, index2*0x10 */
__IO uint32_t PX_SMAG2_JR; /**< Secure Memory Access Group Registers, array offset: 0x10A08, array step: index*0x10000, index2*0x10 */
__IO uint32_t PX_SMAG1_JR; /**< Secure Memory Access Group Registers, array offset: 0x10A0C, array step: index*0x10000, index2*0x10 */
} PX_JR[16];
uint8_t RESERVED_14[228];
__O uint32_t SMCR_JR; /**< Secure Memory Command Register, array offset: 0x10BE4, array step: 0x10000 */
uint8_t RESERVED_15[4];
__I uint32_t SMCSR_JR; /**< Secure Memory Command Status Register, array offset: 0x10BEC, array step: 0x10000 */
uint8_t RESERVED_16[528];
__I uint32_t REIR0JR; /**< Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3, array offset: 0x10E00, array step: 0x10000 */
uint8_t RESERVED_17[4];
__I uint64_t REIR2JR; /**< Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3, array offset: 0x10E08, array step: 0x10000 */
__I uint32_t REIR4JR; /**< Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3, array offset: 0x10E10, array step: 0x10000 */
__I uint32_t REIR5JR; /**< Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3, array offset: 0x10E14, array step: 0x10000 */
uint8_t RESERVED_18[392];
__I uint32_t CRNR_MS_JR; /**< CHA Revision Number Register, most-significant half, array offset: 0x10FA0, array step: 0x10000 */
__I uint32_t CRNR_LS_JR; /**< CHA Revision Number Register, least-significant half, array offset: 0x10FA4, array step: 0x10000 */
__I uint32_t CTPR_MS_JR; /**< Compile Time Parameters Register, most-significant half, array offset: 0x10FA8, array step: 0x10000 */
__I uint32_t CTPR_LS_JR; /**< Compile Time Parameters Register, least-significant half, array offset: 0x10FAC, array step: 0x10000 */
uint8_t RESERVED_19[4];
__I uint32_t SMSTA_JR; /**< Secure Memory Status Register, array offset: 0x10FB4, array step: 0x10000 */
uint8_t RESERVED_20[4];
__I uint32_t SMPO_JR; /**< Secure Memory Partition Owners Register, array offset: 0x10FBC, array step: 0x10000 */
__I uint64_t FAR_JR; /**< Fault Address Register, array offset: 0x10FC0, array step: 0x10000 */
__I uint32_t FADID_JR; /**< Fault Address DID Register, array offset: 0x10FC8, array step: 0x10000 */
__I uint32_t FADR_JR; /**< Fault Address Detail Register, array offset: 0x10FCC, array step: 0x10000 */
uint8_t RESERVED_21[4];
__I uint32_t CSTA_JR; /**< CAAM Status Register, array offset: 0x10FD4, array step: 0x10000 */
__I uint32_t SMVID_MS_JR; /**< Secure Memory Version ID Register, most-significant half, array offset: 0x10FD8, array step: 0x10000 */
__I uint32_t SMVID_LS_JR; /**< Secure Memory Version ID Register, least-significant half, array offset: 0x10FDC, array step: 0x10000 */
__I uint32_t RVID_JR; /**< RTIC Version ID Register, array offset: 0x10FE0, array step: 0x10000 */
__I uint32_t CCBVID_JR; /**< CHA Cluster Block Version ID Register, array offset: 0x10FE4, array step: 0x10000 */
__I uint32_t CHAVID_MS_JR; /**< CHA Version ID Register, most-significant half, array offset: 0x10FE8, array step: 0x10000 */
__I uint32_t CHAVID_LS_JR; /**< CHA Version ID Register, least-significant half, array offset: 0x10FEC, array step: 0x10000 */
__I uint32_t CHANUM_MS_JR; /**< CHA Number Register, most-significant half, array offset: 0x10FF0, array step: 0x10000 */
__I uint32_t CHANUM_LS_JR; /**< CHA Number Register, least-significant half, array offset: 0x10FF4, array step: 0x10000 */
__I uint32_t CAAMVID_MS_JR; /**< CAAM Version ID Register, most-significant half, array offset: 0x10FF8, array step: 0x10000 */
__I uint32_t CAAMVID_LS_JR; /**< CAAM Version ID Register, least-significant half, array offset: 0x10FFC, array step: 0x10000 */
uint8_t RESERVED_22[61440];
} JOBRING[4];
uint8_t RESERVED_38[65540];
__I uint32_t RSTA; /**< RTIC Status Register, offset: 0x60004 */
uint8_t RESERVED_39[4];
__IO uint32_t RCMD; /**< RTIC Command Register, offset: 0x6000C */
uint8_t RESERVED_40[4];
__IO uint32_t RCTL; /**< RTIC Control Register, offset: 0x60014 */
uint8_t RESERVED_41[4];
__IO uint32_t RTHR; /**< RTIC Throttle Register, offset: 0x6001C */
uint8_t RESERVED_42[8];
__IO uint64_t RWDOG; /**< RTIC Watchdog Timer, offset: 0x60028 */
uint8_t RESERVED_43[4];
__IO uint32_t REND; /**< RTIC Endian Register, offset: 0x60034 */
uint8_t RESERVED_44[200];
struct { /* offset: 0x60100, array step: index*0x20, index2*0x10 */
__IO uint64_t RMA; /**< RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register, array offset: 0x60100, array step: index*0x20, index2*0x10 */
uint8_t RESERVED_0[4];
__IO uint32_t RML; /**< RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register, array offset: 0x6010C, array step: index*0x20, index2*0x10 */
} RM[4][2];
uint8_t RESERVED_45[128];
__IO uint32_t RMD[4][2][32]; /**< RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31, array offset: 0x60200, array step: index*0x100, index2*0x80, index3*0x4 */
uint8_t RESERVED_46[2048];
__I uint32_t REIR0RTIC; /**< Recoverable Error Interrupt Record 0 for RTIC, offset: 0x60E00 */
uint8_t RESERVED_47[4];
__I uint64_t REIR2RTIC; /**< Recoverable Error Interrupt Record 2 for RTIC, offset: 0x60E08 */
__I uint32_t REIR4RTIC; /**< Recoverable Error Interrupt Record 4 for RTIC, offset: 0x60E10 */
__I uint32_t REIR5RTIC; /**< Recoverable Error Interrupt Record 5 for RTIC, offset: 0x60E14 */
uint8_t RESERVED_48[392];
__I uint32_t CRNR_MS_RTIC; /**< CHA Revision Number Register, most-significant half, offset: 0x60FA0 */
__I uint32_t CRNR_LS_RTIC; /**< CHA Revision Number Register, least-significant half, offset: 0x60FA4 */
__I uint32_t CTPR_MS_RTIC; /**< Compile Time Parameters Register, most-significant half, offset: 0x60FA8 */
__I uint32_t CTPR_LS_RTIC; /**< Compile Time Parameters Register, least-significant half, offset: 0x60FAC */
uint8_t RESERVED_49[4];
__I uint32_t SMSTA_RTIC; /**< Secure Memory Status Register, offset: 0x60FB4 */
uint8_t RESERVED_50[8];
__I uint64_t FAR_RTIC; /**< Fault Address Register, offset: 0x60FC0 */
__I uint32_t FADID_RTIC; /**< Fault Address DID Register, offset: 0x60FC8 */
__I uint32_t FADR_RTIC; /**< Fault Address Detail Register, offset: 0x60FCC */
uint8_t RESERVED_51[4];
__I uint32_t CSTA_RTIC; /**< CAAM Status Register, offset: 0x60FD4 */
__I uint32_t SMVID_MS_RTIC; /**< Secure Memory Version ID Register, most-significant half, offset: 0x60FD8 */
__I uint32_t SMVID_LS_RTIC; /**< Secure Memory Version ID Register, least-significant half, offset: 0x60FDC */
__I uint32_t RVID_RTIC; /**< RTIC Version ID Register, offset: 0x60FE0 */
__I uint32_t CCBVID_RTIC; /**< CHA Cluster Block Version ID Register, offset: 0x60FE4 */
__I uint32_t CHAVID_MS_RTIC; /**< CHA Version ID Register, most-significant half, offset: 0x60FE8 */
__I uint32_t CHAVID_LS_RTIC; /**< CHA Version ID Register, least-significant half, offset: 0x60FEC */
__I uint32_t CHANUM_MS_RTIC; /**< CHA Number Register, most-significant half, offset: 0x60FF0 */
__I uint32_t CHANUM_LS_RTIC; /**< CHA Number Register, least-significant half, offset: 0x60FF4 */
__I uint32_t CAAMVID_MS_RTIC; /**< CAAM Version ID Register, most-significant half, offset: 0x60FF8 */
__I uint32_t CAAMVID_LS_RTIC; /**< CAAM Version ID Register, least-significant half, offset: 0x60FFC */
uint8_t RESERVED_52[126976];
struct { /* offset: 0x80000, array step: 0xE3C */
uint8_t RESERVED_0[4];
union { /* offset: 0x80004, array step: 0xE3C */
__IO uint32_t CC1MR; /**< CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms, array offset: 0x80004, array step: 0xE3C */
__IO uint32_t CC1MR_PK; /**< CCB 0 Class 1 Mode Register Format for Public Key Algorithms, array offset: 0x80004, array step: 0xE3C */
__IO uint32_t CC1MR_RNG; /**< CCB 0 Class 1 Mode Register Format for RNG4, array offset: 0x80004, array step: 0xE3C */
};
uint8_t RESERVED_1[4];
__IO uint32_t CC1KSR; /**< CCB 0 Class 1 Key Size Register, array offset: 0x8000C, array step: 0xE3C */
__IO uint64_t CC1DSR; /**< CCB 0 Class 1 Data Size Register, array offset: 0x80010, array step: 0xE3C */
uint8_t RESERVED_2[4];
__IO uint32_t CC1ICVSR; /**< CCB 0 Class 1 ICV Size Register, array offset: 0x8001C, array step: 0xE3C */
uint8_t RESERVED_3[20];
__O uint32_t CCCTRL; /**< CCB 0 CHA Control Register, array offset: 0x80034, array step: 0xE3C */
uint8_t RESERVED_4[4];
__IO uint32_t CICTL; /**< CCB 0 Interrupt Control Register, array offset: 0x8003C, array step: 0xE3C */
uint8_t RESERVED_5[4];
__O uint32_t CCWR; /**< CCB 0 Clear Written Register, array offset: 0x80044, array step: 0xE3C */
__I uint32_t CCSTA_MS; /**< CCB 0 Status and Error Register, most-significant half, array offset: 0x80048, array step: 0xE3C */
__I uint32_t CCSTA_LS; /**< CCB 0 Status and Error Register, least-significant half, array offset: 0x8004C, array step: 0xE3C */
uint8_t RESERVED_6[12];
__IO uint32_t CC1AADSZR; /**< CCB 0 Class 1 AAD Size Register, array offset: 0x8005C, array step: 0xE3C */
uint8_t RESERVED_7[4];
__IO uint32_t CC1IVSZR; /**< CCB 0 Class 1 IV Size Register, array offset: 0x80064, array step: 0xE3C */
uint8_t RESERVED_8[28];
__IO uint32_t CPKASZR; /**< PKHA A Size Register, array offset: 0x80084, array step: 0xE3C */
uint8_t RESERVED_9[4];
__IO uint32_t CPKBSZR; /**< PKHA B Size Register, array offset: 0x8008C, array step: 0xE3C */
uint8_t RESERVED_10[4];
__IO uint32_t CPKNSZR; /**< PKHA N Size Register, array offset: 0x80094, array step: 0xE3C */
uint8_t RESERVED_11[4];
__IO uint32_t CPKESZR; /**< PKHA E Size Register, array offset: 0x8009C, array step: 0xE3C */
uint8_t RESERVED_12[96];
__IO uint32_t CC1CTXR[16]; /**< CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15, array offset: 0x80100, array step: index*0xE3C, index2*0x4 */
uint8_t RESERVED_13[192];
__IO uint32_t CC1KR[8]; /**< CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7, array offset: 0x80200, array step: index*0xE3C, index2*0x4 */
uint8_t RESERVED_14[484];
__IO uint32_t CC2MR; /**< CCB 0 Class 2 Mode Register, array offset: 0x80404, array step: 0xE3C */
uint8_t RESERVED_15[4];
__IO uint32_t CC2KSR; /**< CCB 0 Class 2 Key Size Register, array offset: 0x8040C, array step: 0xE3C */
__IO uint64_t CC2DSR; /**< CCB 0 Class 2 Data Size Register, array offset: 0x80410, array step: 0xE3C */
uint8_t RESERVED_16[4];
__IO uint32_t CC2ICVSZR; /**< CCB 0 Class 2 ICV Size Register, array offset: 0x8041C, array step: 0xE3C */
uint8_t RESERVED_17[224];
__IO uint32_t CC2CTXR[18]; /**< CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17, array offset: 0x80500, array step: index*0xE3C, index2*0x4 */
uint8_t RESERVED_18[184];
__IO uint32_t CC2KEYR[32]; /**< CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31, array offset: 0x80600, array step: index*0xE3C, index2*0x4 */
uint8_t RESERVED_19[320];
__I uint32_t CFIFOSTA; /**< CCB 0 FIFO Status Register, array offset: 0x807C0, array step: 0xE3C */
uint8_t RESERVED_20[12];
union { /* offset: 0x807D0, array step: 0xE3C */
__O uint32_t CNFIFO; /**< CCB 0 iNformation FIFO When STYPE != 10b, array offset: 0x807D0, array step: 0xE3C */
__O uint32_t CNFIFO_2; /**< CCB 0 iNformation FIFO When STYPE == 10b, array offset: 0x807D0, array step: 0xE3C */
};
uint8_t RESERVED_21[12];
__O uint32_t CIFIFO; /**< CCB 0 Input Data FIFO, array offset: 0x807E0, array step: 0xE3C */
uint8_t RESERVED_22[12];
__I uint64_t COFIFO; /**< CCB 0 Output Data FIFO, array offset: 0x807F0, array step: 0xE3C */
uint8_t RESERVED_23[8];
__IO uint32_t DJQCR_MS; /**< DECO0 Job Queue Control Register, most-significant half, array offset: 0x80800, array step: 0xE3C */
__I uint32_t DJQCR_LS; /**< DECO0 Job Queue Control Register, least-significant half, array offset: 0x80804, array step: 0xE3C */
__I uint64_t DDAR; /**< DECO0 Descriptor Address Register, array offset: 0x80808, array step: 0xE3C */
__I uint32_t DOPSTA_MS; /**< DECO0 Operation Status Register, most-significant half, array offset: 0x80810, array step: 0xE3C */
__I uint32_t DOPSTA_LS; /**< DECO0 Operation Status Register, least-significant half, array offset: 0x80814, array step: 0xE3C */
uint8_t RESERVED_24[8];
__I uint32_t DPDIDSR; /**< DECO0 Primary DID Status Register, array offset: 0x80820, array step: 0xE3C */
__I uint32_t DODIDSR; /**< DECO0 Output DID Status Register, array offset: 0x80824, array step: 0xE3C */
uint8_t RESERVED_25[24];
struct { /* offset: 0x80840, array step: index*0xE3C, index2*0x8 */
__IO uint32_t DMTH_MS; /**< DECO0 Math Register 0_MS..DECO0 Math Register 3_MS, array offset: 0x80840, array step: index*0xE3C, index2*0x8 */
__IO uint32_t DMTH_LS; /**< DECO0 Math Register 0_LS..DECO0 Math Register 3_LS, array offset: 0x80844, array step: index*0xE3C, index2*0x8 */
} DDMTHB[4];
uint8_t RESERVED_26[32];
struct { /* offset: 0x80880, array step: index*0xE3C, index2*0x10 */
__IO uint32_t DGTR_0; /**< DECO0 Gather Table Register 0 Word 0, array offset: 0x80880, array step: index*0xE3C, index2*0x10 */
__IO uint32_t DGTR_1; /**< DECO0 Gather Table Register 0 Word 1, array offset: 0x80884, array step: index*0xE3C, index2*0x10 */
__IO uint32_t DGTR_2; /**< DECO0 Gather Table Register 0 Word 2, array offset: 0x80888, array step: index*0xE3C, index2*0x10 */
__IO uint32_t DGTR_3; /**< DECO0 Gather Table Register 0 Word 3, array offset: 0x8088C, array step: index*0xE3C, index2*0x10 */
} DDGTR[1];
uint8_t RESERVED_27[112];
struct { /* offset: 0x80900, array step: index*0xE3C, index2*0x10 */
__IO uint32_t DSTR_0; /**< DECO0 Scatter Table Register 0 Word 0, array offset: 0x80900, array step: index*0xE3C, index2*0x10 */
__IO uint32_t DSTR_1; /**< DECO0 Scatter Table Register 0 Word 1, array offset: 0x80904, array step: index*0xE3C, index2*0x10 */
__IO uint32_t DSTR_2; /**< DECO0 Scatter Table Register 0 Word 2, array offset: 0x80908, array step: index*0xE3C, index2*0x10 */
__IO uint32_t DSTR_3; /**< DECO0 Scatter Table Register 0 Word 3, array offset: 0x8090C, array step: index*0xE3C, index2*0x10 */
} DDSTR[1];
uint8_t RESERVED_28[240];
__IO uint32_t DDESB[64]; /**< DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63, array offset: 0x80A00, array step: index*0xE3C, index2*0x4 */
uint8_t RESERVED_29[768];
__I uint32_t DDJR; /**< DECO0 Debug Job Register, array offset: 0x80E00, array step: 0xE3C */
__I uint32_t DDDR; /**< DECO0 Debug DECO Register, array offset: 0x80E04, array step: 0xE3C */
__I uint64_t DDJP; /**< DECO0 Debug Job Pointer, array offset: 0x80E08, array step: 0xE3C */
__I uint64_t DSDP; /**< DECO0 Debug Shared Pointer, array offset: 0x80E10, array step: 0xE3C */
__I uint32_t DDDR_MS; /**< DECO0 Debug DID, most-significant half, array offset: 0x80E18, array step: 0xE3C */
__I uint32_t DDDR_LS; /**< DECO0 Debug DID, least-significant half, array offset: 0x80E1C, array step: 0xE3C */
__IO uint32_t SOL; /**< Sequence Output Length Register, array offset: 0x80E20, array step: 0xE3C */
__IO uint32_t VSOL; /**< Variable Sequence Output Length Register, array offset: 0x80E24, array step: 0xE3C */
__IO uint32_t SIL; /**< Sequence Input Length Register, array offset: 0x80E28, array step: 0xE3C */
__IO uint32_t VSIL; /**< Variable Sequence Input Length Register, array offset: 0x80E2C, array step: 0xE3C */
__IO uint32_t DPOVRD; /**< Protocol Override Register, array offset: 0x80E30, array step: 0xE3C */
__IO uint32_t UVSOL; /**< Variable Sequence Output Length Register; Upper 32 bits, array offset: 0x80E34, array step: 0xE3C */
__IO uint32_t UVSIL; /**< Variable Sequence Input Length Register; Upper 32 bits, array offset: 0x80E38, array step: 0xE3C */
} DC[1];
uint8_t RESERVED_53[356];
__I uint32_t CRNR_MS_DC01; /**< CHA Revision Number Register, most-significant half, offset: 0x80FA0 */
__I uint32_t CRNR_LS_DC01; /**< CHA Revision Number Register, least-significant half, offset: 0x80FA4 */
__I uint32_t CTPR_MS_DC01; /**< Compile Time Parameters Register, most-significant half, offset: 0x80FA8 */
__I uint32_t CTPR_LS_DC01; /**< Compile Time Parameters Register, least-significant half, offset: 0x80FAC */
uint8_t RESERVED_54[4];
__I uint32_t SMSTA_DC01; /**< Secure Memory Status Register, offset: 0x80FB4 */
uint8_t RESERVED_55[8];
__I uint64_t FAR_DC01; /**< Fault Address Register, offset: 0x80FC0 */
__I uint32_t FADID_DC01; /**< Fault Address DID Register, offset: 0x80FC8 */
__I uint32_t FADR_DC01; /**< Fault Address Detail Register, offset: 0x80FCC */
uint8_t RESERVED_56[4];
__I uint32_t CSTA_DC01; /**< CAAM Status Register, offset: 0x80FD4 */
__I uint32_t SMVID_MS_DC01; /**< Secure Memory Version ID Register, most-significant half, offset: 0x80FD8 */
__I uint32_t SMVID_LS_DC01; /**< Secure Memory Version ID Register, least-significant half, offset: 0x80FDC */
__I uint32_t RVID_DC01; /**< RTIC Version ID Register, offset: 0x80FE0 */
__I uint32_t CCBVID_DC01; /**< CHA Cluster Block Version ID Register, offset: 0x80FE4 */
__I uint32_t CHAVID_MS_DC01; /**< CHA Version ID Register, most-significant half, offset: 0x80FE8 */
__I uint32_t CHAVID_LS_DC01; /**< CHA Version ID Register, least-significant half, offset: 0x80FEC */
__I uint32_t CHANUM_MS_DC01; /**< CHA Number Register, most-significant half, offset: 0x80FF0 */
__I uint32_t CHANUM_LS_DC01; /**< CHA Number Register, least-significant half, offset: 0x80FF4 */
__I uint32_t CAAMVID_MS_DC01; /**< CAAM Version ID Register, most-significant half, offset: 0x80FF8 */
__I uint32_t CAAMVID_LS_DC01; /**< CAAM Version ID Register, least-significant half, offset: 0x80FFC */
} CAAM_Type;
/* ----------------------------------------------------------------------------
-- CAAM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAAM_Register_Masks CAAM Register Masks
* @{
*/
/*! @name MCFGR - Master Configuration Register */
/*! @{ */
#define CAAM_MCFGR_NORMAL_BURST_MASK (0x1U)
#define CAAM_MCFGR_NORMAL_BURST_SHIFT (0U)
/*! NORMAL_BURST
* 0b0..Aligned 32 byte burst size target
* 0b1..Aligned 64 byte burst size target
*/
#define CAAM_MCFGR_NORMAL_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_NORMAL_BURST_SHIFT)) & CAAM_MCFGR_NORMAL_BURST_MASK)
#define CAAM_MCFGR_LARGE_BURST_MASK (0x4U)
#define CAAM_MCFGR_LARGE_BURST_SHIFT (2U)
#define CAAM_MCFGR_LARGE_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_LARGE_BURST_SHIFT)) & CAAM_MCFGR_LARGE_BURST_MASK)
#define CAAM_MCFGR_AXIPIPE_MASK (0xF0U)
#define CAAM_MCFGR_AXIPIPE_SHIFT (4U)
#define CAAM_MCFGR_AXIPIPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AXIPIPE_SHIFT)) & CAAM_MCFGR_AXIPIPE_MASK)
#define CAAM_MCFGR_AWCACHE_MASK (0xF00U)
#define CAAM_MCFGR_AWCACHE_SHIFT (8U)
#define CAAM_MCFGR_AWCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_AWCACHE_SHIFT)) & CAAM_MCFGR_AWCACHE_MASK)
#define CAAM_MCFGR_ARCACHE_MASK (0xF000U)
#define CAAM_MCFGR_ARCACHE_SHIFT (12U)
#define CAAM_MCFGR_ARCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_ARCACHE_SHIFT)) & CAAM_MCFGR_ARCACHE_MASK)
#define CAAM_MCFGR_PS_MASK (0x10000U)
#define CAAM_MCFGR_PS_SHIFT (16U)
/*! PS
* 0b0..Pointers fit in one 32-bit word (pointers are 32-bit addresses).
* 0b1..Pointers require two 32-bit words (pointers are 36-bit addresses).
*/
#define CAAM_MCFGR_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_PS_SHIFT)) & CAAM_MCFGR_PS_MASK)
#define CAAM_MCFGR_DWT_MASK (0x80000U)
#define CAAM_MCFGR_DWT_SHIFT (19U)
#define CAAM_MCFGR_DWT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DWT_SHIFT)) & CAAM_MCFGR_DWT_MASK)
#define CAAM_MCFGR_WRHD_MASK (0x8000000U)
#define CAAM_MCFGR_WRHD_SHIFT (27U)
#define CAAM_MCFGR_WRHD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WRHD_SHIFT)) & CAAM_MCFGR_WRHD_MASK)
#define CAAM_MCFGR_DMA_RST_MASK (0x10000000U)
#define CAAM_MCFGR_DMA_RST_SHIFT (28U)
#define CAAM_MCFGR_DMA_RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_DMA_RST_SHIFT)) & CAAM_MCFGR_DMA_RST_MASK)
#define CAAM_MCFGR_WDF_MASK (0x20000000U)
#define CAAM_MCFGR_WDF_SHIFT (29U)
#define CAAM_MCFGR_WDF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDF_SHIFT)) & CAAM_MCFGR_WDF_MASK)
#define CAAM_MCFGR_WDE_MASK (0x40000000U)
#define CAAM_MCFGR_WDE_SHIFT (30U)
#define CAAM_MCFGR_WDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_WDE_SHIFT)) & CAAM_MCFGR_WDE_MASK)
#define CAAM_MCFGR_SWRST_MASK (0x80000000U)
#define CAAM_MCFGR_SWRST_SHIFT (31U)
#define CAAM_MCFGR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MCFGR_SWRST_SHIFT)) & CAAM_MCFGR_SWRST_MASK)
/*! @} */
/*! @name PAGE0_SDID - Page 0 SDID Register */
/*! @{ */
#define CAAM_PAGE0_SDID_SDID_MASK (0x7FFFU)
#define CAAM_PAGE0_SDID_SDID_SHIFT (0U)
#define CAAM_PAGE0_SDID_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PAGE0_SDID_SDID_SHIFT)) & CAAM_PAGE0_SDID_SDID_MASK)
/*! @} */
/*! @name SCFGR - Security Configuration Register */
/*! @{ */
#define CAAM_SCFGR_PRIBLOB_MASK (0x3U)
#define CAAM_SCFGR_PRIBLOB_SHIFT (0U)
/*! PRIBLOB
* 0b00..Private secure boot software blobs
* 0b01..Private provisioning type 1 blobs
* 0b10..Private provisioning type 2 blobs
* 0b11..Normal operation blobs
*/
#define CAAM_SCFGR_PRIBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_PRIBLOB_SHIFT)) & CAAM_SCFGR_PRIBLOB_MASK)
#define CAAM_SCFGR_RNGSH0_MASK (0x200U)
#define CAAM_SCFGR_RNGSH0_SHIFT (9U)
/*! RNGSH0
* 0b0..When RNGSH0 is 0, RNG DRNG State Handle 0 can be instantiated in any mode. RNGSH0 is set to 0 only for testing.
* 0b1..When RNGSH0 is 1, RNG DRNG State Handle 0 cannot be instantiated in deterministic (test) mode. RNGSHO
* should be set to 1 before the RNG is instantiated. If it is currently instantiated in a deterministic mode,
* it will be un-instantiated. Once this bit has been written to a 1, it cannot be changed to a 0 until the
* next power on reset.
*/
#define CAAM_SCFGR_RNGSH0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_RNGSH0_SHIFT)) & CAAM_SCFGR_RNGSH0_MASK)
#define CAAM_SCFGR_LCK_TRNG_MASK (0x800U)
#define CAAM_SCFGR_LCK_TRNG_SHIFT (11U)
#define CAAM_SCFGR_LCK_TRNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_LCK_TRNG_SHIFT)) & CAAM_SCFGR_LCK_TRNG_MASK)
#define CAAM_SCFGR_VIRT_EN_MASK (0x8000U)
#define CAAM_SCFGR_VIRT_EN_SHIFT (15U)
/*! VIRT_EN
* 0b0..Disable job ring virtualization
* 0b1..Enable job ring virtualization
*/
#define CAAM_SCFGR_VIRT_EN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_VIRT_EN_SHIFT)) & CAAM_SCFGR_VIRT_EN_MASK)
#define CAAM_SCFGR_MPMRL_MASK (0x4000000U)
#define CAAM_SCFGR_MPMRL_SHIFT (26U)
#define CAAM_SCFGR_MPMRL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPMRL_SHIFT)) & CAAM_SCFGR_MPMRL_MASK)
#define CAAM_SCFGR_MPPKRC_MASK (0x8000000U)
#define CAAM_SCFGR_MPPKRC_SHIFT (27U)
#define CAAM_SCFGR_MPPKRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPPKRC_SHIFT)) & CAAM_SCFGR_MPPKRC_MASK)
#define CAAM_SCFGR_MPCURVE_MASK (0xF0000000U)
#define CAAM_SCFGR_MPCURVE_SHIFT (28U)
#define CAAM_SCFGR_MPCURVE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SCFGR_MPCURVE_SHIFT)) & CAAM_SCFGR_MPCURVE_MASK)
/*! @} */
/*! @name JRDID_MS - Job Ring 0 DID Register - most significant half..Job Ring 3 DID Register - most significant half */
/*! @{ */
#define CAAM_JRDID_MS_PRIM_DID_MASK (0xFU)
#define CAAM_JRDID_MS_PRIM_DID_SHIFT (0U)
#define CAAM_JRDID_MS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_DID_SHIFT)) & CAAM_JRDID_MS_PRIM_DID_MASK)
#define CAAM_JRDID_MS_PRIM_TZ_MASK (0x10U)
#define CAAM_JRDID_MS_PRIM_TZ_SHIFT (4U)
#define CAAM_JRDID_MS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_TZ_SHIFT)) & CAAM_JRDID_MS_PRIM_TZ_MASK)
#define CAAM_JRDID_MS_SDID_MS_MASK (0x7FE0U)
#define CAAM_JRDID_MS_SDID_MS_SHIFT (5U)
#define CAAM_JRDID_MS_SDID_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_SDID_MS_SHIFT)) & CAAM_JRDID_MS_SDID_MS_MASK)
#define CAAM_JRDID_MS_TZ_OWN_MASK (0x8000U)
#define CAAM_JRDID_MS_TZ_OWN_SHIFT (15U)
#define CAAM_JRDID_MS_TZ_OWN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_TZ_OWN_SHIFT)) & CAAM_JRDID_MS_TZ_OWN_MASK)
#define CAAM_JRDID_MS_AMTD_MASK (0x10000U)
#define CAAM_JRDID_MS_AMTD_SHIFT (16U)
#define CAAM_JRDID_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_AMTD_SHIFT)) & CAAM_JRDID_MS_AMTD_MASK)
#define CAAM_JRDID_MS_LAMTD_MASK (0x20000U)
#define CAAM_JRDID_MS_LAMTD_SHIFT (17U)
#define CAAM_JRDID_MS_LAMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LAMTD_SHIFT)) & CAAM_JRDID_MS_LAMTD_MASK)
#define CAAM_JRDID_MS_PRIM_ICID_MASK (0x3FF80000U)
#define CAAM_JRDID_MS_PRIM_ICID_SHIFT (19U)
#define CAAM_JRDID_MS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_PRIM_ICID_SHIFT)) & CAAM_JRDID_MS_PRIM_ICID_MASK)
#define CAAM_JRDID_MS_USE_OUT_MASK (0x40000000U)
#define CAAM_JRDID_MS_USE_OUT_SHIFT (30U)
#define CAAM_JRDID_MS_USE_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_USE_OUT_SHIFT)) & CAAM_JRDID_MS_USE_OUT_MASK)
#define CAAM_JRDID_MS_LDID_MASK (0x80000000U)
#define CAAM_JRDID_MS_LDID_SHIFT (31U)
#define CAAM_JRDID_MS_LDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_MS_LDID_SHIFT)) & CAAM_JRDID_MS_LDID_MASK)
/*! @} */
/* The count of CAAM_JRDID_MS */
#define CAAM_JRDID_MS_COUNT (4U)
/*! @name JRDID_LS - Job Ring 0 DID Register - least significant half..Job Ring 3 DID Register - least significant half */
/*! @{ */
#define CAAM_JRDID_LS_OUT_DID_MASK (0xFU)
#define CAAM_JRDID_LS_OUT_DID_SHIFT (0U)
#define CAAM_JRDID_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_DID_SHIFT)) & CAAM_JRDID_LS_OUT_DID_MASK)
#define CAAM_JRDID_LS_OUT_ICID_MASK (0x3FF80000U)
#define CAAM_JRDID_LS_OUT_ICID_SHIFT (19U)
#define CAAM_JRDID_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRDID_LS_OUT_ICID_SHIFT)) & CAAM_JRDID_LS_OUT_ICID_MASK)
/*! @} */
/* The count of CAAM_JRDID_LS */
#define CAAM_JRDID_LS_COUNT (4U)
/*! @name DEBUGCTL - Debug Control Register */
/*! @{ */
#define CAAM_DEBUGCTL_STOP_MASK (0x10000U)
#define CAAM_DEBUGCTL_STOP_SHIFT (16U)
#define CAAM_DEBUGCTL_STOP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_SHIFT)) & CAAM_DEBUGCTL_STOP_MASK)
#define CAAM_DEBUGCTL_STOP_ACK_MASK (0x20000U)
#define CAAM_DEBUGCTL_STOP_ACK_SHIFT (17U)
#define CAAM_DEBUGCTL_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DEBUGCTL_STOP_ACK_SHIFT)) & CAAM_DEBUGCTL_STOP_ACK_MASK)
/*! @} */
/*! @name JRSTARTR - Job Ring Start Register */
/*! @{ */
#define CAAM_JRSTARTR_Start_JR0_MASK (0x1U)
#define CAAM_JRSTARTR_Start_JR0_SHIFT (0U)
/*! Start_JR0
* 0b0..Stop Mode. The JR0DID register and the SMVBA register for Job Ring 0 can be written but the IRBAR, IRSR,
* IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 0 are NOT accessible. If Job Ring 0 is
* allocated to TrustZone SecureWorld (JR0DID[TZ]=1), the JR0DID and SMVBA register can be written only via a
* bus transaction that has ns=0.
* 0b1..Start Mode. The JR0DID register and the SMVBA register for Job Ring 0 CANNOT be written but the IRBAR,
* IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 0 ARE accessible. If Job Ring 0 is
* allocated to TrustZone SecureWorld (JR0DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
* ORJRR, ORSFR and JRSTAR registers for Job Ring 0 can be written only via a bus transaction that has ns=0.
*/
#define CAAM_JRSTARTR_Start_JR0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR0_SHIFT)) & CAAM_JRSTARTR_Start_JR0_MASK)
#define CAAM_JRSTARTR_Start_JR1_MASK (0x2U)
#define CAAM_JRSTARTR_Start_JR1_SHIFT (1U)
/*! Start_JR1
* 0b0..Stop Mode. The JR1DID register and the SMVBA register for Job Ring 1 can be written but the IRBAR, IRSR,
* IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 1 are NOT accessible. If Job Ring 1 is
* allocated to TrustZone SecureWorld (JR1DID[TZ]=1), the JR1DID and SMVBA register can be written only via a
* bus transaction that has ns=0.
* 0b1..Start Mode. The JR1DID register and the SMVBA register for Job Ring 1 CANNOT be written but the IRBAR,
* IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 1 ARE accessible. If Job Ring 1 is
* allocated to TrustZone SecureWorld (JR1DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
* ORJRR, ORSFR and JRSTAR registers for Job Ring 1 can be written only via a bus transaction that has ns=0.
*/
#define CAAM_JRSTARTR_Start_JR1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR1_SHIFT)) & CAAM_JRSTARTR_Start_JR1_MASK)
#define CAAM_JRSTARTR_Start_JR2_MASK (0x4U)
#define CAAM_JRSTARTR_Start_JR2_SHIFT (2U)
/*! Start_JR2
* 0b0..Stop Mode. The JR2DID register and the SMVBA register for Job Ring 2 can be written but the IRBAR, IRSR,
* IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 2 are NOT accessible. If Job Ring 2 is
* allocated to TrustZone SecureWorld (JR2DID[TZ]=1), the JR2DID and SMVBA register can be written only via a
* bus transaction that has ns=0.
* 0b1..Start Mode. The JR2DID register and the SMVBA register for Job Ring 2 CANNOT be written but the IRBAR,
* IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 2 ARE accessible. If Job Ring 2 is
* allocated to TrustZone SecureWorld (JR2DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
* ORJRR, ORSFR and JRSTAR registers for Job Ring 2 can be written only via a bus transaction that has ns=0.
*/
#define CAAM_JRSTARTR_Start_JR2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR2_SHIFT)) & CAAM_JRSTARTR_Start_JR2_MASK)
#define CAAM_JRSTARTR_Start_JR3_MASK (0x8U)
#define CAAM_JRSTARTR_Start_JR3_SHIFT (3U)
/*! Start_JR3
* 0b0..Stop Mode. The JR3DID register and the SMVBA register for Job Ring 3 can be written but the IRBAR, IRSR,
* IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 3 are NOT accessible. If Job Ring 3 is
* allocated to TrustZone SecureWorld (JR3DID[TZ]=1), the JR3DID and SMVBA register can be written only via a
* bus transaction that has ns=0.
* 0b1..Start Mode. The JR3DID register and the SMVBA register for Job Ring 3 CANNOT be written but the IRBAR,
* IRSR, IRSAR, IRJAR, ORBAR, ORSR, ORJRR, ORSFR and JRSTAR for Job Ring 3 ARE accessible. If Job Ring 3 is
* allocated to TrustZone SecureWorld (JR3DID[TZ]=1), then the SMVBA, IRBAR, IRSR, IRSAR, IRJAR, ORBAR, ORSR,
* ORJRR, ORSFR and JRSTAR registers for Job Ring 3 can be written only via a bus transaction that has ns=0.
*/
#define CAAM_JRSTARTR_Start_JR3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTARTR_Start_JR3_SHIFT)) & CAAM_JRSTARTR_Start_JR3_MASK)
/*! @} */
/*! @name RTIC_OWN - RTIC OWN Register */
/*! @{ */
#define CAAM_RTIC_OWN_ROWN_DID_MASK (0xFU)
#define CAAM_RTIC_OWN_ROWN_DID_SHIFT (0U)
/*! ROWN_DID - RTIC Owner's DID
*/
#define CAAM_RTIC_OWN_ROWN_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_DID_SHIFT)) & CAAM_RTIC_OWN_ROWN_DID_MASK)
#define CAAM_RTIC_OWN_ROWN_TZ_MASK (0x10U)
#define CAAM_RTIC_OWN_ROWN_TZ_SHIFT (4U)
#define CAAM_RTIC_OWN_ROWN_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_ROWN_TZ_SHIFT)) & CAAM_RTIC_OWN_ROWN_TZ_MASK)
#define CAAM_RTIC_OWN_LCK_MASK (0x80000000U)
#define CAAM_RTIC_OWN_LCK_SHIFT (31U)
#define CAAM_RTIC_OWN_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_OWN_LCK_SHIFT)) & CAAM_RTIC_OWN_LCK_MASK)
/*! @} */
/*! @name RTIC_DID - RTIC DID Register for Block A..RTIC DID Register for Block D */
/*! @{ */
#define CAAM_RTIC_DID_RTIC_DID_MASK (0xFU)
#define CAAM_RTIC_DID_RTIC_DID_SHIFT (0U)
#define CAAM_RTIC_DID_RTIC_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_DID_SHIFT)) & CAAM_RTIC_DID_RTIC_DID_MASK)
#define CAAM_RTIC_DID_RTIC_TZ_MASK (0x10U)
#define CAAM_RTIC_DID_RTIC_TZ_SHIFT (4U)
#define CAAM_RTIC_DID_RTIC_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_TZ_SHIFT)) & CAAM_RTIC_DID_RTIC_TZ_MASK)
#define CAAM_RTIC_DID_RTIC_ICID_MASK (0x3FF80000U)
#define CAAM_RTIC_DID_RTIC_ICID_SHIFT (19U)
#define CAAM_RTIC_DID_RTIC_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTIC_DID_RTIC_ICID_SHIFT)) & CAAM_RTIC_DID_RTIC_ICID_MASK)
/*! @} */
/* The count of CAAM_RTIC_DID */
#define CAAM_RTIC_DID_COUNT (4U)
/*! @name DECORSR - DECO Request Source Register */
/*! @{ */
#define CAAM_DECORSR_JR_MASK (0x3U)
#define CAAM_DECORSR_JR_SHIFT (0U)
#define CAAM_DECORSR_JR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_JR_SHIFT)) & CAAM_DECORSR_JR_MASK)
#define CAAM_DECORSR_VALID_MASK (0x80000000U)
#define CAAM_DECORSR_VALID_SHIFT (31U)
#define CAAM_DECORSR_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORSR_VALID_SHIFT)) & CAAM_DECORSR_VALID_MASK)
/*! @} */
/*! @name DECORR - DECO Request Register */
/*! @{ */
#define CAAM_DECORR_RQD0_MASK (0x1U)
#define CAAM_DECORR_RQD0_SHIFT (0U)
#define CAAM_DECORR_RQD0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_RQD0_SHIFT)) & CAAM_DECORR_RQD0_MASK)
#define CAAM_DECORR_DEN0_MASK (0x10000U)
#define CAAM_DECORR_DEN0_SHIFT (16U)
#define CAAM_DECORR_DEN0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECORR_DEN0_SHIFT)) & CAAM_DECORR_DEN0_MASK)
/*! @} */
/*! @name DECODID_MS - DECO0 DID Register - most significant half */
/*! @{ */
#define CAAM_DECODID_MS_DPRIM_DID_MASK (0xFU)
#define CAAM_DECODID_MS_DPRIM_DID_SHIFT (0U)
/*! DPRIM_DID - DECO Owner
*/
#define CAAM_DECODID_MS_DPRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_DPRIM_DID_SHIFT)) & CAAM_DECODID_MS_DPRIM_DID_MASK)
#define CAAM_DECODID_MS_D_NS_MASK (0x10U)
#define CAAM_DECODID_MS_D_NS_SHIFT (4U)
#define CAAM_DECODID_MS_D_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_D_NS_SHIFT)) & CAAM_DECODID_MS_D_NS_MASK)
#define CAAM_DECODID_MS_LCK_MASK (0x80000000U)
#define CAAM_DECODID_MS_LCK_SHIFT (31U)
#define CAAM_DECODID_MS_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_MS_LCK_SHIFT)) & CAAM_DECODID_MS_LCK_MASK)
/*! @} */
/* The count of CAAM_DECODID_MS */
#define CAAM_DECODID_MS_COUNT (1U)
/*! @name DECODID_LS - DECO0 DID Register - least significant half */
/*! @{ */
#define CAAM_DECODID_LS_DSEQ_DID_MASK (0xFU)
#define CAAM_DECODID_LS_DSEQ_DID_SHIFT (0U)
#define CAAM_DECODID_LS_DSEQ_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DSEQ_DID_MASK)
#define CAAM_DECODID_LS_DSEQ_NS_MASK (0x10U)
#define CAAM_DECODID_LS_DSEQ_NS_SHIFT (4U)
#define CAAM_DECODID_LS_DSEQ_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DSEQ_NS_MASK)
#define CAAM_DECODID_LS_DNSEQ_DID_MASK (0xF0000U)
#define CAAM_DECODID_LS_DNSEQ_DID_SHIFT (16U)
#define CAAM_DECODID_LS_DNSEQ_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNSEQ_DID_SHIFT)) & CAAM_DECODID_LS_DNSEQ_DID_MASK)
#define CAAM_DECODID_LS_DNONSEQ_NS_MASK (0x100000U)
#define CAAM_DECODID_LS_DNONSEQ_NS_SHIFT (20U)
#define CAAM_DECODID_LS_DNONSEQ_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DECODID_LS_DNONSEQ_NS_SHIFT)) & CAAM_DECODID_LS_DNONSEQ_NS_MASK)
/*! @} */
/* The count of CAAM_DECODID_LS */
#define CAAM_DECODID_LS_COUNT (1U)
/*! @name DAR - DECO Availability Register */
/*! @{ */
#define CAAM_DAR_NYA0_MASK (0x1U)
#define CAAM_DAR_NYA0_SHIFT (0U)
#define CAAM_DAR_NYA0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DAR_NYA0_SHIFT)) & CAAM_DAR_NYA0_MASK)
/*! @} */
/*! @name DRR - DECO Reset Register */
/*! @{ */
#define CAAM_DRR_RST0_MASK (0x1U)
#define CAAM_DRR_RST0_SHIFT (0U)
#define CAAM_DRR_RST0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DRR_RST0_SHIFT)) & CAAM_DRR_RST0_MASK)
/*! @} */
/*! @name JRSMVBAR - Job Ring 0 Secure Memory Virtual Base Address Register..Job Ring 3 Secure Memory Virtual Base Address Register */
/*! @{ */
#define CAAM_JRSMVBAR_SMVBA_MASK (0xFFFFFFFFU)
#define CAAM_JRSMVBAR_SMVBA_SHIFT (0U)
#define CAAM_JRSMVBAR_SMVBA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSMVBAR_SMVBA_SHIFT)) & CAAM_JRSMVBAR_SMVBA_MASK)
/*! @} */
/* The count of CAAM_JRSMVBAR */
#define CAAM_JRSMVBAR_COUNT (4U)
/*! @name PBSL - Peak Bandwidth Smoothing Limit Register */
/*! @{ */
#define CAAM_PBSL_PBSL_MASK (0x7FU)
#define CAAM_PBSL_PBSL_SHIFT (0U)
#define CAAM_PBSL_PBSL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PBSL_PBSL_SHIFT)) & CAAM_PBSL_PBSL_MASK)
/*! @} */
/*! @name DMA_AIDL_MAP_MS - DMA0_AIDL_MAP_MS */
/*! @{ */
#define CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK (0xFFU)
#define CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT (0U)
#define CAAM_DMA_AIDL_MAP_MS_AID4_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID4_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID4_BID_MASK)
#define CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK (0xFF00U)
#define CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT (8U)
#define CAAM_DMA_AIDL_MAP_MS_AID5_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID5_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID5_BID_MASK)
#define CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK (0xFF0000U)
#define CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT (16U)
#define CAAM_DMA_AIDL_MAP_MS_AID6_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID6_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID6_BID_MASK)
#define CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK (0xFF000000U)
#define CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT (24U)
#define CAAM_DMA_AIDL_MAP_MS_AID7_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_MS_AID7_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_MS_AID7_BID_MASK)
/*! @} */
/* The count of CAAM_DMA_AIDL_MAP_MS */
#define CAAM_DMA_AIDL_MAP_MS_COUNT (1U)
/*! @name DMA_AIDL_MAP_LS - DMA0_AIDL_MAP_LS */
/*! @{ */
#define CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK (0xFFU)
#define CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT (0U)
#define CAAM_DMA_AIDL_MAP_LS_AID0_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID0_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID0_BID_MASK)
#define CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK (0xFF00U)
#define CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT (8U)
#define CAAM_DMA_AIDL_MAP_LS_AID1_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID1_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID1_BID_MASK)
#define CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK (0xFF0000U)
#define CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT (16U)
#define CAAM_DMA_AIDL_MAP_LS_AID2_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID2_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID2_BID_MASK)
#define CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK (0xFF000000U)
#define CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT (24U)
#define CAAM_DMA_AIDL_MAP_LS_AID3_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDL_MAP_LS_AID3_BID_SHIFT)) & CAAM_DMA_AIDL_MAP_LS_AID3_BID_MASK)
/*! @} */
/* The count of CAAM_DMA_AIDL_MAP_LS */
#define CAAM_DMA_AIDL_MAP_LS_COUNT (1U)
/*! @name DMA_AIDM_MAP_MS - DMA0_AIDM_MAP_MS */
/*! @{ */
#define CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK (0xFFU)
#define CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT (0U)
#define CAAM_DMA_AIDM_MAP_MS_AID12_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID12_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID12_BID_MASK)
#define CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK (0xFF00U)
#define CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT (8U)
#define CAAM_DMA_AIDM_MAP_MS_AID13_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID13_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID13_BID_MASK)
#define CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK (0xFF0000U)
#define CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT (16U)
#define CAAM_DMA_AIDM_MAP_MS_AID14_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID14_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID14_BID_MASK)
#define CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK (0xFF000000U)
#define CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT (24U)
#define CAAM_DMA_AIDM_MAP_MS_AID15_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_MS_AID15_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_MS_AID15_BID_MASK)
/*! @} */
/* The count of CAAM_DMA_AIDM_MAP_MS */
#define CAAM_DMA_AIDM_MAP_MS_COUNT (1U)
/*! @name DMA_AIDM_MAP_LS - DMA0_AIDM_MAP_LS */
/*! @{ */
#define CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK (0xFFU)
#define CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT (0U)
#define CAAM_DMA_AIDM_MAP_LS_AID8_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID8_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID8_BID_MASK)
#define CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK (0xFF00U)
#define CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT (8U)
#define CAAM_DMA_AIDM_MAP_LS_AID9_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID9_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID9_BID_MASK)
#define CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK (0xFF0000U)
#define CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT (16U)
#define CAAM_DMA_AIDM_MAP_LS_AID10_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID10_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID10_BID_MASK)
#define CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK (0xFF000000U)
#define CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT (24U)
#define CAAM_DMA_AIDM_MAP_LS_AID11_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_AIDM_MAP_LS_AID11_BID_SHIFT)) & CAAM_DMA_AIDM_MAP_LS_AID11_BID_MASK)
/*! @} */
/* The count of CAAM_DMA_AIDM_MAP_LS */
#define CAAM_DMA_AIDM_MAP_LS_COUNT (1U)
/*! @name DMA0_AID_ENB - DMA0 AXI ID Enable Register */
/*! @{ */
#define CAAM_DMA0_AID_ENB_AID0E_MASK (0x1U)
#define CAAM_DMA0_AID_ENB_AID0E_SHIFT (0U)
#define CAAM_DMA0_AID_ENB_AID0E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID0E_SHIFT)) & CAAM_DMA0_AID_ENB_AID0E_MASK)
#define CAAM_DMA0_AID_ENB_AID1E_MASK (0x2U)
#define CAAM_DMA0_AID_ENB_AID1E_SHIFT (1U)
#define CAAM_DMA0_AID_ENB_AID1E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID1E_SHIFT)) & CAAM_DMA0_AID_ENB_AID1E_MASK)
#define CAAM_DMA0_AID_ENB_AID2E_MASK (0x4U)
#define CAAM_DMA0_AID_ENB_AID2E_SHIFT (2U)
#define CAAM_DMA0_AID_ENB_AID2E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID2E_SHIFT)) & CAAM_DMA0_AID_ENB_AID2E_MASK)
#define CAAM_DMA0_AID_ENB_AID3E_MASK (0x8U)
#define CAAM_DMA0_AID_ENB_AID3E_SHIFT (3U)
#define CAAM_DMA0_AID_ENB_AID3E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID3E_SHIFT)) & CAAM_DMA0_AID_ENB_AID3E_MASK)
#define CAAM_DMA0_AID_ENB_AID4E_MASK (0x10U)
#define CAAM_DMA0_AID_ENB_AID4E_SHIFT (4U)
#define CAAM_DMA0_AID_ENB_AID4E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID4E_SHIFT)) & CAAM_DMA0_AID_ENB_AID4E_MASK)
#define CAAM_DMA0_AID_ENB_AID5E_MASK (0x20U)
#define CAAM_DMA0_AID_ENB_AID5E_SHIFT (5U)
#define CAAM_DMA0_AID_ENB_AID5E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID5E_SHIFT)) & CAAM_DMA0_AID_ENB_AID5E_MASK)
#define CAAM_DMA0_AID_ENB_AID6E_MASK (0x40U)
#define CAAM_DMA0_AID_ENB_AID6E_SHIFT (6U)
#define CAAM_DMA0_AID_ENB_AID6E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID6E_SHIFT)) & CAAM_DMA0_AID_ENB_AID6E_MASK)
#define CAAM_DMA0_AID_ENB_AID7E_MASK (0x80U)
#define CAAM_DMA0_AID_ENB_AID7E_SHIFT (7U)
#define CAAM_DMA0_AID_ENB_AID7E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID7E_SHIFT)) & CAAM_DMA0_AID_ENB_AID7E_MASK)
#define CAAM_DMA0_AID_ENB_AID8E_MASK (0x100U)
#define CAAM_DMA0_AID_ENB_AID8E_SHIFT (8U)
#define CAAM_DMA0_AID_ENB_AID8E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID8E_SHIFT)) & CAAM_DMA0_AID_ENB_AID8E_MASK)
#define CAAM_DMA0_AID_ENB_AID9E_MASK (0x200U)
#define CAAM_DMA0_AID_ENB_AID9E_SHIFT (9U)
#define CAAM_DMA0_AID_ENB_AID9E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID9E_SHIFT)) & CAAM_DMA0_AID_ENB_AID9E_MASK)
#define CAAM_DMA0_AID_ENB_AID10E_MASK (0x400U)
#define CAAM_DMA0_AID_ENB_AID10E_SHIFT (10U)
#define CAAM_DMA0_AID_ENB_AID10E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID10E_SHIFT)) & CAAM_DMA0_AID_ENB_AID10E_MASK)
#define CAAM_DMA0_AID_ENB_AID11E_MASK (0x800U)
#define CAAM_DMA0_AID_ENB_AID11E_SHIFT (11U)
#define CAAM_DMA0_AID_ENB_AID11E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID11E_SHIFT)) & CAAM_DMA0_AID_ENB_AID11E_MASK)
#define CAAM_DMA0_AID_ENB_AID12E_MASK (0x1000U)
#define CAAM_DMA0_AID_ENB_AID12E_SHIFT (12U)
#define CAAM_DMA0_AID_ENB_AID12E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID12E_SHIFT)) & CAAM_DMA0_AID_ENB_AID12E_MASK)
#define CAAM_DMA0_AID_ENB_AID13E_MASK (0x2000U)
#define CAAM_DMA0_AID_ENB_AID13E_SHIFT (13U)
#define CAAM_DMA0_AID_ENB_AID13E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID13E_SHIFT)) & CAAM_DMA0_AID_ENB_AID13E_MASK)
#define CAAM_DMA0_AID_ENB_AID14E_MASK (0x4000U)
#define CAAM_DMA0_AID_ENB_AID14E_SHIFT (14U)
#define CAAM_DMA0_AID_ENB_AID14E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID14E_SHIFT)) & CAAM_DMA0_AID_ENB_AID14E_MASK)
#define CAAM_DMA0_AID_ENB_AID15E_MASK (0x8000U)
#define CAAM_DMA0_AID_ENB_AID15E_SHIFT (15U)
#define CAAM_DMA0_AID_ENB_AID15E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AID_ENB_AID15E_SHIFT)) & CAAM_DMA0_AID_ENB_AID15E_MASK)
/*! @} */
/*! @name DMA0_ARD_TC - DMA0 AXI Read Timing Check Register */
/*! @{ */
#define CAAM_DMA0_ARD_TC_ARSC_MASK (0xFFFFFU)
#define CAAM_DMA0_ARD_TC_ARSC_SHIFT (0U)
#define CAAM_DMA0_ARD_TC_ARSC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARSC_SHIFT)) & CAAM_DMA0_ARD_TC_ARSC_MASK)
#define CAAM_DMA0_ARD_TC_ARLC_MASK (0xFFFFF000000U)
#define CAAM_DMA0_ARD_TC_ARLC_SHIFT (24U)
#define CAAM_DMA0_ARD_TC_ARLC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARLC_SHIFT)) & CAAM_DMA0_ARD_TC_ARLC_MASK)
#define CAAM_DMA0_ARD_TC_ARL_MASK (0xFFF000000000000U)
#define CAAM_DMA0_ARD_TC_ARL_SHIFT (48U)
#define CAAM_DMA0_ARD_TC_ARL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARL_SHIFT)) & CAAM_DMA0_ARD_TC_ARL_MASK)
#define CAAM_DMA0_ARD_TC_ARTL_MASK (0x1000000000000000U)
#define CAAM_DMA0_ARD_TC_ARTL_SHIFT (60U)
#define CAAM_DMA0_ARD_TC_ARTL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTL_SHIFT)) & CAAM_DMA0_ARD_TC_ARTL_MASK)
#define CAAM_DMA0_ARD_TC_ARTT_MASK (0x2000000000000000U)
#define CAAM_DMA0_ARD_TC_ARTT_SHIFT (61U)
#define CAAM_DMA0_ARD_TC_ARTT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTT_SHIFT)) & CAAM_DMA0_ARD_TC_ARTT_MASK)
#define CAAM_DMA0_ARD_TC_ARCT_MASK (0x4000000000000000U)
#define CAAM_DMA0_ARD_TC_ARCT_SHIFT (62U)
#define CAAM_DMA0_ARD_TC_ARCT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARCT_SHIFT)) & CAAM_DMA0_ARD_TC_ARCT_MASK)
#define CAAM_DMA0_ARD_TC_ARTCE_MASK (0x8000000000000000U)
#define CAAM_DMA0_ARD_TC_ARTCE_SHIFT (63U)
#define CAAM_DMA0_ARD_TC_ARTCE(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_ARD_TC_ARTCE_SHIFT)) & CAAM_DMA0_ARD_TC_ARTCE_MASK)
/*! @} */
/*! @name DMA0_ARD_LAT - DMA0 Read Timing Check Latency Register */
/*! @{ */
#define CAAM_DMA0_ARD_LAT_SARL_MASK (0xFFFFFFFFU)
#define CAAM_DMA0_ARD_LAT_SARL_SHIFT (0U)
#define CAAM_DMA0_ARD_LAT_SARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_ARD_LAT_SARL_SHIFT)) & CAAM_DMA0_ARD_LAT_SARL_MASK)
/*! @} */
/*! @name DMA0_AWR_TC - DMA0 AXI Write Timing Check Register */
/*! @{ */
#define CAAM_DMA0_AWR_TC_AWSC_MASK (0xFFFFFU)
#define CAAM_DMA0_AWR_TC_AWSC_SHIFT (0U)
#define CAAM_DMA0_AWR_TC_AWSC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWSC_SHIFT)) & CAAM_DMA0_AWR_TC_AWSC_MASK)
#define CAAM_DMA0_AWR_TC_AWLC_MASK (0xFFFFF000000U)
#define CAAM_DMA0_AWR_TC_AWLC_SHIFT (24U)
#define CAAM_DMA0_AWR_TC_AWLC(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWLC_SHIFT)) & CAAM_DMA0_AWR_TC_AWLC_MASK)
#define CAAM_DMA0_AWR_TC_AWL_MASK (0xFFF000000000000U)
#define CAAM_DMA0_AWR_TC_AWL_SHIFT (48U)
#define CAAM_DMA0_AWR_TC_AWL(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWL_SHIFT)) & CAAM_DMA0_AWR_TC_AWL_MASK)
#define CAAM_DMA0_AWR_TC_AWTT_MASK (0x2000000000000000U)
#define CAAM_DMA0_AWR_TC_AWTT_SHIFT (61U)
#define CAAM_DMA0_AWR_TC_AWTT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTT_SHIFT)) & CAAM_DMA0_AWR_TC_AWTT_MASK)
#define CAAM_DMA0_AWR_TC_AWCT_MASK (0x4000000000000000U)
#define CAAM_DMA0_AWR_TC_AWCT_SHIFT (62U)
#define CAAM_DMA0_AWR_TC_AWCT(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWCT_SHIFT)) & CAAM_DMA0_AWR_TC_AWCT_MASK)
#define CAAM_DMA0_AWR_TC_AWTCE_MASK (0x8000000000000000U)
#define CAAM_DMA0_AWR_TC_AWTCE_SHIFT (63U)
#define CAAM_DMA0_AWR_TC_AWTCE(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DMA0_AWR_TC_AWTCE_SHIFT)) & CAAM_DMA0_AWR_TC_AWTCE_MASK)
/*! @} */
/*! @name DMA0_AWR_LAT - DMA0 Write Timing Check Latency Register */
/*! @{ */
#define CAAM_DMA0_AWR_LAT_SAWL_MASK (0xFFFFFFFFU)
#define CAAM_DMA0_AWR_LAT_SAWL_SHIFT (0U)
#define CAAM_DMA0_AWR_LAT_SAWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA0_AWR_LAT_SAWL_SHIFT)) & CAAM_DMA0_AWR_LAT_SAWL_MASK)
/*! @} */
/*! @name MPPKR - Manufacturing Protection Private Key Register */
/*! @{ */
#define CAAM_MPPKR_MPPrivK_MASK (0xFFU)
#define CAAM_MPPKR_MPPrivK_SHIFT (0U)
#define CAAM_MPPKR_MPPrivK(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPPKR_MPPrivK_SHIFT)) & CAAM_MPPKR_MPPrivK_MASK)
/*! @} */
/* The count of CAAM_MPPKR */
#define CAAM_MPPKR_COUNT (64U)
/*! @name MPMR - Manufacturing Protection Message Register */
/*! @{ */
#define CAAM_MPMR_MPMSG_MASK (0xFFU)
#define CAAM_MPMR_MPMSG_SHIFT (0U)
#define CAAM_MPMR_MPMSG(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPMR_MPMSG_SHIFT)) & CAAM_MPMR_MPMSG_MASK)
/*! @} */
/* The count of CAAM_MPMR */
#define CAAM_MPMR_COUNT (32U)
/*! @name MPTESTR - Manufacturing Protection Test Register */
/*! @{ */
#define CAAM_MPTESTR_TEST_VALUE_MASK (0xFFU)
#define CAAM_MPTESTR_TEST_VALUE_SHIFT (0U)
#define CAAM_MPTESTR_TEST_VALUE(x) (((uint8_t)(((uint8_t)(x)) << CAAM_MPTESTR_TEST_VALUE_SHIFT)) & CAAM_MPTESTR_TEST_VALUE_MASK)
/*! @} */
/* The count of CAAM_MPTESTR */
#define CAAM_MPTESTR_COUNT (32U)
/*! @name MPECC - Manufacturing Protection ECC Register */
/*! @{ */
#define CAAM_MPECC_MP_SYNDROME_MASK (0x1FF0000U)
#define CAAM_MPECC_MP_SYNDROME_SHIFT (16U)
/*! MP_SYNDROME
* 0b000000000..The MP Key in the SFP passes the ECC check.
* 0b000000001-0b111111111..The MP Key in the SFP fails the ECC check, and this is the ECC failure syndrome.
*/
#define CAAM_MPECC_MP_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_SYNDROME_SHIFT)) & CAAM_MPECC_MP_SYNDROME_MASK)
#define CAAM_MPECC_MP_ZERO_MASK (0x8000000U)
#define CAAM_MPECC_MP_ZERO_SHIFT (27U)
/*! MP_ZERO
* 0b0..The MP Key in the SFP has a non-zero value.
* 0b1..The MP Key in the SFP is all zeros (unprogrammed).
*/
#define CAAM_MPECC_MP_ZERO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_MPECC_MP_ZERO_SHIFT)) & CAAM_MPECC_MP_ZERO_MASK)
/*! @} */
/*! @name JDKEKR - Job Descriptor Key Encryption Key Register */
/*! @{ */
#define CAAM_JDKEKR_JDKEK_MASK (0xFFFFFFFFU)
#define CAAM_JDKEKR_JDKEK_SHIFT (0U)
#define CAAM_JDKEKR_JDKEK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JDKEKR_JDKEK_SHIFT)) & CAAM_JDKEKR_JDKEK_MASK)
/*! @} */
/* The count of CAAM_JDKEKR */
#define CAAM_JDKEKR_COUNT (8U)
/*! @name TDKEKR - Trusted Descriptor Key Encryption Key Register */
/*! @{ */
#define CAAM_TDKEKR_TDKEK_MASK (0xFFFFFFFFU)
#define CAAM_TDKEKR_TDKEK_SHIFT (0U)
#define CAAM_TDKEKR_TDKEK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_TDKEKR_TDKEK_SHIFT)) & CAAM_TDKEKR_TDKEK_MASK)
/*! @} */
/* The count of CAAM_TDKEKR */
#define CAAM_TDKEKR_COUNT (8U)
/*! @name TDSKR - Trusted Descriptor Signing Key Register */
/*! @{ */
#define CAAM_TDSKR_TDSK_MASK (0xFFFFFFFFU)
#define CAAM_TDSKR_TDSK_SHIFT (0U)
#define CAAM_TDSKR_TDSK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_TDSKR_TDSK_SHIFT)) & CAAM_TDSKR_TDSK_MASK)
/*! @} */
/* The count of CAAM_TDSKR */
#define CAAM_TDSKR_COUNT (8U)
/*! @name SKNR - Secure Key Nonce Register */
/*! @{ */
#define CAAM_SKNR_SK_NONCE_LS_MASK (0xFFFFFFFFU)
#define CAAM_SKNR_SK_NONCE_LS_SHIFT (0U)
#define CAAM_SKNR_SK_NONCE_LS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_LS_SHIFT)) & CAAM_SKNR_SK_NONCE_LS_MASK)
#define CAAM_SKNR_SK_NONCE_MS_MASK (0x7FFF00000000U)
#define CAAM_SKNR_SK_NONCE_MS_SHIFT (32U)
#define CAAM_SKNR_SK_NONCE_MS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_SKNR_SK_NONCE_MS_SHIFT)) & CAAM_SKNR_SK_NONCE_MS_MASK)
/*! @} */
/*! @name DMA_STA - DMA Status Register */
/*! @{ */
#define CAAM_DMA_STA_DMA0_ETIF_MASK (0x1FU)
#define CAAM_DMA_STA_DMA0_ETIF_SHIFT (0U)
#define CAAM_DMA_STA_DMA0_ETIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ETIF_SHIFT)) & CAAM_DMA_STA_DMA0_ETIF_MASK)
#define CAAM_DMA_STA_DMA0_ITIF_MASK (0x20U)
#define CAAM_DMA_STA_DMA0_ITIF_SHIFT (5U)
#define CAAM_DMA_STA_DMA0_ITIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_ITIF_SHIFT)) & CAAM_DMA_STA_DMA0_ITIF_MASK)
#define CAAM_DMA_STA_DMA0_IDLE_MASK (0x80U)
#define CAAM_DMA_STA_DMA0_IDLE_SHIFT (7U)
#define CAAM_DMA_STA_DMA0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_STA_DMA0_IDLE_SHIFT)) & CAAM_DMA_STA_DMA0_IDLE_MASK)
/*! @} */
/*! @name DMA_X_AID_7_4_MAP - DMA_X_AID_7_4_MAP */
/*! @{ */
#define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK (0xFFU)
#define CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT (0U)
#define CAAM_DMA_X_AID_7_4_MAP_AID4_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID4_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID4_BID_MASK)
#define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK (0xFF00U)
#define CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT (8U)
#define CAAM_DMA_X_AID_7_4_MAP_AID5_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID5_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID5_BID_MASK)
#define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK (0xFF0000U)
#define CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT (16U)
#define CAAM_DMA_X_AID_7_4_MAP_AID6_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID6_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID6_BID_MASK)
#define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK (0xFF000000U)
#define CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT (24U)
#define CAAM_DMA_X_AID_7_4_MAP_AID7_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_7_4_MAP_AID7_BID_SHIFT)) & CAAM_DMA_X_AID_7_4_MAP_AID7_BID_MASK)
/*! @} */
/*! @name DMA_X_AID_3_0_MAP - DMA_X_AID_3_0_MAP */
/*! @{ */
#define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK (0xFFU)
#define CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT (0U)
#define CAAM_DMA_X_AID_3_0_MAP_AID0_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID0_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID0_BID_MASK)
#define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK (0xFF00U)
#define CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT (8U)
#define CAAM_DMA_X_AID_3_0_MAP_AID1_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID1_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID1_BID_MASK)
#define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK (0xFF0000U)
#define CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT (16U)
#define CAAM_DMA_X_AID_3_0_MAP_AID2_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID2_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID2_BID_MASK)
#define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK (0xFF000000U)
#define CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT (24U)
#define CAAM_DMA_X_AID_3_0_MAP_AID3_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_3_0_MAP_AID3_BID_SHIFT)) & CAAM_DMA_X_AID_3_0_MAP_AID3_BID_MASK)
/*! @} */
/*! @name DMA_X_AID_15_12_MAP - DMA_X_AID_15_12_MAP */
/*! @{ */
#define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK (0xFFU)
#define CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT (0U)
#define CAAM_DMA_X_AID_15_12_MAP_AID12_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID12_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID12_BID_MASK)
#define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK (0xFF00U)
#define CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT (8U)
#define CAAM_DMA_X_AID_15_12_MAP_AID13_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID13_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID13_BID_MASK)
#define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK (0xFF0000U)
#define CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT (16U)
#define CAAM_DMA_X_AID_15_12_MAP_AID14_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID14_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID14_BID_MASK)
#define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK (0xFF000000U)
#define CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT (24U)
#define CAAM_DMA_X_AID_15_12_MAP_AID15_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_12_MAP_AID15_BID_SHIFT)) & CAAM_DMA_X_AID_15_12_MAP_AID15_BID_MASK)
/*! @} */
/*! @name DMA_X_AID_11_8_MAP - DMA_X_AID_11_8_MAP */
/*! @{ */
#define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK (0xFFU)
#define CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT (0U)
#define CAAM_DMA_X_AID_11_8_MAP_AID8_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID8_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID8_BID_MASK)
#define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK (0xFF00U)
#define CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT (8U)
#define CAAM_DMA_X_AID_11_8_MAP_AID9_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID9_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID9_BID_MASK)
#define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK (0xFF0000U)
#define CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT (16U)
#define CAAM_DMA_X_AID_11_8_MAP_AID10_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID10_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID10_BID_MASK)
#define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK (0xFF000000U)
#define CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT (24U)
#define CAAM_DMA_X_AID_11_8_MAP_AID11_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_11_8_MAP_AID11_BID_SHIFT)) & CAAM_DMA_X_AID_11_8_MAP_AID11_BID_MASK)
/*! @} */
/*! @name DMA_X_AID_15_0_EN - DMA_X AXI ID Map Enable Register */
/*! @{ */
#define CAAM_DMA_X_AID_15_0_EN_AID0E_MASK (0x1U)
#define CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT (0U)
#define CAAM_DMA_X_AID_15_0_EN_AID0E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID0E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID0E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID1E_MASK (0x2U)
#define CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT (1U)
#define CAAM_DMA_X_AID_15_0_EN_AID1E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID1E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID1E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID2E_MASK (0x4U)
#define CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT (2U)
#define CAAM_DMA_X_AID_15_0_EN_AID2E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID2E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID2E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID3E_MASK (0x8U)
#define CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT (3U)
#define CAAM_DMA_X_AID_15_0_EN_AID3E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID3E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID3E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID4E_MASK (0x10U)
#define CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT (4U)
#define CAAM_DMA_X_AID_15_0_EN_AID4E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID4E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID4E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID5E_MASK (0x20U)
#define CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT (5U)
#define CAAM_DMA_X_AID_15_0_EN_AID5E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID5E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID5E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID6E_MASK (0x40U)
#define CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT (6U)
#define CAAM_DMA_X_AID_15_0_EN_AID6E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID6E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID6E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID7E_MASK (0x80U)
#define CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT (7U)
#define CAAM_DMA_X_AID_15_0_EN_AID7E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID7E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID7E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID8E_MASK (0x100U)
#define CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT (8U)
#define CAAM_DMA_X_AID_15_0_EN_AID8E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID8E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID8E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID9E_MASK (0x200U)
#define CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT (9U)
#define CAAM_DMA_X_AID_15_0_EN_AID9E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID9E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID9E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID10E_MASK (0x400U)
#define CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT (10U)
#define CAAM_DMA_X_AID_15_0_EN_AID10E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID10E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID10E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID11E_MASK (0x800U)
#define CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT (11U)
#define CAAM_DMA_X_AID_15_0_EN_AID11E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID11E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID11E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID12E_MASK (0x1000U)
#define CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT (12U)
#define CAAM_DMA_X_AID_15_0_EN_AID12E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID12E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID12E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID13E_MASK (0x2000U)
#define CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT (13U)
#define CAAM_DMA_X_AID_15_0_EN_AID13E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID13E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID13E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID14E_MASK (0x4000U)
#define CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT (14U)
#define CAAM_DMA_X_AID_15_0_EN_AID14E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID14E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID14E_MASK)
#define CAAM_DMA_X_AID_15_0_EN_AID15E_MASK (0x8000U)
#define CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT (15U)
#define CAAM_DMA_X_AID_15_0_EN_AID15E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AID_15_0_EN_AID15E_SHIFT)) & CAAM_DMA_X_AID_15_0_EN_AID15E_MASK)
/*! @} */
/*! @name DMA_X_ARTC_CTL - DMA_X AXI Read Timing Check Control Register */
/*! @{ */
#define CAAM_DMA_X_ARTC_CTL_ART_MASK (0xFFFU)
#define CAAM_DMA_X_ARTC_CTL_ART_SHIFT (0U)
#define CAAM_DMA_X_ARTC_CTL_ART(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ART_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ART_MASK)
#define CAAM_DMA_X_ARTC_CTL_ARL_MASK (0xFFF0000U)
#define CAAM_DMA_X_ARTC_CTL_ARL_SHIFT (16U)
#define CAAM_DMA_X_ARTC_CTL_ARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARL_MASK)
#define CAAM_DMA_X_ARTC_CTL_ARTL_MASK (0x10000000U)
#define CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT (28U)
#define CAAM_DMA_X_ARTC_CTL_ARTL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTL_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTL_MASK)
#define CAAM_DMA_X_ARTC_CTL_ARTT_MASK (0x20000000U)
#define CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT (29U)
#define CAAM_DMA_X_ARTC_CTL_ARTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTT_MASK)
#define CAAM_DMA_X_ARTC_CTL_ARCT_MASK (0x40000000U)
#define CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT (30U)
#define CAAM_DMA_X_ARTC_CTL_ARCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARCT_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARCT_MASK)
#define CAAM_DMA_X_ARTC_CTL_ARTCE_MASK (0x80000000U)
#define CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT (31U)
#define CAAM_DMA_X_ARTC_CTL_ARTCE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_CTL_ARTCE_SHIFT)) & CAAM_DMA_X_ARTC_CTL_ARTCE_MASK)
/*! @} */
/*! @name DMA_X_ARTC_LC - DMA_X AXI Read Timing Check Late Count Register */
/*! @{ */
#define CAAM_DMA_X_ARTC_LC_ARLC_MASK (0xFFFFFU)
#define CAAM_DMA_X_ARTC_LC_ARLC_SHIFT (0U)
#define CAAM_DMA_X_ARTC_LC_ARLC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LC_ARLC_SHIFT)) & CAAM_DMA_X_ARTC_LC_ARLC_MASK)
/*! @} */
/*! @name DMA_X_ARTC_SC - DMA_X AXI Read Timing Check Sample Count Register */
/*! @{ */
#define CAAM_DMA_X_ARTC_SC_ARSC_MASK (0xFFFFFU)
#define CAAM_DMA_X_ARTC_SC_ARSC_SHIFT (0U)
#define CAAM_DMA_X_ARTC_SC_ARSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_SC_ARSC_SHIFT)) & CAAM_DMA_X_ARTC_SC_ARSC_MASK)
/*! @} */
/*! @name DMA_X_ARTC_LAT - DMA_X Read Timing Check Latency Register */
/*! @{ */
#define CAAM_DMA_X_ARTC_LAT_SARL_MASK (0xFFFFFFFFU)
#define CAAM_DMA_X_ARTC_LAT_SARL_SHIFT (0U)
#define CAAM_DMA_X_ARTC_LAT_SARL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_ARTC_LAT_SARL_SHIFT)) & CAAM_DMA_X_ARTC_LAT_SARL_MASK)
/*! @} */
/*! @name DMA_X_AWTC_CTL - DMA_X AXI Write Timing Check Control Register */
/*! @{ */
#define CAAM_DMA_X_AWTC_CTL_AWT_MASK (0xFFFU)
#define CAAM_DMA_X_AWTC_CTL_AWT_SHIFT (0U)
#define CAAM_DMA_X_AWTC_CTL_AWT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWT_MASK)
#define CAAM_DMA_X_AWTC_CTL_AWL_MASK (0xFFF0000U)
#define CAAM_DMA_X_AWTC_CTL_AWL_SHIFT (16U)
#define CAAM_DMA_X_AWTC_CTL_AWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWL_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWL_MASK)
#define CAAM_DMA_X_AWTC_CTL_AWTT_MASK (0x20000000U)
#define CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT (29U)
#define CAAM_DMA_X_AWTC_CTL_AWTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTT_MASK)
#define CAAM_DMA_X_AWTC_CTL_AWCT_MASK (0x40000000U)
#define CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT (30U)
#define CAAM_DMA_X_AWTC_CTL_AWCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWCT_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWCT_MASK)
#define CAAM_DMA_X_AWTC_CTL_AWTCE_MASK (0x80000000U)
#define CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT (31U)
#define CAAM_DMA_X_AWTC_CTL_AWTCE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_CTL_AWTCE_SHIFT)) & CAAM_DMA_X_AWTC_CTL_AWTCE_MASK)
/*! @} */
/*! @name DMA_X_AWTC_LC - DMA_X AXI Write Timing Check Late Count Register */
/*! @{ */
#define CAAM_DMA_X_AWTC_LC_AWLC_MASK (0xFFFFFU)
#define CAAM_DMA_X_AWTC_LC_AWLC_SHIFT (0U)
#define CAAM_DMA_X_AWTC_LC_AWLC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LC_AWLC_SHIFT)) & CAAM_DMA_X_AWTC_LC_AWLC_MASK)
/*! @} */
/*! @name DMA_X_AWTC_SC - DMA_X AXI Write Timing Check Sample Count Register */
/*! @{ */
#define CAAM_DMA_X_AWTC_SC_AWSC_MASK (0xFFFFFU)
#define CAAM_DMA_X_AWTC_SC_AWSC_SHIFT (0U)
#define CAAM_DMA_X_AWTC_SC_AWSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_SC_AWSC_SHIFT)) & CAAM_DMA_X_AWTC_SC_AWSC_MASK)
/*! @} */
/*! @name DMA_X_AWTC_LAT - DMA_X Write Timing Check Latency Register */
/*! @{ */
#define CAAM_DMA_X_AWTC_LAT_SAWL_MASK (0xFFFFFFFFU)
#define CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT (0U)
#define CAAM_DMA_X_AWTC_LAT_SAWL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMA_X_AWTC_LAT_SAWL_SHIFT)) & CAAM_DMA_X_AWTC_LAT_SAWL_MASK)
/*! @} */
/*! @name RTMCTL - RNG TRNG Miscellaneous Control Register */
/*! @{ */
#define CAAM_RTMCTL_SAMP_MODE_MASK (0x3U)
#define CAAM_RTMCTL_SAMP_MODE_SHIFT (0U)
/*! SAMP_MODE
* 0b00..use Von Neumann data into both Entropy shifter and Statistical Checker
* 0b01..use raw data into both Entropy shifter and Statistical Checker
* 0b10..use Von Neumann data into Entropy shifter. Use raw data into Statistical Checker
* 0b11..undefined/reserved.
*/
#define CAAM_RTMCTL_SAMP_MODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_SAMP_MODE_SHIFT)) & CAAM_RTMCTL_SAMP_MODE_MASK)
#define CAAM_RTMCTL_OSC_DIV_MASK (0xCU)
#define CAAM_RTMCTL_OSC_DIV_SHIFT (2U)
/*! OSC_DIV
* 0b00..use ring oscillator with no divide
* 0b01..use ring oscillator divided-by-2
* 0b10..use ring oscillator divided-by-4
* 0b11..use ring oscillator divided-by-8
*/
#define CAAM_RTMCTL_OSC_DIV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_OSC_DIV_SHIFT)) & CAAM_RTMCTL_OSC_DIV_MASK)
#define CAAM_RTMCTL_CLK_OUT_EN_MASK (0x10U)
#define CAAM_RTMCTL_CLK_OUT_EN_SHIFT (4U)
#define CAAM_RTMCTL_CLK_OUT_EN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_CLK_OUT_EN_SHIFT)) & CAAM_RTMCTL_CLK_OUT_EN_MASK)
#define CAAM_RTMCTL_TRNG_ACC_MASK (0x20U)
#define CAAM_RTMCTL_TRNG_ACC_SHIFT (5U)
#define CAAM_RTMCTL_TRNG_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TRNG_ACC_SHIFT)) & CAAM_RTMCTL_TRNG_ACC_MASK)
#define CAAM_RTMCTL_RST_DEF_MASK (0x40U)
#define CAAM_RTMCTL_RST_DEF_SHIFT (6U)
#define CAAM_RTMCTL_RST_DEF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_RST_DEF_SHIFT)) & CAAM_RTMCTL_RST_DEF_MASK)
#define CAAM_RTMCTL_FORCE_SYSCLK_MASK (0x80U)
#define CAAM_RTMCTL_FORCE_SYSCLK_SHIFT (7U)
#define CAAM_RTMCTL_FORCE_SYSCLK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FORCE_SYSCLK_SHIFT)) & CAAM_RTMCTL_FORCE_SYSCLK_MASK)
#define CAAM_RTMCTL_FCT_FAIL_MASK (0x100U)
#define CAAM_RTMCTL_FCT_FAIL_SHIFT (8U)
#define CAAM_RTMCTL_FCT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_FAIL_SHIFT)) & CAAM_RTMCTL_FCT_FAIL_MASK)
#define CAAM_RTMCTL_FCT_VAL_MASK (0x200U)
#define CAAM_RTMCTL_FCT_VAL_SHIFT (9U)
#define CAAM_RTMCTL_FCT_VAL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_FCT_VAL_SHIFT)) & CAAM_RTMCTL_FCT_VAL_MASK)
#define CAAM_RTMCTL_ENT_VAL_MASK (0x400U)
#define CAAM_RTMCTL_ENT_VAL_SHIFT (10U)
#define CAAM_RTMCTL_ENT_VAL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ENT_VAL_SHIFT)) & CAAM_RTMCTL_ENT_VAL_MASK)
#define CAAM_RTMCTL_TST_OUT_MASK (0x800U)
#define CAAM_RTMCTL_TST_OUT_SHIFT (11U)
#define CAAM_RTMCTL_TST_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TST_OUT_SHIFT)) & CAAM_RTMCTL_TST_OUT_MASK)
#define CAAM_RTMCTL_ERR_MASK (0x1000U)
#define CAAM_RTMCTL_ERR_SHIFT (12U)
#define CAAM_RTMCTL_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_ERR_SHIFT)) & CAAM_RTMCTL_ERR_MASK)
#define CAAM_RTMCTL_TSTOP_OK_MASK (0x2000U)
#define CAAM_RTMCTL_TSTOP_OK_SHIFT (13U)
#define CAAM_RTMCTL_TSTOP_OK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_TSTOP_OK_SHIFT)) & CAAM_RTMCTL_TSTOP_OK_MASK)
#define CAAM_RTMCTL_PRGM_MASK (0x10000U)
#define CAAM_RTMCTL_PRGM_SHIFT (16U)
#define CAAM_RTMCTL_PRGM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTMCTL_PRGM_SHIFT)) & CAAM_RTMCTL_PRGM_MASK)
/*! @} */
/*! @name RTSCMISC - RNG TRNG Statistical Check Miscellaneous Register */
/*! @{ */
#define CAAM_RTSCMISC_LRUN_MAX_MASK (0xFFU)
#define CAAM_RTSCMISC_LRUN_MAX_SHIFT (0U)
#define CAAM_RTSCMISC_LRUN_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_LRUN_MAX_SHIFT)) & CAAM_RTSCMISC_LRUN_MAX_MASK)
#define CAAM_RTSCMISC_RTY_CNT_MASK (0xF0000U)
#define CAAM_RTSCMISC_RTY_CNT_SHIFT (16U)
#define CAAM_RTSCMISC_RTY_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMISC_RTY_CNT_SHIFT)) & CAAM_RTSCMISC_RTY_CNT_MASK)
/*! @} */
/*! @name RTPKRRNG - RNG TRNG Poker Range Register */
/*! @{ */
#define CAAM_RTPKRRNG_PKR_RNG_MASK (0xFFFFU)
#define CAAM_RTPKRRNG_PKR_RNG_SHIFT (0U)
#define CAAM_RTPKRRNG_PKR_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRRNG_PKR_RNG_SHIFT)) & CAAM_RTPKRRNG_PKR_RNG_MASK)
/*! @} */
/*! @name RTPKRMAX - RNG TRNG Poker Maximum Limit Register */
/*! @{ */
#define CAAM_RTPKRMAX_PKR_MAX_MASK (0xFFFFFFU)
#define CAAM_RTPKRMAX_PKR_MAX_SHIFT (0U)
#define CAAM_RTPKRMAX_PKR_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRMAX_PKR_MAX_SHIFT)) & CAAM_RTPKRMAX_PKR_MAX_MASK)
/*! @} */
/*! @name RTPKRSQ - RNG TRNG Poker Square Calculation Result Register */
/*! @{ */
#define CAAM_RTPKRSQ_PKR_SQ_MASK (0xFFFFFFU)
#define CAAM_RTPKRSQ_PKR_SQ_SHIFT (0U)
#define CAAM_RTPKRSQ_PKR_SQ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRSQ_PKR_SQ_SHIFT)) & CAAM_RTPKRSQ_PKR_SQ_MASK)
/*! @} */
/*! @name RTSDCTL - RNG TRNG Seed Control Register */
/*! @{ */
#define CAAM_RTSDCTL_SAMP_SIZE_MASK (0xFFFFU)
#define CAAM_RTSDCTL_SAMP_SIZE_SHIFT (0U)
#define CAAM_RTSDCTL_SAMP_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_SAMP_SIZE_SHIFT)) & CAAM_RTSDCTL_SAMP_SIZE_MASK)
#define CAAM_RTSDCTL_ENT_DLY_MASK (0xFFFF0000U)
#define CAAM_RTSDCTL_ENT_DLY_SHIFT (16U)
#define CAAM_RTSDCTL_ENT_DLY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSDCTL_ENT_DLY_SHIFT)) & CAAM_RTSDCTL_ENT_DLY_MASK)
/*! @} */
/*! @name RTSBLIM - RNG TRNG Sparse Bit Limit Register */
/*! @{ */
#define CAAM_RTSBLIM_SB_LIM_MASK (0x3FFU)
#define CAAM_RTSBLIM_SB_LIM_SHIFT (0U)
#define CAAM_RTSBLIM_SB_LIM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSBLIM_SB_LIM_SHIFT)) & CAAM_RTSBLIM_SB_LIM_MASK)
/*! @} */
/*! @name RTTOTSAM - RNG TRNG Total Samples Register */
/*! @{ */
#define CAAM_RTTOTSAM_TOT_SAM_MASK (0xFFFFFU)
#define CAAM_RTTOTSAM_TOT_SAM_SHIFT (0U)
#define CAAM_RTTOTSAM_TOT_SAM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTTOTSAM_TOT_SAM_SHIFT)) & CAAM_RTTOTSAM_TOT_SAM_MASK)
/*! @} */
/*! @name RTFRQMIN - RNG TRNG Frequency Count Minimum Limit Register */
/*! @{ */
#define CAAM_RTFRQMIN_FRQ_MIN_MASK (0x3FFFFFU)
#define CAAM_RTFRQMIN_FRQ_MIN_SHIFT (0U)
#define CAAM_RTFRQMIN_FRQ_MIN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMIN_FRQ_MIN_SHIFT)) & CAAM_RTFRQMIN_FRQ_MIN_MASK)
/*! @} */
/*! @name RTFRQCNT - RNG TRNG Frequency Count Register */
/*! @{ */
#define CAAM_RTFRQCNT_FRQ_CNT_MASK (0x3FFFFFU)
#define CAAM_RTFRQCNT_FRQ_CNT_SHIFT (0U)
#define CAAM_RTFRQCNT_FRQ_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQCNT_FRQ_CNT_SHIFT)) & CAAM_RTFRQCNT_FRQ_CNT_MASK)
/*! @} */
/*! @name RTSCMC - RNG TRNG Statistical Check Monobit Count Register */
/*! @{ */
#define CAAM_RTSCMC_MONO_CNT_MASK (0xFFFFU)
#define CAAM_RTSCMC_MONO_CNT_SHIFT (0U)
#define CAAM_RTSCMC_MONO_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCMC_MONO_CNT_SHIFT)) & CAAM_RTSCMC_MONO_CNT_MASK)
/*! @} */
/*! @name RTSCR1C - RNG TRNG Statistical Check Run Length 1 Count Register */
/*! @{ */
#define CAAM_RTSCR1C_R1_0_COUNT_MASK (0x7FFFU)
#define CAAM_RTSCR1C_R1_0_COUNT_SHIFT (0U)
#define CAAM_RTSCR1C_R1_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_0_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_0_COUNT_MASK)
#define CAAM_RTSCR1C_R1_1_COUNT_MASK (0x7FFF0000U)
#define CAAM_RTSCR1C_R1_1_COUNT_SHIFT (16U)
#define CAAM_RTSCR1C_R1_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1C_R1_1_COUNT_SHIFT)) & CAAM_RTSCR1C_R1_1_COUNT_MASK)
/*! @} */
/*! @name RTSCR2C - RNG TRNG Statistical Check Run Length 2 Count Register */
/*! @{ */
#define CAAM_RTSCR2C_R2_0_COUNT_MASK (0x3FFFU)
#define CAAM_RTSCR2C_R2_0_COUNT_SHIFT (0U)
#define CAAM_RTSCR2C_R2_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_0_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_0_COUNT_MASK)
#define CAAM_RTSCR2C_R2_1_COUNT_MASK (0x3FFF0000U)
#define CAAM_RTSCR2C_R2_1_COUNT_SHIFT (16U)
#define CAAM_RTSCR2C_R2_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2C_R2_1_COUNT_SHIFT)) & CAAM_RTSCR2C_R2_1_COUNT_MASK)
/*! @} */
/*! @name RTSCR3C - RNG TRNG Statistical Check Run Length 3 Count Register */
/*! @{ */
#define CAAM_RTSCR3C_R3_0_COUNT_MASK (0x1FFFU)
#define CAAM_RTSCR3C_R3_0_COUNT_SHIFT (0U)
#define CAAM_RTSCR3C_R3_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_0_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_0_COUNT_MASK)
#define CAAM_RTSCR3C_R3_1_COUNT_MASK (0x1FFF0000U)
#define CAAM_RTSCR3C_R3_1_COUNT_SHIFT (16U)
#define CAAM_RTSCR3C_R3_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3C_R3_1_COUNT_SHIFT)) & CAAM_RTSCR3C_R3_1_COUNT_MASK)
/*! @} */
/*! @name RTSCR4C - RNG TRNG Statistical Check Run Length 4 Count Register */
/*! @{ */
#define CAAM_RTSCR4C_R4_0_COUNT_MASK (0xFFFU)
#define CAAM_RTSCR4C_R4_0_COUNT_SHIFT (0U)
#define CAAM_RTSCR4C_R4_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_0_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_0_COUNT_MASK)
#define CAAM_RTSCR4C_R4_1_COUNT_MASK (0xFFF0000U)
#define CAAM_RTSCR4C_R4_1_COUNT_SHIFT (16U)
#define CAAM_RTSCR4C_R4_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4C_R4_1_COUNT_SHIFT)) & CAAM_RTSCR4C_R4_1_COUNT_MASK)
/*! @} */
/*! @name RTSCR5C - RNG TRNG Statistical Check Run Length 5 Count Register */
/*! @{ */
#define CAAM_RTSCR5C_R5_0_COUNT_MASK (0x7FFU)
#define CAAM_RTSCR5C_R5_0_COUNT_SHIFT (0U)
#define CAAM_RTSCR5C_R5_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_0_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_0_COUNT_MASK)
#define CAAM_RTSCR5C_R5_1_COUNT_MASK (0x7FF0000U)
#define CAAM_RTSCR5C_R5_1_COUNT_SHIFT (16U)
#define CAAM_RTSCR5C_R5_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5C_R5_1_COUNT_SHIFT)) & CAAM_RTSCR5C_R5_1_COUNT_MASK)
/*! @} */
/*! @name RTSCR6PC - RNG TRNG Statistical Check Run Length 6+ Count Register */
/*! @{ */
#define CAAM_RTSCR6PC_R6P_0_COUNT_MASK (0x7FFU)
#define CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT (0U)
#define CAAM_RTSCR6PC_R6P_0_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_0_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_0_COUNT_MASK)
#define CAAM_RTSCR6PC_R6P_1_COUNT_MASK (0x7FF0000U)
#define CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT (16U)
#define CAAM_RTSCR6PC_R6P_1_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PC_R6P_1_COUNT_SHIFT)) & CAAM_RTSCR6PC_R6P_1_COUNT_MASK)
/*! @} */
/*! @name RTFRQMAX - RNG TRNG Frequency Count Maximum Limit Register */
/*! @{ */
#define CAAM_RTFRQMAX_FRQ_MAX_MASK (0x3FFFFFU)
#define CAAM_RTFRQMAX_FRQ_MAX_SHIFT (0U)
#define CAAM_RTFRQMAX_FRQ_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTFRQMAX_FRQ_MAX_SHIFT)) & CAAM_RTFRQMAX_FRQ_MAX_MASK)
/*! @} */
/*! @name RTSCML - RNG TRNG Statistical Check Monobit Limit Register */
/*! @{ */
#define CAAM_RTSCML_MONO_MAX_MASK (0xFFFFU)
#define CAAM_RTSCML_MONO_MAX_SHIFT (0U)
#define CAAM_RTSCML_MONO_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_MAX_SHIFT)) & CAAM_RTSCML_MONO_MAX_MASK)
#define CAAM_RTSCML_MONO_RNG_MASK (0xFFFF0000U)
#define CAAM_RTSCML_MONO_RNG_SHIFT (16U)
#define CAAM_RTSCML_MONO_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCML_MONO_RNG_SHIFT)) & CAAM_RTSCML_MONO_RNG_MASK)
/*! @} */
/*! @name RTSCR1L - RNG TRNG Statistical Check Run Length 1 Limit Register */
/*! @{ */
#define CAAM_RTSCR1L_RUN1_MAX_MASK (0x7FFFU)
#define CAAM_RTSCR1L_RUN1_MAX_SHIFT (0U)
#define CAAM_RTSCR1L_RUN1_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_MAX_SHIFT)) & CAAM_RTSCR1L_RUN1_MAX_MASK)
#define CAAM_RTSCR1L_RUN1_RNG_MASK (0x7FFF0000U)
#define CAAM_RTSCR1L_RUN1_RNG_SHIFT (16U)
#define CAAM_RTSCR1L_RUN1_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR1L_RUN1_RNG_SHIFT)) & CAAM_RTSCR1L_RUN1_RNG_MASK)
/*! @} */
/*! @name RTSCR2L - RNG TRNG Statistical Check Run Length 2 Limit Register */
/*! @{ */
#define CAAM_RTSCR2L_RUN2_MAX_MASK (0x3FFFU)
#define CAAM_RTSCR2L_RUN2_MAX_SHIFT (0U)
#define CAAM_RTSCR2L_RUN2_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_MAX_SHIFT)) & CAAM_RTSCR2L_RUN2_MAX_MASK)
#define CAAM_RTSCR2L_RUN2_RNG_MASK (0x3FFF0000U)
#define CAAM_RTSCR2L_RUN2_RNG_SHIFT (16U)
#define CAAM_RTSCR2L_RUN2_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR2L_RUN2_RNG_SHIFT)) & CAAM_RTSCR2L_RUN2_RNG_MASK)
/*! @} */
/*! @name RTSCR3L - RNG TRNG Statistical Check Run Length 3 Limit Register */
/*! @{ */
#define CAAM_RTSCR3L_RUN3_MAX_MASK (0x1FFFU)
#define CAAM_RTSCR3L_RUN3_MAX_SHIFT (0U)
#define CAAM_RTSCR3L_RUN3_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_MAX_SHIFT)) & CAAM_RTSCR3L_RUN3_MAX_MASK)
#define CAAM_RTSCR3L_RUN3_RNG_MASK (0x1FFF0000U)
#define CAAM_RTSCR3L_RUN3_RNG_SHIFT (16U)
#define CAAM_RTSCR3L_RUN3_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR3L_RUN3_RNG_SHIFT)) & CAAM_RTSCR3L_RUN3_RNG_MASK)
/*! @} */
/*! @name RTSCR4L - RNG TRNG Statistical Check Run Length 4 Limit Register */
/*! @{ */
#define CAAM_RTSCR4L_RUN4_MAX_MASK (0xFFFU)
#define CAAM_RTSCR4L_RUN4_MAX_SHIFT (0U)
#define CAAM_RTSCR4L_RUN4_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_MAX_SHIFT)) & CAAM_RTSCR4L_RUN4_MAX_MASK)
#define CAAM_RTSCR4L_RUN4_RNG_MASK (0xFFF0000U)
#define CAAM_RTSCR4L_RUN4_RNG_SHIFT (16U)
#define CAAM_RTSCR4L_RUN4_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR4L_RUN4_RNG_SHIFT)) & CAAM_RTSCR4L_RUN4_RNG_MASK)
/*! @} */
/*! @name RTSCR5L - RNG TRNG Statistical Check Run Length 5 Limit Register */
/*! @{ */
#define CAAM_RTSCR5L_RUN5_MAX_MASK (0x7FFU)
#define CAAM_RTSCR5L_RUN5_MAX_SHIFT (0U)
#define CAAM_RTSCR5L_RUN5_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_MAX_SHIFT)) & CAAM_RTSCR5L_RUN5_MAX_MASK)
#define CAAM_RTSCR5L_RUN5_RNG_MASK (0x7FF0000U)
#define CAAM_RTSCR5L_RUN5_RNG_SHIFT (16U)
#define CAAM_RTSCR5L_RUN5_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR5L_RUN5_RNG_SHIFT)) & CAAM_RTSCR5L_RUN5_RNG_MASK)
/*! @} */
/*! @name RTSCR6PL - RNG TRNG Statistical Check Run Length 6+ Limit Register */
/*! @{ */
#define CAAM_RTSCR6PL_RUN6P_MAX_MASK (0x7FFU)
#define CAAM_RTSCR6PL_RUN6P_MAX_SHIFT (0U)
#define CAAM_RTSCR6PL_RUN6P_MAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_MAX_SHIFT)) & CAAM_RTSCR6PL_RUN6P_MAX_MASK)
#define CAAM_RTSCR6PL_RUN6P_RNG_MASK (0x7FF0000U)
#define CAAM_RTSCR6PL_RUN6P_RNG_SHIFT (16U)
#define CAAM_RTSCR6PL_RUN6P_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSCR6PL_RUN6P_RNG_SHIFT)) & CAAM_RTSCR6PL_RUN6P_RNG_MASK)
/*! @} */
/*! @name RTSTATUS - RNG TRNG Status Register */
/*! @{ */
#define CAAM_RTSTATUS_F1BR0TF_MASK (0x1U)
#define CAAM_RTSTATUS_F1BR0TF_SHIFT (0U)
#define CAAM_RTSTATUS_F1BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR0TF_SHIFT)) & CAAM_RTSTATUS_F1BR0TF_MASK)
#define CAAM_RTSTATUS_F1BR1TF_MASK (0x2U)
#define CAAM_RTSTATUS_F1BR1TF_SHIFT (1U)
#define CAAM_RTSTATUS_F1BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F1BR1TF_SHIFT)) & CAAM_RTSTATUS_F1BR1TF_MASK)
#define CAAM_RTSTATUS_F2BR0TF_MASK (0x4U)
#define CAAM_RTSTATUS_F2BR0TF_SHIFT (2U)
#define CAAM_RTSTATUS_F2BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR0TF_SHIFT)) & CAAM_RTSTATUS_F2BR0TF_MASK)
#define CAAM_RTSTATUS_F2BR1TF_MASK (0x8U)
#define CAAM_RTSTATUS_F2BR1TF_SHIFT (3U)
#define CAAM_RTSTATUS_F2BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F2BR1TF_SHIFT)) & CAAM_RTSTATUS_F2BR1TF_MASK)
#define CAAM_RTSTATUS_F3BR01TF_MASK (0x10U)
#define CAAM_RTSTATUS_F3BR01TF_SHIFT (4U)
#define CAAM_RTSTATUS_F3BR01TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR01TF_SHIFT)) & CAAM_RTSTATUS_F3BR01TF_MASK)
#define CAAM_RTSTATUS_F3BR1TF_MASK (0x20U)
#define CAAM_RTSTATUS_F3BR1TF_SHIFT (5U)
#define CAAM_RTSTATUS_F3BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F3BR1TF_SHIFT)) & CAAM_RTSTATUS_F3BR1TF_MASK)
#define CAAM_RTSTATUS_F4BR0TF_MASK (0x40U)
#define CAAM_RTSTATUS_F4BR0TF_SHIFT (6U)
#define CAAM_RTSTATUS_F4BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR0TF_SHIFT)) & CAAM_RTSTATUS_F4BR0TF_MASK)
#define CAAM_RTSTATUS_F4BR1TF_MASK (0x80U)
#define CAAM_RTSTATUS_F4BR1TF_SHIFT (7U)
#define CAAM_RTSTATUS_F4BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F4BR1TF_SHIFT)) & CAAM_RTSTATUS_F4BR1TF_MASK)
#define CAAM_RTSTATUS_F5BR0TF_MASK (0x100U)
#define CAAM_RTSTATUS_F5BR0TF_SHIFT (8U)
#define CAAM_RTSTATUS_F5BR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR0TF_SHIFT)) & CAAM_RTSTATUS_F5BR0TF_MASK)
#define CAAM_RTSTATUS_F5BR1TF_MASK (0x200U)
#define CAAM_RTSTATUS_F5BR1TF_SHIFT (9U)
#define CAAM_RTSTATUS_F5BR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F5BR1TF_SHIFT)) & CAAM_RTSTATUS_F5BR1TF_MASK)
#define CAAM_RTSTATUS_F6PBR0TF_MASK (0x400U)
#define CAAM_RTSTATUS_F6PBR0TF_SHIFT (10U)
#define CAAM_RTSTATUS_F6PBR0TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR0TF_SHIFT)) & CAAM_RTSTATUS_F6PBR0TF_MASK)
#define CAAM_RTSTATUS_F6PBR1TF_MASK (0x800U)
#define CAAM_RTSTATUS_F6PBR1TF_SHIFT (11U)
#define CAAM_RTSTATUS_F6PBR1TF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_F6PBR1TF_SHIFT)) & CAAM_RTSTATUS_F6PBR1TF_MASK)
#define CAAM_RTSTATUS_FSBTF_MASK (0x1000U)
#define CAAM_RTSTATUS_FSBTF_SHIFT (12U)
#define CAAM_RTSTATUS_FSBTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FSBTF_SHIFT)) & CAAM_RTSTATUS_FSBTF_MASK)
#define CAAM_RTSTATUS_FLRTF_MASK (0x2000U)
#define CAAM_RTSTATUS_FLRTF_SHIFT (13U)
#define CAAM_RTSTATUS_FLRTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FLRTF_SHIFT)) & CAAM_RTSTATUS_FLRTF_MASK)
#define CAAM_RTSTATUS_FPTF_MASK (0x4000U)
#define CAAM_RTSTATUS_FPTF_SHIFT (14U)
#define CAAM_RTSTATUS_FPTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FPTF_SHIFT)) & CAAM_RTSTATUS_FPTF_MASK)
#define CAAM_RTSTATUS_FMBTF_MASK (0x8000U)
#define CAAM_RTSTATUS_FMBTF_SHIFT (15U)
#define CAAM_RTSTATUS_FMBTF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_FMBTF_SHIFT)) & CAAM_RTSTATUS_FMBTF_MASK)
#define CAAM_RTSTATUS_RETRY_COUNT_MASK (0xF0000U)
#define CAAM_RTSTATUS_RETRY_COUNT_SHIFT (16U)
#define CAAM_RTSTATUS_RETRY_COUNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTSTATUS_RETRY_COUNT_SHIFT)) & CAAM_RTSTATUS_RETRY_COUNT_MASK)
/*! @} */
/*! @name RTENT - RNG TRNG Entropy Read Register */
/*! @{ */
#define CAAM_RTENT_ENT_MASK (0xFFFFFFFFU)
#define CAAM_RTENT_ENT_SHIFT (0U)
#define CAAM_RTENT_ENT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTENT_ENT_SHIFT)) & CAAM_RTENT_ENT_MASK)
/*! @} */
/* The count of CAAM_RTENT */
#define CAAM_RTENT_COUNT (16U)
/*! @name RTPKRCNT10 - RNG TRNG Statistical Check Poker Count 1 and 0 Register */
/*! @{ */
#define CAAM_RTPKRCNT10_PKR_0_CNT_MASK (0xFFFFU)
#define CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT (0U)
#define CAAM_RTPKRCNT10_PKR_0_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_0_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_0_CNT_MASK)
#define CAAM_RTPKRCNT10_PKR_1_CNT_MASK (0xFFFF0000U)
#define CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT (16U)
#define CAAM_RTPKRCNT10_PKR_1_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT10_PKR_1_CNT_SHIFT)) & CAAM_RTPKRCNT10_PKR_1_CNT_MASK)
/*! @} */
/*! @name RTPKRCNT32 - RNG TRNG Statistical Check Poker Count 3 and 2 Register */
/*! @{ */
#define CAAM_RTPKRCNT32_PKR_2_CNT_MASK (0xFFFFU)
#define CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT (0U)
#define CAAM_RTPKRCNT32_PKR_2_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_2_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_2_CNT_MASK)
#define CAAM_RTPKRCNT32_PKR_3_CNT_MASK (0xFFFF0000U)
#define CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT (16U)
#define CAAM_RTPKRCNT32_PKR_3_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT32_PKR_3_CNT_SHIFT)) & CAAM_RTPKRCNT32_PKR_3_CNT_MASK)
/*! @} */
/*! @name RTPKRCNT54 - RNG TRNG Statistical Check Poker Count 5 and 4 Register */
/*! @{ */
#define CAAM_RTPKRCNT54_PKR_4_CNT_MASK (0xFFFFU)
#define CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT (0U)
#define CAAM_RTPKRCNT54_PKR_4_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_4_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_4_CNT_MASK)
#define CAAM_RTPKRCNT54_PKR_5_CNT_MASK (0xFFFF0000U)
#define CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT (16U)
#define CAAM_RTPKRCNT54_PKR_5_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT54_PKR_5_CNT_SHIFT)) & CAAM_RTPKRCNT54_PKR_5_CNT_MASK)
/*! @} */
/*! @name RTPKRCNT76 - RNG TRNG Statistical Check Poker Count 7 and 6 Register */
/*! @{ */
#define CAAM_RTPKRCNT76_PKR_6_CNT_MASK (0xFFFFU)
#define CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT (0U)
#define CAAM_RTPKRCNT76_PKR_6_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_6_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_6_CNT_MASK)
#define CAAM_RTPKRCNT76_PKR_7_CNT_MASK (0xFFFF0000U)
#define CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT (16U)
#define CAAM_RTPKRCNT76_PKR_7_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT76_PKR_7_CNT_SHIFT)) & CAAM_RTPKRCNT76_PKR_7_CNT_MASK)
/*! @} */
/*! @name RTPKRCNT98 - RNG TRNG Statistical Check Poker Count 9 and 8 Register */
/*! @{ */
#define CAAM_RTPKRCNT98_PKR_8_CNT_MASK (0xFFFFU)
#define CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT (0U)
#define CAAM_RTPKRCNT98_PKR_8_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_8_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_8_CNT_MASK)
#define CAAM_RTPKRCNT98_PKR_9_CNT_MASK (0xFFFF0000U)
#define CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT (16U)
#define CAAM_RTPKRCNT98_PKR_9_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNT98_PKR_9_CNT_SHIFT)) & CAAM_RTPKRCNT98_PKR_9_CNT_MASK)
/*! @} */
/*! @name RTPKRCNTBA - RNG TRNG Statistical Check Poker Count B and A Register */
/*! @{ */
#define CAAM_RTPKRCNTBA_PKR_A_CNT_MASK (0xFFFFU)
#define CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT (0U)
#define CAAM_RTPKRCNTBA_PKR_A_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_A_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_A_CNT_MASK)
#define CAAM_RTPKRCNTBA_PKR_B_CNT_MASK (0xFFFF0000U)
#define CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT (16U)
#define CAAM_RTPKRCNTBA_PKR_B_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTBA_PKR_B_CNT_SHIFT)) & CAAM_RTPKRCNTBA_PKR_B_CNT_MASK)
/*! @} */
/*! @name RTPKRCNTDC - RNG TRNG Statistical Check Poker Count D and C Register */
/*! @{ */
#define CAAM_RTPKRCNTDC_PKR_C_CNT_MASK (0xFFFFU)
#define CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT (0U)
#define CAAM_RTPKRCNTDC_PKR_C_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_C_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_C_CNT_MASK)
#define CAAM_RTPKRCNTDC_PKR_D_CNT_MASK (0xFFFF0000U)
#define CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT (16U)
#define CAAM_RTPKRCNTDC_PKR_D_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTDC_PKR_D_CNT_SHIFT)) & CAAM_RTPKRCNTDC_PKR_D_CNT_MASK)
/*! @} */
/*! @name RTPKRCNTFE - RNG TRNG Statistical Check Poker Count F and E Register */
/*! @{ */
#define CAAM_RTPKRCNTFE_PKR_E_CNT_MASK (0xFFFFU)
#define CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT (0U)
#define CAAM_RTPKRCNTFE_PKR_E_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_E_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_E_CNT_MASK)
#define CAAM_RTPKRCNTFE_PKR_F_CNT_MASK (0xFFFF0000U)
#define CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT (16U)
#define CAAM_RTPKRCNTFE_PKR_F_CNT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTPKRCNTFE_PKR_F_CNT_SHIFT)) & CAAM_RTPKRCNTFE_PKR_F_CNT_MASK)
/*! @} */
/*! @name RDSTA - RNG DRNG Status Register */
/*! @{ */
#define CAAM_RDSTA_IF0_MASK (0x1U)
#define CAAM_RDSTA_IF0_SHIFT (0U)
#define CAAM_RDSTA_IF0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF0_SHIFT)) & CAAM_RDSTA_IF0_MASK)
#define CAAM_RDSTA_IF1_MASK (0x2U)
#define CAAM_RDSTA_IF1_SHIFT (1U)
#define CAAM_RDSTA_IF1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_IF1_SHIFT)) & CAAM_RDSTA_IF1_MASK)
#define CAAM_RDSTA_PR0_MASK (0x10U)
#define CAAM_RDSTA_PR0_SHIFT (4U)
#define CAAM_RDSTA_PR0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR0_SHIFT)) & CAAM_RDSTA_PR0_MASK)
#define CAAM_RDSTA_PR1_MASK (0x20U)
#define CAAM_RDSTA_PR1_SHIFT (5U)
#define CAAM_RDSTA_PR1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_PR1_SHIFT)) & CAAM_RDSTA_PR1_MASK)
#define CAAM_RDSTA_TF0_MASK (0x100U)
#define CAAM_RDSTA_TF0_SHIFT (8U)
#define CAAM_RDSTA_TF0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF0_SHIFT)) & CAAM_RDSTA_TF0_MASK)
#define CAAM_RDSTA_TF1_MASK (0x200U)
#define CAAM_RDSTA_TF1_SHIFT (9U)
#define CAAM_RDSTA_TF1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_TF1_SHIFT)) & CAAM_RDSTA_TF1_MASK)
#define CAAM_RDSTA_ERRCODE_MASK (0xF0000U)
#define CAAM_RDSTA_ERRCODE_SHIFT (16U)
#define CAAM_RDSTA_ERRCODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_ERRCODE_SHIFT)) & CAAM_RDSTA_ERRCODE_MASK)
#define CAAM_RDSTA_CE_MASK (0x100000U)
#define CAAM_RDSTA_CE_SHIFT (20U)
#define CAAM_RDSTA_CE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_CE_SHIFT)) & CAAM_RDSTA_CE_MASK)
#define CAAM_RDSTA_SKVN_MASK (0x40000000U)
#define CAAM_RDSTA_SKVN_SHIFT (30U)
#define CAAM_RDSTA_SKVN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVN_SHIFT)) & CAAM_RDSTA_SKVN_MASK)
#define CAAM_RDSTA_SKVT_MASK (0x80000000U)
#define CAAM_RDSTA_SKVT_SHIFT (31U)
#define CAAM_RDSTA_SKVT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDSTA_SKVT_SHIFT)) & CAAM_RDSTA_SKVT_MASK)
/*! @} */
/*! @name RDINT0 - RNG DRNG State Handle 0 Reseed Interval Register */
/*! @{ */
#define CAAM_RDINT0_RESINT0_MASK (0xFFFFFFFFU)
#define CAAM_RDINT0_RESINT0_SHIFT (0U)
#define CAAM_RDINT0_RESINT0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT0_RESINT0_SHIFT)) & CAAM_RDINT0_RESINT0_MASK)
/*! @} */
/*! @name RDINT1 - RNG DRNG State Handle 1 Reseed Interval Register */
/*! @{ */
#define CAAM_RDINT1_RESINT1_MASK (0xFFFFFFFFU)
#define CAAM_RDINT1_RESINT1_SHIFT (0U)
#define CAAM_RDINT1_RESINT1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDINT1_RESINT1_SHIFT)) & CAAM_RDINT1_RESINT1_MASK)
/*! @} */
/*! @name RDHCNTL - RNG DRNG Hash Control Register */
/*! @{ */
#define CAAM_RDHCNTL_HD_MASK (0x1U)
#define CAAM_RDHCNTL_HD_SHIFT (0U)
#define CAAM_RDHCNTL_HD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HD_SHIFT)) & CAAM_RDHCNTL_HD_MASK)
#define CAAM_RDHCNTL_HB_MASK (0x2U)
#define CAAM_RDHCNTL_HB_SHIFT (1U)
#define CAAM_RDHCNTL_HB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HB_SHIFT)) & CAAM_RDHCNTL_HB_MASK)
#define CAAM_RDHCNTL_HI_MASK (0x4U)
#define CAAM_RDHCNTL_HI_SHIFT (2U)
#define CAAM_RDHCNTL_HI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HI_SHIFT)) & CAAM_RDHCNTL_HI_MASK)
#define CAAM_RDHCNTL_HTM_MASK (0x8U)
#define CAAM_RDHCNTL_HTM_SHIFT (3U)
#define CAAM_RDHCNTL_HTM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTM_SHIFT)) & CAAM_RDHCNTL_HTM_MASK)
#define CAAM_RDHCNTL_HTC_MASK (0x10U)
#define CAAM_RDHCNTL_HTC_SHIFT (4U)
#define CAAM_RDHCNTL_HTC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHCNTL_HTC_SHIFT)) & CAAM_RDHCNTL_HTC_MASK)
/*! @} */
/*! @name RDHDIG - RNG DRNG Hash Digest Register */
/*! @{ */
#define CAAM_RDHDIG_HASHMD_MASK (0xFFFFFFFFU)
#define CAAM_RDHDIG_HASHMD_SHIFT (0U)
#define CAAM_RDHDIG_HASHMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHDIG_HASHMD_SHIFT)) & CAAM_RDHDIG_HASHMD_MASK)
/*! @} */
/*! @name RDHBUF - RNG DRNG Hash Buffer Register */
/*! @{ */
#define CAAM_RDHBUF_HASHBUF_MASK (0xFFFFFFFFU)
#define CAAM_RDHBUF_HASHBUF_SHIFT (0U)
#define CAAM_RDHBUF_HASHBUF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RDHBUF_HASHBUF_SHIFT)) & CAAM_RDHBUF_HASHBUF_MASK)
/*! @} */
/*! @name PX_SDID_PG0 - Partition 0 SDID register..Partition 15 SDID register */
/*! @{ */
#define CAAM_PX_SDID_PG0_SDID_MASK (0xFFFFU)
#define CAAM_PX_SDID_PG0_SDID_SHIFT (0U)
#define CAAM_PX_SDID_PG0_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_PG0_SDID_SHIFT)) & CAAM_PX_SDID_PG0_SDID_MASK)
/*! @} */
/* The count of CAAM_PX_SDID_PG0 */
#define CAAM_PX_SDID_PG0_COUNT (16U)
/*! @name PX_SMAPR_PG0 - Secure Memory Access Permissions register */
/*! @{ */
#define CAAM_PX_SMAPR_PG0_G1_READ_MASK (0x1U)
#define CAAM_PX_SMAPR_PG0_G1_READ_SHIFT (0U)
/*! G1_READ
* 0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and
* key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a
* Trusted Descriptor and G1_TDO=1).
* 0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
* G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0).
*/
#define CAAM_PX_SMAPR_PG0_G1_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_READ_MASK)
#define CAAM_PX_SMAPR_PG0_G1_WRITE_MASK (0x2U)
#define CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT (1U)
/*! G1_WRITE
* 0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
* Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1).
* 0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is
* not a Trusted Descriptor or if G1_TDO=0).
*/
#define CAAM_PX_SMAPR_PG0_G1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_WRITE_MASK)
#define CAAM_PX_SMAPR_PG0_G1_TDO_MASK (0x4U)
#define CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT (2U)
/*! G1_TDO
* 0b0..Trusted Descriptors have the same access privileges as Job Descriptors
* 0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
* or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB,
* G1_WRITE and G1_READ settings.
*/
#define CAAM_PX_SMAPR_PG0_G1_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_TDO_MASK)
#define CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK (0x8U)
#define CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT (3U)
/*! G1_SMBLOB
* 0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1.
* 0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings.
*/
#define CAAM_PX_SMAPR_PG0_G1_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G1_SMBLOB_MASK)
#define CAAM_PX_SMAPR_PG0_G2_READ_MASK (0x10U)
#define CAAM_PX_SMAPR_PG0_G2_READ_SHIFT (4U)
/*! G2_READ
* 0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and
* key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a
* Trusted Descriptor and G2_TDO=1).
* 0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
* G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0).
*/
#define CAAM_PX_SMAPR_PG0_G2_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_READ_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_READ_MASK)
#define CAAM_PX_SMAPR_PG0_G2_WRITE_MASK (0x20U)
#define CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT (5U)
/*! G2_WRITE
* 0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
* Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1).
* 0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is
* not a Trusted Descriptor or if G2_TDO=0).
*/
#define CAAM_PX_SMAPR_PG0_G2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_WRITE_MASK)
#define CAAM_PX_SMAPR_PG0_G2_TDO_MASK (0x40U)
#define CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT (6U)
/*! G2_TDO
* 0b0..Trusted Descriptors have the same access privileges as Job Descriptors
* 0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
* or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB,
* G2_WRITE and G2_READ settings.
*/
#define CAAM_PX_SMAPR_PG0_G2_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_TDO_MASK)
#define CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK (0x80U)
#define CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT (7U)
/*! G2_SMBLOB
* 0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1.
* 0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings.
*/
#define CAAM_PX_SMAPR_PG0_G2_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_PG0_G2_SMBLOB_MASK)
#define CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK (0x1000U)
#define CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT (12U)
/*! SMAG_LCK
* 0b0..The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers.
* 0b1..The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed
* until the partition is de-allocated or a POR occurs.
*/
#define CAAM_PX_SMAPR_PG0_SMAG_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAG_LCK_MASK)
#define CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK (0x2000U)
#define CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT (13U)
/*! SMAP_LCK
* 0b0..The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register.
* 0b1..The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP
* register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can
* still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0.
*/
#define CAAM_PX_SMAPR_PG0_SMAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_PG0_SMAP_LCK_MASK)
#define CAAM_PX_SMAPR_PG0_PSP_MASK (0x4000U)
#define CAAM_PX_SMAPR_PG0_PSP_SHIFT (14U)
/*! PSP
* 0b0..The partition and any of the pages allocated to the partition can be de-allocated.
* 0b1..The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated.
*/
#define CAAM_PX_SMAPR_PG0_PSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PSP_SHIFT)) & CAAM_PX_SMAPR_PG0_PSP_MASK)
#define CAAM_PX_SMAPR_PG0_CSP_MASK (0x8000U)
#define CAAM_PX_SMAPR_PG0_CSP_SHIFT (15U)
/*! CSP
* 0b0..The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is
* released or a security alarm occurs.
* 0b1..The pages allocated to the partition will be zeroized when they are individually de-allocated or the
* partition is released or a security alarm occurs.
*/
#define CAAM_PX_SMAPR_PG0_CSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_CSP_SHIFT)) & CAAM_PX_SMAPR_PG0_CSP_MASK)
#define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK (0xFFFF0000U)
#define CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT (16U)
#define CAAM_PX_SMAPR_PG0_PARTITION_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_PG0_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_PG0_PARTITION_KMOD_MASK)
/*! @} */
/* The count of CAAM_PX_SMAPR_PG0 */
#define CAAM_PX_SMAPR_PG0_COUNT (16U)
/*! @name PX_SMAG2_PG0 - Secure Memory Access Group Registers */
/*! @{ */
#define CAAM_PX_SMAG2_PG0_Gx_ID00_MASK (0x1U)
#define CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT (0U)
#define CAAM_PX_SMAG2_PG0_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID00_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID01_MASK (0x2U)
#define CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT (1U)
#define CAAM_PX_SMAG2_PG0_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID01_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID02_MASK (0x4U)
#define CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT (2U)
#define CAAM_PX_SMAG2_PG0_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID02_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID03_MASK (0x8U)
#define CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT (3U)
#define CAAM_PX_SMAG2_PG0_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID03_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID04_MASK (0x10U)
#define CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT (4U)
#define CAAM_PX_SMAG2_PG0_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID04_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID05_MASK (0x20U)
#define CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT (5U)
#define CAAM_PX_SMAG2_PG0_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID05_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID06_MASK (0x40U)
#define CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT (6U)
#define CAAM_PX_SMAG2_PG0_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID06_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID07_MASK (0x80U)
#define CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT (7U)
#define CAAM_PX_SMAG2_PG0_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID07_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID08_MASK (0x100U)
#define CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT (8U)
#define CAAM_PX_SMAG2_PG0_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID08_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID09_MASK (0x200U)
#define CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT (9U)
#define CAAM_PX_SMAG2_PG0_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID09_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID10_MASK (0x400U)
#define CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT (10U)
#define CAAM_PX_SMAG2_PG0_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID10_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID11_MASK (0x800U)
#define CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT (11U)
#define CAAM_PX_SMAG2_PG0_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID11_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID12_MASK (0x1000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT (12U)
#define CAAM_PX_SMAG2_PG0_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID12_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID13_MASK (0x2000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT (13U)
#define CAAM_PX_SMAG2_PG0_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID13_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID14_MASK (0x4000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT (14U)
#define CAAM_PX_SMAG2_PG0_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID14_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID15_MASK (0x8000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT (15U)
#define CAAM_PX_SMAG2_PG0_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID15_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID16_MASK (0x10000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT (16U)
#define CAAM_PX_SMAG2_PG0_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID16_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID17_MASK (0x20000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT (17U)
#define CAAM_PX_SMAG2_PG0_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID17_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID18_MASK (0x40000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT (18U)
#define CAAM_PX_SMAG2_PG0_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID18_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID19_MASK (0x80000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT (19U)
#define CAAM_PX_SMAG2_PG0_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID19_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID20_MASK (0x100000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT (20U)
#define CAAM_PX_SMAG2_PG0_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID20_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID21_MASK (0x200000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT (21U)
#define CAAM_PX_SMAG2_PG0_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID21_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID22_MASK (0x400000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT (22U)
#define CAAM_PX_SMAG2_PG0_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID22_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID23_MASK (0x800000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT (23U)
#define CAAM_PX_SMAG2_PG0_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID23_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID24_MASK (0x1000000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT (24U)
#define CAAM_PX_SMAG2_PG0_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID24_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID25_MASK (0x2000000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT (25U)
#define CAAM_PX_SMAG2_PG0_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID25_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID26_MASK (0x4000000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT (26U)
#define CAAM_PX_SMAG2_PG0_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID26_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID27_MASK (0x8000000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT (27U)
#define CAAM_PX_SMAG2_PG0_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID27_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID28_MASK (0x10000000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT (28U)
#define CAAM_PX_SMAG2_PG0_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID28_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID29_MASK (0x20000000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT (29U)
#define CAAM_PX_SMAG2_PG0_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID29_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID30_MASK (0x40000000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT (30U)
#define CAAM_PX_SMAG2_PG0_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID30_MASK)
#define CAAM_PX_SMAG2_PG0_Gx_ID31_MASK (0x80000000U)
#define CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT (31U)
#define CAAM_PX_SMAG2_PG0_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_PG0_Gx_ID31_MASK)
/*! @} */
/* The count of CAAM_PX_SMAG2_PG0 */
#define CAAM_PX_SMAG2_PG0_COUNT (16U)
/*! @name PX_SMAG1_PG0 - Secure Memory Access Group Registers */
/*! @{ */
#define CAAM_PX_SMAG1_PG0_Gx_ID00_MASK (0x1U)
#define CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT (0U)
#define CAAM_PX_SMAG1_PG0_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID00_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID01_MASK (0x2U)
#define CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT (1U)
#define CAAM_PX_SMAG1_PG0_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID01_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID02_MASK (0x4U)
#define CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT (2U)
#define CAAM_PX_SMAG1_PG0_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID02_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID03_MASK (0x8U)
#define CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT (3U)
#define CAAM_PX_SMAG1_PG0_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID03_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID04_MASK (0x10U)
#define CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT (4U)
#define CAAM_PX_SMAG1_PG0_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID04_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID05_MASK (0x20U)
#define CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT (5U)
#define CAAM_PX_SMAG1_PG0_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID05_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID06_MASK (0x40U)
#define CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT (6U)
#define CAAM_PX_SMAG1_PG0_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID06_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID07_MASK (0x80U)
#define CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT (7U)
#define CAAM_PX_SMAG1_PG0_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID07_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID08_MASK (0x100U)
#define CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT (8U)
#define CAAM_PX_SMAG1_PG0_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID08_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID09_MASK (0x200U)
#define CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT (9U)
#define CAAM_PX_SMAG1_PG0_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID09_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID10_MASK (0x400U)
#define CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT (10U)
#define CAAM_PX_SMAG1_PG0_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID10_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID11_MASK (0x800U)
#define CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT (11U)
#define CAAM_PX_SMAG1_PG0_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID11_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID12_MASK (0x1000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT (12U)
#define CAAM_PX_SMAG1_PG0_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID12_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID13_MASK (0x2000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT (13U)
#define CAAM_PX_SMAG1_PG0_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID13_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID14_MASK (0x4000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT (14U)
#define CAAM_PX_SMAG1_PG0_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID14_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID15_MASK (0x8000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT (15U)
#define CAAM_PX_SMAG1_PG0_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID15_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID16_MASK (0x10000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT (16U)
#define CAAM_PX_SMAG1_PG0_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID16_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID17_MASK (0x20000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT (17U)
#define CAAM_PX_SMAG1_PG0_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID17_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID18_MASK (0x40000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT (18U)
#define CAAM_PX_SMAG1_PG0_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID18_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID19_MASK (0x80000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT (19U)
#define CAAM_PX_SMAG1_PG0_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID19_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID20_MASK (0x100000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT (20U)
#define CAAM_PX_SMAG1_PG0_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID20_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID21_MASK (0x200000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT (21U)
#define CAAM_PX_SMAG1_PG0_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID21_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID22_MASK (0x400000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT (22U)
#define CAAM_PX_SMAG1_PG0_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID22_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID23_MASK (0x800000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT (23U)
#define CAAM_PX_SMAG1_PG0_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID23_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID24_MASK (0x1000000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT (24U)
#define CAAM_PX_SMAG1_PG0_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID24_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID25_MASK (0x2000000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT (25U)
#define CAAM_PX_SMAG1_PG0_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID25_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID26_MASK (0x4000000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT (26U)
#define CAAM_PX_SMAG1_PG0_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID26_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID27_MASK (0x8000000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT (27U)
#define CAAM_PX_SMAG1_PG0_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID27_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID28_MASK (0x10000000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT (28U)
#define CAAM_PX_SMAG1_PG0_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID28_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID29_MASK (0x20000000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT (29U)
#define CAAM_PX_SMAG1_PG0_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID29_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID30_MASK (0x40000000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT (30U)
#define CAAM_PX_SMAG1_PG0_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID30_MASK)
#define CAAM_PX_SMAG1_PG0_Gx_ID31_MASK (0x80000000U)
#define CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT (31U)
#define CAAM_PX_SMAG1_PG0_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_PG0_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_PG0_Gx_ID31_MASK)
/*! @} */
/* The count of CAAM_PX_SMAG1_PG0 */
#define CAAM_PX_SMAG1_PG0_COUNT (16U)
/*! @name REIS - Recoverable Error Interrupt Status */
/*! @{ */
#define CAAM_REIS_CWDE_MASK (0x1U)
#define CAAM_REIS_CWDE_SHIFT (0U)
#define CAAM_REIS_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_CWDE_SHIFT)) & CAAM_REIS_CWDE_MASK)
#define CAAM_REIS_RBAE_MASK (0x10000U)
#define CAAM_REIS_RBAE_SHIFT (16U)
#define CAAM_REIS_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_RBAE_SHIFT)) & CAAM_REIS_RBAE_MASK)
#define CAAM_REIS_JBAE0_MASK (0x1000000U)
#define CAAM_REIS_JBAE0_SHIFT (24U)
#define CAAM_REIS_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE0_SHIFT)) & CAAM_REIS_JBAE0_MASK)
#define CAAM_REIS_JBAE1_MASK (0x2000000U)
#define CAAM_REIS_JBAE1_SHIFT (25U)
#define CAAM_REIS_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE1_SHIFT)) & CAAM_REIS_JBAE1_MASK)
#define CAAM_REIS_JBAE2_MASK (0x4000000U)
#define CAAM_REIS_JBAE2_SHIFT (26U)
#define CAAM_REIS_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE2_SHIFT)) & CAAM_REIS_JBAE2_MASK)
#define CAAM_REIS_JBAE3_MASK (0x8000000U)
#define CAAM_REIS_JBAE3_SHIFT (27U)
#define CAAM_REIS_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIS_JBAE3_SHIFT)) & CAAM_REIS_JBAE3_MASK)
/*! @} */
/*! @name REIE - Recoverable Error Interrupt Enable */
/*! @{ */
#define CAAM_REIE_CWDE_MASK (0x1U)
#define CAAM_REIE_CWDE_SHIFT (0U)
#define CAAM_REIE_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_CWDE_SHIFT)) & CAAM_REIE_CWDE_MASK)
#define CAAM_REIE_RBAE_MASK (0x10000U)
#define CAAM_REIE_RBAE_SHIFT (16U)
#define CAAM_REIE_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_RBAE_SHIFT)) & CAAM_REIE_RBAE_MASK)
#define CAAM_REIE_JBAE0_MASK (0x1000000U)
#define CAAM_REIE_JBAE0_SHIFT (24U)
#define CAAM_REIE_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE0_SHIFT)) & CAAM_REIE_JBAE0_MASK)
#define CAAM_REIE_JBAE1_MASK (0x2000000U)
#define CAAM_REIE_JBAE1_SHIFT (25U)
#define CAAM_REIE_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE1_SHIFT)) & CAAM_REIE_JBAE1_MASK)
#define CAAM_REIE_JBAE2_MASK (0x4000000U)
#define CAAM_REIE_JBAE2_SHIFT (26U)
#define CAAM_REIE_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE2_SHIFT)) & CAAM_REIE_JBAE2_MASK)
#define CAAM_REIE_JBAE3_MASK (0x8000000U)
#define CAAM_REIE_JBAE3_SHIFT (27U)
#define CAAM_REIE_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIE_JBAE3_SHIFT)) & CAAM_REIE_JBAE3_MASK)
/*! @} */
/*! @name REIF - Recoverable Error Interrupt Force */
/*! @{ */
#define CAAM_REIF_CWDE_MASK (0x1U)
#define CAAM_REIF_CWDE_SHIFT (0U)
#define CAAM_REIF_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_CWDE_SHIFT)) & CAAM_REIF_CWDE_MASK)
#define CAAM_REIF_RBAE_MASK (0x10000U)
#define CAAM_REIF_RBAE_SHIFT (16U)
#define CAAM_REIF_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_RBAE_SHIFT)) & CAAM_REIF_RBAE_MASK)
#define CAAM_REIF_JBAE0_MASK (0x1000000U)
#define CAAM_REIF_JBAE0_SHIFT (24U)
#define CAAM_REIF_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE0_SHIFT)) & CAAM_REIF_JBAE0_MASK)
#define CAAM_REIF_JBAE1_MASK (0x2000000U)
#define CAAM_REIF_JBAE1_SHIFT (25U)
#define CAAM_REIF_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE1_SHIFT)) & CAAM_REIF_JBAE1_MASK)
#define CAAM_REIF_JBAE2_MASK (0x4000000U)
#define CAAM_REIF_JBAE2_SHIFT (26U)
#define CAAM_REIF_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE2_SHIFT)) & CAAM_REIF_JBAE2_MASK)
#define CAAM_REIF_JBAE3_MASK (0x8000000U)
#define CAAM_REIF_JBAE3_SHIFT (27U)
#define CAAM_REIF_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIF_JBAE3_SHIFT)) & CAAM_REIF_JBAE3_MASK)
/*! @} */
/*! @name REIH - Recoverable Error Interrupt Halt */
/*! @{ */
#define CAAM_REIH_CWDE_MASK (0x1U)
#define CAAM_REIH_CWDE_SHIFT (0U)
/*! CWDE
* 0b0..Don't halt CAAM if CAAM watchdog expired.
* 0b1..Halt CAAM if CAAM watchdog expired..
*/
#define CAAM_REIH_CWDE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_CWDE_SHIFT)) & CAAM_REIH_CWDE_MASK)
#define CAAM_REIH_RBAE_MASK (0x10000U)
#define CAAM_REIH_RBAE_SHIFT (16U)
/*! RBAE
* 0b0..Don't halt CAAM if RTIC-initiated job execution caused bus access error.
* 0b1..Halt CAAM if RTIC-initiated job execution caused bus access error.
*/
#define CAAM_REIH_RBAE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_RBAE_SHIFT)) & CAAM_REIH_RBAE_MASK)
#define CAAM_REIH_JBAE0_MASK (0x1000000U)
#define CAAM_REIH_JBAE0_SHIFT (24U)
/*! JBAE0
* 0b0..Don't halt CAAM if JR0-initiated job execution caused bus access error.
* 0b1..Halt CAAM if JR0-initiated job execution caused bus access error.
*/
#define CAAM_REIH_JBAE0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE0_SHIFT)) & CAAM_REIH_JBAE0_MASK)
#define CAAM_REIH_JBAE1_MASK (0x2000000U)
#define CAAM_REIH_JBAE1_SHIFT (25U)
/*! JBAE1
* 0b0..Don't halt CAAM if JR1-initiated job execution caused bus access error.
* 0b1..Halt CAAM if JR1-initiated job execution caused bus access error.
*/
#define CAAM_REIH_JBAE1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE1_SHIFT)) & CAAM_REIH_JBAE1_MASK)
#define CAAM_REIH_JBAE2_MASK (0x4000000U)
#define CAAM_REIH_JBAE2_SHIFT (26U)
/*! JBAE2
* 0b0..Don't halt CAAM if JR2-initiated job execution caused bus access error.
* 0b1..Halt CAAM if JR2-initiated job execution caused bus access error.
*/
#define CAAM_REIH_JBAE2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE2_SHIFT)) & CAAM_REIH_JBAE2_MASK)
#define CAAM_REIH_JBAE3_MASK (0x8000000U)
#define CAAM_REIH_JBAE3_SHIFT (27U)
/*! JBAE3
* 0b0..Don't halt CAAM if JR3-initiated job execution caused bus access error.
* 0b1..Halt CAAM if JR3-initiated job execution caused bus access error.
*/
#define CAAM_REIH_JBAE3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIH_JBAE3_SHIFT)) & CAAM_REIH_JBAE3_MASK)
/*! @} */
/*! @name SMWPJRR - Secure Memory Write Protect Job Ring Register */
/*! @{ */
#define CAAM_SMWPJRR_SMR_WP_JRa_MASK (0x1U)
#define CAAM_SMWPJRR_SMR_WP_JRa_SHIFT (0U)
#define CAAM_SMWPJRR_SMR_WP_JRa(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMWPJRR_SMR_WP_JRa_SHIFT)) & CAAM_SMWPJRR_SMR_WP_JRa_MASK)
/*! @} */
/* The count of CAAM_SMWPJRR */
#define CAAM_SMWPJRR_COUNT (4U)
/*! @name SMCR_PG0 - Secure Memory Command Register */
/*! @{ */
#define CAAM_SMCR_PG0_CMD_MASK (0xFU)
#define CAAM_SMCR_PG0_CMD_SHIFT (0U)
#define CAAM_SMCR_PG0_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_CMD_SHIFT)) & CAAM_SMCR_PG0_CMD_MASK)
#define CAAM_SMCR_PG0_PRTN_MASK (0xF00U)
#define CAAM_SMCR_PG0_PRTN_SHIFT (8U)
#define CAAM_SMCR_PG0_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PRTN_SHIFT)) & CAAM_SMCR_PG0_PRTN_MASK)
#define CAAM_SMCR_PG0_PAGE_MASK (0xFFFF0000U)
#define CAAM_SMCR_PG0_PAGE_SHIFT (16U)
#define CAAM_SMCR_PG0_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_PG0_PAGE_SHIFT)) & CAAM_SMCR_PG0_PAGE_MASK)
/*! @} */
/*! @name SMCSR_PG0 - Secure Memory Command Status Register */
/*! @{ */
#define CAAM_SMCSR_PG0_PRTN_MASK (0xFU)
#define CAAM_SMCSR_PG0_PRTN_SHIFT (0U)
#define CAAM_SMCSR_PG0_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PRTN_SHIFT)) & CAAM_SMCSR_PG0_PRTN_MASK)
#define CAAM_SMCSR_PG0_PO_MASK (0xC0U)
#define CAAM_SMCSR_PG0_PO_SHIFT (6U)
/*! PO
* 0b00..Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No
* zeroization is needed since it has already been cleared, therefore no interrupt should be expected.
* 0b01..Page does not exist in this version or is not initialized yet.
* 0b10..Another entity owns the page. This page is unavailable to the issuer of the inquiry.
* 0b11..Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not
* marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized
* upon de-allocation.
*/
#define CAAM_SMCSR_PG0_PO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PO_SHIFT)) & CAAM_SMCSR_PG0_PO_MASK)
#define CAAM_SMCSR_PG0_AERR_MASK (0x3000U)
#define CAAM_SMCSR_PG0_AERR_SHIFT (12U)
#define CAAM_SMCSR_PG0_AERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_AERR_SHIFT)) & CAAM_SMCSR_PG0_AERR_MASK)
#define CAAM_SMCSR_PG0_CERR_MASK (0xC000U)
#define CAAM_SMCSR_PG0_CERR_SHIFT (14U)
/*! CERR
* 0b00..No Error.
* 0b01..Command has not yet completed.
* 0b10..A security failure occurred.
* 0b11..Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous
* command completed. The additional command was ignored.
*/
#define CAAM_SMCSR_PG0_CERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_CERR_SHIFT)) & CAAM_SMCSR_PG0_CERR_MASK)
#define CAAM_SMCSR_PG0_PAGE_MASK (0xFFF0000U)
#define CAAM_SMCSR_PG0_PAGE_SHIFT (16U)
#define CAAM_SMCSR_PG0_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_PG0_PAGE_SHIFT)) & CAAM_SMCSR_PG0_PAGE_MASK)
/*! @} */
/*! @name CAAMVID_MS_TRAD - CAAM Version ID Register, most-significant half */
/*! @{ */
#define CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK (0xFFU)
#define CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT (0U)
#define CAAM_CAAMVID_MS_TRAD_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MIN_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MIN_REV_MASK)
#define CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK (0xFF00U)
#define CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT (8U)
#define CAAM_CAAMVID_MS_TRAD_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_MAJ_REV_SHIFT)) & CAAM_CAAMVID_MS_TRAD_MAJ_REV_MASK)
#define CAAM_CAAMVID_MS_TRAD_IP_ID_MASK (0xFFFF0000U)
#define CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT (16U)
#define CAAM_CAAMVID_MS_TRAD_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_MS_TRAD_IP_ID_SHIFT)) & CAAM_CAAMVID_MS_TRAD_IP_ID_MASK)
/*! @} */
/*! @name CAAMVID_LS_TRAD - CAAM Version ID Register, least-significant half */
/*! @{ */
#define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK (0xFFU)
#define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT (0U)
#define CAAM_CAAMVID_LS_TRAD_CONFIG_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_CONFIG_OPT_MASK)
#define CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK (0xFF00U)
#define CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT (8U)
#define CAAM_CAAMVID_LS_TRAD_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_ECO_REV_SHIFT)) & CAAM_CAAMVID_LS_TRAD_ECO_REV_MASK)
#define CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK (0xFF0000U)
#define CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT (16U)
#define CAAM_CAAMVID_LS_TRAD_INTG_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_INTG_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_INTG_OPT_MASK)
#define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK (0xFF000000U)
#define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT (24U)
#define CAAM_CAAMVID_LS_TRAD_COMPILE_OPT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_SHIFT)) & CAAM_CAAMVID_LS_TRAD_COMPILE_OPT_MASK)
/*! @} */
/*! @name HT_JD_ADDR - Holding Tank 0 Job Descriptor Address */
/*! @{ */
#define CAAM_HT_JD_ADDR_JD_ADDR_MASK (0xFFFFFFFFFU)
#define CAAM_HT_JD_ADDR_JD_ADDR_SHIFT (0U)
#define CAAM_HT_JD_ADDR_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_HT_JD_ADDR_JD_ADDR_SHIFT)) & CAAM_HT_JD_ADDR_JD_ADDR_MASK)
/*! @} */
/* The count of CAAM_HT_JD_ADDR */
#define CAAM_HT_JD_ADDR_COUNT (1U)
/*! @name HT_SD_ADDR - Holding Tank 0 Shared Descriptor Address */
/*! @{ */
#define CAAM_HT_SD_ADDR_SD_ADDR_MASK (0xFFFFFFFFFU)
#define CAAM_HT_SD_ADDR_SD_ADDR_SHIFT (0U)
#define CAAM_HT_SD_ADDR_SD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_HT_SD_ADDR_SD_ADDR_SHIFT)) & CAAM_HT_SD_ADDR_SD_ADDR_MASK)
/*! @} */
/* The count of CAAM_HT_SD_ADDR */
#define CAAM_HT_SD_ADDR_COUNT (1U)
/*! @name HT_JQ_CTRL_MS - Holding Tank 0 Job Queue Control, most-significant half */
/*! @{ */
#define CAAM_HT_JQ_CTRL_MS_ID_MASK (0x7U)
#define CAAM_HT_JQ_CTRL_MS_ID_SHIFT (0U)
#define CAAM_HT_JQ_CTRL_MS_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ID_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ID_MASK)
#define CAAM_HT_JQ_CTRL_MS_SRC_MASK (0x700U)
#define CAAM_HT_JQ_CTRL_MS_SRC_SHIFT (8U)
/*! SRC
* 0b000..Job Ring 0
* 0b001..Job Ring 1
* 0b010..Job Ring 2
* 0b011..Job Ring 3
* 0b100..RTIC
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define CAAM_HT_JQ_CTRL_MS_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SRC_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SRC_MASK)
#define CAAM_HT_JQ_CTRL_MS_JDDS_MASK (0x4000U)
#define CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT (14U)
/*! JDDS
* 0b1..SEQ DID
* 0b0..Non-SEQ DID
*/
#define CAAM_HT_JQ_CTRL_MS_JDDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_JDDS_SHIFT)) & CAAM_HT_JQ_CTRL_MS_JDDS_MASK)
#define CAAM_HT_JQ_CTRL_MS_AMTD_MASK (0x8000U)
#define CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT (15U)
#define CAAM_HT_JQ_CTRL_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_AMTD_SHIFT)) & CAAM_HT_JQ_CTRL_MS_AMTD_MASK)
#define CAAM_HT_JQ_CTRL_MS_SOB_MASK (0x10000U)
#define CAAM_HT_JQ_CTRL_MS_SOB_SHIFT (16U)
#define CAAM_HT_JQ_CTRL_MS_SOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SOB_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SOB_MASK)
#define CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK (0x60000U)
#define CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT (17U)
/*! HT_ERROR
* 0b00..No error
* 0b01..Job Descriptor or Shared Descriptor length error
* 0b10..AXI_error while reading a Job Ring Shared Descriptor or the remainder of a Job Ring Job Descriptor
* 0b11..reserved
*/
#define CAAM_HT_JQ_CTRL_MS_HT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_HT_ERROR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_HT_ERROR_MASK)
#define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK (0x80000U)
#define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT (19U)
/*! DWORD_SWAP
* 0b0..DWords are in the order most-significant word, least-significant word.
* 0b1..DWords are in the order least-significant word, most-significant word.
*/
#define CAAM_HT_JQ_CTRL_MS_DWORD_SWAP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_SHIFT)) & CAAM_HT_JQ_CTRL_MS_DWORD_SWAP_MASK)
#define CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK (0x7C00000U)
#define CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT (22U)
#define CAAM_HT_JQ_CTRL_MS_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_SHR_FROM_SHIFT)) & CAAM_HT_JQ_CTRL_MS_SHR_FROM_MASK)
#define CAAM_HT_JQ_CTRL_MS_ILE_MASK (0x8000000U)
#define CAAM_HT_JQ_CTRL_MS_ILE_SHIFT (27U)
/*! ILE
* 0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
* 0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
*/
#define CAAM_HT_JQ_CTRL_MS_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_ILE_SHIFT)) & CAAM_HT_JQ_CTRL_MS_ILE_MASK)
#define CAAM_HT_JQ_CTRL_MS_FOUR_MASK (0x10000000U)
#define CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT (28U)
#define CAAM_HT_JQ_CTRL_MS_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_FOUR_SHIFT)) & CAAM_HT_JQ_CTRL_MS_FOUR_MASK)
#define CAAM_HT_JQ_CTRL_MS_WHL_MASK (0x20000000U)
#define CAAM_HT_JQ_CTRL_MS_WHL_SHIFT (29U)
#define CAAM_HT_JQ_CTRL_MS_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_MS_WHL_SHIFT)) & CAAM_HT_JQ_CTRL_MS_WHL_MASK)
/*! @} */
/* The count of CAAM_HT_JQ_CTRL_MS */
#define CAAM_HT_JQ_CTRL_MS_COUNT (1U)
/*! @name HT_JQ_CTRL_LS - Holding Tank 0 Job Queue Control, least-significant half */
/*! @{ */
#define CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK (0xFU)
#define CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT (0U)
#define CAAM_HT_JQ_CTRL_LS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_DID_MASK)
#define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK (0x10U)
#define CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT (4U)
/*! PRIM_TZ
* 0b0..TrustZone NonSecureWorld
* 0b1..TrustZone SecureWorld
*/
#define CAAM_HT_JQ_CTRL_LS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_TZ_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_TZ_MASK)
#define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK (0xFFE0U)
#define CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT (5U)
#define CAAM_HT_JQ_CTRL_LS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_PRIM_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_PRIM_ICID_MASK)
#define CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK (0xF0000U)
#define CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT (16U)
#define CAAM_HT_JQ_CTRL_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_DID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_DID_MASK)
#define CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK (0xFFE00000U)
#define CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT (21U)
#define CAAM_HT_JQ_CTRL_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_JQ_CTRL_LS_OUT_ICID_SHIFT)) & CAAM_HT_JQ_CTRL_LS_OUT_ICID_MASK)
/*! @} */
/* The count of CAAM_HT_JQ_CTRL_LS */
#define CAAM_HT_JQ_CTRL_LS_COUNT (1U)
/*! @name HT_STATUS - Holding Tank Status */
/*! @{ */
#define CAAM_HT_STATUS_PEND_0_MASK (0x1U)
#define CAAM_HT_STATUS_PEND_0_SHIFT (0U)
#define CAAM_HT_STATUS_PEND_0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_PEND_0_SHIFT)) & CAAM_HT_STATUS_PEND_0_MASK)
#define CAAM_HT_STATUS_IN_USE_MASK (0x40000000U)
#define CAAM_HT_STATUS_IN_USE_SHIFT (30U)
#define CAAM_HT_STATUS_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_IN_USE_SHIFT)) & CAAM_HT_STATUS_IN_USE_MASK)
#define CAAM_HT_STATUS_BC_MASK (0x80000000U)
#define CAAM_HT_STATUS_BC_SHIFT (31U)
#define CAAM_HT_STATUS_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_HT_STATUS_BC_SHIFT)) & CAAM_HT_STATUS_BC_MASK)
/*! @} */
/* The count of CAAM_HT_STATUS */
#define CAAM_HT_STATUS_COUNT (1U)
/*! @name JQ_DEBUG_SEL - Job Queue Debug Select Register */
/*! @{ */
#define CAAM_JQ_DEBUG_SEL_HT_SEL_MASK (0x1U)
#define CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT (0U)
#define CAAM_JQ_DEBUG_SEL_HT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_HT_SEL_SHIFT)) & CAAM_JQ_DEBUG_SEL_HT_SEL_MASK)
#define CAAM_JQ_DEBUG_SEL_JOB_ID_MASK (0x70000U)
#define CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT (16U)
#define CAAM_JQ_DEBUG_SEL_JOB_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JQ_DEBUG_SEL_JOB_ID_SHIFT)) & CAAM_JQ_DEBUG_SEL_JOB_ID_MASK)
/*! @} */
/*! @name JRJIDU_LS - Job Ring Job IDs in Use Register, least-significant half */
/*! @{ */
#define CAAM_JRJIDU_LS_JID00_MASK (0x1U)
#define CAAM_JRJIDU_LS_JID00_SHIFT (0U)
#define CAAM_JRJIDU_LS_JID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID00_SHIFT)) & CAAM_JRJIDU_LS_JID00_MASK)
#define CAAM_JRJIDU_LS_JID01_MASK (0x2U)
#define CAAM_JRJIDU_LS_JID01_SHIFT (1U)
#define CAAM_JRJIDU_LS_JID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID01_SHIFT)) & CAAM_JRJIDU_LS_JID01_MASK)
#define CAAM_JRJIDU_LS_JID02_MASK (0x4U)
#define CAAM_JRJIDU_LS_JID02_SHIFT (2U)
#define CAAM_JRJIDU_LS_JID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID02_SHIFT)) & CAAM_JRJIDU_LS_JID02_MASK)
#define CAAM_JRJIDU_LS_JID03_MASK (0x8U)
#define CAAM_JRJIDU_LS_JID03_SHIFT (3U)
#define CAAM_JRJIDU_LS_JID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJIDU_LS_JID03_SHIFT)) & CAAM_JRJIDU_LS_JID03_MASK)
/*! @} */
/*! @name JRJDJIFBC - Job Ring Job-Done Job ID FIFO BC */
/*! @{ */
#define CAAM_JRJDJIFBC_BC_MASK (0x80000000U)
#define CAAM_JRJDJIFBC_BC_SHIFT (31U)
#define CAAM_JRJDJIFBC_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIFBC_BC_SHIFT)) & CAAM_JRJDJIFBC_BC_MASK)
/*! @} */
/*! @name JRJDJIF - Job Ring Job-Done Job ID FIFO */
/*! @{ */
#define CAAM_JRJDJIF_JOB_ID_ENTRY_MASK (0x7U)
#define CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT (0U)
#define CAAM_JRJDJIF_JOB_ID_ENTRY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDJIF_JOB_ID_ENTRY_SHIFT)) & CAAM_JRJDJIF_JOB_ID_ENTRY_MASK)
/*! @} */
/*! @name JRJDS1 - Job Ring Job-Done Source 1 */
/*! @{ */
#define CAAM_JRJDS1_SRC_MASK (0x3U)
#define CAAM_JRJDS1_SRC_SHIFT (0U)
#define CAAM_JRJDS1_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_SRC_SHIFT)) & CAAM_JRJDS1_SRC_MASK)
#define CAAM_JRJDS1_VALID_MASK (0x80000000U)
#define CAAM_JRJDS1_VALID_SHIFT (31U)
#define CAAM_JRJDS1_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRJDS1_VALID_SHIFT)) & CAAM_JRJDS1_VALID_MASK)
/*! @} */
/*! @name JRJDDA - Job Ring Job-Done Descriptor Address 0 Register */
/*! @{ */
#define CAAM_JRJDDA_JD_ADDR_MASK (0xFFFFFFFFFU)
#define CAAM_JRJDDA_JD_ADDR_SHIFT (0U)
#define CAAM_JRJDDA_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_JRJDDA_JD_ADDR_SHIFT)) & CAAM_JRJDDA_JD_ADDR_MASK)
/*! @} */
/* The count of CAAM_JRJDDA */
#define CAAM_JRJDDA_COUNT (1U)
/*! @name CRNR_MS - CHA Revision Number Register, most-significant half */
/*! @{ */
#define CAAM_CRNR_MS_CRCRN_MASK (0xFU)
#define CAAM_CRNR_MS_CRCRN_SHIFT (0U)
#define CAAM_CRNR_MS_CRCRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_CRCRN_SHIFT)) & CAAM_CRNR_MS_CRCRN_MASK)
#define CAAM_CRNR_MS_SNW9RN_MASK (0xF0U)
#define CAAM_CRNR_MS_SNW9RN_SHIFT (4U)
#define CAAM_CRNR_MS_SNW9RN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_SNW9RN_SHIFT)) & CAAM_CRNR_MS_SNW9RN_MASK)
#define CAAM_CRNR_MS_ZERN_MASK (0xF00U)
#define CAAM_CRNR_MS_ZERN_SHIFT (8U)
#define CAAM_CRNR_MS_ZERN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZERN_SHIFT)) & CAAM_CRNR_MS_ZERN_MASK)
#define CAAM_CRNR_MS_ZARN_MASK (0xF000U)
#define CAAM_CRNR_MS_ZARN_SHIFT (12U)
#define CAAM_CRNR_MS_ZARN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_ZARN_SHIFT)) & CAAM_CRNR_MS_ZARN_MASK)
#define CAAM_CRNR_MS_DECORN_MASK (0xF000000U)
#define CAAM_CRNR_MS_DECORN_SHIFT (24U)
#define CAAM_CRNR_MS_DECORN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_DECORN_SHIFT)) & CAAM_CRNR_MS_DECORN_MASK)
#define CAAM_CRNR_MS_JRRN_MASK (0xF0000000U)
#define CAAM_CRNR_MS_JRRN_SHIFT (28U)
#define CAAM_CRNR_MS_JRRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_MS_JRRN_SHIFT)) & CAAM_CRNR_MS_JRRN_MASK)
/*! @} */
/*! @name CRNR_LS - CHA Revision Number Register, least-significant half */
/*! @{ */
#define CAAM_CRNR_LS_AESRN_MASK (0xFU)
#define CAAM_CRNR_LS_AESRN_SHIFT (0U)
#define CAAM_CRNR_LS_AESRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_AESRN_SHIFT)) & CAAM_CRNR_LS_AESRN_MASK)
#define CAAM_CRNR_LS_DESRN_MASK (0xF0U)
#define CAAM_CRNR_LS_DESRN_SHIFT (4U)
#define CAAM_CRNR_LS_DESRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_DESRN_SHIFT)) & CAAM_CRNR_LS_DESRN_MASK)
#define CAAM_CRNR_LS_MDRN_MASK (0xF000U)
#define CAAM_CRNR_LS_MDRN_SHIFT (12U)
#define CAAM_CRNR_LS_MDRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_MDRN_SHIFT)) & CAAM_CRNR_LS_MDRN_MASK)
#define CAAM_CRNR_LS_RNGRN_MASK (0xF0000U)
#define CAAM_CRNR_LS_RNGRN_SHIFT (16U)
#define CAAM_CRNR_LS_RNGRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_RNGRN_SHIFT)) & CAAM_CRNR_LS_RNGRN_MASK)
#define CAAM_CRNR_LS_SNW8RN_MASK (0xF00000U)
#define CAAM_CRNR_LS_SNW8RN_SHIFT (20U)
#define CAAM_CRNR_LS_SNW8RN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_SNW8RN_SHIFT)) & CAAM_CRNR_LS_SNW8RN_MASK)
#define CAAM_CRNR_LS_KASRN_MASK (0xF000000U)
#define CAAM_CRNR_LS_KASRN_SHIFT (24U)
#define CAAM_CRNR_LS_KASRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_KASRN_SHIFT)) & CAAM_CRNR_LS_KASRN_MASK)
#define CAAM_CRNR_LS_PKRN_MASK (0xF0000000U)
#define CAAM_CRNR_LS_PKRN_SHIFT (28U)
/*! PKRN
* 0b0000..PKHA-SDv1
* 0b0001..PKHA-SDv2
* 0b0010..PKHA-SDv3
* 0b0011..PKHA-SDv4
*/
#define CAAM_CRNR_LS_PKRN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CRNR_LS_PKRN_SHIFT)) & CAAM_CRNR_LS_PKRN_MASK)
/*! @} */
/*! @name CTPR_MS - Compile Time Parameters Register, most-significant half */
/*! @{ */
#define CAAM_CTPR_MS_VIRT_EN_INCL_MASK (0x1U)
#define CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT (0U)
#define CAAM_CTPR_MS_VIRT_EN_INCL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_INCL_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_INCL_MASK)
#define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK (0x2U)
#define CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT (1U)
#define CAAM_CTPR_MS_VIRT_EN_POR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_VIRT_EN_POR_VALUE_SHIFT)) & CAAM_CTPR_MS_VIRT_EN_POR_VALUE_MASK)
#define CAAM_CTPR_MS_REG_PG_SIZE_MASK (0x10U)
#define CAAM_CTPR_MS_REG_PG_SIZE_SHIFT (4U)
#define CAAM_CTPR_MS_REG_PG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_REG_PG_SIZE_SHIFT)) & CAAM_CTPR_MS_REG_PG_SIZE_MASK)
#define CAAM_CTPR_MS_RNG_I_MASK (0x700U)
#define CAAM_CTPR_MS_RNG_I_SHIFT (8U)
#define CAAM_CTPR_MS_RNG_I(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_RNG_I_SHIFT)) & CAAM_CTPR_MS_RNG_I_MASK)
#define CAAM_CTPR_MS_AI_INCL_MASK (0x800U)
#define CAAM_CTPR_MS_AI_INCL_SHIFT (11U)
#define CAAM_CTPR_MS_AI_INCL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AI_INCL_SHIFT)) & CAAM_CTPR_MS_AI_INCL_MASK)
#define CAAM_CTPR_MS_DPAA2_MASK (0x2000U)
#define CAAM_CTPR_MS_DPAA2_SHIFT (13U)
#define CAAM_CTPR_MS_DPAA2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DPAA2_SHIFT)) & CAAM_CTPR_MS_DPAA2_MASK)
#define CAAM_CTPR_MS_IP_CLK_MASK (0x4000U)
#define CAAM_CTPR_MS_IP_CLK_SHIFT (14U)
#define CAAM_CTPR_MS_IP_CLK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_IP_CLK_SHIFT)) & CAAM_CTPR_MS_IP_CLK_MASK)
#define CAAM_CTPR_MS_MCFG_BURST_MASK (0x10000U)
#define CAAM_CTPR_MS_MCFG_BURST_SHIFT (16U)
#define CAAM_CTPR_MS_MCFG_BURST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_BURST_SHIFT)) & CAAM_CTPR_MS_MCFG_BURST_MASK)
#define CAAM_CTPR_MS_MCFG_PS_MASK (0x20000U)
#define CAAM_CTPR_MS_MCFG_PS_SHIFT (17U)
#define CAAM_CTPR_MS_MCFG_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_MCFG_PS_SHIFT)) & CAAM_CTPR_MS_MCFG_PS_MASK)
#define CAAM_CTPR_MS_SG8_MASK (0x40000U)
#define CAAM_CTPR_MS_SG8_SHIFT (18U)
#define CAAM_CTPR_MS_SG8(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_SG8_SHIFT)) & CAAM_CTPR_MS_SG8_MASK)
#define CAAM_CTPR_MS_PM_EVT_BUS_MASK (0x80000U)
#define CAAM_CTPR_MS_PM_EVT_BUS_SHIFT (19U)
#define CAAM_CTPR_MS_PM_EVT_BUS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PM_EVT_BUS_SHIFT)) & CAAM_CTPR_MS_PM_EVT_BUS_MASK)
#define CAAM_CTPR_MS_DECO_WD_MASK (0x100000U)
#define CAAM_CTPR_MS_DECO_WD_SHIFT (20U)
#define CAAM_CTPR_MS_DECO_WD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_DECO_WD_SHIFT)) & CAAM_CTPR_MS_DECO_WD_MASK)
#define CAAM_CTPR_MS_PC_MASK (0x200000U)
#define CAAM_CTPR_MS_PC_SHIFT (21U)
#define CAAM_CTPR_MS_PC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_PC_SHIFT)) & CAAM_CTPR_MS_PC_MASK)
#define CAAM_CTPR_MS_C1C2_MASK (0x800000U)
#define CAAM_CTPR_MS_C1C2_SHIFT (23U)
#define CAAM_CTPR_MS_C1C2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_C1C2_SHIFT)) & CAAM_CTPR_MS_C1C2_MASK)
#define CAAM_CTPR_MS_ACC_CTL_MASK (0x1000000U)
#define CAAM_CTPR_MS_ACC_CTL_SHIFT (24U)
#define CAAM_CTPR_MS_ACC_CTL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_ACC_CTL_SHIFT)) & CAAM_CTPR_MS_ACC_CTL_MASK)
#define CAAM_CTPR_MS_QI_MASK (0x2000000U)
#define CAAM_CTPR_MS_QI_SHIFT (25U)
#define CAAM_CTPR_MS_QI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_QI_SHIFT)) & CAAM_CTPR_MS_QI_MASK)
#define CAAM_CTPR_MS_AXI_PRI_MASK (0x4000000U)
#define CAAM_CTPR_MS_AXI_PRI_SHIFT (26U)
#define CAAM_CTPR_MS_AXI_PRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PRI_SHIFT)) & CAAM_CTPR_MS_AXI_PRI_MASK)
#define CAAM_CTPR_MS_AXI_LIODN_MASK (0x8000000U)
#define CAAM_CTPR_MS_AXI_LIODN_SHIFT (27U)
#define CAAM_CTPR_MS_AXI_LIODN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_LIODN_SHIFT)) & CAAM_CTPR_MS_AXI_LIODN_MASK)
#define CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK (0xF0000000U)
#define CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT (28U)
#define CAAM_CTPR_MS_AXI_PIPE_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_MS_AXI_PIPE_DEPTH_SHIFT)) & CAAM_CTPR_MS_AXI_PIPE_DEPTH_MASK)
/*! @} */
/*! @name CTPR_LS - Compile Time Parameters Register, least-significant half */
/*! @{ */
#define CAAM_CTPR_LS_KG_DS_MASK (0x1U)
#define CAAM_CTPR_LS_KG_DS_SHIFT (0U)
/*! KG_DS
* 0b0..CAAM does not implement specialized support for Public Key Generation and Digital Signatures.
* 0b1..CAAM implements specialized support for Public Key Generation and Digital Signatures.
*/
#define CAAM_CTPR_LS_KG_DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_KG_DS_SHIFT)) & CAAM_CTPR_LS_KG_DS_MASK)
#define CAAM_CTPR_LS_BLOB_MASK (0x2U)
#define CAAM_CTPR_LS_BLOB_SHIFT (1U)
/*! BLOB
* 0b0..CAAM does not implement specialized support for encapsulating and decapsulating cryptographic blobs.
* 0b1..CAAM implements specialized support for encapsulating and decapsulating cryptographic blobs.
*/
#define CAAM_CTPR_LS_BLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_BLOB_SHIFT)) & CAAM_CTPR_LS_BLOB_MASK)
#define CAAM_CTPR_LS_WIFI_MASK (0x4U)
#define CAAM_CTPR_LS_WIFI_SHIFT (2U)
/*! WIFI
* 0b0..CAAM does not implement specialized support for the WIFI protocol.
* 0b1..CAAM implements specialized support for the WIFI protocol.
*/
#define CAAM_CTPR_LS_WIFI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIFI_SHIFT)) & CAAM_CTPR_LS_WIFI_MASK)
#define CAAM_CTPR_LS_WIMAX_MASK (0x8U)
#define CAAM_CTPR_LS_WIMAX_SHIFT (3U)
/*! WIMAX
* 0b0..CAAM does not implement specialized support for the WIMAX protocol.
* 0b1..CAAM implements specialized support for the WIMAX protocol.
*/
#define CAAM_CTPR_LS_WIMAX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_WIMAX_SHIFT)) & CAAM_CTPR_LS_WIMAX_MASK)
#define CAAM_CTPR_LS_SRTP_MASK (0x10U)
#define CAAM_CTPR_LS_SRTP_SHIFT (4U)
/*! SRTP
* 0b0..CAAM does not implement specialized support for the SRTP protocol.
* 0b1..CAAM implements specialized support for the SRTP protocol.
*/
#define CAAM_CTPR_LS_SRTP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SRTP_SHIFT)) & CAAM_CTPR_LS_SRTP_MASK)
#define CAAM_CTPR_LS_IPSEC_MASK (0x20U)
#define CAAM_CTPR_LS_IPSEC_SHIFT (5U)
/*! IPSEC
* 0b0..CAAM does not implement specialized support for the IPSEC protocol.
* 0b1..CAAM implements specialized support for the IPSEC protocol.
*/
#define CAAM_CTPR_LS_IPSEC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IPSEC_SHIFT)) & CAAM_CTPR_LS_IPSEC_MASK)
#define CAAM_CTPR_LS_IKE_MASK (0x40U)
#define CAAM_CTPR_LS_IKE_SHIFT (6U)
/*! IKE
* 0b0..CAAM does not implement specialized support for the IKE protocol.
* 0b1..CAAM implements specialized support for the IKE protocol.
*/
#define CAAM_CTPR_LS_IKE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_IKE_SHIFT)) & CAAM_CTPR_LS_IKE_MASK)
#define CAAM_CTPR_LS_SSL_TLS_MASK (0x80U)
#define CAAM_CTPR_LS_SSL_TLS_SHIFT (7U)
/*! SSL_TLS
* 0b0..CAAM does not implement specialized support for the SSL and TLS protocols.
* 0b1..CAAM implements specialized support for the SSL and TLS protocols.
*/
#define CAAM_CTPR_LS_SSL_TLS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_SSL_TLS_SHIFT)) & CAAM_CTPR_LS_SSL_TLS_MASK)
#define CAAM_CTPR_LS_TLS_PRF_MASK (0x100U)
#define CAAM_CTPR_LS_TLS_PRF_SHIFT (8U)
/*! TLS_PRF
* 0b0..CAAM does not implement specialized support for the TLS protocol pseudo-random function.
* 0b1..CAAM implements specialized support for the TLS protocol pseudo-random function.
*/
#define CAAM_CTPR_LS_TLS_PRF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_TLS_PRF_SHIFT)) & CAAM_CTPR_LS_TLS_PRF_MASK)
#define CAAM_CTPR_LS_MACSEC_MASK (0x200U)
#define CAAM_CTPR_LS_MACSEC_SHIFT (9U)
/*! MACSEC
* 0b0..CAAM does not implement specialized support for the MACSEC protocol.
* 0b1..CAAM implements specialized support for the MACSEC protocol.
*/
#define CAAM_CTPR_LS_MACSEC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MACSEC_SHIFT)) & CAAM_CTPR_LS_MACSEC_MASK)
#define CAAM_CTPR_LS_RSA_MASK (0x400U)
#define CAAM_CTPR_LS_RSA_SHIFT (10U)
/*! RSA
* 0b0..CAAM does not implement specialized support for RSA encrypt and decrypt operations.
* 0b1..CAAM implements specialized support for RSA encrypt and decrypt operations.
*/
#define CAAM_CTPR_LS_RSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_RSA_SHIFT)) & CAAM_CTPR_LS_RSA_MASK)
#define CAAM_CTPR_LS_P3G_LTE_MASK (0x800U)
#define CAAM_CTPR_LS_P3G_LTE_SHIFT (11U)
/*! P3G_LTE
* 0b0..CAAM does not implement specialized support for 3G and LTE protocols.
* 0b1..CAAM implements specialized support for 3G and LTE protocols.
*/
#define CAAM_CTPR_LS_P3G_LTE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_P3G_LTE_SHIFT)) & CAAM_CTPR_LS_P3G_LTE_MASK)
#define CAAM_CTPR_LS_DBL_CRC_MASK (0x1000U)
#define CAAM_CTPR_LS_DBL_CRC_SHIFT (12U)
/*! DBL_CRC
* 0b0..CAAM does not implement specialized support for Double CRC.
* 0b1..CAAM implements specialized support for Double CRC.
*/
#define CAAM_CTPR_LS_DBL_CRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DBL_CRC_SHIFT)) & CAAM_CTPR_LS_DBL_CRC_MASK)
#define CAAM_CTPR_LS_MAN_PROT_MASK (0x2000U)
#define CAAM_CTPR_LS_MAN_PROT_SHIFT (13U)
/*! MAN_PROT
* 0b0..CAAM does not implement Manufacturing Protection functions.
* 0b1..CAAM implements Manufacturing Protection functions.
*/
#define CAAM_CTPR_LS_MAN_PROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_MAN_PROT_SHIFT)) & CAAM_CTPR_LS_MAN_PROT_MASK)
#define CAAM_CTPR_LS_DKP_MASK (0x4000U)
#define CAAM_CTPR_LS_DKP_SHIFT (14U)
/*! DKP
* 0b0..CAAM does not implement the Derived Key Protocol.
* 0b1..CAAM implements the Derived Key Protocol.
*/
#define CAAM_CTPR_LS_DKP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CTPR_LS_DKP_SHIFT)) & CAAM_CTPR_LS_DKP_MASK)
/*! @} */
/*! @name SMSTA - Secure Memory Status Register */
/*! @{ */
#define CAAM_SMSTA_STATE_MASK (0xFU)
#define CAAM_SMSTA_STATE_SHIFT (0U)
/*! STATE
* 0b0000..Reset State
* 0b0001..Initialize State
* 0b0010..Normal State
* 0b0011..Fail State
*/
#define CAAM_SMSTA_STATE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_STATE_SHIFT)) & CAAM_SMSTA_STATE_MASK)
#define CAAM_SMSTA_ACCERR_MASK (0xF0U)
#define CAAM_SMSTA_ACCERR_SHIFT (4U)
/*! ACCERR
* 0b0000..No error occurred
* 0b0001..A bus transaction attempted to access a page in Secure Memory, but the page was not allocated to any partition.
* 0b0010..A bus transaction attempted to access a partition, but the transaction's TrustZone World, DID was not
* granted access to the partition in the partition's SMAG2/1JR registers.
* 0b0011..A bus transaction attempted to read, but reads from this partition are not allowed.
* 0b0100..A bus transaction attempted to write, but writes to this partition are not allowed.
* 0b0110..A bus transaction attempted a non-key read, but the only reads permitted from this partition are key reads.
* 0b1001..Secure Memory Blob import or export was attempted, but Secure Memory Blob access is not allowed for this partition.
* 0b1010..A Descriptor attempted a Secure Memory Blob import or export, but not all of the pages referenced were from the same partition.
* 0b1011..A memory access was directed to Secure Memory, but the specified address is not implemented in Secure
* Memory. The address was either outside the address range occupied by Secure Memory, or was within an
* unimplemented portion of the 4kbyte address block occupied by a 1Kbyte or 2Kbyte Secure Memory page.
* 0b1100..A bus transaction was attempted, but the burst would have crossed a page boundary.
* 0b1101..An attempt was made to access a page while it was still being initialized.
*/
#define CAAM_SMSTA_ACCERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_ACCERR_SHIFT)) & CAAM_SMSTA_ACCERR_MASK)
#define CAAM_SMSTA_DID_MASK (0xF00U)
#define CAAM_SMSTA_DID_SHIFT (8U)
#define CAAM_SMSTA_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_DID_SHIFT)) & CAAM_SMSTA_DID_MASK)
#define CAAM_SMSTA_NS_MASK (0x1000U)
#define CAAM_SMSTA_NS_SHIFT (12U)
#define CAAM_SMSTA_NS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_NS_SHIFT)) & CAAM_SMSTA_NS_MASK)
#define CAAM_SMSTA_SMR_WP_MASK (0x8000U)
#define CAAM_SMSTA_SMR_WP_SHIFT (15U)
#define CAAM_SMSTA_SMR_WP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_SMR_WP_SHIFT)) & CAAM_SMSTA_SMR_WP_MASK)
#define CAAM_SMSTA_PAGE_MASK (0x7FF0000U)
#define CAAM_SMSTA_PAGE_SHIFT (16U)
#define CAAM_SMSTA_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PAGE_SHIFT)) & CAAM_SMSTA_PAGE_MASK)
#define CAAM_SMSTA_PART_MASK (0xF0000000U)
#define CAAM_SMSTA_PART_SHIFT (28U)
#define CAAM_SMSTA_PART(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMSTA_PART_SHIFT)) & CAAM_SMSTA_PART_MASK)
/*! @} */
/*! @name SMPO - Secure Memory Partition Owners Register */
/*! @{ */
#define CAAM_SMPO_PO0_MASK (0x3U)
#define CAAM_SMPO_PO0_SHIFT (0U)
/*! PO0
* 0b00..Available; Unowned. A Job Ring owner may claim partition 0 by writing to the appropriate SMAPJR register
* address alias. Note that the entire register will return all 0s if read by a entity that does not own
* the Job Ring associated with the SMPO address alias that was read.
* 0b01..Partition 0 does not exist in this version
* 0b10..Another entity owns partition 0. Partition 0 is unavailable to the reader. If the reader attempts to
* de-allocate partition 0 or write to the SMAPJR register or SMAGJR register for partition 0 or allocate a
* page to or de-allocate a page from partition 0 the command will be ignored. (Note that if a CSP partition is
* de-allocated, all entities (including the owner that de-allocated the partition) will see a 0b10 value
* for that partition until all its pages have been zeroized.)
* 0b11..The entity that read the SMPO register owns partition 0. Ownership is claimed when the access
* permissions register (SMAPJR) of an available partition is first written.
*/
#define CAAM_SMPO_PO0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO0_SHIFT)) & CAAM_SMPO_PO0_MASK)
#define CAAM_SMPO_PO1_MASK (0xCU)
#define CAAM_SMPO_PO1_SHIFT (2U)
#define CAAM_SMPO_PO1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO1_SHIFT)) & CAAM_SMPO_PO1_MASK)
#define CAAM_SMPO_PO2_MASK (0x30U)
#define CAAM_SMPO_PO2_SHIFT (4U)
#define CAAM_SMPO_PO2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO2_SHIFT)) & CAAM_SMPO_PO2_MASK)
#define CAAM_SMPO_PO3_MASK (0xC0U)
#define CAAM_SMPO_PO3_SHIFT (6U)
#define CAAM_SMPO_PO3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO3_SHIFT)) & CAAM_SMPO_PO3_MASK)
#define CAAM_SMPO_PO4_MASK (0x300U)
#define CAAM_SMPO_PO4_SHIFT (8U)
#define CAAM_SMPO_PO4(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO4_SHIFT)) & CAAM_SMPO_PO4_MASK)
#define CAAM_SMPO_PO5_MASK (0xC00U)
#define CAAM_SMPO_PO5_SHIFT (10U)
#define CAAM_SMPO_PO5(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO5_SHIFT)) & CAAM_SMPO_PO5_MASK)
#define CAAM_SMPO_PO6_MASK (0x3000U)
#define CAAM_SMPO_PO6_SHIFT (12U)
#define CAAM_SMPO_PO6(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO6_SHIFT)) & CAAM_SMPO_PO6_MASK)
#define CAAM_SMPO_PO7_MASK (0xC000U)
#define CAAM_SMPO_PO7_SHIFT (14U)
#define CAAM_SMPO_PO7(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO7_SHIFT)) & CAAM_SMPO_PO7_MASK)
#define CAAM_SMPO_PO8_MASK (0x30000U)
#define CAAM_SMPO_PO8_SHIFT (16U)
#define CAAM_SMPO_PO8(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO8_SHIFT)) & CAAM_SMPO_PO8_MASK)
#define CAAM_SMPO_PO9_MASK (0xC0000U)
#define CAAM_SMPO_PO9_SHIFT (18U)
#define CAAM_SMPO_PO9(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO9_SHIFT)) & CAAM_SMPO_PO9_MASK)
#define CAAM_SMPO_PO10_MASK (0x300000U)
#define CAAM_SMPO_PO10_SHIFT (20U)
#define CAAM_SMPO_PO10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO10_SHIFT)) & CAAM_SMPO_PO10_MASK)
#define CAAM_SMPO_PO11_MASK (0xC00000U)
#define CAAM_SMPO_PO11_SHIFT (22U)
#define CAAM_SMPO_PO11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO11_SHIFT)) & CAAM_SMPO_PO11_MASK)
#define CAAM_SMPO_PO12_MASK (0x3000000U)
#define CAAM_SMPO_PO12_SHIFT (24U)
#define CAAM_SMPO_PO12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO12_SHIFT)) & CAAM_SMPO_PO12_MASK)
#define CAAM_SMPO_PO13_MASK (0xC000000U)
#define CAAM_SMPO_PO13_SHIFT (26U)
#define CAAM_SMPO_PO13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO13_SHIFT)) & CAAM_SMPO_PO13_MASK)
#define CAAM_SMPO_PO14_MASK (0x30000000U)
#define CAAM_SMPO_PO14_SHIFT (28U)
#define CAAM_SMPO_PO14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO14_SHIFT)) & CAAM_SMPO_PO14_MASK)
#define CAAM_SMPO_PO15_MASK (0xC0000000U)
#define CAAM_SMPO_PO15_SHIFT (30U)
#define CAAM_SMPO_PO15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMPO_PO15_SHIFT)) & CAAM_SMPO_PO15_MASK)
/*! @} */
/*! @name FAR - Fault Address Register */
/*! @{ */
#define CAAM_FAR_FAR_MASK (0xFFFFFFFFFU)
#define CAAM_FAR_FAR_SHIFT (0U)
#define CAAM_FAR_FAR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_FAR_FAR_SHIFT)) & CAAM_FAR_FAR_MASK)
/*! @} */
/*! @name FADID - Fault Address DID Register */
/*! @{ */
#define CAAM_FADID_FDID_MASK (0xFU)
#define CAAM_FADID_FDID_SHIFT (0U)
#define CAAM_FADID_FDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FDID_SHIFT)) & CAAM_FADID_FDID_MASK)
#define CAAM_FADID_FNS_MASK (0x10U)
#define CAAM_FADID_FNS_SHIFT (4U)
#define CAAM_FADID_FNS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FNS_SHIFT)) & CAAM_FADID_FNS_MASK)
#define CAAM_FADID_FICID_MASK (0xFFE0U)
#define CAAM_FADID_FICID_SHIFT (5U)
#define CAAM_FADID_FICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADID_FICID_SHIFT)) & CAAM_FADID_FICID_MASK)
/*! @} */
/*! @name FADR - Fault Address Detail Register */
/*! @{ */
#define CAAM_FADR_FSZ_MASK (0x7FU)
#define CAAM_FADR_FSZ_SHIFT (0U)
#define CAAM_FADR_FSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_SHIFT)) & CAAM_FADR_FSZ_MASK)
#define CAAM_FADR_TYP_MASK (0x80U)
#define CAAM_FADR_TYP_SHIFT (7U)
/*! TYP
* 0b0..Read.
* 0b1..Write.
*/
#define CAAM_FADR_TYP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_TYP_SHIFT)) & CAAM_FADR_TYP_MASK)
#define CAAM_FADR_BLKID_MASK (0xF00U)
#define CAAM_FADR_BLKID_SHIFT (8U)
/*! BLKID
* 0b0100..job queue controller Burst Buffer
* 0b0101..One of the Job Rings (see JSRC field)
* 0b1000..DECO0
*/
#define CAAM_FADR_BLKID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_BLKID_SHIFT)) & CAAM_FADR_BLKID_MASK)
#define CAAM_FADR_JSRC_MASK (0x7000U)
#define CAAM_FADR_JSRC_SHIFT (12U)
/*! JSRC
* 0b000..Job Ring 0
* 0b001..Job Ring 1
* 0b010..Job Ring 2
* 0b011..Job Ring 3
* 0b100..RTIC
* 0b101..reserved
* 0b110..reserved
* 0b111..reserved
*/
#define CAAM_FADR_JSRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_JSRC_SHIFT)) & CAAM_FADR_JSRC_MASK)
#define CAAM_FADR_DTYP_MASK (0x8000U)
#define CAAM_FADR_DTYP_SHIFT (15U)
/*! DTYP
* 0b0..message data
* 0b1..control data
*/
#define CAAM_FADR_DTYP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_DTYP_SHIFT)) & CAAM_FADR_DTYP_MASK)
#define CAAM_FADR_FSZ_EXT_MASK (0x70000U)
#define CAAM_FADR_FSZ_EXT_SHIFT (16U)
#define CAAM_FADR_FSZ_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FSZ_EXT_SHIFT)) & CAAM_FADR_FSZ_EXT_MASK)
#define CAAM_FADR_FKMOD_MASK (0x1000000U)
#define CAAM_FADR_FKMOD_SHIFT (24U)
/*! FKMOD
* 0b0..CAAM DMA was not attempting to read the key modifier from Secure Memory at the time that the DMA error occurred.
* 0b1..CAAM DMA was attempting to read the key modifier from Secure Memory at the time that the DMA error occurred.
*/
#define CAAM_FADR_FKMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKMOD_SHIFT)) & CAAM_FADR_FKMOD_MASK)
#define CAAM_FADR_FKEY_MASK (0x2000000U)
#define CAAM_FADR_FKEY_SHIFT (25U)
/*! FKEY
* 0b0..CAAM DMA was not attempting to perform a key read from Secure Memory at the time of the DMA error.
* 0b1..CAAM DMA was attempting to perform a key read from Secure Memory at the time of the DMA error.
*/
#define CAAM_FADR_FKEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FKEY_SHIFT)) & CAAM_FADR_FKEY_MASK)
#define CAAM_FADR_FTDSC_MASK (0x4000000U)
#define CAAM_FADR_FTDSC_SHIFT (26U)
/*! FTDSC
* 0b0..CAAM DMA was not executing a Trusted Descriptor at the time of the DMA error.
* 0b1..CAAM DMA was executing a Trusted Descriptor at the time of the DMA error.
*/
#define CAAM_FADR_FTDSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FTDSC_SHIFT)) & CAAM_FADR_FTDSC_MASK)
#define CAAM_FADR_FBNDG_MASK (0x8000000U)
#define CAAM_FADR_FBNDG_SHIFT (27U)
/*! FBNDG
* 0b0..CAAM DMA was not reading access permissions from a Secure Memory partition at the time of the DMA error.
* 0b1..CAAM DMA was reading access permissions from a Secure Memory partition at the time of the DMA error.
*/
#define CAAM_FADR_FBNDG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FBNDG_SHIFT)) & CAAM_FADR_FBNDG_MASK)
#define CAAM_FADR_FNS_MASK (0x10000000U)
#define CAAM_FADR_FNS_SHIFT (28U)
/*! FNS
* 0b0..CAAM DMA was asserting ns=0 at the time of the DMA error.
* 0b1..CAAM DMA was asserting ns=1 at the time of the DMA error.
*/
#define CAAM_FADR_FNS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FNS_SHIFT)) & CAAM_FADR_FNS_MASK)
#define CAAM_FADR_FERR_MASK (0xC0000000U)
#define CAAM_FADR_FERR_SHIFT (30U)
/*! FERR
* 0b00..OKAY - Normal Access
* 0b01..Reserved
* 0b10..SLVERR - Slave Error
* 0b11..DECERR - Decode Error
*/
#define CAAM_FADR_FERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_FADR_FERR_SHIFT)) & CAAM_FADR_FERR_MASK)
/*! @} */
/*! @name CSTA - CAAM Status Register */
/*! @{ */
#define CAAM_CSTA_BSY_MASK (0x1U)
#define CAAM_CSTA_BSY_SHIFT (0U)
#define CAAM_CSTA_BSY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_BSY_SHIFT)) & CAAM_CSTA_BSY_MASK)
#define CAAM_CSTA_IDLE_MASK (0x2U)
#define CAAM_CSTA_IDLE_SHIFT (1U)
#define CAAM_CSTA_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_IDLE_SHIFT)) & CAAM_CSTA_IDLE_MASK)
#define CAAM_CSTA_TRNG_IDLE_MASK (0x4U)
#define CAAM_CSTA_TRNG_IDLE_SHIFT (2U)
#define CAAM_CSTA_TRNG_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_TRNG_IDLE_SHIFT)) & CAAM_CSTA_TRNG_IDLE_MASK)
#define CAAM_CSTA_MOO_MASK (0x300U)
#define CAAM_CSTA_MOO_SHIFT (8U)
/*! MOO
* 0b00..Non-Secure
* 0b01..Secure
* 0b10..Trusted
* 0b11..Fail
*/
#define CAAM_CSTA_MOO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_MOO_SHIFT)) & CAAM_CSTA_MOO_MASK)
#define CAAM_CSTA_PLEND_MASK (0x400U)
#define CAAM_CSTA_PLEND_SHIFT (10U)
/*! PLEND
* 0b0..Platform default is Little Endian
* 0b1..Platform default is Big Endian
*/
#define CAAM_CSTA_PLEND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CSTA_PLEND_SHIFT)) & CAAM_CSTA_PLEND_MASK)
/*! @} */
/*! @name SMVID_MS - Secure Memory Version ID Register, most-significant half */
/*! @{ */
#define CAAM_SMVID_MS_NPAG_MASK (0x3FFU)
#define CAAM_SMVID_MS_NPAG_SHIFT (0U)
#define CAAM_SMVID_MS_NPAG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPAG_SHIFT)) & CAAM_SMVID_MS_NPAG_MASK)
#define CAAM_SMVID_MS_NPRT_MASK (0xF000U)
#define CAAM_SMVID_MS_NPRT_SHIFT (12U)
#define CAAM_SMVID_MS_NPRT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_NPRT_SHIFT)) & CAAM_SMVID_MS_NPRT_MASK)
#define CAAM_SMVID_MS_MAX_NPAG_MASK (0x3FF0000U)
#define CAAM_SMVID_MS_MAX_NPAG_SHIFT (16U)
#define CAAM_SMVID_MS_MAX_NPAG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_MS_MAX_NPAG_SHIFT)) & CAAM_SMVID_MS_MAX_NPAG_MASK)
/*! @} */
/*! @name SMVID_LS - Secure Memory Version ID Register, least-significant half */
/*! @{ */
#define CAAM_SMVID_LS_SMNV_MASK (0xFFU)
#define CAAM_SMVID_LS_SMNV_SHIFT (0U)
#define CAAM_SMVID_LS_SMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMNV_SHIFT)) & CAAM_SMVID_LS_SMNV_MASK)
#define CAAM_SMVID_LS_SMJV_MASK (0xFF00U)
#define CAAM_SMVID_LS_SMJV_SHIFT (8U)
#define CAAM_SMVID_LS_SMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_SMJV_SHIFT)) & CAAM_SMVID_LS_SMJV_MASK)
#define CAAM_SMVID_LS_PSIZ_MASK (0x70000U)
#define CAAM_SMVID_LS_PSIZ_SHIFT (16U)
#define CAAM_SMVID_LS_PSIZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMVID_LS_PSIZ_SHIFT)) & CAAM_SMVID_LS_PSIZ_MASK)
/*! @} */
/*! @name RVID - RTIC Version ID Register */
/*! @{ */
#define CAAM_RVID_RMNV_MASK (0xFFU)
#define CAAM_RVID_RMNV_SHIFT (0U)
#define CAAM_RVID_RMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMNV_SHIFT)) & CAAM_RVID_RMNV_MASK)
#define CAAM_RVID_RMJV_MASK (0xFF00U)
#define CAAM_RVID_RMJV_SHIFT (8U)
#define CAAM_RVID_RMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_RMJV_SHIFT)) & CAAM_RVID_RMJV_MASK)
#define CAAM_RVID_SHA_256_MASK (0x20000U)
#define CAAM_RVID_SHA_256_SHIFT (17U)
/*! SHA_256
* 0b0..RTIC cannot use the SHA-256 hashing algorithm.
* 0b1..RTIC can use the SHA-256 hashing algorithm.
*/
#define CAAM_RVID_SHA_256(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_256_SHIFT)) & CAAM_RVID_SHA_256_MASK)
#define CAAM_RVID_SHA_512_MASK (0x80000U)
#define CAAM_RVID_SHA_512_SHIFT (19U)
/*! SHA_512
* 0b0..RTIC cannot use the SHA-512 hashing algorithm.
* 0b1..RTIC can use the SHA-512 hashing algorithm.
*/
#define CAAM_RVID_SHA_512(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_SHA_512_SHIFT)) & CAAM_RVID_SHA_512_MASK)
#define CAAM_RVID_MA_MASK (0x1000000U)
#define CAAM_RVID_MA_SHIFT (24U)
#define CAAM_RVID_MA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MA_SHIFT)) & CAAM_RVID_MA_MASK)
#define CAAM_RVID_MB_MASK (0x2000000U)
#define CAAM_RVID_MB_SHIFT (25U)
#define CAAM_RVID_MB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MB_SHIFT)) & CAAM_RVID_MB_MASK)
#define CAAM_RVID_MC_MASK (0x4000000U)
#define CAAM_RVID_MC_SHIFT (26U)
#define CAAM_RVID_MC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MC_SHIFT)) & CAAM_RVID_MC_MASK)
#define CAAM_RVID_MD_MASK (0x8000000U)
#define CAAM_RVID_MD_SHIFT (27U)
#define CAAM_RVID_MD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RVID_MD_SHIFT)) & CAAM_RVID_MD_MASK)
/*! @} */
/*! @name CCBVID - CHA Cluster Block Version ID Register */
/*! @{ */
#define CAAM_CCBVID_AMNV_MASK (0xFFU)
#define CAAM_CCBVID_AMNV_SHIFT (0U)
#define CAAM_CCBVID_AMNV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMNV_SHIFT)) & CAAM_CCBVID_AMNV_MASK)
#define CAAM_CCBVID_AMJV_MASK (0xFF00U)
#define CAAM_CCBVID_AMJV_SHIFT (8U)
#define CAAM_CCBVID_AMJV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_AMJV_SHIFT)) & CAAM_CCBVID_AMJV_MASK)
#define CAAM_CCBVID_CAAM_ERA_MASK (0xFF000000U)
#define CAAM_CCBVID_CAAM_ERA_SHIFT (24U)
#define CAAM_CCBVID_CAAM_ERA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCBVID_CAAM_ERA_SHIFT)) & CAAM_CCBVID_CAAM_ERA_MASK)
/*! @} */
/*! @name CHAVID_MS - CHA Version ID Register, most-significant half */
/*! @{ */
#define CAAM_CHAVID_MS_CRCVID_MASK (0xFU)
#define CAAM_CHAVID_MS_CRCVID_SHIFT (0U)
#define CAAM_CHAVID_MS_CRCVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_CRCVID_SHIFT)) & CAAM_CHAVID_MS_CRCVID_MASK)
#define CAAM_CHAVID_MS_SNW9VID_MASK (0xF0U)
#define CAAM_CHAVID_MS_SNW9VID_SHIFT (4U)
#define CAAM_CHAVID_MS_SNW9VID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_SNW9VID_SHIFT)) & CAAM_CHAVID_MS_SNW9VID_MASK)
#define CAAM_CHAVID_MS_ZEVID_MASK (0xF00U)
#define CAAM_CHAVID_MS_ZEVID_SHIFT (8U)
#define CAAM_CHAVID_MS_ZEVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZEVID_SHIFT)) & CAAM_CHAVID_MS_ZEVID_MASK)
#define CAAM_CHAVID_MS_ZAVID_MASK (0xF000U)
#define CAAM_CHAVID_MS_ZAVID_SHIFT (12U)
#define CAAM_CHAVID_MS_ZAVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_ZAVID_SHIFT)) & CAAM_CHAVID_MS_ZAVID_MASK)
#define CAAM_CHAVID_MS_DECOVID_MASK (0xF000000U)
#define CAAM_CHAVID_MS_DECOVID_SHIFT (24U)
#define CAAM_CHAVID_MS_DECOVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_DECOVID_SHIFT)) & CAAM_CHAVID_MS_DECOVID_MASK)
#define CAAM_CHAVID_MS_JRVID_MASK (0xF0000000U)
#define CAAM_CHAVID_MS_JRVID_SHIFT (28U)
#define CAAM_CHAVID_MS_JRVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_MS_JRVID_SHIFT)) & CAAM_CHAVID_MS_JRVID_MASK)
/*! @} */
/*! @name CHAVID_LS - CHA Version ID Register, least-significant half */
/*! @{ */
#define CAAM_CHAVID_LS_AESVID_MASK (0xFU)
#define CAAM_CHAVID_LS_AESVID_SHIFT (0U)
/*! AESVID
* 0b0100..High-performance AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, CBCXCBC, CTRXCBC, XTS, and GCM modes
* 0b0011..Low-power AESA, implementing ECB, CBC, CBC-CS2, CFB128, OFB, CTR, CCM, CMAC, XCBC-MAC, and GCM modes
*/
#define CAAM_CHAVID_LS_AESVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_AESVID_SHIFT)) & CAAM_CHAVID_LS_AESVID_MASK)
#define CAAM_CHAVID_LS_DESVID_MASK (0xF0U)
#define CAAM_CHAVID_LS_DESVID_SHIFT (4U)
#define CAAM_CHAVID_LS_DESVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_DESVID_SHIFT)) & CAAM_CHAVID_LS_DESVID_MASK)
#define CAAM_CHAVID_LS_MDVID_MASK (0xF000U)
#define CAAM_CHAVID_LS_MDVID_SHIFT (12U)
/*! MDVID
* 0b0000..Low-power MDHA, with SHA-1, SHA-256, SHA 224, MD5 and HMAC
* 0b0001..Low-power MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5 and HMAC
* 0b0010..Medium-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC
* 0b0011..High-performance MDHA, with SHA-1, SHA-256, SHA 224, SHA-512, SHA-512/224, SHA-512/256, SHA-384, MD5, HMAC & SMAC
*/
#define CAAM_CHAVID_LS_MDVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_MDVID_SHIFT)) & CAAM_CHAVID_LS_MDVID_MASK)
#define CAAM_CHAVID_LS_RNGVID_MASK (0xF0000U)
#define CAAM_CHAVID_LS_RNGVID_SHIFT (16U)
/*! RNGVID
* 0b0010..RNGB
* 0b0100..RNG4
*/
#define CAAM_CHAVID_LS_RNGVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_RNGVID_SHIFT)) & CAAM_CHAVID_LS_RNGVID_MASK)
#define CAAM_CHAVID_LS_SNW8VID_MASK (0xF00000U)
#define CAAM_CHAVID_LS_SNW8VID_SHIFT (20U)
#define CAAM_CHAVID_LS_SNW8VID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_SNW8VID_SHIFT)) & CAAM_CHAVID_LS_SNW8VID_MASK)
#define CAAM_CHAVID_LS_KASVID_MASK (0xF000000U)
#define CAAM_CHAVID_LS_KASVID_SHIFT (24U)
#define CAAM_CHAVID_LS_KASVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_KASVID_SHIFT)) & CAAM_CHAVID_LS_KASVID_MASK)
#define CAAM_CHAVID_LS_PKVID_MASK (0xF0000000U)
#define CAAM_CHAVID_LS_PKVID_SHIFT (28U)
/*! PKVID
* 0b0000..PKHA-XT (32-bit); minimum modulus five bytes
* 0b0001..PKHA-SD (32-bit)
* 0b0010..PKHA-SD (64-bit)
* 0b0011..PKHA-SD (128-bit)
*/
#define CAAM_CHAVID_LS_PKVID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHAVID_LS_PKVID_SHIFT)) & CAAM_CHAVID_LS_PKVID_MASK)
/*! @} */
/*! @name CHANUM_MS - CHA Number Register, most-significant half */
/*! @{ */
#define CAAM_CHANUM_MS_CRCNUM_MASK (0xFU)
#define CAAM_CHANUM_MS_CRCNUM_SHIFT (0U)
#define CAAM_CHANUM_MS_CRCNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_CRCNUM_SHIFT)) & CAAM_CHANUM_MS_CRCNUM_MASK)
#define CAAM_CHANUM_MS_SNW9NUM_MASK (0xF0U)
#define CAAM_CHANUM_MS_SNW9NUM_SHIFT (4U)
#define CAAM_CHANUM_MS_SNW9NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_SNW9NUM_SHIFT)) & CAAM_CHANUM_MS_SNW9NUM_MASK)
#define CAAM_CHANUM_MS_ZENUM_MASK (0xF00U)
#define CAAM_CHANUM_MS_ZENUM_SHIFT (8U)
#define CAAM_CHANUM_MS_ZENUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZENUM_SHIFT)) & CAAM_CHANUM_MS_ZENUM_MASK)
#define CAAM_CHANUM_MS_ZANUM_MASK (0xF000U)
#define CAAM_CHANUM_MS_ZANUM_SHIFT (12U)
#define CAAM_CHANUM_MS_ZANUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_ZANUM_SHIFT)) & CAAM_CHANUM_MS_ZANUM_MASK)
#define CAAM_CHANUM_MS_DECONUM_MASK (0xF000000U)
#define CAAM_CHANUM_MS_DECONUM_SHIFT (24U)
#define CAAM_CHANUM_MS_DECONUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_DECONUM_SHIFT)) & CAAM_CHANUM_MS_DECONUM_MASK)
#define CAAM_CHANUM_MS_JRNUM_MASK (0xF0000000U)
#define CAAM_CHANUM_MS_JRNUM_SHIFT (28U)
#define CAAM_CHANUM_MS_JRNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_MS_JRNUM_SHIFT)) & CAAM_CHANUM_MS_JRNUM_MASK)
/*! @} */
/*! @name CHANUM_LS - CHA Number Register, least-significant half */
/*! @{ */
#define CAAM_CHANUM_LS_AESNUM_MASK (0xFU)
#define CAAM_CHANUM_LS_AESNUM_SHIFT (0U)
#define CAAM_CHANUM_LS_AESNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_AESNUM_SHIFT)) & CAAM_CHANUM_LS_AESNUM_MASK)
#define CAAM_CHANUM_LS_DESNUM_MASK (0xF0U)
#define CAAM_CHANUM_LS_DESNUM_SHIFT (4U)
#define CAAM_CHANUM_LS_DESNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_DESNUM_SHIFT)) & CAAM_CHANUM_LS_DESNUM_MASK)
#define CAAM_CHANUM_LS_ARC4NUM_MASK (0xF00U)
#define CAAM_CHANUM_LS_ARC4NUM_SHIFT (8U)
#define CAAM_CHANUM_LS_ARC4NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_ARC4NUM_SHIFT)) & CAAM_CHANUM_LS_ARC4NUM_MASK)
#define CAAM_CHANUM_LS_MDNUM_MASK (0xF000U)
#define CAAM_CHANUM_LS_MDNUM_SHIFT (12U)
#define CAAM_CHANUM_LS_MDNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_MDNUM_SHIFT)) & CAAM_CHANUM_LS_MDNUM_MASK)
#define CAAM_CHANUM_LS_RNGNUM_MASK (0xF0000U)
#define CAAM_CHANUM_LS_RNGNUM_SHIFT (16U)
#define CAAM_CHANUM_LS_RNGNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_RNGNUM_SHIFT)) & CAAM_CHANUM_LS_RNGNUM_MASK)
#define CAAM_CHANUM_LS_SNW8NUM_MASK (0xF00000U)
#define CAAM_CHANUM_LS_SNW8NUM_SHIFT (20U)
#define CAAM_CHANUM_LS_SNW8NUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_SNW8NUM_SHIFT)) & CAAM_CHANUM_LS_SNW8NUM_MASK)
#define CAAM_CHANUM_LS_KASNUM_MASK (0xF000000U)
#define CAAM_CHANUM_LS_KASNUM_SHIFT (24U)
#define CAAM_CHANUM_LS_KASNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_KASNUM_SHIFT)) & CAAM_CHANUM_LS_KASNUM_MASK)
#define CAAM_CHANUM_LS_PKNUM_MASK (0xF0000000U)
#define CAAM_CHANUM_LS_PKNUM_SHIFT (28U)
#define CAAM_CHANUM_LS_PKNUM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CHANUM_LS_PKNUM_SHIFT)) & CAAM_CHANUM_LS_PKNUM_MASK)
/*! @} */
/*! @name IRBAR_JR - Input Ring Base Address Register for Job Ring 0..Input Ring Base Address Register for Job Ring 3 */
/*! @{ */
#define CAAM_IRBAR_JR_IRBA_MASK (0xFFFFFFFFFU)
#define CAAM_IRBAR_JR_IRBA_SHIFT (0U)
#define CAAM_IRBAR_JR_IRBA(x) (((uint64_t)(((uint64_t)(x)) << CAAM_IRBAR_JR_IRBA_SHIFT)) & CAAM_IRBAR_JR_IRBA_MASK)
/*! @} */
/* The count of CAAM_IRBAR_JR */
#define CAAM_IRBAR_JR_COUNT (4U)
/*! @name IRSR_JR - Input Ring Size Register for Job Ring 0..Input Ring Size Register for Job Ring 3 */
/*! @{ */
#define CAAM_IRSR_JR_IRS_MASK (0x3FFU)
#define CAAM_IRSR_JR_IRS_SHIFT (0U)
#define CAAM_IRSR_JR_IRS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRSR_JR_IRS_SHIFT)) & CAAM_IRSR_JR_IRS_MASK)
/*! @} */
/* The count of CAAM_IRSR_JR */
#define CAAM_IRSR_JR_COUNT (4U)
/*! @name IRSAR_JR - Input Ring Slots Available Register for Job Ring 0..Input Ring Slots Available Register for Job Ring 3 */
/*! @{ */
#define CAAM_IRSAR_JR_IRSA_MASK (0x3FFU)
#define CAAM_IRSAR_JR_IRSA_SHIFT (0U)
#define CAAM_IRSAR_JR_IRSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRSAR_JR_IRSA_SHIFT)) & CAAM_IRSAR_JR_IRSA_MASK)
/*! @} */
/* The count of CAAM_IRSAR_JR */
#define CAAM_IRSAR_JR_COUNT (4U)
/*! @name IRJAR_JR - Input Ring Jobs Added Register for Job Ring0..Input Ring Jobs Added Register for Job Ring3 */
/*! @{ */
#define CAAM_IRJAR_JR_IRJA_MASK (0x3FFU)
#define CAAM_IRJAR_JR_IRJA_SHIFT (0U)
#define CAAM_IRJAR_JR_IRJA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRJAR_JR_IRJA_SHIFT)) & CAAM_IRJAR_JR_IRJA_MASK)
/*! @} */
/* The count of CAAM_IRJAR_JR */
#define CAAM_IRJAR_JR_COUNT (4U)
/*! @name ORBAR_JR - Output Ring Base Address Register for Job Ring 0..Output Ring Base Address Register for Job Ring 3 */
/*! @{ */
#define CAAM_ORBAR_JR_ORBA_MASK (0xFFFFFFFFFU)
#define CAAM_ORBAR_JR_ORBA_SHIFT (0U)
#define CAAM_ORBAR_JR_ORBA(x) (((uint64_t)(((uint64_t)(x)) << CAAM_ORBAR_JR_ORBA_SHIFT)) & CAAM_ORBAR_JR_ORBA_MASK)
/*! @} */
/* The count of CAAM_ORBAR_JR */
#define CAAM_ORBAR_JR_COUNT (4U)
/*! @name ORSR_JR - Output Ring Size Register for Job Ring 0..Output Ring Size Register for Job Ring 3 */
/*! @{ */
#define CAAM_ORSR_JR_ORS_MASK (0x3FFU)
#define CAAM_ORSR_JR_ORS_SHIFT (0U)
#define CAAM_ORSR_JR_ORS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORSR_JR_ORS_SHIFT)) & CAAM_ORSR_JR_ORS_MASK)
/*! @} */
/* The count of CAAM_ORSR_JR */
#define CAAM_ORSR_JR_COUNT (4U)
/*! @name ORJRR_JR - Output Ring Jobs Removed Register for Job Ring 0..Output Ring Jobs Removed Register for Job Ring 3 */
/*! @{ */
#define CAAM_ORJRR_JR_ORJR_MASK (0x3FFU)
#define CAAM_ORJRR_JR_ORJR_SHIFT (0U)
#define CAAM_ORJRR_JR_ORJR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORJRR_JR_ORJR_SHIFT)) & CAAM_ORJRR_JR_ORJR_MASK)
/*! @} */
/* The count of CAAM_ORJRR_JR */
#define CAAM_ORJRR_JR_COUNT (4U)
/*! @name ORSFR_JR - Output Ring Slots Full Register for Job Ring 0..Output Ring Slots Full Register for Job Ring 3 */
/*! @{ */
#define CAAM_ORSFR_JR_ORSF_MASK (0x3FFU)
#define CAAM_ORSFR_JR_ORSF_SHIFT (0U)
#define CAAM_ORSFR_JR_ORSF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORSFR_JR_ORSF_SHIFT)) & CAAM_ORSFR_JR_ORSF_MASK)
/*! @} */
/* The count of CAAM_ORSFR_JR */
#define CAAM_ORSFR_JR_COUNT (4U)
/*! @name JRSTAR_JR - Job Ring Output Status Register for Job Ring 0..Job Ring Output Status Register for Job Ring 3 */
/*! @{ */
#define CAAM_JRSTAR_JR_SSED_MASK (0xFFFFFFFU)
#define CAAM_JRSTAR_JR_SSED_SHIFT (0U)
#define CAAM_JRSTAR_JR_SSED(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSED_SHIFT)) & CAAM_JRSTAR_JR_SSED_MASK)
#define CAAM_JRSTAR_JR_SSRC_MASK (0xF0000000U)
#define CAAM_JRSTAR_JR_SSRC_SHIFT (28U)
/*! SSRC
* 0b0000..No Status Source (No Error or Status Reported)
* 0b0001..Reserved
* 0b0010..CCB Status Source (CCB Error Reported)
* 0b0011..Jump Halt User Status Source (User-Provided Status Reported)
* 0b0100..DECO Status Source (DECO Error Reported)
* 0b0101..Reserved
* 0b0110..Job Ring Status Source (Job Ring Error Reported)
* 0b0111..Jump Halt Condition Codes (Condition Code Status Reported)
*/
#define CAAM_JRSTAR_JR_SSRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRSTAR_JR_SSRC_SHIFT)) & CAAM_JRSTAR_JR_SSRC_MASK)
/*! @} */
/* The count of CAAM_JRSTAR_JR */
#define CAAM_JRSTAR_JR_COUNT (4U)
/*! @name JRINTR_JR - Job Ring Interrupt Status Register for Job Ring 0..Job Ring Interrupt Status Register for Job Ring 3 */
/*! @{ */
#define CAAM_JRINTR_JR_JRI_MASK (0x1U)
#define CAAM_JRINTR_JR_JRI_SHIFT (0U)
#define CAAM_JRINTR_JR_JRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRI_SHIFT)) & CAAM_JRINTR_JR_JRI_MASK)
#define CAAM_JRINTR_JR_JRE_MASK (0x2U)
#define CAAM_JRINTR_JR_JRE_SHIFT (1U)
#define CAAM_JRINTR_JR_JRE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_JRE_SHIFT)) & CAAM_JRINTR_JR_JRE_MASK)
#define CAAM_JRINTR_JR_HALT_MASK (0xCU)
#define CAAM_JRINTR_JR_HALT_SHIFT (2U)
#define CAAM_JRINTR_JR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_HALT_SHIFT)) & CAAM_JRINTR_JR_HALT_MASK)
#define CAAM_JRINTR_JR_ENTER_FAIL_MASK (0x10U)
#define CAAM_JRINTR_JR_ENTER_FAIL_SHIFT (4U)
#define CAAM_JRINTR_JR_ENTER_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ENTER_FAIL_SHIFT)) & CAAM_JRINTR_JR_ENTER_FAIL_MASK)
#define CAAM_JRINTR_JR_EXIT_FAIL_MASK (0x20U)
#define CAAM_JRINTR_JR_EXIT_FAIL_SHIFT (5U)
#define CAAM_JRINTR_JR_EXIT_FAIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_EXIT_FAIL_SHIFT)) & CAAM_JRINTR_JR_EXIT_FAIL_MASK)
#define CAAM_JRINTR_JR_ERR_TYPE_MASK (0x1F00U)
#define CAAM_JRINTR_JR_ERR_TYPE_SHIFT (8U)
/*! ERR_TYPE
* 0b00001..Error writing status to Output Ring
* 0b00011..Bad input ring base address (not on a 4-byte boundary).
* 0b00100..Bad output ring base address (not on a 4-byte boundary).
* 0b00101..Invalid write to Input Ring Base Address Register or Input Ring Size Register. Can be written when
* there are no jobs in the input ring or when the Job Ring is halted. These are fatal and will likely
* result in not being able to get all jobs out into the output ring for processing by software. Resetting
* the job ring will almost certainly be necessary.
* 0b00110..Invalid write to Output Ring Base Address Register or Output Ring Size Register. Can be written when
* there are no jobs in the output ring and no jobs from this queue are already processing in CAAM (in
* the holding tanks or DECOs), or when the Job Ring is halted.
* 0b00111..Job Ring reset released before Job Ring is halted.
* 0b01000..Removed too many jobs (ORJRR larger than ORSFR).
* 0b01001..Added too many jobs (IRJAR larger than IRSAR).
* 0b01010..Writing ORSF > ORS In these error cases the write is ignored, the interrupt is asserted (unless
* masked) and the error bit and error_type fields are set in the Job Ring Interrupt Status Register.
* 0b01011..Writing IRSA > IRS
* 0b01100..Writing ORWI > ORS in bytes
* 0b01101..Writing IRRI > IRS in bytes
* 0b01110..Writing IRSA when ring is active
* 0b01111..Writing IRRI when ring is active
* 0b10000..Writing ORSF when ring is active
* 0b10001..Writing ORWI when ring is active
*/
#define CAAM_JRINTR_JR_ERR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_TYPE_SHIFT)) & CAAM_JRINTR_JR_ERR_TYPE_MASK)
#define CAAM_JRINTR_JR_ERR_ORWI_MASK (0x3FFF0000U)
#define CAAM_JRINTR_JR_ERR_ORWI_SHIFT (16U)
#define CAAM_JRINTR_JR_ERR_ORWI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRINTR_JR_ERR_ORWI_SHIFT)) & CAAM_JRINTR_JR_ERR_ORWI_MASK)
/*! @} */
/* The count of CAAM_JRINTR_JR */
#define CAAM_JRINTR_JR_COUNT (4U)
/*! @name JRCFGR_JR_MS - Job Ring Configuration Register for Job Ring 0, most-significant half..Job Ring Configuration Register for Job Ring 3, most-significant half */
/*! @{ */
#define CAAM_JRCFGR_JR_MS_MBSI_MASK (0x1U)
#define CAAM_JRCFGR_JR_MS_MBSI_SHIFT (0U)
#define CAAM_JRCFGR_JR_MS_MBSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSI_MASK)
#define CAAM_JRCFGR_JR_MS_MHWSI_MASK (0x2U)
#define CAAM_JRCFGR_JR_MS_MHWSI_SHIFT (1U)
#define CAAM_JRCFGR_JR_MS_MHWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSI_MASK)
#define CAAM_JRCFGR_JR_MS_MWSI_MASK (0x4U)
#define CAAM_JRCFGR_JR_MS_MWSI_SHIFT (2U)
#define CAAM_JRCFGR_JR_MS_MWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSI_MASK)
#define CAAM_JRCFGR_JR_MS_CBSI_MASK (0x10U)
#define CAAM_JRCFGR_JR_MS_CBSI_SHIFT (4U)
#define CAAM_JRCFGR_JR_MS_CBSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSI_MASK)
#define CAAM_JRCFGR_JR_MS_CHWSI_MASK (0x20U)
#define CAAM_JRCFGR_JR_MS_CHWSI_SHIFT (5U)
#define CAAM_JRCFGR_JR_MS_CHWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSI_MASK)
#define CAAM_JRCFGR_JR_MS_CWSI_MASK (0x40U)
#define CAAM_JRCFGR_JR_MS_CWSI_SHIFT (6U)
#define CAAM_JRCFGR_JR_MS_CWSI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSI_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSI_MASK)
#define CAAM_JRCFGR_JR_MS_MBSO_MASK (0x100U)
#define CAAM_JRCFGR_JR_MS_MBSO_SHIFT (8U)
#define CAAM_JRCFGR_JR_MS_MBSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MBSO_MASK)
#define CAAM_JRCFGR_JR_MS_MHWSO_MASK (0x200U)
#define CAAM_JRCFGR_JR_MS_MHWSO_SHIFT (9U)
#define CAAM_JRCFGR_JR_MS_MHWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MHWSO_MASK)
#define CAAM_JRCFGR_JR_MS_MWSO_MASK (0x400U)
#define CAAM_JRCFGR_JR_MS_MWSO_SHIFT (10U)
#define CAAM_JRCFGR_JR_MS_MWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_MWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_MWSO_MASK)
#define CAAM_JRCFGR_JR_MS_CBSO_MASK (0x1000U)
#define CAAM_JRCFGR_JR_MS_CBSO_SHIFT (12U)
#define CAAM_JRCFGR_JR_MS_CBSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CBSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CBSO_MASK)
#define CAAM_JRCFGR_JR_MS_CHWSO_MASK (0x2000U)
#define CAAM_JRCFGR_JR_MS_CHWSO_SHIFT (13U)
#define CAAM_JRCFGR_JR_MS_CHWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CHWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CHWSO_MASK)
#define CAAM_JRCFGR_JR_MS_CWSO_MASK (0x4000U)
#define CAAM_JRCFGR_JR_MS_CWSO_SHIFT (14U)
#define CAAM_JRCFGR_JR_MS_CWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_CWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_CWSO_MASK)
#define CAAM_JRCFGR_JR_MS_DMBS_MASK (0x10000U)
#define CAAM_JRCFGR_JR_MS_DMBS_SHIFT (16U)
#define CAAM_JRCFGR_JR_MS_DMBS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DMBS_SHIFT)) & CAAM_JRCFGR_JR_MS_DMBS_MASK)
#define CAAM_JRCFGR_JR_MS_PEO_MASK (0x20000U)
#define CAAM_JRCFGR_JR_MS_PEO_SHIFT (17U)
#define CAAM_JRCFGR_JR_MS_PEO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_PEO_SHIFT)) & CAAM_JRCFGR_JR_MS_PEO_MASK)
#define CAAM_JRCFGR_JR_MS_DWSO_MASK (0x40000U)
#define CAAM_JRCFGR_JR_MS_DWSO_SHIFT (18U)
#define CAAM_JRCFGR_JR_MS_DWSO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_DWSO_SHIFT)) & CAAM_JRCFGR_JR_MS_DWSO_MASK)
#define CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK (0x20000000U)
#define CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT (29U)
#define CAAM_JRCFGR_JR_MS_FAIL_MODE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_FAIL_MODE_SHIFT)) & CAAM_JRCFGR_JR_MS_FAIL_MODE_MASK)
#define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK (0x40000000U)
#define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT (30U)
#define CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_SHIFT)) & CAAM_JRCFGR_JR_MS_INCL_SEQ_OUT_MASK)
/*! @} */
/* The count of CAAM_JRCFGR_JR_MS */
#define CAAM_JRCFGR_JR_MS_COUNT (4U)
/*! @name JRCFGR_JR_LS - Job Ring Configuration Register for Job Ring 0, least-significant half..Job Ring Configuration Register for Job Ring 3, least-significant half */
/*! @{ */
#define CAAM_JRCFGR_JR_LS_IMSK_MASK (0x1U)
#define CAAM_JRCFGR_JR_LS_IMSK_SHIFT (0U)
/*! IMSK
* 0b0..Interrupt enabled.
* 0b1..Interrupt masked.
*/
#define CAAM_JRCFGR_JR_LS_IMSK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_IMSK_SHIFT)) & CAAM_JRCFGR_JR_LS_IMSK_MASK)
#define CAAM_JRCFGR_JR_LS_ICEN_MASK (0x2U)
#define CAAM_JRCFGR_JR_LS_ICEN_SHIFT (1U)
/*! ICEN
* 0b0..Interrupt coalescing is disabled. If the IMSK bit is cleared, an interrupt is asserted whenever a job is
* written to the output ring. ICDCT is ignored. Note that if software removes one or more jobs and clears
* the interrupt but the output rings slots full is still greater than 0 (ORSF > 0), then the interrupt will
* clear but reassert on the next clock cycle.
* 0b1..Interrupt coalescing is enabled. If the IMSK bit is cleared, an interrupt is asserted whenever the
* threshold number of frames is reached (ICDCT) or when the threshold timer expires (ICTT). Note that if software
* removes one or more jobs and clears the interrupt but the interrupt coalescing threshold is still met
* (ORSF >= ICDCT), then the interrupt will clear but reassert on the next clock cycle.
*/
#define CAAM_JRCFGR_JR_LS_ICEN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICEN_SHIFT)) & CAAM_JRCFGR_JR_LS_ICEN_MASK)
#define CAAM_JRCFGR_JR_LS_ICDCT_MASK (0xFF00U)
#define CAAM_JRCFGR_JR_LS_ICDCT_SHIFT (8U)
#define CAAM_JRCFGR_JR_LS_ICDCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICDCT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICDCT_MASK)
#define CAAM_JRCFGR_JR_LS_ICTT_MASK (0xFFFF0000U)
#define CAAM_JRCFGR_JR_LS_ICTT_SHIFT (16U)
#define CAAM_JRCFGR_JR_LS_ICTT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCFGR_JR_LS_ICTT_SHIFT)) & CAAM_JRCFGR_JR_LS_ICTT_MASK)
/*! @} */
/* The count of CAAM_JRCFGR_JR_LS */
#define CAAM_JRCFGR_JR_LS_COUNT (4U)
/*! @name IRRIR_JR - Input Ring Read Index Register for Job Ring 0..Input Ring Read Index Register for Job Ring 3 */
/*! @{ */
#define CAAM_IRRIR_JR_IRRI_MASK (0x1FFFU)
#define CAAM_IRRIR_JR_IRRI_SHIFT (0U)
#define CAAM_IRRIR_JR_IRRI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_IRRIR_JR_IRRI_SHIFT)) & CAAM_IRRIR_JR_IRRI_MASK)
/*! @} */
/* The count of CAAM_IRRIR_JR */
#define CAAM_IRRIR_JR_COUNT (4U)
/*! @name ORWIR_JR - Output Ring Write Index Register for Job Ring 0..Output Ring Write Index Register for Job Ring 3 */
/*! @{ */
#define CAAM_ORWIR_JR_ORWI_MASK (0x3FFFU)
#define CAAM_ORWIR_JR_ORWI_SHIFT (0U)
#define CAAM_ORWIR_JR_ORWI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_ORWIR_JR_ORWI_SHIFT)) & CAAM_ORWIR_JR_ORWI_MASK)
/*! @} */
/* The count of CAAM_ORWIR_JR */
#define CAAM_ORWIR_JR_COUNT (4U)
/*! @name JRCR_JR - Job Ring Command Register for Job Ring 0..Job Ring Command Register for Job Ring 3 */
/*! @{ */
#define CAAM_JRCR_JR_RESET_MASK (0x1U)
#define CAAM_JRCR_JR_RESET_SHIFT (0U)
#define CAAM_JRCR_JR_RESET(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_RESET_SHIFT)) & CAAM_JRCR_JR_RESET_MASK)
#define CAAM_JRCR_JR_PARK_MASK (0x2U)
#define CAAM_JRCR_JR_PARK_SHIFT (1U)
#define CAAM_JRCR_JR_PARK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRCR_JR_PARK_SHIFT)) & CAAM_JRCR_JR_PARK_MASK)
/*! @} */
/* The count of CAAM_JRCR_JR */
#define CAAM_JRCR_JR_COUNT (4U)
/*! @name JRAAV - Job Ring 0 Address-Array Valid Register..Job Ring 3 Address-Array Valid Register */
/*! @{ */
#define CAAM_JRAAV_V0_MASK (0x1U)
#define CAAM_JRAAV_V0_SHIFT (0U)
#define CAAM_JRAAV_V0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V0_SHIFT)) & CAAM_JRAAV_V0_MASK)
#define CAAM_JRAAV_V1_MASK (0x2U)
#define CAAM_JRAAV_V1_SHIFT (1U)
#define CAAM_JRAAV_V1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V1_SHIFT)) & CAAM_JRAAV_V1_MASK)
#define CAAM_JRAAV_V2_MASK (0x4U)
#define CAAM_JRAAV_V2_SHIFT (2U)
#define CAAM_JRAAV_V2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V2_SHIFT)) & CAAM_JRAAV_V2_MASK)
#define CAAM_JRAAV_V3_MASK (0x8U)
#define CAAM_JRAAV_V3_SHIFT (3U)
#define CAAM_JRAAV_V3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_V3_SHIFT)) & CAAM_JRAAV_V3_MASK)
#define CAAM_JRAAV_BC_MASK (0x80000000U)
#define CAAM_JRAAV_BC_SHIFT (31U)
#define CAAM_JRAAV_BC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_JRAAV_BC_SHIFT)) & CAAM_JRAAV_BC_MASK)
/*! @} */
/* The count of CAAM_JRAAV */
#define CAAM_JRAAV_COUNT (4U)
/*! @name JRAAA - Job Ring 0 Address-Array Address 0 Register..Job Ring 3 Address-Array Address 3 Register */
/*! @{ */
#define CAAM_JRAAA_JD_ADDR_MASK (0xFFFFFFFFFU)
#define CAAM_JRAAA_JD_ADDR_SHIFT (0U)
#define CAAM_JRAAA_JD_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_JRAAA_JD_ADDR_SHIFT)) & CAAM_JRAAA_JD_ADDR_MASK)
/*! @} */
/* The count of CAAM_JRAAA */
#define CAAM_JRAAA_COUNT (4U)
/* The count of CAAM_JRAAA */
#define CAAM_JRAAA_COUNT2 (4U)
/*! @name PX_SDID_JR - Partition 0 SDID register..Partition 15 SDID register */
/*! @{ */
#define CAAM_PX_SDID_JR_SDID_MASK (0xFFFFU)
#define CAAM_PX_SDID_JR_SDID_SHIFT (0U)
#define CAAM_PX_SDID_JR_SDID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SDID_JR_SDID_SHIFT)) & CAAM_PX_SDID_JR_SDID_MASK)
/*! @} */
/* The count of CAAM_PX_SDID_JR */
#define CAAM_PX_SDID_JR_COUNT (4U)
/* The count of CAAM_PX_SDID_JR */
#define CAAM_PX_SDID_JR_COUNT2 (16U)
/*! @name PX_SMAPR_JR - Secure Memory Access Permissions register */
/*! @{ */
#define CAAM_PX_SMAPR_JR_G1_READ_MASK (0x1U)
#define CAAM_PX_SMAPR_JR_G1_READ_SHIFT (0U)
/*! G1_READ
* 0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G1_TDO=1) and
* key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G1_SMBLOB=1 or if done by a
* Trusted Descriptor and G1_TDO=1).
* 0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
* G1_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G1_TDO=0).
*/
#define CAAM_PX_SMAPR_JR_G1_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G1_READ_MASK)
#define CAAM_PX_SMAPR_JR_G1_WRITE_MASK (0x2U)
#define CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT (1U)
/*! G1_WRITE
* 0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
* Blobs is allowed if G1_SMBLOB=1 or if done by a Trusted Descriptor and G1_TDO=1).
* 0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G1_SMBLOB=0 and the descriptor is
* not a Trusted Descriptor or if G1_TDO=0).
*/
#define CAAM_PX_SMAPR_JR_G1_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G1_WRITE_MASK)
#define CAAM_PX_SMAPR_JR_G1_TDO_MASK (0x4U)
#define CAAM_PX_SMAPR_JR_G1_TDO_SHIFT (2U)
/*! G1_TDO
* 0b0..Trusted Descriptors have the same access privileges as Job Descriptors
* 0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
* or import blobs to the partition and read from and write to the partition regardless of the G1_SMBLOB,
* G1_WRITE and G1_READ settings.
*/
#define CAAM_PX_SMAPR_JR_G1_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G1_TDO_MASK)
#define CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK (0x8U)
#define CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT (3U)
/*! G1_SMBLOB
* 0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G1_TDO=1.
* 0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G1_READ and G1_WRITE settings.
*/
#define CAAM_PX_SMAPR_JR_G1_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G1_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G1_SMBLOB_MASK)
#define CAAM_PX_SMAPR_JR_G2_READ_MASK (0x10U)
#define CAAM_PX_SMAPR_JR_G2_READ_SHIFT (4U)
/*! G2_READ
* 0b0..Instruction fetches and reads are prohibited (except that Trusted Descriptor reads (if G2_TDO=1) and
* key-reads are always allowed, and exporting Secure Memory Blobs is allowed if G2_SMBLOB=1 or if done by a
* Trusted Descriptor and G2_TDO=1).
* 0b1..Instruction fetches and reads are allowed (but exporting a Secure Memory Blob is prohibited if
* G2_SMBLOB=0 and the descriptor is not a Trusted Descriptor or if G2_TDO=0).
*/
#define CAAM_PX_SMAPR_JR_G2_READ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_READ_SHIFT)) & CAAM_PX_SMAPR_JR_G2_READ_MASK)
#define CAAM_PX_SMAPR_JR_G2_WRITE_MASK (0x20U)
#define CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT (5U)
/*! G2_WRITE
* 0b0..Writes are prohibited (except that Trusted Descriptor writes are allowed, and importing Secure Memory
* Blobs is allowed if G2_SMBLOB=1 or if done by a Trusted Descriptor and G2_TDO=1).
* 0b1..Writes are allowed (but importing a Secure Memory Blob is prohibited if G2_SMBLOB=0 and the descriptor is
* not a Trusted Descriptor or if G2_TDO=0).
*/
#define CAAM_PX_SMAPR_JR_G2_WRITE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_WRITE_SHIFT)) & CAAM_PX_SMAPR_JR_G2_WRITE_MASK)
#define CAAM_PX_SMAPR_JR_G2_TDO_MASK (0x40U)
#define CAAM_PX_SMAPR_JR_G2_TDO_SHIFT (6U)
/*! G2_TDO
* 0b0..Trusted Descriptors have the same access privileges as Job Descriptors
* 0b1..Trusted Descriptors are allowed to override the other access permissions, i.e. they can export blobs from
* or import blobs to the partition and read from and write to the partition regardless of the G2_SMBLOB,
* G2_WRITE and G2_READ settings.
*/
#define CAAM_PX_SMAPR_JR_G2_TDO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_TDO_SHIFT)) & CAAM_PX_SMAPR_JR_G2_TDO_MASK)
#define CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK (0x80U)
#define CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT (7U)
/*! G2_SMBLOB
* 0b0..Exporting or importing Secure Memory Blobs is prohibited, unless done via a Trusted Descriptor and G2_TDO=1.
* 0b1..Exporting or importing Secure Memory Blobs is allowed, regardless of the G2_READ and G2_WRITE settings.
*/
#define CAAM_PX_SMAPR_JR_G2_SMBLOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_G2_SMBLOB_SHIFT)) & CAAM_PX_SMAPR_JR_G2_SMBLOB_MASK)
#define CAAM_PX_SMAPR_JR_SMAG_LCK_MASK (0x1000U)
#define CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT (12U)
/*! SMAG_LCK
* 0b0..The SMAG2JR register and SMAG1JR register are unlocked. The partition owner can change any writable bits of these registers.
* 0b1..The SMAG2JR register and SMAG1JR register are locked. The SMAG2JR and SMAG1JR registers cannot be changed
* until the partition is de-allocated or a POR occurs.
*/
#define CAAM_PX_SMAPR_JR_SMAG_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAG_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAG_LCK_MASK)
#define CAAM_PX_SMAPR_JR_SMAP_LCK_MASK (0x2000U)
#define CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT (13U)
/*! SMAP_LCK
* 0b0..The SMAP register is unlocked. The partition owner can change any writable bits of the SMAP register.
* 0b1..The SMAP register is locked. The SMAP_LCK, CSP and PSP bits and G1 and G2 permission bits of the SMAP
* register cannot be changed until the partition is de-allocated or a POR occurs. The PARTITION_KMOD value can
* still be changed. The SMAG_LCK bit can be changed to a 1, but cannot be changed to a 0.
*/
#define CAAM_PX_SMAPR_JR_SMAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_SMAP_LCK_SHIFT)) & CAAM_PX_SMAPR_JR_SMAP_LCK_MASK)
#define CAAM_PX_SMAPR_JR_PSP_MASK (0x4000U)
#define CAAM_PX_SMAPR_JR_PSP_SHIFT (14U)
/*! PSP
* 0b0..The partition and any of the pages allocated to the partition can be de-allocated.
* 0b1..The partition cannot be de-allocated and the pages allocated to the partition cannot be de-allocated.
*/
#define CAAM_PX_SMAPR_JR_PSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PSP_SHIFT)) & CAAM_PX_SMAPR_JR_PSP_MASK)
#define CAAM_PX_SMAPR_JR_CSP_MASK (0x8000U)
#define CAAM_PX_SMAPR_JR_CSP_SHIFT (15U)
/*! CSP
* 0b0..The pages allocated to the partition will not be zeroized when they are de-allocated or the partition is
* released or a security alarm occurs.
* 0b1..The pages allocated to the partition will be zeroized when they are individually de-allocated or the
* partition is released or a security alarm occurs.
*/
#define CAAM_PX_SMAPR_JR_CSP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_CSP_SHIFT)) & CAAM_PX_SMAPR_JR_CSP_MASK)
#define CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK (0xFFFF0000U)
#define CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT (16U)
#define CAAM_PX_SMAPR_JR_PARTITION_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAPR_JR_PARTITION_KMOD_SHIFT)) & CAAM_PX_SMAPR_JR_PARTITION_KMOD_MASK)
/*! @} */
/* The count of CAAM_PX_SMAPR_JR */
#define CAAM_PX_SMAPR_JR_COUNT (4U)
/* The count of CAAM_PX_SMAPR_JR */
#define CAAM_PX_SMAPR_JR_COUNT2 (16U)
/*! @name PX_SMAG2_JR - Secure Memory Access Group Registers */
/*! @{ */
#define CAAM_PX_SMAG2_JR_Gx_ID00_MASK (0x1U)
#define CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT (0U)
#define CAAM_PX_SMAG2_JR_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID00_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID01_MASK (0x2U)
#define CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT (1U)
#define CAAM_PX_SMAG2_JR_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID01_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID02_MASK (0x4U)
#define CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT (2U)
#define CAAM_PX_SMAG2_JR_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID02_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID03_MASK (0x8U)
#define CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT (3U)
#define CAAM_PX_SMAG2_JR_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID03_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID04_MASK (0x10U)
#define CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT (4U)
#define CAAM_PX_SMAG2_JR_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID04_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID05_MASK (0x20U)
#define CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT (5U)
#define CAAM_PX_SMAG2_JR_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID05_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID06_MASK (0x40U)
#define CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT (6U)
#define CAAM_PX_SMAG2_JR_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID06_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID07_MASK (0x80U)
#define CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT (7U)
#define CAAM_PX_SMAG2_JR_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID07_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID08_MASK (0x100U)
#define CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT (8U)
#define CAAM_PX_SMAG2_JR_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID08_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID09_MASK (0x200U)
#define CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT (9U)
#define CAAM_PX_SMAG2_JR_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID09_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID10_MASK (0x400U)
#define CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT (10U)
#define CAAM_PX_SMAG2_JR_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID10_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID11_MASK (0x800U)
#define CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT (11U)
#define CAAM_PX_SMAG2_JR_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID11_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID12_MASK (0x1000U)
#define CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT (12U)
#define CAAM_PX_SMAG2_JR_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID12_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID13_MASK (0x2000U)
#define CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT (13U)
#define CAAM_PX_SMAG2_JR_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID13_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID14_MASK (0x4000U)
#define CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT (14U)
#define CAAM_PX_SMAG2_JR_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID14_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID15_MASK (0x8000U)
#define CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT (15U)
#define CAAM_PX_SMAG2_JR_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID15_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID16_MASK (0x10000U)
#define CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT (16U)
#define CAAM_PX_SMAG2_JR_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID16_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID17_MASK (0x20000U)
#define CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT (17U)
#define CAAM_PX_SMAG2_JR_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID17_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID18_MASK (0x40000U)
#define CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT (18U)
#define CAAM_PX_SMAG2_JR_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID18_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID19_MASK (0x80000U)
#define CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT (19U)
#define CAAM_PX_SMAG2_JR_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID19_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID20_MASK (0x100000U)
#define CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT (20U)
#define CAAM_PX_SMAG2_JR_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID20_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID21_MASK (0x200000U)
#define CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT (21U)
#define CAAM_PX_SMAG2_JR_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID21_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID22_MASK (0x400000U)
#define CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT (22U)
#define CAAM_PX_SMAG2_JR_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID22_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID23_MASK (0x800000U)
#define CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT (23U)
#define CAAM_PX_SMAG2_JR_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID23_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID24_MASK (0x1000000U)
#define CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT (24U)
#define CAAM_PX_SMAG2_JR_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID24_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID25_MASK (0x2000000U)
#define CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT (25U)
#define CAAM_PX_SMAG2_JR_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID25_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID26_MASK (0x4000000U)
#define CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT (26U)
#define CAAM_PX_SMAG2_JR_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID26_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID27_MASK (0x8000000U)
#define CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT (27U)
#define CAAM_PX_SMAG2_JR_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID27_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID28_MASK (0x10000000U)
#define CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT (28U)
#define CAAM_PX_SMAG2_JR_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID28_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID29_MASK (0x20000000U)
#define CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT (29U)
#define CAAM_PX_SMAG2_JR_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID29_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID30_MASK (0x40000000U)
#define CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT (30U)
#define CAAM_PX_SMAG2_JR_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID30_MASK)
#define CAAM_PX_SMAG2_JR_Gx_ID31_MASK (0x80000000U)
#define CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT (31U)
#define CAAM_PX_SMAG2_JR_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG2_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG2_JR_Gx_ID31_MASK)
/*! @} */
/* The count of CAAM_PX_SMAG2_JR */
#define CAAM_PX_SMAG2_JR_COUNT (4U)
/* The count of CAAM_PX_SMAG2_JR */
#define CAAM_PX_SMAG2_JR_COUNT2 (16U)
/*! @name PX_SMAG1_JR - Secure Memory Access Group Registers */
/*! @{ */
#define CAAM_PX_SMAG1_JR_Gx_ID00_MASK (0x1U)
#define CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT (0U)
#define CAAM_PX_SMAG1_JR_Gx_ID00(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID00_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID00_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID01_MASK (0x2U)
#define CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT (1U)
#define CAAM_PX_SMAG1_JR_Gx_ID01(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID01_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID01_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID02_MASK (0x4U)
#define CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT (2U)
#define CAAM_PX_SMAG1_JR_Gx_ID02(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID02_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID02_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID03_MASK (0x8U)
#define CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT (3U)
#define CAAM_PX_SMAG1_JR_Gx_ID03(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID03_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID03_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID04_MASK (0x10U)
#define CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT (4U)
#define CAAM_PX_SMAG1_JR_Gx_ID04(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID04_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID04_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID05_MASK (0x20U)
#define CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT (5U)
#define CAAM_PX_SMAG1_JR_Gx_ID05(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID05_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID05_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID06_MASK (0x40U)
#define CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT (6U)
#define CAAM_PX_SMAG1_JR_Gx_ID06(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID06_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID06_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID07_MASK (0x80U)
#define CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT (7U)
#define CAAM_PX_SMAG1_JR_Gx_ID07(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID07_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID07_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID08_MASK (0x100U)
#define CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT (8U)
#define CAAM_PX_SMAG1_JR_Gx_ID08(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID08_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID08_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID09_MASK (0x200U)
#define CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT (9U)
#define CAAM_PX_SMAG1_JR_Gx_ID09(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID09_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID09_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID10_MASK (0x400U)
#define CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT (10U)
#define CAAM_PX_SMAG1_JR_Gx_ID10(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID10_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID10_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID11_MASK (0x800U)
#define CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT (11U)
#define CAAM_PX_SMAG1_JR_Gx_ID11(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID11_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID11_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID12_MASK (0x1000U)
#define CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT (12U)
#define CAAM_PX_SMAG1_JR_Gx_ID12(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID12_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID12_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID13_MASK (0x2000U)
#define CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT (13U)
#define CAAM_PX_SMAG1_JR_Gx_ID13(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID13_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID13_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID14_MASK (0x4000U)
#define CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT (14U)
#define CAAM_PX_SMAG1_JR_Gx_ID14(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID14_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID14_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID15_MASK (0x8000U)
#define CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT (15U)
#define CAAM_PX_SMAG1_JR_Gx_ID15(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID15_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID15_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID16_MASK (0x10000U)
#define CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT (16U)
#define CAAM_PX_SMAG1_JR_Gx_ID16(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID16_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID16_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID17_MASK (0x20000U)
#define CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT (17U)
#define CAAM_PX_SMAG1_JR_Gx_ID17(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID17_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID17_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID18_MASK (0x40000U)
#define CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT (18U)
#define CAAM_PX_SMAG1_JR_Gx_ID18(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID18_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID18_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID19_MASK (0x80000U)
#define CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT (19U)
#define CAAM_PX_SMAG1_JR_Gx_ID19(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID19_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID19_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID20_MASK (0x100000U)
#define CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT (20U)
#define CAAM_PX_SMAG1_JR_Gx_ID20(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID20_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID20_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID21_MASK (0x200000U)
#define CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT (21U)
#define CAAM_PX_SMAG1_JR_Gx_ID21(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID21_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID21_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID22_MASK (0x400000U)
#define CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT (22U)
#define CAAM_PX_SMAG1_JR_Gx_ID22(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID22_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID22_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID23_MASK (0x800000U)
#define CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT (23U)
#define CAAM_PX_SMAG1_JR_Gx_ID23(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID23_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID23_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID24_MASK (0x1000000U)
#define CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT (24U)
#define CAAM_PX_SMAG1_JR_Gx_ID24(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID24_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID24_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID25_MASK (0x2000000U)
#define CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT (25U)
#define CAAM_PX_SMAG1_JR_Gx_ID25(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID25_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID25_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID26_MASK (0x4000000U)
#define CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT (26U)
#define CAAM_PX_SMAG1_JR_Gx_ID26(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID26_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID26_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID27_MASK (0x8000000U)
#define CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT (27U)
#define CAAM_PX_SMAG1_JR_Gx_ID27(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID27_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID27_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID28_MASK (0x10000000U)
#define CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT (28U)
#define CAAM_PX_SMAG1_JR_Gx_ID28(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID28_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID28_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID29_MASK (0x20000000U)
#define CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT (29U)
#define CAAM_PX_SMAG1_JR_Gx_ID29(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID29_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID29_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID30_MASK (0x40000000U)
#define CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT (30U)
#define CAAM_PX_SMAG1_JR_Gx_ID30(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID30_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID30_MASK)
#define CAAM_PX_SMAG1_JR_Gx_ID31_MASK (0x80000000U)
#define CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT (31U)
#define CAAM_PX_SMAG1_JR_Gx_ID31(x) (((uint32_t)(((uint32_t)(x)) << CAAM_PX_SMAG1_JR_Gx_ID31_SHIFT)) & CAAM_PX_SMAG1_JR_Gx_ID31_MASK)
/*! @} */
/* The count of CAAM_PX_SMAG1_JR */
#define CAAM_PX_SMAG1_JR_COUNT (4U)
/* The count of CAAM_PX_SMAG1_JR */
#define CAAM_PX_SMAG1_JR_COUNT2 (16U)
/*! @name SMCR_JR - Secure Memory Command Register */
/*! @{ */
#define CAAM_SMCR_JR_CMD_MASK (0xFU)
#define CAAM_SMCR_JR_CMD_SHIFT (0U)
#define CAAM_SMCR_JR_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_CMD_SHIFT)) & CAAM_SMCR_JR_CMD_MASK)
#define CAAM_SMCR_JR_PRTN_MASK (0xF00U)
#define CAAM_SMCR_JR_PRTN_SHIFT (8U)
#define CAAM_SMCR_JR_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PRTN_SHIFT)) & CAAM_SMCR_JR_PRTN_MASK)
#define CAAM_SMCR_JR_PAGE_MASK (0xFFFF0000U)
#define CAAM_SMCR_JR_PAGE_SHIFT (16U)
#define CAAM_SMCR_JR_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCR_JR_PAGE_SHIFT)) & CAAM_SMCR_JR_PAGE_MASK)
/*! @} */
/* The count of CAAM_SMCR_JR */
#define CAAM_SMCR_JR_COUNT (4U)
/*! @name SMCSR_JR - Secure Memory Command Status Register */
/*! @{ */
#define CAAM_SMCSR_JR_PRTN_MASK (0xFU)
#define CAAM_SMCSR_JR_PRTN_SHIFT (0U)
#define CAAM_SMCSR_JR_PRTN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PRTN_SHIFT)) & CAAM_SMCSR_JR_PRTN_MASK)
#define CAAM_SMCSR_JR_PO_MASK (0xC0U)
#define CAAM_SMCSR_JR_PO_SHIFT (6U)
/*! PO
* 0b00..Available; Unowned: The entity that issued the inquiry may allocate this page to a partition. No
* zeroization is needed since it has already been cleared, therefore no interrupt should be expected.
* 0b01..Page does not exist in this version or is not initialized yet.
* 0b10..Another entity owns the page. This page is unavailable to the issuer of the inquiry.
* 0b11..Owned by the entity making the inquiry. The owner may de-allocate this page if its partition is not
* marked PSP. If the partition to which the page is allocated is designated as CSP, the page will be zeroized
* upon de-allocation.
*/
#define CAAM_SMCSR_JR_PO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PO_SHIFT)) & CAAM_SMCSR_JR_PO_MASK)
#define CAAM_SMCSR_JR_AERR_MASK (0x3000U)
#define CAAM_SMCSR_JR_AERR_SHIFT (12U)
#define CAAM_SMCSR_JR_AERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_AERR_SHIFT)) & CAAM_SMCSR_JR_AERR_MASK)
#define CAAM_SMCSR_JR_CERR_MASK (0xC000U)
#define CAAM_SMCSR_JR_CERR_SHIFT (14U)
/*! CERR
* 0b00..No Error.
* 0b01..Command has not yet completed.
* 0b10..A security failure occurred.
* 0b11..Command Overflow. Another command was issued by the same Job Ring owner before the owner's previous
* command completed. The additional command was ignored.
*/
#define CAAM_SMCSR_JR_CERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_CERR_SHIFT)) & CAAM_SMCSR_JR_CERR_MASK)
#define CAAM_SMCSR_JR_PAGE_MASK (0xFFF0000U)
#define CAAM_SMCSR_JR_PAGE_SHIFT (16U)
#define CAAM_SMCSR_JR_PAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SMCSR_JR_PAGE_SHIFT)) & CAAM_SMCSR_JR_PAGE_MASK)
/*! @} */
/* The count of CAAM_SMCSR_JR */
#define CAAM_SMCSR_JR_COUNT (4U)
/*! @name REIR0JR - Recoverable Error Interrupt Record 0 for Job Ring 0..Recoverable Error Interrupt Record 0 for Job Ring 3 */
/*! @{ */
#define CAAM_REIR0JR_TYPE_MASK (0x3000000U)
#define CAAM_REIR0JR_TYPE_SHIFT (24U)
#define CAAM_REIR0JR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_TYPE_SHIFT)) & CAAM_REIR0JR_TYPE_MASK)
#define CAAM_REIR0JR_MISS_MASK (0x80000000U)
#define CAAM_REIR0JR_MISS_SHIFT (31U)
#define CAAM_REIR0JR_MISS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0JR_MISS_SHIFT)) & CAAM_REIR0JR_MISS_MASK)
/*! @} */
/* The count of CAAM_REIR0JR */
#define CAAM_REIR0JR_COUNT (4U)
/*! @name REIR2JR - Recoverable Error Interrupt Record 2 for Job Ring 0..Recoverable Error Interrupt Record 2 for Job Ring 3 */
/*! @{ */
#define CAAM_REIR2JR_ADDR_MASK (0xFFFFFFFFFU)
#define CAAM_REIR2JR_ADDR_SHIFT (0U)
#define CAAM_REIR2JR_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2JR_ADDR_SHIFT)) & CAAM_REIR2JR_ADDR_MASK)
/*! @} */
/* The count of CAAM_REIR2JR */
#define CAAM_REIR2JR_COUNT (4U)
/*! @name REIR4JR - Recoverable Error Interrupt Record 4 for Job Ring 0..Recoverable Error Interrupt Record 4 for Job Ring 3 */
/*! @{ */
#define CAAM_REIR4JR_ICID_MASK (0x7FFU)
#define CAAM_REIR4JR_ICID_SHIFT (0U)
#define CAAM_REIR4JR_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ICID_SHIFT)) & CAAM_REIR4JR_ICID_MASK)
#define CAAM_REIR4JR_DID_MASK (0x7800U)
#define CAAM_REIR4JR_DID_SHIFT (11U)
#define CAAM_REIR4JR_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_DID_SHIFT)) & CAAM_REIR4JR_DID_MASK)
#define CAAM_REIR4JR_AXCACHE_MASK (0xF0000U)
#define CAAM_REIR4JR_AXCACHE_SHIFT (16U)
#define CAAM_REIR4JR_AXCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXCACHE_SHIFT)) & CAAM_REIR4JR_AXCACHE_MASK)
#define CAAM_REIR4JR_AXPROT_MASK (0x700000U)
#define CAAM_REIR4JR_AXPROT_SHIFT (20U)
#define CAAM_REIR4JR_AXPROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_AXPROT_SHIFT)) & CAAM_REIR4JR_AXPROT_MASK)
#define CAAM_REIR4JR_RWB_MASK (0x800000U)
#define CAAM_REIR4JR_RWB_SHIFT (23U)
#define CAAM_REIR4JR_RWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_RWB_SHIFT)) & CAAM_REIR4JR_RWB_MASK)
#define CAAM_REIR4JR_ERR_MASK (0x30000000U)
#define CAAM_REIR4JR_ERR_SHIFT (28U)
#define CAAM_REIR4JR_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_ERR_SHIFT)) & CAAM_REIR4JR_ERR_MASK)
#define CAAM_REIR4JR_MIX_MASK (0xC0000000U)
#define CAAM_REIR4JR_MIX_SHIFT (30U)
#define CAAM_REIR4JR_MIX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4JR_MIX_SHIFT)) & CAAM_REIR4JR_MIX_MASK)
/*! @} */
/* The count of CAAM_REIR4JR */
#define CAAM_REIR4JR_COUNT (4U)
/*! @name REIR5JR - Recoverable Error Interrupt Record 5 for Job Ring 0..Recoverable Error Interrupt Record 5 for Job Ring 3 */
/*! @{ */
#define CAAM_REIR5JR_BID_MASK (0xF0000U)
#define CAAM_REIR5JR_BID_SHIFT (16U)
#define CAAM_REIR5JR_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BID_SHIFT)) & CAAM_REIR5JR_BID_MASK)
#define CAAM_REIR5JR_BNDG_MASK (0x2000000U)
#define CAAM_REIR5JR_BNDG_SHIFT (25U)
#define CAAM_REIR5JR_BNDG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_BNDG_SHIFT)) & CAAM_REIR5JR_BNDG_MASK)
#define CAAM_REIR5JR_TDSC_MASK (0x4000000U)
#define CAAM_REIR5JR_TDSC_SHIFT (26U)
#define CAAM_REIR5JR_TDSC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_TDSC_SHIFT)) & CAAM_REIR5JR_TDSC_MASK)
#define CAAM_REIR5JR_KMOD_MASK (0x8000000U)
#define CAAM_REIR5JR_KMOD_SHIFT (27U)
#define CAAM_REIR5JR_KMOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KMOD_SHIFT)) & CAAM_REIR5JR_KMOD_MASK)
#define CAAM_REIR5JR_KEY_MASK (0x10000000U)
#define CAAM_REIR5JR_KEY_SHIFT (28U)
#define CAAM_REIR5JR_KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_KEY_SHIFT)) & CAAM_REIR5JR_KEY_MASK)
#define CAAM_REIR5JR_SMA_MASK (0x20000000U)
#define CAAM_REIR5JR_SMA_SHIFT (29U)
#define CAAM_REIR5JR_SMA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5JR_SMA_SHIFT)) & CAAM_REIR5JR_SMA_MASK)
/*! @} */
/* The count of CAAM_REIR5JR */
#define CAAM_REIR5JR_COUNT (4U)
/*! @name RSTA - RTIC Status Register */
/*! @{ */
#define CAAM_RSTA_BSY_MASK (0x1U)
#define CAAM_RSTA_BSY_SHIFT (0U)
/*! BSY
* 0b0..RTIC Idle.
* 0b1..RTIC Busy.
*/
#define CAAM_RSTA_BSY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_BSY_SHIFT)) & CAAM_RSTA_BSY_MASK)
#define CAAM_RSTA_HD_MASK (0x2U)
#define CAAM_RSTA_HD_SHIFT (1U)
/*! HD
* 0b0..Boot authentication disabled
* 0b1..Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode.
*/
#define CAAM_RSTA_HD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HD_SHIFT)) & CAAM_RSTA_HD_MASK)
#define CAAM_RSTA_SV_MASK (0x4U)
#define CAAM_RSTA_SV_SHIFT (2U)
/*! SV
* 0b0..Memory block contents authenticated.
* 0b1..Memory block hash doesn't match reference value.
*/
#define CAAM_RSTA_SV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_SV_SHIFT)) & CAAM_RSTA_SV_MASK)
#define CAAM_RSTA_HE_MASK (0x8U)
#define CAAM_RSTA_HE_SHIFT (3U)
/*! HE
* 0b0..Memory block contents authenticated.
* 0b1..Memory block hash doesn't match reference value.
*/
#define CAAM_RSTA_HE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HE_SHIFT)) & CAAM_RSTA_HE_MASK)
#define CAAM_RSTA_MIS_MASK (0xF0U)
#define CAAM_RSTA_MIS_SHIFT (4U)
/*! MIS
* 0b0000..Memory Block X is valid or state unknown
* 0b0001..Memory Block X has been corrupted
*/
#define CAAM_RSTA_MIS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_MIS_SHIFT)) & CAAM_RSTA_MIS_MASK)
#define CAAM_RSTA_AE_MASK (0xF00U)
#define CAAM_RSTA_AE_SHIFT (8U)
/*! AE
* 0b0000..All reads by RTIC were valid.
* 0b0001..An illegal address was accessed by the RTIC
*/
#define CAAM_RSTA_AE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_AE_SHIFT)) & CAAM_RSTA_AE_MASK)
#define CAAM_RSTA_WE_MASK (0x10000U)
#define CAAM_RSTA_WE_SHIFT (16U)
/*! WE
* 0b0..No RTIC Watchdog timer error has occurred.
* 0b1..RTIC Watchdog timer has expired prior to completing a round of hashing.
*/
#define CAAM_RSTA_WE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_WE_SHIFT)) & CAAM_RSTA_WE_MASK)
#define CAAM_RSTA_ABH_MASK (0x20000U)
#define CAAM_RSTA_ABH_SHIFT (17U)
#define CAAM_RSTA_ABH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_ABH_SHIFT)) & CAAM_RSTA_ABH_MASK)
#define CAAM_RSTA_HOD_MASK (0x40000U)
#define CAAM_RSTA_HOD_SHIFT (18U)
#define CAAM_RSTA_HOD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_HOD_SHIFT)) & CAAM_RSTA_HOD_MASK)
#define CAAM_RSTA_RTD_MASK (0x80000U)
#define CAAM_RSTA_RTD_SHIFT (19U)
#define CAAM_RSTA_RTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_RTD_SHIFT)) & CAAM_RSTA_RTD_MASK)
#define CAAM_RSTA_CS_MASK (0x6000000U)
#define CAAM_RSTA_CS_SHIFT (25U)
/*! CS
* 0b00..Idle State
* 0b01..Single Hash State
* 0b10..Run-time State
* 0b11..Error State
*/
#define CAAM_RSTA_CS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RSTA_CS_SHIFT)) & CAAM_RSTA_CS_MASK)
/*! @} */
/*! @name RCMD - RTIC Command Register */
/*! @{ */
#define CAAM_RCMD_CINT_MASK (0x1U)
#define CAAM_RCMD_CINT_SHIFT (0U)
/*! CINT
* 0b0..Do not clear interrupt
* 0b1..Clear interrupt. This bit cannot be modified during run-time checking mode
*/
#define CAAM_RCMD_CINT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_CINT_SHIFT)) & CAAM_RCMD_CINT_MASK)
#define CAAM_RCMD_HO_MASK (0x2U)
#define CAAM_RCMD_HO_SHIFT (1U)
/*! HO
* 0b0..Boot authentication disabled
* 0b1..Authenticate code/generate reference hash value. This bit cannot be modified during run-time checking mode.
*/
#define CAAM_RCMD_HO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_HO_SHIFT)) & CAAM_RCMD_HO_MASK)
#define CAAM_RCMD_RTC_MASK (0x4U)
#define CAAM_RCMD_RTC_SHIFT (2U)
/*! RTC
* 0b0..Run-time checking disabled
* 0b1..Verify run-time memory blocks continually
*/
#define CAAM_RCMD_RTC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTC_SHIFT)) & CAAM_RCMD_RTC_MASK)
#define CAAM_RCMD_RTD_MASK (0x8U)
#define CAAM_RCMD_RTD_SHIFT (3U)
/*! RTD
* 0b0..Allow Run Time Mode
* 0b1..Prevent Run Time Mode
*/
#define CAAM_RCMD_RTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCMD_RTD_SHIFT)) & CAAM_RCMD_RTD_MASK)
/*! @} */
/*! @name RCTL - RTIC Control Register */
/*! @{ */
#define CAAM_RCTL_IE_MASK (0x1U)
#define CAAM_RCTL_IE_SHIFT (0U)
/*! IE
* 0b0..Interrupts disabled
* 0b1..Interrupts enabled
*/
#define CAAM_RCTL_IE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_IE_SHIFT)) & CAAM_RCTL_IE_MASK)
#define CAAM_RCTL_RREQS_MASK (0xEU)
#define CAAM_RCTL_RREQS_SHIFT (1U)
#define CAAM_RCTL_RREQS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RREQS_SHIFT)) & CAAM_RCTL_RREQS_MASK)
#define CAAM_RCTL_HOME_MASK (0xF0U)
#define CAAM_RCTL_HOME_SHIFT (4U)
#define CAAM_RCTL_HOME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_HOME_SHIFT)) & CAAM_RCTL_HOME_MASK)
#define CAAM_RCTL_RTME_MASK (0xF00U)
#define CAAM_RCTL_RTME_SHIFT (8U)
#define CAAM_RCTL_RTME(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTME_SHIFT)) & CAAM_RCTL_RTME_MASK)
#define CAAM_RCTL_RTMU_MASK (0xF000U)
#define CAAM_RCTL_RTMU_SHIFT (12U)
#define CAAM_RCTL_RTMU(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RTMU_SHIFT)) & CAAM_RCTL_RTMU_MASK)
#define CAAM_RCTL_RALG_MASK (0xF0000U)
#define CAAM_RCTL_RALG_SHIFT (16U)
#define CAAM_RCTL_RALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RALG_SHIFT)) & CAAM_RCTL_RALG_MASK)
#define CAAM_RCTL_RIDLE_MASK (0x100000U)
#define CAAM_RCTL_RIDLE_SHIFT (20U)
#define CAAM_RCTL_RIDLE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RCTL_RIDLE_SHIFT)) & CAAM_RCTL_RIDLE_MASK)
/*! @} */
/*! @name RTHR - RTIC Throttle Register */
/*! @{ */
#define CAAM_RTHR_RTHR_MASK (0xFFFFU)
#define CAAM_RTHR_RTHR_SHIFT (0U)
#define CAAM_RTHR_RTHR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RTHR_RTHR_SHIFT)) & CAAM_RTHR_RTHR_MASK)
/*! @} */
/*! @name RWDOG - RTIC Watchdog Timer */
/*! @{ */
#define CAAM_RWDOG_RWDOG_MASK (0xFFFFFFFFU)
#define CAAM_RWDOG_RWDOG_SHIFT (0U)
#define CAAM_RWDOG_RWDOG(x) (((uint64_t)(((uint64_t)(x)) << CAAM_RWDOG_RWDOG_SHIFT)) & CAAM_RWDOG_RWDOG_MASK)
/*! @} */
/*! @name REND - RTIC Endian Register */
/*! @{ */
#define CAAM_REND_REPO_MASK (0xFU)
#define CAAM_REND_REPO_SHIFT (0U)
/*! REPO
* 0bxxx1..Byte Swap Memory Block A
* 0bxx1x..Byte Swap Memory Block B
* 0bx1xx..Byte Swap Memory Block C
* 0b1xxx..Byte Swap Memory Block D
*/
#define CAAM_REND_REPO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_REPO_SHIFT)) & CAAM_REND_REPO_MASK)
#define CAAM_REND_RBS_MASK (0xF0U)
#define CAAM_REND_RBS_SHIFT (4U)
/*! RBS
* 0bxxx1..Byte Swap Memory Block A
* 0bxx1x..Byte Swap Memory Block B
* 0bx1xx..Byte Swap Memory Block C
* 0b1xxx..Byte Swap Memory Block D
*/
#define CAAM_REND_RBS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RBS_SHIFT)) & CAAM_REND_RBS_MASK)
#define CAAM_REND_RHWS_MASK (0xF00U)
#define CAAM_REND_RHWS_SHIFT (8U)
/*! RHWS
* 0bxxx1..Half-Word Swap Memory Block A
* 0bxx1x..Half-Word Swap Memory Block B
* 0bx1xx..Half-Word Swap Memory Block C
* 0b1xxx..Half-Word Swap Memory Block D
*/
#define CAAM_REND_RHWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RHWS_SHIFT)) & CAAM_REND_RHWS_MASK)
#define CAAM_REND_RWS_MASK (0xF000U)
#define CAAM_REND_RWS_SHIFT (12U)
/*! RWS
* 0bxxx1..Word Swap Memory Block A
* 0bxx1x..Word Swap Memory Block B
* 0bx1xx..Word Swap Memory Block C
* 0b1xxx..Word Swap Memory Block D
*/
#define CAAM_REND_RWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REND_RWS_SHIFT)) & CAAM_REND_RWS_MASK)
/*! @} */
/*! @name RMA - RTIC Memory Block A Address 0 Register..RTIC Memory Block D Address 1 Register */
/*! @{ */
#define CAAM_RMA_MEMBLKADDR_MASK (0xFFFFFFFFFU)
#define CAAM_RMA_MEMBLKADDR_SHIFT (0U)
#define CAAM_RMA_MEMBLKADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_RMA_MEMBLKADDR_SHIFT)) & CAAM_RMA_MEMBLKADDR_MASK)
/*! @} */
/* The count of CAAM_RMA */
#define CAAM_RMA_COUNT (4U)
/* The count of CAAM_RMA */
#define CAAM_RMA_COUNT2 (2U)
/*! @name RML - RTIC Memory Block A Length 0 Register..RTIC Memory Block D Length 1 Register */
/*! @{ */
#define CAAM_RML_MEMBLKLEN_MASK (0xFFFFFFFFU)
#define CAAM_RML_MEMBLKLEN_SHIFT (0U)
#define CAAM_RML_MEMBLKLEN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RML_MEMBLKLEN_SHIFT)) & CAAM_RML_MEMBLKLEN_MASK)
/*! @} */
/* The count of CAAM_RML */
#define CAAM_RML_COUNT (4U)
/* The count of CAAM_RML */
#define CAAM_RML_COUNT2 (2U)
/*! @name RMD - RTIC Memory Block A Big Endian Hash Result Word 0..RTIC Memory Block D Little Endian Hash Result Word 31 */
/*! @{ */
#define CAAM_RMD_RTIC_Hash_Result_MASK (0xFFFFFFFFU)
#define CAAM_RMD_RTIC_Hash_Result_SHIFT (0U)
#define CAAM_RMD_RTIC_Hash_Result(x) (((uint32_t)(((uint32_t)(x)) << CAAM_RMD_RTIC_Hash_Result_SHIFT)) & CAAM_RMD_RTIC_Hash_Result_MASK)
/*! @} */
/* The count of CAAM_RMD */
#define CAAM_RMD_COUNT (4U)
/* The count of CAAM_RMD */
#define CAAM_RMD_COUNT2 (2U)
/* The count of CAAM_RMD */
#define CAAM_RMD_COUNT3 (32U)
/*! @name REIR0RTIC - Recoverable Error Interrupt Record 0 for RTIC */
/*! @{ */
#define CAAM_REIR0RTIC_TYPE_MASK (0x3000000U)
#define CAAM_REIR0RTIC_TYPE_SHIFT (24U)
#define CAAM_REIR0RTIC_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_TYPE_SHIFT)) & CAAM_REIR0RTIC_TYPE_MASK)
#define CAAM_REIR0RTIC_MISS_MASK (0x80000000U)
#define CAAM_REIR0RTIC_MISS_SHIFT (31U)
#define CAAM_REIR0RTIC_MISS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR0RTIC_MISS_SHIFT)) & CAAM_REIR0RTIC_MISS_MASK)
/*! @} */
/*! @name REIR2RTIC - Recoverable Error Interrupt Record 2 for RTIC */
/*! @{ */
#define CAAM_REIR2RTIC_ADDR_MASK (0xFFFFFFFFFFFFFFFFU)
#define CAAM_REIR2RTIC_ADDR_SHIFT (0U)
#define CAAM_REIR2RTIC_ADDR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_REIR2RTIC_ADDR_SHIFT)) & CAAM_REIR2RTIC_ADDR_MASK)
/*! @} */
/*! @name REIR4RTIC - Recoverable Error Interrupt Record 4 for RTIC */
/*! @{ */
#define CAAM_REIR4RTIC_ICID_MASK (0x7FFU)
#define CAAM_REIR4RTIC_ICID_SHIFT (0U)
#define CAAM_REIR4RTIC_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ICID_SHIFT)) & CAAM_REIR4RTIC_ICID_MASK)
#define CAAM_REIR4RTIC_DID_MASK (0x7800U)
#define CAAM_REIR4RTIC_DID_SHIFT (11U)
#define CAAM_REIR4RTIC_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_DID_SHIFT)) & CAAM_REIR4RTIC_DID_MASK)
#define CAAM_REIR4RTIC_AXCACHE_MASK (0xF0000U)
#define CAAM_REIR4RTIC_AXCACHE_SHIFT (16U)
#define CAAM_REIR4RTIC_AXCACHE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXCACHE_SHIFT)) & CAAM_REIR4RTIC_AXCACHE_MASK)
#define CAAM_REIR4RTIC_AXPROT_MASK (0x700000U)
#define CAAM_REIR4RTIC_AXPROT_SHIFT (20U)
#define CAAM_REIR4RTIC_AXPROT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_AXPROT_SHIFT)) & CAAM_REIR4RTIC_AXPROT_MASK)
#define CAAM_REIR4RTIC_RWB_MASK (0x800000U)
#define CAAM_REIR4RTIC_RWB_SHIFT (23U)
#define CAAM_REIR4RTIC_RWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_RWB_SHIFT)) & CAAM_REIR4RTIC_RWB_MASK)
#define CAAM_REIR4RTIC_ERR_MASK (0x30000000U)
#define CAAM_REIR4RTIC_ERR_SHIFT (28U)
#define CAAM_REIR4RTIC_ERR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_ERR_SHIFT)) & CAAM_REIR4RTIC_ERR_MASK)
#define CAAM_REIR4RTIC_MIX_MASK (0xC0000000U)
#define CAAM_REIR4RTIC_MIX_SHIFT (30U)
#define CAAM_REIR4RTIC_MIX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR4RTIC_MIX_SHIFT)) & CAAM_REIR4RTIC_MIX_MASK)
/*! @} */
/*! @name REIR5RTIC - Recoverable Error Interrupt Record 5 for RTIC */
/*! @{ */
#define CAAM_REIR5RTIC_BID_MASK (0xF0000U)
#define CAAM_REIR5RTIC_BID_SHIFT (16U)
#define CAAM_REIR5RTIC_BID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_BID_SHIFT)) & CAAM_REIR5RTIC_BID_MASK)
#define CAAM_REIR5RTIC_SAFE_MASK (0x1000000U)
#define CAAM_REIR5RTIC_SAFE_SHIFT (24U)
#define CAAM_REIR5RTIC_SAFE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SAFE_SHIFT)) & CAAM_REIR5RTIC_SAFE_MASK)
#define CAAM_REIR5RTIC_SMA_MASK (0x2000000U)
#define CAAM_REIR5RTIC_SMA_SHIFT (25U)
#define CAAM_REIR5RTIC_SMA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_REIR5RTIC_SMA_SHIFT)) & CAAM_REIR5RTIC_SMA_MASK)
/*! @} */
/*! @name CC1MR - CCB 0 Class 1 Mode Register Format for Non-Public Key Algorithms */
/*! @{ */
#define CAAM_CC1MR_ENC_MASK (0x1U)
#define CAAM_CC1MR_ENC_SHIFT (0U)
/*! ENC
* 0b0..Decrypt.
* 0b1..Encrypt.
*/
#define CAAM_CC1MR_ENC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ENC_SHIFT)) & CAAM_CC1MR_ENC_MASK)
#define CAAM_CC1MR_ICV_TEST_MASK (0x2U)
#define CAAM_CC1MR_ICV_TEST_SHIFT (1U)
#define CAAM_CC1MR_ICV_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ICV_TEST_SHIFT)) & CAAM_CC1MR_ICV_TEST_MASK)
#define CAAM_CC1MR_AS_MASK (0xCU)
#define CAAM_CC1MR_AS_SHIFT (2U)
/*! AS
* 0b00..Update
* 0b01..Initialize
* 0b10..Finalize
* 0b11..Initialize/Finalize
*/
#define CAAM_CC1MR_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AS_SHIFT)) & CAAM_CC1MR_AS_MASK)
#define CAAM_CC1MR_AAI_MASK (0x1FF0U)
#define CAAM_CC1MR_AAI_SHIFT (4U)
#define CAAM_CC1MR_AAI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_AAI_SHIFT)) & CAAM_CC1MR_AAI_MASK)
#define CAAM_CC1MR_ALG_MASK (0xFF0000U)
#define CAAM_CC1MR_ALG_SHIFT (16U)
/*! ALG
* 0b00010000..AES
* 0b00100000..DES
* 0b00100001..3DES
* 0b01010000..RNG
*/
#define CAAM_CC1MR_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_ALG_SHIFT)) & CAAM_CC1MR_ALG_MASK)
/*! @} */
/* The count of CAAM_CC1MR */
#define CAAM_CC1MR_COUNT (1U)
/*! @name CC1MR_PK - CCB 0 Class 1 Mode Register Format for Public Key Algorithms */
/*! @{ */
#define CAAM_CC1MR_PK_PKHA_MODE_LS_MASK (0xFFFU)
#define CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT (0U)
#define CAAM_CC1MR_PK_PKHA_MODE_LS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_LS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_LS_MASK)
#define CAAM_CC1MR_PK_PKHA_MODE_MS_MASK (0xF0000U)
#define CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT (16U)
#define CAAM_CC1MR_PK_PKHA_MODE_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_PK_PKHA_MODE_MS_SHIFT)) & CAAM_CC1MR_PK_PKHA_MODE_MS_MASK)
/*! @} */
/* The count of CAAM_CC1MR_PK */
#define CAAM_CC1MR_PK_COUNT (1U)
/*! @name CC1MR_RNG - CCB 0 Class 1 Mode Register Format for RNG4 */
/*! @{ */
#define CAAM_CC1MR_RNG_TST_MASK (0x1U)
#define CAAM_CC1MR_RNG_TST_SHIFT (0U)
#define CAAM_CC1MR_RNG_TST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_TST_SHIFT)) & CAAM_CC1MR_RNG_TST_MASK)
#define CAAM_CC1MR_RNG_PR_MASK (0x2U)
#define CAAM_CC1MR_RNG_PR_SHIFT (1U)
#define CAAM_CC1MR_RNG_PR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PR_SHIFT)) & CAAM_CC1MR_RNG_PR_MASK)
#define CAAM_CC1MR_RNG_AS_MASK (0xCU)
#define CAAM_CC1MR_RNG_AS_SHIFT (2U)
#define CAAM_CC1MR_RNG_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AS_SHIFT)) & CAAM_CC1MR_RNG_AS_MASK)
#define CAAM_CC1MR_RNG_SH_MASK (0x30U)
#define CAAM_CC1MR_RNG_SH_SHIFT (4U)
/*! SH
* 0b00..State Handle 0
* 0b01..State Handle 1
* 0b10..Reserved
* 0b11..Reserved
*/
#define CAAM_CC1MR_RNG_SH(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SH_SHIFT)) & CAAM_CC1MR_RNG_SH_MASK)
#define CAAM_CC1MR_RNG_NZB_MASK (0x100U)
#define CAAM_CC1MR_RNG_NZB_SHIFT (8U)
/*! NZB
* 0b0..Generate random data with all-zero bytes permitted.
* 0b1..Generate random data without any all-zero bytes.
*/
#define CAAM_CC1MR_RNG_NZB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_NZB_SHIFT)) & CAAM_CC1MR_RNG_NZB_MASK)
#define CAAM_CC1MR_RNG_OBP_MASK (0x200U)
#define CAAM_CC1MR_RNG_OBP_SHIFT (9U)
/*! OBP
* 0b0..No odd byte parity.
* 0b1..Generate random data with odd byte parity.
*/
#define CAAM_CC1MR_RNG_OBP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_OBP_SHIFT)) & CAAM_CC1MR_RNG_OBP_MASK)
#define CAAM_CC1MR_RNG_PS_MASK (0x400U)
#define CAAM_CC1MR_RNG_PS_SHIFT (10U)
/*! PS
* 0b0..No personalization string is included.
* 0b1..A personalization string is included.
*/
#define CAAM_CC1MR_RNG_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_PS_SHIFT)) & CAAM_CC1MR_RNG_PS_MASK)
#define CAAM_CC1MR_RNG_AI_MASK (0x800U)
#define CAAM_CC1MR_RNG_AI_SHIFT (11U)
/*! AI
* 0b0..No additional entropy input has been provided.
* 0b1..Additional entropy input has been provided.
*/
#define CAAM_CC1MR_RNG_AI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_AI_SHIFT)) & CAAM_CC1MR_RNG_AI_MASK)
#define CAAM_CC1MR_RNG_SK_MASK (0x1000U)
#define CAAM_CC1MR_RNG_SK_SHIFT (12U)
/*! SK
* 0b0..The destination for the RNG data is specified by the FIFO STORE command.
* 0b1..The RNG data will go to the JDKEKR, TDKEKR and DSKR.
*/
#define CAAM_CC1MR_RNG_SK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_SK_SHIFT)) & CAAM_CC1MR_RNG_SK_MASK)
#define CAAM_CC1MR_RNG_ALG_MASK (0xFF0000U)
#define CAAM_CC1MR_RNG_ALG_SHIFT (16U)
/*! ALG
* 0b01010000..RNG
*/
#define CAAM_CC1MR_RNG_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1MR_RNG_ALG_SHIFT)) & CAAM_CC1MR_RNG_ALG_MASK)
/*! @} */
/* The count of CAAM_CC1MR_RNG */
#define CAAM_CC1MR_RNG_COUNT (1U)
/*! @name CC1KSR - CCB 0 Class 1 Key Size Register */
/*! @{ */
#define CAAM_CC1KSR_C1KS_MASK (0x7FU)
#define CAAM_CC1KSR_C1KS_SHIFT (0U)
#define CAAM_CC1KSR_C1KS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KSR_C1KS_SHIFT)) & CAAM_CC1KSR_C1KS_MASK)
/*! @} */
/* The count of CAAM_CC1KSR */
#define CAAM_CC1KSR_COUNT (1U)
/*! @name CC1DSR - CCB 0 Class 1 Data Size Register */
/*! @{ */
#define CAAM_CC1DSR_C1DS_MASK (0xFFFFFFFFU)
#define CAAM_CC1DSR_C1DS_SHIFT (0U)
#define CAAM_CC1DSR_C1DS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1DS_SHIFT)) & CAAM_CC1DSR_C1DS_MASK)
#define CAAM_CC1DSR_C1CY_MASK (0x100000000U)
#define CAAM_CC1DSR_C1CY_SHIFT (32U)
/*! C1CY
* 0b0..No carry out of the C1 Data Size Reg.
* 0b1..There was a carry out of the C1 Data Size Reg.
*/
#define CAAM_CC1DSR_C1CY(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_C1CY_SHIFT)) & CAAM_CC1DSR_C1CY_MASK)
#define CAAM_CC1DSR_NUMBITS_MASK (0xE000000000000000U)
#define CAAM_CC1DSR_NUMBITS_SHIFT (61U)
#define CAAM_CC1DSR_NUMBITS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC1DSR_NUMBITS_SHIFT)) & CAAM_CC1DSR_NUMBITS_MASK)
/*! @} */
/* The count of CAAM_CC1DSR */
#define CAAM_CC1DSR_COUNT (1U)
/*! @name CC1ICVSR - CCB 0 Class 1 ICV Size Register */
/*! @{ */
#define CAAM_CC1ICVSR_C1ICVS_MASK (0x1FU)
#define CAAM_CC1ICVSR_C1ICVS_SHIFT (0U)
#define CAAM_CC1ICVSR_C1ICVS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1ICVSR_C1ICVS_SHIFT)) & CAAM_CC1ICVSR_C1ICVS_MASK)
/*! @} */
/* The count of CAAM_CC1ICVSR */
#define CAAM_CC1ICVSR_COUNT (1U)
/*! @name CCCTRL - CCB 0 CHA Control Register */
/*! @{ */
#define CAAM_CCCTRL_CCB_MASK (0x1U)
#define CAAM_CCCTRL_CCB_SHIFT (0U)
/*! CCB
* 0b0..Do Not Reset
* 0b1..Reset CCB
*/
#define CAAM_CCCTRL_CCB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CCB_SHIFT)) & CAAM_CCCTRL_CCB_MASK)
#define CAAM_CCCTRL_AES_MASK (0x2U)
#define CAAM_CCCTRL_AES_SHIFT (1U)
/*! AES
* 0b0..Do Not Reset
* 0b1..Reset AES Accelerator
*/
#define CAAM_CCCTRL_AES(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_AES_SHIFT)) & CAAM_CCCTRL_AES_MASK)
#define CAAM_CCCTRL_DES_MASK (0x4U)
#define CAAM_CCCTRL_DES_SHIFT (2U)
/*! DES
* 0b0..Do Not Reset
* 0b1..Reset DES Accelerator
*/
#define CAAM_CCCTRL_DES(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_DES_SHIFT)) & CAAM_CCCTRL_DES_MASK)
#define CAAM_CCCTRL_PK_MASK (0x40U)
#define CAAM_CCCTRL_PK_SHIFT (6U)
/*! PK
* 0b0..Do Not Reset
* 0b1..Reset Public Key Hardware Accelerator
*/
#define CAAM_CCCTRL_PK(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_PK_SHIFT)) & CAAM_CCCTRL_PK_MASK)
#define CAAM_CCCTRL_MD_MASK (0x80U)
#define CAAM_CCCTRL_MD_SHIFT (7U)
/*! MD
* 0b0..Do Not Reset
* 0b1..Reset Message Digest Hardware Accelerator
*/
#define CAAM_CCCTRL_MD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_MD_SHIFT)) & CAAM_CCCTRL_MD_MASK)
#define CAAM_CCCTRL_CRC_MASK (0x100U)
#define CAAM_CCCTRL_CRC_SHIFT (8U)
/*! CRC
* 0b0..Do Not Reset
* 0b1..Reset CRC Accelerator
*/
#define CAAM_CCCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_CRC_SHIFT)) & CAAM_CCCTRL_CRC_MASK)
#define CAAM_CCCTRL_RNG_MASK (0x200U)
#define CAAM_CCCTRL_RNG_SHIFT (9U)
/*! RNG
* 0b0..Do Not Reset
* 0b1..Reset Random Number Generator Block.
*/
#define CAAM_CCCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_RNG_SHIFT)) & CAAM_CCCTRL_RNG_MASK)
#define CAAM_CCCTRL_UA0_MASK (0x10000U)
#define CAAM_CCCTRL_UA0_SHIFT (16U)
/*! UA0
* 0b0..Don't unload the PKHA A0 Memory.
* 0b1..Unload the PKHA A0 Memory into OFIFO.
*/
#define CAAM_CCCTRL_UA0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA0_SHIFT)) & CAAM_CCCTRL_UA0_MASK)
#define CAAM_CCCTRL_UA1_MASK (0x20000U)
#define CAAM_CCCTRL_UA1_SHIFT (17U)
/*! UA1
* 0b0..Don't unload the PKHA A1 Memory.
* 0b1..Unload the PKHA A1 Memory into OFIFO.
*/
#define CAAM_CCCTRL_UA1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA1_SHIFT)) & CAAM_CCCTRL_UA1_MASK)
#define CAAM_CCCTRL_UA2_MASK (0x40000U)
#define CAAM_CCCTRL_UA2_SHIFT (18U)
/*! UA2
* 0b0..Don't unload the PKHA A2 Memory.
* 0b1..Unload the PKHA A2 Memory into OFIFO.
*/
#define CAAM_CCCTRL_UA2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA2_SHIFT)) & CAAM_CCCTRL_UA2_MASK)
#define CAAM_CCCTRL_UA3_MASK (0x80000U)
#define CAAM_CCCTRL_UA3_SHIFT (19U)
/*! UA3
* 0b0..Don't unload the PKHA A3 Memory.
* 0b1..Unload the PKHA A3 Memory into OFIFO.
*/
#define CAAM_CCCTRL_UA3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA3_SHIFT)) & CAAM_CCCTRL_UA3_MASK)
#define CAAM_CCCTRL_UB0_MASK (0x100000U)
#define CAAM_CCCTRL_UB0_SHIFT (20U)
/*! UB0
* 0b0..Don't unload the PKHA B0 Memory.
* 0b1..Unload the PKHA B0 Memory into OFIFO.
*/
#define CAAM_CCCTRL_UB0(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB0_SHIFT)) & CAAM_CCCTRL_UB0_MASK)
#define CAAM_CCCTRL_UB1_MASK (0x200000U)
#define CAAM_CCCTRL_UB1_SHIFT (21U)
/*! UB1
* 0b0..Don't unload the PKHA B1 Memory.
* 0b1..Unload the PKHA B1 Memory into OFIFO.
*/
#define CAAM_CCCTRL_UB1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB1_SHIFT)) & CAAM_CCCTRL_UB1_MASK)
#define CAAM_CCCTRL_UB2_MASK (0x400000U)
#define CAAM_CCCTRL_UB2_SHIFT (22U)
/*! UB2
* 0b0..Don't unload the PKHA B2 Memory.
* 0b1..Unload the PKHA B2 Memory into OFIFO.
*/
#define CAAM_CCCTRL_UB2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB2_SHIFT)) & CAAM_CCCTRL_UB2_MASK)
#define CAAM_CCCTRL_UB3_MASK (0x800000U)
#define CAAM_CCCTRL_UB3_SHIFT (23U)
/*! UB3
* 0b0..Don't unload the PKHA B3 Memory.
* 0b1..Unload the PKHA B3 Memory into OFIFO.
*/
#define CAAM_CCCTRL_UB3(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB3_SHIFT)) & CAAM_CCCTRL_UB3_MASK)
#define CAAM_CCCTRL_UN_MASK (0x1000000U)
#define CAAM_CCCTRL_UN_SHIFT (24U)
/*! UN
* 0b0..Don't unload the PKHA N Memory.
* 0b1..Unload the PKHA N Memory into OFIFO.
*/
#define CAAM_CCCTRL_UN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UN_SHIFT)) & CAAM_CCCTRL_UN_MASK)
#define CAAM_CCCTRL_UA_MASK (0x4000000U)
#define CAAM_CCCTRL_UA_SHIFT (26U)
/*! UA
* 0b0..Don't unload the PKHA A Memory.
* 0b1..Unload the PKHA A Memory into OFIFO.
*/
#define CAAM_CCCTRL_UA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UA_SHIFT)) & CAAM_CCCTRL_UA_MASK)
#define CAAM_CCCTRL_UB_MASK (0x8000000U)
#define CAAM_CCCTRL_UB_SHIFT (27U)
/*! UB
* 0b0..Don't unload the PKHA B Memory.
* 0b1..Unload the PKHA B Memory into OFIFO.
*/
#define CAAM_CCCTRL_UB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCCTRL_UB_SHIFT)) & CAAM_CCCTRL_UB_MASK)
/*! @} */
/* The count of CAAM_CCCTRL */
#define CAAM_CCCTRL_COUNT (1U)
/*! @name CICTL - CCB 0 Interrupt Control Register */
/*! @{ */
#define CAAM_CICTL_ADI_MASK (0x2U)
#define CAAM_CICTL_ADI_SHIFT (1U)
#define CAAM_CICTL_ADI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_ADI_SHIFT)) & CAAM_CICTL_ADI_MASK)
#define CAAM_CICTL_DDI_MASK (0x4U)
#define CAAM_CICTL_DDI_SHIFT (2U)
#define CAAM_CICTL_DDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DDI_SHIFT)) & CAAM_CICTL_DDI_MASK)
#define CAAM_CICTL_PDI_MASK (0x40U)
#define CAAM_CICTL_PDI_SHIFT (6U)
#define CAAM_CICTL_PDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PDI_SHIFT)) & CAAM_CICTL_PDI_MASK)
#define CAAM_CICTL_MDI_MASK (0x80U)
#define CAAM_CICTL_MDI_SHIFT (7U)
#define CAAM_CICTL_MDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MDI_SHIFT)) & CAAM_CICTL_MDI_MASK)
#define CAAM_CICTL_CDI_MASK (0x100U)
#define CAAM_CICTL_CDI_SHIFT (8U)
#define CAAM_CICTL_CDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CDI_SHIFT)) & CAAM_CICTL_CDI_MASK)
#define CAAM_CICTL_RNDI_MASK (0x200U)
#define CAAM_CICTL_RNDI_SHIFT (9U)
#define CAAM_CICTL_RNDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNDI_SHIFT)) & CAAM_CICTL_RNDI_MASK)
#define CAAM_CICTL_AEI_MASK (0x20000U)
#define CAAM_CICTL_AEI_SHIFT (17U)
/*! AEI
* 0b0..No AESA error detected
* 0b1..AESA error detected
*/
#define CAAM_CICTL_AEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_AEI_SHIFT)) & CAAM_CICTL_AEI_MASK)
#define CAAM_CICTL_DEI_MASK (0x40000U)
#define CAAM_CICTL_DEI_SHIFT (18U)
/*! DEI
* 0b0..No DESA error detected
* 0b1..DESA error detected
*/
#define CAAM_CICTL_DEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_DEI_SHIFT)) & CAAM_CICTL_DEI_MASK)
#define CAAM_CICTL_PEI_MASK (0x400000U)
#define CAAM_CICTL_PEI_SHIFT (22U)
/*! PEI
* 0b0..No PKHA error detected
* 0b1..PKHA error detected
*/
#define CAAM_CICTL_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_PEI_SHIFT)) & CAAM_CICTL_PEI_MASK)
#define CAAM_CICTL_MEI_MASK (0x800000U)
#define CAAM_CICTL_MEI_SHIFT (23U)
/*! MEI
* 0b0..No MDHA error detected
* 0b1..MDHA error detected
*/
#define CAAM_CICTL_MEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_MEI_SHIFT)) & CAAM_CICTL_MEI_MASK)
#define CAAM_CICTL_CEI_MASK (0x1000000U)
#define CAAM_CICTL_CEI_SHIFT (24U)
/*! CEI
* 0b0..No CRCA error detected
* 0b1..CRCA error detected
*/
#define CAAM_CICTL_CEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_CEI_SHIFT)) & CAAM_CICTL_CEI_MASK)
#define CAAM_CICTL_RNEI_MASK (0x2000000U)
#define CAAM_CICTL_RNEI_SHIFT (25U)
/*! RNEI
* 0b0..No RNG error detected
* 0b1..RNG error detected
*/
#define CAAM_CICTL_RNEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CICTL_RNEI_SHIFT)) & CAAM_CICTL_RNEI_MASK)
/*! @} */
/* The count of CAAM_CICTL */
#define CAAM_CICTL_COUNT (1U)
/*! @name CCWR - CCB 0 Clear Written Register */
/*! @{ */
#define CAAM_CCWR_C1M_MASK (0x1U)
#define CAAM_CCWR_C1M_SHIFT (0U)
/*! C1M
* 0b0..Don't clear the Class 1 Mode Register.
* 0b1..Clear the Class 1 Mode Register.
*/
#define CAAM_CCWR_C1M(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1M_SHIFT)) & CAAM_CCWR_C1M_MASK)
#define CAAM_CCWR_C1DS_MASK (0x4U)
#define CAAM_CCWR_C1DS_SHIFT (2U)
/*! C1DS
* 0b0..Don't clear the Class 1 Data Size Register.
* 0b1..Clear the Class 1 Data Size Register.
*/
#define CAAM_CCWR_C1DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1DS_SHIFT)) & CAAM_CCWR_C1DS_MASK)
#define CAAM_CCWR_C1ICV_MASK (0x8U)
#define CAAM_CCWR_C1ICV_SHIFT (3U)
/*! C1ICV
* 0b0..Don't clear the Class 1 ICV Size Register.
* 0b1..Clear the Class 1 ICV Size Register.
*/
#define CAAM_CCWR_C1ICV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1ICV_SHIFT)) & CAAM_CCWR_C1ICV_MASK)
#define CAAM_CCWR_C1C_MASK (0x20U)
#define CAAM_CCWR_C1C_SHIFT (5U)
/*! C1C
* 0b0..Don't clear the Class 1 Context Register.
* 0b1..Clear the Class 1 Context Register.
*/
#define CAAM_CCWR_C1C(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1C_SHIFT)) & CAAM_CCWR_C1C_MASK)
#define CAAM_CCWR_C1K_MASK (0x40U)
#define CAAM_CCWR_C1K_SHIFT (6U)
/*! C1K
* 0b0..Don't clear the Class 1 Key Register.
* 0b1..Clear the Class 1 Key Register.
*/
#define CAAM_CCWR_C1K(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1K_SHIFT)) & CAAM_CCWR_C1K_MASK)
#define CAAM_CCWR_CPKA_MASK (0x1000U)
#define CAAM_CCWR_CPKA_SHIFT (12U)
/*! CPKA
* 0b0..Don't clear the PKHA A Size Register.
* 0b1..Clear the PKHA A Size Register.
*/
#define CAAM_CCWR_CPKA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKA_SHIFT)) & CAAM_CCWR_CPKA_MASK)
#define CAAM_CCWR_CPKB_MASK (0x2000U)
#define CAAM_CCWR_CPKB_SHIFT (13U)
/*! CPKB
* 0b0..Don't clear the PKHA B Size Register.
* 0b1..Clear the PKHA B Size Register.
*/
#define CAAM_CCWR_CPKB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKB_SHIFT)) & CAAM_CCWR_CPKB_MASK)
#define CAAM_CCWR_CPKN_MASK (0x4000U)
#define CAAM_CCWR_CPKN_SHIFT (14U)
/*! CPKN
* 0b0..Don't clear the PKHA N Size Register.
* 0b1..Clear the PKHA N Size Register.
*/
#define CAAM_CCWR_CPKN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKN_SHIFT)) & CAAM_CCWR_CPKN_MASK)
#define CAAM_CCWR_CPKE_MASK (0x8000U)
#define CAAM_CCWR_CPKE_SHIFT (15U)
/*! CPKE
* 0b0..Don't clear the PKHA E Size Register..
* 0b1..Clear the PKHA E Size Register.
*/
#define CAAM_CCWR_CPKE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CPKE_SHIFT)) & CAAM_CCWR_CPKE_MASK)
#define CAAM_CCWR_C2M_MASK (0x10000U)
#define CAAM_CCWR_C2M_SHIFT (16U)
/*! C2M
* 0b0..Don't clear the Class 2 Mode Register.
* 0b1..Clear the Class 2 Mode Register.
*/
#define CAAM_CCWR_C2M(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2M_SHIFT)) & CAAM_CCWR_C2M_MASK)
#define CAAM_CCWR_C2DS_MASK (0x40000U)
#define CAAM_CCWR_C2DS_SHIFT (18U)
/*! C2DS
* 0b0..Don't clear the Class 2 Data Size Register.
* 0b1..Clear the Class 2 Data Size Register.
*/
#define CAAM_CCWR_C2DS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2DS_SHIFT)) & CAAM_CCWR_C2DS_MASK)
#define CAAM_CCWR_C2C_MASK (0x200000U)
#define CAAM_CCWR_C2C_SHIFT (21U)
/*! C2C
* 0b0..Don't clear the Class 2 Context Register.
* 0b1..Clear the Class 2 Context Register.
*/
#define CAAM_CCWR_C2C(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2C_SHIFT)) & CAAM_CCWR_C2C_MASK)
#define CAAM_CCWR_C2K_MASK (0x400000U)
#define CAAM_CCWR_C2K_SHIFT (22U)
/*! C2K
* 0b0..Don't clear the Class 2 Key Register.
* 0b1..Clear the Class 2 Key Register.
*/
#define CAAM_CCWR_C2K(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2K_SHIFT)) & CAAM_CCWR_C2K_MASK)
#define CAAM_CCWR_CDS_MASK (0x2000000U)
#define CAAM_CCWR_CDS_SHIFT (25U)
/*! CDS
* 0b0..Don't clear the shared descriptor signal.
* 0b1..Clear the shared descriptor signal.
*/
#define CAAM_CCWR_CDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CDS_SHIFT)) & CAAM_CCWR_CDS_MASK)
#define CAAM_CCWR_C2D_MASK (0x4000000U)
#define CAAM_CCWR_C2D_SHIFT (26U)
/*! C2D
* 0b0..Don't clear the Class 2 done interrrupt.
* 0b1..Clear the Class 2 done interrrupt.
*/
#define CAAM_CCWR_C2D(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2D_SHIFT)) & CAAM_CCWR_C2D_MASK)
#define CAAM_CCWR_C1D_MASK (0x8000000U)
#define CAAM_CCWR_C1D_SHIFT (27U)
/*! C1D
* 0b0..Don't clear the Class 1 done interrrupt.
* 0b1..Clear the Class 1 done interrrupt.
*/
#define CAAM_CCWR_C1D(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1D_SHIFT)) & CAAM_CCWR_C1D_MASK)
#define CAAM_CCWR_C2RST_MASK (0x10000000U)
#define CAAM_CCWR_C2RST_SHIFT (28U)
/*! C2RST
* 0b0..Don't reset the Class 2 CHA.
* 0b1..Reset the Class 2 CHA.
*/
#define CAAM_CCWR_C2RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C2RST_SHIFT)) & CAAM_CCWR_C2RST_MASK)
#define CAAM_CCWR_C1RST_MASK (0x20000000U)
#define CAAM_CCWR_C1RST_SHIFT (29U)
/*! C1RST
* 0b0..Don't reset the Class 1 CHA.
* 0b1..Reset the Class 1 CHA.
*/
#define CAAM_CCWR_C1RST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_C1RST_SHIFT)) & CAAM_CCWR_C1RST_MASK)
#define CAAM_CCWR_COF_MASK (0x40000000U)
#define CAAM_CCWR_COF_SHIFT (30U)
/*! COF
* 0b0..Don't clear the OFIFO.
* 0b1..Clear the OFIFO.
*/
#define CAAM_CCWR_COF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_COF_SHIFT)) & CAAM_CCWR_COF_MASK)
#define CAAM_CCWR_CIF_MASK (0x80000000U)
#define CAAM_CCWR_CIF_SHIFT (31U)
/*! CIF
* 0b0..Don't clear the IFIFO.
* 0b1..Clear the IFIFO.
*/
#define CAAM_CCWR_CIF(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCWR_CIF_SHIFT)) & CAAM_CCWR_CIF_MASK)
/*! @} */
/* The count of CAAM_CCWR */
#define CAAM_CCWR_COUNT (1U)
/*! @name CCSTA_MS - CCB 0 Status and Error Register, most-significant half */
/*! @{ */
#define CAAM_CCSTA_MS_ERRID1_MASK (0xFU)
#define CAAM_CCSTA_MS_ERRID1_SHIFT (0U)
/*! ERRID1
* 0b0001..Mode Error
* 0b0010..Data Size Error, including PKHA N Memory Size Error
* 0b0011..Key Size Error, including PKHA E Memory Size Error
* 0b0100..PKHA A Memory Size Error
* 0b0101..PKHA B Memory Size Error
* 0b0110..Data Arrived out of Sequence Error
* 0b0111..PKHA Divide by Zero Error
* 0b1000..PKHA Modulus Even Error
* 0b1001..DES Key Parity Error
* 0b1010..ICV Check Failed
* 0b1011..Internal Hardware Failure
* 0b1100..CCM AAD Size Error (either 1. AAD flag in B0 =1 and no AAD type provided, 2. AAD flag in B0 = 0 and
* AAD provided, or 3. AAD flag in B0 =1 and not enough AAD provided - expecting more based on AAD size.)
* 0b1101..Class 1 CHA is not reset
* 0b1110..Invalid CHA combination was selected
* 0b1111..Invalid CHA Selected
*/
#define CAAM_CCSTA_MS_ERRID1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID1_SHIFT)) & CAAM_CCSTA_MS_ERRID1_MASK)
#define CAAM_CCSTA_MS_CL1_MASK (0xF000U)
#define CAAM_CCSTA_MS_CL1_SHIFT (12U)
/*! CL1
* 0b0001..AES
* 0b0010..DES
* 0b0101..RNG
* 0b1000..Public Key
*/
#define CAAM_CCSTA_MS_CL1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL1_SHIFT)) & CAAM_CCSTA_MS_CL1_MASK)
#define CAAM_CCSTA_MS_ERRID2_MASK (0xF0000U)
#define CAAM_CCSTA_MS_ERRID2_SHIFT (16U)
/*! ERRID2
* 0b0001..Mode Error
* 0b0010..Data Size Error
* 0b0011..Key Size Error
* 0b0110..Data Arrived out of Sequence Error
* 0b1010..ICV Check Failed
* 0b1011..Internal Hardware Failure
* 0b1110..Invalid CHA combination was selected.
* 0b1111..Invalid CHA Selected
*/
#define CAAM_CCSTA_MS_ERRID2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_ERRID2_SHIFT)) & CAAM_CCSTA_MS_ERRID2_MASK)
#define CAAM_CCSTA_MS_CL2_MASK (0xF0000000U)
#define CAAM_CCSTA_MS_CL2_SHIFT (28U)
/*! CL2
* 0b0100..MD5, SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 and SHA-512/224, SHA-512/256
* 0b1001..CRC
*/
#define CAAM_CCSTA_MS_CL2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_MS_CL2_SHIFT)) & CAAM_CCSTA_MS_CL2_MASK)
/*! @} */
/* The count of CAAM_CCSTA_MS */
#define CAAM_CCSTA_MS_COUNT (1U)
/*! @name CCSTA_LS - CCB 0 Status and Error Register, least-significant half */
/*! @{ */
#define CAAM_CCSTA_LS_AB_MASK (0x2U)
#define CAAM_CCSTA_LS_AB_SHIFT (1U)
/*! AB
* 0b0..AESA Idle
* 0b1..AESA Busy
*/
#define CAAM_CCSTA_LS_AB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_AB_SHIFT)) & CAAM_CCSTA_LS_AB_MASK)
#define CAAM_CCSTA_LS_DB_MASK (0x4U)
#define CAAM_CCSTA_LS_DB_SHIFT (2U)
/*! DB
* 0b0..DESA Idle
* 0b1..DESA Busy
*/
#define CAAM_CCSTA_LS_DB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_DB_SHIFT)) & CAAM_CCSTA_LS_DB_MASK)
#define CAAM_CCSTA_LS_PB_MASK (0x40U)
#define CAAM_CCSTA_LS_PB_SHIFT (6U)
/*! PB
* 0b0..PKHA Idle
* 0b1..PKHA Busy
*/
#define CAAM_CCSTA_LS_PB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PB_SHIFT)) & CAAM_CCSTA_LS_PB_MASK)
#define CAAM_CCSTA_LS_MB_MASK (0x80U)
#define CAAM_CCSTA_LS_MB_SHIFT (7U)
/*! MB
* 0b0..MDHA Idle
* 0b1..MDHA Busy
*/
#define CAAM_CCSTA_LS_MB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_MB_SHIFT)) & CAAM_CCSTA_LS_MB_MASK)
#define CAAM_CCSTA_LS_CB_MASK (0x100U)
#define CAAM_CCSTA_LS_CB_SHIFT (8U)
/*! CB
* 0b0..CRCA Idle
* 0b1..CRCA Busy
*/
#define CAAM_CCSTA_LS_CB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_CB_SHIFT)) & CAAM_CCSTA_LS_CB_MASK)
#define CAAM_CCSTA_LS_RNB_MASK (0x200U)
#define CAAM_CCSTA_LS_RNB_SHIFT (9U)
/*! RNB
* 0b0..RNG Idle
* 0b1..RNG Busy
*/
#define CAAM_CCSTA_LS_RNB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_RNB_SHIFT)) & CAAM_CCSTA_LS_RNB_MASK)
#define CAAM_CCSTA_LS_PDI_MASK (0x10000U)
#define CAAM_CCSTA_LS_PDI_SHIFT (16U)
/*! PDI
* 0b0..Not Done
* 0b1..Done Interrupt
*/
#define CAAM_CCSTA_LS_PDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PDI_SHIFT)) & CAAM_CCSTA_LS_PDI_MASK)
#define CAAM_CCSTA_LS_SDI_MASK (0x20000U)
#define CAAM_CCSTA_LS_SDI_SHIFT (17U)
/*! SDI
* 0b0..Not Done
* 0b1..Done Interrupt
*/
#define CAAM_CCSTA_LS_SDI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SDI_SHIFT)) & CAAM_CCSTA_LS_SDI_MASK)
#define CAAM_CCSTA_LS_PEI_MASK (0x100000U)
#define CAAM_CCSTA_LS_PEI_SHIFT (20U)
/*! PEI
* 0b0..No Error
* 0b1..Error Interrupt
*/
#define CAAM_CCSTA_LS_PEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PEI_SHIFT)) & CAAM_CCSTA_LS_PEI_MASK)
#define CAAM_CCSTA_LS_SEI_MASK (0x200000U)
#define CAAM_CCSTA_LS_SEI_SHIFT (21U)
/*! SEI
* 0b0..No Error
* 0b1..Error Interrupt
*/
#define CAAM_CCSTA_LS_SEI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_SEI_SHIFT)) & CAAM_CCSTA_LS_SEI_MASK)
#define CAAM_CCSTA_LS_PRM_MASK (0x10000000U)
#define CAAM_CCSTA_LS_PRM_SHIFT (28U)
/*! PRM
* 0b0..The given number is NOT prime.
* 0b1..The given number is probably prime.
*/
#define CAAM_CCSTA_LS_PRM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PRM_SHIFT)) & CAAM_CCSTA_LS_PRM_MASK)
#define CAAM_CCSTA_LS_GCD_MASK (0x20000000U)
#define CAAM_CCSTA_LS_GCD_SHIFT (29U)
/*! GCD
* 0b0..The greatest common divisor of two numbers is NOT one.
* 0b1..The greatest common divisor of two numbers is one.
*/
#define CAAM_CCSTA_LS_GCD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_GCD_SHIFT)) & CAAM_CCSTA_LS_GCD_MASK)
#define CAAM_CCSTA_LS_PIZ_MASK (0x40000000U)
#define CAAM_CCSTA_LS_PIZ_SHIFT (30U)
/*! PIZ
* 0b0..The result of a Public Key operation is not zero.
* 0b1..The result of a Public Key operation is zero.
*/
#define CAAM_CCSTA_LS_PIZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CCSTA_LS_PIZ_SHIFT)) & CAAM_CCSTA_LS_PIZ_MASK)
/*! @} */
/* The count of CAAM_CCSTA_LS */
#define CAAM_CCSTA_LS_COUNT (1U)
/*! @name CC1AADSZR - CCB 0 Class 1 AAD Size Register */
/*! @{ */
#define CAAM_CC1AADSZR_AASZ_MASK (0xFU)
#define CAAM_CC1AADSZR_AASZ_SHIFT (0U)
#define CAAM_CC1AADSZR_AASZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1AADSZR_AASZ_SHIFT)) & CAAM_CC1AADSZR_AASZ_MASK)
/*! @} */
/* The count of CAAM_CC1AADSZR */
#define CAAM_CC1AADSZR_COUNT (1U)
/*! @name CC1IVSZR - CCB 0 Class 1 IV Size Register */
/*! @{ */
#define CAAM_CC1IVSZR_IVSZ_MASK (0xFU)
#define CAAM_CC1IVSZR_IVSZ_SHIFT (0U)
#define CAAM_CC1IVSZR_IVSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1IVSZR_IVSZ_SHIFT)) & CAAM_CC1IVSZR_IVSZ_MASK)
/*! @} */
/* The count of CAAM_CC1IVSZR */
#define CAAM_CC1IVSZR_COUNT (1U)
/*! @name CPKASZR - PKHA A Size Register */
/*! @{ */
#define CAAM_CPKASZR_PKASZ_MASK (0x3FFU)
#define CAAM_CPKASZR_PKASZ_SHIFT (0U)
#define CAAM_CPKASZR_PKASZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKASZR_PKASZ_SHIFT)) & CAAM_CPKASZR_PKASZ_MASK)
/*! @} */
/* The count of CAAM_CPKASZR */
#define CAAM_CPKASZR_COUNT (1U)
/*! @name CPKBSZR - PKHA B Size Register */
/*! @{ */
#define CAAM_CPKBSZR_PKBSZ_MASK (0x3FFU)
#define CAAM_CPKBSZR_PKBSZ_SHIFT (0U)
#define CAAM_CPKBSZR_PKBSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKBSZR_PKBSZ_SHIFT)) & CAAM_CPKBSZR_PKBSZ_MASK)
/*! @} */
/* The count of CAAM_CPKBSZR */
#define CAAM_CPKBSZR_COUNT (1U)
/*! @name CPKNSZR - PKHA N Size Register */
/*! @{ */
#define CAAM_CPKNSZR_PKNSZ_MASK (0x3FFU)
#define CAAM_CPKNSZR_PKNSZ_SHIFT (0U)
#define CAAM_CPKNSZR_PKNSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKNSZR_PKNSZ_SHIFT)) & CAAM_CPKNSZR_PKNSZ_MASK)
/*! @} */
/* The count of CAAM_CPKNSZR */
#define CAAM_CPKNSZR_COUNT (1U)
/*! @name CPKESZR - PKHA E Size Register */
/*! @{ */
#define CAAM_CPKESZR_PKESZ_MASK (0x3FFU)
#define CAAM_CPKESZR_PKESZ_SHIFT (0U)
#define CAAM_CPKESZR_PKESZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CPKESZR_PKESZ_SHIFT)) & CAAM_CPKESZR_PKESZ_MASK)
/*! @} */
/* The count of CAAM_CPKESZR */
#define CAAM_CPKESZR_COUNT (1U)
/*! @name CC1CTXR - CCB 0 Class 1 Context Register Word 0..CCB 0 Class 1 Context Register Word 15 */
/*! @{ */
#define CAAM_CC1CTXR_C1CTX_MASK (0xFFFFFFFFU)
#define CAAM_CC1CTXR_C1CTX_SHIFT (0U)
#define CAAM_CC1CTXR_C1CTX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1CTXR_C1CTX_SHIFT)) & CAAM_CC1CTXR_C1CTX_MASK)
/*! @} */
/* The count of CAAM_CC1CTXR */
#define CAAM_CC1CTXR_COUNT (1U)
/* The count of CAAM_CC1CTXR */
#define CAAM_CC1CTXR_COUNT2 (16U)
/*! @name CC1KR - CCB 0 Class 1 Key Registers Word 0..CCB 0 Class 1 Key Registers Word 7 */
/*! @{ */
#define CAAM_CC1KR_C1KEY_MASK (0xFFFFFFFFU)
#define CAAM_CC1KR_C1KEY_SHIFT (0U)
#define CAAM_CC1KR_C1KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC1KR_C1KEY_SHIFT)) & CAAM_CC1KR_C1KEY_MASK)
/*! @} */
/* The count of CAAM_CC1KR */
#define CAAM_CC1KR_COUNT (1U)
/* The count of CAAM_CC1KR */
#define CAAM_CC1KR_COUNT2 (8U)
/*! @name CC2MR - CCB 0 Class 2 Mode Register */
/*! @{ */
#define CAAM_CC2MR_AP_MASK (0x1U)
#define CAAM_CC2MR_AP_SHIFT (0U)
/*! AP
* 0b0..Authenticate
* 0b1..Protect
*/
#define CAAM_CC2MR_AP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AP_SHIFT)) & CAAM_CC2MR_AP_MASK)
#define CAAM_CC2MR_ICV_MASK (0x2U)
#define CAAM_CC2MR_ICV_SHIFT (1U)
/*! ICV
* 0b0..Don't compare the calculated ICV against a received ICV.
* 0b1..Compare the calculated ICV against a received ICV.
*/
#define CAAM_CC2MR_ICV(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ICV_SHIFT)) & CAAM_CC2MR_ICV_MASK)
#define CAAM_CC2MR_AS_MASK (0xCU)
#define CAAM_CC2MR_AS_SHIFT (2U)
/*! AS
* 0b00..Update.
* 0b01..Initialize.
* 0b10..Finalize.
* 0b11..Initialize/Finalize.
*/
#define CAAM_CC2MR_AS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AS_SHIFT)) & CAAM_CC2MR_AS_MASK)
#define CAAM_CC2MR_AAI_MASK (0x1FF0U)
#define CAAM_CC2MR_AAI_SHIFT (4U)
#define CAAM_CC2MR_AAI(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_AAI_SHIFT)) & CAAM_CC2MR_AAI_MASK)
#define CAAM_CC2MR_ALG_MASK (0xFF0000U)
#define CAAM_CC2MR_ALG_SHIFT (16U)
/*! ALG
* 0b01000000..MD5
* 0b01000001..SHA-1
* 0b01000010..SHA-224
* 0b01000011..SHA-256
* 0b01000100..SHA-384
* 0b01000101..SHA-512
* 0b01000110..SHA-512/224
* 0b01000111..SHA-512/256
* 0b10010000..CRC
*/
#define CAAM_CC2MR_ALG(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2MR_ALG_SHIFT)) & CAAM_CC2MR_ALG_MASK)
/*! @} */
/* The count of CAAM_CC2MR */
#define CAAM_CC2MR_COUNT (1U)
/*! @name CC2KSR - CCB 0 Class 2 Key Size Register */
/*! @{ */
#define CAAM_CC2KSR_C2KS_MASK (0xFFU)
#define CAAM_CC2KSR_C2KS_SHIFT (0U)
#define CAAM_CC2KSR_C2KS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KSR_C2KS_SHIFT)) & CAAM_CC2KSR_C2KS_MASK)
/*! @} */
/* The count of CAAM_CC2KSR */
#define CAAM_CC2KSR_COUNT (1U)
/*! @name CC2DSR - CCB 0 Class 2 Data Size Register */
/*! @{ */
#define CAAM_CC2DSR_C2DS_MASK (0xFFFFFFFFU)
#define CAAM_CC2DSR_C2DS_SHIFT (0U)
#define CAAM_CC2DSR_C2DS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2DS_SHIFT)) & CAAM_CC2DSR_C2DS_MASK)
#define CAAM_CC2DSR_C2CY_MASK (0x100000000U)
#define CAAM_CC2DSR_C2CY_SHIFT (32U)
/*! C2CY
* 0b0..A write to the Class 2 Data Size Register did not cause a carry.
* 0b1..A write to the Class 2 Data Size Register caused a carry.
*/
#define CAAM_CC2DSR_C2CY(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_C2CY_SHIFT)) & CAAM_CC2DSR_C2CY_MASK)
#define CAAM_CC2DSR_NUMBITS_MASK (0xE000000000000000U)
#define CAAM_CC2DSR_NUMBITS_SHIFT (61U)
#define CAAM_CC2DSR_NUMBITS(x) (((uint64_t)(((uint64_t)(x)) << CAAM_CC2DSR_NUMBITS_SHIFT)) & CAAM_CC2DSR_NUMBITS_MASK)
/*! @} */
/* The count of CAAM_CC2DSR */
#define CAAM_CC2DSR_COUNT (1U)
/*! @name CC2ICVSZR - CCB 0 Class 2 ICV Size Register */
/*! @{ */
#define CAAM_CC2ICVSZR_ICVSZ_MASK (0xFU)
#define CAAM_CC2ICVSZR_ICVSZ_SHIFT (0U)
#define CAAM_CC2ICVSZR_ICVSZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2ICVSZR_ICVSZ_SHIFT)) & CAAM_CC2ICVSZR_ICVSZ_MASK)
/*! @} */
/* The count of CAAM_CC2ICVSZR */
#define CAAM_CC2ICVSZR_COUNT (1U)
/*! @name CC2CTXR - CCB 0 Class 2 Context Register Word 0..CCB 0 Class 2 Context Register Word 17 */
/*! @{ */
#define CAAM_CC2CTXR_C2CTXR_MASK (0xFFFFFFFFU)
#define CAAM_CC2CTXR_C2CTXR_SHIFT (0U)
#define CAAM_CC2CTXR_C2CTXR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2CTXR_C2CTXR_SHIFT)) & CAAM_CC2CTXR_C2CTXR_MASK)
/*! @} */
/* The count of CAAM_CC2CTXR */
#define CAAM_CC2CTXR_COUNT (1U)
/* The count of CAAM_CC2CTXR */
#define CAAM_CC2CTXR_COUNT2 (18U)
/*! @name CC2KEYR - CCB 0 Class 2 Key Register Word 0..CCB 0 Class 2 Key Register Word 31 */
/*! @{ */
#define CAAM_CC2KEYR_C2KEY_MASK (0xFFFFFFFFU)
#define CAAM_CC2KEYR_C2KEY_SHIFT (0U)
#define CAAM_CC2KEYR_C2KEY(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CC2KEYR_C2KEY_SHIFT)) & CAAM_CC2KEYR_C2KEY_MASK)
/*! @} */
/* The count of CAAM_CC2KEYR */
#define CAAM_CC2KEYR_COUNT (1U)
/* The count of CAAM_CC2KEYR */
#define CAAM_CC2KEYR_COUNT2 (32U)
/*! @name CFIFOSTA - CCB 0 FIFO Status Register */
/*! @{ */
#define CAAM_CFIFOSTA_DECOOQHEAD_MASK (0xFFU)
#define CAAM_CFIFOSTA_DECOOQHEAD_SHIFT (0U)
#define CAAM_CFIFOSTA_DECOOQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DECOOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DECOOQHEAD_MASK)
#define CAAM_CFIFOSTA_DMAOQHEAD_MASK (0xFF00U)
#define CAAM_CFIFOSTA_DMAOQHEAD_SHIFT (8U)
#define CAAM_CFIFOSTA_DMAOQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_DMAOQHEAD_SHIFT)) & CAAM_CFIFOSTA_DMAOQHEAD_MASK)
#define CAAM_CFIFOSTA_C2IQHEAD_MASK (0xFF0000U)
#define CAAM_CFIFOSTA_C2IQHEAD_SHIFT (16U)
#define CAAM_CFIFOSTA_C2IQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C2IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C2IQHEAD_MASK)
#define CAAM_CFIFOSTA_C1IQHEAD_MASK (0xFF000000U)
#define CAAM_CFIFOSTA_C1IQHEAD_SHIFT (24U)
#define CAAM_CFIFOSTA_C1IQHEAD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CFIFOSTA_C1IQHEAD_SHIFT)) & CAAM_CFIFOSTA_C1IQHEAD_MASK)
/*! @} */
/* The count of CAAM_CFIFOSTA */
#define CAAM_CFIFOSTA_COUNT (1U)
/*! @name CNFIFO - CCB 0 iNformation FIFO When STYPE != 10b */
/*! @{ */
#define CAAM_CNFIFO_DL_MASK (0xFFFU)
#define CAAM_CNFIFO_DL_SHIFT (0U)
#define CAAM_CNFIFO_DL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DL_SHIFT)) & CAAM_CNFIFO_DL_MASK)
#define CAAM_CNFIFO_AST_MASK (0x4000U)
#define CAAM_CNFIFO_AST_SHIFT (14U)
#define CAAM_CNFIFO_AST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_AST_SHIFT)) & CAAM_CNFIFO_AST_MASK)
#define CAAM_CNFIFO_OC_MASK (0x8000U)
#define CAAM_CNFIFO_OC_SHIFT (15U)
/*! OC
* 0b0..Allow the final word to be popped from the Output Data FIFO.
* 0b1..Don't pop the final word from the Output Data FIFO.
*/
#define CAAM_CNFIFO_OC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_OC_SHIFT)) & CAAM_CNFIFO_OC_MASK)
#define CAAM_CNFIFO_PTYPE_MASK (0x70000U)
#define CAAM_CNFIFO_PTYPE_SHIFT (16U)
#define CAAM_CNFIFO_PTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_PTYPE_SHIFT)) & CAAM_CNFIFO_PTYPE_MASK)
#define CAAM_CNFIFO_BND_MASK (0x80000U)
#define CAAM_CNFIFO_BND_SHIFT (19U)
/*! BND
* 0b0..Don't pad.
* 0b1..Pad to the next 16-byte boundary.
*/
#define CAAM_CNFIFO_BND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_BND_SHIFT)) & CAAM_CNFIFO_BND_MASK)
#define CAAM_CNFIFO_DTYPE_MASK (0xF00000U)
#define CAAM_CNFIFO_DTYPE_SHIFT (20U)
#define CAAM_CNFIFO_DTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DTYPE_SHIFT)) & CAAM_CNFIFO_DTYPE_MASK)
#define CAAM_CNFIFO_STYPE_MASK (0x3000000U)
#define CAAM_CNFIFO_STYPE_SHIFT (24U)
#define CAAM_CNFIFO_STYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_STYPE_SHIFT)) & CAAM_CNFIFO_STYPE_MASK)
#define CAAM_CNFIFO_FC1_MASK (0x4000000U)
#define CAAM_CNFIFO_FC1_SHIFT (26U)
/*! FC1
* 0b0..Don't flush Class 1 data.
* 0b1..Flush Class 1 data.
*/
#define CAAM_CNFIFO_FC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC1_SHIFT)) & CAAM_CNFIFO_FC1_MASK)
#define CAAM_CNFIFO_FC2_MASK (0x8000000U)
#define CAAM_CNFIFO_FC2_SHIFT (27U)
/*! FC2
* 0b0..Don't flush Class 2 data.
* 0b1..Flush Class 2 data.
*/
#define CAAM_CNFIFO_FC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_FC2_SHIFT)) & CAAM_CNFIFO_FC2_MASK)
#define CAAM_CNFIFO_LC1_MASK (0x10000000U)
#define CAAM_CNFIFO_LC1_SHIFT (28U)
/*! LC1
* 0b0..This is not the last Class 1 data.
* 0b1..This is the last Class 1 data.
*/
#define CAAM_CNFIFO_LC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC1_SHIFT)) & CAAM_CNFIFO_LC1_MASK)
#define CAAM_CNFIFO_LC2_MASK (0x20000000U)
#define CAAM_CNFIFO_LC2_SHIFT (29U)
/*! LC2
* 0b0..This is not the last Class 2 data.
* 0b1..This is the last Class 2 data.
*/
#define CAAM_CNFIFO_LC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_LC2_SHIFT)) & CAAM_CNFIFO_LC2_MASK)
#define CAAM_CNFIFO_DEST_MASK (0xC0000000U)
#define CAAM_CNFIFO_DEST_SHIFT (30U)
/*! DEST
* 0b00..DECO Alignment Block. If DTYPE == Eh, data sent to the DECO Alignment Block is dropped. This is used to
* skip over input data. An error is generated if a DTYPE other than Eh (drop) or Fh (message) is used with
* the DECO Alignment Block destination.
* 0b01..Class 1.
* 0b10..Class 2.
* 0b11..Both Class 1 and Class 2.
*/
#define CAAM_CNFIFO_DEST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_DEST_SHIFT)) & CAAM_CNFIFO_DEST_MASK)
/*! @} */
/* The count of CAAM_CNFIFO */
#define CAAM_CNFIFO_COUNT (1U)
/*! @name CNFIFO_2 - CCB 0 iNformation FIFO When STYPE == 10b */
/*! @{ */
#define CAAM_CNFIFO_2_PL_MASK (0x7FU)
#define CAAM_CNFIFO_2_PL_SHIFT (0U)
#define CAAM_CNFIFO_2_PL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PL_SHIFT)) & CAAM_CNFIFO_2_PL_MASK)
#define CAAM_CNFIFO_2_PS_MASK (0x400U)
#define CAAM_CNFIFO_2_PS_SHIFT (10U)
/*! PS
* 0b0..C2 CHA snoops pad data from padding block.
* 0b1..C2 CHA snoops pad data from OFIFO.
*/
#define CAAM_CNFIFO_2_PS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PS_SHIFT)) & CAAM_CNFIFO_2_PS_MASK)
#define CAAM_CNFIFO_2_BM_MASK (0x800U)
#define CAAM_CNFIFO_2_BM_SHIFT (11U)
/*! BM
* 0b0..When padding, pad to power-of-2 boundary.
* 0b1..When padding, pad to power-of-2 boundary minus 1 byte.
*/
#define CAAM_CNFIFO_2_BM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BM_SHIFT)) & CAAM_CNFIFO_2_BM_MASK)
#define CAAM_CNFIFO_2_PR_MASK (0x8000U)
#define CAAM_CNFIFO_2_PR_SHIFT (15U)
/*! PR
* 0b0..No prediction resistance.
* 0b1..Prediction resistance.
*/
#define CAAM_CNFIFO_2_PR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PR_SHIFT)) & CAAM_CNFIFO_2_PR_MASK)
#define CAAM_CNFIFO_2_PTYPE_MASK (0x70000U)
#define CAAM_CNFIFO_2_PTYPE_SHIFT (16U)
/*! PTYPE
* 0b000..All Zero.
* 0b001..Random with nonzero bytes.
* 0b010..Incremented (starting with 01h), followed by a byte containing the value N-1, i.e., if N==1, a single byte is output with value 0h.
* 0b011..Random.
* 0b100..All Zero with last byte containing the number of 0 bytes, i.e., if N==1, a single byte is output with value 0h.
* 0b101..Random with nonzero bytes with last byte 0.
* 0b110..N bytes of padding all containing the value N-1.
* 0b111..Random with nonzero bytes, with the last byte containing the value N-1.
*/
#define CAAM_CNFIFO_2_PTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_PTYPE_SHIFT)) & CAAM_CNFIFO_2_PTYPE_MASK)
#define CAAM_CNFIFO_2_BND_MASK (0x80000U)
#define CAAM_CNFIFO_2_BND_SHIFT (19U)
/*! BND
* 0b0..Don't add boundary padding.
* 0b1..Add boundary padding.
*/
#define CAAM_CNFIFO_2_BND(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_BND_SHIFT)) & CAAM_CNFIFO_2_BND_MASK)
#define CAAM_CNFIFO_2_DTYPE_MASK (0xF00000U)
#define CAAM_CNFIFO_2_DTYPE_SHIFT (20U)
#define CAAM_CNFIFO_2_DTYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DTYPE_SHIFT)) & CAAM_CNFIFO_2_DTYPE_MASK)
#define CAAM_CNFIFO_2_STYPE_MASK (0x3000000U)
#define CAAM_CNFIFO_2_STYPE_SHIFT (24U)
#define CAAM_CNFIFO_2_STYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_STYPE_SHIFT)) & CAAM_CNFIFO_2_STYPE_MASK)
#define CAAM_CNFIFO_2_FC1_MASK (0x4000000U)
#define CAAM_CNFIFO_2_FC1_SHIFT (26U)
/*! FC1
* 0b0..Don't flush the Class 1 data.
* 0b1..Flush the Class 1 data.
*/
#define CAAM_CNFIFO_2_FC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC1_SHIFT)) & CAAM_CNFIFO_2_FC1_MASK)
#define CAAM_CNFIFO_2_FC2_MASK (0x8000000U)
#define CAAM_CNFIFO_2_FC2_SHIFT (27U)
/*! FC2
* 0b0..Don't flush the Class 2 data.
* 0b1..Flush the Class 2 data.
*/
#define CAAM_CNFIFO_2_FC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_FC2_SHIFT)) & CAAM_CNFIFO_2_FC2_MASK)
#define CAAM_CNFIFO_2_LC1_MASK (0x10000000U)
#define CAAM_CNFIFO_2_LC1_SHIFT (28U)
/*! LC1
* 0b0..This is not the last Class 1 data.
* 0b1..This is the last Class 1 data.
*/
#define CAAM_CNFIFO_2_LC1(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC1_SHIFT)) & CAAM_CNFIFO_2_LC1_MASK)
#define CAAM_CNFIFO_2_LC2_MASK (0x20000000U)
#define CAAM_CNFIFO_2_LC2_SHIFT (29U)
/*! LC2
* 0b0..This is not the last Class 2 data.
* 0b1..This is the last Class 2 data.
*/
#define CAAM_CNFIFO_2_LC2(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_LC2_SHIFT)) & CAAM_CNFIFO_2_LC2_MASK)
#define CAAM_CNFIFO_2_DEST_MASK (0xC0000000U)
#define CAAM_CNFIFO_2_DEST_SHIFT (30U)
/*! DEST
* 0b00..DECO Alignment Block. If DTYPE is Eh, data sent to the DECO Alignment Block is dropped. This is used to
* skip over input data. An error is generated if a DTYPE other than Eh (drop) or Fh (message) is used with
* the DECO Alignment Block destination.
* 0b01..Class 1.
* 0b10..Class 2.
* 0b11..Both Class 1 and Class 2.
*/
#define CAAM_CNFIFO_2_DEST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CNFIFO_2_DEST_SHIFT)) & CAAM_CNFIFO_2_DEST_MASK)
/*! @} */
/* The count of CAAM_CNFIFO_2 */
#define CAAM_CNFIFO_2_COUNT (1U)
/*! @name CIFIFO - CCB 0 Input Data FIFO */
/*! @{ */
#define CAAM_CIFIFO_IFIFO_MASK (0xFFFFFFFFU)
#define CAAM_CIFIFO_IFIFO_SHIFT (0U)
#define CAAM_CIFIFO_IFIFO(x) (((uint32_t)(((uint32_t)(x)) << CAAM_CIFIFO_IFIFO_SHIFT)) & CAAM_CIFIFO_IFIFO_MASK)
/*! @} */
/* The count of CAAM_CIFIFO */
#define CAAM_CIFIFO_COUNT (1U)
/*! @name COFIFO - CCB 0 Output Data FIFO */
/*! @{ */
#define CAAM_COFIFO_OFIFO_MASK (0xFFFFFFFFFFFFFFFFU)
#define CAAM_COFIFO_OFIFO_SHIFT (0U)
#define CAAM_COFIFO_OFIFO(x) (((uint64_t)(((uint64_t)(x)) << CAAM_COFIFO_OFIFO_SHIFT)) & CAAM_COFIFO_OFIFO_MASK)
/*! @} */
/* The count of CAAM_COFIFO */
#define CAAM_COFIFO_COUNT (1U)
/*! @name DJQCR_MS - DECO0 Job Queue Control Register, most-significant half */
/*! @{ */
#define CAAM_DJQCR_MS_ID_MASK (0x7U)
#define CAAM_DJQCR_MS_ID_SHIFT (0U)
#define CAAM_DJQCR_MS_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ID_SHIFT)) & CAAM_DJQCR_MS_ID_MASK)
#define CAAM_DJQCR_MS_SRC_MASK (0x700U)
#define CAAM_DJQCR_MS_SRC_SHIFT (8U)
/*! SRC
* 0b000..Job Ring 0
* 0b001..Job Ring 1
* 0b010..Job Ring 2
* 0b011..Job Ring 3
* 0b100..RTIC
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define CAAM_DJQCR_MS_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SRC_SHIFT)) & CAAM_DJQCR_MS_SRC_MASK)
#define CAAM_DJQCR_MS_AMTD_MASK (0x8000U)
#define CAAM_DJQCR_MS_AMTD_SHIFT (15U)
/*! AMTD
* 0b0..The Allowed Make Trusted Descriptor bit was NOT set.
* 0b1..The Allowed Make Trusted Descriptor bit was set.
*/
#define CAAM_DJQCR_MS_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_AMTD_SHIFT)) & CAAM_DJQCR_MS_AMTD_MASK)
#define CAAM_DJQCR_MS_SOB_MASK (0x10000U)
#define CAAM_DJQCR_MS_SOB_SHIFT (16U)
/*! SOB
* 0b0..Shared Descriptor has NOT been loaded.
* 0b1..Shared Descriptor HAS been loaded.
*/
#define CAAM_DJQCR_MS_SOB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SOB_SHIFT)) & CAAM_DJQCR_MS_SOB_MASK)
#define CAAM_DJQCR_MS_DWS_MASK (0x80000U)
#define CAAM_DJQCR_MS_DWS_SHIFT (19U)
/*! DWS
* 0b0..Double Word Swap is NOT set.
* 0b1..Double Word Swap is set.
*/
#define CAAM_DJQCR_MS_DWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_DWS_SHIFT)) & CAAM_DJQCR_MS_DWS_MASK)
#define CAAM_DJQCR_MS_SHR_FROM_MASK (0x7000000U)
#define CAAM_DJQCR_MS_SHR_FROM_SHIFT (24U)
#define CAAM_DJQCR_MS_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SHR_FROM_SHIFT)) & CAAM_DJQCR_MS_SHR_FROM_MASK)
#define CAAM_DJQCR_MS_ILE_MASK (0x8000000U)
#define CAAM_DJQCR_MS_ILE_SHIFT (27U)
/*! ILE
* 0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
* 0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
*/
#define CAAM_DJQCR_MS_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_ILE_SHIFT)) & CAAM_DJQCR_MS_ILE_MASK)
#define CAAM_DJQCR_MS_FOUR_MASK (0x10000000U)
#define CAAM_DJQCR_MS_FOUR_SHIFT (28U)
/*! FOUR
* 0b0..DECO has not been given at least four words of the descriptor.
* 0b1..DECO has been given at least four words of the descriptor.
*/
#define CAAM_DJQCR_MS_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_FOUR_SHIFT)) & CAAM_DJQCR_MS_FOUR_MASK)
#define CAAM_DJQCR_MS_WHL_MASK (0x20000000U)
#define CAAM_DJQCR_MS_WHL_SHIFT (29U)
/*! WHL
* 0b0..DECO has not been given the whole descriptor.
* 0b1..DECO has been given the whole descriptor.
*/
#define CAAM_DJQCR_MS_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_WHL_SHIFT)) & CAAM_DJQCR_MS_WHL_MASK)
#define CAAM_DJQCR_MS_SING_MASK (0x40000000U)
#define CAAM_DJQCR_MS_SING_SHIFT (30U)
/*! SING
* 0b0..Do not tell DECO to execute the descriptor in single-step mode.
* 0b1..Tell DECO to execute the descriptor in single-step mode.
*/
#define CAAM_DJQCR_MS_SING(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_SING_SHIFT)) & CAAM_DJQCR_MS_SING_MASK)
#define CAAM_DJQCR_MS_STEP_MASK (0x80000000U)
#define CAAM_DJQCR_MS_STEP_SHIFT (31U)
/*! STEP
* 0b0..DECO has not been told to execute the next command in the descriptor.
* 0b1..DECO has been told to execute the next command in the descriptor.
*/
#define CAAM_DJQCR_MS_STEP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_MS_STEP_SHIFT)) & CAAM_DJQCR_MS_STEP_MASK)
/*! @} */
/* The count of CAAM_DJQCR_MS */
#define CAAM_DJQCR_MS_COUNT (1U)
/*! @name DJQCR_LS - DECO0 Job Queue Control Register, least-significant half */
/*! @{ */
#define CAAM_DJQCR_LS_CMD_MASK (0xFFFFFFFFU)
#define CAAM_DJQCR_LS_CMD_SHIFT (0U)
#define CAAM_DJQCR_LS_CMD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DJQCR_LS_CMD_SHIFT)) & CAAM_DJQCR_LS_CMD_MASK)
/*! @} */
/* The count of CAAM_DJQCR_LS */
#define CAAM_DJQCR_LS_COUNT (1U)
/*! @name DDAR - DECO0 Descriptor Address Register */
/*! @{ */
#define CAAM_DDAR_DPTR_MASK (0xFFFFFFFFFU)
#define CAAM_DDAR_DPTR_SHIFT (0U)
#define CAAM_DDAR_DPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DDAR_DPTR_SHIFT)) & CAAM_DDAR_DPTR_MASK)
/*! @} */
/* The count of CAAM_DDAR */
#define CAAM_DDAR_COUNT (1U)
/*! @name DOPSTA_MS - DECO0 Operation Status Register, most-significant half */
/*! @{ */
#define CAAM_DOPSTA_MS_STATUS_MASK (0xFFU)
#define CAAM_DOPSTA_MS_STATUS_SHIFT (0U)
#define CAAM_DOPSTA_MS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_SHIFT)) & CAAM_DOPSTA_MS_STATUS_MASK)
#define CAAM_DOPSTA_MS_COMMAND_INDEX_MASK (0x7F00U)
#define CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT (8U)
#define CAAM_DOPSTA_MS_COMMAND_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_COMMAND_INDEX_SHIFT)) & CAAM_DOPSTA_MS_COMMAND_INDEX_MASK)
#define CAAM_DOPSTA_MS_NLJ_MASK (0x8000000U)
#define CAAM_DOPSTA_MS_NLJ_SHIFT (27U)
/*! NLJ
* 0b0..The original job descriptor running in this DECO has not caused another job descriptor to be executed.
* 0b1..The original job descriptor running in this DECO has caused another job descriptor to be executed.
*/
#define CAAM_DOPSTA_MS_NLJ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_NLJ_SHIFT)) & CAAM_DOPSTA_MS_NLJ_MASK)
#define CAAM_DOPSTA_MS_STATUS_TYPE_MASK (0xF0000000U)
#define CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT (28U)
/*! STATUS_TYPE
* 0b0000..no error
* 0b0001..DMA error
* 0b0010..CCB error
* 0b0011..Jump Halt User Status
* 0b0100..DECO error
* 0b0101, 0b0110..Reserved
* 0b0111..Jump Halt Condition Code
*/
#define CAAM_DOPSTA_MS_STATUS_TYPE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_MS_STATUS_TYPE_SHIFT)) & CAAM_DOPSTA_MS_STATUS_TYPE_MASK)
/*! @} */
/* The count of CAAM_DOPSTA_MS */
#define CAAM_DOPSTA_MS_COUNT (1U)
/*! @name DOPSTA_LS - DECO0 Operation Status Register, least-significant half */
/*! @{ */
#define CAAM_DOPSTA_LS_OUT_CT_MASK (0xFFFFFFFFU)
#define CAAM_DOPSTA_LS_OUT_CT_SHIFT (0U)
#define CAAM_DOPSTA_LS_OUT_CT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DOPSTA_LS_OUT_CT_SHIFT)) & CAAM_DOPSTA_LS_OUT_CT_MASK)
/*! @} */
/* The count of CAAM_DOPSTA_LS */
#define CAAM_DOPSTA_LS_COUNT (1U)
/*! @name DPDIDSR - DECO0 Primary DID Status Register */
/*! @{ */
#define CAAM_DPDIDSR_PRIM_DID_MASK (0xFU)
#define CAAM_DPDIDSR_PRIM_DID_SHIFT (0U)
#define CAAM_DPDIDSR_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_DID_SHIFT)) & CAAM_DPDIDSR_PRIM_DID_MASK)
#define CAAM_DPDIDSR_PRIM_ICID_MASK (0x3FF80000U)
#define CAAM_DPDIDSR_PRIM_ICID_SHIFT (19U)
#define CAAM_DPDIDSR_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPDIDSR_PRIM_ICID_SHIFT)) & CAAM_DPDIDSR_PRIM_ICID_MASK)
/*! @} */
/* The count of CAAM_DPDIDSR */
#define CAAM_DPDIDSR_COUNT (1U)
/*! @name DODIDSR - DECO0 Output DID Status Register */
/*! @{ */
#define CAAM_DODIDSR_OUT_DID_MASK (0xFU)
#define CAAM_DODIDSR_OUT_DID_SHIFT (0U)
#define CAAM_DODIDSR_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_DID_SHIFT)) & CAAM_DODIDSR_OUT_DID_MASK)
#define CAAM_DODIDSR_OUT_ICID_MASK (0x3FF80000U)
#define CAAM_DODIDSR_OUT_ICID_SHIFT (19U)
#define CAAM_DODIDSR_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DODIDSR_OUT_ICID_SHIFT)) & CAAM_DODIDSR_OUT_ICID_MASK)
/*! @} */
/* The count of CAAM_DODIDSR */
#define CAAM_DODIDSR_COUNT (1U)
/*! @name DMTH_MS - DECO0 Math Register 0_MS..DECO0 Math Register 3_MS */
/*! @{ */
#define CAAM_DMTH_MS_MATH_MS_MASK (0xFFFFFFFFU)
#define CAAM_DMTH_MS_MATH_MS_SHIFT (0U)
#define CAAM_DMTH_MS_MATH_MS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_MS_MATH_MS_SHIFT)) & CAAM_DMTH_MS_MATH_MS_MASK)
/*! @} */
/* The count of CAAM_DMTH_MS */
#define CAAM_DMTH_MS_COUNT (1U)
/* The count of CAAM_DMTH_MS */
#define CAAM_DMTH_MS_COUNT2 (4U)
/*! @name DMTH_LS - DECO0 Math Register 0_LS..DECO0 Math Register 3_LS */
/*! @{ */
#define CAAM_DMTH_LS_MATH_LS_MASK (0xFFFFFFFFU)
#define CAAM_DMTH_LS_MATH_LS_SHIFT (0U)
#define CAAM_DMTH_LS_MATH_LS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DMTH_LS_MATH_LS_SHIFT)) & CAAM_DMTH_LS_MATH_LS_MASK)
/*! @} */
/* The count of CAAM_DMTH_LS */
#define CAAM_DMTH_LS_COUNT (1U)
/* The count of CAAM_DMTH_LS */
#define CAAM_DMTH_LS_COUNT2 (4U)
/*! @name DGTR_0 - DECO0 Gather Table Register 0 Word 0 */
/*! @{ */
#define CAAM_DGTR_0_ADDRESS_POINTER_MASK (0xFU)
#define CAAM_DGTR_0_ADDRESS_POINTER_SHIFT (0U)
/*! ADDRESS_POINTER - most-significant bits of memory address pointed to by table entry
*/
#define CAAM_DGTR_0_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_0_ADDRESS_POINTER_MASK)
/*! @} */
/* The count of CAAM_DGTR_0 */
#define CAAM_DGTR_0_COUNT (1U)
/* The count of CAAM_DGTR_0 */
#define CAAM_DGTR_0_COUNT2 (1U)
/*! @name DGTR_1 - DECO0 Gather Table Register 0 Word 1 */
/*! @{ */
#define CAAM_DGTR_1_ADDRESS_POINTER_MASK (0xFFFFFFFFU)
#define CAAM_DGTR_1_ADDRESS_POINTER_SHIFT (0U)
#define CAAM_DGTR_1_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DGTR_1_ADDRESS_POINTER_MASK)
/*! @} */
/* The count of CAAM_DGTR_1 */
#define CAAM_DGTR_1_COUNT (1U)
/* The count of CAAM_DGTR_1 */
#define CAAM_DGTR_1_COUNT2 (1U)
/*! @name DGTR_2 - DECO0 Gather Table Register 0 Word 2 */
/*! @{ */
#define CAAM_DGTR_2_Length_MASK (0x3FFFFFFFU)
#define CAAM_DGTR_2_Length_SHIFT (0U)
#define CAAM_DGTR_2_Length(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_Length_SHIFT)) & CAAM_DGTR_2_Length_MASK)
#define CAAM_DGTR_2_F_MASK (0x40000000U)
#define CAAM_DGTR_2_F_SHIFT (30U)
/*! F
* 0b0..This is not the last entry of the SGT.
* 0b1..This is the last entry of the SGT.
*/
#define CAAM_DGTR_2_F(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_F_SHIFT)) & CAAM_DGTR_2_F_MASK)
#define CAAM_DGTR_2_E_MASK (0x80000000U)
#define CAAM_DGTR_2_E_SHIFT (31U)
/*! E
* 0b0..Address Pointer points to a memory buffer.
* 0b1..Address Pointer points to a Scatter/Gather Table Entry.
*/
#define CAAM_DGTR_2_E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_2_E_SHIFT)) & CAAM_DGTR_2_E_MASK)
/*! @} */
/* The count of CAAM_DGTR_2 */
#define CAAM_DGTR_2_COUNT (1U)
/* The count of CAAM_DGTR_2 */
#define CAAM_DGTR_2_COUNT2 (1U)
/*! @name DGTR_3 - DECO0 Gather Table Register 0 Word 3 */
/*! @{ */
#define CAAM_DGTR_3_Offset_MASK (0x1FFFU)
#define CAAM_DGTR_3_Offset_SHIFT (0U)
#define CAAM_DGTR_3_Offset(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DGTR_3_Offset_SHIFT)) & CAAM_DGTR_3_Offset_MASK)
/*! @} */
/* The count of CAAM_DGTR_3 */
#define CAAM_DGTR_3_COUNT (1U)
/* The count of CAAM_DGTR_3 */
#define CAAM_DGTR_3_COUNT2 (1U)
/*! @name DSTR_0 - DECO0 Scatter Table Register 0 Word 0 */
/*! @{ */
#define CAAM_DSTR_0_ADDRESS_POINTER_MASK (0xFU)
#define CAAM_DSTR_0_ADDRESS_POINTER_SHIFT (0U)
/*! ADDRESS_POINTER - most-significant bits of memory address pointed to by table entry
*/
#define CAAM_DSTR_0_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_0_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_0_ADDRESS_POINTER_MASK)
/*! @} */
/* The count of CAAM_DSTR_0 */
#define CAAM_DSTR_0_COUNT (1U)
/* The count of CAAM_DSTR_0 */
#define CAAM_DSTR_0_COUNT2 (1U)
/*! @name DSTR_1 - DECO0 Scatter Table Register 0 Word 1 */
/*! @{ */
#define CAAM_DSTR_1_ADDRESS_POINTER_MASK (0xFFFFFFFFU)
#define CAAM_DSTR_1_ADDRESS_POINTER_SHIFT (0U)
#define CAAM_DSTR_1_ADDRESS_POINTER(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_1_ADDRESS_POINTER_SHIFT)) & CAAM_DSTR_1_ADDRESS_POINTER_MASK)
/*! @} */
/* The count of CAAM_DSTR_1 */
#define CAAM_DSTR_1_COUNT (1U)
/* The count of CAAM_DSTR_1 */
#define CAAM_DSTR_1_COUNT2 (1U)
/*! @name DSTR_2 - DECO0 Scatter Table Register 0 Word 2 */
/*! @{ */
#define CAAM_DSTR_2_Length_MASK (0x3FFFFFFFU)
#define CAAM_DSTR_2_Length_SHIFT (0U)
#define CAAM_DSTR_2_Length(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_Length_SHIFT)) & CAAM_DSTR_2_Length_MASK)
#define CAAM_DSTR_2_F_MASK (0x40000000U)
#define CAAM_DSTR_2_F_SHIFT (30U)
/*! F
* 0b0..This is not the last entry of the SGT.
* 0b1..This is the last entry of the SGT.
*/
#define CAAM_DSTR_2_F(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_F_SHIFT)) & CAAM_DSTR_2_F_MASK)
#define CAAM_DSTR_2_E_MASK (0x80000000U)
#define CAAM_DSTR_2_E_SHIFT (31U)
/*! E
* 0b0..Address Pointer points to a memory buffer.
* 0b1..Address Pointer points to a Scatter/Gather Table Entry.
*/
#define CAAM_DSTR_2_E(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_2_E_SHIFT)) & CAAM_DSTR_2_E_MASK)
/*! @} */
/* The count of CAAM_DSTR_2 */
#define CAAM_DSTR_2_COUNT (1U)
/* The count of CAAM_DSTR_2 */
#define CAAM_DSTR_2_COUNT2 (1U)
/*! @name DSTR_3 - DECO0 Scatter Table Register 0 Word 3 */
/*! @{ */
#define CAAM_DSTR_3_Offset_MASK (0x1FFFU)
#define CAAM_DSTR_3_Offset_SHIFT (0U)
#define CAAM_DSTR_3_Offset(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DSTR_3_Offset_SHIFT)) & CAAM_DSTR_3_Offset_MASK)
/*! @} */
/* The count of CAAM_DSTR_3 */
#define CAAM_DSTR_3_COUNT (1U)
/* The count of CAAM_DSTR_3 */
#define CAAM_DSTR_3_COUNT2 (1U)
/*! @name DDESB - DECO0 Descriptor Buffer Word 0..DECO0 Descriptor Buffer Word 63 */
/*! @{ */
#define CAAM_DDESB_DESBW_MASK (0xFFFFFFFFU)
#define CAAM_DDESB_DESBW_SHIFT (0U)
#define CAAM_DDESB_DESBW(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDESB_DESBW_SHIFT)) & CAAM_DDESB_DESBW_MASK)
/*! @} */
/* The count of CAAM_DDESB */
#define CAAM_DDESB_COUNT (1U)
/* The count of CAAM_DDESB */
#define CAAM_DDESB_COUNT2 (64U)
/*! @name DDJR - DECO0 Debug Job Register */
/*! @{ */
#define CAAM_DDJR_ID_MASK (0x7U)
#define CAAM_DDJR_ID_SHIFT (0U)
#define CAAM_DDJR_ID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ID_SHIFT)) & CAAM_DDJR_ID_MASK)
#define CAAM_DDJR_SRC_MASK (0x700U)
#define CAAM_DDJR_SRC_SHIFT (8U)
/*! SRC
* 0b000..Job Ring 0
* 0b001..Job Ring 1
* 0b010..Job Ring 2
* 0b011..Job Ring 3
* 0b100..RTIC
* 0b101, 0b110, 0b111..Reserved
*/
#define CAAM_DDJR_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SRC_SHIFT)) & CAAM_DDJR_SRC_MASK)
#define CAAM_DDJR_JDDS_MASK (0x4000U)
#define CAAM_DDJR_JDDS_SHIFT (14U)
/*! JDDS
* 0b1..SEQ DID
* 0b0..Non-SEQ DID
*/
#define CAAM_DDJR_JDDS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_JDDS_SHIFT)) & CAAM_DDJR_JDDS_MASK)
#define CAAM_DDJR_AMTD_MASK (0x8000U)
#define CAAM_DDJR_AMTD_SHIFT (15U)
/*! AMTD
* 0b0..The Allowed Make Trusted Descriptor bit was NOT set.
* 0b1..The Allowed Make Trusted Descriptor bit was set.
*/
#define CAAM_DDJR_AMTD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_AMTD_SHIFT)) & CAAM_DDJR_AMTD_MASK)
#define CAAM_DDJR_GSD_MASK (0x10000U)
#define CAAM_DDJR_GSD_SHIFT (16U)
/*! GSD
* 0b0..Shared Descriptor was NOT obtained from another DECO.
* 0b1..Shared Descriptor was obtained from another DECO.
*/
#define CAAM_DDJR_GSD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_GSD_SHIFT)) & CAAM_DDJR_GSD_MASK)
#define CAAM_DDJR_DWS_MASK (0x80000U)
#define CAAM_DDJR_DWS_SHIFT (19U)
/*! DWS
* 0b0..Double Word Swap is NOT set.
* 0b1..Double Word Swap is set.
*/
#define CAAM_DDJR_DWS(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_DWS_SHIFT)) & CAAM_DDJR_DWS_MASK)
#define CAAM_DDJR_SHR_FROM_MASK (0x7000000U)
#define CAAM_DDJR_SHR_FROM_SHIFT (24U)
#define CAAM_DDJR_SHR_FROM(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SHR_FROM_SHIFT)) & CAAM_DDJR_SHR_FROM_MASK)
#define CAAM_DDJR_ILE_MASK (0x8000000U)
#define CAAM_DDJR_ILE_SHIFT (27U)
/*! ILE
* 0b0..No byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
* 0b1..Byte-swapping is performed for immediate data transferred to or from the Descriptor Buffer.
*/
#define CAAM_DDJR_ILE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_ILE_SHIFT)) & CAAM_DDJR_ILE_MASK)
#define CAAM_DDJR_FOUR_MASK (0x10000000U)
#define CAAM_DDJR_FOUR_SHIFT (28U)
/*! FOUR
* 0b0..DECO has not been given at least four words of the descriptor.
* 0b1..DECO has been given at least four words of the descriptor.
*/
#define CAAM_DDJR_FOUR(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_FOUR_SHIFT)) & CAAM_DDJR_FOUR_MASK)
#define CAAM_DDJR_WHL_MASK (0x20000000U)
#define CAAM_DDJR_WHL_SHIFT (29U)
/*! WHL
* 0b0..DECO has not been given the whole descriptor.
* 0b1..DECO has been given the whole descriptor.
*/
#define CAAM_DDJR_WHL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_WHL_SHIFT)) & CAAM_DDJR_WHL_MASK)
#define CAAM_DDJR_SING_MASK (0x40000000U)
#define CAAM_DDJR_SING_SHIFT (30U)
/*! SING
* 0b0..DECO has not been told to execute the descriptor in single-step mode.
* 0b1..DECO has been told to execute the descriptor in single-step mode.
*/
#define CAAM_DDJR_SING(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_SING_SHIFT)) & CAAM_DDJR_SING_MASK)
#define CAAM_DDJR_STEP_MASK (0x80000000U)
#define CAAM_DDJR_STEP_SHIFT (31U)
/*! STEP
* 0b0..DECO has not been told to execute the next command in the descriptor.
* 0b1..DECO has been told to execute the next command in the descriptor.
*/
#define CAAM_DDJR_STEP(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDJR_STEP_SHIFT)) & CAAM_DDJR_STEP_MASK)
/*! @} */
/* The count of CAAM_DDJR */
#define CAAM_DDJR_COUNT (1U)
/*! @name DDDR - DECO0 Debug DECO Register */
/*! @{ */
#define CAAM_DDDR_CT_MASK (0x1U)
#define CAAM_DDDR_CT_SHIFT (0U)
/*! CT
* 0b0..This DECO is NOTcurrently generating the signature of a Trusted Descriptor.
* 0b1..This DECO is currently generating the signature of a Trusted Descriptor.
*/
#define CAAM_DDDR_CT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CT_SHIFT)) & CAAM_DDDR_CT_MASK)
#define CAAM_DDDR_BRB_MASK (0x2U)
#define CAAM_DDDR_BRB_SHIFT (1U)
/*! BRB
* 0b0..The READ machine in the Burster is not busy.
* 0b1..The READ machine in the Burster is busy.
*/
#define CAAM_DDDR_BRB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BRB_SHIFT)) & CAAM_DDDR_BRB_MASK)
#define CAAM_DDDR_BWB_MASK (0x4U)
#define CAAM_DDDR_BWB_SHIFT (2U)
/*! BWB
* 0b0..The WRITE machine in the Burster is not busy.
* 0b1..The WRITE machine in the Burster is busy.
*/
#define CAAM_DDDR_BWB(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_BWB_SHIFT)) & CAAM_DDDR_BWB_MASK)
#define CAAM_DDDR_NC_MASK (0x8U)
#define CAAM_DDDR_NC_SHIFT (3U)
/*! NC
* 0b0..This DECO is currently executing a command.
* 0b1..This DECO is not currently executing a command.
*/
#define CAAM_DDDR_NC(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NC_SHIFT)) & CAAM_DDDR_NC_MASK)
#define CAAM_DDDR_CSA_MASK (0x10U)
#define CAAM_DDDR_CSA_SHIFT (4U)
#define CAAM_DDDR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CSA_SHIFT)) & CAAM_DDDR_CSA_MASK)
#define CAAM_DDDR_CMD_STAGE_MASK (0xE0U)
#define CAAM_DDDR_CMD_STAGE_SHIFT (5U)
#define CAAM_DDDR_CMD_STAGE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_STAGE_SHIFT)) & CAAM_DDDR_CMD_STAGE_MASK)
#define CAAM_DDDR_CMD_INDEX_MASK (0x3F00U)
#define CAAM_DDDR_CMD_INDEX_SHIFT (8U)
#define CAAM_DDDR_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_CMD_INDEX_SHIFT)) & CAAM_DDDR_CMD_INDEX_MASK)
#define CAAM_DDDR_NLJ_MASK (0x4000U)
#define CAAM_DDDR_NLJ_SHIFT (14U)
/*! NLJ
* 0b0..The original job descriptor running in this DECO has not caused another job descriptor to be executed.
* 0b1..The original job descriptor running in this DECO has caused another job descriptor to be executed.
*/
#define CAAM_DDDR_NLJ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NLJ_SHIFT)) & CAAM_DDDR_NLJ_MASK)
#define CAAM_DDDR_PTCL_RUN_MASK (0x8000U)
#define CAAM_DDDR_PTCL_RUN_SHIFT (15U)
/*! PTCL_RUN
* 0b0..No protocol is running in this DECO.
* 0b1..A protocol is running in this DECO.
*/
#define CAAM_DDDR_PTCL_RUN(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PTCL_RUN_SHIFT)) & CAAM_DDDR_PTCL_RUN_MASK)
#define CAAM_DDDR_PDB_STALL_MASK (0x30000U)
#define CAAM_DDDR_PDB_STALL_SHIFT (16U)
#define CAAM_DDDR_PDB_STALL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_STALL_SHIFT)) & CAAM_DDDR_PDB_STALL_MASK)
#define CAAM_DDDR_PDB_WB_ST_MASK (0xC0000U)
#define CAAM_DDDR_PDB_WB_ST_SHIFT (18U)
#define CAAM_DDDR_PDB_WB_ST(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_PDB_WB_ST_SHIFT)) & CAAM_DDDR_PDB_WB_ST_MASK)
#define CAAM_DDDR_DECO_STATE_MASK (0xF00000U)
#define CAAM_DDDR_DECO_STATE_SHIFT (20U)
#define CAAM_DDDR_DECO_STATE(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_DECO_STATE_SHIFT)) & CAAM_DDDR_DECO_STATE_MASK)
#define CAAM_DDDR_NSEQLSEL_MASK (0x3000000U)
#define CAAM_DDDR_NSEQLSEL_SHIFT (24U)
/*! NSEQLSEL
* 0b01..SEQ DID
* 0b10..Non-SEQ DID
* 0b11..Trusted DID
*/
#define CAAM_DDDR_NSEQLSEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_NSEQLSEL_SHIFT)) & CAAM_DDDR_NSEQLSEL_MASK)
#define CAAM_DDDR_SEQLSEL_MASK (0xC000000U)
#define CAAM_DDDR_SEQLSEL_SHIFT (26U)
/*! SEQLSEL
* 0b01..SEQ DID
* 0b10..Non-SEQ DID
* 0b11..Trusted DID
*/
#define CAAM_DDDR_SEQLSEL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SEQLSEL_SHIFT)) & CAAM_DDDR_SEQLSEL_MASK)
#define CAAM_DDDR_TRCT_MASK (0x30000000U)
#define CAAM_DDDR_TRCT_SHIFT (28U)
#define CAAM_DDDR_TRCT(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_TRCT_SHIFT)) & CAAM_DDDR_TRCT_MASK)
#define CAAM_DDDR_SD_MASK (0x40000000U)
#define CAAM_DDDR_SD_SHIFT (30U)
/*! SD
* 0b0..This DECO has not received a shared descriptor from another DECO.
* 0b1..This DECO has received a shared descriptor from another DECO.
*/
#define CAAM_DDDR_SD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_SD_SHIFT)) & CAAM_DDDR_SD_MASK)
#define CAAM_DDDR_VALID_MASK (0x80000000U)
#define CAAM_DDDR_VALID_SHIFT (31U)
/*! VALID
* 0b0..No descriptor is currently running in this DECO.
* 0b1..There is currently a descriptor running in this DECO.
*/
#define CAAM_DDDR_VALID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_VALID_SHIFT)) & CAAM_DDDR_VALID_MASK)
/*! @} */
/* The count of CAAM_DDDR */
#define CAAM_DDDR_COUNT (1U)
/*! @name DDJP - DECO0 Debug Job Pointer */
/*! @{ */
#define CAAM_DDJP_JDPTR_MASK (0xFFFFFFFFFU)
#define CAAM_DDJP_JDPTR_SHIFT (0U)
#define CAAM_DDJP_JDPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DDJP_JDPTR_SHIFT)) & CAAM_DDJP_JDPTR_MASK)
/*! @} */
/* The count of CAAM_DDJP */
#define CAAM_DDJP_COUNT (1U)
/*! @name DSDP - DECO0 Debug Shared Pointer */
/*! @{ */
#define CAAM_DSDP_SDPTR_MASK (0xFFFFFFFFFU)
#define CAAM_DSDP_SDPTR_SHIFT (0U)
#define CAAM_DSDP_SDPTR(x) (((uint64_t)(((uint64_t)(x)) << CAAM_DSDP_SDPTR_SHIFT)) & CAAM_DSDP_SDPTR_MASK)
/*! @} */
/* The count of CAAM_DSDP */
#define CAAM_DSDP_COUNT (1U)
/*! @name DDDR_MS - DECO0 Debug DID, most-significant half */
/*! @{ */
#define CAAM_DDDR_MS_PRIM_DID_MASK (0xFU)
#define CAAM_DDDR_MS_PRIM_DID_SHIFT (0U)
#define CAAM_DDDR_MS_PRIM_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_DID_SHIFT)) & CAAM_DDDR_MS_PRIM_DID_MASK)
#define CAAM_DDDR_MS_PRIM_TZ_MASK (0x10U)
#define CAAM_DDDR_MS_PRIM_TZ_SHIFT (4U)
/*! PRIM_TZ
* 0b0..TrustZone NonSecureWorld
* 0b1..TrustZone SecureWorld
*/
#define CAAM_DDDR_MS_PRIM_TZ(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_TZ_SHIFT)) & CAAM_DDDR_MS_PRIM_TZ_MASK)
#define CAAM_DDDR_MS_PRIM_ICID_MASK (0xFFE0U)
#define CAAM_DDDR_MS_PRIM_ICID_SHIFT (5U)
#define CAAM_DDDR_MS_PRIM_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_PRIM_ICID_SHIFT)) & CAAM_DDDR_MS_PRIM_ICID_MASK)
#define CAAM_DDDR_MS_OUT_DID_MASK (0xF0000U)
#define CAAM_DDDR_MS_OUT_DID_SHIFT (16U)
#define CAAM_DDDR_MS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_DID_SHIFT)) & CAAM_DDDR_MS_OUT_DID_MASK)
#define CAAM_DDDR_MS_OUT_ICID_MASK (0xFFE00000U)
#define CAAM_DDDR_MS_OUT_ICID_SHIFT (21U)
#define CAAM_DDDR_MS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_MS_OUT_ICID_SHIFT)) & CAAM_DDDR_MS_OUT_ICID_MASK)
/*! @} */
/* The count of CAAM_DDDR_MS */
#define CAAM_DDDR_MS_COUNT (1U)
/*! @name DDDR_LS - DECO0 Debug DID, least-significant half */
/*! @{ */
#define CAAM_DDDR_LS_OUT_DID_MASK (0xFU)
#define CAAM_DDDR_LS_OUT_DID_SHIFT (0U)
#define CAAM_DDDR_LS_OUT_DID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_DID_SHIFT)) & CAAM_DDDR_LS_OUT_DID_MASK)
#define CAAM_DDDR_LS_OUT_ICID_MASK (0x3FF80000U)
#define CAAM_DDDR_LS_OUT_ICID_SHIFT (19U)
#define CAAM_DDDR_LS_OUT_ICID(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DDDR_LS_OUT_ICID_SHIFT)) & CAAM_DDDR_LS_OUT_ICID_MASK)
/*! @} */
/* The count of CAAM_DDDR_LS */
#define CAAM_DDDR_LS_COUNT (1U)
/*! @name SOL - Sequence Output Length Register */
/*! @{ */
#define CAAM_SOL_SOL_MASK (0xFFFFFFFFU)
#define CAAM_SOL_SOL_SHIFT (0U)
#define CAAM_SOL_SOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SOL_SOL_SHIFT)) & CAAM_SOL_SOL_MASK)
/*! @} */
/* The count of CAAM_SOL */
#define CAAM_SOL_COUNT (1U)
/*! @name VSOL - Variable Sequence Output Length Register */
/*! @{ */
#define CAAM_VSOL_VSOL_MASK (0xFFFFFFFFU)
#define CAAM_VSOL_VSOL_SHIFT (0U)
#define CAAM_VSOL_VSOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_VSOL_VSOL_SHIFT)) & CAAM_VSOL_VSOL_MASK)
/*! @} */
/* The count of CAAM_VSOL */
#define CAAM_VSOL_COUNT (1U)
/*! @name SIL - Sequence Input Length Register */
/*! @{ */
#define CAAM_SIL_SIL_MASK (0xFFFFFFFFU)
#define CAAM_SIL_SIL_SHIFT (0U)
#define CAAM_SIL_SIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_SIL_SIL_SHIFT)) & CAAM_SIL_SIL_MASK)
/*! @} */
/* The count of CAAM_SIL */
#define CAAM_SIL_COUNT (1U)
/*! @name VSIL - Variable Sequence Input Length Register */
/*! @{ */
#define CAAM_VSIL_VSIL_MASK (0xFFFFFFFFU)
#define CAAM_VSIL_VSIL_SHIFT (0U)
#define CAAM_VSIL_VSIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_VSIL_VSIL_SHIFT)) & CAAM_VSIL_VSIL_MASK)
/*! @} */
/* The count of CAAM_VSIL */
#define CAAM_VSIL_COUNT (1U)
/*! @name DPOVRD - Protocol Override Register */
/*! @{ */
#define CAAM_DPOVRD_DPOVRD_MASK (0xFFFFFFFFU)
#define CAAM_DPOVRD_DPOVRD_SHIFT (0U)
#define CAAM_DPOVRD_DPOVRD(x) (((uint32_t)(((uint32_t)(x)) << CAAM_DPOVRD_DPOVRD_SHIFT)) & CAAM_DPOVRD_DPOVRD_MASK)
/*! @} */
/* The count of CAAM_DPOVRD */
#define CAAM_DPOVRD_COUNT (1U)
/*! @name UVSOL - Variable Sequence Output Length Register; Upper 32 bits */
/*! @{ */
#define CAAM_UVSOL_UVSOL_MASK (0xFFFFFFFFU)
#define CAAM_UVSOL_UVSOL_SHIFT (0U)
#define CAAM_UVSOL_UVSOL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_UVSOL_UVSOL_SHIFT)) & CAAM_UVSOL_UVSOL_MASK)
/*! @} */
/* The count of CAAM_UVSOL */
#define CAAM_UVSOL_COUNT (1U)
/*! @name UVSIL - Variable Sequence Input Length Register; Upper 32 bits */
/*! @{ */
#define CAAM_UVSIL_UVSIL_MASK (0xFFFFFFFFU)
#define CAAM_UVSIL_UVSIL_SHIFT (0U)
#define CAAM_UVSIL_UVSIL(x) (((uint32_t)(((uint32_t)(x)) << CAAM_UVSIL_UVSIL_SHIFT)) & CAAM_UVSIL_UVSIL_MASK)
/*! @} */
/* The count of CAAM_UVSIL */
#define CAAM_UVSIL_COUNT (1U)
/*!
* @}
*/ /* end of group CAAM_Register_Masks */
/* CAAM - Peripheral instance base addresses */
/** Peripheral CAAM base address */
#define CAAM_BASE (0x40440000u)
/** Peripheral CAAM base pointer */
#define CAAM ((CAAM_Type *)CAAM_BASE)
/** Array initializer of CAAM peripheral base addresses */
#define CAAM_BASE_ADDRS { CAAM_BASE }
/** Array initializer of CAAM peripheral base pointers */
#define CAAM_BASE_PTRS { CAAM }
/*!
* @}
*/ /* end of group CAAM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAN Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
* @{
*/
/** CAN - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Configuration register, offset: 0x0 */
__IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
__IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask register, offset: 0x10 */
__IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
__IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
__IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
__IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
__IO uint32_t IMASK2; /**< Interrupt Masks 2 register, offset: 0x24 */
__IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
__IO uint32_t IFLAG2; /**< Interrupt Flags 2 register, offset: 0x2C */
__IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
__IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
__I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
uint8_t RESERVED_1[8];
__I uint32_t CRCR; /**< CRC register, offset: 0x44 */
__IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
__I uint32_t RXFIR; /**< Rx FIFO Information register, offset: 0x4C */
__IO uint32_t CBT; /**< CAN Bit Timing register, offset: 0x50 */
uint8_t RESERVED_2[44];
union { /* offset: 0x80 */
struct { /* offset: 0x80, array step: 0x10 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
__IO uint32_t WORD[2]; /**< Message Buffer 0 WORD_8B Register..Message Buffer 63 WORD_8B Register, array offset: 0x88, array step: index*0x10, index2*0x4 */
} MB_8B[64];
struct { /* offset: 0x80 */
struct { /* offset: 0x80, array step: 0x18 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x80, array step: 0x18 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x84, array step: 0x18 */
__IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x88, array step: index*0x18, index2*0x4 */
} MB_16B_L[21];
uint8_t RESERVED_0[8];
struct { /* offset: 0x280, array step: 0x18 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 20 CS Register, array offset: 0x280, array step: 0x18 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 20 ID Register, array offset: 0x284, array step: 0x18 */
__IO uint32_t WORD[4]; /**< Message Buffer 0 WORD_16B Register..Message Buffer 20 WORD_16B Register, array offset: 0x288, array step: index*0x18, index2*0x4 */
} MB_16B_H[21];
} MB_16B;
struct { /* offset: 0x80 */
struct { /* offset: 0x80, array step: 0x28 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x80, array step: 0x28 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x84, array step: 0x28 */
__IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x88, array step: index*0x28, index2*0x4 */
} MB_32B_L[12];
uint8_t RESERVED_0[32];
struct { /* offset: 0x280, array step: 0x28 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 11 CS Register, array offset: 0x280, array step: 0x28 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 11 ID Register, array offset: 0x284, array step: 0x28 */
__IO uint32_t WORD[8]; /**< Message Buffer 0 WORD_32B Register..Message Buffer 11 WORD_32B Register, array offset: 0x288, array step: index*0x28, index2*0x4 */
} MB_32B_H[12];
} MB_32B;
struct { /* offset: 0x80 */
struct { /* offset: 0x80, array step: 0x48 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x80, array step: 0x48 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x84, array step: 0x48 */
__IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x88, array step: index*0x48, index2*0x4 */
} MB_64B_L[7];
uint8_t RESERVED_0[8];
struct { /* offset: 0x280, array step: 0x48 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 6 CS Register, array offset: 0x280, array step: 0x48 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 6 ID Register, array offset: 0x284, array step: 0x48 */
__IO uint32_t WORD[16]; /**< Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register, array offset: 0x288, array step: index*0x48, index2*0x4 */
} MB_64B_H[7];
} MB_64B;
struct { /* offset: 0x80, array step: 0x10 */
__IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 63 CS Register, array offset: 0x80, array step: 0x10 */
__IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 63 ID Register, array offset: 0x84, array step: 0x10 */
__IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register, array offset: 0x88, array step: 0x10 */
__IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register, array offset: 0x8C, array step: 0x10 */
} MB[64];
};
uint8_t RESERVED_3[1024];
__IO uint32_t RXIMR[64]; /**< Rx Individual Mask registers, array offset: 0x880, array step: 0x4 */
uint8_t RESERVED_4[352];
__IO uint32_t MECR; /**< Memory Error Control register, offset: 0xAE0 */
__IO uint32_t ERRIAR; /**< Error Injection Address register, offset: 0xAE4 */
__IO uint32_t ERRIDPR; /**< Error Injection Data Pattern register, offset: 0xAE8 */
__IO uint32_t ERRIPPR; /**< Error Injection Parity Pattern register, offset: 0xAEC */
__I uint32_t RERRAR; /**< Error Report Address register, offset: 0xAF0 */
__I uint32_t RERRDR; /**< Error Report Data register, offset: 0xAF4 */
__I uint32_t RERRSYNR; /**< Error Report Syndrome register, offset: 0xAF8 */
__IO uint32_t ERRSR; /**< Error Status register, offset: 0xAFC */
uint8_t RESERVED_5[256];
__IO uint32_t FDCTRL; /**< CAN FD Control register, offset: 0xC00 */
__IO uint32_t FDCBT; /**< CAN FD Bit Timing register, offset: 0xC04 */
__I uint32_t FDCRC; /**< CAN FD CRC register, offset: 0xC08 */
} CAN_Type;
/* ----------------------------------------------------------------------------
-- CAN Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_Register_Masks CAN Register Masks
* @{
*/
/*! @name MCR - Module Configuration register */
/*! @{ */
#define CAN_MCR_MAXMB_MASK (0x7FU)
#define CAN_MCR_MAXMB_SHIFT (0U)
/*! MAXMB - Number Of The Last Message Buffer
*/
#define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
#define CAN_MCR_IDAM_MASK (0x300U)
#define CAN_MCR_IDAM_SHIFT (8U)
/*! IDAM - ID Acceptance Mode
* 0b00..Format A: One full ID (standard and extended) per ID filter table element.
* 0b01..Format B: Two full standard IDs or two partial 14-bit (standard and extended) IDs per ID filter table element.
* 0b10..Format C: Four partial 8-bit standard IDs per ID filter table element.
* 0b11..Format D: All frames rejected.
*/
#define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
#define CAN_MCR_FDEN_MASK (0x800U)
#define CAN_MCR_FDEN_SHIFT (11U)
/*! FDEN - CAN FD operation enable
* 0b1..CAN FD is enabled. FlexCAN is able to receive and transmit messages in both CAN FD and CAN 2.0 formats.
* 0b0..CAN FD is disabled. FlexCAN is able to receive and transmit messages in CAN 2.0 format.
*/
#define CAN_MCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FDEN_SHIFT)) & CAN_MCR_FDEN_MASK)
#define CAN_MCR_AEN_MASK (0x1000U)
#define CAN_MCR_AEN_SHIFT (12U)
/*! AEN - Abort Enable
* 0b0..Abort disabled.
* 0b1..Abort enabled.
*/
#define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
#define CAN_MCR_LPRIOEN_MASK (0x2000U)
#define CAN_MCR_LPRIOEN_SHIFT (13U)
/*! LPRIOEN - Local Priority Enable
* 0b0..Local Priority disabled.
* 0b1..Local Priority enabled.
*/
#define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
#define CAN_MCR_DMA_MASK (0x8000U)
#define CAN_MCR_DMA_SHIFT (15U)
/*! DMA - DMA Enable
* 0b0..DMA feature for RX FIFO disabled.
* 0b1..DMA feature for RX FIFO enabled.
*/
#define CAN_MCR_DMA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DMA_SHIFT)) & CAN_MCR_DMA_MASK)
#define CAN_MCR_IRMQ_MASK (0x10000U)
#define CAN_MCR_IRMQ_SHIFT (16U)
/*! IRMQ - Individual Rx Masking And Queue Enable
* 0b0..Individual Rx masking and queue feature are disabled. For backward compatibility with legacy
* applications, the reading of C/S word locks the MB even if it is EMPTY.
* 0b1..Individual Rx masking and queue feature are enabled.
*/
#define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
#define CAN_MCR_SRXDIS_MASK (0x20000U)
#define CAN_MCR_SRXDIS_SHIFT (17U)
/*! SRXDIS - Self Reception Disable
* 0b0..Self-reception enabled.
* 0b1..Self-reception disabled.
*/
#define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
#define CAN_MCR_DOZE_MASK (0x40000U)
#define CAN_MCR_DOZE_SHIFT (18U)
/*! DOZE - Doze Mode Enable
* 0b0..FlexCAN is not enabled to enter low-power mode when Doze mode is requested.
* 0b1..FlexCAN is enabled to enter low-power mode when Doze mode is requested.
*/
#define CAN_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_DOZE_SHIFT)) & CAN_MCR_DOZE_MASK)
#define CAN_MCR_WAKSRC_MASK (0x80000U)
#define CAN_MCR_WAKSRC_SHIFT (19U)
/*! WAKSRC - Wake Up Source
* 0b0..FlexCAN uses the unfiltered Rx input to detect recessive to dominant edges on the CAN bus.
* 0b1..FlexCAN uses the filtered Rx input to detect recessive to dominant edges on the CAN bus.
*/
#define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
#define CAN_MCR_LPMACK_MASK (0x100000U)
#define CAN_MCR_LPMACK_SHIFT (20U)
/*! LPMACK - Low-Power Mode Acknowledge
* 0b0..FlexCAN is not in a low-power mode.
* 0b1..FlexCAN is in a low-power mode.
*/
#define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
#define CAN_MCR_WRNEN_MASK (0x200000U)
#define CAN_MCR_WRNEN_SHIFT (21U)
/*! WRNEN - Warning Interrupt Enable
* 0b0..TWRNINT and RWRNINT bits are zero, independent of the values in the error counters.
* 0b1..TWRNINT and RWRNINT bits are set when the respective error counter transitions from less than 96 to greater than or equal to 96.
*/
#define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
#define CAN_MCR_SLFWAK_MASK (0x400000U)
#define CAN_MCR_SLFWAK_SHIFT (22U)
/*! SLFWAK - Self Wake Up
* 0b0..FlexCAN Self Wake Up feature is disabled.
* 0b1..FlexCAN Self Wake Up feature is enabled.
*/
#define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
#define CAN_MCR_SUPV_MASK (0x800000U)
#define CAN_MCR_SUPV_SHIFT (23U)
/*! SUPV - Supervisor Mode
* 0b0..FlexCAN is in User mode. Affected registers allow both Supervisor and Unrestricted accesses.
* 0b1..FlexCAN is in Supervisor mode. Affected registers allow only Supervisor access. Unrestricted access
* behaves as though the access was done to an unimplemented register location.
*/
#define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
#define CAN_MCR_FRZACK_MASK (0x1000000U)
#define CAN_MCR_FRZACK_SHIFT (24U)
/*! FRZACK - Freeze Mode Acknowledge
* 0b0..FlexCAN not in Freeze mode, prescaler running.
* 0b1..FlexCAN in Freeze mode, prescaler stopped.
*/
#define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
#define CAN_MCR_SOFTRST_MASK (0x2000000U)
#define CAN_MCR_SOFTRST_SHIFT (25U)
/*! SOFTRST - Soft Reset
* 0b0..No reset request.
* 0b1..Resets the registers affected by soft reset.
*/
#define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
#define CAN_MCR_WAKMSK_MASK (0x4000000U)
#define CAN_MCR_WAKMSK_SHIFT (26U)
/*! WAKMSK - Wake Up Interrupt Mask
* 0b0..Wake Up interrupt is disabled.
* 0b1..Wake Up interrupt is enabled.
*/
#define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
#define CAN_MCR_NOTRDY_MASK (0x8000000U)
#define CAN_MCR_NOTRDY_SHIFT (27U)
/*! NOTRDY - FlexCAN Not Ready
* 0b0..FlexCAN module is either in Normal mode, Listen-Only mode, or Loop-Back mode.
* 0b1..FlexCAN module is either in Disable mode, Doze mode, Stop mode, or Freeze mode.
*/
#define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
#define CAN_MCR_HALT_MASK (0x10000000U)
#define CAN_MCR_HALT_SHIFT (28U)
/*! HALT - Halt FlexCAN
* 0b0..No Freeze mode request.
* 0b1..Enters Freeze mode if the FRZ bit is asserted.
*/
#define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
#define CAN_MCR_RFEN_MASK (0x20000000U)
#define CAN_MCR_RFEN_SHIFT (29U)
/*! RFEN - Rx FIFO Enable
* 0b0..Rx FIFO not enabled.
* 0b1..Rx FIFO enabled.
*/
#define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
#define CAN_MCR_FRZ_MASK (0x40000000U)
#define CAN_MCR_FRZ_SHIFT (30U)
/*! FRZ - Freeze Enable
* 0b0..Not enabled to enter Freeze mode.
* 0b1..Enabled to enter Freeze mode.
*/
#define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
#define CAN_MCR_MDIS_MASK (0x80000000U)
#define CAN_MCR_MDIS_SHIFT (31U)
/*! MDIS - Module Disable
* 0b0..Enable the FlexCAN module.
* 0b1..Disable the FlexCAN module.
*/
#define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
/*! @} */
/*! @name CTRL1 - Control 1 register */
/*! @{ */
#define CAN_CTRL1_PROPSEG_MASK (0x7U)
#define CAN_CTRL1_PROPSEG_SHIFT (0U)
/*! PROPSEG - Propagation Segment
*/
#define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
#define CAN_CTRL1_LOM_MASK (0x8U)
#define CAN_CTRL1_LOM_SHIFT (3U)
/*! LOM - Listen-Only Mode
* 0b0..Listen-Only mode is deactivated.
* 0b1..FlexCAN module operates in Listen-Only mode.
*/
#define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
#define CAN_CTRL1_LBUF_MASK (0x10U)
#define CAN_CTRL1_LBUF_SHIFT (4U)
/*! LBUF - Lowest Buffer Transmitted First
* 0b0..Buffer with highest priority is transmitted first.
* 0b1..Lowest number buffer is transmitted first.
*/
#define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
#define CAN_CTRL1_TSYN_MASK (0x20U)
#define CAN_CTRL1_TSYN_SHIFT (5U)
/*! TSYN - Timer Sync
* 0b0..Timer sync feature disabled
* 0b1..Timer sync feature enabled
*/
#define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
#define CAN_CTRL1_BOFFREC_MASK (0x40U)
#define CAN_CTRL1_BOFFREC_SHIFT (6U)
/*! BOFFREC - Bus Off Recovery
* 0b0..Automatic recovering from Bus Off state enabled.
* 0b1..Automatic recovering from Bus Off state disabled.
*/
#define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
#define CAN_CTRL1_SMP_MASK (0x80U)
#define CAN_CTRL1_SMP_SHIFT (7U)
/*! SMP - CAN Bit Sampling
* 0b0..Just one sample is used to determine the bit value.
* 0b1..Three samples are used to determine the value of the received bit: the regular one (sample point) and two
* preceding samples; a majority rule is used.
*/
#define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
#define CAN_CTRL1_RWRNMSK_MASK (0x400U)
#define CAN_CTRL1_RWRNMSK_SHIFT (10U)
/*! RWRNMSK - Rx Warning Interrupt Mask
* 0b0..Rx Warning interrupt disabled.
* 0b1..Rx Warning interrupt enabled.
*/
#define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
#define CAN_CTRL1_TWRNMSK_MASK (0x800U)
#define CAN_CTRL1_TWRNMSK_SHIFT (11U)
/*! TWRNMSK - Tx Warning Interrupt Mask
* 0b0..Tx Warning interrupt disabled.
* 0b1..Tx Warning interrupt enabled.
*/
#define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
#define CAN_CTRL1_LPB_MASK (0x1000U)
#define CAN_CTRL1_LPB_SHIFT (12U)
/*! LPB - Loop Back Mode
* 0b0..Loop Back disabled.
* 0b1..Loop Back enabled.
*/
#define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
#define CAN_CTRL1_CLKSRC_MASK (0x2000U)
#define CAN_CTRL1_CLKSRC_SHIFT (13U)
/*! CLKSRC - CAN Engine Clock Source
* 0b0..The CAN engine clock source is the oscillator clock. Under this condition, the oscillator clock frequency must be lower than the bus clock.
* 0b1..The CAN engine clock source is the peripheral clock.
*/
#define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
#define CAN_CTRL1_ERRMSK_MASK (0x4000U)
#define CAN_CTRL1_ERRMSK_SHIFT (14U)
/*! ERRMSK - Error Interrupt Mask
* 0b0..Error interrupt disabled.
* 0b1..Error interrupt enabled.
*/
#define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
#define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
#define CAN_CTRL1_BOFFMSK_SHIFT (15U)
/*! BOFFMSK - Bus Off Interrupt Mask
* 0b0..Bus Off interrupt disabled.
* 0b1..Bus Off interrupt enabled.
*/
#define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
#define CAN_CTRL1_PSEG2_MASK (0x70000U)
#define CAN_CTRL1_PSEG2_SHIFT (16U)
/*! PSEG2 - Phase Segment 2
*/
#define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
#define CAN_CTRL1_PSEG1_MASK (0x380000U)
#define CAN_CTRL1_PSEG1_SHIFT (19U)
/*! PSEG1 - Phase Segment 1
*/
#define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
#define CAN_CTRL1_RJW_MASK (0xC00000U)
#define CAN_CTRL1_RJW_SHIFT (22U)
/*! RJW - Resync Jump Width
*/
#define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
#define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
#define CAN_CTRL1_PRESDIV_SHIFT (24U)
/*! PRESDIV - Prescaler Division Factor
*/
#define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
/*! @} */
/*! @name TIMER - Free Running Timer */
/*! @{ */
#define CAN_TIMER_TIMER_MASK (0xFFFFU)
#define CAN_TIMER_TIMER_SHIFT (0U)
/*! TIMER - Timer Value
*/
#define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
/*! @} */
/*! @name RXMGMASK - Rx Mailboxes Global Mask register */
/*! @{ */
#define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
#define CAN_RXMGMASK_MG_SHIFT (0U)
/*! MG - Rx Mailboxes Global Mask Bits
*/
#define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
/*! @} */
/*! @name RX14MASK - Rx 14 Mask register */
/*! @{ */
#define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
#define CAN_RX14MASK_RX14M_SHIFT (0U)
/*! RX14M - Rx Buffer 14 Mask Bits
*/
#define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
/*! @} */
/*! @name RX15MASK - Rx 15 Mask register */
/*! @{ */
#define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
#define CAN_RX15MASK_RX15M_SHIFT (0U)
/*! RX15M - Rx Buffer 15 Mask Bits
*/
#define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
/*! @} */
/*! @name ECR - Error Counter */
/*! @{ */
#define CAN_ECR_TXERRCNT_MASK (0xFFU)
#define CAN_ECR_TXERRCNT_SHIFT (0U)
/*! TXERRCNT - Transmit Error Counter
*/
#define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
#define CAN_ECR_RXERRCNT_MASK (0xFF00U)
#define CAN_ECR_RXERRCNT_SHIFT (8U)
/*! RXERRCNT - Receive Error Counter
*/
#define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
#define CAN_ECR_TXERRCNT_FAST_MASK (0xFF0000U)
#define CAN_ECR_TXERRCNT_FAST_SHIFT (16U)
/*! TXERRCNT_FAST - Transmit Error Counter for fast bits
*/
#define CAN_ECR_TXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_FAST_SHIFT)) & CAN_ECR_TXERRCNT_FAST_MASK)
#define CAN_ECR_RXERRCNT_FAST_MASK (0xFF000000U)
#define CAN_ECR_RXERRCNT_FAST_SHIFT (24U)
/*! RXERRCNT_FAST - Receive Error Counter for fast bits
*/
#define CAN_ECR_RXERRCNT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_FAST_SHIFT)) & CAN_ECR_RXERRCNT_FAST_MASK)
/*! @} */
/*! @name ESR1 - Error and Status 1 register */
/*! @{ */
#define CAN_ESR1_WAKINT_MASK (0x1U)
#define CAN_ESR1_WAKINT_SHIFT (0U)
/*! WAKINT - Wake-Up Interrupt
* 0b0..No such occurrence.
* 0b1..Indicates a recessive to dominant transition was received on the CAN bus.
*/
#define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
#define CAN_ESR1_ERRINT_MASK (0x2U)
#define CAN_ESR1_ERRINT_SHIFT (1U)
/*! ERRINT - Error Interrupt
* 0b0..No such occurrence.
* 0b1..Indicates setting of any error bit in the Error and Status register.
*/
#define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
#define CAN_ESR1_BOFFINT_MASK (0x4U)
#define CAN_ESR1_BOFFINT_SHIFT (2U)
/*! BOFFINT - Bus Off Interrupt
* 0b0..No such occurrence.
* 0b1..FlexCAN module entered Bus Off state.
*/
#define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
#define CAN_ESR1_RX_MASK (0x8U)
#define CAN_ESR1_RX_SHIFT (3U)
/*! RX - FlexCAN In Reception
* 0b0..FlexCAN is not receiving a message.
* 0b1..FlexCAN is receiving a message.
*/
#define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
#define CAN_ESR1_FLTCONF_MASK (0x30U)
#define CAN_ESR1_FLTCONF_SHIFT (4U)
/*! FLTCONF - Fault Confinement State
* 0b00..Error Active
* 0b01..Error Passive
* 0b1x..Bus Off
*/
#define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
#define CAN_ESR1_TX_MASK (0x40U)
#define CAN_ESR1_TX_SHIFT (6U)
/*! TX - FlexCAN In Transmission
* 0b0..FlexCAN is not transmitting a message.
* 0b1..FlexCAN is transmitting a message.
*/
#define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
#define CAN_ESR1_IDLE_MASK (0x80U)
#define CAN_ESR1_IDLE_SHIFT (7U)
/*! IDLE - IDLE
* 0b0..No such occurrence.
* 0b1..CAN bus is now IDLE.
*/
#define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
#define CAN_ESR1_RXWRN_MASK (0x100U)
#define CAN_ESR1_RXWRN_SHIFT (8U)
/*! RXWRN - Rx Error Warning
* 0b0..No such occurrence.
* 0b1..RXERRCNT is greater than or equal to 96.
*/
#define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
#define CAN_ESR1_TXWRN_MASK (0x200U)
#define CAN_ESR1_TXWRN_SHIFT (9U)
/*! TXWRN - TX Error Warning
* 0b0..No such occurrence.
* 0b1..TXERRCNT is greater than or equal to 96.
*/
#define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
#define CAN_ESR1_STFERR_MASK (0x400U)
#define CAN_ESR1_STFERR_SHIFT (10U)
/*! STFERR - Stuffing Error
* 0b0..No such occurrence.
* 0b1..A stuffing error occurred since last read of this register.
*/
#define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
#define CAN_ESR1_FRMERR_MASK (0x800U)
#define CAN_ESR1_FRMERR_SHIFT (11U)
/*! FRMERR - Form Error
* 0b0..No such occurrence.
* 0b1..A Form Error occurred since last read of this register.
*/
#define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
#define CAN_ESR1_CRCERR_MASK (0x1000U)
#define CAN_ESR1_CRCERR_SHIFT (12U)
/*! CRCERR - Cyclic Redundancy Check Error
* 0b0..No such occurrence.
* 0b1..A CRC error occurred since last read of this register.
*/
#define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
#define CAN_ESR1_ACKERR_MASK (0x2000U)
#define CAN_ESR1_ACKERR_SHIFT (13U)
/*! ACKERR - Acknowledge Error
* 0b0..No such occurrence.
* 0b1..An ACK error occurred since last read of this register.
*/
#define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
#define CAN_ESR1_BIT0ERR_MASK (0x4000U)
#define CAN_ESR1_BIT0ERR_SHIFT (14U)
/*! BIT0ERR - Bit0 Error
* 0b0..No such occurrence.
* 0b1..At least one bit sent as dominant is received as recessive.
*/
#define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
#define CAN_ESR1_BIT1ERR_MASK (0x8000U)
#define CAN_ESR1_BIT1ERR_SHIFT (15U)
/*! BIT1ERR - Bit1 Error
* 0b0..No such occurrence.
* 0b1..At least one bit sent as recessive is received as dominant.
*/
#define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
#define CAN_ESR1_RWRNINT_MASK (0x10000U)
#define CAN_ESR1_RWRNINT_SHIFT (16U)
/*! RWRNINT - Rx Warning Interrupt Flag
* 0b0..No such occurrence.
* 0b1..The Rx error counter transitioned from less than 96 to greater than or equal to 96.
*/
#define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
#define CAN_ESR1_TWRNINT_MASK (0x20000U)
#define CAN_ESR1_TWRNINT_SHIFT (17U)
/*! TWRNINT - Tx Warning Interrupt Flag
* 0b0..No such occurrence.
* 0b1..The Tx error counter transitioned from less than 96 to greater than or equal to 96.
*/
#define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
#define CAN_ESR1_SYNCH_MASK (0x40000U)
#define CAN_ESR1_SYNCH_SHIFT (18U)
/*! SYNCH - CAN Synchronization Status
* 0b0..FlexCAN is not synchronized to the CAN bus.
* 0b1..FlexCAN is synchronized to the CAN bus.
*/
#define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
#define CAN_ESR1_BOFFDONEINT_MASK (0x80000U)
#define CAN_ESR1_BOFFDONEINT_SHIFT (19U)
/*! BOFFDONEINT - Bus Off Done Interrupt
* 0b0..No such occurrence.
* 0b1..FlexCAN module has completed Bus Off process.
*/
#define CAN_ESR1_BOFFDONEINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFDONEINT_SHIFT)) & CAN_ESR1_BOFFDONEINT_MASK)
#define CAN_ESR1_ERRINT_FAST_MASK (0x100000U)
#define CAN_ESR1_ERRINT_FAST_SHIFT (20U)
/*! ERRINT_FAST - Error interrupt for errors detected in Data Phase of CAN FD frames with BRS bit set
* 0b0..No such occurrence.
* 0b1..Indicates setting of any error bit detected in the data phase of CAN FD frames with the BRS bit set.
*/
#define CAN_ESR1_ERRINT_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_FAST_SHIFT)) & CAN_ESR1_ERRINT_FAST_MASK)
#define CAN_ESR1_ERROVR_MASK (0x200000U)
#define CAN_ESR1_ERROVR_SHIFT (21U)
/*! ERROVR - Error Overrun
* 0b0..Overrun has not occurred.
* 0b1..Overrun has occurred.
*/
#define CAN_ESR1_ERROVR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERROVR_SHIFT)) & CAN_ESR1_ERROVR_MASK)
#define CAN_ESR1_STFERR_FAST_MASK (0x4000000U)
#define CAN_ESR1_STFERR_FAST_SHIFT (26U)
/*! STFERR_FAST - Stuffing Error in the Data Phase of CAN FD frames with the BRS bit set
* 0b0..No such occurrence.
* 0b1..A stuffing error occurred since last read of this register.
*/
#define CAN_ESR1_STFERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_FAST_SHIFT)) & CAN_ESR1_STFERR_FAST_MASK)
#define CAN_ESR1_FRMERR_FAST_MASK (0x8000000U)
#define CAN_ESR1_FRMERR_FAST_SHIFT (27U)
/*! FRMERR_FAST - Form Error in the Data Phase of CAN FD frames with the BRS bit set
* 0b0..No such occurrence.
* 0b1..A form error occurred since last read of this register.
*/
#define CAN_ESR1_FRMERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_FAST_SHIFT)) & CAN_ESR1_FRMERR_FAST_MASK)
#define CAN_ESR1_CRCERR_FAST_MASK (0x10000000U)
#define CAN_ESR1_CRCERR_FAST_SHIFT (28U)
/*! CRCERR_FAST - Cyclic Redundancy Check Error in the CRC field of CAN FD frames with the BRS bit set
* 0b0..No such occurrence.
* 0b1..A CRC error occurred since last read of this register.
*/
#define CAN_ESR1_CRCERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_FAST_SHIFT)) & CAN_ESR1_CRCERR_FAST_MASK)
#define CAN_ESR1_BIT0ERR_FAST_MASK (0x40000000U)
#define CAN_ESR1_BIT0ERR_FAST_SHIFT (30U)
/*! BIT0ERR_FAST - Bit0 Error in the Data Phase of CAN FD frames with the BRS bit set
* 0b0..No such occurrence.
* 0b1..At least one bit sent as dominant is received as recessive.
*/
#define CAN_ESR1_BIT0ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_FAST_SHIFT)) & CAN_ESR1_BIT0ERR_FAST_MASK)
#define CAN_ESR1_BIT1ERR_FAST_MASK (0x80000000U)
#define CAN_ESR1_BIT1ERR_FAST_SHIFT (31U)
/*! BIT1ERR_FAST - Bit1 Error in the Data Phase of CAN FD frames with the BRS bit set
* 0b0..No such occurrence.
* 0b1..At least one bit sent as recessive is received as dominant.
*/
#define CAN_ESR1_BIT1ERR_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_FAST_SHIFT)) & CAN_ESR1_BIT1ERR_FAST_MASK)
/*! @} */
/*! @name IMASK2 - Interrupt Masks 2 register */
/*! @{ */
#define CAN_IMASK2_BUF63TO32M_MASK (0xFFFFFFFFU)
#define CAN_IMASK2_BUF63TO32M_SHIFT (0U)
/*! BUF63TO32M - Buffer MBi Mask
*/
#define CAN_IMASK2_BUF63TO32M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK2_BUF63TO32M_SHIFT)) & CAN_IMASK2_BUF63TO32M_MASK)
/*! @} */
/*! @name IMASK1 - Interrupt Masks 1 register */
/*! @{ */
#define CAN_IMASK1_BUF31TO0M_MASK (0xFFFFFFFFU)
#define CAN_IMASK1_BUF31TO0M_SHIFT (0U)
/*! BUF31TO0M - Buffer MBi Mask
*/
#define CAN_IMASK1_BUF31TO0M(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUF31TO0M_SHIFT)) & CAN_IMASK1_BUF31TO0M_MASK)
/*! @} */
/*! @name IFLAG2 - Interrupt Flags 2 register */
/*! @{ */
#define CAN_IFLAG2_BUF63TO32I_MASK (0xFFFFFFFFU)
#define CAN_IFLAG2_BUF63TO32I_SHIFT (0U)
/*! BUF63TO32I - Buffer MBi Interrupt
*/
#define CAN_IFLAG2_BUF63TO32I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG2_BUF63TO32I_SHIFT)) & CAN_IFLAG2_BUF63TO32I_MASK)
/*! @} */
/*! @name IFLAG1 - Interrupt Flags 1 register */
/*! @{ */
#define CAN_IFLAG1_BUF0I_MASK (0x1U)
#define CAN_IFLAG1_BUF0I_SHIFT (0U)
/*! BUF0I - Buffer MB0 Interrupt Or Clear FIFO bit
* 0b0..The corresponding buffer has no occurrence of successfully completed transmission or reception when MCR[RFEN]=0.
* 0b1..The corresponding buffer has successfully completed transmission or reception when MCR[RFEN]=0.
*/
#define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
#define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
#define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
/*! BUF4TO1I - Buffer MBi Interrupt Or Reserved
*/
#define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
#define CAN_IFLAG1_BUF5I_MASK (0x20U)
#define CAN_IFLAG1_BUF5I_SHIFT (5U)
/*! BUF5I - Buffer MB5 Interrupt Or Frames available in Rx FIFO
* 0b0..No occurrence of MB5 completing transmission/reception when MCR[RFEN]=0, or of frame(s) available in the FIFO, when MCR[RFEN]=1
* 0b1..MB5 completed transmission/reception when MCR[RFEN]=0, or frame(s) available in the Rx FIFO when
* MCR[RFEN]=1. It generates a DMA request in case of MCR[RFEN] and MCR[DMA] are enabled.
*/
#define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
#define CAN_IFLAG1_BUF6I_MASK (0x40U)
#define CAN_IFLAG1_BUF6I_SHIFT (6U)
/*! BUF6I - Buffer MB6 Interrupt Or Rx FIFO Warning
* 0b0..No occurrence of MB6 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO almost full when MCR[RFEN]=1
* 0b1..MB6 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO almost full when MCR[RFEN]=1
*/
#define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
#define CAN_IFLAG1_BUF7I_MASK (0x80U)
#define CAN_IFLAG1_BUF7I_SHIFT (7U)
/*! BUF7I - Buffer MB7 Interrupt Or Rx FIFO Overflow
* 0b0..No occurrence of MB7 completing transmission/reception when MCR[RFEN]=0, or of Rx FIFO overflow when MCR[RFEN]=1
* 0b1..MB7 completed transmission/reception when MCR[RFEN]=0, or Rx FIFO overflow when MCR[RFEN]=1
*/
#define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
#define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
#define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
/*! BUF31TO8I - Buffer MBi Interrupt
*/
#define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
/*! @} */
/*! @name CTRL2 - Control 2 register */
/*! @{ */
#define CAN_CTRL2_EDFLTDIS_MASK (0x800U)
#define CAN_CTRL2_EDFLTDIS_SHIFT (11U)
/*! EDFLTDIS - Edge Filter Disable
* 0b0..Edge filter is enabled
* 0b1..Edge filter is disabled
*/
#define CAN_CTRL2_EDFLTDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EDFLTDIS_SHIFT)) & CAN_CTRL2_EDFLTDIS_MASK)
#define CAN_CTRL2_ISOCANFDEN_MASK (0x1000U)
#define CAN_CTRL2_ISOCANFDEN_SHIFT (12U)
/*! ISOCANFDEN - ISO CAN FD Enable
* 0b0..FlexCAN operates using the non-ISO CAN FD protocol.
* 0b1..FlexCAN operates using the ISO CAN FD protocol (ISO 11898-1).
*/
#define CAN_CTRL2_ISOCANFDEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ISOCANFDEN_SHIFT)) & CAN_CTRL2_ISOCANFDEN_MASK)
#define CAN_CTRL2_PREXCEN_MASK (0x4000U)
#define CAN_CTRL2_PREXCEN_SHIFT (14U)
/*! PREXCEN - Protocol Exception Enable
* 0b0..Protocol exception is disabled.
* 0b1..Protocol exception is enabled.
*/
#define CAN_CTRL2_PREXCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_PREXCEN_SHIFT)) & CAN_CTRL2_PREXCEN_MASK)
#define CAN_CTRL2_TIMER_SRC_MASK (0x8000U)
#define CAN_CTRL2_TIMER_SRC_SHIFT (15U)
/*! TIMER_SRC - Timer Source
* 0b0..The free running timer is clocked by the CAN bit clock, which defines the baud rate on the CAN bus.
* 0b1..The free running timer is clocked by an external time tick. The period can be either adjusted to be equal
* to the baud rate on the CAN bus, or a different value as required. See the device-specific section for
* details about the external time tick.
*/
#define CAN_CTRL2_TIMER_SRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TIMER_SRC_SHIFT)) & CAN_CTRL2_TIMER_SRC_MASK)
#define CAN_CTRL2_EACEN_MASK (0x10000U)
#define CAN_CTRL2_EACEN_SHIFT (16U)
/*! EACEN - Entire Frame Arbitration Field Comparison Enable For Rx Mailboxes
* 0b0..Rx mailbox filter's IDE bit is always compared and RTR is never compared despite mask bits.
* 0b1..Enables the comparison of both Rx mailbox filter's IDE and RTR bit with their corresponding bits within
* the incoming frame. Mask bits do apply.
*/
#define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
#define CAN_CTRL2_RRS_MASK (0x20000U)
#define CAN_CTRL2_RRS_SHIFT (17U)
/*! RRS - Remote Request Storing
* 0b0..Remote response frame is generated.
* 0b1..Remote request frame is stored.
*/
#define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
#define CAN_CTRL2_MRP_MASK (0x40000U)
#define CAN_CTRL2_MRP_SHIFT (18U)
/*! MRP - Mailboxes Reception Priority
* 0b0..Matching starts from Rx FIFO and continues on mailboxes.
* 0b1..Matching starts from mailboxes and continues on Rx FIFO.
*/
#define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
#define CAN_CTRL2_TASD_MASK (0xF80000U)
#define CAN_CTRL2_TASD_SHIFT (19U)
/*! TASD - Tx Arbitration Start Delay
*/
#define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
#define CAN_CTRL2_RFFN_MASK (0xF000000U)
#define CAN_CTRL2_RFFN_SHIFT (24U)
/*! RFFN - Number Of Rx FIFO Filters
*/
#define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
#define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
#define CAN_CTRL2_WRMFRZ_SHIFT (28U)
/*! WRMFRZ - Write-Access To Memory In Freeze Mode
* 0b0..Maintain the write access restrictions.
* 0b1..Enable unrestricted write access to FlexCAN memory.
*/
#define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
#define CAN_CTRL2_ECRWRE_MASK (0x20000000U)
#define CAN_CTRL2_ECRWRE_SHIFT (29U)
/*! ECRWRE - Error-correction Configuration Register Write Enable
* 0b0..Disable update.
* 0b1..Enable update.
*/
#define CAN_CTRL2_ECRWRE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ECRWRE_SHIFT)) & CAN_CTRL2_ECRWRE_MASK)
#define CAN_CTRL2_BOFFDONEMSK_MASK (0x40000000U)
#define CAN_CTRL2_BOFFDONEMSK_SHIFT (30U)
/*! BOFFDONEMSK - Bus Off Done Interrupt Mask
* 0b0..Bus off done interrupt disabled.
* 0b1..Bus off done interrupt enabled.
*/
#define CAN_CTRL2_BOFFDONEMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_BOFFDONEMSK_SHIFT)) & CAN_CTRL2_BOFFDONEMSK_MASK)
#define CAN_CTRL2_ERRMSK_FAST_MASK (0x80000000U)
#define CAN_CTRL2_ERRMSK_FAST_SHIFT (31U)
/*! ERRMSK_FAST - Error Interrupt Mask for errors detected in the data phase of fast CAN FD frames
* 0b0..ERRINT_FAST error interrupt disabled.
* 0b1..ERRINT_FAST error interrupt enabled.
*/
#define CAN_CTRL2_ERRMSK_FAST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_ERRMSK_FAST_SHIFT)) & CAN_CTRL2_ERRMSK_FAST_MASK)
/*! @} */
/*! @name ESR2 - Error and Status 2 register */
/*! @{ */
#define CAN_ESR2_IMB_MASK (0x2000U)
#define CAN_ESR2_IMB_SHIFT (13U)
/*! IMB - Inactive Mailbox
* 0b0..If ESR2[VPS] is asserted, the ESR2[LPTM] is not an inactive mailbox.
* 0b1..If ESR2[VPS] is asserted, there is at least one inactive mailbox. LPTM content is the number of the first one.
*/
#define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
#define CAN_ESR2_VPS_MASK (0x4000U)
#define CAN_ESR2_VPS_SHIFT (14U)
/*! VPS - Valid Priority Status
* 0b0..Contents of IMB and LPTM are invalid.
* 0b1..Contents of IMB and LPTM are valid.
*/
#define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
#define CAN_ESR2_LPTM_MASK (0x7F0000U)
#define CAN_ESR2_LPTM_SHIFT (16U)
/*! LPTM - Lowest Priority Tx Mailbox
*/
#define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
/*! @} */
/*! @name CRCR - CRC register */
/*! @{ */
#define CAN_CRCR_TXCRC_MASK (0x7FFFU)
#define CAN_CRCR_TXCRC_SHIFT (0U)
/*! TXCRC - Transmitted CRC value
*/
#define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
#define CAN_CRCR_MBCRC_MASK (0x7F0000U)
#define CAN_CRCR_MBCRC_SHIFT (16U)
/*! MBCRC - CRC Mailbox
*/
#define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
/*! @} */
/*! @name RXFGMASK - Rx FIFO Global Mask register */
/*! @{ */
#define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
#define CAN_RXFGMASK_FGM_SHIFT (0U)
/*! FGM - Rx FIFO Global Mask Bits
*/
#define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
/*! @} */
/*! @name RXFIR - Rx FIFO Information register */
/*! @{ */
#define CAN_RXFIR_IDHIT_MASK (0x1FFU)
#define CAN_RXFIR_IDHIT_SHIFT (0U)
/*! IDHIT - Identifier Acceptance Filter Hit Indicator
*/
#define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
/*! @} */
/*! @name CBT - CAN Bit Timing register */
/*! @{ */
#define CAN_CBT_EPSEG2_MASK (0x1FU)
#define CAN_CBT_EPSEG2_SHIFT (0U)
/*! EPSEG2 - Extended Phase Segment 2
*/
#define CAN_CBT_EPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG2_SHIFT)) & CAN_CBT_EPSEG2_MASK)
#define CAN_CBT_EPSEG1_MASK (0x3E0U)
#define CAN_CBT_EPSEG1_SHIFT (5U)
/*! EPSEG1 - Extended Phase Segment 1
*/
#define CAN_CBT_EPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPSEG1_SHIFT)) & CAN_CBT_EPSEG1_MASK)
#define CAN_CBT_EPROPSEG_MASK (0xFC00U)
#define CAN_CBT_EPROPSEG_SHIFT (10U)
/*! EPROPSEG - Extended Propagation Segment
*/
#define CAN_CBT_EPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPROPSEG_SHIFT)) & CAN_CBT_EPROPSEG_MASK)
#define CAN_CBT_ERJW_MASK (0x1F0000U)
#define CAN_CBT_ERJW_SHIFT (16U)
/*! ERJW - Extended Resync Jump Width
*/
#define CAN_CBT_ERJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_ERJW_SHIFT)) & CAN_CBT_ERJW_MASK)
#define CAN_CBT_EPRESDIV_MASK (0x7FE00000U)
#define CAN_CBT_EPRESDIV_SHIFT (21U)
/*! EPRESDIV - Extended Prescaler Division Factor
*/
#define CAN_CBT_EPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_EPRESDIV_SHIFT)) & CAN_CBT_EPRESDIV_MASK)
#define CAN_CBT_BTF_MASK (0x80000000U)
#define CAN_CBT_BTF_SHIFT (31U)
/*! BTF - Bit Timing Format Enable
* 0b0..Extended bit time definitions disabled.
* 0b1..Extended bit time definitions enabled.
*/
#define CAN_CBT_BTF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CBT_BTF_SHIFT)) & CAN_CBT_BTF_MASK)
/*! @} */
/* The count of CAN_CS */
#define CAN_CS_COUNT_MB8B (64U)
/* The count of CAN_ID */
#define CAN_ID_COUNT_MB8B (64U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB8B (64U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB8B2 (2U)
/* The count of CAN_CS */
#define CAN_CS_COUNT_MB16B_L (21U)
/* The count of CAN_ID */
#define CAN_ID_COUNT_MB16B_L (21U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB16B_L (21U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB16B_L2 (4U)
/* The count of CAN_CS */
#define CAN_CS_COUNT_MB16B_H (21U)
/* The count of CAN_ID */
#define CAN_ID_COUNT_MB16B_H (21U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB16B_H (21U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB16B_H2 (4U)
/* The count of CAN_CS */
#define CAN_CS_COUNT_MB32B_L (12U)
/* The count of CAN_ID */
#define CAN_ID_COUNT_MB32B_L (12U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB32B_L (12U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB32B_L2 (8U)
/* The count of CAN_CS */
#define CAN_CS_COUNT_MB32B_H (12U)
/* The count of CAN_ID */
#define CAN_ID_COUNT_MB32B_H (12U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB32B_H (12U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB32B_H2 (8U)
/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
/*! @{ */
#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
#define CAN_CS_TIME_STAMP_SHIFT (0U)
/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
* Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
* appears on the CAN bus.
*/
#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK (0xF0000U)
#define CAN_CS_DLC_SHIFT (16U)
/*! DLC - Length of the data to be stored/transmitted.
*/
#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK (0x100000U)
#define CAN_CS_RTR_SHIFT (20U)
/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
*/
#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
#define CAN_CS_IDE_MASK (0x200000U)
#define CAN_CS_IDE_SHIFT (21U)
/*! IDE - ID Extended. One/zero for extended/standard format frame.
*/
#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
#define CAN_CS_SRR_MASK (0x400000U)
#define CAN_CS_SRR_SHIFT (22U)
/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
*/
#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
#define CAN_CS_CODE_MASK (0xF000000U)
#define CAN_CS_CODE_SHIFT (24U)
/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
* the FlexCAN module itself, as part of the message buffer matching and arbitration process.
*/
#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
#define CAN_CS_ESI_MASK (0x20000000U)
#define CAN_CS_ESI_SHIFT (29U)
/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
*/
#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
#define CAN_CS_BRS_MASK (0x40000000U)
#define CAN_CS_BRS_SHIFT (30U)
/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
*/
#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
#define CAN_CS_EDL_MASK (0x80000000U)
#define CAN_CS_EDL_SHIFT (31U)
/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
* The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
*/
#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
/*! @} */
/* The count of CAN_CS */
#define CAN_CS_COUNT_MB64B_L (7U)
/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
/*! @{ */
#define CAN_ID_EXT_MASK (0x3FFFFU)
#define CAN_ID_EXT_SHIFT (0U)
/*! EXT - Contains extended (LOW word) identifier of message buffer.
*/
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK (0x1FFC0000U)
#define CAN_ID_STD_SHIFT (18U)
/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
*/
#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK (0xE0000000U)
#define CAN_ID_PRIO_SHIFT (29U)
/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
* makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
* ID to define the transmission priority.
*/
#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
/*! @} */
/* The count of CAN_ID */
#define CAN_ID_COUNT_MB64B_L (7U)
/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
/*! @{ */
#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_3_SHIFT (0U)
/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_7_SHIFT (0U)
/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_11_SHIFT (0U)
/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_15_SHIFT (0U)
/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_19_SHIFT (0U)
/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_23_SHIFT (0U)
/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_27_SHIFT (0U)
/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_31_SHIFT (0U)
/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_35_SHIFT (0U)
/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_39_SHIFT (0U)
/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_43_SHIFT (0U)
/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_47_SHIFT (0U)
/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_51_SHIFT (0U)
/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_55_SHIFT (0U)
/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_59_SHIFT (0U)
/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_63_SHIFT (0U)
/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_2_SHIFT (8U)
/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_6_SHIFT (8U)
/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_10_SHIFT (8U)
/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_14_SHIFT (8U)
/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_18_SHIFT (8U)
/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_22_SHIFT (8U)
/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_26_SHIFT (8U)
/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_30_SHIFT (8U)
/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_34_SHIFT (8U)
/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_38_SHIFT (8U)
/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_42_SHIFT (8U)
/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_46_SHIFT (8U)
/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_50_SHIFT (8U)
/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_54_SHIFT (8U)
/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_58_SHIFT (8U)
/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_62_SHIFT (8U)
/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_1_SHIFT (16U)
/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_5_SHIFT (16U)
/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_9_SHIFT (16U)
/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_13_SHIFT (16U)
/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_17_SHIFT (16U)
/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_21_SHIFT (16U)
/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_25_SHIFT (16U)
/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_29_SHIFT (16U)
/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_33_SHIFT (16U)
/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_37_SHIFT (16U)
/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_41_SHIFT (16U)
/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_45_SHIFT (16U)
/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_49_SHIFT (16U)
/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_53_SHIFT (16U)
/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_57_SHIFT (16U)
/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_61_SHIFT (16U)
/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_0_SHIFT (24U)
/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_4_SHIFT (24U)
/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_8_SHIFT (24U)
/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_12_SHIFT (24U)
/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_16_SHIFT (24U)
/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_20_SHIFT (24U)
/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_24_SHIFT (24U)
/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_28_SHIFT (24U)
/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_32_SHIFT (24U)
/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_36_SHIFT (24U)
/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_40_SHIFT (24U)
/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_44_SHIFT (24U)
/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_48_SHIFT (24U)
/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_52_SHIFT (24U)
/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_56_SHIFT (24U)
/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_60_SHIFT (24U)
/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
/*! @} */
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB64B_L (7U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB64B_L2 (16U)
/*! @name CS - Message Buffer 0 CS Register..Message Buffer 6 CS Register */
/*! @{ */
#define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
#define CAN_CS_TIME_STAMP_SHIFT (0U)
/*! TIME_STAMP - Free-Running Counter Time stamp. This 16-bit field is a copy of the Free-Running
* Timer, captured for Tx and Rx frames at the time when the beginning of the Identifier field
* appears on the CAN bus.
*/
#define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
#define CAN_CS_DLC_MASK (0xF0000U)
#define CAN_CS_DLC_SHIFT (16U)
/*! DLC - Length of the data to be stored/transmitted.
*/
#define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
#define CAN_CS_RTR_MASK (0x100000U)
#define CAN_CS_RTR_SHIFT (20U)
/*! RTR - Remote Transmission Request. One/zero for remote/data frame.
*/
#define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
#define CAN_CS_IDE_MASK (0x200000U)
#define CAN_CS_IDE_SHIFT (21U)
/*! IDE - ID Extended. One/zero for extended/standard format frame.
*/
#define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
#define CAN_CS_SRR_MASK (0x400000U)
#define CAN_CS_SRR_SHIFT (22U)
/*! SRR - Substitute Remote Request. Contains a fixed recessive bit.
*/
#define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
#define CAN_CS_CODE_MASK (0xF000000U)
#define CAN_CS_CODE_SHIFT (24U)
/*! CODE - Message Buffer Code. This 4-bit field can be accessed (read or write) by the CPU and by
* the FlexCAN module itself, as part of the message buffer matching and arbitration process.
*/
#define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
#define CAN_CS_ESI_MASK (0x20000000U)
#define CAN_CS_ESI_SHIFT (29U)
/*! ESI - Error State Indicator. This bit indicates if the transmitting node is error active or error passive.
*/
#define CAN_CS_ESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_ESI_SHIFT)) & CAN_CS_ESI_MASK)
#define CAN_CS_BRS_MASK (0x40000000U)
#define CAN_CS_BRS_SHIFT (30U)
/*! BRS - Bit Rate Switch. This bit defines whether the bit rate is switched inside a CAN FD format frame.
*/
#define CAN_CS_BRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_BRS_SHIFT)) & CAN_CS_BRS_MASK)
#define CAN_CS_EDL_MASK (0x80000000U)
#define CAN_CS_EDL_SHIFT (31U)
/*! EDL - Extended Data Length. This bit distinguishes between CAN format and CAN FD format frames.
* The EDL bit must not be set for Message Buffers configured to RANSWER with code field 0b1010.
*/
#define CAN_CS_EDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_EDL_SHIFT)) & CAN_CS_EDL_MASK)
/*! @} */
/* The count of CAN_CS */
#define CAN_CS_COUNT_MB64B_H (7U)
/*! @name ID - Message Buffer 0 ID Register..Message Buffer 6 ID Register */
/*! @{ */
#define CAN_ID_EXT_MASK (0x3FFFFU)
#define CAN_ID_EXT_SHIFT (0U)
/*! EXT - Contains extended (LOW word) identifier of message buffer.
*/
#define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
#define CAN_ID_STD_MASK (0x1FFC0000U)
#define CAN_ID_STD_SHIFT (18U)
/*! STD - Contains standard/extended (HIGH word) identifier of message buffer.
*/
#define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
#define CAN_ID_PRIO_MASK (0xE0000000U)
#define CAN_ID_PRIO_SHIFT (29U)
/*! PRIO - Local priority. This 3-bit fieldis only used when LPRIO_EN bit is set in MCR and it only
* makes sense for Tx buffers. These bits are not transmitted. They are appended to the regular
* ID to define the transmission priority.
*/
#define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
/*! @} */
/* The count of CAN_ID */
#define CAN_ID_COUNT_MB64B_H (7U)
/*! @name WORD - Message Buffer 0 WORD_64B Register..Message Buffer 6 WORD_64B Register */
/*! @{ */
#define CAN_WORD_DATA_BYTE_3_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_3_SHIFT (0U)
/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_3_SHIFT)) & CAN_WORD_DATA_BYTE_3_MASK)
#define CAN_WORD_DATA_BYTE_7_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_7_SHIFT (0U)
/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_7_SHIFT)) & CAN_WORD_DATA_BYTE_7_MASK)
#define CAN_WORD_DATA_BYTE_11_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_11_SHIFT (0U)
/*! DATA_BYTE_11 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_11(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_11_SHIFT)) & CAN_WORD_DATA_BYTE_11_MASK)
#define CAN_WORD_DATA_BYTE_15_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_15_SHIFT (0U)
/*! DATA_BYTE_15 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_15(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_15_SHIFT)) & CAN_WORD_DATA_BYTE_15_MASK)
#define CAN_WORD_DATA_BYTE_19_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_19_SHIFT (0U)
/*! DATA_BYTE_19 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_19(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_19_SHIFT)) & CAN_WORD_DATA_BYTE_19_MASK)
#define CAN_WORD_DATA_BYTE_23_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_23_SHIFT (0U)
/*! DATA_BYTE_23 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_23(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_23_SHIFT)) & CAN_WORD_DATA_BYTE_23_MASK)
#define CAN_WORD_DATA_BYTE_27_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_27_SHIFT (0U)
/*! DATA_BYTE_27 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_27(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_27_SHIFT)) & CAN_WORD_DATA_BYTE_27_MASK)
#define CAN_WORD_DATA_BYTE_31_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_31_SHIFT (0U)
/*! DATA_BYTE_31 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_31(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_31_SHIFT)) & CAN_WORD_DATA_BYTE_31_MASK)
#define CAN_WORD_DATA_BYTE_35_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_35_SHIFT (0U)
/*! DATA_BYTE_35 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_35(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_35_SHIFT)) & CAN_WORD_DATA_BYTE_35_MASK)
#define CAN_WORD_DATA_BYTE_39_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_39_SHIFT (0U)
/*! DATA_BYTE_39 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_39(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_39_SHIFT)) & CAN_WORD_DATA_BYTE_39_MASK)
#define CAN_WORD_DATA_BYTE_43_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_43_SHIFT (0U)
/*! DATA_BYTE_43 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_43(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_43_SHIFT)) & CAN_WORD_DATA_BYTE_43_MASK)
#define CAN_WORD_DATA_BYTE_47_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_47_SHIFT (0U)
/*! DATA_BYTE_47 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_47(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_47_SHIFT)) & CAN_WORD_DATA_BYTE_47_MASK)
#define CAN_WORD_DATA_BYTE_51_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_51_SHIFT (0U)
/*! DATA_BYTE_51 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_51(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_51_SHIFT)) & CAN_WORD_DATA_BYTE_51_MASK)
#define CAN_WORD_DATA_BYTE_55_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_55_SHIFT (0U)
/*! DATA_BYTE_55 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_55(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_55_SHIFT)) & CAN_WORD_DATA_BYTE_55_MASK)
#define CAN_WORD_DATA_BYTE_59_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_59_SHIFT (0U)
/*! DATA_BYTE_59 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_59(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_59_SHIFT)) & CAN_WORD_DATA_BYTE_59_MASK)
#define CAN_WORD_DATA_BYTE_63_MASK (0xFFU)
#define CAN_WORD_DATA_BYTE_63_SHIFT (0U)
/*! DATA_BYTE_63 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_63(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_63_SHIFT)) & CAN_WORD_DATA_BYTE_63_MASK)
#define CAN_WORD_DATA_BYTE_2_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_2_SHIFT (8U)
/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_2_SHIFT)) & CAN_WORD_DATA_BYTE_2_MASK)
#define CAN_WORD_DATA_BYTE_6_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_6_SHIFT (8U)
/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_6_SHIFT)) & CAN_WORD_DATA_BYTE_6_MASK)
#define CAN_WORD_DATA_BYTE_10_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_10_SHIFT (8U)
/*! DATA_BYTE_10 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_10(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_10_SHIFT)) & CAN_WORD_DATA_BYTE_10_MASK)
#define CAN_WORD_DATA_BYTE_14_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_14_SHIFT (8U)
/*! DATA_BYTE_14 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_14(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_14_SHIFT)) & CAN_WORD_DATA_BYTE_14_MASK)
#define CAN_WORD_DATA_BYTE_18_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_18_SHIFT (8U)
/*! DATA_BYTE_18 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_18(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_18_SHIFT)) & CAN_WORD_DATA_BYTE_18_MASK)
#define CAN_WORD_DATA_BYTE_22_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_22_SHIFT (8U)
/*! DATA_BYTE_22 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_22(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_22_SHIFT)) & CAN_WORD_DATA_BYTE_22_MASK)
#define CAN_WORD_DATA_BYTE_26_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_26_SHIFT (8U)
/*! DATA_BYTE_26 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_26(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_26_SHIFT)) & CAN_WORD_DATA_BYTE_26_MASK)
#define CAN_WORD_DATA_BYTE_30_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_30_SHIFT (8U)
/*! DATA_BYTE_30 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_30(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_30_SHIFT)) & CAN_WORD_DATA_BYTE_30_MASK)
#define CAN_WORD_DATA_BYTE_34_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_34_SHIFT (8U)
/*! DATA_BYTE_34 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_34(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_34_SHIFT)) & CAN_WORD_DATA_BYTE_34_MASK)
#define CAN_WORD_DATA_BYTE_38_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_38_SHIFT (8U)
/*! DATA_BYTE_38 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_38(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_38_SHIFT)) & CAN_WORD_DATA_BYTE_38_MASK)
#define CAN_WORD_DATA_BYTE_42_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_42_SHIFT (8U)
/*! DATA_BYTE_42 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_42(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_42_SHIFT)) & CAN_WORD_DATA_BYTE_42_MASK)
#define CAN_WORD_DATA_BYTE_46_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_46_SHIFT (8U)
/*! DATA_BYTE_46 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_46(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_46_SHIFT)) & CAN_WORD_DATA_BYTE_46_MASK)
#define CAN_WORD_DATA_BYTE_50_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_50_SHIFT (8U)
/*! DATA_BYTE_50 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_50(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_50_SHIFT)) & CAN_WORD_DATA_BYTE_50_MASK)
#define CAN_WORD_DATA_BYTE_54_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_54_SHIFT (8U)
/*! DATA_BYTE_54 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_54(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_54_SHIFT)) & CAN_WORD_DATA_BYTE_54_MASK)
#define CAN_WORD_DATA_BYTE_58_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_58_SHIFT (8U)
/*! DATA_BYTE_58 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_58(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_58_SHIFT)) & CAN_WORD_DATA_BYTE_58_MASK)
#define CAN_WORD_DATA_BYTE_62_MASK (0xFF00U)
#define CAN_WORD_DATA_BYTE_62_SHIFT (8U)
/*! DATA_BYTE_62 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_62(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_62_SHIFT)) & CAN_WORD_DATA_BYTE_62_MASK)
#define CAN_WORD_DATA_BYTE_1_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_1_SHIFT (16U)
/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_1_SHIFT)) & CAN_WORD_DATA_BYTE_1_MASK)
#define CAN_WORD_DATA_BYTE_5_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_5_SHIFT (16U)
/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_5_SHIFT)) & CAN_WORD_DATA_BYTE_5_MASK)
#define CAN_WORD_DATA_BYTE_9_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_9_SHIFT (16U)
/*! DATA_BYTE_9 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_9(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_9_SHIFT)) & CAN_WORD_DATA_BYTE_9_MASK)
#define CAN_WORD_DATA_BYTE_13_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_13_SHIFT (16U)
/*! DATA_BYTE_13 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_13(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_13_SHIFT)) & CAN_WORD_DATA_BYTE_13_MASK)
#define CAN_WORD_DATA_BYTE_17_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_17_SHIFT (16U)
/*! DATA_BYTE_17 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_17(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_17_SHIFT)) & CAN_WORD_DATA_BYTE_17_MASK)
#define CAN_WORD_DATA_BYTE_21_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_21_SHIFT (16U)
/*! DATA_BYTE_21 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_21(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_21_SHIFT)) & CAN_WORD_DATA_BYTE_21_MASK)
#define CAN_WORD_DATA_BYTE_25_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_25_SHIFT (16U)
/*! DATA_BYTE_25 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_25(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_25_SHIFT)) & CAN_WORD_DATA_BYTE_25_MASK)
#define CAN_WORD_DATA_BYTE_29_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_29_SHIFT (16U)
/*! DATA_BYTE_29 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_29(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_29_SHIFT)) & CAN_WORD_DATA_BYTE_29_MASK)
#define CAN_WORD_DATA_BYTE_33_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_33_SHIFT (16U)
/*! DATA_BYTE_33 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_33(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_33_SHIFT)) & CAN_WORD_DATA_BYTE_33_MASK)
#define CAN_WORD_DATA_BYTE_37_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_37_SHIFT (16U)
/*! DATA_BYTE_37 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_37(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_37_SHIFT)) & CAN_WORD_DATA_BYTE_37_MASK)
#define CAN_WORD_DATA_BYTE_41_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_41_SHIFT (16U)
/*! DATA_BYTE_41 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_41(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_41_SHIFT)) & CAN_WORD_DATA_BYTE_41_MASK)
#define CAN_WORD_DATA_BYTE_45_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_45_SHIFT (16U)
/*! DATA_BYTE_45 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_45(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_45_SHIFT)) & CAN_WORD_DATA_BYTE_45_MASK)
#define CAN_WORD_DATA_BYTE_49_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_49_SHIFT (16U)
/*! DATA_BYTE_49 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_49(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_49_SHIFT)) & CAN_WORD_DATA_BYTE_49_MASK)
#define CAN_WORD_DATA_BYTE_53_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_53_SHIFT (16U)
/*! DATA_BYTE_53 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_53(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_53_SHIFT)) & CAN_WORD_DATA_BYTE_53_MASK)
#define CAN_WORD_DATA_BYTE_57_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_57_SHIFT (16U)
/*! DATA_BYTE_57 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_57(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_57_SHIFT)) & CAN_WORD_DATA_BYTE_57_MASK)
#define CAN_WORD_DATA_BYTE_61_MASK (0xFF0000U)
#define CAN_WORD_DATA_BYTE_61_SHIFT (16U)
/*! DATA_BYTE_61 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_61(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_61_SHIFT)) & CAN_WORD_DATA_BYTE_61_MASK)
#define CAN_WORD_DATA_BYTE_0_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_0_SHIFT (24U)
/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_0_SHIFT)) & CAN_WORD_DATA_BYTE_0_MASK)
#define CAN_WORD_DATA_BYTE_4_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_4_SHIFT (24U)
/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_4_SHIFT)) & CAN_WORD_DATA_BYTE_4_MASK)
#define CAN_WORD_DATA_BYTE_8_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_8_SHIFT (24U)
/*! DATA_BYTE_8 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_8(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_8_SHIFT)) & CAN_WORD_DATA_BYTE_8_MASK)
#define CAN_WORD_DATA_BYTE_12_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_12_SHIFT (24U)
/*! DATA_BYTE_12 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_12(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_12_SHIFT)) & CAN_WORD_DATA_BYTE_12_MASK)
#define CAN_WORD_DATA_BYTE_16_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_16_SHIFT (24U)
/*! DATA_BYTE_16 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_16(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_16_SHIFT)) & CAN_WORD_DATA_BYTE_16_MASK)
#define CAN_WORD_DATA_BYTE_20_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_20_SHIFT (24U)
/*! DATA_BYTE_20 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_20(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_20_SHIFT)) & CAN_WORD_DATA_BYTE_20_MASK)
#define CAN_WORD_DATA_BYTE_24_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_24_SHIFT (24U)
/*! DATA_BYTE_24 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_24(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_24_SHIFT)) & CAN_WORD_DATA_BYTE_24_MASK)
#define CAN_WORD_DATA_BYTE_28_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_28_SHIFT (24U)
/*! DATA_BYTE_28 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_28(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_28_SHIFT)) & CAN_WORD_DATA_BYTE_28_MASK)
#define CAN_WORD_DATA_BYTE_32_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_32_SHIFT (24U)
/*! DATA_BYTE_32 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_32(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_32_SHIFT)) & CAN_WORD_DATA_BYTE_32_MASK)
#define CAN_WORD_DATA_BYTE_36_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_36_SHIFT (24U)
/*! DATA_BYTE_36 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_36(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_36_SHIFT)) & CAN_WORD_DATA_BYTE_36_MASK)
#define CAN_WORD_DATA_BYTE_40_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_40_SHIFT (24U)
/*! DATA_BYTE_40 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_40(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_40_SHIFT)) & CAN_WORD_DATA_BYTE_40_MASK)
#define CAN_WORD_DATA_BYTE_44_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_44_SHIFT (24U)
/*! DATA_BYTE_44 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_44(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_44_SHIFT)) & CAN_WORD_DATA_BYTE_44_MASK)
#define CAN_WORD_DATA_BYTE_48_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_48_SHIFT (24U)
/*! DATA_BYTE_48 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_48(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_48_SHIFT)) & CAN_WORD_DATA_BYTE_48_MASK)
#define CAN_WORD_DATA_BYTE_52_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_52_SHIFT (24U)
/*! DATA_BYTE_52 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_52(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_52_SHIFT)) & CAN_WORD_DATA_BYTE_52_MASK)
#define CAN_WORD_DATA_BYTE_56_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_56_SHIFT (24U)
/*! DATA_BYTE_56 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_56(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_56_SHIFT)) & CAN_WORD_DATA_BYTE_56_MASK)
#define CAN_WORD_DATA_BYTE_60_MASK (0xFF000000U)
#define CAN_WORD_DATA_BYTE_60_SHIFT (24U)
/*! DATA_BYTE_60 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD_DATA_BYTE_60(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD_DATA_BYTE_60_SHIFT)) & CAN_WORD_DATA_BYTE_60_MASK)
/*! @} */
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB64B_H (7U)
/* The count of CAN_WORD */
#define CAN_WORD_COUNT_MB64B_H2 (16U)
/* The count of CAN_CS */
#define CAN_CS_COUNT (64U)
/* The count of CAN_ID */
#define CAN_ID_COUNT (64U)
/*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 63 WORD0 Register */
/*! @{ */
#define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
#define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
/*! DATA_BYTE_3 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
#define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
#define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
/*! DATA_BYTE_2 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
#define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
#define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
/*! DATA_BYTE_1 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
#define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
#define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
/*! DATA_BYTE_0 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
/*! @} */
/* The count of CAN_WORD0 */
#define CAN_WORD0_COUNT (64U)
/*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 63 WORD1 Register */
/*! @{ */
#define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
#define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
/*! DATA_BYTE_7 - Data byte 0 of Rx/Tx frame.
*/
#define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
#define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
#define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
/*! DATA_BYTE_6 - Data byte 1 of Rx/Tx frame.
*/
#define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
#define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
#define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
/*! DATA_BYTE_5 - Data byte 2 of Rx/Tx frame.
*/
#define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
#define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
#define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
/*! DATA_BYTE_4 - Data byte 3 of Rx/Tx frame.
*/
#define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
/*! @} */
/* The count of CAN_WORD1 */
#define CAN_WORD1_COUNT (64U)
/*! @name RXIMR - Rx Individual Mask registers */
/*! @{ */
#define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
#define CAN_RXIMR_MI_SHIFT (0U)
/*! MI - Individual Mask Bits
*/
#define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
/*! @} */
/* The count of CAN_RXIMR */
#define CAN_RXIMR_COUNT (64U)
/*! @name MECR - Memory Error Control register */
/*! @{ */
#define CAN_MECR_NCEFAFRZ_MASK (0x80U)
#define CAN_MECR_NCEFAFRZ_SHIFT (7U)
/*! NCEFAFRZ - Non-Correctable Errors In FlexCAN Access Put Device In Freeze Mode
* 0b0..Keep normal operation.
* 0b1..Put FlexCAN in Freeze mode (see section "Freeze mode").
*/
#define CAN_MECR_NCEFAFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_NCEFAFRZ_SHIFT)) & CAN_MECR_NCEFAFRZ_MASK)
#define CAN_MECR_ECCDIS_MASK (0x100U)
#define CAN_MECR_ECCDIS_SHIFT (8U)
/*! ECCDIS - Error Correction Disable
* 0b0..Enable memory error correction.
* 0b1..Disable memory error correction.
*/
#define CAN_MECR_ECCDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECCDIS_SHIFT)) & CAN_MECR_ECCDIS_MASK)
#define CAN_MECR_RERRDIS_MASK (0x200U)
#define CAN_MECR_RERRDIS_SHIFT (9U)
/*! RERRDIS - Error Report Disable
* 0b0..Enable updates of the error report registers.
* 0b1..Disable updates of the error report registers.
*/
#define CAN_MECR_RERRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_RERRDIS_SHIFT)) & CAN_MECR_RERRDIS_MASK)
#define CAN_MECR_EXTERRIE_MASK (0x2000U)
#define CAN_MECR_EXTERRIE_SHIFT (13U)
/*! EXTERRIE - Extended Error Injection Enable
* 0b0..Error injection is applied only to the 32-bit word.
* 0b1..Error injection is applied to the 64-bit word.
*/
#define CAN_MECR_EXTERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_EXTERRIE_SHIFT)) & CAN_MECR_EXTERRIE_MASK)
#define CAN_MECR_FAERRIE_MASK (0x4000U)
#define CAN_MECR_FAERRIE_SHIFT (14U)
/*! FAERRIE - FlexCAN Access Error Injection Enable
* 0b0..Injection is disabled.
* 0b1..Injection is enabled.
*/
#define CAN_MECR_FAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FAERRIE_SHIFT)) & CAN_MECR_FAERRIE_MASK)
#define CAN_MECR_HAERRIE_MASK (0x8000U)
#define CAN_MECR_HAERRIE_SHIFT (15U)
/*! HAERRIE - Host Access Error Injection Enable
* 0b0..Injection is disabled.
* 0b1..Injection is enabled.
*/
#define CAN_MECR_HAERRIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HAERRIE_SHIFT)) & CAN_MECR_HAERRIE_MASK)
#define CAN_MECR_CEI_MSK_MASK (0x10000U)
#define CAN_MECR_CEI_MSK_SHIFT (16U)
/*! CEI_MSK - Correctable Errors Interrupt Mask
* 0b0..Interrupt is disabled.
* 0b1..Interrupt is enabled.
*/
#define CAN_MECR_CEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_CEI_MSK_SHIFT)) & CAN_MECR_CEI_MSK_MASK)
#define CAN_MECR_FANCEI_MSK_MASK (0x40000U)
#define CAN_MECR_FANCEI_MSK_SHIFT (18U)
/*! FANCEI_MSK - FlexCAN Access With Non-Correctable Errors Interrupt Mask
* 0b0..Interrupt is disabled.
* 0b1..Interrupt is enabled.
*/
#define CAN_MECR_FANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_FANCEI_MSK_SHIFT)) & CAN_MECR_FANCEI_MSK_MASK)
#define CAN_MECR_HANCEI_MSK_MASK (0x80000U)
#define CAN_MECR_HANCEI_MSK_SHIFT (19U)
/*! HANCEI_MSK - Host Access With Non-Correctable Errors Interrupt Mask
* 0b0..Interrupt is disabled.
* 0b1..Interrupt is enabled.
*/
#define CAN_MECR_HANCEI_MSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_HANCEI_MSK_SHIFT)) & CAN_MECR_HANCEI_MSK_MASK)
#define CAN_MECR_ECRWRDIS_MASK (0x80000000U)
#define CAN_MECR_ECRWRDIS_SHIFT (31U)
/*! ECRWRDIS - Error Configuration Register Write Disable
* 0b0..Write is enabled.
* 0b1..Write is disabled.
*/
#define CAN_MECR_ECRWRDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MECR_ECRWRDIS_SHIFT)) & CAN_MECR_ECRWRDIS_MASK)
/*! @} */
/*! @name ERRIAR - Error Injection Address register */
/*! @{ */
#define CAN_ERRIAR_INJADDR_L_MASK (0x3U)
#define CAN_ERRIAR_INJADDR_L_SHIFT (0U)
/*! INJADDR_L - Error Injection Address Low
*/
#define CAN_ERRIAR_INJADDR_L(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_L_SHIFT)) & CAN_ERRIAR_INJADDR_L_MASK)
#define CAN_ERRIAR_INJADDR_H_MASK (0x3FFCU)
#define CAN_ERRIAR_INJADDR_H_SHIFT (2U)
/*! INJADDR_H - Error Injection Address High
*/
#define CAN_ERRIAR_INJADDR_H(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIAR_INJADDR_H_SHIFT)) & CAN_ERRIAR_INJADDR_H_MASK)
/*! @} */
/*! @name ERRIDPR - Error Injection Data Pattern register */
/*! @{ */
#define CAN_ERRIDPR_DFLIP_MASK (0xFFFFFFFFU)
#define CAN_ERRIDPR_DFLIP_SHIFT (0U)
/*! DFLIP - Data flip pattern
*/
#define CAN_ERRIDPR_DFLIP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIDPR_DFLIP_SHIFT)) & CAN_ERRIDPR_DFLIP_MASK)
/*! @} */
/*! @name ERRIPPR - Error Injection Parity Pattern register */
/*! @{ */
#define CAN_ERRIPPR_PFLIP0_MASK (0x1FU)
#define CAN_ERRIPPR_PFLIP0_SHIFT (0U)
/*! PFLIP0 - Parity Flip Pattern For Byte 0 (Least Significant)
*/
#define CAN_ERRIPPR_PFLIP0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP0_SHIFT)) & CAN_ERRIPPR_PFLIP0_MASK)
#define CAN_ERRIPPR_PFLIP1_MASK (0x1F00U)
#define CAN_ERRIPPR_PFLIP1_SHIFT (8U)
/*! PFLIP1 - Parity Flip Pattern For Byte 1
*/
#define CAN_ERRIPPR_PFLIP1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP1_SHIFT)) & CAN_ERRIPPR_PFLIP1_MASK)
#define CAN_ERRIPPR_PFLIP2_MASK (0x1F0000U)
#define CAN_ERRIPPR_PFLIP2_SHIFT (16U)
/*! PFLIP2 - Parity Flip Pattern For Byte 2
*/
#define CAN_ERRIPPR_PFLIP2(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP2_SHIFT)) & CAN_ERRIPPR_PFLIP2_MASK)
#define CAN_ERRIPPR_PFLIP3_MASK (0x1F000000U)
#define CAN_ERRIPPR_PFLIP3_SHIFT (24U)
/*! PFLIP3 - Parity Flip Pattern For Byte 3 (most significant)
*/
#define CAN_ERRIPPR_PFLIP3(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRIPPR_PFLIP3_SHIFT)) & CAN_ERRIPPR_PFLIP3_MASK)
/*! @} */
/*! @name RERRAR - Error Report Address register */
/*! @{ */
#define CAN_RERRAR_ERRADDR_MASK (0x3FFFU)
#define CAN_RERRAR_ERRADDR_SHIFT (0U)
/*! ERRADDR - Address Where Error Detected
*/
#define CAN_RERRAR_ERRADDR(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_ERRADDR_SHIFT)) & CAN_RERRAR_ERRADDR_MASK)
#define CAN_RERRAR_SAID_MASK (0x70000U)
#define CAN_RERRAR_SAID_SHIFT (16U)
/*! SAID - SAID
*/
#define CAN_RERRAR_SAID(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_SAID_SHIFT)) & CAN_RERRAR_SAID_MASK)
#define CAN_RERRAR_NCE_MASK (0x1000000U)
#define CAN_RERRAR_NCE_SHIFT (24U)
/*! NCE - Non-Correctable Error
* 0b0..Reporting a correctable error
* 0b1..Reporting a non-correctable error
*/
#define CAN_RERRAR_NCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRAR_NCE_SHIFT)) & CAN_RERRAR_NCE_MASK)
/*! @} */
/*! @name RERRDR - Error Report Data register */
/*! @{ */
#define CAN_RERRDR_RDATA_MASK (0xFFFFFFFFU)
#define CAN_RERRDR_RDATA_SHIFT (0U)
/*! RDATA - Raw data word read from memory with error
*/
#define CAN_RERRDR_RDATA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRDR_RDATA_SHIFT)) & CAN_RERRDR_RDATA_MASK)
/*! @} */
/*! @name RERRSYNR - Error Report Syndrome register */
/*! @{ */
#define CAN_RERRSYNR_SYND0_MASK (0x1FU)
#define CAN_RERRSYNR_SYND0_SHIFT (0U)
/*! SYND0 - Error Syndrome For Byte 0 (least significant)
*/
#define CAN_RERRSYNR_SYND0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND0_SHIFT)) & CAN_RERRSYNR_SYND0_MASK)
#define CAN_RERRSYNR_BE0_MASK (0x80U)
#define CAN_RERRSYNR_BE0_SHIFT (7U)
/*! BE0 - Byte Enabled For Byte 0 (least significant)
* 0b0..The byte was not read.
* 0b1..The byte was read.
*/
#define CAN_RERRSYNR_BE0(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE0_SHIFT)) & CAN_RERRSYNR_BE0_MASK)
#define CAN_RERRSYNR_SYND1_MASK (0x1F00U)
#define CAN_RERRSYNR_SYND1_SHIFT (8U)
/*! SYND1 - Error Syndrome for Byte 1
*/
#define CAN_RERRSYNR_SYND1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND1_SHIFT)) & CAN_RERRSYNR_SYND1_MASK)
#define CAN_RERRSYNR_BE1_MASK (0x8000U)
#define CAN_RERRSYNR_BE1_SHIFT (15U)
/*! BE1 - Byte Enabled For Byte 1
* 0b0..The byte was not read.
* 0b1..The byte was read.
*/
#define CAN_RERRSYNR_BE1(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE1_SHIFT)) & CAN_RERRSYNR_BE1_MASK)
#define CAN_RERRSYNR_SYND2_MASK (0x1F0000U)
#define CAN_RERRSYNR_SYND2_SHIFT (16U)
/*! SYND2 - Error Syndrome For Byte 2
*/
#define CAN_RERRSYNR_SYND2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND2_SHIFT)) & CAN_RERRSYNR_SYND2_MASK)
#define CAN_RERRSYNR_BE2_MASK (0x800000U)
#define CAN_RERRSYNR_BE2_SHIFT (23U)
/*! BE2 - Byte Enabled For Byte 2
* 0b0..The byte was not read.
* 0b1..The byte was read.
*/
#define CAN_RERRSYNR_BE2(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE2_SHIFT)) & CAN_RERRSYNR_BE2_MASK)
#define CAN_RERRSYNR_SYND3_MASK (0x1F000000U)
#define CAN_RERRSYNR_SYND3_SHIFT (24U)
/*! SYND3 - Error Syndrome For Byte 3 (most significant)
*/
#define CAN_RERRSYNR_SYND3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_SYND3_SHIFT)) & CAN_RERRSYNR_SYND3_MASK)
#define CAN_RERRSYNR_BE3_MASK (0x80000000U)
#define CAN_RERRSYNR_BE3_SHIFT (31U)
/*! BE3 - Byte Enabled For Byte 3 (most significant)
* 0b0..The byte was not read.
* 0b1..The byte was read.
*/
#define CAN_RERRSYNR_BE3(x) (((uint32_t)(((uint32_t)(x)) << CAN_RERRSYNR_BE3_SHIFT)) & CAN_RERRSYNR_BE3_MASK)
/*! @} */
/*! @name ERRSR - Error Status register */
/*! @{ */
#define CAN_ERRSR_CEIOF_MASK (0x1U)
#define CAN_ERRSR_CEIOF_SHIFT (0U)
/*! CEIOF - Correctable Error Interrupt Overrun Flag
* 0b0..No overrun on correctable errors
* 0b1..Overrun on correctable errors
*/
#define CAN_ERRSR_CEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIOF_SHIFT)) & CAN_ERRSR_CEIOF_MASK)
#define CAN_ERRSR_FANCEIOF_MASK (0x4U)
#define CAN_ERRSR_FANCEIOF_SHIFT (2U)
/*! FANCEIOF - FlexCAN Access With Non-Correctable Error Interrupt Overrun Flag
* 0b0..No overrun on non-correctable errors in FlexCAN access
* 0b1..Overrun on non-correctable errors in FlexCAN access
*/
#define CAN_ERRSR_FANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIOF_SHIFT)) & CAN_ERRSR_FANCEIOF_MASK)
#define CAN_ERRSR_HANCEIOF_MASK (0x8U)
#define CAN_ERRSR_HANCEIOF_SHIFT (3U)
/*! HANCEIOF - Host Access With Non-Correctable Error Interrupt Overrun Flag
* 0b0..No overrun on non-correctable errors in host access
* 0b1..Overrun on non-correctable errors in host access
*/
#define CAN_ERRSR_HANCEIOF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIOF_SHIFT)) & CAN_ERRSR_HANCEIOF_MASK)
#define CAN_ERRSR_CEIF_MASK (0x10000U)
#define CAN_ERRSR_CEIF_SHIFT (16U)
/*! CEIF - Correctable Error Interrupt Flag
* 0b0..No correctable errors were detected so far.
* 0b1..A correctable error was detected.
*/
#define CAN_ERRSR_CEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_CEIF_SHIFT)) & CAN_ERRSR_CEIF_MASK)
#define CAN_ERRSR_FANCEIF_MASK (0x40000U)
#define CAN_ERRSR_FANCEIF_SHIFT (18U)
/*! FANCEIF - FlexCAN Access With Non-Correctable Error Interrupt Flag
* 0b0..No non-correctable errors were detected in FlexCAN accesses so far.
* 0b1..A non-correctable error was detected in a FlexCAN access.
*/
#define CAN_ERRSR_FANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_FANCEIF_SHIFT)) & CAN_ERRSR_FANCEIF_MASK)
#define CAN_ERRSR_HANCEIF_MASK (0x80000U)
#define CAN_ERRSR_HANCEIF_SHIFT (19U)
/*! HANCEIF - Host Access With Non-Correctable Error Interrupt Flag
* 0b0..No non-correctable errors were detected in host accesses so far.
* 0b1..A non-correctable error was detected in a host access.
*/
#define CAN_ERRSR_HANCEIF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ERRSR_HANCEIF_SHIFT)) & CAN_ERRSR_HANCEIF_MASK)
/*! @} */
/*! @name FDCTRL - CAN FD Control register */
/*! @{ */
#define CAN_FDCTRL_TDCVAL_MASK (0x3FU)
#define CAN_FDCTRL_TDCVAL_SHIFT (0U)
/*! TDCVAL - Transceiver Delay Compensation Value
*/
#define CAN_FDCTRL_TDCVAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCVAL_SHIFT)) & CAN_FDCTRL_TDCVAL_MASK)
#define CAN_FDCTRL_TDCOFF_MASK (0x1F00U)
#define CAN_FDCTRL_TDCOFF_SHIFT (8U)
/*! TDCOFF - Transceiver Delay Compensation Offset
*/
#define CAN_FDCTRL_TDCOFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCOFF_SHIFT)) & CAN_FDCTRL_TDCOFF_MASK)
#define CAN_FDCTRL_TDCFAIL_MASK (0x4000U)
#define CAN_FDCTRL_TDCFAIL_SHIFT (14U)
/*! TDCFAIL - Transceiver Delay Compensation Fail
* 0b0..Measured loop delay is in range.
* 0b1..Measured loop delay is out of range.
*/
#define CAN_FDCTRL_TDCFAIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCFAIL_SHIFT)) & CAN_FDCTRL_TDCFAIL_MASK)
#define CAN_FDCTRL_TDCEN_MASK (0x8000U)
#define CAN_FDCTRL_TDCEN_SHIFT (15U)
/*! TDCEN - Transceiver Delay Compensation Enable
* 0b0..TDC is disabled
* 0b1..TDC is enabled
*/
#define CAN_FDCTRL_TDCEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_TDCEN_SHIFT)) & CAN_FDCTRL_TDCEN_MASK)
#define CAN_FDCTRL_MBDSR0_MASK (0x30000U)
#define CAN_FDCTRL_MBDSR0_SHIFT (16U)
/*! MBDSR0 - Message Buffer Data Size for Region 0
* 0b00..Selects 8 bytes per message buffer.
* 0b01..Selects 16 bytes per message buffer.
* 0b10..Selects 32 bytes per message buffer.
* 0b11..Selects 64 bytes per message buffer.
*/
#define CAN_FDCTRL_MBDSR0(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR0_SHIFT)) & CAN_FDCTRL_MBDSR0_MASK)
#define CAN_FDCTRL_MBDSR1_MASK (0x180000U)
#define CAN_FDCTRL_MBDSR1_SHIFT (19U)
/*! MBDSR1 - Message Buffer Data Size for Region 1
* 0b00..Selects 8 bytes per message buffer.
* 0b01..Selects 16 bytes per message buffer.
* 0b10..Selects 32 bytes per message buffer.
* 0b11..Selects 64 bytes per message buffer.
*/
#define CAN_FDCTRL_MBDSR1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_MBDSR1_SHIFT)) & CAN_FDCTRL_MBDSR1_MASK)
#define CAN_FDCTRL_FDRATE_MASK (0x80000000U)
#define CAN_FDCTRL_FDRATE_SHIFT (31U)
/*! FDRATE - Bit Rate Switch Enable
* 0b0..Transmit a frame in nominal rate. The BRS bit in the Tx MB has no effect.
* 0b1..Transmit a frame with bit rate switching if the BRS bit in the Tx MB is recessive.
*/
#define CAN_FDCTRL_FDRATE(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCTRL_FDRATE_SHIFT)) & CAN_FDCTRL_FDRATE_MASK)
/*! @} */
/*! @name FDCBT - CAN FD Bit Timing register */
/*! @{ */
#define CAN_FDCBT_FPSEG2_MASK (0x7U)
#define CAN_FDCBT_FPSEG2_SHIFT (0U)
/*! FPSEG2 - Fast Phase Segment 2
*/
#define CAN_FDCBT_FPSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG2_SHIFT)) & CAN_FDCBT_FPSEG2_MASK)
#define CAN_FDCBT_FPSEG1_MASK (0xE0U)
#define CAN_FDCBT_FPSEG1_SHIFT (5U)
/*! FPSEG1 - Fast Phase Segment 1
*/
#define CAN_FDCBT_FPSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPSEG1_SHIFT)) & CAN_FDCBT_FPSEG1_MASK)
#define CAN_FDCBT_FPROPSEG_MASK (0x7C00U)
#define CAN_FDCBT_FPROPSEG_SHIFT (10U)
/*! FPROPSEG - Fast Propagation Segment
*/
#define CAN_FDCBT_FPROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPROPSEG_SHIFT)) & CAN_FDCBT_FPROPSEG_MASK)
#define CAN_FDCBT_FRJW_MASK (0x70000U)
#define CAN_FDCBT_FRJW_SHIFT (16U)
/*! FRJW - Fast Resync Jump Width
*/
#define CAN_FDCBT_FRJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FRJW_SHIFT)) & CAN_FDCBT_FRJW_MASK)
#define CAN_FDCBT_FPRESDIV_MASK (0x3FF00000U)
#define CAN_FDCBT_FPRESDIV_SHIFT (20U)
/*! FPRESDIV - Fast Prescaler Division Factor
*/
#define CAN_FDCBT_FPRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCBT_FPRESDIV_SHIFT)) & CAN_FDCBT_FPRESDIV_MASK)
/*! @} */
/*! @name FDCRC - CAN FD CRC register */
/*! @{ */
#define CAN_FDCRC_FD_TXCRC_MASK (0x1FFFFFU)
#define CAN_FDCRC_FD_TXCRC_SHIFT (0U)
/*! FD_TXCRC - Extended Transmitted CRC value
*/
#define CAN_FDCRC_FD_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_TXCRC_SHIFT)) & CAN_FDCRC_FD_TXCRC_MASK)
#define CAN_FDCRC_FD_MBCRC_MASK (0x7F000000U)
#define CAN_FDCRC_FD_MBCRC_SHIFT (24U)
/*! FD_MBCRC - CRC Mailbox Number for FD_TXCRC
*/
#define CAN_FDCRC_FD_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_FDCRC_FD_MBCRC_SHIFT)) & CAN_FDCRC_FD_MBCRC_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CAN_Register_Masks */
/* CAN - Peripheral instance base addresses */
/** Peripheral CAN1 base address */
#define CAN1_BASE (0x400C4000u)
/** Peripheral CAN1 base pointer */
#define CAN1 ((CAN_Type *)CAN1_BASE)
/** Peripheral CAN2 base address */
#define CAN2_BASE (0x400C8000u)
/** Peripheral CAN2 base pointer */
#define CAN2 ((CAN_Type *)CAN2_BASE)
/** Peripheral CAN3 base address */
#define CAN3_BASE (0x40C3C000u)
/** Peripheral CAN3 base pointer */
#define CAN3 ((CAN_Type *)CAN3_BASE)
/** Array initializer of CAN peripheral base addresses */
#define CAN_BASE_ADDRS { 0u, CAN1_BASE, CAN2_BASE, CAN3_BASE }
/** Array initializer of CAN peripheral base pointers */
#define CAN_BASE_PTRS { (CAN_Type *)0u, CAN1, CAN2, CAN3 }
/** Interrupt vectors for the CAN peripheral type */
#define CAN_Rx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define CAN_Tx_Warning_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define CAN_Wake_Up_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define CAN_Error_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define CAN_Bus_Off_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
#define CAN_ORed_Message_buffer_IRQS { NotAvail_IRQn, CAN1_IRQn, CAN2_IRQn, CAN3_IRQn }
/*!
* @}
*/ /* end of group CAN_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CAN_WRAPPER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_WRAPPER_Peripheral_Access_Layer CAN_WRAPPER Peripheral Access Layer
* @{
*/
/** CAN_WRAPPER - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[2528];
__IO uint32_t GFWR; /**< Glitch Filter Width Register, offset: 0x9E0 */
} CAN_WRAPPER_Type;
/* ----------------------------------------------------------------------------
-- CAN_WRAPPER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CAN_WRAPPER_Register_Masks CAN_WRAPPER Register Masks
* @{
*/
/*! @name GFWR - Glitch Filter Width Register */
/*! @{ */
#define CAN_WRAPPER_GFWR_GFWR_MASK (0xFFU)
#define CAN_WRAPPER_GFWR_GFWR_SHIFT (0U)
/*! GFWR - Glitch Filter Width
*/
#define CAN_WRAPPER_GFWR_GFWR(x) (((uint32_t)(((uint32_t)(x)) << CAN_WRAPPER_GFWR_GFWR_SHIFT)) & CAN_WRAPPER_GFWR_GFWR_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CAN_WRAPPER_Register_Masks */
/* CAN_WRAPPER - Peripheral instance base addresses */
/** Peripheral CAN1_WRAPPER base address */
#define CAN1_WRAPPER_BASE (0x400C4000u)
/** Peripheral CAN1_WRAPPER base pointer */
#define CAN1_WRAPPER ((CAN_WRAPPER_Type *)CAN1_WRAPPER_BASE)
/** Peripheral CAN2_WRAPPER base address */
#define CAN2_WRAPPER_BASE (0x400C8000u)
/** Peripheral CAN2_WRAPPER base pointer */
#define CAN2_WRAPPER ((CAN_WRAPPER_Type *)CAN2_WRAPPER_BASE)
/** Peripheral CAN3_WRAPPER base address */
#define CAN3_WRAPPER_BASE (0x40C3C000u)
/** Peripheral CAN3_WRAPPER base pointer */
#define CAN3_WRAPPER ((CAN_WRAPPER_Type *)CAN3_WRAPPER_BASE)
/** Array initializer of CAN_WRAPPER peripheral base addresses */
#define CAN_WRAPPER_BASE_ADDRS { 0u, CAN1_WRAPPER_BASE, CAN2_WRAPPER_BASE, CAN3_WRAPPER_BASE }
/** Array initializer of CAN_WRAPPER peripheral base pointers */
#define CAN_WRAPPER_BASE_PTRS { (CAN_WRAPPER_Type *)0u, CAN1_WRAPPER, CAN2_WRAPPER, CAN3_WRAPPER }
/*!
* @}
*/ /* end of group CAN_WRAPPER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_Peripheral_Access_Layer CCM Peripheral Access Layer
* @{
*/
/** CCM - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x80 */
__IO uint32_t CONTROL; /**< Clock root control, array offset: 0x0, array step: 0x80 */
__IO uint32_t CONTROL_SET; /**< Clock root control, array offset: 0x4, array step: 0x80 */
__IO uint32_t CONTROL_CLR; /**< Clock root control, array offset: 0x8, array step: 0x80 */
__IO uint32_t CONTROL_TOG; /**< Clock root control, array offset: 0xC, array step: 0x80 */
uint8_t RESERVED_0[16];
__I uint32_t STATUS0; /**< Clock root working status, array offset: 0x20, array step: 0x80 */
__I uint32_t STATUS1; /**< Clock root low power status, array offset: 0x24, array step: 0x80 */
uint8_t RESERVED_1[4];
__I uint32_t CONFIG; /**< Clock root configuration, array offset: 0x2C, array step: 0x80 */
__IO uint32_t AUTHEN; /**< Clock root access control, array offset: 0x30, array step: 0x80 */
__IO uint32_t AUTHEN_SET; /**< Clock root access control, array offset: 0x34, array step: 0x80 */
__IO uint32_t AUTHEN_CLR; /**< Clock root access control, array offset: 0x38, array step: 0x80 */
__IO uint32_t AUTHEN_TOG; /**< Clock root access control, array offset: 0x3C, array step: 0x80 */
__IO uint32_t SETPOINT[16]; /**< Setpoint setting, array offset: 0x40, array step: index*0x80, index2*0x4 */
} CLOCK_ROOT[79];
uint8_t RESERVED_0[6272];
struct { /* offset: 0x4000, array step: 0x80 */
__IO uint32_t CONTROL; /**< Clock group control, array offset: 0x4000, array step: 0x80 */
__IO uint32_t CONTROL_SET; /**< Clock group control, array offset: 0x4004, array step: 0x80 */
__IO uint32_t CONTROL_CLR; /**< Clock group control, array offset: 0x4008, array step: 0x80 */
__IO uint32_t CONTROL_TOG; /**< Clock group control, array offset: 0x400C, array step: 0x80 */
uint8_t RESERVED_0[16];
__IO uint32_t STATUS0; /**< Clock group working status, array offset: 0x4020, array step: 0x80 */
__I uint32_t STATUS1; /**< Clock group low power/extend status, array offset: 0x4024, array step: 0x80 */
uint8_t RESERVED_1[4];
__I uint32_t CONFIG; /**< Clock group configuration, array offset: 0x402C, array step: 0x80 */
__IO uint32_t AUTHEN; /**< Clock group access control, array offset: 0x4030, array step: 0x80 */
__IO uint32_t AUTHEN_SET; /**< Clock group access control, array offset: 0x4034, array step: 0x80 */
__IO uint32_t AUTHEN_CLR; /**< Clock group access control, array offset: 0x4038, array step: 0x80 */
__IO uint32_t AUTHEN_TOG; /**< Clock group access control, array offset: 0x403C, array step: 0x80 */
__IO uint32_t SETPOINT[16]; /**< Setpoint setting, array offset: 0x4040, array step: index*0x80, index2*0x4 */
} CLOCK_GROUP[2];
uint8_t RESERVED_1[1792];
struct { /* offset: 0x4800, array step: 0x20 */
__IO uint32_t GPR_SHARED; /**< General Purpose Register, array offset: 0x4800, array step: 0x20 */
__IO uint32_t SET; /**< General Purpose Register, array offset: 0x4804, array step: 0x20 */
__IO uint32_t CLR; /**< General Purpose Register, array offset: 0x4808, array step: 0x20 */
__IO uint32_t TOG; /**< General Purpose Register, array offset: 0x480C, array step: 0x20 */
__IO uint32_t AUTHEN; /**< GPR access control, array offset: 0x4810, array step: 0x20 */
__IO uint32_t AUTHEN_SET; /**< GPR access control, array offset: 0x4814, array step: 0x20 */
__IO uint32_t AUTHEN_CLR; /**< GPR access control, array offset: 0x4818, array step: 0x20 */
__IO uint32_t AUTHEN_TOG; /**< GPR access control, array offset: 0x481C, array step: 0x20 */
} GPR_SHARED[8];
uint8_t RESERVED_2[800];
__IO uint32_t GPR_PRIVATE1; /**< General Purpose Register, offset: 0x4C20 */
__IO uint32_t GPR_PRIVATE1_SET; /**< General Purpose Register, offset: 0x4C24 */
__IO uint32_t GPR_PRIVATE1_CLR; /**< General Purpose Register, offset: 0x4C28 */
__IO uint32_t GPR_PRIVATE1_TOG; /**< General Purpose Register, offset: 0x4C2C */
__IO uint32_t GPR_PRIVATE1_AUTHEN; /**< GPR access control, offset: 0x4C30 */
__IO uint32_t GPR_PRIVATE1_AUTHEN_SET; /**< GPR access control, offset: 0x4C34 */
__IO uint32_t GPR_PRIVATE1_AUTHEN_CLR; /**< GPR access control, offset: 0x4C38 */
__IO uint32_t GPR_PRIVATE1_AUTHEN_TOG; /**< GPR access control, offset: 0x4C3C */
__IO uint32_t GPR_PRIVATE2; /**< General Purpose Register, offset: 0x4C40 */
__IO uint32_t GPR_PRIVATE2_SET; /**< General Purpose Register, offset: 0x4C44 */
__IO uint32_t GPR_PRIVATE2_CLR; /**< General Purpose Register, offset: 0x4C48 */
__IO uint32_t GPR_PRIVATE2_TOG; /**< General Purpose Register, offset: 0x4C4C */
__IO uint32_t GPR_PRIVATE2_AUTHEN; /**< GPR access control, offset: 0x4C50 */
__IO uint32_t GPR_PRIVATE2_AUTHEN_SET; /**< GPR access control, offset: 0x4C54 */
__IO uint32_t GPR_PRIVATE2_AUTHEN_CLR; /**< GPR access control, offset: 0x4C58 */
__IO uint32_t GPR_PRIVATE2_AUTHEN_TOG; /**< GPR access control, offset: 0x4C5C */
__IO uint32_t GPR_PRIVATE3; /**< General Purpose Register, offset: 0x4C60 */
__IO uint32_t GPR_PRIVATE3_SET; /**< General Purpose Register, offset: 0x4C64 */
__IO uint32_t GPR_PRIVATE3_CLR; /**< General Purpose Register, offset: 0x4C68 */
__IO uint32_t GPR_PRIVATE3_TOG; /**< General Purpose Register, offset: 0x4C6C */
__IO uint32_t GPR_PRIVATE3_AUTHEN; /**< GPR access control, offset: 0x4C70 */
__IO uint32_t GPR_PRIVATE3_AUTHEN_SET; /**< GPR access control, offset: 0x4C74 */
__IO uint32_t GPR_PRIVATE3_AUTHEN_CLR; /**< GPR access control, offset: 0x4C78 */
__IO uint32_t GPR_PRIVATE3_AUTHEN_TOG; /**< GPR access control, offset: 0x4C7C */
__IO uint32_t GPR_PRIVATE4; /**< General Purpose Register, offset: 0x4C80 */
__IO uint32_t GPR_PRIVATE4_SET; /**< General Purpose Register, offset: 0x4C84 */
__IO uint32_t GPR_PRIVATE4_CLR; /**< General Purpose Register, offset: 0x4C88 */
__IO uint32_t GPR_PRIVATE4_TOG; /**< General Purpose Register, offset: 0x4C8C */
__IO uint32_t GPR_PRIVATE4_AUTHEN; /**< GPR access control, offset: 0x4C90 */
__IO uint32_t GPR_PRIVATE4_AUTHEN_SET; /**< GPR access control, offset: 0x4C94 */
__IO uint32_t GPR_PRIVATE4_AUTHEN_CLR; /**< GPR access control, offset: 0x4C98 */
__IO uint32_t GPR_PRIVATE4_AUTHEN_TOG; /**< GPR access control, offset: 0x4C9C */
__IO uint32_t GPR_PRIVATE5; /**< General Purpose Register, offset: 0x4CA0 */
__IO uint32_t GPR_PRIVATE5_SET; /**< General Purpose Register, offset: 0x4CA4 */
__IO uint32_t GPR_PRIVATE5_CLR; /**< General Purpose Register, offset: 0x4CA8 */
__IO uint32_t GPR_PRIVATE5_TOG; /**< General Purpose Register, offset: 0x4CAC */
__IO uint32_t GPR_PRIVATE5_AUTHEN; /**< GPR access control, offset: 0x4CB0 */
__IO uint32_t GPR_PRIVATE5_AUTHEN_SET; /**< GPR access control, offset: 0x4CB4 */
__IO uint32_t GPR_PRIVATE5_AUTHEN_CLR; /**< GPR access control, offset: 0x4CB8 */
__IO uint32_t GPR_PRIVATE5_AUTHEN_TOG; /**< GPR access control, offset: 0x4CBC */
__IO uint32_t GPR_PRIVATE6; /**< General Purpose Register, offset: 0x4CC0 */
__IO uint32_t GPR_PRIVATE6_SET; /**< General Purpose Register, offset: 0x4CC4 */
__IO uint32_t GPR_PRIVATE6_CLR; /**< General Purpose Register, offset: 0x4CC8 */
__IO uint32_t GPR_PRIVATE6_TOG; /**< General Purpose Register, offset: 0x4CCC */
__IO uint32_t GPR_PRIVATE6_AUTHEN; /**< GPR access control, offset: 0x4CD0 */
__IO uint32_t GPR_PRIVATE6_AUTHEN_SET; /**< GPR access control, offset: 0x4CD4 */
__IO uint32_t GPR_PRIVATE6_AUTHEN_CLR; /**< GPR access control, offset: 0x4CD8 */
__IO uint32_t GPR_PRIVATE6_AUTHEN_TOG; /**< GPR access control, offset: 0x4CDC */
__IO uint32_t GPR_PRIVATE7; /**< General Purpose Register, offset: 0x4CE0 */
__IO uint32_t GPR_PRIVATE7_SET; /**< General Purpose Register, offset: 0x4CE4 */
__IO uint32_t GPR_PRIVATE7_CLR; /**< General Purpose Register, offset: 0x4CE8 */
__IO uint32_t GPR_PRIVATE7_TOG; /**< General Purpose Register, offset: 0x4CEC */
__IO uint32_t GPR_PRIVATE7_AUTHEN; /**< GPR access control, offset: 0x4CF0 */
__IO uint32_t GPR_PRIVATE7_AUTHEN_SET; /**< GPR access control, offset: 0x4CF4 */
__IO uint32_t GPR_PRIVATE7_AUTHEN_CLR; /**< GPR access control, offset: 0x4CF8 */
__IO uint32_t GPR_PRIVATE7_AUTHEN_TOG; /**< GPR access control, offset: 0x4CFC */
uint8_t RESERVED_3[768];
struct { /* offset: 0x5000, array step: 0x20 */
__IO uint32_t DIRECT; /**< Clock source direct control, array offset: 0x5000, array step: 0x20 */
__IO uint32_t DOMAINr; /**< Clock source domain control, array offset: 0x5004, array step: 0x20 */
__IO uint32_t SETPOINT; /**< Clock source Setpoint setting, array offset: 0x5008, array step: 0x20 */
uint8_t RESERVED_0[4];
__I uint32_t STATUS0; /**< Clock source working status, array offset: 0x5010, array step: 0x20 */
__I uint32_t STATUS1; /**< Clock source low power status, array offset: 0x5014, array step: 0x20 */
__I uint32_t CONFIG; /**< Clock source configuration, array offset: 0x5018, array step: 0x20 */
__IO uint32_t AUTHEN; /**< Clock source access control, array offset: 0x501C, array step: 0x20 */
} OSCPLL[29];
uint8_t RESERVED_4[3168];
struct { /* offset: 0x6000, array step: 0x20 */
__IO uint32_t DIRECT; /**< LPCG direct control, array offset: 0x6000, array step: 0x20 */
__IO uint32_t DOMAINr; /**< LPCG domain control, array offset: 0x6004, array step: 0x20 */
__IO uint32_t SETPOINT; /**< LPCG Setpoint setting, array offset: 0x6008, array step: 0x20 */
uint8_t RESERVED_0[4];
__I uint32_t STATUS0; /**< LPCG working status, array offset: 0x6010, array step: 0x20 */
__I uint32_t STATUS1; /**< LPCG low power status, array offset: 0x6014, array step: 0x20 */
__I uint32_t CONFIG; /**< LPCG configuration, array offset: 0x6018, array step: 0x20 */
__IO uint32_t AUTHEN; /**< LPCG access control, array offset: 0x601C, array step: 0x20 */
} LPCG[138];
} CCM_Type;
/* ----------------------------------------------------------------------------
-- CCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_Register_Masks CCM Register Masks
* @{
*/
/*! @name CLOCK_ROOT_CONTROL - Clock root control */
/*! @{ */
#define CCM_CLOCK_ROOT_CONTROL_DIV_MASK (0xFFU)
#define CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT (0U)
/*! DIV - Clock divider
*/
#define CCM_CLOCK_ROOT_CONTROL_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_DIV_MASK)
#define CCM_CLOCK_ROOT_CONTROL_MUX_MASK (0x700U)
#define CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT (8U)
/*! MUX - Clock multiplexer
*/
#define CCM_CLOCK_ROOT_CONTROL_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_MUX_MASK)
#define CCM_CLOCK_ROOT_CONTROL_OFF_MASK (0x1000000U)
#define CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT (24U)
/*! OFF - OFF
* 0b0..Turn on clock
* 0b1..Turn off clock
*/
#define CCM_CLOCK_ROOT_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_OFF_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_CONTROL */
#define CCM_CLOCK_ROOT_CONTROL_COUNT (79U)
/*! @name CLOCK_ROOT_CONTROL_SET - Clock root control */
/*! @{ */
#define CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK (0xFFU)
#define CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT (0U)
/*! DIV - Clock divider
*/
#define CCM_CLOCK_ROOT_CONTROL_SET_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_DIV_MASK)
#define CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK (0x700U)
#define CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT (8U)
/*! MUX - Clock multiplexer
*/
#define CCM_CLOCK_ROOT_CONTROL_SET_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_MUX_MASK)
#define CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK (0x1000000U)
#define CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT (24U)
/*! OFF - OFF
*/
#define CCM_CLOCK_ROOT_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_SET_OFF_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_CONTROL_SET */
#define CCM_CLOCK_ROOT_CONTROL_SET_COUNT (79U)
/*! @name CLOCK_ROOT_CONTROL_CLR - Clock root control */
/*! @{ */
#define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK (0xFFU)
#define CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT (0U)
/*! DIV - Clock divider
*/
#define CCM_CLOCK_ROOT_CONTROL_CLR_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_DIV_MASK)
#define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK (0x700U)
#define CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT (8U)
/*! MUX - Clock multiplexer
*/
#define CCM_CLOCK_ROOT_CONTROL_CLR_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_MUX_MASK)
#define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK (0x1000000U)
#define CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT (24U)
/*! OFF - OFF
*/
#define CCM_CLOCK_ROOT_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_CLR_OFF_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_CONTROL_CLR */
#define CCM_CLOCK_ROOT_CONTROL_CLR_COUNT (79U)
/*! @name CLOCK_ROOT_CONTROL_TOG - Clock root control */
/*! @{ */
#define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK (0xFFU)
#define CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT (0U)
/*! DIV - Clock divider
*/
#define CCM_CLOCK_ROOT_CONTROL_TOG_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_DIV_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_DIV_MASK)
#define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK (0x700U)
#define CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT (8U)
/*! MUX - Clock multiplexer
*/
#define CCM_CLOCK_ROOT_CONTROL_TOG_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_MUX_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_MUX_MASK)
#define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK (0x1000000U)
#define CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT (24U)
/*! OFF - OFF
*/
#define CCM_CLOCK_ROOT_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_ROOT_CONTROL_TOG_OFF_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_CONTROL_TOG */
#define CCM_CLOCK_ROOT_CONTROL_TOG_COUNT (79U)
/*! @name CLOCK_ROOT_STATUS0 - Clock root working status */
/*! @{ */
#define CCM_CLOCK_ROOT_STATUS0_DIV_MASK (0xFFU)
#define CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT (0U)
/*! DIV - Current clock root DIV setting
*/
#define CCM_CLOCK_ROOT_STATUS0_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_DIV_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_DIV_MASK)
#define CCM_CLOCK_ROOT_STATUS0_MUX_MASK (0x700U)
#define CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT (8U)
/*! MUX - Current clock root MUX setting
*/
#define CCM_CLOCK_ROOT_STATUS0_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_MUX_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_MUX_MASK)
#define CCM_CLOCK_ROOT_STATUS0_OFF_MASK (0x1000000U)
#define CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT (24U)
/*! OFF - Current clock root OFF setting
* 0b0..Clock is running
* 0b1..Clock is disabled/off
*/
#define CCM_CLOCK_ROOT_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_OFF_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_OFF_MASK)
#define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK (0x8000000U)
#define CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT (27U)
/*! POWERDOWN - Current clock root POWERDOWN setting
* 0b1..Clock root is Powered Down
* 0b0..Clock root is running
*/
#define CCM_CLOCK_ROOT_STATUS0_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_POWERDOWN_MASK)
#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK (0x10000000U)
#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT (28U)
/*! SLICE_BUSY - Internal updating in generation logic
* 0b1..Clock generation logic is applying the new setting
* 0b0..Clock generation logic is not busy
*/
#define CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_SLICE_BUSY_MASK)
#define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
#define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT (29U)
/*! UPDATE_FORWARD - Internal status synchronization to clock generation logic
* 0b1..Synchronization in process
* 0b0..Synchronization not in process
*/
#define CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_FORWARD_MASK)
#define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK (0x40000000U)
#define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT (30U)
/*! UPDATE_REVERSE - Internal status synchronization from clock generation logic
* 0b1..Synchronization in process
* 0b0..Synchronization not in process
*/
#define CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_UPDATE_REVERSE_MASK)
#define CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK (0x80000000U)
#define CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT (31U)
/*! CHANGING - Internal updating in clock root
* 0b1..Clock generation logic is updating currently
* 0b0..Clock Status is not updating currently
*/
#define CCM_CLOCK_ROOT_STATUS0_CHANGING(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_ROOT_STATUS0_CHANGING_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_STATUS0 */
#define CCM_CLOCK_ROOT_STATUS0_COUNT (79U)
/*! @name CLOCK_ROOT_STATUS1 - Clock root low power status */
/*! @{ */
#define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
#define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT (16U)
/*! TARGET_SETPOINT - Target Setpoint
*/
#define CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_TARGET_SETPOINT_MASK)
#define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
#define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
/*! CURRENT_SETPOINT - Current Setpoint
*/
#define CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_CURRENT_SETPOINT_MASK)
#define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK (0x1000000U)
#define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT (24U)
/*! DOWN_REQUEST - Clock frequency decrease request
* 0b1..Frequency decrease requested
* 0b0..Frequency decrease not requested
*/
#define CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_REQUEST_MASK)
#define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK (0x2000000U)
#define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT (25U)
/*! DOWN_DONE - Clock frequency decrease finish
* 0b1..Frequency decrease completed
* 0b0..Frequency decrease not completed
*/
#define CCM_CLOCK_ROOT_STATUS1_DOWN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_DOWN_DONE_MASK)
#define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK (0x4000000U)
#define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT (26U)
/*! UP_REQUEST - Clock frequency increase request
* 0b1..Frequency increase requested
* 0b0..Frequency increase not requested
*/
#define CCM_CLOCK_ROOT_STATUS1_UP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_REQUEST_MASK)
#define CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK (0x8000000U)
#define CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT (27U)
/*! UP_DONE - Clock frequency increase finish
* 0b1..Frequency increase completed
* 0b0..Frequency increase not completed
*/
#define CCM_CLOCK_ROOT_STATUS1_UP_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_ROOT_STATUS1_UP_DONE_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_STATUS1 */
#define CCM_CLOCK_ROOT_STATUS1_COUNT (79U)
/*! @name CLOCK_ROOT_CONFIG - Clock root configuration */
/*! @{ */
#define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
#define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
/*! SETPOINT_PRESENT - Setpoint present
* 0b1..Setpoint is implemented.
* 0b0..Setpoint is not implemented.
*/
#define CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_ROOT_CONFIG_SETPOINT_PRESENT_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_CONFIG */
#define CCM_CLOCK_ROOT_CONFIG_COUNT (79U)
/*! @name CLOCK_ROOT_AUTHEN - Clock root access control */
/*! @{ */
#define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode
* 0b0..Clock cannot be changed in user mode
*/
#define CCM_CLOCK_ROOT_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_USER_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode
* 0b1..Can be changed in Non-secure mode
*/
#define CCM_CLOCK_ROOT_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TZ_NS_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked
* 0b1..Trustzone setting is locked
*/
#define CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_TZ_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
* 0b0000..This domain is NOT allowed to change clock
* 0b0001..This domain is allowed to change clock
*/
#define CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_WHITE_LIST_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked
* 0b1..Whitelist is locked
*/
#define CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_LIST_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
* 0b1..Clock works in Domain Mode
* 0b0..Clock does NOT work in Domain Mode
*/
#define CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
#define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT (17U)
/*! SETPOINT_MODE - Low power and access control by Setpoint
* 0b1..Clock works in Setpoint Mode
* 0b0..Clock does NOT work in Setpoint Mode
*/
#define CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SETPOINT_MODE_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked
* 0b1..MODE is locked
*/
#define CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_AUTHEN */
#define CCM_CLOCK_ROOT_AUTHEN_COUNT (79U)
/*! @name CLOCK_ROOT_AUTHEN_SET - Clock root access control */
/*! @{ */
#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_USER_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_TZ_NS_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U)
#define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U)
/*! SETPOINT_MODE - Low power and access control by Setpoint
*/
#define CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_SETPOINT_MODE_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_AUTHEN_SET */
#define CCM_CLOCK_ROOT_AUTHEN_SET_COUNT (79U)
/*! @name CLOCK_ROOT_AUTHEN_CLR - Clock root access control */
/*! @{ */
#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U)
/*! SETPOINT_MODE - Low power and access control by Setpoint
*/
#define CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_SETPOINT_MODE_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_AUTHEN_CLR */
#define CCM_CLOCK_ROOT_AUTHEN_CLR_COUNT (79U)
/*! @name CLOCK_ROOT_AUTHEN_TOG - Clock root access control */
/*! @{ */
#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U)
/*! SETPOINT_MODE - Low power and access control by Setpoint
*/
#define CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_SETPOINT_MODE_MASK)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_ROOT_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_AUTHEN_TOG */
#define CCM_CLOCK_ROOT_AUTHEN_TOG_COUNT (79U)
/*! @name CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT - Setpoint setting */
/*! @{ */
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK (0xFFU)
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT (0U)
/*! DIV - Clock divider
*/
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_DIV_MASK)
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK (0x700U)
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT (8U)
/*! MUX - Clock multiplexer
*/
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_MUX_MASK)
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK (0x1000000U)
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT (24U)
/*! OFF - OFF
* 0b1..OFF
* 0b0..ON
*/
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_OFF_MASK)
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U)
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT (28U)
/*! GRADE - Grade
*/
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_GRADE_MASK)
/*! @} */
/* The count of CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT */
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT (79U)
/* The count of CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT */
#define CCM_CLOCK_ROOT_CLOCK_ROOT_SETPOINT_SETPOINT_COUNT2 (16U)
/*! @name CLOCK_GROUP_CONTROL - Clock group control */
/*! @{ */
#define CCM_CLOCK_GROUP_CONTROL_DIV0_MASK (0xFU)
#define CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT (0U)
/*! DIV0 - Clock divider0
*/
#define CCM_CLOCK_GROUP_CONTROL_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_DIV0_MASK)
#define CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK (0xFF0000U)
#define CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT (16U)
/*! RSTDIV - Clock group global restart count
*/
#define CCM_CLOCK_GROUP_CONTROL_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_RSTDIV_MASK)
#define CCM_CLOCK_GROUP_CONTROL_OFF_MASK (0x1000000U)
#define CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT (24U)
/*! OFF - OFF
* 0b0..Clock is running
* 0b1..Turn off clock
*/
#define CCM_CLOCK_GROUP_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_OFF_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_CONTROL */
#define CCM_CLOCK_GROUP_CONTROL_COUNT (2U)
/*! @name CLOCK_GROUP_CONTROL_SET - Clock group control */
/*! @{ */
#define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK (0xFU)
#define CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT (0U)
/*! DIV0 - Clock divider0
*/
#define CCM_CLOCK_GROUP_CONTROL_SET_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_DIV0_MASK)
#define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK (0xFF0000U)
#define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT (16U)
/*! RSTDIV - Clock group global restart count
*/
#define CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_RSTDIV_MASK)
#define CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK (0x1000000U)
#define CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT (24U)
/*! OFF - OFF
*/
#define CCM_CLOCK_GROUP_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_SET_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_SET_OFF_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_CONTROL_SET */
#define CCM_CLOCK_GROUP_CONTROL_SET_COUNT (2U)
/*! @name CLOCK_GROUP_CONTROL_CLR - Clock group control */
/*! @{ */
#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK (0xFU)
#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT (0U)
/*! DIV0 - Clock divider0
*/
#define CCM_CLOCK_GROUP_CONTROL_CLR_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_DIV0_MASK)
#define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK (0xFF0000U)
#define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT (16U)
/*! RSTDIV - Clock group global restart count
*/
#define CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_RSTDIV_MASK)
#define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK (0x1000000U)
#define CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT (24U)
/*! OFF - OFF
*/
#define CCM_CLOCK_GROUP_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_CLR_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_CLR_OFF_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_CONTROL_CLR */
#define CCM_CLOCK_GROUP_CONTROL_CLR_COUNT (2U)
/*! @name CLOCK_GROUP_CONTROL_TOG - Clock group control */
/*! @{ */
#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK (0xFU)
#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT (0U)
/*! DIV0 - Clock divider0
*/
#define CCM_CLOCK_GROUP_CONTROL_TOG_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_DIV0_MASK)
#define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK (0xFF0000U)
#define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT (16U)
/*! RSTDIV - Clock group global restart count
*/
#define CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_RSTDIV_MASK)
#define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK (0x1000000U)
#define CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT (24U)
/*! OFF - OFF
*/
#define CCM_CLOCK_GROUP_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONTROL_TOG_OFF_SHIFT)) & CCM_CLOCK_GROUP_CONTROL_TOG_OFF_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_CONTROL_TOG */
#define CCM_CLOCK_GROUP_CONTROL_TOG_COUNT (2U)
/*! @name CLOCK_GROUP_STATUS0 - Clock group working status */
/*! @{ */
#define CCM_CLOCK_GROUP_STATUS0_DIV0_MASK (0xFU)
#define CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT (0U)
/*! DIV0 - Clock divider
*/
#define CCM_CLOCK_GROUP_STATUS0_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_DIV0_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_DIV0_MASK)
#define CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK (0xFF0000U)
#define CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT (16U)
/*! RSTDIV - Clock divider
*/
#define CCM_CLOCK_GROUP_STATUS0_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_RSTDIV_MASK)
#define CCM_CLOCK_GROUP_STATUS0_OFF_MASK (0x1000000U)
#define CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT (24U)
/*! OFF - OFF
* 0b0..Clock is running.
* 0b1..Turn off clock.
*/
#define CCM_CLOCK_GROUP_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_OFF_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_OFF_MASK)
#define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK (0x8000000U)
#define CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT (27U)
/*! POWERDOWN - Current clock root POWERDOWN setting
* 0b1..Clock root is Powered Down
* 0b0..Clock root is running
*/
#define CCM_CLOCK_GROUP_STATUS0_POWERDOWN(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_POWERDOWN_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_POWERDOWN_MASK)
#define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK (0x10000000U)
#define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT (28U)
/*! SLICE_BUSY - Internal updating in generation logic
* 0b1..Clock generation logic is applying the new setting
* 0b0..Clock generation logic is not busy
*/
#define CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_SLICE_BUSY_MASK)
#define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK (0x20000000U)
#define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT (29U)
/*! UPDATE_FORWARD - Internal status synchronization to clock generation logic
* 0b1..Synchronization in process
* 0b0..Synchronization not in process
*/
#define CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_FORWARD_MASK)
#define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK (0x40000000U)
#define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT (30U)
/*! UPDATE_REVERSE - Internal status synchronization from clock generation logic
* 0b1..Synchronization in process
* 0b0..Synchronization not in process
*/
#define CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_UPDATE_REVERSE_MASK)
#define CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK (0x80000000U)
#define CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT (31U)
/*! CHANGING - Internal updating in clock group
* 0b1..Clock root logic is updating currently
* 0b0..Clock root is not updating currently
*/
#define CCM_CLOCK_GROUP_STATUS0_CHANGING(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS0_CHANGING_SHIFT)) & CCM_CLOCK_GROUP_STATUS0_CHANGING_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_STATUS0 */
#define CCM_CLOCK_GROUP_STATUS0_COUNT (2U)
/*! @name CLOCK_GROUP_STATUS1 - Clock group low power/extend status */
/*! @{ */
#define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
#define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT (16U)
/*! TARGET_SETPOINT - Next Setpoint to change to
*/
#define CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_TARGET_SETPOINT_MASK)
#define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
#define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
/*! CURRENT_SETPOINT - Current Setpoint
*/
#define CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_CURRENT_SETPOINT_MASK)
#define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK (0x1000000U)
#define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT (24U)
/*! DOWN_REQUEST - Clock frequency decrease request
* 0b1..Handshake signal with GPC status indicating frequency decrease is requested
* 0b0..No handshake signal is not requested
*/
#define CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_REQUEST_MASK)
#define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK (0x2000000U)
#define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT (25U)
/*! DOWN_DONE - Clock frequency decrease complete
* 0b1..Handshake signal with GPC status indicating frequency decrease is complete
* 0b0..Handshake signal with GPC status indicating frequency decrease is not complete
*/
#define CCM_CLOCK_GROUP_STATUS1_DOWN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_DOWN_DONE_MASK)
#define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK (0x4000000U)
#define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT (26U)
/*! UP_REQUEST - Clock frequency increase request
* 0b1..Handshake signal with GPC status indicating frequency increase is requested
* 0b0..No handshake signal is not requested
*/
#define CCM_CLOCK_GROUP_STATUS1_UP_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_REQUEST_MASK)
#define CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK (0x8000000U)
#define CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT (27U)
/*! UP_DONE - Clock frequency increase complete
* 0b1..Handshake signal with GPC status indicating frequency increase is complete
* 0b0..Handshake signal with GPC status indicating frequency increase is not complete
*/
#define CCM_CLOCK_GROUP_STATUS1_UP_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_STATUS1_UP_DONE_SHIFT)) & CCM_CLOCK_GROUP_STATUS1_UP_DONE_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_STATUS1 */
#define CCM_CLOCK_GROUP_STATUS1_COUNT (2U)
/*! @name CLOCK_GROUP_CONFIG - Clock group configuration */
/*! @{ */
#define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
#define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
/*! SETPOINT_PRESENT - Setpoint present
* 0b1..Setpoint is implemented.
* 0b0..Setpoint is not implemented.
*/
#define CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_CLOCK_GROUP_CONFIG_SETPOINT_PRESENT_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_CONFIG */
#define CCM_CLOCK_GROUP_CONFIG_COUNT (2U)
/*! @name CLOCK_GROUP_AUTHEN - Clock group access control */
/*! @{ */
#define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_CLOCK_GROUP_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_USER_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_CLOCK_GROUP_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TZ_NS_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_TZ_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_WHITE_LIST_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_LIST_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
* 0b1..Clock works in Domain Mode.
* 0b0..Clock does not work in Domain Mode.
*/
#define CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
#define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT (17U)
/*! SETPOINT_MODE - Low power and access control by Setpoint
*/
#define CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SETPOINT_MODE_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_AUTHEN */
#define CCM_CLOCK_GROUP_AUTHEN_COUNT (2U)
/*! @name CLOCK_GROUP_AUTHEN_SET - Clock group access control */
/*! @{ */
#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_USER_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_TZ_NS_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK (0x20000U)
#define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT (17U)
/*! SETPOINT_MODE - Low power and access control by Setpoint
*/
#define CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_SETPOINT_MODE_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_AUTHEN_SET */
#define CCM_CLOCK_GROUP_AUTHEN_SET_COUNT (2U)
/*! @name CLOCK_GROUP_AUTHEN_CLR - Clock group access control */
/*! @{ */
#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK (0x20000U)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT (17U)
/*! SETPOINT_MODE - Low power and access control by Setpoint
*/
#define CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_SETPOINT_MODE_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_AUTHEN_CLR */
#define CCM_CLOCK_GROUP_AUTHEN_CLR_COUNT (2U)
/*! @name CLOCK_GROUP_AUTHEN_TOG - Clock group access control */
/*! @{ */
#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK (0x20000U)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT (17U)
/*! SETPOINT_MODE - Low power and access control by Setpoint
*/
#define CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_SETPOINT_MODE_MASK)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_CLOCK_GROUP_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_AUTHEN_TOG */
#define CCM_CLOCK_GROUP_AUTHEN_TOG_COUNT (2U)
/*! @name CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT - Setpoint setting */
/*! @{ */
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK (0xFU)
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT (0U)
/*! DIV0 - Clock divider
* 0b0000..Direct output.
* 0b0001..Divide by 2.
* 0b0010..Divide by 3.
* 0b0011..Divide by 4.
* 0b1111..Divide by 16.
*/
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_DIV0_MASK)
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK (0xFF0000U)
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT (16U)
/*! RSTDIV - Clock group global restart count
*/
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_RSTDIV_MASK)
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK (0x1000000U)
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT (24U)
/*! OFF - OFF
* 0b0..Clock is running.
* 0b1..Turn off clock.
*/
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_OFF_MASK)
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK (0xF0000000U)
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT (28U)
/*! GRADE - Grade
*/
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE(x) (((uint32_t)(((uint32_t)(x)) << CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_SHIFT)) & CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_GRADE_MASK)
/*! @} */
/* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT (2U)
/* The count of CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT */
#define CCM_CLOCK_GROUP_CLOCK_GROUP_SETPOINT_SETPOINT_COUNT2 (16U)
/*! @name GPR_SHARED - General Purpose Register */
/*! @{ */
#define CCM_GPR_SHARED_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_SHARED_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_SHARED_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_GPR_SHIFT)) & CCM_GPR_SHARED_GPR_MASK)
/*! @} */
/* The count of CCM_GPR_SHARED */
#define CCM_GPR_SHARED_COUNT (8U)
/*! @name GPR_SHARED_SET - General Purpose Register */
/*! @{ */
#define CCM_GPR_SHARED_SET_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_SHARED_SET_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_SHARED_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_SET_GPR_SHIFT)) & CCM_GPR_SHARED_SET_GPR_MASK)
/*! @} */
/* The count of CCM_GPR_SHARED_SET */
#define CCM_GPR_SHARED_SET_COUNT (8U)
/*! @name GPR_SHARED_CLR - General Purpose Register */
/*! @{ */
#define CCM_GPR_SHARED_CLR_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_SHARED_CLR_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_SHARED_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_CLR_GPR_SHIFT)) & CCM_GPR_SHARED_CLR_GPR_MASK)
/*! @} */
/* The count of CCM_GPR_SHARED_CLR */
#define CCM_GPR_SHARED_CLR_COUNT (8U)
/*! @name GPR_SHARED_TOG - General Purpose Register */
/*! @{ */
#define CCM_GPR_SHARED_TOG_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_SHARED_TOG_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_SHARED_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_TOG_GPR_SHIFT)) & CCM_GPR_SHARED_TOG_GPR_MASK)
/*! @} */
/* The count of CCM_GPR_SHARED_TOG */
#define CCM_GPR_SHARED_TOG_COUNT (8U)
/*! @name GPR_SHARED_AUTHEN - GPR access control */
/*! @{ */
#define CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_GPR_SHARED_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_USER_MASK)
#define CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_GPR_SHARED_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TZ_NS_MASK)
#define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_GPR_SHARED_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_TZ_MASK)
#define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
* 0b0000..This domain is NOT allowed to change clock.
* 0b0001..This domain is allowed to change clock.
*/
#define CCM_GPR_SHARED_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_WHITE_LIST_MASK)
#define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_GPR_SHARED_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_LIST_MASK)
#define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
* 0b1..Clock works in Domain Mode.
* 0b0..Clock does NOT work in Domain Mode.
*/
#define CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_GPR_SHARED_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_GPR_SHARED_AUTHEN */
#define CCM_GPR_SHARED_AUTHEN_COUNT (8U)
/*! @name GPR_SHARED_AUTHEN_SET - GPR access control */
/*! @{ */
#define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_SHARED_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_USER_MASK)
#define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_SHARED_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_TZ_NS_MASK)
#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_GPR_SHARED_AUTHEN_SET */
#define CCM_GPR_SHARED_AUTHEN_SET_COUNT (8U)
/*! @name GPR_SHARED_AUTHEN_CLR - GPR access control */
/*! @{ */
#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_GPR_SHARED_AUTHEN_CLR */
#define CCM_GPR_SHARED_AUTHEN_CLR_COUNT (8U)
/*! @name GPR_SHARED_AUTHEN_TOG - GPR access control */
/*! @{ */
#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_SHARED_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_GPR_SHARED_AUTHEN_TOG */
#define CCM_GPR_SHARED_AUTHEN_TOG_COUNT (8U)
/*! @name GPR_PRIVATE1 - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE1_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE1_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE1_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_GPR_SHIFT)) & CCM_GPR_PRIVATE1_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE1_SET - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE1_SET_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE1_SET_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE1_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE1_SET_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE1_CLR - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE1_CLR_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE1_CLR_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE1_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE1_CLR_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE1_TOG - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE1_TOG_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE1_TOG_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE1_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE1_TOG_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE1_AUTHEN - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_GPR_PRIVATE1_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_USER_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_GPR_PRIVATE1_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TZ_NS_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
* 0b0000..This domain is NOT allowed to change clock.
* 0b0001..This domain is allowed to change clock.
*/
#define CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
* 0b1..Clock works in Domain Mode.
* 0b0..Clock does NOT work in Domain Mode.
*/
#define CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE1_AUTHEN_SET - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_USER_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_TZ_NS_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE1_AUTHEN_CLR - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE1_AUTHEN_TOG - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE1_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE2 - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE2_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE2_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE2_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_GPR_SHIFT)) & CCM_GPR_PRIVATE2_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE2_SET - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE2_SET_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE2_SET_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE2_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE2_SET_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE2_CLR - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE2_CLR_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE2_CLR_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE2_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE2_CLR_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE2_TOG - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE2_TOG_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE2_TOG_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE2_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE2_TOG_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE2_AUTHEN - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_GPR_PRIVATE2_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_USER_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_GPR_PRIVATE2_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TZ_NS_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
* 0b0000..This domain is NOT allowed to change clock.
* 0b0001..This domain is allowed to change clock.
*/
#define CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
* 0b1..Clock works in Domain Mode.
* 0b0..Clock does NOT work in Domain Mode.
*/
#define CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE2_AUTHEN_SET - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_USER_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_TZ_NS_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE2_AUTHEN_CLR - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE2_AUTHEN_TOG - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE2_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE3 - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE3_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE3_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE3_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_GPR_SHIFT)) & CCM_GPR_PRIVATE3_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE3_SET - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE3_SET_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE3_SET_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE3_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE3_SET_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE3_CLR - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE3_CLR_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE3_CLR_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE3_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE3_CLR_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE3_TOG - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE3_TOG_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE3_TOG_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE3_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE3_TOG_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE3_AUTHEN - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_GPR_PRIVATE3_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_USER_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_GPR_PRIVATE3_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TZ_NS_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
* 0b0000..This domain is NOT allowed to change clock.
* 0b0001..This domain is allowed to change clock.
*/
#define CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
* 0b1..Clock works in Domain Mode.
* 0b0..Clock does NOT work in Domain Mode.
*/
#define CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE3_AUTHEN_SET - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_USER_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_TZ_NS_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE3_AUTHEN_CLR - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE3_AUTHEN_TOG - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE3_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE4 - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE4_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE4_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE4_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_GPR_SHIFT)) & CCM_GPR_PRIVATE4_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE4_SET - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE4_SET_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE4_SET_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE4_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE4_SET_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE4_CLR - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE4_CLR_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE4_CLR_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE4_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE4_CLR_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE4_TOG - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE4_TOG_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE4_TOG_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE4_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE4_TOG_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE4_AUTHEN - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_GPR_PRIVATE4_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_USER_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_GPR_PRIVATE4_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TZ_NS_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
* 0b0000..This domain is NOT allowed to change clock.
* 0b0001..This domain is allowed to change clock.
*/
#define CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
* 0b1..Clock works in Domain Mode.
* 0b0..Clock does NOT work in Domain Mode.
*/
#define CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE4_AUTHEN_SET - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_USER_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_TZ_NS_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE4_AUTHEN_CLR - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE4_AUTHEN_TOG - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE4_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE5 - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE5_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE5_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE5_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_GPR_SHIFT)) & CCM_GPR_PRIVATE5_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE5_SET - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE5_SET_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE5_SET_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE5_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE5_SET_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE5_CLR - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE5_CLR_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE5_CLR_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE5_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE5_CLR_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE5_TOG - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE5_TOG_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE5_TOG_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE5_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE5_TOG_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE5_AUTHEN - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_GPR_PRIVATE5_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_USER_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_GPR_PRIVATE5_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TZ_NS_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
* 0b0000..This domain is NOT allowed to change clock.
* 0b0001..This domain is allowed to change clock.
*/
#define CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
* 0b1..Clock works in Domain Mode.
* 0b0..Clock does NOT work in Domain Mode.
*/
#define CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE5_AUTHEN_SET - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_USER_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_TZ_NS_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE5_AUTHEN_CLR - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE5_AUTHEN_TOG - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE5_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE6 - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE6_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE6_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE6_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_GPR_SHIFT)) & CCM_GPR_PRIVATE6_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE6_SET - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE6_SET_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE6_SET_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE6_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE6_SET_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE6_CLR - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE6_CLR_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE6_CLR_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE6_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE6_CLR_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE6_TOG - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE6_TOG_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE6_TOG_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE6_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE6_TOG_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE6_AUTHEN - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_GPR_PRIVATE6_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_USER_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_GPR_PRIVATE6_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TZ_NS_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
* 0b0000..This domain is NOT allowed to change clock.
* 0b0001..This domain is allowed to change clock.
*/
#define CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
* 0b1..Clock works in Domain Mode.
* 0b0..Clock does NOT work in Domain Mode.
*/
#define CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE6_AUTHEN_SET - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_USER_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_TZ_NS_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE6_AUTHEN_CLR - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE6_AUTHEN_TOG - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE6_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE7 - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE7_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE7_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE7_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_GPR_SHIFT)) & CCM_GPR_PRIVATE7_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE7_SET - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE7_SET_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE7_SET_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE7_SET_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_SET_GPR_SHIFT)) & CCM_GPR_PRIVATE7_SET_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE7_CLR - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE7_CLR_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE7_CLR_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE7_CLR_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_CLR_GPR_SHIFT)) & CCM_GPR_PRIVATE7_CLR_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE7_TOG - General Purpose Register */
/*! @{ */
#define CCM_GPR_PRIVATE7_TOG_GPR_MASK (0xFFFFFFFFU)
#define CCM_GPR_PRIVATE7_TOG_GPR_SHIFT (0U)
/*! GPR - GP register
*/
#define CCM_GPR_PRIVATE7_TOG_GPR(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_TOG_GPR_SHIFT)) & CCM_GPR_PRIVATE7_TOG_GPR_MASK)
/*! @} */
/*! @name GPR_PRIVATE7_AUTHEN - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_GPR_PRIVATE7_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_USER_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_GPR_PRIVATE7_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TZ_NS_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
* 0b0000..This domain is NOT allowed to change clock.
* 0b0001..This domain is allowed to change clock.
*/
#define CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
* 0b1..Clock works in Domain Mode.
* 0b0..Clock does NOT work in Domain Mode.
*/
#define CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE7_AUTHEN_SET - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_USER_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_TZ_NS_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE7_AUTHEN_CLR - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/*! @name GPR_PRIVATE7_AUTHEN_TOG - GPR access control */
/*! @{ */
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
*/
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by Domain
*/
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_GPR_PRIVATE7_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/*! @name OSCPLL_DIRECT - Clock source direct control */
/*! @{ */
#define CCM_OSCPLL_DIRECT_ON_MASK (0x1U)
#define CCM_OSCPLL_DIRECT_ON_SHIFT (0U)
/*! ON - turn on clock source
* 0b0..OSCPLL is OFF
* 0b1..OSCPLL is ON
*/
#define CCM_OSCPLL_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DIRECT_ON_SHIFT)) & CCM_OSCPLL_DIRECT_ON_MASK)
/*! @} */
/* The count of CCM_OSCPLL_DIRECT */
#define CCM_OSCPLL_DIRECT_COUNT (29U)
/*! @name OSCPLL_DOMAIN - Clock source domain control */
/*! @{ */
#define CCM_OSCPLL_DOMAIN_LEVEL_MASK (0x7U)
#define CCM_OSCPLL_DOMAIN_LEVEL_SHIFT (0U)
/*! LEVEL - Current dependence level
* 0b000..This clock source is not needed in any mode, and can be turned off
* 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
* 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
* 0b011..This clock source is needed in RUN, WAIT and STOP mode
* 0b100..This clock source is always on in any mode (including SUSPEND)
* 0b101, 0b110, 0b111..Reserved
*/
#define CCM_OSCPLL_DOMAIN_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL_MASK)
#define CCM_OSCPLL_DOMAIN_LEVEL0_MASK (0x70000U)
#define CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT (16U)
/*! LEVEL0 - Dependence level
* 0b000..This clock source is not needed in any mode, and can be turned off
* 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
* 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
* 0b011..This clock source is needed in RUN, WAIT and STOP mode
* 0b100..This clock source is always on in any mode (including SUSPEND)
* 0b101, 0b110, 0b111..Reserved
*/
#define CCM_OSCPLL_DOMAIN_LEVEL0(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL0_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL0_MASK)
#define CCM_OSCPLL_DOMAIN_LEVEL1_MASK (0x700000U)
#define CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT (20U)
/*! LEVEL1 - Depend level
* 0b000..This clock source is not needed in any mode, and can be turned off
* 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
* 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
* 0b011..This clock source is needed in RUN, WAIT and STOP mode
* 0b100..This clock source is always on in any mode (including SUSPEND)
* 0b101, 0b110, 0b111..Reserved
*/
#define CCM_OSCPLL_DOMAIN_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL1_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL1_MASK)
#define CCM_OSCPLL_DOMAIN_LEVEL2_MASK (0x7000000U)
#define CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT (24U)
/*! LEVEL2 - Depend level
* 0b000..This clock source is not needed in any mode, and can be turned off
* 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
* 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
* 0b011..This clock source is needed in RUN, WAIT and STOP mode
* 0b100..This clock source is always on in any mode (including SUSPEND)
* 0b101, 0b110, 0b111..Reserved
*/
#define CCM_OSCPLL_DOMAIN_LEVEL2(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL2_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL2_MASK)
#define CCM_OSCPLL_DOMAIN_LEVEL3_MASK (0x70000000U)
#define CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT (28U)
/*! LEVEL3 - Depend level
* 0b000..This clock source is not needed in any mode, and can be turned off
* 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
* 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
* 0b011..This clock source is needed in RUN, WAIT and STOP mode
* 0b100..This clock source is always on in any mode (including SUSPEND)
* 0b101, 0b110, 0b111..Reserved
*/
#define CCM_OSCPLL_DOMAIN_LEVEL3(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_DOMAIN_LEVEL3_SHIFT)) & CCM_OSCPLL_DOMAIN_LEVEL3_MASK)
/*! @} */
/* The count of CCM_OSCPLL_DOMAIN */
#define CCM_OSCPLL_DOMAIN_COUNT (29U)
/*! @name OSCPLL_SETPOINT - Clock source Setpoint setting */
/*! @{ */
#define CCM_OSCPLL_SETPOINT_SETPOINT_MASK (0xFFFFU)
#define CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT (0U)
/*! SETPOINT - Setpoint
*/
#define CCM_OSCPLL_SETPOINT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_SETPOINT_SHIFT)) & CCM_OSCPLL_SETPOINT_SETPOINT_MASK)
#define CCM_OSCPLL_SETPOINT_STANDBY_MASK (0xFFFF0000U)
#define CCM_OSCPLL_SETPOINT_STANDBY_SHIFT (16U)
/*! STANDBY - Standby
*/
#define CCM_OSCPLL_SETPOINT_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_SETPOINT_STANDBY_SHIFT)) & CCM_OSCPLL_SETPOINT_STANDBY_MASK)
/*! @} */
/* The count of CCM_OSCPLL_SETPOINT */
#define CCM_OSCPLL_SETPOINT_COUNT (29U)
/*! @name OSCPLL_STATUS0 - Clock source working status */
/*! @{ */
#define CCM_OSCPLL_STATUS0_ON_MASK (0x1U)
#define CCM_OSCPLL_STATUS0_ON_SHIFT (0U)
/*! ON - Clock source current state
* 0b0..Clock source is OFF
* 0b1..Clock source is ON
*/
#define CCM_OSCPLL_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ON_SHIFT)) & CCM_OSCPLL_STATUS0_ON_MASK)
#define CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK (0x10U)
#define CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT (4U)
/*! STATUS_EARLY - Clock source active
* 0b1..Clock source is active
* 0b0..Clock source is not active
*/
#define CCM_OSCPLL_STATUS0_STATUS_EARLY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_EARLY_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_EARLY_MASK)
#define CCM_OSCPLL_STATUS0_STATUS_LATE_MASK (0x20U)
#define CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT (5U)
/*! STATUS_LATE - Clock source ready
* 0b1..Clock source is ready to use
* 0b0..Clock source is not ready to use
*/
#define CCM_OSCPLL_STATUS0_STATUS_LATE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_STATUS_LATE_SHIFT)) & CCM_OSCPLL_STATUS0_STATUS_LATE_MASK)
#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK (0xF00U)
#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT (8U)
/*! ACTIVE_DOMAIN - Domains that own this clock source
* 0b0000..Clock not owned by any domain
* 0b0001..Clock owned by Domain0
* 0b0010..Clock owned by Domain1
* 0b0011..Clock owned by Domain0 and Domain1
* 0b0100..Clock owned by Domain2
* 0b0101..Clock owned by Domain0 and Domain2
* 0b0110..Clock owned by Domain1 and Domain2
* 0b0111..Clock owned by Domain0, Domain1 and Domain 2
* 0b1000..Clock owned by Domain3
* 0b1001..Clock owned by Domain0 and Domain3
* 0b1010..Clock owned by Domain1 and Domain3
* 0b1011..Clock owned by Domain2 and Domain3
* 0b1100..Clock owned by Domain0, Domain 1, and Domain3
* 0b1101..Clock owned by Domain0, Domain 2, and Domain3
* 0b1110..Clock owned by Domain1, Domain 2, and Domain3
* 0b1111..Clock owned by all domains
*/
#define CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_OSCPLL_STATUS0_ACTIVE_DOMAIN_MASK)
#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK (0xF000U)
#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT (12U)
/*! DOMAIN_ENABLE - Enable status from each domain
* 0b0000..No domain request
* 0b0001..Request from Domain0
* 0b0010..Request from Domain1
* 0b0011..Request from Domain0 and Domain1
* 0b0100..Request from Domain2
* 0b0101..Request from Domain0 and Domain2
* 0b0110..Request from Domain1 and Domain2
* 0b0111..Request from Domain0, Domain1 and Domain 2
* 0b1000..Request from Domain3
* 0b1001..Request from Domain0 and Domain3
* 0b1010..Request from Domain1 and Domain3
* 0b1011..Request from Domain2 and Domain3
* 0b1100..Request from Domain0, Domain 1, and Domain3
* 0b1101..Request from Domain0, Domain 2, and Domain3
* 0b1110..Request from Domain1, Domain 2, and Domain3
* 0b1111..Request from all domains
*/
#define CCM_OSCPLL_STATUS0_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_OSCPLL_STATUS0_DOMAIN_ENABLE_MASK)
#define CCM_OSCPLL_STATUS0_IN_USE_MASK (0x10000000U)
#define CCM_OSCPLL_STATUS0_IN_USE_SHIFT (28U)
/*! IN_USE - In use
* 0b1..Clock source is being used by clock roots
* 0b0..Clock source is not being used by clock roots
*/
#define CCM_OSCPLL_STATUS0_IN_USE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS0_IN_USE_SHIFT)) & CCM_OSCPLL_STATUS0_IN_USE_MASK)
/*! @} */
/* The count of CCM_OSCPLL_STATUS0 */
#define CCM_OSCPLL_STATUS0_COUNT (29U)
/*! @name OSCPLL_STATUS1 - Clock source low power status */
/*! @{ */
#define CCM_OSCPLL_STATUS1_CPU0_MODE_MASK (0x3U)
#define CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT (0U)
/*! CPU0_MODE - Domain0 Low Power Mode
* 0b00..Run
* 0b01..Wait
* 0b10..Stop
* 0b11..Suspend
*/
#define CCM_OSCPLL_STATUS1_CPU0_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_MASK)
#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U)
#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U)
/*! CPU0_MODE_REQUEST - Domain0 request enter Low Power Mode
* 0b1..Request from domain to enter Low Power Mode
* 0b0..No request
*/
#define CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_REQUEST_MASK)
#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK (0x8U)
#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT (3U)
/*! CPU0_MODE_DONE - Domain0 Low Power Mode task done
* 0b1..Clock is gated-off
* 0b0..Clock is not gated
*/
#define CCM_OSCPLL_STATUS1_CPU0_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU0_MODE_DONE_MASK)
#define CCM_OSCPLL_STATUS1_CPU1_MODE_MASK (0x30U)
#define CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT (4U)
/*! CPU1_MODE - Domain1 Low Power Mode
* 0b00..Run
* 0b01..Wait
* 0b10..Stop
* 0b11..Suspend
*/
#define CCM_OSCPLL_STATUS1_CPU1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_MASK)
#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U)
#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U)
/*! CPU1_MODE_REQUEST - Domain1 request enter Low Power Mode
* 0b1..Request from domain to enter Low Power Mode
* 0b0..No request
*/
#define CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_REQUEST_MASK)
#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK (0x80U)
#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT (7U)
/*! CPU1_MODE_DONE - Domain1 Low Power Mode task done
* 0b1..Clock is gated-off
* 0b0..Clock is not gated
*/
#define CCM_OSCPLL_STATUS1_CPU1_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU1_MODE_DONE_MASK)
#define CCM_OSCPLL_STATUS1_CPU2_MODE_MASK (0x300U)
#define CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT (8U)
/*! CPU2_MODE - Domain2 Low Power Mode
* 0b00..Run
* 0b01..Wait
* 0b10..Stop
* 0b11..Suspend
*/
#define CCM_OSCPLL_STATUS1_CPU2_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_MASK)
#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U)
#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U)
/*! CPU2_MODE_REQUEST - Domain2 request enter Low Power Mode
* 0b1..Request from domain to enter Low Power Mode
* 0b0..No request
*/
#define CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_REQUEST_MASK)
#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK (0x800U)
#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT (11U)
/*! CPU2_MODE_DONE - Domain2 Low Power Mode task done
* 0b1..Clock is gated-off
* 0b0..Clock is not gated
*/
#define CCM_OSCPLL_STATUS1_CPU2_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU2_MODE_DONE_MASK)
#define CCM_OSCPLL_STATUS1_CPU3_MODE_MASK (0x3000U)
#define CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT (12U)
/*! CPU3_MODE - Domain3 Low Power Mode
* 0b00..Run
* 0b01..Wait
* 0b10..Stop
* 0b11..Suspend
*/
#define CCM_OSCPLL_STATUS1_CPU3_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_MASK)
#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U)
#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U)
/*! CPU3_MODE_REQUEST - Domain3 request enter Low Power Mode
* 0b1..Request from domain to enter Low Power Mode
* 0b0..No request
*/
#define CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_REQUEST_MASK)
#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK (0x8000U)
#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT (15U)
/*! CPU3_MODE_DONE - Domain3 Low Power Mode task done
* 0b1..Clock is gated-off
* 0b0..Clock is not gated
*/
#define CCM_OSCPLL_STATUS1_CPU3_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_CPU3_MODE_DONE_MASK)
#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT (16U)
/*! TARGET_SETPOINT - Next Setpoint to change to
*/
#define CCM_OSCPLL_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_TARGET_SETPOINT_MASK)
#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
/*! CURRENT_SETPOINT - Current Setpoint
*/
#define CCM_OSCPLL_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_OSCPLL_STATUS1_CURRENT_SETPOINT_MASK)
#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U)
#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U)
/*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC Setpoint
* 0b1..Clock gate requested to be turned off
* 0b0..No request
*/
#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_REQUEST_MASK)
#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U)
#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U)
/*! SETPOINT_OFF_DONE - Clock source turn off finish from GPC Setpoint
* 0b1..Clock source is turned off
* 0b0..Clock source is not turned off
*/
#define CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_OFF_DONE_MASK)
#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U)
#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U)
/*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC Setpoint
* 0b1..Clock gate requested to be turned on
* 0b0..No request
*/
#define CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_REQUEST_MASK)
#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U)
#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT (27U)
/*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC Setpoint
* 0b1..Request to turn on clock gate
* 0b0..No request
*/
#define CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_SETPOINT_ON_DONE_MASK)
#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK (0x10000000U)
#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT (28U)
/*! STANDBY_IN_REQUEST - Clock gate turn off request from GPC standby
* 0b1..Clock gate requested to be turned off
* 0b0..No request
*/
#define CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_REQUEST_MASK)
#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK (0x20000000U)
#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT (29U)
/*! STANDBY_IN_DONE - Clock source turn off finish from GPC standby
* 0b1..Clock source is turned off
* 0b0..Clock source is not turned off
*/
#define CCM_OSCPLL_STATUS1_STANDBY_IN_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_IN_DONE_MASK)
#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK (0x40000000U)
#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT (30U)
/*! STANDBY_OUT_DONE - Clock gate turn on finish from GPC standby
* 0b1..Request to turn on Clock gate is complete
* 0b0..Request to turn on Clock gate is not complete
*/
#define CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_DONE_MASK)
#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK (0x80000000U)
#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT (31U)
/*! STANDBY_OUT_REQUEST - Clock gate turn on request from GPC standby
* 0b1..Clock gate requested to be turned on
* 0b0..No request
*/
#define CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_SHIFT)) & CCM_OSCPLL_STATUS1_STANDBY_OUT_REQUEST_MASK)
/*! @} */
/* The count of CCM_OSCPLL_STATUS1 */
#define CCM_OSCPLL_STATUS1_COUNT (29U)
/*! @name OSCPLL_CONFIG - Clock source configuration */
/*! @{ */
#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK (0x2U)
#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT (1U)
/*! AUTOMODE_PRESENT - Automode Present
* 0b1..Present
* 0b0..Not present
*/
#define CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_AUTOMODE_PRESENT_MASK)
#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
/*! SETPOINT_PRESENT - Setpoint present
* 0b1..Setpoint is implemented.
* 0b0..Setpoint is not implemented.
*/
#define CCM_OSCPLL_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_OSCPLL_CONFIG_SETPOINT_PRESENT_MASK)
/*! @} */
/* The count of CCM_OSCPLL_CONFIG */
#define CCM_OSCPLL_CONFIG_COUNT (29U)
/*! @name OSCPLL_AUTHEN - Clock source access control */
/*! @{ */
#define CCM_OSCPLL_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_OSCPLL_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_USER_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_USER_MASK)
#define CCM_OSCPLL_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_OSCPLL_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_TZ_NS_SHIFT)) & CCM_OSCPLL_AUTHEN_TZ_NS_MASK)
#define CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_OSCPLL_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_TZ_MASK)
#define CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_OSCPLL_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_WHITE_LIST_MASK)
#define CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_OSCPLL_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_LIST_MASK)
#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
* 0b1..Clock works in Domain Mode.
* 0b0..Clock does not work in Domain Mode.
*/
#define CCM_OSCPLL_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT (17U)
/*! SETPOINT_MODE - LPCG works in Setpoint controlled Mode.
*/
#define CCM_OSCPLL_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_SETPOINT_MODE_MASK)
#define CCM_OSCPLL_AUTHEN_CPULPM_MASK (0x40000U)
#define CCM_OSCPLL_AUTHEN_CPULPM_SHIFT (18U)
/*! CPULPM - CPU Low Power Mode
* 0b1..PLL functions in Low Power Mode
* 0b0..PLL does not function in Low power Mode
*/
#define CCM_OSCPLL_AUTHEN_CPULPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_CPULPM_SHIFT)) & CCM_OSCPLL_AUTHEN_CPULPM_MASK)
#define CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_OSCPLL_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OSCPLL_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OSCPLL_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_OSCPLL_AUTHEN */
#define CCM_OSCPLL_AUTHEN_COUNT (29U)
/*! @name LPCG_DIRECT - LPCG direct control */
/*! @{ */
#define CCM_LPCG_DIRECT_ON_MASK (0x1U)
#define CCM_LPCG_DIRECT_ON_SHIFT (0U)
/*! ON - LPCG on
* 0b0..LPCG is OFF.
* 0b1..LPCG is ON.
*/
#define CCM_LPCG_DIRECT_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DIRECT_ON_SHIFT)) & CCM_LPCG_DIRECT_ON_MASK)
/*! @} */
/* The count of CCM_LPCG_DIRECT */
#define CCM_LPCG_DIRECT_COUNT (138U)
/*! @name LPCG_DOMAIN - LPCG domain control */
/*! @{ */
#define CCM_LPCG_DOMAIN_LEVEL_MASK (0x7U)
#define CCM_LPCG_DOMAIN_LEVEL_SHIFT (0U)
/*! LEVEL - Current dependence level
* 0b000..This clock source is not needed in any mode, and can be turned off
* 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
* 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
* 0b011..This clock source is needed in RUN, WAIT and STOP mode
* 0b100..This clock source is always on in any mode (including SUSPEND)
* 0b101, 0b110, 0b111..Reserved
*/
#define CCM_LPCG_DOMAIN_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL_MASK)
#define CCM_LPCG_DOMAIN_LEVEL0_MASK (0x70000U)
#define CCM_LPCG_DOMAIN_LEVEL0_SHIFT (16U)
/*! LEVEL0 - Depend level
* 0b000..This clock source is not needed in any mode, and can be turned off
* 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
* 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
* 0b011..This clock source is needed in RUN, WAIT and STOP mode
* 0b100..This clock source is always on in any mode (including SUSPEND)
* 0b101, 0b110, 0b111..Reserved
*/
#define CCM_LPCG_DOMAIN_LEVEL0(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL0_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL0_MASK)
#define CCM_LPCG_DOMAIN_LEVEL1_MASK (0x700000U)
#define CCM_LPCG_DOMAIN_LEVEL1_SHIFT (20U)
/*! LEVEL1 - Depend level
* 0b000..This clock source is not needed in any mode, and can be turned off
* 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
* 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
* 0b011..This clock source is needed in RUN, WAIT and STOP mode
* 0b100..This clock source is always on in any mode (including SUSPEND)
* 0b101, 0b110, 0b111..Reserved
*/
#define CCM_LPCG_DOMAIN_LEVEL1(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL1_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL1_MASK)
#define CCM_LPCG_DOMAIN_LEVEL2_MASK (0x7000000U)
#define CCM_LPCG_DOMAIN_LEVEL2_SHIFT (24U)
/*! LEVEL2 - Depend level
* 0b000..This clock source is not needed in any mode, and can be turned off
* 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
* 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
* 0b011..This clock source is needed in RUN, WAIT and STOP mode
* 0b100..This clock source is always on in any mode (including SUSPEND)
* 0b101, 0b110, 0b111..Reserved
*/
#define CCM_LPCG_DOMAIN_LEVEL2(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL2_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL2_MASK)
#define CCM_LPCG_DOMAIN_LEVEL3_MASK (0x70000000U)
#define CCM_LPCG_DOMAIN_LEVEL3_SHIFT (28U)
/*! LEVEL3 - Depend level
* 0b000..This clock source is not needed in any mode, and can be turned off
* 0b001..This clock source is needed in RUN mode, but not needed in WAIT, STOP mode
* 0b010..This clock source is needed in RUN and WAIT mode, but not needed in STOP mode
* 0b011..This clock source is needed in RUN, WAIT and STOP mode
* 0b100..This clock source is always on in any mode (including SUSPEND)
* 0b101, 0b110, 0b111..Reserved
*/
#define CCM_LPCG_DOMAIN_LEVEL3(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_DOMAIN_LEVEL3_SHIFT)) & CCM_LPCG_DOMAIN_LEVEL3_MASK)
/*! @} */
/* The count of CCM_LPCG_DOMAIN */
#define CCM_LPCG_DOMAIN_COUNT (138U)
/*! @name LPCG_SETPOINT - LPCG Setpoint setting */
/*! @{ */
#define CCM_LPCG_SETPOINT_SETPOINT_MASK (0xFFFFU)
#define CCM_LPCG_SETPOINT_SETPOINT_SHIFT (0U)
/*! SETPOINT - Setpoints
*/
#define CCM_LPCG_SETPOINT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_SETPOINT_SHIFT)) & CCM_LPCG_SETPOINT_SETPOINT_MASK)
#define CCM_LPCG_SETPOINT_STANDBY_MASK (0xFFFF0000U)
#define CCM_LPCG_SETPOINT_STANDBY_SHIFT (16U)
/*! STANDBY - Standby
*/
#define CCM_LPCG_SETPOINT_STANDBY(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_SETPOINT_STANDBY_SHIFT)) & CCM_LPCG_SETPOINT_STANDBY_MASK)
/*! @} */
/* The count of CCM_LPCG_SETPOINT */
#define CCM_LPCG_SETPOINT_COUNT (138U)
/*! @name LPCG_STATUS0 - LPCG working status */
/*! @{ */
#define CCM_LPCG_STATUS0_ON_MASK (0x1U)
#define CCM_LPCG_STATUS0_ON_SHIFT (0U)
/*! ON - LPCG current state
* 0b0..LPCG is OFF.
* 0b1..LPCG is ON.
*/
#define CCM_LPCG_STATUS0_ON(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ON_SHIFT)) & CCM_LPCG_STATUS0_ON_MASK)
#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK (0xF00U)
#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT (8U)
/*! ACTIVE_DOMAIN - Domains that own this clock gate
* 0b0000..Clock not owned by any domain
* 0b0001..Clock owned by Domain0
* 0b0010..Clock owned by Domain1
* 0b0011..Clock owned by Domain0 and Domain1
* 0b0100..Clock owned by Domain2
* 0b0101..Clock owned by Domain0 and Domain2
* 0b0110..Clock owned by Domain1 and Domain2
* 0b0111..Clock owned by Domain0, Domain1 and Domain 2
* 0b1000..Clock owned by Domain3
* 0b1001..Clock owned by Domain0 and Domain3
* 0b1010..Clock owned by Domain1 and Domain3
* 0b1011..Clock owned by Domain2 and Domain3
* 0b1100..Clock owned by Domain0, Domain 1, and Domain3
* 0b1101..Clock owned by Domain0, Domain 2, and Domain3
* 0b1110..Clock owned by Domain1, Domain 2, and Domain3
* 0b1111..Clock owned by all domains
*/
#define CCM_LPCG_STATUS0_ACTIVE_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_ACTIVE_DOMAIN_SHIFT)) & CCM_LPCG_STATUS0_ACTIVE_DOMAIN_MASK)
#define CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK (0xF000U)
#define CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT (12U)
/*! DOMAIN_ENABLE - Enable status from each domain
* 0b0000..No domain request
* 0b0001..Request from Domain0
* 0b0010..Request from Domain1
* 0b0011..Request from Domain0 and Domain1
* 0b0100..Request from Domain2
* 0b0101..Request from Domain0 and Domain2
* 0b0110..Request from Domain1 and Domain2
* 0b0111..Request from Domain0, Domain1 and Domain 2
* 0b1000..Request from Domain3
* 0b1001..Request from Domain0 and Domain3
* 0b1010..Request from Domain1 and Domain3
* 0b1011..Request from Domain2 and Domain3
* 0b1100..Request from Domain0, Domain 1, and Domain3
* 0b1101..Request from Domain0, Domain 2, and Domain3
* 0b1110..Request from Domain1, Domain 2, and Domain3
* 0b1111..Request from all domains
*/
#define CCM_LPCG_STATUS0_DOMAIN_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS0_DOMAIN_ENABLE_SHIFT)) & CCM_LPCG_STATUS0_DOMAIN_ENABLE_MASK)
/*! @} */
/* The count of CCM_LPCG_STATUS0 */
#define CCM_LPCG_STATUS0_COUNT (138U)
/*! @name LPCG_STATUS1 - LPCG low power status */
/*! @{ */
#define CCM_LPCG_STATUS1_CPU0_MODE_MASK (0x3U)
#define CCM_LPCG_STATUS1_CPU0_MODE_SHIFT (0U)
/*! CPU0_MODE - Domain0 Low Power Mode
* 0b00..Run
* 0b01..Wait
* 0b10..Stop
* 0b11..Suspend
*/
#define CCM_LPCG_STATUS1_CPU0_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_MASK)
#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK (0x4U)
#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT (2U)
/*! CPU0_MODE_REQUEST - Domain0 request enter Low Power Mode
* 0b1..Request from domain to enter Low Power Mode
* 0b0..No request
*/
#define CCM_LPCG_STATUS1_CPU0_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_REQUEST_MASK)
#define CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK (0x8U)
#define CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT (3U)
/*! CPU0_MODE_DONE - Domain0 Low Power Mode task done
* 0b1..Clock is gated-off
* 0b0..Clock is not gated
*/
#define CCM_LPCG_STATUS1_CPU0_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU0_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU0_MODE_DONE_MASK)
#define CCM_LPCG_STATUS1_CPU1_MODE_MASK (0x30U)
#define CCM_LPCG_STATUS1_CPU1_MODE_SHIFT (4U)
/*! CPU1_MODE - Domain1 Low Power Mode
* 0b00..Run
* 0b01..Wait
* 0b10..Stop
* 0b11..Suspend
*/
#define CCM_LPCG_STATUS1_CPU1_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_MASK)
#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK (0x40U)
#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT (6U)
/*! CPU1_MODE_REQUEST - Domain1 request enter Low Power Mode
* 0b1..Request from domain to enter Low Power Mode
* 0b0..No request
*/
#define CCM_LPCG_STATUS1_CPU1_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_REQUEST_MASK)
#define CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK (0x80U)
#define CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT (7U)
/*! CPU1_MODE_DONE - Domain1 Low Power Mode task done
* 0b1..Clock is gated-off
* 0b0..Clock is not gated
*/
#define CCM_LPCG_STATUS1_CPU1_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU1_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU1_MODE_DONE_MASK)
#define CCM_LPCG_STATUS1_CPU2_MODE_MASK (0x300U)
#define CCM_LPCG_STATUS1_CPU2_MODE_SHIFT (8U)
/*! CPU2_MODE - Domain2 Low Power Mode
* 0b00..Run
* 0b01..Wait
* 0b10..Stop
* 0b11..Suspend
*/
#define CCM_LPCG_STATUS1_CPU2_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_MASK)
#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK (0x400U)
#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT (10U)
/*! CPU2_MODE_REQUEST - Domain2 request enter Low Power Mode
* 0b1..Request from domain to enter Low Power Mode
* 0b0..No request
*/
#define CCM_LPCG_STATUS1_CPU2_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_REQUEST_MASK)
#define CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK (0x800U)
#define CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT (11U)
/*! CPU2_MODE_DONE - Domain2 Low Power Mode task done
* 0b1..Clock is gated-off
* 0b0..Clock is not gated
*/
#define CCM_LPCG_STATUS1_CPU2_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU2_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU2_MODE_DONE_MASK)
#define CCM_LPCG_STATUS1_CPU3_MODE_MASK (0x3000U)
#define CCM_LPCG_STATUS1_CPU3_MODE_SHIFT (12U)
/*! CPU3_MODE - Domain3 Low Power Mode
* 0b00..Run
* 0b01..Wait
* 0b10..Stop
* 0b11..Suspend
*/
#define CCM_LPCG_STATUS1_CPU3_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_MASK)
#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK (0x4000U)
#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT (14U)
/*! CPU3_MODE_REQUEST - Domain3 request enter Low Power Mode
* 0b1..Request from domain to enter Low Power Mode
* 0b0..No request
*/
#define CCM_LPCG_STATUS1_CPU3_MODE_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_REQUEST_MASK)
#define CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK (0x8000U)
#define CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT (15U)
/*! CPU3_MODE_DONE - Domain3 Low Power Mode task done
* 0b1..Clock is gated-off
* 0b0..Clock is not gated
*/
#define CCM_LPCG_STATUS1_CPU3_MODE_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CPU3_MODE_DONE_SHIFT)) & CCM_LPCG_STATUS1_CPU3_MODE_DONE_MASK)
#define CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK (0xF0000U)
#define CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT (16U)
/*! TARGET_SETPOINT - Next Setpoint to change to
*/
#define CCM_LPCG_STATUS1_TARGET_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_TARGET_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_TARGET_SETPOINT_MASK)
#define CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK (0xF00000U)
#define CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT (20U)
/*! CURRENT_SETPOINT - Current Setpoint
*/
#define CCM_LPCG_STATUS1_CURRENT_SETPOINT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_CURRENT_SETPOINT_SHIFT)) & CCM_LPCG_STATUS1_CURRENT_SETPOINT_MASK)
#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK (0x1000000U)
#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT (24U)
/*! SETPOINT_OFF_REQUEST - Clock gate turn off request from GPC Setpoint
* 0b1..Clock gate requested to be turned off
* 0b0..No request
*/
#define CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_REQUEST_MASK)
#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK (0x2000000U)
#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT (25U)
/*! SETPOINT_OFF_DONE - Clock gate turn off finish from GPC Setpoint
* 0b1..Clock gate is turned off
* 0b0..Clock gate is not turned off
*/
#define CCM_LPCG_STATUS1_SETPOINT_OFF_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_OFF_DONE_MASK)
#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK (0x4000000U)
#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT (26U)
/*! SETPOINT_ON_REQUEST - Clock gate turn on request from GPC Setpoint
* 0b1..Clock gate requested to be turned on
* 0b0..No request
*/
#define CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_REQUEST_MASK)
#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK (0x8000000U)
#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT (27U)
/*! SETPOINT_ON_DONE - Clock gate turn on finish from GPC Setpoint
* 0b1..Clock gate is turned on
* 0b0..Clock gate is not turned on
*/
#define CCM_LPCG_STATUS1_SETPOINT_ON_DONE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_STATUS1_SETPOINT_ON_DONE_SHIFT)) & CCM_LPCG_STATUS1_SETPOINT_ON_DONE_MASK)
/*! @} */
/* The count of CCM_LPCG_STATUS1 */
#define CCM_LPCG_STATUS1_COUNT (138U)
/*! @name LPCG_CONFIG - LPCG configuration */
/*! @{ */
#define CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK (0x10U)
#define CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT (4U)
/*! SETPOINT_PRESENT - Setpoint present
* 0b1..Setpoint is implemented.
* 0b0..Setpoint is not implemented.
*/
#define CCM_LPCG_CONFIG_SETPOINT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_CONFIG_SETPOINT_PRESENT_SHIFT)) & CCM_LPCG_CONFIG_SETPOINT_PRESENT_MASK)
/*! @} */
/* The count of CCM_LPCG_CONFIG */
#define CCM_LPCG_CONFIG_COUNT (138U)
/*! @name LPCG_AUTHEN - LPCG access control */
/*! @{ */
#define CCM_LPCG_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_LPCG_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..LPCG can be changed in user mode.
* 0b0..LPCG cannot be changed in user mode.
*/
#define CCM_LPCG_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_USER_SHIFT)) & CCM_LPCG_AUTHEN_TZ_USER_MASK)
#define CCM_LPCG_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_LPCG_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_LPCG_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_TZ_NS_SHIFT)) & CCM_LPCG_AUTHEN_TZ_NS_MASK)
#define CCM_LPCG_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_LPCG_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_TZ_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_TZ_MASK)
#define CCM_LPCG_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Whitelist
*/
#define CCM_LPCG_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_WHITE_LIST_SHIFT)) & CCM_LPCG_AUTHEN_WHITE_LIST_MASK)
#define CCM_LPCG_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock Whitelist
* 0b0..Whitelist is not locked.
* 0b1..Whitelist is locked.
*/
#define CCM_LPCG_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_LIST_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_LIST_MASK)
#define CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
* 0b1..Clock works in Domain Mode
* 0b0..Clock does not work in Domain Mode
*/
#define CCM_LPCG_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_LPCG_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK (0x20000U)
#define CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT (17U)
/*! SETPOINT_MODE - Low power and access control by Setpoint
* 0b1..LPCG is functioning in Setpoint controlled Mode
* 0b0..LPCG is not functioning in Setpoint controlled Mode
*/
#define CCM_LPCG_AUTHEN_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_SETPOINT_MODE_SHIFT)) & CCM_LPCG_AUTHEN_SETPOINT_MODE_MASK)
#define CCM_LPCG_AUTHEN_CPULPM_MASK (0x40000U)
#define CCM_LPCG_AUTHEN_CPULPM_SHIFT (18U)
/*! CPULPM - CPU Low Power Mode
* 0b1..LPCG is functioning in Low Power Mode
* 0b0..LPCG is not functioning in Low power Mode
*/
#define CCM_LPCG_AUTHEN_CPULPM(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_CPULPM_SHIFT)) & CCM_LPCG_AUTHEN_CPULPM_MASK)
#define CCM_LPCG_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_LPCG_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_LPCG_AUTHEN_LOCK_MODE_SHIFT)) & CCM_LPCG_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_LPCG_AUTHEN */
#define CCM_LPCG_AUTHEN_COUNT (138U)
/*!
* @}
*/ /* end of group CCM_Register_Masks */
/* CCM - Peripheral instance base addresses */
/** Peripheral CCM base address */
#define CCM_BASE (0x40CC0000u)
/** Peripheral CCM base pointer */
#define CCM ((CCM_Type *)CCM_BASE)
/** Array initializer of CCM peripheral base addresses */
#define CCM_BASE_ADDRS { CCM_BASE }
/** Array initializer of CCM peripheral base pointers */
#define CCM_BASE_PTRS { CCM }
/*!
* @}
*/ /* end of group CCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CCM_OBS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_OBS_Peripheral_Access_Layer CCM_OBS Peripheral Access Layer
* @{
*/
/** CCM_OBS - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x80 */
__IO uint32_t CONTROL; /**< Observe control, array offset: 0x0, array step: 0x80 */
__IO uint32_t CONTROL_SET; /**< Observe control, array offset: 0x4, array step: 0x80 */
__IO uint32_t CONTROL_CLR; /**< Observe control, array offset: 0x8, array step: 0x80 */
__IO uint32_t CONTROL_TOG; /**< Observe control, array offset: 0xC, array step: 0x80 */
uint8_t RESERVED_0[16];
__I uint32_t STATUS0; /**< Observe status, array offset: 0x20, array step: 0x80 */
uint8_t RESERVED_1[12];
__IO uint32_t AUTHEN; /**< Observe access control, array offset: 0x30, array step: 0x80 */
__IO uint32_t AUTHEN_SET; /**< Observe access control, array offset: 0x34, array step: 0x80 */
__IO uint32_t AUTHEN_CLR; /**< Observe access control, array offset: 0x38, array step: 0x80 */
__IO uint32_t AUTHEN_TOG; /**< Observe access control, array offset: 0x3C, array step: 0x80 */
__I uint32_t FREQUENCY_CURRENT; /**< Current frequency detected, array offset: 0x40, array step: 0x80 */
__I uint32_t FREQUENCY_MIN; /**< Minimum frequency detected, array offset: 0x44, array step: 0x80 */
__I uint32_t FREQUENCY_MAX; /**< Maximum frequency detected, array offset: 0x48, array step: 0x80 */
uint8_t RESERVED_2[52];
} OBSERVE[6];
} CCM_OBS_Type;
/* ----------------------------------------------------------------------------
-- CCM_OBS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CCM_OBS_Register_Masks CCM_OBS Register Masks
* @{
*/
/*! @name OBSERVE_CONTROL - Observe control */
/*! @{ */
#define CCM_OBS_OBSERVE_CONTROL_SELECT_MASK (0x1FFU)
#define CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT (0U)
/*! SELECT - Observe signal selector
*/
#define CCM_OBS_OBSERVE_CONTROL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SELECT_MASK)
#define CCM_OBS_OBSERVE_CONTROL_RAW_MASK (0x1000U)
#define CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT (12U)
/*! RAW - Observe raw signal
* 0b0..Select divided signal.
* 0b1..Select raw signal.
*/
#define CCM_OBS_OBSERVE_CONTROL_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RAW_MASK)
#define CCM_OBS_OBSERVE_CONTROL_INV_MASK (0x2000U)
#define CCM_OBS_OBSERVE_CONTROL_INV_SHIFT (13U)
/*! INV - Invert
* 0b0..Clock phase remain same.
* 0b1..Invert clock phase before measurement or send to IO.
*/
#define CCM_OBS_OBSERVE_CONTROL_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_INV_MASK)
#define CCM_OBS_OBSERVE_CONTROL_RESET_MASK (0x8000U)
#define CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT (15U)
/*! RESET - Reset observe divider
* 0b0..No reset
* 0b1..Reset observe divider
*/
#define CCM_OBS_OBSERVE_CONTROL_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_RESET_MASK)
#define CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK (0xFF0000U)
#define CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT (16U)
/*! DIVIDE - Divider for observe signal
*/
#define CCM_OBS_OBSERVE_CONTROL_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_DIVIDE_MASK)
#define CCM_OBS_OBSERVE_CONTROL_OFF_MASK (0x1000000U)
#define CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT (24U)
/*! OFF - Turn off
* 0b0..observe slice is on
* 0b1..observe slice is off
*/
#define CCM_OBS_OBSERVE_CONTROL_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_OFF_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_CONTROL */
#define CCM_OBS_OBSERVE_CONTROL_COUNT (6U)
/*! @name OBSERVE_CONTROL_SET - Observe control */
/*! @{ */
#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK (0x1FFU)
#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT (0U)
/*! SELECT - Observe signal selector
*/
#define CCM_OBS_OBSERVE_CONTROL_SET_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_SELECT_MASK)
#define CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK (0x1000U)
#define CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT (12U)
/*! RAW - Observe raw signal
*/
#define CCM_OBS_OBSERVE_CONTROL_SET_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RAW_MASK)
#define CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK (0x2000U)
#define CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT (13U)
/*! INV - Invert
*/
#define CCM_OBS_OBSERVE_CONTROL_SET_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_INV_MASK)
#define CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK (0x8000U)
#define CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT (15U)
/*! RESET - Reset observe divider
*/
#define CCM_OBS_OBSERVE_CONTROL_SET_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_RESET_MASK)
#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK (0xFF0000U)
#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT (16U)
/*! DIVIDE - Divider for observe signal
*/
#define CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_DIVIDE_MASK)
#define CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK (0x1000000U)
#define CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT (24U)
/*! OFF - Turn off
*/
#define CCM_OBS_OBSERVE_CONTROL_SET_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_SET_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_SET_OFF_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_CONTROL_SET */
#define CCM_OBS_OBSERVE_CONTROL_SET_COUNT (6U)
/*! @name OBSERVE_CONTROL_CLR - Observe control */
/*! @{ */
#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK (0x1FFU)
#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT (0U)
/*! SELECT - Observe signal selector
*/
#define CCM_OBS_OBSERVE_CONTROL_CLR_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_SELECT_MASK)
#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK (0x1000U)
#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT (12U)
/*! RAW - Observe raw signal
*/
#define CCM_OBS_OBSERVE_CONTROL_CLR_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RAW_MASK)
#define CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK (0x2000U)
#define CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT (13U)
/*! INV - Invert
*/
#define CCM_OBS_OBSERVE_CONTROL_CLR_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_INV_MASK)
#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK (0x8000U)
#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT (15U)
/*! RESET - Reset observe divider
*/
#define CCM_OBS_OBSERVE_CONTROL_CLR_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_RESET_MASK)
#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK (0xFF0000U)
#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT (16U)
/*! DIVIDE - Divider for observe signal
*/
#define CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_DIVIDE_MASK)
#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK (0x1000000U)
#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT (24U)
/*! OFF - Turn off
*/
#define CCM_OBS_OBSERVE_CONTROL_CLR_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_CLR_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_CLR_OFF_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_CONTROL_CLR */
#define CCM_OBS_OBSERVE_CONTROL_CLR_COUNT (6U)
/*! @name OBSERVE_CONTROL_TOG - Observe control */
/*! @{ */
#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK (0x1FFU)
#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT (0U)
/*! SELECT - Observe signal selector
*/
#define CCM_OBS_OBSERVE_CONTROL_TOG_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_SELECT_MASK)
#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK (0x1000U)
#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT (12U)
/*! RAW - Observe raw signal
*/
#define CCM_OBS_OBSERVE_CONTROL_TOG_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RAW_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RAW_MASK)
#define CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK (0x2000U)
#define CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT (13U)
/*! INV - Invert
*/
#define CCM_OBS_OBSERVE_CONTROL_TOG_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_INV_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_INV_MASK)
#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK (0x8000U)
#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT (15U)
/*! RESET - Reset observe divider
*/
#define CCM_OBS_OBSERVE_CONTROL_TOG_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_RESET_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_RESET_MASK)
#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK (0xFF0000U)
#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT (16U)
/*! DIVIDE - Divider for observe signal
*/
#define CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_DIVIDE_MASK)
#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK (0x1000000U)
#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT (24U)
/*! OFF - Turn off
*/
#define CCM_OBS_OBSERVE_CONTROL_TOG_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_CONTROL_TOG_OFF_SHIFT)) & CCM_OBS_OBSERVE_CONTROL_TOG_OFF_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_CONTROL_TOG */
#define CCM_OBS_OBSERVE_CONTROL_TOG_COUNT (6U)
/*! @name OBSERVE_STATUS0 - Observe status */
/*! @{ */
#define CCM_OBS_OBSERVE_STATUS0_SELECT_MASK (0x1FFU)
#define CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT (0U)
/*! SELECT - Select value
*/
#define CCM_OBS_OBSERVE_STATUS0_SELECT(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_SELECT_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_SELECT_MASK)
#define CCM_OBS_OBSERVE_STATUS0_RAW_MASK (0x1000U)
#define CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT (12U)
/*! RAW - Observe raw signal
* 0b0..Divided signal is selected
* 0b1..Raw signal is selected
*/
#define CCM_OBS_OBSERVE_STATUS0_RAW(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RAW_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RAW_MASK)
#define CCM_OBS_OBSERVE_STATUS0_INV_MASK (0x2000U)
#define CCM_OBS_OBSERVE_STATUS0_INV_SHIFT (13U)
/*! INV - Polarity of the observe target
* 0b1..Polarity of the observe target is inverted
* 0b0..Polarity is not inverted
*/
#define CCM_OBS_OBSERVE_STATUS0_INV(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_INV_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_INV_MASK)
#define CCM_OBS_OBSERVE_STATUS0_RESET_MASK (0x8000U)
#define CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT (15U)
/*! RESET - Reset state
* 0b1..Observe divider is in reset state
* 0b0..Observe divider is not in reset state
*/
#define CCM_OBS_OBSERVE_STATUS0_RESET(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_RESET_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_RESET_MASK)
#define CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK (0xFF0000U)
#define CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT (16U)
/*! DIVIDE - Divide value status. The clock will be divided by DIVIDE + 1.
*/
#define CCM_OBS_OBSERVE_STATUS0_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_DIVIDE_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_DIVIDE_MASK)
#define CCM_OBS_OBSERVE_STATUS0_OFF_MASK (0x1000000U)
#define CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT (24U)
/*! OFF - Turn off slice
* 0b0..observe slice is on
* 0b1..observe slice is off
*/
#define CCM_OBS_OBSERVE_STATUS0_OFF(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_STATUS0_OFF_SHIFT)) & CCM_OBS_OBSERVE_STATUS0_OFF_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_STATUS0 */
#define CCM_OBS_OBSERVE_STATUS0_COUNT (6U)
/*! @name OBSERVE_AUTHEN - Observe access control */
/*! @{ */
#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK (0x1U)
#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
* 0b1..Clock can be changed in user mode.
* 0b0..Clock cannot be changed in user mode.
*/
#define CCM_OBS_OBSERVE_AUTHEN_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_USER_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK (0x2U)
#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
* 0b0..Cannot be changed in Non-secure mode.
* 0b1..Can be changed in Non-secure mode.
*/
#define CCM_OBS_OBSERVE_AUTHEN_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TZ_NS_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK (0x10U)
#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
* 0b0..Trustzone setting is not locked.
* 0b1..Trustzone setting is locked.
*/
#define CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_TZ_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK (0xF00U)
#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - White list
* 0b1111..All domain can change.
* 0b0010..Domain 1 can change.
* 0b0011..Domain 0 and domain 1 can change.
* 0b0000..No domain can change.
* 0b0100..Domain 2 can change.
* 0b0001..Domain 0 can change.
*/
#define CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_WHITE_LIST_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK (0x1000U)
#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock white list
* 0b0..White list is not locked.
* 0b1..White list is locked.
*/
#define CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_LIST_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK (0x10000U)
#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
* 0b1..Clock works in domain mode.
* 0b0..Clock does not work in domain mode.
*/
#define CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_DOMAIN_MODE_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK (0x100000U)
#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
* 0b0..MODE is not locked.
* 0b1..MODE is locked.
*/
#define CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_AUTHEN */
#define CCM_OBS_OBSERVE_AUTHEN_COUNT (6U)
/*! @name OBSERVE_AUTHEN_SET - Observe access control */
/*! @{ */
#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK (0x1U)
#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_USER_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK (0x2U)
#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_TZ_NS_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK (0x10U)
#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_TZ_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK (0xF00U)
#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - White list
*/
#define CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_WHITE_LIST_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK (0x1000U)
#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock white list
*/
#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_LIST_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK (0x10000U)
#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_DOMAIN_MODE_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK (0x100000U)
#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_SET_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_AUTHEN_SET */
#define CCM_OBS_OBSERVE_AUTHEN_SET_COUNT (6U)
/*! @name OBSERVE_AUTHEN_CLR - Observe access control */
/*! @{ */
#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK (0x1U)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_USER_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK (0x2U)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_TZ_NS_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK (0x10U)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_TZ_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK (0xF00U)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - White list
*/
#define CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_WHITE_LIST_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK (0x1000U)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock white list
*/
#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_LIST_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK (0x10000U)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_DOMAIN_MODE_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK (0x100000U)
#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_CLR_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_AUTHEN_CLR */
#define CCM_OBS_OBSERVE_AUTHEN_CLR_COUNT (6U)
/*! @name OBSERVE_AUTHEN_TOG - Observe access control */
/*! @{ */
#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK (0x1U)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT (0U)
/*! TZ_USER - User access
*/
#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_USER_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK (0x2U)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT (1U)
/*! TZ_NS - Non-secure access
*/
#define CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_TZ_NS_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK (0x10U)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT (4U)
/*! LOCK_TZ - Lock truszone setting
*/
#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_TZ_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK (0xF00U)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - White list
*/
#define CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_WHITE_LIST_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK (0x1000U)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - Lock white list
*/
#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_LIST_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK (0x10000U)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT (16U)
/*! DOMAIN_MODE - Low power and access control by domain
*/
#define CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_DOMAIN_MODE_MASK)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK (0x100000U)
#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT (20U)
/*! LOCK_MODE - Lock low power and access mode
*/
#define CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_SHIFT)) & CCM_OBS_OBSERVE_AUTHEN_TOG_LOCK_MODE_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_AUTHEN_TOG */
#define CCM_OBS_OBSERVE_AUTHEN_TOG_COUNT (6U)
/*! @name OBSERVE_FREQUENCY_CURRENT - Current frequency detected */
/*! @{ */
#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK (0xFFFFFFFFU)
#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT (0U)
/*! FREQUENCY - Frequency
*/
#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_CURRENT_FREQUENCY_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_FREQUENCY_CURRENT */
#define CCM_OBS_OBSERVE_FREQUENCY_CURRENT_COUNT (6U)
/*! @name OBSERVE_FREQUENCY_MIN - Minimum frequency detected */
/*! @{ */
#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK (0xFFFFFFFFU)
#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT (0U)
/*! FREQUENCY - Frequency
*/
#define CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MIN_FREQUENCY_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_FREQUENCY_MIN */
#define CCM_OBS_OBSERVE_FREQUENCY_MIN_COUNT (6U)
/*! @name OBSERVE_FREQUENCY_MAX - Maximum frequency detected */
/*! @{ */
#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK (0xFFFFFFFFU)
#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT (0U)
/*! FREQUENCY - Frequency
*/
#define CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY(x) (((uint32_t)(((uint32_t)(x)) << CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_SHIFT)) & CCM_OBS_OBSERVE_FREQUENCY_MAX_FREQUENCY_MASK)
/*! @} */
/* The count of CCM_OBS_OBSERVE_FREQUENCY_MAX */
#define CCM_OBS_OBSERVE_FREQUENCY_MAX_COUNT (6U)
/*!
* @}
*/ /* end of group CCM_OBS_Register_Masks */
/* CCM_OBS - Peripheral instance base addresses */
/** Peripheral CCM_OBS base address */
#define CCM_OBS_BASE (0x40150000u)
/** Peripheral CCM_OBS base pointer */
#define CCM_OBS ((CCM_OBS_Type *)CCM_OBS_BASE)
/** Array initializer of CCM_OBS peripheral base addresses */
#define CCM_OBS_BASE_ADDRS { CCM_OBS_BASE }
/** Array initializer of CCM_OBS peripheral base pointers */
#define CCM_OBS_BASE_PTRS { CCM_OBS }
/*!
* @}
*/ /* end of group CCM_OBS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CDOG_Peripheral_Access_Layer CDOG Peripheral Access Layer
* @{
*/
/** CDOG - Register Layout Typedef */
typedef struct {
__IO uint32_t CONTROL; /**< Control, offset: 0x0 */
__IO uint32_t RELOAD; /**< Instruction Timer reload, offset: 0x4 */
__IO uint32_t INSTRUCTION_TIMER; /**< Instruction Timer, offset: 0x8 */
__O uint32_t SECURE_COUNTER; /**< Secure Counter, offset: 0xC */
__I uint32_t STATUS; /**< Status 1, offset: 0x10 */
__I uint32_t STATUS2; /**< Status 2, offset: 0x14 */
__IO uint32_t FLAGS; /**< Flags, offset: 0x18 */
__IO uint32_t PERSISTENT; /**< Persistent Data Storage, offset: 0x1C */
__O uint32_t START; /**< START Command, offset: 0x20 */
__O uint32_t STOP; /**< STOP Command, offset: 0x24 */
__O uint32_t RESTART; /**< RESTART Command, offset: 0x28 */
__O uint32_t ADD; /**< ADD Command, offset: 0x2C */
__O uint32_t ADD1; /**< ADD1 Command, offset: 0x30 */
__O uint32_t ADD16; /**< ADD16 Command, offset: 0x34 */
__O uint32_t ADD256; /**< ADD256 Command, offset: 0x38 */
__O uint32_t SUB; /**< SUB Command, offset: 0x3C */
__O uint32_t SUB1; /**< SUB1 Command, offset: 0x40 */
__O uint32_t SUB16; /**< SUB16 Command, offset: 0x44 */
__O uint32_t SUB256; /**< SUB256 Command, offset: 0x48 */
} CDOG_Type;
/* ----------------------------------------------------------------------------
-- CDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CDOG_Register_Masks CDOG Register Masks
* @{
*/
/*! @name CONTROL - Control */
/*! @{ */
#define CDOG_CONTROL_LOCK_CTRL_MASK (0x3U)
#define CDOG_CONTROL_LOCK_CTRL_SHIFT (0U)
/*! LOCK_CTRL - Lock control
* 0b01..Locked
* 0b10..Unlocked
*/
#define CDOG_CONTROL_LOCK_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_LOCK_CTRL_SHIFT)) & CDOG_CONTROL_LOCK_CTRL_MASK)
#define CDOG_CONTROL_TIMEOUT_CTRL_MASK (0x1CU)
#define CDOG_CONTROL_TIMEOUT_CTRL_SHIFT (2U)
/*! TIMEOUT_CTRL - TIMEOUT fault control
* 0b100..Disable both reset and interrupt
* 0b001..Enable reset
* 0b010..Enable interrupt
*/
#define CDOG_CONTROL_TIMEOUT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_TIMEOUT_CTRL_SHIFT)) & CDOG_CONTROL_TIMEOUT_CTRL_MASK)
#define CDOG_CONTROL_MISCOMPARE_CTRL_MASK (0xE0U)
#define CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT (5U)
/*! MISCOMPARE_CTRL - MISCOMPARE fault control
* 0b100..Disable both reset and interrupt
* 0b001..Enable reset
* 0b010..Enable interrupt
*/
#define CDOG_CONTROL_MISCOMPARE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_MISCOMPARE_CTRL_SHIFT)) & CDOG_CONTROL_MISCOMPARE_CTRL_MASK)
#define CDOG_CONTROL_SEQUENCE_CTRL_MASK (0x700U)
#define CDOG_CONTROL_SEQUENCE_CTRL_SHIFT (8U)
/*! SEQUENCE_CTRL - SEQUENCE fault control
* 0b001..Enable reset
* 0b010..Enable interrupt
* 0b100..Disable both reset and interrupt
*/
#define CDOG_CONTROL_SEQUENCE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_SEQUENCE_CTRL_SHIFT)) & CDOG_CONTROL_SEQUENCE_CTRL_MASK)
#define CDOG_CONTROL_CONTROL_CTRL_MASK (0x3800U)
#define CDOG_CONTROL_CONTROL_CTRL_SHIFT (11U)
/*! CONTROL_CTRL - CONTROL fault control
* 0b001..Enable reset
* 0b100..Disable reset
*/
#define CDOG_CONTROL_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_CONTROL_CTRL_SHIFT)) & CDOG_CONTROL_CONTROL_CTRL_MASK)
#define CDOG_CONTROL_STATE_CTRL_MASK (0x1C000U)
#define CDOG_CONTROL_STATE_CTRL_SHIFT (14U)
/*! STATE_CTRL - STATE fault control
* 0b001..Enable reset
* 0b010..Enable interrupt
* 0b100..Disable both reset and interrupt
*/
#define CDOG_CONTROL_STATE_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_STATE_CTRL_SHIFT)) & CDOG_CONTROL_STATE_CTRL_MASK)
#define CDOG_CONTROL_ADDRESS_CTRL_MASK (0xE0000U)
#define CDOG_CONTROL_ADDRESS_CTRL_SHIFT (17U)
/*! ADDRESS_CTRL - ADDRESS fault control
* 0b001..Enable reset
* 0b010..Enable interrupt
* 0b100..Disable both reset and interrupt
*/
#define CDOG_CONTROL_ADDRESS_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_ADDRESS_CTRL_SHIFT)) & CDOG_CONTROL_ADDRESS_CTRL_MASK)
#define CDOG_CONTROL_IRQ_PAUSE_MASK (0x30000000U)
#define CDOG_CONTROL_IRQ_PAUSE_SHIFT (28U)
/*! IRQ_PAUSE - IRQ pause control
* 0b01..Keep the timer running
* 0b10..Stop the timer
*/
#define CDOG_CONTROL_IRQ_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_IRQ_PAUSE_SHIFT)) & CDOG_CONTROL_IRQ_PAUSE_MASK)
#define CDOG_CONTROL_DEBUG_HALT_CTRL_MASK (0xC0000000U)
#define CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT (30U)
/*! DEBUG_HALT_CTRL - DEBUG_HALT control
* 0b01..Keep the timer running
* 0b10..Stop the timer
*/
#define CDOG_CONTROL_DEBUG_HALT_CTRL(x) (((uint32_t)(((uint32_t)(x)) << CDOG_CONTROL_DEBUG_HALT_CTRL_SHIFT)) & CDOG_CONTROL_DEBUG_HALT_CTRL_MASK)
/*! @} */
/*! @name RELOAD - Instruction Timer reload */
/*! @{ */
#define CDOG_RELOAD_RLOAD_MASK (0xFFFFFFFFU)
#define CDOG_RELOAD_RLOAD_SHIFT (0U)
/*! RLOAD - Instruction Timer reload value
*/
#define CDOG_RELOAD_RLOAD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RELOAD_RLOAD_SHIFT)) & CDOG_RELOAD_RLOAD_MASK)
/*! @} */
/*! @name INSTRUCTION_TIMER - Instruction Timer */
/*! @{ */
#define CDOG_INSTRUCTION_TIMER_INSTIM_MASK (0xFFFFFFFFU)
#define CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT (0U)
/*! INSTIM - Current value of the Instruction Timer
*/
#define CDOG_INSTRUCTION_TIMER_INSTIM(x) (((uint32_t)(((uint32_t)(x)) << CDOG_INSTRUCTION_TIMER_INSTIM_SHIFT)) & CDOG_INSTRUCTION_TIMER_INSTIM_MASK)
/*! @} */
/*! @name SECURE_COUNTER - Secure Counter */
/*! @{ */
#define CDOG_SECURE_COUNTER_SECCNT_MASK (0xFFFFFFFFU)
#define CDOG_SECURE_COUNTER_SECCNT_SHIFT (0U)
/*! SECCNT - Secure Counter
*/
#define CDOG_SECURE_COUNTER_SECCNT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SECURE_COUNTER_SECCNT_SHIFT)) & CDOG_SECURE_COUNTER_SECCNT_MASK)
/*! @} */
/*! @name STATUS - Status 1 */
/*! @{ */
#define CDOG_STATUS_NUMTOF_MASK (0xFFU)
#define CDOG_STATUS_NUMTOF_SHIFT (0U)
/*! NUMTOF - Number of TIMEOUT faults since the last POR
*/
#define CDOG_STATUS_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMTOF_SHIFT)) & CDOG_STATUS_NUMTOF_MASK)
#define CDOG_STATUS_NUMMISCOMPF_MASK (0xFF00U)
#define CDOG_STATUS_NUMMISCOMPF_SHIFT (8U)
/*! NUMMISCOMPF - Number of MISCOMPARE faults since the last POR
*/
#define CDOG_STATUS_NUMMISCOMPF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMMISCOMPF_SHIFT)) & CDOG_STATUS_NUMMISCOMPF_MASK)
#define CDOG_STATUS_NUMILSEQF_MASK (0xFF0000U)
#define CDOG_STATUS_NUMILSEQF_SHIFT (16U)
/*! NUMILSEQF - Number of SEQUENCE faults since the last POR
*/
#define CDOG_STATUS_NUMILSEQF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_NUMILSEQF_SHIFT)) & CDOG_STATUS_NUMILSEQF_MASK)
#define CDOG_STATUS_CURST_MASK (0xF0000000U)
#define CDOG_STATUS_CURST_SHIFT (28U)
/*! CURST - Current State
*/
#define CDOG_STATUS_CURST(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS_CURST_SHIFT)) & CDOG_STATUS_CURST_MASK)
/*! @} */
/*! @name STATUS2 - Status 2 */
/*! @{ */
#define CDOG_STATUS2_NUMCNTF_MASK (0xFFU)
#define CDOG_STATUS2_NUMCNTF_SHIFT (0U)
/*! NUMCNTF - Number of CONTROL faults since the last POR
*/
#define CDOG_STATUS2_NUMCNTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMCNTF_SHIFT)) & CDOG_STATUS2_NUMCNTF_MASK)
#define CDOG_STATUS2_NUMILLSTF_MASK (0xFF00U)
#define CDOG_STATUS2_NUMILLSTF_SHIFT (8U)
/*! NUMILLSTF - Number of STATE faults since the last POR
*/
#define CDOG_STATUS2_NUMILLSTF(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLSTF_SHIFT)) & CDOG_STATUS2_NUMILLSTF_MASK)
#define CDOG_STATUS2_NUMILLA_MASK (0xFF0000U)
#define CDOG_STATUS2_NUMILLA_SHIFT (16U)
/*! NUMILLA - Number of ADDRESS faults since the last POR
*/
#define CDOG_STATUS2_NUMILLA(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STATUS2_NUMILLA_SHIFT)) & CDOG_STATUS2_NUMILLA_MASK)
/*! @} */
/*! @name FLAGS - Flags */
/*! @{ */
#define CDOG_FLAGS_TO_FLAG_MASK (0x1U)
#define CDOG_FLAGS_TO_FLAG_SHIFT (0U)
/*! TO_FLAG - TIMEOUT fault flag
* 0b0..A TIMEOUT fault has not occurred
* 0b1..A TIMEOUT fault has occurred
*/
#define CDOG_FLAGS_TO_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_TO_FLAG_SHIFT)) & CDOG_FLAGS_TO_FLAG_MASK)
#define CDOG_FLAGS_MISCOM_FLAG_MASK (0x2U)
#define CDOG_FLAGS_MISCOM_FLAG_SHIFT (1U)
/*! MISCOM_FLAG - MISCOMPARE fault flag
* 0b0..A MISCOMPARE fault has not occurred
* 0b1..A MISCOMPARE fault has occurred
*/
#define CDOG_FLAGS_MISCOM_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_MISCOM_FLAG_SHIFT)) & CDOG_FLAGS_MISCOM_FLAG_MASK)
#define CDOG_FLAGS_SEQ_FLAG_MASK (0x4U)
#define CDOG_FLAGS_SEQ_FLAG_SHIFT (2U)
/*! SEQ_FLAG - SEQUENCE fault flag
* 0b0..A SEQUENCE fault has not occurred
* 0b1..A SEQUENCE fault has occurred
*/
#define CDOG_FLAGS_SEQ_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_SEQ_FLAG_SHIFT)) & CDOG_FLAGS_SEQ_FLAG_MASK)
#define CDOG_FLAGS_CNT_FLAG_MASK (0x8U)
#define CDOG_FLAGS_CNT_FLAG_SHIFT (3U)
/*! CNT_FLAG - CONTROL fault flag
* 0b0..A CONTROL fault has not occurred
* 0b1..A CONTROL fault has occurred
*/
#define CDOG_FLAGS_CNT_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_CNT_FLAG_SHIFT)) & CDOG_FLAGS_CNT_FLAG_MASK)
#define CDOG_FLAGS_STATE_FLAG_MASK (0x10U)
#define CDOG_FLAGS_STATE_FLAG_SHIFT (4U)
/*! STATE_FLAG - STATE fault flag
* 0b0..A STATE fault has not occurred
* 0b1..A STATE fault has occurred
*/
#define CDOG_FLAGS_STATE_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_STATE_FLAG_SHIFT)) & CDOG_FLAGS_STATE_FLAG_MASK)
#define CDOG_FLAGS_ADDR_FLAG_MASK (0x20U)
#define CDOG_FLAGS_ADDR_FLAG_SHIFT (5U)
/*! ADDR_FLAG - ADDRESS fault flag
* 0b0..An ADDRESS fault has not occurred
* 0b1..An ADDRESS fault has occurred
*/
#define CDOG_FLAGS_ADDR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_ADDR_FLAG_SHIFT)) & CDOG_FLAGS_ADDR_FLAG_MASK)
#define CDOG_FLAGS_POR_FLAG_MASK (0x10000U)
#define CDOG_FLAGS_POR_FLAG_SHIFT (16U)
/*! POR_FLAG - Power-on reset flag
* 0b0..A Power-on reset event has not occurred
* 0b1..A Power-on reset event has occurred
*/
#define CDOG_FLAGS_POR_FLAG(x) (((uint32_t)(((uint32_t)(x)) << CDOG_FLAGS_POR_FLAG_SHIFT)) & CDOG_FLAGS_POR_FLAG_MASK)
/*! @} */
/*! @name PERSISTENT - Persistent Data Storage */
/*! @{ */
#define CDOG_PERSISTENT_PERSIS_MASK (0xFFFFFFFFU)
#define CDOG_PERSISTENT_PERSIS_SHIFT (0U)
/*! PERSIS - Persistent Storage
*/
#define CDOG_PERSISTENT_PERSIS(x) (((uint32_t)(((uint32_t)(x)) << CDOG_PERSISTENT_PERSIS_SHIFT)) & CDOG_PERSISTENT_PERSIS_MASK)
/*! @} */
/*! @name START - START Command */
/*! @{ */
#define CDOG_START_STRT_MASK (0xFFFFFFFFU)
#define CDOG_START_STRT_SHIFT (0U)
/*! STRT - Start command
*/
#define CDOG_START_STRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_START_STRT_SHIFT)) & CDOG_START_STRT_MASK)
/*! @} */
/*! @name STOP - STOP Command */
/*! @{ */
#define CDOG_STOP_STP_MASK (0xFFFFFFFFU)
#define CDOG_STOP_STP_SHIFT (0U)
/*! STP - Stop command
*/
#define CDOG_STOP_STP(x) (((uint32_t)(((uint32_t)(x)) << CDOG_STOP_STP_SHIFT)) & CDOG_STOP_STP_MASK)
/*! @} */
/*! @name RESTART - RESTART Command */
/*! @{ */
#define CDOG_RESTART_RSTRT_MASK (0xFFFFFFFFU)
#define CDOG_RESTART_RSTRT_SHIFT (0U)
/*! RSTRT - Restart command
*/
#define CDOG_RESTART_RSTRT(x) (((uint32_t)(((uint32_t)(x)) << CDOG_RESTART_RSTRT_SHIFT)) & CDOG_RESTART_RSTRT_MASK)
/*! @} */
/*! @name ADD - ADD Command */
/*! @{ */
#define CDOG_ADD_AD_MASK (0xFFFFFFFFU)
#define CDOG_ADD_AD_SHIFT (0U)
/*! AD - ADD Write Value
*/
#define CDOG_ADD_AD(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD_AD_SHIFT)) & CDOG_ADD_AD_MASK)
/*! @} */
/*! @name ADD1 - ADD1 Command */
/*! @{ */
#define CDOG_ADD1_AD1_MASK (0xFFFFFFFFU)
#define CDOG_ADD1_AD1_SHIFT (0U)
/*! AD1 - ADD 1
*/
#define CDOG_ADD1_AD1(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD1_AD1_SHIFT)) & CDOG_ADD1_AD1_MASK)
/*! @} */
/*! @name ADD16 - ADD16 Command */
/*! @{ */
#define CDOG_ADD16_AD16_MASK (0xFFFFFFFFU)
#define CDOG_ADD16_AD16_SHIFT (0U)
/*! AD16 - ADD 16
*/
#define CDOG_ADD16_AD16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD16_AD16_SHIFT)) & CDOG_ADD16_AD16_MASK)
/*! @} */
/*! @name ADD256 - ADD256 Command */
/*! @{ */
#define CDOG_ADD256_AD256_MASK (0xFFFFFFFFU)
#define CDOG_ADD256_AD256_SHIFT (0U)
/*! AD256 - ADD 256
*/
#define CDOG_ADD256_AD256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_ADD256_AD256_SHIFT)) & CDOG_ADD256_AD256_MASK)
/*! @} */
/*! @name SUB - SUB Command */
/*! @{ */
#define CDOG_SUB_S0B_MASK (0xFFFFFFFFU)
#define CDOG_SUB_S0B_SHIFT (0U)
/*! S0B - Subtract Write Value
*/
#define CDOG_SUB_S0B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB_S0B_SHIFT)) & CDOG_SUB_S0B_MASK)
/*! @} */
/*! @name SUB1 - SUB1 Command */
/*! @{ */
#define CDOG_SUB1_S1B_MASK (0xFFFFFFFFU)
#define CDOG_SUB1_S1B_SHIFT (0U)
/*! S1B - Subtract 1
*/
#define CDOG_SUB1_S1B(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB1_S1B_SHIFT)) & CDOG_SUB1_S1B_MASK)
/*! @} */
/*! @name SUB16 - SUB16 Command */
/*! @{ */
#define CDOG_SUB16_SB16_MASK (0xFFFFFFFFU)
#define CDOG_SUB16_SB16_SHIFT (0U)
/*! SB16 - Subtract 16
*/
#define CDOG_SUB16_SB16(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB16_SB16_SHIFT)) & CDOG_SUB16_SB16_MASK)
/*! @} */
/*! @name SUB256 - SUB256 Command */
/*! @{ */
#define CDOG_SUB256_SB256_MASK (0xFFFFFFFFU)
#define CDOG_SUB256_SB256_SHIFT (0U)
/*! SB256 - Subtract 256
*/
#define CDOG_SUB256_SB256(x) (((uint32_t)(((uint32_t)(x)) << CDOG_SUB256_SB256_SHIFT)) & CDOG_SUB256_SB256_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CDOG_Register_Masks */
/* CDOG - Peripheral instance base addresses */
/** Peripheral CDOG base address */
#define CDOG_BASE (0x41900000u)
/** Peripheral CDOG base pointer */
#define CDOG ((CDOG_Type *)CDOG_BASE)
/** Array initializer of CDOG peripheral base addresses */
#define CDOG_BASE_ADDRS { CDOG_BASE }
/** Array initializer of CDOG peripheral base pointers */
#define CDOG_BASE_PTRS { CDOG }
/*!
* @}
*/ /* end of group CDOG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CMP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
* @{
*/
/** CMP - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t C0; /**< CMP Control Register 0, offset: 0x8 */
__IO uint32_t C1; /**< CMP Control Register 1, offset: 0xC */
__IO uint32_t C2; /**< CMP Control Register 2, offset: 0x10 */
__IO uint32_t C3; /**< CMP Control Register 3, offset: 0x14 */
} CMP_Type;
/* ----------------------------------------------------------------------------
-- CMP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CMP_Register_Masks CMP Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
/*! @{ */
#define CMP_VERID_FEATURE_MASK (0xFFFFU)
#define CMP_VERID_FEATURE_SHIFT (0U)
/*! FEATURE - Feature Specification Number. This read only filed returns the feature set number.
*/
#define CMP_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_FEATURE_SHIFT)) & CMP_VERID_FEATURE_MASK)
#define CMP_VERID_MINOR_MASK (0xFF0000U)
#define CMP_VERID_MINOR_SHIFT (16U)
/*! MINOR - Minor Version Number. This read only field returns the minor version number for the module specification.
*/
#define CMP_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MINOR_SHIFT)) & CMP_VERID_MINOR_MASK)
#define CMP_VERID_MAJOR_MASK (0xFF000000U)
#define CMP_VERID_MAJOR_SHIFT (24U)
/*! MAJOR - Major Version Number. This read only field returns the major version number for the module specification.
*/
#define CMP_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << CMP_VERID_MAJOR_SHIFT)) & CMP_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define CMP_PARAM_PARAM_MASK (0xFFFFFFFFU)
#define CMP_PARAM_PARAM_SHIFT (0U)
/*! PARAM - Parameter Registers. This read only filed returns the feature parameters implemented along with the Version ID register.
*/
#define CMP_PARAM_PARAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_PARAM_PARAM_SHIFT)) & CMP_PARAM_PARAM_MASK)
/*! @} */
/*! @name C0 - CMP Control Register 0 */
/*! @{ */
#define CMP_C0_HYSTCTR_MASK (0x3U)
#define CMP_C0_HYSTCTR_SHIFT (0U)
/*! HYSTCTR - Comparator hard block hysteresis control. See chip data sheet to get the actual hystersis value with each level
* 0b00..The hard block output has level 0 hysteresis internally.
* 0b01..The hard block output has level 1 hysteresis internally.
* 0b10..The hard block output has level 2 hysteresis internally.
* 0b11..The hard block output has level 3 hysteresis internally.
*/
#define CMP_C0_HYSTCTR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_HYSTCTR_SHIFT)) & CMP_C0_HYSTCTR_MASK)
#define CMP_C0_FILTER_CNT_MASK (0x70U)
#define CMP_C0_FILTER_CNT_SHIFT (4U)
/*! FILTER_CNT - Filter Sample Count
* 0b000..Filter is disabled. If SE = 1, then COUT is a logic zero (this is not a legal state, and is not recommended). If SE = 0, COUT = COUTA.
* 0b001..1 consecutive sample must agree (comparator output is simply sampled).
* 0b010..2 consecutive samples must agree.
* 0b011..3 consecutive samples must agree.
* 0b100..4 consecutive samples must agree.
* 0b101..5 consecutive samples must agree.
* 0b110..6 consecutive samples must agree.
* 0b111..7 consecutive samples must agree.
*/
#define CMP_C0_FILTER_CNT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FILTER_CNT_SHIFT)) & CMP_C0_FILTER_CNT_MASK)
#define CMP_C0_EN_MASK (0x100U)
#define CMP_C0_EN_SHIFT (8U)
/*! EN - Comparator Module Enable
* 0b0..Analog Comparator is disabled.
* 0b1..Analog Comparator is enabled.
*/
#define CMP_C0_EN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_EN_SHIFT)) & CMP_C0_EN_MASK)
#define CMP_C0_OPE_MASK (0x200U)
#define CMP_C0_OPE_SHIFT (9U)
/*! OPE - Comparator Output Pin Enable
* 0b0..When OPE is 0, the comparator output (after window/filter settings dependent on software configuration) is not available to a packaged pin.
* 0b1..When OPE is 1, and if the software has configured the comparator to own a packaged pin, the comparator is available in a packaged pin.
*/
#define CMP_C0_OPE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_OPE_SHIFT)) & CMP_C0_OPE_MASK)
#define CMP_C0_COS_MASK (0x400U)
#define CMP_C0_COS_SHIFT (10U)
/*! COS - Comparator Output Select
* 0b0..Set CMPO to equal COUT (filtered comparator output).
* 0b1..Set CMPO to equal COUTA (unfiltered comparator output).
*/
#define CMP_C0_COS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COS_SHIFT)) & CMP_C0_COS_MASK)
#define CMP_C0_INVT_MASK (0x800U)
#define CMP_C0_INVT_SHIFT (11U)
/*! INVT - Comparator invert
* 0b0..Does not invert the comparator output.
* 0b1..Inverts the comparator output.
*/
#define CMP_C0_INVT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_INVT_SHIFT)) & CMP_C0_INVT_MASK)
#define CMP_C0_PMODE_MASK (0x1000U)
#define CMP_C0_PMODE_SHIFT (12U)
/*! PMODE - Power Mode Select
* 0b0..Low Speed (LS) comparison mode is selected.
* 0b1..High Speed (HS) comparison mode is selected.
*/
#define CMP_C0_PMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_PMODE_SHIFT)) & CMP_C0_PMODE_MASK)
#define CMP_C0_WE_MASK (0x4000U)
#define CMP_C0_WE_SHIFT (14U)
/*! WE - Windowing Enable
* 0b0..Windowing mode is not selected.
* 0b1..Windowing mode is selected.
*/
#define CMP_C0_WE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_WE_SHIFT)) & CMP_C0_WE_MASK)
#define CMP_C0_SE_MASK (0x8000U)
#define CMP_C0_SE_SHIFT (15U)
/*! SE - Sample Enable
* 0b0..Sampling mode is not selected.
* 0b1..Sampling mode is selected.
*/
#define CMP_C0_SE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_SE_SHIFT)) & CMP_C0_SE_MASK)
#define CMP_C0_FPR_MASK (0xFF0000U)
#define CMP_C0_FPR_SHIFT (16U)
/*! FPR - Filter Sample Period
*/
#define CMP_C0_FPR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_FPR_SHIFT)) & CMP_C0_FPR_MASK)
#define CMP_C0_COUT_MASK (0x1000000U)
#define CMP_C0_COUT_SHIFT (24U)
/*! COUT - Analog Comparator Output
*/
#define CMP_C0_COUT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_COUT_SHIFT)) & CMP_C0_COUT_MASK)
#define CMP_C0_CFF_MASK (0x2000000U)
#define CMP_C0_CFF_SHIFT (25U)
/*! CFF - Analog Comparator Flag Falling
* 0b0..A falling edge has not been detected on COUT.
* 0b1..A falling edge on COUT has occurred.
*/
#define CMP_C0_CFF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFF_SHIFT)) & CMP_C0_CFF_MASK)
#define CMP_C0_CFR_MASK (0x4000000U)
#define CMP_C0_CFR_SHIFT (26U)
/*! CFR - Analog Comparator Flag Rising
* 0b0..A rising edge has not been detected on COUT.
* 0b1..A rising edge on COUT has occurred.
*/
#define CMP_C0_CFR(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_CFR_SHIFT)) & CMP_C0_CFR_MASK)
#define CMP_C0_IEF_MASK (0x8000000U)
#define CMP_C0_IEF_SHIFT (27U)
/*! IEF - Comparator Interrupt Enable Falling
* 0b0..Interrupt is disabled.
* 0b1..Interrupt is enabled.
*/
#define CMP_C0_IEF(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IEF_SHIFT)) & CMP_C0_IEF_MASK)
#define CMP_C0_IER_MASK (0x10000000U)
#define CMP_C0_IER_SHIFT (28U)
/*! IER - Comparator Interrupt Enable Rising
* 0b0..Interrupt is disabled.
* 0b1..Interrupt is enabled.
*/
#define CMP_C0_IER(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_IER_SHIFT)) & CMP_C0_IER_MASK)
#define CMP_C0_DMAEN_MASK (0x40000000U)
#define CMP_C0_DMAEN_SHIFT (30U)
/*! DMAEN - DMA Enable
* 0b0..DMA is disabled.
* 0b1..DMA is enabled.
*/
#define CMP_C0_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_DMAEN_SHIFT)) & CMP_C0_DMAEN_MASK)
#define CMP_C0_LINKEN_MASK (0x80000000U)
#define CMP_C0_LINKEN_SHIFT (31U)
/*! LINKEN - CMP to DAC link enable.
* 0b0..CMP to DAC link is disabled
* 0b1..CMP to DAC link is enabled.
*/
#define CMP_C0_LINKEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C0_LINKEN_SHIFT)) & CMP_C0_LINKEN_MASK)
/*! @} */
/*! @name C1 - CMP Control Register 1 */
/*! @{ */
#define CMP_C1_VOSEL_MASK (0xFFU)
#define CMP_C1_VOSEL_SHIFT (0U)
/*! VOSEL - DAC Output Voltage Select
*/
#define CMP_C1_VOSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VOSEL_SHIFT)) & CMP_C1_VOSEL_MASK)
#define CMP_C1_DMODE_MASK (0x100U)
#define CMP_C1_DMODE_SHIFT (8U)
/*! DMODE - DAC Mode Selection
* 0b0..DAC is selected to work in low speed and low power mode.
* 0b1..DAC is selected to work in high speed high power mode.
*/
#define CMP_C1_DMODE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DMODE_SHIFT)) & CMP_C1_DMODE_MASK)
#define CMP_C1_VRSEL_MASK (0x200U)
#define CMP_C1_VRSEL_SHIFT (9U)
/*! VRSEL - Supply Voltage Reference Source Select
* 0b0..Vin1 is selected as resistor ladder network supply reference Vin. Vin1 is from internal PMC.
* 0b1..Vin2 is selected as resistor ladder network supply reference Vin. Vin2 is from PAD.
*/
#define CMP_C1_VRSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_VRSEL_SHIFT)) & CMP_C1_VRSEL_MASK)
#define CMP_C1_DACEN_MASK (0x400U)
#define CMP_C1_DACEN_SHIFT (10U)
/*! DACEN - DAC Enable
* 0b0..DAC is disabled.
* 0b1..DAC is enabled.
*/
#define CMP_C1_DACEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_DACEN_SHIFT)) & CMP_C1_DACEN_MASK)
#define CMP_C1_CHN0_MASK (0x10000U)
#define CMP_C1_CHN0_SHIFT (16U)
/*! CHN0 - Channel 0 input enable
*/
#define CMP_C1_CHN0(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN0_SHIFT)) & CMP_C1_CHN0_MASK)
#define CMP_C1_CHN1_MASK (0x20000U)
#define CMP_C1_CHN1_SHIFT (17U)
/*! CHN1 - Channel 1 input enable
*/
#define CMP_C1_CHN1(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN1_SHIFT)) & CMP_C1_CHN1_MASK)
#define CMP_C1_CHN2_MASK (0x40000U)
#define CMP_C1_CHN2_SHIFT (18U)
/*! CHN2 - Channel 2 input enable
*/
#define CMP_C1_CHN2(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN2_SHIFT)) & CMP_C1_CHN2_MASK)
#define CMP_C1_CHN3_MASK (0x80000U)
#define CMP_C1_CHN3_SHIFT (19U)
/*! CHN3 - Channel 3 input enable
*/
#define CMP_C1_CHN3(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN3_SHIFT)) & CMP_C1_CHN3_MASK)
#define CMP_C1_CHN4_MASK (0x100000U)
#define CMP_C1_CHN4_SHIFT (20U)
/*! CHN4 - Channel 4 input enable
*/
#define CMP_C1_CHN4(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN4_SHIFT)) & CMP_C1_CHN4_MASK)
#define CMP_C1_CHN5_MASK (0x200000U)
#define CMP_C1_CHN5_SHIFT (21U)
/*! CHN5 - Channel 5 input enable
*/
#define CMP_C1_CHN5(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_CHN5_SHIFT)) & CMP_C1_CHN5_MASK)
#define CMP_C1_MSEL_MASK (0x7000000U)
#define CMP_C1_MSEL_SHIFT (24U)
/*! MSEL - Minus Input MUX Control
* 0b000..Internal Negative Input 0 for Minus Channel -- Internal Minus Input
* 0b001..External Input 1 for Minus Channel -- Reference Input 0
* 0b010..External Input 2 for Minus Channel -- Reference Input 1
* 0b011..External Input 3 for Minus Channel -- Reference Input 2
* 0b100..External Input 4 for Minus Channel -- Reference Input 3
* 0b101..External Input 5 for Minus Channel -- Reference Input 4
* 0b110..External Input 6 for Minus Channel -- Reference Input 5
* 0b111..Internal 8b DAC output
*/
#define CMP_C1_MSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_MSEL_SHIFT)) & CMP_C1_MSEL_MASK)
#define CMP_C1_PSEL_MASK (0x70000000U)
#define CMP_C1_PSEL_SHIFT (28U)
/*! PSEL - Plus Input MUX Control
* 0b000..Internal Positive Input 0 for Plus Channel -- Internal Plus Input
* 0b001..External Input 1 for Plus Channel -- Reference Input 0
* 0b010..External Input 2 for Plus Channel -- Reference Input 1
* 0b011..External Input 3 for Plus Channel -- Reference Input 2
* 0b100..External Input 4 for Plus Channel -- Reference Input 3
* 0b101..External Input 5 for Plus Channel -- Reference Input 4
* 0b110..External Input 6 for Plus Channel -- Reference Input 5
* 0b111..Internal 8b DAC output
*/
#define CMP_C1_PSEL(x) (((uint32_t)(((uint32_t)(x)) << CMP_C1_PSEL_SHIFT)) & CMP_C1_PSEL_MASK)
/*! @} */
/*! @name C2 - CMP Control Register 2 */
/*! @{ */
#define CMP_C2_ACOn_MASK (0x3FU)
#define CMP_C2_ACOn_SHIFT (0U)
/*! ACOn - ACOn
*/
#define CMP_C2_ACOn(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_ACOn_SHIFT)) & CMP_C2_ACOn_MASK)
#define CMP_C2_INITMOD_MASK (0x3F00U)
#define CMP_C2_INITMOD_SHIFT (8U)
/*! INITMOD - Comparator and DAC initialization delay modulus.
*/
#define CMP_C2_INITMOD(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_INITMOD_SHIFT)) & CMP_C2_INITMOD_MASK)
#define CMP_C2_NSAM_MASK (0xC000U)
#define CMP_C2_NSAM_SHIFT (14U)
/*! NSAM - Number of sample clocks
* 0b00..The comparison result is sampled as soon as the active channel is scanned in one round-robin clock.
* 0b01..The sampling takes place 1 round-robin clock cycle after the next cycle of the round-robin clock.
* 0b10..The sampling takes place 2 round-robin clock cycles after the next cycle of the round-robin clock.
* 0b11..The sampling takes place 3 round-robin clock cycles after the next cycle of the round-robin clock.
*/
#define CMP_C2_NSAM(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_NSAM_SHIFT)) & CMP_C2_NSAM_MASK)
#define CMP_C2_CH0F_MASK (0x10000U)
#define CMP_C2_CH0F_SHIFT (16U)
/*! CH0F - CH0F
*/
#define CMP_C2_CH0F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH0F_SHIFT)) & CMP_C2_CH0F_MASK)
#define CMP_C2_CH1F_MASK (0x20000U)
#define CMP_C2_CH1F_SHIFT (17U)
/*! CH1F - CH1F
*/
#define CMP_C2_CH1F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH1F_SHIFT)) & CMP_C2_CH1F_MASK)
#define CMP_C2_CH2F_MASK (0x40000U)
#define CMP_C2_CH2F_SHIFT (18U)
/*! CH2F - CH2F
*/
#define CMP_C2_CH2F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH2F_SHIFT)) & CMP_C2_CH2F_MASK)
#define CMP_C2_CH3F_MASK (0x80000U)
#define CMP_C2_CH3F_SHIFT (19U)
/*! CH3F - CH3F
*/
#define CMP_C2_CH3F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH3F_SHIFT)) & CMP_C2_CH3F_MASK)
#define CMP_C2_CH4F_MASK (0x100000U)
#define CMP_C2_CH4F_SHIFT (20U)
/*! CH4F - CH4F
*/
#define CMP_C2_CH4F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH4F_SHIFT)) & CMP_C2_CH4F_MASK)
#define CMP_C2_CH5F_MASK (0x200000U)
#define CMP_C2_CH5F_SHIFT (21U)
/*! CH5F - CH5F
*/
#define CMP_C2_CH5F(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_CH5F_SHIFT)) & CMP_C2_CH5F_MASK)
#define CMP_C2_FXMXCH_MASK (0xE000000U)
#define CMP_C2_FXMXCH_SHIFT (25U)
/*! FXMXCH - Fixed channel selection
* 0b000..External Reference Input 0 is selected as the fixed reference input for the fixed mux port.
* 0b001..External Reference Input 1 is selected as the fixed reference input for the fixed mux port.
* 0b010..External Reference Input 2 is selected as the fixed reference input for the fixed mux port.
* 0b011..External Reference Input 3 is selected as the fixed reference input for the fixed mux port.
* 0b100..External Reference Input 4 is selected as the fixed reference input for the fixed mux port.
* 0b101..External Reference Input 5 is selected as the fixed reference input for the fixed mux port.
* 0b110..Reserved.
* 0b111..The 8bit DAC is selected as the fixed reference input for the fixed mux port.
*/
#define CMP_C2_FXMXCH(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMXCH_SHIFT)) & CMP_C2_FXMXCH_MASK)
#define CMP_C2_FXMP_MASK (0x20000000U)
#define CMP_C2_FXMP_SHIFT (29U)
/*! FXMP - Fixed MUX Port
* 0b0..The Plus port is fixed. Only the inputs to the Minus port are swept in each round.
* 0b1..The Minus port is fixed. Only the inputs to the Plus port are swept in each round.
*/
#define CMP_C2_FXMP(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_FXMP_SHIFT)) & CMP_C2_FXMP_MASK)
#define CMP_C2_RRIE_MASK (0x40000000U)
#define CMP_C2_RRIE_SHIFT (30U)
/*! RRIE - Round-Robin interrupt enable
* 0b0..The round-robin interrupt is disabled.
* 0b1..The round-robin interrupt is enabled when a comparison result changes from the last sample.
*/
#define CMP_C2_RRIE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C2_RRIE_SHIFT)) & CMP_C2_RRIE_MASK)
/*! @} */
/*! @name C3 - CMP Control Register 3 */
/*! @{ */
#define CMP_C3_ACPH2TC_MASK (0x70U)
#define CMP_C3_ACPH2TC_SHIFT (4U)
/*! ACPH2TC - Analog Comparator Phase2 Timing Control.
* 0b000..Phase2 active time in one sampling period equals to T
* 0b001..Phase2 active time in one sampling period equals to 2*T
* 0b010..Phase2 active time in one sampling period equals to 4*T
* 0b011..Phase2 active time in one sampling period equals to 8*T
* 0b100..Phase2 active time in one sampling period equals to 16*T
* 0b101..Phase2 active time in one sampling period equals to 32*T
* 0b110..Phase2 active time in one sampling period equals to 64*T
* 0b111..Phase2 active time in one sampling period equals to 16*T
*/
#define CMP_C3_ACPH2TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH2TC_SHIFT)) & CMP_C3_ACPH2TC_MASK)
#define CMP_C3_ACPH1TC_MASK (0x700U)
#define CMP_C3_ACPH1TC_SHIFT (8U)
/*! ACPH1TC - Analog Comparator Phase1 Timing Control.
* 0b000..Phase1 active time in one sampling period equals to T
* 0b001..Phase1 active time in one sampling period equals to 2*T
* 0b010..Phase1 active time in one sampling period equals to 4*T
* 0b011..Phase1 active time in one sampling period equals to 8*T
* 0b100..Phase1 active time in one sampling period equals to T
* 0b101..Phase1 active time in one sampling period equals to T
* 0b110..Phase1 active time in one sampling period equals to T
* 0b111..Phase1 active time in one sampling period equals to 0
*/
#define CMP_C3_ACPH1TC(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACPH1TC_SHIFT)) & CMP_C3_ACPH1TC_MASK)
#define CMP_C3_ACSAT_MASK (0x7000U)
#define CMP_C3_ACSAT_SHIFT (12U)
/*! ACSAT - Analog Comparator Sampling Time control.
* 0b000..The sampling time equals to T
* 0b001..The sampling time equasl to 2*T
* 0b010..The sampling time equasl to 4*T
* 0b011..The sampling time equasl to 8*T
* 0b100..The sampling time equasl to 16*T
* 0b101..The sampling time equasl to 32*T
* 0b110..The sampling time equasl to 64*T
* 0b111..The sampling time equasl to 256*T
*/
#define CMP_C3_ACSAT(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_ACSAT_SHIFT)) & CMP_C3_ACSAT_MASK)
#define CMP_C3_DMCS_MASK (0x10000U)
#define CMP_C3_DMCS_SHIFT (16U)
/*! DMCS - Discrete Mode Clock Selection
* 0b0..Slow clock is selected for the timing generation.
* 0b1..Fast clock is selected for the timing generation.
*/
#define CMP_C3_DMCS(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_DMCS_SHIFT)) & CMP_C3_DMCS_MASK)
#define CMP_C3_RDIVE_MASK (0x100000U)
#define CMP_C3_RDIVE_SHIFT (20U)
/*! RDIVE - Resistor Divider Enable
* 0b0..The resistor is not enabled even when either NCHEN or PCHEN is set to1 but the actual input is in the range of 0 - 1.8v.
* 0b1..The resistor is enabled because the inputs are above 1.8v.
*/
#define CMP_C3_RDIVE(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_RDIVE_SHIFT)) & CMP_C3_RDIVE_MASK)
#define CMP_C3_NCHCTEN_MASK (0x1000000U)
#define CMP_C3_NCHCTEN_SHIFT (24U)
/*! NCHCTEN - Negative Channel Continuous Mode Enable.
* 0b0..Negative channel is in Discrete Mode and special timing needs to be configured.
* 0b1..Negative channel is in Continuous Mode and no special timing is requried.
*/
#define CMP_C3_NCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_NCHCTEN_SHIFT)) & CMP_C3_NCHCTEN_MASK)
#define CMP_C3_PCHCTEN_MASK (0x10000000U)
#define CMP_C3_PCHCTEN_SHIFT (28U)
/*! PCHCTEN - Positive Channel Continuous Mode Enable.
* 0b0..Positive channel is in Discrete Mode and special timing needs to be configured.
* 0b1..Positive channel is in Continuous Mode and no special timing is requried.
*/
#define CMP_C3_PCHCTEN(x) (((uint32_t)(((uint32_t)(x)) << CMP_C3_PCHCTEN_SHIFT)) & CMP_C3_PCHCTEN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group CMP_Register_Masks */
/* CMP - Peripheral instance base addresses */
/** Peripheral CMP1 base address */
#define CMP1_BASE (0x401A4000u)
/** Peripheral CMP1 base pointer */
#define CMP1 ((CMP_Type *)CMP1_BASE)
/** Peripheral CMP2 base address */
#define CMP2_BASE (0x401A8000u)
/** Peripheral CMP2 base pointer */
#define CMP2 ((CMP_Type *)CMP2_BASE)
/** Peripheral CMP3 base address */
#define CMP3_BASE (0x401AC000u)
/** Peripheral CMP3 base pointer */
#define CMP3 ((CMP_Type *)CMP3_BASE)
/** Peripheral CMP4 base address */
#define CMP4_BASE (0x401B0000u)
/** Peripheral CMP4 base pointer */
#define CMP4 ((CMP_Type *)CMP4_BASE)
/** Array initializer of CMP peripheral base addresses */
#define CMP_BASE_ADDRS { 0u, CMP1_BASE, CMP2_BASE, CMP3_BASE, CMP4_BASE }
/** Array initializer of CMP peripheral base pointers */
#define CMP_BASE_PTRS { (CMP_Type *)0u, CMP1, CMP2, CMP3, CMP4 }
/** Interrupt vectors for the CMP peripheral type */
#define CMP_IRQS { NotAvail_IRQn, ACMP1_IRQn, ACMP2_IRQn, ACMP3_IRQn, ACMP4_IRQn }
/*!
* @}
*/ /* end of group CMP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- CSI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup CSI_Peripheral_Access_Layer CSI Peripheral Access Layer
* @{
*/
/** CSI - Register Layout Typedef */
typedef struct {
__IO uint32_t CR1; /**< CSI Control Register 1, offset: 0x0 */
__IO uint32_t CR2; /**< CSI Control Register 2, offset: 0x4 */
__IO uint32_t CR3; /**< CSI Control Register 3, offset: 0x8 */
__I uint32_t STATFIFO; /**< CSI Statistic FIFO Register, offset: 0xC */
__I uint32_t RFIFO; /**< CSI RX FIFO Register, offset: 0x10 */
__IO uint32_t RXCNT; /**< CSI RX Count Register, offset: 0x14 */
__IO uint32_t SR; /**< CSI Status Register, offset: 0x18 */
uint8_t RESERVED_0[4];
__IO uint32_t DMASA_STATFIFO; /**< CSI DMA Start Address Register - for STATFIFO, offset: 0x20 */
__IO uint32_t DMATS_STATFIFO; /**< CSI DMA Transfer Size Register - for STATFIFO, offset: 0x24 */
__IO uint32_t DMASA_FB1; /**< CSI DMA Start Address Register - for Frame Buffer1, offset: 0x28 */
__IO uint32_t DMASA_FB2; /**< CSI DMA Transfer Size Register - for Frame Buffer2, offset: 0x2C */
__IO uint32_t FBUF_PARA; /**< CSI Frame Buffer Parameter Register, offset: 0x30 */
__IO uint32_t IMAG_PARA; /**< CSI Image Parameter Register, offset: 0x34 */
uint8_t RESERVED_1[16];
__IO uint32_t CR18; /**< CSI Control Register 18, offset: 0x48 */
__IO uint32_t CR19; /**< CSI Control Register 19, offset: 0x4C */
__IO uint32_t CR20; /**< CSI Control Register 20, offset: 0x50 */
__IO uint32_t CR[256]; /**< CSI Control Register, array offset: 0x54, array step: 0x4 */
} CSI_Type;
/* ----------------------------------------------------------------------------
-- CSI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup CSI_Register_Masks CSI Register Masks
* @{
*/
/*! @name CR1 - CSI Control Register 1 */
/*! @{ */
#define CSI_CR1_PIXEL_BIT_MASK (0x1U)
#define CSI_CR1_PIXEL_BIT_SHIFT (0U)
/*! PIXEL_BIT
* 0b0..8-bit data for each pixel
* 0b1..10-bit data for each pixel
*/
#define CSI_CR1_PIXEL_BIT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PIXEL_BIT_SHIFT)) & CSI_CR1_PIXEL_BIT_MASK)
#define CSI_CR1_REDGE_MASK (0x2U)
#define CSI_CR1_REDGE_SHIFT (1U)
/*! REDGE
* 0b0..Pixel data is latched at the falling edge of CSI_PIXCLK
* 0b1..Pixel data is latched at the rising edge of CSI_PIXCLK
*/
#define CSI_CR1_REDGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_REDGE_SHIFT)) & CSI_CR1_REDGE_MASK)
#define CSI_CR1_INV_PCLK_MASK (0x4U)
#define CSI_CR1_INV_PCLK_SHIFT (2U)
/*! INV_PCLK
* 0b0..CSI_PIXCLK is directly applied to internal circuitry
* 0b1..CSI_PIXCLK is inverted before applied to internal circuitry
*/
#define CSI_CR1_INV_PCLK(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_PCLK_SHIFT)) & CSI_CR1_INV_PCLK_MASK)
#define CSI_CR1_INV_DATA_MASK (0x8U)
#define CSI_CR1_INV_DATA_SHIFT (3U)
/*! INV_DATA
* 0b0..CSI_D[7:0] data lines are directly applied to internal circuitry
* 0b1..CSI_D[7:0] data lines are inverted before applied to internal circuitry
*/
#define CSI_CR1_INV_DATA(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_INV_DATA_SHIFT)) & CSI_CR1_INV_DATA_MASK)
#define CSI_CR1_GCLK_MODE_MASK (0x10U)
#define CSI_CR1_GCLK_MODE_SHIFT (4U)
/*! GCLK_MODE
* 0b0..Non-gated clock mode. All incoming pixel clocks are valid. HSYNC is ignored.
* 0b1..Gated clock mode. Pixel clock signal is valid only when HSYNC is active.
*/
#define CSI_CR1_GCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_GCLK_MODE_SHIFT)) & CSI_CR1_GCLK_MODE_MASK)
#define CSI_CR1_CLR_RXFIFO_MASK (0x20U)
#define CSI_CR1_CLR_RXFIFO_SHIFT (5U)
#define CSI_CR1_CLR_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_RXFIFO_SHIFT)) & CSI_CR1_CLR_RXFIFO_MASK)
#define CSI_CR1_CLR_STATFIFO_MASK (0x40U)
#define CSI_CR1_CLR_STATFIFO_SHIFT (6U)
#define CSI_CR1_CLR_STATFIFO(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CLR_STATFIFO_SHIFT)) & CSI_CR1_CLR_STATFIFO_MASK)
#define CSI_CR1_PACK_DIR_MASK (0x80U)
#define CSI_CR1_PACK_DIR_SHIFT (7U)
/*! PACK_DIR
* 0b0..Pack from LSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x44332211 in RX FIFO. For
* stat data, 0xAAAA, 0xBBBB, it will appear as 0xBBBBAAAA in STAT FIFO.
* 0b1..Pack from MSB first. For image data, 0x11, 0x22, 0x33, 0x44, it will appear as 0x11223344 in RX FIFO. For
* stat data, 0xAAAA, 0xBBBB, it will appear as 0xAAAABBBB in STAT FIFO.
*/
#define CSI_CR1_PACK_DIR(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_PACK_DIR_SHIFT)) & CSI_CR1_PACK_DIR_MASK)
#define CSI_CR1_FCC_MASK (0x100U)
#define CSI_CR1_FCC_SHIFT (8U)
/*! FCC
* 0b0..Asynchronous FIFO clear is selected.
* 0b1..Synchronous FIFO clear is selected.
*/
#define CSI_CR1_FCC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FCC_SHIFT)) & CSI_CR1_FCC_MASK)
#define CSI_CR1_CCIR_EN_MASK (0x400U)
#define CSI_CR1_CCIR_EN_SHIFT (10U)
/*! CCIR_EN
* 0b0..Traditional interface is selected.
* 0b1..BT.656 interface is selected.
*/
#define CSI_CR1_CCIR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_CCIR_EN_SHIFT)) & CSI_CR1_CCIR_EN_MASK)
#define CSI_CR1_HSYNC_POL_MASK (0x800U)
#define CSI_CR1_HSYNC_POL_SHIFT (11U)
/*! HSYNC_POL
* 0b0..HSYNC is active low
* 0b1..HSYNC is active high
*/
#define CSI_CR1_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HSYNC_POL_SHIFT)) & CSI_CR1_HSYNC_POL_MASK)
#define CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK (0x1000U)
#define CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT (12U)
/*! HISTOGRAM_CALC_DONE_IE
* 0b0..Histogram done interrupt disable
* 0b1..Histogram done interrupt enable
*/
#define CSI_CR1_HISTOGRAM_CALC_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT)) & CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK)
#define CSI_CR1_SOF_INTEN_MASK (0x10000U)
#define CSI_CR1_SOF_INTEN_SHIFT (16U)
/*! SOF_INTEN
* 0b0..SOF interrupt disable
* 0b1..SOF interrupt enable
*/
#define CSI_CR1_SOF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_INTEN_SHIFT)) & CSI_CR1_SOF_INTEN_MASK)
#define CSI_CR1_SOF_POL_MASK (0x20000U)
#define CSI_CR1_SOF_POL_SHIFT (17U)
/*! SOF_POL
* 0b0..SOF interrupt is generated on SOF falling edge
* 0b1..SOF interrupt is generated on SOF rising edge
*/
#define CSI_CR1_SOF_POL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SOF_POL_SHIFT)) & CSI_CR1_SOF_POL_MASK)
#define CSI_CR1_RXFF_INTEN_MASK (0x40000U)
#define CSI_CR1_RXFF_INTEN_SHIFT (18U)
/*! RXFF_INTEN
* 0b0..RxFIFO full interrupt disable
* 0b1..RxFIFO full interrupt enable
*/
#define CSI_CR1_RXFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RXFF_INTEN_SHIFT)) & CSI_CR1_RXFF_INTEN_MASK)
#define CSI_CR1_FB1_DMA_DONE_INTEN_MASK (0x80000U)
#define CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT (19U)
/*! FB1_DMA_DONE_INTEN
* 0b0..Frame Buffer1 DMA Transfer Done interrupt disable
* 0b1..Frame Buffer1 DMA Transfer Done interrupt enable
*/
#define CSI_CR1_FB1_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB1_DMA_DONE_INTEN_MASK)
#define CSI_CR1_FB2_DMA_DONE_INTEN_MASK (0x100000U)
#define CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT (20U)
/*! FB2_DMA_DONE_INTEN
* 0b0..Frame Buffer2 DMA Transfer Done interrupt disable
* 0b1..Frame Buffer2 DMA Transfer Done interrupt enable
*/
#define CSI_CR1_FB2_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_FB2_DMA_DONE_INTEN_MASK)
#define CSI_CR1_STATFF_INTEN_MASK (0x200000U)
#define CSI_CR1_STATFF_INTEN_SHIFT (21U)
/*! STATFF_INTEN
* 0b0..STATFIFO full interrupt disable
* 0b1..STATFIFO full interrupt enable
*/
#define CSI_CR1_STATFF_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_STATFF_INTEN_SHIFT)) & CSI_CR1_STATFF_INTEN_MASK)
#define CSI_CR1_SFF_DMA_DONE_INTEN_MASK (0x400000U)
#define CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT (22U)
/*! SFF_DMA_DONE_INTEN
* 0b0..STATFIFO DMA Transfer Done interrupt disable
* 0b1..STATFIFO DMA Transfer Done interrupt enable
*/
#define CSI_CR1_SFF_DMA_DONE_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT)) & CSI_CR1_SFF_DMA_DONE_INTEN_MASK)
#define CSI_CR1_RF_OR_INTEN_MASK (0x1000000U)
#define CSI_CR1_RF_OR_INTEN_SHIFT (24U)
/*! RF_OR_INTEN
* 0b0..RxFIFO overrun interrupt is disabled
* 0b1..RxFIFO overrun interrupt is enabled
*/
#define CSI_CR1_RF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_RF_OR_INTEN_SHIFT)) & CSI_CR1_RF_OR_INTEN_MASK)
#define CSI_CR1_SF_OR_INTEN_MASK (0x2000000U)
#define CSI_CR1_SF_OR_INTEN_SHIFT (25U)
/*! SF_OR_INTEN
* 0b0..STATFIFO overrun interrupt is disabled
* 0b1..STATFIFO overrun interrupt is enabled
*/
#define CSI_CR1_SF_OR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SF_OR_INTEN_SHIFT)) & CSI_CR1_SF_OR_INTEN_MASK)
#define CSI_CR1_COF_INT_EN_MASK (0x4000000U)
#define CSI_CR1_COF_INT_EN_SHIFT (26U)
/*! COF_INT_EN
* 0b0..COF interrupt is disabled
* 0b1..COF interrupt is enabled
*/
#define CSI_CR1_COF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_COF_INT_EN_SHIFT)) & CSI_CR1_COF_INT_EN_MASK)
#define CSI_CR1_VIDEO_MODE_MASK (0x8000000U)
#define CSI_CR1_VIDEO_MODE_SHIFT (27U)
/*! VIDEO_MODE
* 0b0..Progressive mode is selected
* 0b1..Interlace mode is selected
*/
#define CSI_CR1_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_VIDEO_MODE_SHIFT)) & CSI_CR1_VIDEO_MODE_MASK)
#define CSI_CR1_EOF_INT_EN_MASK (0x20000000U)
#define CSI_CR1_EOF_INT_EN_SHIFT (29U)
/*! EOF_INT_EN
* 0b0..EOF interrupt is disabled.
* 0b1..EOF interrupt is generated when RX count value is reached.
*/
#define CSI_CR1_EOF_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EOF_INT_EN_SHIFT)) & CSI_CR1_EOF_INT_EN_MASK)
#define CSI_CR1_EXT_VSYNC_MASK (0x40000000U)
#define CSI_CR1_EXT_VSYNC_SHIFT (30U)
/*! EXT_VSYNC
* 0b0..Internal VSYNC mode
* 0b1..External VSYNC mode
*/
#define CSI_CR1_EXT_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_EXT_VSYNC_SHIFT)) & CSI_CR1_EXT_VSYNC_MASK)
#define CSI_CR1_SWAP16_EN_MASK (0x80000000U)
#define CSI_CR1_SWAP16_EN_SHIFT (31U)
/*! SWAP16_EN
* 0b0..Disable swapping
* 0b1..Enable swapping
*/
#define CSI_CR1_SWAP16_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR1_SWAP16_EN_SHIFT)) & CSI_CR1_SWAP16_EN_MASK)
/*! @} */
/*! @name CR2 - CSI Control Register 2 */
/*! @{ */
#define CSI_CR2_HSC_MASK (0xFFU)
#define CSI_CR2_HSC_SHIFT (0U)
/*! HSC
* 0b00000000-0b11111111..Number of pixels to skip minus 1
*/
#define CSI_CR2_HSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_HSC_SHIFT)) & CSI_CR2_HSC_MASK)
#define CSI_CR2_VSC_MASK (0xFF00U)
#define CSI_CR2_VSC_SHIFT (8U)
/*! VSC
* 0b00000000-0b11111111..Number of rows to skip minus 1
*/
#define CSI_CR2_VSC(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_VSC_SHIFT)) & CSI_CR2_VSC_MASK)
#define CSI_CR2_LVRM_MASK (0x70000U)
#define CSI_CR2_LVRM_SHIFT (16U)
/*! LVRM
* 0b000..512 x 384
* 0b001..448 x 336
* 0b010..384 x 288
* 0b011..384 x 256
* 0b100..320 x 240
* 0b101..288 x 216
* 0b110..400 x 300
*/
#define CSI_CR2_LVRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_LVRM_SHIFT)) & CSI_CR2_LVRM_MASK)
#define CSI_CR2_BTS_MASK (0x180000U)
#define CSI_CR2_BTS_SHIFT (19U)
/*! BTS
* 0b00..GR
* 0b01..RG
* 0b10..BG
* 0b11..GB
*/
#define CSI_CR2_BTS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_BTS_SHIFT)) & CSI_CR2_BTS_MASK)
#define CSI_CR2_SCE_MASK (0x800000U)
#define CSI_CR2_SCE_SHIFT (23U)
/*! SCE
* 0b0..Skip count disable
* 0b1..Skip count enable
*/
#define CSI_CR2_SCE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_SCE_SHIFT)) & CSI_CR2_SCE_MASK)
#define CSI_CR2_AFS_MASK (0x3000000U)
#define CSI_CR2_AFS_SHIFT (24U)
/*! AFS
* 0b00..Abs Diff on consecutive green pixels
* 0b01..Abs Diff on every third green pixels
* 0b1x..Abs Diff on every four green pixels
*/
#define CSI_CR2_AFS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_AFS_SHIFT)) & CSI_CR2_AFS_MASK)
#define CSI_CR2_DRM_MASK (0x4000000U)
#define CSI_CR2_DRM_SHIFT (26U)
/*! DRM
* 0b0..Stats grid of 8 x 6
* 0b1..Stats grid of 8 x 12
*/
#define CSI_CR2_DRM(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DRM_SHIFT)) & CSI_CR2_DRM_MASK)
#define CSI_CR2_DMA_BURST_TYPE_SFF_MASK (0x30000000U)
#define CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT (28U)
/*! DMA_BURST_TYPE_SFF
* 0bx0..INCR8
* 0b01..INCR4
* 0b11..INCR16
*/
#define CSI_CR2_DMA_BURST_TYPE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_SFF_MASK)
#define CSI_CR2_DMA_BURST_TYPE_RFF_MASK (0xC0000000U)
#define CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT (30U)
/*! DMA_BURST_TYPE_RFF
* 0bx0..INCR8
* 0b01..INCR4
* 0b11..INCR16
*/
#define CSI_CR2_DMA_BURST_TYPE_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT)) & CSI_CR2_DMA_BURST_TYPE_RFF_MASK)
/*! @} */
/*! @name CR3 - CSI Control Register 3 */
/*! @{ */
#define CSI_CR3_ECC_AUTO_EN_MASK (0x1U)
#define CSI_CR3_ECC_AUTO_EN_SHIFT (0U)
/*! ECC_AUTO_EN
* 0b0..Auto Error correction is disabled.
* 0b1..Auto Error correction is enabled.
*/
#define CSI_CR3_ECC_AUTO_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_AUTO_EN_SHIFT)) & CSI_CR3_ECC_AUTO_EN_MASK)
#define CSI_CR3_ECC_INT_EN_MASK (0x2U)
#define CSI_CR3_ECC_INT_EN_SHIFT (1U)
/*! ECC_INT_EN
* 0b0..No interrupt is generated when error is detected. Only the status bit ECC_INT is set.
* 0b1..Interrupt is generated when error is detected.
*/
#define CSI_CR3_ECC_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ECC_INT_EN_SHIFT)) & CSI_CR3_ECC_INT_EN_MASK)
#define CSI_CR3_ZERO_PACK_EN_MASK (0x4U)
#define CSI_CR3_ZERO_PACK_EN_SHIFT (2U)
/*! ZERO_PACK_EN
* 0b0..Zero packing disabled
* 0b1..Zero packing enabled
*/
#define CSI_CR3_ZERO_PACK_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_ZERO_PACK_EN_SHIFT)) & CSI_CR3_ZERO_PACK_EN_MASK)
#define CSI_CR3_SENSOR_16BITS_MASK (0x8U)
#define CSI_CR3_SENSOR_16BITS_SHIFT (3U)
/*! SENSOR_16BITS
* 0b0..Only one 8-bit sensor is connected.
* 0b1..One 16-bit sensor is connected.
*/
#define CSI_CR3_SENSOR_16BITS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_SENSOR_16BITS_SHIFT)) & CSI_CR3_SENSOR_16BITS_MASK)
#define CSI_CR3_RxFF_LEVEL_MASK (0x70U)
#define CSI_CR3_RxFF_LEVEL_SHIFT (4U)
/*! RxFF_LEVEL
* 0b000..4 Double words
* 0b001..8 Double words
* 0b010..16 Double words
* 0b011..24 Double words
* 0b100..32 Double words
* 0b101..48 Double words
* 0b110..64 Double words
* 0b111..96 Double words
*/
#define CSI_CR3_RxFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_RxFF_LEVEL_SHIFT)) & CSI_CR3_RxFF_LEVEL_MASK)
#define CSI_CR3_HRESP_ERR_EN_MASK (0x80U)
#define CSI_CR3_HRESP_ERR_EN_SHIFT (7U)
/*! HRESP_ERR_EN
* 0b0..Disable hresponse error interrupt
* 0b1..Enable hresponse error interrupt
*/
#define CSI_CR3_HRESP_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_HRESP_ERR_EN_SHIFT)) & CSI_CR3_HRESP_ERR_EN_MASK)
#define CSI_CR3_STATFF_LEVEL_MASK (0x700U)
#define CSI_CR3_STATFF_LEVEL_SHIFT (8U)
/*! STATFF_LEVEL
* 0b000..4 Double words
* 0b001..8 Double words
* 0b010..12 Double words
* 0b011..16 Double words
* 0b100..24 Double words
* 0b101..32 Double words
* 0b110..48 Double words
* 0b111..64 Double words
*/
#define CSI_CR3_STATFF_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_STATFF_LEVEL_SHIFT)) & CSI_CR3_STATFF_LEVEL_MASK)
#define CSI_CR3_DMA_REQ_EN_SFF_MASK (0x800U)
#define CSI_CR3_DMA_REQ_EN_SFF_SHIFT (11U)
/*! DMA_REQ_EN_SFF
* 0b0..Disable the dma request
* 0b1..Enable the dma request
*/
#define CSI_CR3_DMA_REQ_EN_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_SFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_SFF_MASK)
#define CSI_CR3_DMA_REQ_EN_RFF_MASK (0x1000U)
#define CSI_CR3_DMA_REQ_EN_RFF_SHIFT (12U)
/*! DMA_REQ_EN_RFF
* 0b0..Disable the dma request
* 0b1..Enable the dma request
*/
#define CSI_CR3_DMA_REQ_EN_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REQ_EN_RFF_SHIFT)) & CSI_CR3_DMA_REQ_EN_RFF_MASK)
#define CSI_CR3_DMA_REFLASH_SFF_MASK (0x2000U)
#define CSI_CR3_DMA_REFLASH_SFF_SHIFT (13U)
/*! DMA_REFLASH_SFF
* 0b0..No reflashing
* 0b1..Reflash the embedded DMA controller
*/
#define CSI_CR3_DMA_REFLASH_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_SFF_SHIFT)) & CSI_CR3_DMA_REFLASH_SFF_MASK)
#define CSI_CR3_DMA_REFLASH_RFF_MASK (0x4000U)
#define CSI_CR3_DMA_REFLASH_RFF_SHIFT (14U)
/*! DMA_REFLASH_RFF
* 0b0..No reflashing
* 0b1..Reflash the embedded DMA controller
*/
#define CSI_CR3_DMA_REFLASH_RFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_DMA_REFLASH_RFF_SHIFT)) & CSI_CR3_DMA_REFLASH_RFF_MASK)
#define CSI_CR3_FRMCNT_RST_MASK (0x8000U)
#define CSI_CR3_FRMCNT_RST_SHIFT (15U)
/*! FRMCNT_RST
* 0b0..Do not reset
* 0b1..Reset frame counter immediately
*/
#define CSI_CR3_FRMCNT_RST(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_RST_SHIFT)) & CSI_CR3_FRMCNT_RST_MASK)
#define CSI_CR3_FRMCNT_MASK (0xFFFF0000U)
#define CSI_CR3_FRMCNT_SHIFT (16U)
#define CSI_CR3_FRMCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR3_FRMCNT_SHIFT)) & CSI_CR3_FRMCNT_MASK)
/*! @} */
/*! @name STATFIFO - CSI Statistic FIFO Register */
/*! @{ */
#define CSI_STATFIFO_STAT_MASK (0xFFFFFFFFU)
#define CSI_STATFIFO_STAT_SHIFT (0U)
#define CSI_STATFIFO_STAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_STATFIFO_STAT_SHIFT)) & CSI_STATFIFO_STAT_MASK)
/*! @} */
/*! @name RFIFO - CSI RX FIFO Register */
/*! @{ */
#define CSI_RFIFO_IMAGE_MASK (0xFFFFFFFFU)
#define CSI_RFIFO_IMAGE_SHIFT (0U)
#define CSI_RFIFO_IMAGE(x) (((uint32_t)(((uint32_t)(x)) << CSI_RFIFO_IMAGE_SHIFT)) & CSI_RFIFO_IMAGE_MASK)
/*! @} */
/*! @name RXCNT - CSI RX Count Register */
/*! @{ */
#define CSI_RXCNT_RXCNT_MASK (0x3FFFFFU)
#define CSI_RXCNT_RXCNT_SHIFT (0U)
#define CSI_RXCNT_RXCNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_RXCNT_RXCNT_SHIFT)) & CSI_RXCNT_RXCNT_MASK)
/*! @} */
/*! @name SR - CSI Status Register */
/*! @{ */
#define CSI_SR_DRDY_MASK (0x1U)
#define CSI_SR_DRDY_SHIFT (0U)
/*! DRDY
* 0b0..No data (word) is ready
* 0b1..At least 1 datum (word) is ready in RXFIFO.
*/
#define CSI_SR_DRDY(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DRDY_SHIFT)) & CSI_SR_DRDY_MASK)
#define CSI_SR_ECC_INT_MASK (0x2U)
#define CSI_SR_ECC_INT_SHIFT (1U)
/*! ECC_INT
* 0b0..No error detected
* 0b1..Error is detected in BT.656 coding
*/
#define CSI_SR_ECC_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_ECC_INT_SHIFT)) & CSI_SR_ECC_INT_MASK)
#define CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK (0x4U)
#define CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT (2U)
/*! HISTOGRAM_CALC_DONE_INT
* 0b0..Histogram calculation is not finished
* 0b1..Histogram calculation is done and driver can access the PIXEL_COUNTERS(CSI_CSICR21~CSI_CSICR276) to get the gray level
*/
#define CSI_SR_HISTOGRAM_CALC_DONE_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT)) & CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK)
#define CSI_SR_HRESP_ERR_INT_MASK (0x80U)
#define CSI_SR_HRESP_ERR_INT_SHIFT (7U)
/*! HRESP_ERR_INT
* 0b0..No hresponse error.
* 0b1..Hresponse error is detected.
*/
#define CSI_SR_HRESP_ERR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_HRESP_ERR_INT_SHIFT)) & CSI_SR_HRESP_ERR_INT_MASK)
#define CSI_SR_COF_INT_MASK (0x2000U)
#define CSI_SR_COF_INT_SHIFT (13U)
/*! COF_INT
* 0b0..Video field has no change.
* 0b1..Change of video field is detected.
*/
#define CSI_SR_COF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_COF_INT_SHIFT)) & CSI_SR_COF_INT_MASK)
#define CSI_SR_F1_INT_MASK (0x4000U)
#define CSI_SR_F1_INT_SHIFT (14U)
/*! F1_INT
* 0b0..Field 1 of video is not detected.
* 0b1..Field 1 of video is about to start.
*/
#define CSI_SR_F1_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_F1_INT_SHIFT)) & CSI_SR_F1_INT_MASK)
#define CSI_SR_F2_INT_MASK (0x8000U)
#define CSI_SR_F2_INT_SHIFT (15U)
/*! F2_INT
* 0b0..Field 2 of video is not detected
* 0b1..Field 2 of video is about to start
*/
#define CSI_SR_F2_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_F2_INT_SHIFT)) & CSI_SR_F2_INT_MASK)
#define CSI_SR_SOF_INT_MASK (0x10000U)
#define CSI_SR_SOF_INT_SHIFT (16U)
/*! SOF_INT
* 0b0..SOF is not detected.
* 0b1..SOF is detected.
*/
#define CSI_SR_SOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_SOF_INT_SHIFT)) & CSI_SR_SOF_INT_MASK)
#define CSI_SR_EOF_INT_MASK (0x20000U)
#define CSI_SR_EOF_INT_SHIFT (17U)
/*! EOF_INT
* 0b0..EOF is not detected.
* 0b1..EOF is detected.
*/
#define CSI_SR_EOF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_EOF_INT_SHIFT)) & CSI_SR_EOF_INT_MASK)
#define CSI_SR_RxFF_INT_MASK (0x40000U)
#define CSI_SR_RxFF_INT_SHIFT (18U)
/*! RxFF_INT
* 0b0..RxFIFO is not full.
* 0b1..RxFIFO is full.
*/
#define CSI_SR_RxFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_RxFF_INT_SHIFT)) & CSI_SR_RxFF_INT_MASK)
#define CSI_SR_DMA_TSF_DONE_FB1_MASK (0x80000U)
#define CSI_SR_DMA_TSF_DONE_FB1_SHIFT (19U)
/*! DMA_TSF_DONE_FB1
* 0b0..DMA transfer is not completed.
* 0b1..DMA transfer is completed.
*/
#define CSI_SR_DMA_TSF_DONE_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB1_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB1_MASK)
#define CSI_SR_DMA_TSF_DONE_FB2_MASK (0x100000U)
#define CSI_SR_DMA_TSF_DONE_FB2_SHIFT (20U)
/*! DMA_TSF_DONE_FB2
* 0b0..DMA transfer is not completed.
* 0b1..DMA transfer is completed.
*/
#define CSI_SR_DMA_TSF_DONE_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_FB2_SHIFT)) & CSI_SR_DMA_TSF_DONE_FB2_MASK)
#define CSI_SR_STATFF_INT_MASK (0x200000U)
#define CSI_SR_STATFF_INT_SHIFT (21U)
/*! STATFF_INT
* 0b0..STATFIFO is not full.
* 0b1..STATFIFO is full.
*/
#define CSI_SR_STATFF_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_STATFF_INT_SHIFT)) & CSI_SR_STATFF_INT_MASK)
#define CSI_SR_DMA_TSF_DONE_SFF_MASK (0x400000U)
#define CSI_SR_DMA_TSF_DONE_SFF_SHIFT (22U)
/*! DMA_TSF_DONE_SFF
* 0b0..DMA transfer is not completed.
* 0b1..DMA transfer is completed.
*/
#define CSI_SR_DMA_TSF_DONE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_TSF_DONE_SFF_SHIFT)) & CSI_SR_DMA_TSF_DONE_SFF_MASK)
#define CSI_SR_RF_OR_INT_MASK (0x1000000U)
#define CSI_SR_RF_OR_INT_SHIFT (24U)
/*! RF_OR_INT
* 0b0..RXFIFO has not overflowed.
* 0b1..RXFIFO has overflowed.
*/
#define CSI_SR_RF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_RF_OR_INT_SHIFT)) & CSI_SR_RF_OR_INT_MASK)
#define CSI_SR_SF_OR_INT_MASK (0x2000000U)
#define CSI_SR_SF_OR_INT_SHIFT (25U)
/*! SF_OR_INT
* 0b0..STATFIFO has not overflowed.
* 0b1..STATFIFO has overflowed.
*/
#define CSI_SR_SF_OR_INT(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_SF_OR_INT_SHIFT)) & CSI_SR_SF_OR_INT_MASK)
#define CSI_SR_DMA_FIELD1_DONE_MASK (0x4000000U)
#define CSI_SR_DMA_FIELD1_DONE_SHIFT (26U)
#define CSI_SR_DMA_FIELD1_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD1_DONE_SHIFT)) & CSI_SR_DMA_FIELD1_DONE_MASK)
#define CSI_SR_DMA_FIELD0_DONE_MASK (0x8000000U)
#define CSI_SR_DMA_FIELD0_DONE_SHIFT (27U)
#define CSI_SR_DMA_FIELD0_DONE(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_DMA_FIELD0_DONE_SHIFT)) & CSI_SR_DMA_FIELD0_DONE_MASK)
#define CSI_SR_BASEADDR_CHHANGE_ERROR_MASK (0x10000000U)
#define CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT (28U)
#define CSI_SR_BASEADDR_CHHANGE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT)) & CSI_SR_BASEADDR_CHHANGE_ERROR_MASK)
/*! @} */
/*! @name DMASA_STATFIFO - CSI DMA Start Address Register - for STATFIFO */
/*! @{ */
#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK (0xFFFFFFFCU)
#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT (2U)
#define CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT)) & CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK)
/*! @} */
/*! @name DMATS_STATFIFO - CSI DMA Transfer Size Register - for STATFIFO */
/*! @{ */
#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK (0xFFFFFFFFU)
#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT (0U)
#define CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT)) & CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK)
/*! @} */
/*! @name DMASA_FB1 - CSI DMA Start Address Register - for Frame Buffer1 */
/*! @{ */
#define CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK (0xFFFFFFFCU)
#define CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT (2U)
#define CSI_DMASA_FB1_DMA_START_ADDR_FB1(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT)) & CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK)
/*! @} */
/*! @name DMASA_FB2 - CSI DMA Transfer Size Register - for Frame Buffer2 */
/*! @{ */
#define CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK (0xFFFFFFFCU)
#define CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT (2U)
#define CSI_DMASA_FB2_DMA_START_ADDR_FB2(x) (((uint32_t)(((uint32_t)(x)) << CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT)) & CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK)
/*! @} */
/*! @name FBUF_PARA - CSI Frame Buffer Parameter Register */
/*! @{ */
#define CSI_FBUF_PARA_FBUF_STRIDE_MASK (0xFFFFU)
#define CSI_FBUF_PARA_FBUF_STRIDE_SHIFT (0U)
#define CSI_FBUF_PARA_FBUF_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_FBUF_STRIDE_SHIFT)) & CSI_FBUF_PARA_FBUF_STRIDE_MASK)
#define CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK (0xFFFF0000U)
#define CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT (16U)
#define CSI_FBUF_PARA_DEINTERLACE_STRIDE(x) (((uint32_t)(((uint32_t)(x)) << CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT)) & CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK)
/*! @} */
/*! @name IMAG_PARA - CSI Image Parameter Register */
/*! @{ */
#define CSI_IMAG_PARA_IMAGE_HEIGHT_MASK (0xFFFFU)
#define CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT (0U)
#define CSI_IMAG_PARA_IMAGE_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT)) & CSI_IMAG_PARA_IMAGE_HEIGHT_MASK)
#define CSI_IMAG_PARA_IMAGE_WIDTH_MASK (0xFFFF0000U)
#define CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT (16U)
#define CSI_IMAG_PARA_IMAGE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT)) & CSI_IMAG_PARA_IMAGE_WIDTH_MASK)
/*! @} */
/*! @name CR18 - CSI Control Register 18 */
/*! @{ */
#define CSI_CR18_NTSC_EN_MASK (0x1U)
#define CSI_CR18_NTSC_EN_SHIFT (0U)
/*! NTSC_EN
* 0b0..PAL
* 0b1..NTSC
*/
#define CSI_CR18_NTSC_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_NTSC_EN_SHIFT)) & CSI_CR18_NTSC_EN_MASK)
#define CSI_CR18_TVDECODER_IN_EN_MASK (0x2U)
#define CSI_CR18_TVDECODER_IN_EN_SHIFT (1U)
#define CSI_CR18_TVDECODER_IN_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_TVDECODER_IN_EN_SHIFT)) & CSI_CR18_TVDECODER_IN_EN_MASK)
#define CSI_CR18_DEINTERLACE_EN_MASK (0x4U)
#define CSI_CR18_DEINTERLACE_EN_SHIFT (2U)
/*! DEINTERLACE_EN
* 0b0..Deinterlace disabled
* 0b1..Deinterlace enabled
*/
#define CSI_CR18_DEINTERLACE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DEINTERLACE_EN_SHIFT)) & CSI_CR18_DEINTERLACE_EN_MASK)
#define CSI_CR18_PARALLEL24_EN_MASK (0x8U)
#define CSI_CR18_PARALLEL24_EN_SHIFT (3U)
/*! PARALLEL24_EN
* 0b0..Input is disabled
* 0b1..Input is enabled
*/
#define CSI_CR18_PARALLEL24_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_PARALLEL24_EN_SHIFT)) & CSI_CR18_PARALLEL24_EN_MASK)
#define CSI_CR18_BASEADDR_SWITCH_EN_MASK (0x10U)
#define CSI_CR18_BASEADDR_SWITCH_EN_SHIFT (4U)
#define CSI_CR18_BASEADDR_SWITCH_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_EN_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_EN_MASK)
#define CSI_CR18_BASEADDR_SWITCH_SEL_MASK (0x20U)
#define CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT (5U)
/*! BASEADDR_SWITCH_SEL
* 0b0..Switching base address at the edge of the vsync
* 0b1..Switching base address at the edge of the first data of each frame
*/
#define CSI_CR18_BASEADDR_SWITCH_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT)) & CSI_CR18_BASEADDR_SWITCH_SEL_MASK)
#define CSI_CR18_FIELD0_DONE_IE_MASK (0x40U)
#define CSI_CR18_FIELD0_DONE_IE_SHIFT (6U)
/*! FIELD0_DONE_IE
* 0b0..Interrupt disabled
* 0b1..Interrupt enabled
*/
#define CSI_CR18_FIELD0_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_FIELD0_DONE_IE_SHIFT)) & CSI_CR18_FIELD0_DONE_IE_MASK)
#define CSI_CR18_DMA_FIELD1_DONE_IE_MASK (0x80U)
#define CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT (7U)
/*! DMA_FIELD1_DONE_IE
* 0b0..Interrupt disabled
* 0b1..Interrupt enabled
*/
#define CSI_CR18_DMA_FIELD1_DONE_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT)) & CSI_CR18_DMA_FIELD1_DONE_IE_MASK)
#define CSI_CR18_LAST_DMA_REQ_SEL_MASK (0x100U)
#define CSI_CR18_LAST_DMA_REQ_SEL_SHIFT (8U)
/*! LAST_DMA_REQ_SEL
* 0b0..fifo_full_level
* 0b1..hburst_length
*/
#define CSI_CR18_LAST_DMA_REQ_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LAST_DMA_REQ_SEL_SHIFT)) & CSI_CR18_LAST_DMA_REQ_SEL_MASK)
#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK (0x200U)
#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT (9U)
/*! BASEADDR_CHANGE_ERROR_IE
* 0b0..Interrupt disabled
* 0b1..Interrupt enabled
*/
#define CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT)) & CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK)
#define CSI_CR18_RGB888A_FORMAT_SEL_MASK (0x400U)
#define CSI_CR18_RGB888A_FORMAT_SEL_SHIFT (10U)
/*! RGB888A_FORMAT_SEL
* 0b0..{8'h0, data[23:0]}
* 0b1..{data[23:0], 8'h0}
*/
#define CSI_CR18_RGB888A_FORMAT_SEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_RGB888A_FORMAT_SEL_SHIFT)) & CSI_CR18_RGB888A_FORMAT_SEL_MASK)
#define CSI_CR18_AHB_HPROT_MASK (0xF000U)
#define CSI_CR18_AHB_HPROT_SHIFT (12U)
#define CSI_CR18_AHB_HPROT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_AHB_HPROT_SHIFT)) & CSI_CR18_AHB_HPROT_MASK)
#define CSI_CR18_MASK_OPTION_MASK (0xC0000U)
#define CSI_CR18_MASK_OPTION_SHIFT (18U)
/*! MASK_OPTION
* 0b00..Writing to memory (OCRAM or external DDR) from first completely frame, when using this option, the CSI_ENABLE should be 1.
* 0b01..Writing to memory when CSI_ENABLE is 1.
* 0b10..Writing to memory from second completely frame, when using this option, the CSI_ENABLE should be 1.
* 0b11..Writing to memory when data comes in, not matter the CSI_ENABLE is 1 or 0.
*/
#define CSI_CR18_MASK_OPTION(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MASK_OPTION_SHIFT)) & CSI_CR18_MASK_OPTION_MASK)
#define CSI_CR18_MIPI_DOUBLE_CMPNT_MASK (0x100000U)
#define CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT (20U)
/*! MIPI_DOUBLE_CMPNT
* 0b0..Single component per clock cycle (half pixel per clock cycle)
* 0b1..Double component per clock cycle (a pixel per clock cycle)
*/
#define CSI_CR18_MIPI_DOUBLE_CMPNT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT)) & CSI_CR18_MIPI_DOUBLE_CMPNT_MASK)
#define CSI_CR18_MIPI_YU_SWAP_MASK (0x200000U)
#define CSI_CR18_MIPI_YU_SWAP_SHIFT (21U)
/*! MIPI_YU_SWAP - It only works in MIPI CSI YUV422 double component mode.
*/
#define CSI_CR18_MIPI_YU_SWAP(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_YU_SWAP_SHIFT)) & CSI_CR18_MIPI_YU_SWAP_MASK)
#define CSI_CR18_DATA_FROM_MIPI_MASK (0x400000U)
#define CSI_CR18_DATA_FROM_MIPI_SHIFT (22U)
/*! DATA_FROM_MIPI
* 0b0..Data from parallel sensor
* 0b1..Data from MIPI
*/
#define CSI_CR18_DATA_FROM_MIPI(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_DATA_FROM_MIPI_SHIFT)) & CSI_CR18_DATA_FROM_MIPI_MASK)
#define CSI_CR18_LINE_STRIDE_EN_MASK (0x1000000U)
#define CSI_CR18_LINE_STRIDE_EN_SHIFT (24U)
#define CSI_CR18_LINE_STRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_LINE_STRIDE_EN_SHIFT)) & CSI_CR18_LINE_STRIDE_EN_MASK)
#define CSI_CR18_MIPI_DATA_FORMAT_MASK (0x7E000000U)
#define CSI_CR18_MIPI_DATA_FORMAT_SHIFT (25U)
/*! MIPI_DATA_FORMAT - Image Data Format
*/
#define CSI_CR18_MIPI_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_MIPI_DATA_FORMAT_SHIFT)) & CSI_CR18_MIPI_DATA_FORMAT_MASK)
#define CSI_CR18_CSI_ENABLE_MASK (0x80000000U)
#define CSI_CR18_CSI_ENABLE_SHIFT (31U)
#define CSI_CR18_CSI_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR18_CSI_ENABLE_SHIFT)) & CSI_CR18_CSI_ENABLE_MASK)
/*! @} */
/*! @name CR19 - CSI Control Register 19 */
/*! @{ */
#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK (0xFFU)
#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT (0U)
#define CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT)) & CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK)
/*! @} */
/*! @name CR20 - CSI Control Register 20 */
/*! @{ */
#define CSI_CR20_THRESHOLD_MASK (0xFFU)
#define CSI_CR20_THRESHOLD_SHIFT (0U)
#define CSI_CR20_THRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_THRESHOLD_SHIFT)) & CSI_CR20_THRESHOLD_MASK)
#define CSI_CR20_BINARY_EN_MASK (0x100U)
#define CSI_CR20_BINARY_EN_SHIFT (8U)
/*! BINARY_EN
* 0b0..Output is Y8 format(8 bits each pixel)
* 0b1..Output is Y1 format(1 bit each pixel)
*/
#define CSI_CR20_BINARY_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BINARY_EN_SHIFT)) & CSI_CR20_BINARY_EN_MASK)
#define CSI_CR20_QR_DATA_FORMAT_MASK (0xE00U)
#define CSI_CR20_QR_DATA_FORMAT_SHIFT (9U)
/*! QR_DATA_FORMAT
* 0b000..YU YV one cycle per 1 pixel input
* 0b001..UY VY one cycle per1 pixel input
* 0b010..Y U Y V two cycles per 1 pixel input
* 0b011..U Y V Y two cycles per 1 pixel input
* 0b100..YUV one cycle per 1 pixel input
* 0b101..Y U V three cycles per 1 pixel input
*/
#define CSI_CR20_QR_DATA_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QR_DATA_FORMAT_SHIFT)) & CSI_CR20_QR_DATA_FORMAT_MASK)
#define CSI_CR20_BIG_END_MASK (0x1000U)
#define CSI_CR20_BIG_END_SHIFT (12U)
/*! BIG_END
* 0b0..The newest (most recent) data will be assigned the lowest position when store to memory.
* 0b1..The newest (most recent) data will be assigned the highest position when store to memory.
*/
#define CSI_CR20_BIG_END(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_BIG_END_SHIFT)) & CSI_CR20_BIG_END_MASK)
#define CSI_CR20_10BIT_NEW_EN_MASK (0x20000000U)
#define CSI_CR20_10BIT_NEW_EN_SHIFT (29U)
/*! 10BIT_NEW_EN
* 0b0..When input 8bits data, it will use the data[9:2]
* 0b1..If input is 10bits data, it will use the data[7:0] (optional)
*/
#define CSI_CR20_10BIT_NEW_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_10BIT_NEW_EN_SHIFT)) & CSI_CR20_10BIT_NEW_EN_MASK)
#define CSI_CR20_HISTOGRAM_EN_MASK (0x40000000U)
#define CSI_CR20_HISTOGRAM_EN_SHIFT (30U)
/*! HISTOGRAM_EN
* 0b0..Histogram disable
* 0b1..Histogram enable
*/
#define CSI_CR20_HISTOGRAM_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_HISTOGRAM_EN_SHIFT)) & CSI_CR20_HISTOGRAM_EN_MASK)
#define CSI_CR20_QRCODE_EN_MASK (0x80000000U)
#define CSI_CR20_QRCODE_EN_SHIFT (31U)
/*! QRCODE_EN
* 0b0..Normal mode
* 0b1..Gray scale mode
*/
#define CSI_CR20_QRCODE_EN(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR20_QRCODE_EN_SHIFT)) & CSI_CR20_QRCODE_EN_MASK)
/*! @} */
/*! @name CR - CSI Control Register */
/*! @{ */
#define CSI_CR_PIXEL_COUNTERS_MASK (0xFFFFFFU)
#define CSI_CR_PIXEL_COUNTERS_SHIFT (0U)
#define CSI_CR_PIXEL_COUNTERS(x) (((uint32_t)(((uint32_t)(x)) << CSI_CR_PIXEL_COUNTERS_SHIFT)) & CSI_CR_PIXEL_COUNTERS_MASK)
/*! @} */
/* The count of CSI_CR */
#define CSI_CR_COUNT (256U)
/*!
* @}
*/ /* end of group CSI_Register_Masks */
/* CSI - Peripheral instance base addresses */
/** Peripheral CSI base address */
#define CSI_BASE (0x40800000u)
/** Peripheral CSI base pointer */
#define CSI ((CSI_Type *)CSI_BASE)
/** Array initializer of CSI peripheral base addresses */
#define CSI_BASE_ADDRS { CSI_BASE }
/** Array initializer of CSI peripheral base pointers */
#define CSI_BASE_PTRS { CSI }
/** Interrupt vectors for the CSI peripheral type */
#define CSI_IRQS { CSI_IRQn }
/* Backward compatibility */
#define CSI_CSICR1_PIXEL_BIT_MASK CSI_CR1_PIXEL_BIT_MASK
#define CSI_CSICR1_PIXEL_BIT_SHIFT CSI_CR1_PIXEL_BIT_SHIFT
#define CSI_CSICR1_PIXEL_BIT(x) CSI_CR1_PIXEL_BIT(x)
#define CSI_CSICR1_REDGE_MASK CSI_CR1_REDGE_MASK
#define CSI_CSICR1_REDGE_SHIFT CSI_CR1_REDGE_SHIFT
#define CSI_CSICR1_REDGE(x) CSI_CR1_REDGE(x)
#define CSI_CSICR1_INV_PCLK_MASK CSI_CR1_INV_PCLK_MASK
#define CSI_CSICR1_INV_PCLK_SHIFT CSI_CR1_INV_PCLK_SHIFT
#define CSI_CSICR1_INV_PCLK(x) CSI_CR1_INV_PCLK(x)
#define CSI_CSICR1_INV_DATA_MASK CSI_CR1_INV_DATA_MASK
#define CSI_CSICR1_INV_DATA_SHIFT CSI_CR1_INV_DATA_SHIFT
#define CSI_CSICR1_INV_DATA(x) CSI_CR1_INV_DATA(x)
#define CSI_CSICR1_GCLK_MODE_MASK CSI_CR1_GCLK_MODE_MASK
#define CSI_CSICR1_GCLK_MODE_SHIFT CSI_CR1_GCLK_MODE_SHIFT
#define CSI_CSICR1_GCLK_MODE(x) CSI_CR1_GCLK_MODE(x)
#define CSI_CSICR1_CLR_RXFIFO_MASK CSI_CR1_CLR_RXFIFO_MASK
#define CSI_CSICR1_CLR_RXFIFO_SHIFT CSI_CR1_CLR_RXFIFO_SHIFT
#define CSI_CSICR1_CLR_RXFIFO(x) CSI_CR1_CLR_RXFIFO(x)
#define CSI_CSICR1_CLR_STATFIFO_MASK CSI_CR1_CLR_STATFIFO_MASK
#define CSI_CSICR1_CLR_STATFIFO_SHIFT CSI_CR1_CLR_STATFIFO_SHIFT
#define CSI_CSICR1_CLR_STATFIFO(x) CSI_CR1_CLR_STATFIFO(x)
#define CSI_CSICR1_PACK_DIR_MASK CSI_CR1_PACK_DIR_MASK
#define CSI_CSICR1_PACK_DIR_SHIFT CSI_CR1_PACK_DIR_SHIFT
#define CSI_CSICR1_PACK_DIR(x) CSI_CR1_PACK_DIR(x)
#define CSI_CSICR1_FCC_MASK CSI_CR1_FCC_MASK
#define CSI_CSICR1_FCC_SHIFT CSI_CR1_FCC_SHIFT
#define CSI_CSICR1_FCC(x) CSI_CR1_FCC(x)
#define CSI_CSICR1_CCIR_EN_MASK CSI_CR1_CCIR_EN_MASK
#define CSI_CSICR1_CCIR_EN_SHIFT CSI_CR1_CCIR_EN_SHIFT
#define CSI_CSICR1_CCIR_EN(x) CSI_CR1_CCIR_EN(x)
#define CSI_CSICR1_HSYNC_POL_MASK CSI_CR1_HSYNC_POL_MASK
#define CSI_CSICR1_HSYNC_POL_SHIFT CSI_CR1_HSYNC_POL_SHIFT
#define CSI_CSICR1_HSYNC_POL(x) CSI_CR1_HSYNC_POL(x)
#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_MASK CSI_CR1_HISTOGRAM_CALC_DONE_IE_MASK
#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE_SHIFT CSI_CR1_HISTOGRAM_CALC_DONE_IE_SHIFT
#define CSI_CSICR1_HISTOGRAM_CALC_DONE_IE(x) CSI_CR1_HISTOGRAM_CALC_DONE_IE(x)
#define CSI_CSICR1_SOF_INTEN_MASK CSI_CR1_SOF_INTEN_MASK
#define CSI_CSICR1_SOF_INTEN_SHIFT CSI_CR1_SOF_INTEN_SHIFT
#define CSI_CSICR1_SOF_INTEN(x) CSI_CR1_SOF_INTEN(x)
#define CSI_CSICR1_SOF_POL_MASK CSI_CR1_SOF_POL_MASK
#define CSI_CSICR1_SOF_POL_SHIFT CSI_CR1_SOF_POL_SHIFT
#define CSI_CSICR1_SOF_POL(x) CSI_CR1_SOF_POL(x)
#define CSI_CSICR1_RXFF_INTEN_MASK CSI_CR1_RXFF_INTEN_MASK
#define CSI_CSICR1_RXFF_INTEN_SHIFT CSI_CR1_RXFF_INTEN_SHIFT
#define CSI_CSICR1_RXFF_INTEN(x) CSI_CR1_RXFF_INTEN(x)
#define CSI_CSICR1_FB1_DMA_DONE_INTEN_MASK CSI_CR1_FB1_DMA_DONE_INTEN_MASK
#define CSI_CSICR1_FB1_DMA_DONE_INTEN_SHIFT CSI_CR1_FB1_DMA_DONE_INTEN_SHIFT
#define CSI_CSICR1_FB1_DMA_DONE_INTEN(x) CSI_CR1_FB1_DMA_DONE_INTEN(x)
#define CSI_CSICR1_FB2_DMA_DONE_INTEN_MASK CSI_CR1_FB2_DMA_DONE_INTEN_MASK
#define CSI_CSICR1_FB2_DMA_DONE_INTEN_SHIFT CSI_CR1_FB2_DMA_DONE_INTEN_SHIFT
#define CSI_CSICR1_FB2_DMA_DONE_INTEN(x) CSI_CR1_FB2_DMA_DONE_INTEN(x)
#define CSI_CSICR1_STATFF_INTEN_MASK CSI_CR1_STATFF_INTEN_MASK
#define CSI_CSICR1_STATFF_INTEN_SHIFT CSI_CR1_STATFF_INTEN_SHIFT
#define CSI_CSICR1_STATFF_INTEN(x) CSI_CR1_STATFF_INTEN(x)
#define CSI_CSICR1_SFF_DMA_DONE_INTEN_MASK CSI_CR1_SFF_DMA_DONE_INTEN_MASK
#define CSI_CSICR1_SFF_DMA_DONE_INTEN_SHIFT CSI_CR1_SFF_DMA_DONE_INTEN_SHIFT
#define CSI_CSICR1_SFF_DMA_DONE_INTEN(x) CSI_CR1_SFF_DMA_DONE_INTEN(x)
#define CSI_CSICR1_RF_OR_INTEN_MASK CSI_CR1_RF_OR_INTEN_MASK
#define CSI_CSICR1_RF_OR_INTEN_SHIFT CSI_CR1_RF_OR_INTEN_SHIFT
#define CSI_CSICR1_RF_OR_INTEN(x) CSI_CR1_RF_OR_INTEN(x)
#define CSI_CSICR1_SF_OR_INTEN_MASK CSI_CR1_SF_OR_INTEN_MASK
#define CSI_CSICR1_SF_OR_INTEN_SHIFT CSI_CR1_SF_OR_INTEN_SHIFT
#define CSI_CSICR1_SF_OR_INTEN(x) CSI_CR1_SF_OR_INTEN(x)
#define CSI_CSICR1_COF_INT_EN_MASK CSI_CR1_COF_INT_EN_MASK
#define CSI_CSICR1_COF_INT_EN_SHIFT CSI_CR1_COF_INT_EN_SHIFT
#define CSI_CSICR1_COF_INT_EN(x) CSI_CR1_COF_INT_EN(x)
#define CSI_CSICR1_VIDEO_MODE_MASK CSI_CR1_VIDEO_MODE_MASK
#define CSI_CSICR1_VIDEO_MODE_SHIFT CSI_CR1_VIDEO_MODE_SHIFT
#define CSI_CSICR1_VIDEO_MODE(x) CSI_CR1_VIDEO_MODE(x)
#define CSI_CSICR1_EOF_INT_EN_MASK CSI_CR1_EOF_INT_EN_MASK
#define CSI_CSICR1_EOF_INT_EN_SHIFT CSI_CR1_EOF_INT_EN_SHIFT
#define CSI_CSICR1_EOF_INT_EN(x) CSI_CR1_EOF_INT_EN(x)
#define CSI_CSICR1_EXT_VSYNC_MASK CSI_CR1_EXT_VSYNC_MASK
#define CSI_CSICR1_EXT_VSYNC_SHIFT CSI_CR1_EXT_VSYNC_SHIFT
#define CSI_CSICR1_EXT_VSYNC(x) CSI_CR1_EXT_VSYNC(x)
#define CSI_CSICR1_SWAP16_EN_MASK CSI_CR1_SWAP16_EN_MASK
#define CSI_CSICR1_SWAP16_EN_SHIFT CSI_CR1_SWAP16_EN_SHIFT
#define CSI_CSICR1_SWAP16_EN(x) CSI_CR1_SWAP16_EN(x)
#define CSI_CSICR2_HSC_MASK CSI_CR2_HSC_MASK
#define CSI_CSICR2_HSC_SHIFT CSI_CR2_HSC_SHIFT
#define CSI_CSICR2_HSC(x) CSI_CR2_HSC(x)
#define CSI_CSICR2_VSC_MASK CSI_CR2_VSC_MASK
#define CSI_CSICR2_VSC_SHIFT CSI_CR2_VSC_SHIFT
#define CSI_CSICR2_VSC(x) CSI_CR2_VSC(x)
#define CSI_CSICR2_LVRM_MASK CSI_CR2_LVRM_MASK
#define CSI_CSICR2_LVRM_SHIFT CSI_CR2_LVRM_SHIFT
#define CSI_CSICR2_LVRM(x) CSI_CR2_LVRM(x)
#define CSI_CSICR2_BTS_MASK CSI_CR2_BTS_MASK
#define CSI_CSICR2_BTS_SHIFT CSI_CR2_BTS_SHIFT
#define CSI_CSICR2_BTS(x) CSI_CR2_BTS(x)
#define CSI_CSICR2_SCE_MASK CSI_CR2_SCE_MASK
#define CSI_CSICR2_SCE_SHIFT CSI_CR2_SCE_SHIFT
#define CSI_CSICR2_SCE(x) CSI_CR2_SCE(x)
#define CSI_CSICR2_AFS_MASK CSI_CR2_AFS_MASK
#define CSI_CSICR2_AFS_SHIFT CSI_CR2_AFS_SHIFT
#define CSI_CSICR2_AFS(x) CSI_CR2_AFS(x)
#define CSI_CSICR2_DRM_MASK CSI_CR2_DRM_MASK
#define CSI_CSICR2_DRM_SHIFT CSI_CR2_DRM_SHIFT
#define CSI_CSICR2_DRM(x) CSI_CR2_DRM(x)
#define CSI_CSICR2_DMA_BURST_TYPE_SFF_MASK CSI_CR2_DMA_BURST_TYPE_SFF_MASK
#define CSI_CSICR2_DMA_BURST_TYPE_SFF_SHIFT CSI_CR2_DMA_BURST_TYPE_SFF_SHIFT
#define CSI_CSICR2_DMA_BURST_TYPE_SFF(x) CSI_CR2_DMA_BURST_TYPE_SFF(x)
#define CSI_CSICR2_DMA_BURST_TYPE_RFF_MASK CSI_CR2_DMA_BURST_TYPE_RFF_MASK
#define CSI_CSICR2_DMA_BURST_TYPE_RFF_SHIFT CSI_CR2_DMA_BURST_TYPE_RFF_SHIFT
#define CSI_CSICR2_DMA_BURST_TYPE_RFF(x) CSI_CR2_DMA_BURST_TYPE_RFF(x)
#define CSI_CSICR3_ECC_AUTO_EN_MASK CSI_CR3_ECC_AUTO_EN_MASK
#define CSI_CSICR3_ECC_AUTO_EN_SHIFT CSI_CR3_ECC_AUTO_EN_SHIFT
#define CSI_CSICR3_ECC_AUTO_EN(x) CSI_CR3_ECC_AUTO_EN(x)
#define CSI_CSICR3_ECC_INT_EN_MASK CSI_CR3_ECC_INT_EN_MASK
#define CSI_CSICR3_ECC_INT_EN_SHIFT CSI_CR3_ECC_INT_EN_SHIFT
#define CSI_CSICR3_ECC_INT_EN(x) CSI_CR3_ECC_INT_EN(x)
#define CSI_CSICR3_ZERO_PACK_EN_MASK CSI_CR3_ZERO_PACK_EN_MASK
#define CSI_CSICR3_ZERO_PACK_EN_SHIFT CSI_CR3_ZERO_PACK_EN_SHIFT
#define CSI_CSICR3_ZERO_PACK_EN(x) CSI_CR3_ZERO_PACK_EN(x)
#define CSI_CSICR3_SENSOR_16BITS_MASK CSI_CR3_SENSOR_16BITS_MASK
#define CSI_CSICR3_SENSOR_16BITS_SHIFT CSI_CR3_SENSOR_16BITS_SHIFT
#define CSI_CSICR3_SENSOR_16BITS(x) CSI_CR3_SENSOR_16BITS(x)
#define CSI_CSICR3_RxFF_LEVEL_MASK CSI_CR3_RxFF_LEVEL_MASK
#define CSI_CSICR3_RxFF_LEVEL_SHIFT CSI_CR3_RxFF_LEVEL_SHIFT
#define CSI_CSICR3_RxFF_LEVEL(x) CSI_CR3_RxFF_LEVEL(x)
#define CSI_CSICR3_HRESP_ERR_EN_MASK CSI_CR3_HRESP_ERR_EN_MASK
#define CSI_CSICR3_HRESP_ERR_EN_SHIFT CSI_CR3_HRESP_ERR_EN_SHIFT
#define CSI_CSICR3_HRESP_ERR_EN(x) CSI_CR3_HRESP_ERR_EN(x)
#define CSI_CSICR3_STATFF_LEVEL_MASK CSI_CR3_STATFF_LEVEL_MASK
#define CSI_CSICR3_STATFF_LEVEL_SHIFT CSI_CR3_STATFF_LEVEL_SHIFT
#define CSI_CSICR3_STATFF_LEVEL(x) CSI_CR3_STATFF_LEVEL(x)
#define CSI_CSICR3_DMA_REQ_EN_SFF_MASK CSI_CR3_DMA_REQ_EN_SFF_MASK
#define CSI_CSICR3_DMA_REQ_EN_SFF_SHIFT CSI_CR3_DMA_REQ_EN_SFF_SHIFT
#define CSI_CSICR3_DMA_REQ_EN_SFF(x) CSI_CR3_DMA_REQ_EN_SFF(x)
#define CSI_CSICR3_DMA_REQ_EN_RFF_MASK CSI_CR3_DMA_REQ_EN_RFF_MASK
#define CSI_CSICR3_DMA_REQ_EN_RFF_SHIFT CSI_CR3_DMA_REQ_EN_RFF_SHIFT
#define CSI_CSICR3_DMA_REQ_EN_RFF(x) CSI_CR3_DMA_REQ_EN_RFF(x)
#define CSI_CSICR3_DMA_REFLASH_SFF_MASK CSI_CR3_DMA_REFLASH_SFF_MASK
#define CSI_CSICR3_DMA_REFLASH_SFF_SHIFT CSI_CR3_DMA_REFLASH_SFF_SHIFT
#define CSI_CSICR3_DMA_REFLASH_SFF(x) CSI_CR3_DMA_REFLASH_SFF(x)
#define CSI_CSICR3_DMA_REFLASH_RFF_MASK CSI_CR3_DMA_REFLASH_RFF_MASK
#define CSI_CSICR3_DMA_REFLASH_RFF_SHIFT CSI_CR3_DMA_REFLASH_RFF_SHIFT
#define CSI_CSICR3_DMA_REFLASH_RFF(x) CSI_CR3_DMA_REFLASH_RFF(x)
#define CSI_CSICR3_FRMCNT_RST_MASK CSI_CR3_FRMCNT_RST_MASK
#define CSI_CSICR3_FRMCNT_RST_SHIFT CSI_CR3_FRMCNT_RST_SHIFT
#define CSI_CSICR3_FRMCNT_RST(x) CSI_CR3_FRMCNT_RST(x)
#define CSI_CSICR3_FRMCNT_MASK CSI_CR3_FRMCNT_MASK
#define CSI_CSICR3_FRMCNT_SHIFT CSI_CR3_FRMCNT_SHIFT
#define CSI_CSICR3_FRMCNT(x) CSI_CR3_FRMCNT(x)
#define CSI_CSISTATFIFO_STAT_MASK CSI_STATFIFO_STAT_MASK
#define CSI_CSISTATFIFO_STAT_SHIFT CSI_STATFIFO_STAT_SHIFT
#define CSI_CSISTATFIFO_STAT(x) CSI_STATFIFO_STAT(x)
#define CSI_CSIRFIFO_IMAGE_MASK CSI_RFIFO_IMAGE_MASK
#define CSI_CSIRFIFO_IMAGE_SHIFT CSI_RFIFO_IMAGE_SHIFT
#define CSI_CSIRFIFO_IMAGE(x) CSI_RFIFO_IMAGE(x)
#define CSI_CSIRXCNT_RXCNT_MASK CSI_RXCNT_RXCNT_MASK
#define CSI_CSIRXCNT_RXCNT_SHIFT CSI_RXCNT_RXCNT_SHIFT
#define CSI_CSIRXCNT_RXCNT(x) CSI_RXCNT_RXCNT(x)
#define CSI_CSISR_DRDY_MASK CSI_SR_DRDY_MASK
#define CSI_CSISR_DRDY_SHIFT CSI_SR_DRDY_SHIFT
#define CSI_CSISR_DRDY(x) CSI_SR_DRDY(x)
#define CSI_CSISR_ECC_INT_MASK CSI_SR_ECC_INT_MASK
#define CSI_CSISR_ECC_INT_SHIFT CSI_SR_ECC_INT_SHIFT
#define CSI_CSISR_ECC_INT(x) CSI_SR_ECC_INT(x)
#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_MASK CSI_SR_HISTOGRAM_CALC_DONE_INT_MASK
#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT_SHIFT CSI_SR_HISTOGRAM_CALC_DONE_INT_SHIFT
#define CSI_CSISR_HISTOGRAM_CALC_DONE_INT(x) CSI_SR_HISTOGRAM_CALC_DONE_INT(x)
#define CSI_CSISR_HRESP_ERR_INT_MASK CSI_SR_HRESP_ERR_INT_MASK
#define CSI_CSISR_HRESP_ERR_INT_SHIFT CSI_SR_HRESP_ERR_INT_SHIFT
#define CSI_CSISR_HRESP_ERR_INT(x) CSI_SR_HRESP_ERR_INT(x)
#define CSI_CSISR_COF_INT_MASK CSI_SR_COF_INT_MASK
#define CSI_CSISR_COF_INT_SHIFT CSI_SR_COF_INT_SHIFT
#define CSI_CSISR_COF_INT(x) CSI_SR_COF_INT(x)
#define CSI_CSISR_F1_INT_MASK CSI_SR_F1_INT_MASK
#define CSI_CSISR_F1_INT_SHIFT CSI_SR_F1_INT_SHIFT
#define CSI_CSISR_F1_INT(x) CSI_SR_F1_INT(x)
#define CSI_CSISR_F2_INT_MASK CSI_SR_F2_INT_MASK
#define CSI_CSISR_F2_INT_SHIFT CSI_SR_F2_INT_SHIFT
#define CSI_CSISR_F2_INT(x) CSI_SR_F2_INT(x)
#define CSI_CSISR_SOF_INT_MASK CSI_SR_SOF_INT_MASK
#define CSI_CSISR_SOF_INT_SHIFT CSI_SR_SOF_INT_SHIFT
#define CSI_CSISR_SOF_INT(x) CSI_SR_SOF_INT(x)
#define CSI_CSISR_EOF_INT_MASK CSI_SR_EOF_INT_MASK
#define CSI_CSISR_EOF_INT_SHIFT CSI_SR_EOF_INT_SHIFT
#define CSI_CSISR_EOF_INT(x) CSI_SR_EOF_INT(x)
#define CSI_CSISR_RxFF_INT_MASK CSI_SR_RxFF_INT_MASK
#define CSI_CSISR_RxFF_INT_SHIFT CSI_SR_RxFF_INT_SHIFT
#define CSI_CSISR_RxFF_INT(x) CSI_SR_RxFF_INT(x)
#define CSI_CSISR_DMA_TSF_DONE_FB1_MASK CSI_SR_DMA_TSF_DONE_FB1_MASK
#define CSI_CSISR_DMA_TSF_DONE_FB1_SHIFT CSI_SR_DMA_TSF_DONE_FB1_SHIFT
#define CSI_CSISR_DMA_TSF_DONE_FB1(x) CSI_SR_DMA_TSF_DONE_FB1(x)
#define CSI_CSISR_DMA_TSF_DONE_FB2_MASK CSI_SR_DMA_TSF_DONE_FB2_MASK
#define CSI_CSISR_DMA_TSF_DONE_FB2_SHIFT CSI_SR_DMA_TSF_DONE_FB2_SHIFT
#define CSI_CSISR_DMA_TSF_DONE_FB2(x) CSI_SR_DMA_TSF_DONE_FB2(x)
#define CSI_CSISR_STATFF_INT_MASK CSI_SR_STATFF_INT_MASK
#define CSI_CSISR_STATFF_INT_SHIFT CSI_SR_STATFF_INT_SHIFT
#define CSI_CSISR_STATFF_INT(x) CSI_SR_STATFF_INT(x)
#define CSI_CSISR_DMA_TSF_DONE_SFF_MASK CSI_SR_DMA_TSF_DONE_SFF_MASK
#define CSI_CSISR_DMA_TSF_DONE_SFF_SHIFT CSI_SR_DMA_TSF_DONE_SFF_SHIFT
#define CSI_CSISR_DMA_TSF_DONE_SFF(x) CSI_SR_DMA_TSF_DONE_SFF(x)
#define CSI_CSISR_RF_OR_INT_MASK CSI_SR_RF_OR_INT_MASK
#define CSI_CSISR_RF_OR_INT_SHIFT CSI_SR_RF_OR_INT_SHIFT
#define CSI_CSISR_RF_OR_INT(x) CSI_SR_RF_OR_INT(x)
#define CSI_CSISR_SF_OR_INT_MASK CSI_SR_SF_OR_INT_MASK
#define CSI_CSISR_SF_OR_INT_SHIFT CSI_SR_SF_OR_INT_SHIFT
#define CSI_CSISR_SF_OR_INT(x) CSI_SR_SF_OR_INT(x)
#define CSI_CSISR_DMA_FIELD1_DONE_MASK CSI_SR_DMA_FIELD1_DONE_MASK
#define CSI_CSISR_DMA_FIELD1_DONE_SHIFT CSI_SR_DMA_FIELD1_DONE_SHIFT
#define CSI_CSISR_DMA_FIELD1_DONE(x) CSI_SR_DMA_FIELD1_DONE(x)
#define CSI_CSISR_DMA_FIELD0_DONE_MASK CSI_SR_DMA_FIELD0_DONE_MASK
#define CSI_CSISR_DMA_FIELD0_DONE_SHIFT CSI_SR_DMA_FIELD0_DONE_SHIFT
#define CSI_CSISR_DMA_FIELD0_DONE(x) CSI_SR_DMA_FIELD0_DONE(x)
#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_MASK CSI_SR_BASEADDR_CHHANGE_ERROR_MASK
#define CSI_CSISR_BASEADDR_CHHANGE_ERROR_SHIFT CSI_SR_BASEADDR_CHHANGE_ERROR_SHIFT
#define CSI_CSISR_BASEADDR_CHHANGE_ERROR(x) CSI_SR_BASEADDR_CHHANGE_ERROR(x)
#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_MASK CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_MASK
#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF_SHIFT
#define CSI_CSIDMASA_STATFIFO_DMA_START_ADDR_SFF(x) CSI_DMASA_STATFIFO_DMA_START_ADDR_SFF(x)
#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_MASK
#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF_SHIFT
#define CSI_CSIDMATS_STATFIFO_DMA_TSF_SIZE_SFF(x) CSI_DMATS_STATFIFO_DMA_TSF_SIZE_SFF(x)
#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_MASK CSI_DMASA_FB1_DMA_START_ADDR_FB1_MASK
#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1_SHIFT CSI_DMASA_FB1_DMA_START_ADDR_FB1_SHIFT
#define CSI_CSIDMASA_FB1_DMA_START_ADDR_FB1(x) CSI_DMASA_FB1_DMA_START_ADDR_FB1(x)
#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_MASK CSI_DMASA_FB2_DMA_START_ADDR_FB2_MASK
#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2_SHIFT CSI_DMASA_FB2_DMA_START_ADDR_FB2_SHIFT
#define CSI_CSIDMASA_FB2_DMA_START_ADDR_FB2(x) CSI_DMASA_FB2_DMA_START_ADDR_FB2(x)
#define CSI_CSIFBUF_PARA_FBUF_STRIDE_MASK CSI_FBUF_PARA_FBUF_STRIDE_MASK
#define CSI_CSIFBUF_PARA_FBUF_STRIDE_SHIFT CSI_FBUF_PARA_FBUF_STRIDE_SHIFT
#define CSI_CSIFBUF_PARA_FBUF_STRIDE(x) CSI_FBUF_PARA_FBUF_STRIDE(x)
#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_MASK CSI_FBUF_PARA_DEINTERLACE_STRIDE_MASK
#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE_SHIFT CSI_FBUF_PARA_DEINTERLACE_STRIDE_SHIFT
#define CSI_CSIFBUF_PARA_DEINTERLACE_STRIDE(x) CSI_FBUF_PARA_DEINTERLACE_STRIDE(x)
#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_MASK CSI_IMAG_PARA_IMAGE_HEIGHT_MASK
#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT_SHIFT CSI_IMAG_PARA_IMAGE_HEIGHT_SHIFT
#define CSI_CSIIMAG_PARA_IMAGE_HEIGHT(x) CSI_IMAG_PARA_IMAGE_HEIGHT(x)
#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_MASK CSI_IMAG_PARA_IMAGE_WIDTH_MASK
#define CSI_CSIIMAG_PARA_IMAGE_WIDTH_SHIFT CSI_IMAG_PARA_IMAGE_WIDTH_SHIFT
#define CSI_CSIIMAG_PARA_IMAGE_WIDTH(x) CSI_IMAG_PARA_IMAGE_WIDTH(x)
#define CSI_CSICR18_NTSC_EN_MASK CSI_CR18_NTSC_EN_MASK
#define CSI_CSICR18_NTSC_EN_SHIFT CSI_CR18_NTSC_EN_SHIFT
#define CSI_CSICR18_NTSC_EN(x) CSI_CR18_NTSC_EN(x)
#define CSI_CSICR18_TVDECODER_IN_EN_MASK CSI_CR18_TVDECODER_IN_EN_MASK
#define CSI_CSICR18_TVDECODER_IN_EN_SHIFT CSI_CR18_TVDECODER_IN_EN_SHIFT
#define CSI_CSICR18_TVDECODER_IN_EN(x) CSI_CR18_TVDECODER_IN_EN(x)
#define CSI_CSICR18_DEINTERLACE_EN_MASK CSI_CR18_DEINTERLACE_EN_MASK
#define CSI_CSICR18_DEINTERLACE_EN_SHIFT CSI_CR18_DEINTERLACE_EN_SHIFT
#define CSI_CSICR18_DEINTERLACE_EN(x) CSI_CR18_DEINTERLACE_EN(x)
#define CSI_CSICR18_PARALLEL24_EN_MASK CSI_CR18_PARALLEL24_EN_MASK
#define CSI_CSICR18_PARALLEL24_EN_SHIFT CSI_CR18_PARALLEL24_EN_SHIFT
#define CSI_CSICR18_PARALLEL24_EN(x) CSI_CR18_PARALLEL24_EN(x)
#define CSI_CSICR18_BASEADDR_SWITCH_EN_MASK CSI_CR18_BASEADDR_SWITCH_EN_MASK
#define CSI_CSICR18_BASEADDR_SWITCH_EN_SHIFT CSI_CR18_BASEADDR_SWITCH_EN_SHIFT
#define CSI_CSICR18_BASEADDR_SWITCH_EN(x) CSI_CR18_BASEADDR_SWITCH_EN(x)
#define CSI_CSICR18_BASEADDR_SWITCH_SEL_MASK CSI_CR18_BASEADDR_SWITCH_SEL_MASK
#define CSI_CSICR18_BASEADDR_SWITCH_SEL_SHIFT CSI_CR18_BASEADDR_SWITCH_SEL_SHIFT
#define CSI_CSICR18_BASEADDR_SWITCH_SEL(x) CSI_CR18_BASEADDR_SWITCH_SEL(x)
#define CSI_CSICR18_FIELD0_DONE_IE_MASK CSI_CR18_FIELD0_DONE_IE_MASK
#define CSI_CSICR18_FIELD0_DONE_IE_SHIFT CSI_CR18_FIELD0_DONE_IE_SHIFT
#define CSI_CSICR18_FIELD0_DONE_IE(x) CSI_CR18_FIELD0_DONE_IE(x)
#define CSI_CSICR18_DMA_FIELD1_DONE_IE_MASK CSI_CR18_DMA_FIELD1_DONE_IE_MASK
#define CSI_CSICR18_DMA_FIELD1_DONE_IE_SHIFT CSI_CR18_DMA_FIELD1_DONE_IE_SHIFT
#define CSI_CSICR18_DMA_FIELD1_DONE_IE(x) CSI_CR18_DMA_FIELD1_DONE_IE(x)
#define CSI_CSICR18_LAST_DMA_REQ_SEL_MASK CSI_CR18_LAST_DMA_REQ_SEL_MASK
#define CSI_CSICR18_LAST_DMA_REQ_SEL_SHIFT CSI_CR18_LAST_DMA_REQ_SEL_SHIFT
#define CSI_CSICR18_LAST_DMA_REQ_SEL(x) CSI_CR18_LAST_DMA_REQ_SEL(x)
#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_MASK CSI_CR18_BASEADDR_CHANGE_ERROR_IE_MASK
#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE_SHIFT CSI_CR18_BASEADDR_CHANGE_ERROR_IE_SHIFT
#define CSI_CSICR18_BASEADDR_CHANGE_ERROR_IE(x) CSI_CR18_BASEADDR_CHANGE_ERROR_IE(x)
#define CSI_CSICR18_RGB888A_FORMAT_SEL_MASK CSI_CR18_RGB888A_FORMAT_SEL_MASK
#define CSI_CSICR18_RGB888A_FORMAT_SEL_SHIFT CSI_CR18_RGB888A_FORMAT_SEL_SHIFT
#define CSI_CSICR18_RGB888A_FORMAT_SEL(x) CSI_CR18_RGB888A_FORMAT_SEL(x)
#define CSI_CSICR18_AHB_HPROT_MASK CSI_CR18_AHB_HPROT_MASK
#define CSI_CSICR18_AHB_HPROT_SHIFT CSI_CR18_AHB_HPROT_SHIFT
#define CSI_CSICR18_AHB_HPROT(x) CSI_CR18_AHB_HPROT(x)
#define CSI_CSICR18_MASK_OPTION_MASK CSI_CR18_MASK_OPTION_MASK
#define CSI_CSICR18_MASK_OPTION_SHIFT CSI_CR18_MASK_OPTION_SHIFT
#define CSI_CSICR18_MASK_OPTION(x) CSI_CR18_MASK_OPTION(x)
#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_MASK CSI_CR18_MIPI_DOUBLE_CMPNT_MASK
#define CSI_CSICR18_MIPI_DOUBLE_CMPNT_SHIFT CSI_CR18_MIPI_DOUBLE_CMPNT_SHIFT
#define CSI_CSICR18_MIPI_DOUBLE_CMPNT(x) CSI_CR18_MIPI_DOUBLE_CMPNT(x)
#define CSI_CSICR18_MIPI_YU_SWAP_MASK CSI_CR18_MIPI_YU_SWAP_MASK
#define CSI_CSICR18_MIPI_YU_SWAP_SHIFT CSI_CR18_MIPI_YU_SWAP_SHIFT
#define CSI_CSICR18_MIPI_YU_SWAP(x) CSI_CR18_MIPI_YU_SWAP(x)
#define CSI_CSICR18_DATA_FROM_MIPI_MASK CSI_CR18_DATA_FROM_MIPI_MASK
#define CSI_CSICR18_DATA_FROM_MIPI_SHIFT CSI_CR18_DATA_FROM_MIPI_SHIFT
#define CSI_CSICR18_DATA_FROM_MIPI(x) CSI_CR18_DATA_FROM_MIPI(x)
#define CSI_CSICR18_LINE_STRIDE_EN_MASK CSI_CR18_LINE_STRIDE_EN_MASK
#define CSI_CSICR18_LINE_STRIDE_EN_SHIFT CSI_CR18_LINE_STRIDE_EN_SHIFT
#define CSI_CSICR18_LINE_STRIDE_EN(x) CSI_CR18_LINE_STRIDE_EN(x)
#define CSI_CSICR18_MIPI_DATA_FORMAT_MASK CSI_CR18_MIPI_DATA_FORMAT_MASK
#define CSI_CSICR18_MIPI_DATA_FORMAT_SHIFT CSI_CR18_MIPI_DATA_FORMAT_SHIFT
#define CSI_CSICR18_MIPI_DATA_FORMAT(x) CSI_CR18_MIPI_DATA_FORMAT(x)
#define CSI_CSICR18_CSI_ENABLE_MASK CSI_CR18_CSI_ENABLE_MASK
#define CSI_CSICR18_CSI_ENABLE_SHIFT CSI_CR18_CSI_ENABLE_SHIFT
#define CSI_CSICR18_CSI_ENABLE(x) CSI_CR18_CSI_ENABLE(x)
#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_MASK
#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL_SHIFT
#define CSI_CSICR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x) CSI_CR19_DMA_RFIFO_HIGHEST_FIFO_LEVEL(x)
#define CSI_CSICR20_THRESHOLD_MASK CSI_CR20_THRESHOLD_MASK
#define CSI_CSICR20_THRESHOLD_SHIFT CSI_CR20_THRESHOLD_SHIFT
#define CSI_CSICR20_THRESHOLD(x) CSI_CR20_THRESHOLD(x)
#define CSI_CSICR20_BINARY_EN_MASK CSI_CR20_BINARY_EN_MASK
#define CSI_CSICR20_BINARY_EN_SHIFT CSI_CR20_BINARY_EN_SHIFT
#define CSI_CSICR20_BINARY_EN(x) CSI_CR20_BINARY_EN(x)
#define CSI_CSICR20_QR_DATA_FORMAT_MASK CSI_CR20_QR_DATA_FORMAT_MASK
#define CSI_CSICR20_QR_DATA_FORMAT_SHIFT CSI_CR20_QR_DATA_FORMAT_SHIFT
#define CSI_CSICR20_QR_DATA_FORMAT(x) CSI_CR20_QR_DATA_FORMAT(x)
#define CSI_CSICR20_BIG_END_MASK CSI_CR20_BIG_END_MASK
#define CSI_CSICR20_BIG_END_SHIFT CSI_CR20_BIG_END_SHIFT
#define CSI_CSICR20_BIG_END(x) CSI_CR20_BIG_END(x)
#define CSI_CSICR20_10BIT_NEW_EN_MASK CSI_CR20_10BIT_NEW_EN_MASK
#define CSI_CSICR20_10BIT_NEW_EN_SHIFT CSI_CR20_10BIT_NEW_EN_SHIFT
#define CSI_CSICR20_10BIT_NEW_EN(x) CSI_CR20_10BIT_NEW_EN(x)
#define CSI_CSICR20_HISTOGRAM_EN_MASK CSI_CR20_HISTOGRAM_EN_MASK
#define CSI_CSICR20_HISTOGRAM_EN_SHIFT CSI_CR20_HISTOGRAM_EN_SHIFT
#define CSI_CSICR20_HISTOGRAM_EN(x) CSI_CR20_HISTOGRAM_EN(x)
#define CSI_CSICR20_QRCODE_EN_MASK CSI_CR20_QRCODE_EN_MASK
#define CSI_CSICR20_QRCODE_EN_SHIFT CSI_CR20_QRCODE_EN_SHIFT
#define CSI_CSICR20_QRCODE_EN(x) CSI_CR20_QRCODE_EN(x)
#define CSI_CSICR21_PIXEL_COUNTERS_MASK CSI_CR21_PIXEL_COUNTERS_MASK
#define CSI_CSICR21_PIXEL_COUNTERS_SHIFT CSI_CR21_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR21_PIXEL_COUNTERS(x) CSI_CR21_PIXEL_COUNTERS(x)
#define CSI_CSICR22_PIXEL_COUNTERS_MASK CSI_CR22_PIXEL_COUNTERS_MASK
#define CSI_CSICR22_PIXEL_COUNTERS_SHIFT CSI_CR22_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR22_PIXEL_COUNTERS(x) CSI_CR22_PIXEL_COUNTERS(x)
#define CSI_CSICR23_PIXEL_COUNTERS_MASK CSI_CR23_PIXEL_COUNTERS_MASK
#define CSI_CSICR23_PIXEL_COUNTERS_SHIFT CSI_CR23_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR23_PIXEL_COUNTERS(x) CSI_CR23_PIXEL_COUNTERS(x)
#define CSI_CSICR24_PIXEL_COUNTERS_MASK CSI_CR24_PIXEL_COUNTERS_MASK
#define CSI_CSICR24_PIXEL_COUNTERS_SHIFT CSI_CR24_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR24_PIXEL_COUNTERS(x) CSI_CR24_PIXEL_COUNTERS(x)
#define CSI_CSICR25_PIXEL_COUNTERS_MASK CSI_CR25_PIXEL_COUNTERS_MASK
#define CSI_CSICR25_PIXEL_COUNTERS_SHIFT CSI_CR25_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR25_PIXEL_COUNTERS(x) CSI_CR25_PIXEL_COUNTERS(x)
#define CSI_CSICR26_PIXEL_COUNTERS_MASK CSI_CR26_PIXEL_COUNTERS_MASK
#define CSI_CSICR26_PIXEL_COUNTERS_SHIFT CSI_CR26_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR26_PIXEL_COUNTERS(x) CSI_CR26_PIXEL_COUNTERS(x)
#define CSI_CSICR27_PIXEL_COUNTERS_MASK CSI_CR27_PIXEL_COUNTERS_MASK
#define CSI_CSICR27_PIXEL_COUNTERS_SHIFT CSI_CR27_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR27_PIXEL_COUNTERS(x) CSI_CR27_PIXEL_COUNTERS(x)
#define CSI_CSICR28_PIXEL_COUNTERS_MASK CSI_CR28_PIXEL_COUNTERS_MASK
#define CSI_CSICR28_PIXEL_COUNTERS_SHIFT CSI_CR28_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR28_PIXEL_COUNTERS(x) CSI_CR28_PIXEL_COUNTERS(x)
#define CSI_CSICR29_PIXEL_COUNTERS_MASK CSI_CR29_PIXEL_COUNTERS_MASK
#define CSI_CSICR29_PIXEL_COUNTERS_SHIFT CSI_CR29_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR29_PIXEL_COUNTERS(x) CSI_CR29_PIXEL_COUNTERS(x)
#define CSI_CSICR30_PIXEL_COUNTERS_MASK CSI_CR30_PIXEL_COUNTERS_MASK
#define CSI_CSICR30_PIXEL_COUNTERS_SHIFT CSI_CR30_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR30_PIXEL_COUNTERS(x) CSI_CR30_PIXEL_COUNTERS(x)
#define CSI_CSICR31_PIXEL_COUNTERS_MASK CSI_CR31_PIXEL_COUNTERS_MASK
#define CSI_CSICR31_PIXEL_COUNTERS_SHIFT CSI_CR31_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR31_PIXEL_COUNTERS(x) CSI_CR31_PIXEL_COUNTERS(x)
#define CSI_CSICR32_PIXEL_COUNTERS_MASK CSI_CR32_PIXEL_COUNTERS_MASK
#define CSI_CSICR32_PIXEL_COUNTERS_SHIFT CSI_CR32_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR32_PIXEL_COUNTERS(x) CSI_CR32_PIXEL_COUNTERS(x)
#define CSI_CSICR33_PIXEL_COUNTERS_MASK CSI_CR33_PIXEL_COUNTERS_MASK
#define CSI_CSICR33_PIXEL_COUNTERS_SHIFT CSI_CR33_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR33_PIXEL_COUNTERS(x) CSI_CR33_PIXEL_COUNTERS(x)
#define CSI_CSICR34_PIXEL_COUNTERS_MASK CSI_CR34_PIXEL_COUNTERS_MASK
#define CSI_CSICR34_PIXEL_COUNTERS_SHIFT CSI_CR34_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR34_PIXEL_COUNTERS(x) CSI_CR34_PIXEL_COUNTERS(x)
#define CSI_CSICR35_PIXEL_COUNTERS_MASK CSI_CR35_PIXEL_COUNTERS_MASK
#define CSI_CSICR35_PIXEL_COUNTERS_SHIFT CSI_CR35_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR35_PIXEL_COUNTERS(x) CSI_CR35_PIXEL_COUNTERS(x)
#define CSI_CSICR36_PIXEL_COUNTERS_MASK CSI_CR36_PIXEL_COUNTERS_MASK
#define CSI_CSICR36_PIXEL_COUNTERS_SHIFT CSI_CR36_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR36_PIXEL_COUNTERS(x) CSI_CR36_PIXEL_COUNTERS(x)
#define CSI_CSICR37_PIXEL_COUNTERS_MASK CSI_CR37_PIXEL_COUNTERS_MASK
#define CSI_CSICR37_PIXEL_COUNTERS_SHIFT CSI_CR37_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR37_PIXEL_COUNTERS(x) CSI_CR37_PIXEL_COUNTERS(x)
#define CSI_CSICR38_PIXEL_COUNTERS_MASK CSI_CR38_PIXEL_COUNTERS_MASK
#define CSI_CSICR38_PIXEL_COUNTERS_SHIFT CSI_CR38_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR38_PIXEL_COUNTERS(x) CSI_CR38_PIXEL_COUNTERS(x)
#define CSI_CSICR39_PIXEL_COUNTERS_MASK CSI_CR39_PIXEL_COUNTERS_MASK
#define CSI_CSICR39_PIXEL_COUNTERS_SHIFT CSI_CR39_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR39_PIXEL_COUNTERS(x) CSI_CR39_PIXEL_COUNTERS(x)
#define CSI_CSICR40_PIXEL_COUNTERS_MASK CSI_CR40_PIXEL_COUNTERS_MASK
#define CSI_CSICR40_PIXEL_COUNTERS_SHIFT CSI_CR40_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR40_PIXEL_COUNTERS(x) CSI_CR40_PIXEL_COUNTERS(x)
#define CSI_CSICR41_PIXEL_COUNTERS_MASK CSI_CR41_PIXEL_COUNTERS_MASK
#define CSI_CSICR41_PIXEL_COUNTERS_SHIFT CSI_CR41_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR41_PIXEL_COUNTERS(x) CSI_CR41_PIXEL_COUNTERS(x)
#define CSI_CSICR42_PIXEL_COUNTERS_MASK CSI_CR42_PIXEL_COUNTERS_MASK
#define CSI_CSICR42_PIXEL_COUNTERS_SHIFT CSI_CR42_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR42_PIXEL_COUNTERS(x) CSI_CR42_PIXEL_COUNTERS(x)
#define CSI_CSICR43_PIXEL_COUNTERS_MASK CSI_CR43_PIXEL_COUNTERS_MASK
#define CSI_CSICR43_PIXEL_COUNTERS_SHIFT CSI_CR43_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR43_PIXEL_COUNTERS(x) CSI_CR43_PIXEL_COUNTERS(x)
#define CSI_CSICR44_PIXEL_COUNTERS_MASK CSI_CR44_PIXEL_COUNTERS_MASK
#define CSI_CSICR44_PIXEL_COUNTERS_SHIFT CSI_CR44_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR44_PIXEL_COUNTERS(x) CSI_CR44_PIXEL_COUNTERS(x)
#define CSI_CSICR45_PIXEL_COUNTERS_MASK CSI_CR45_PIXEL_COUNTERS_MASK
#define CSI_CSICR45_PIXEL_COUNTERS_SHIFT CSI_CR45_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR45_PIXEL_COUNTERS(x) CSI_CR45_PIXEL_COUNTERS(x)
#define CSI_CSICR46_PIXEL_COUNTERS_MASK CSI_CR46_PIXEL_COUNTERS_MASK
#define CSI_CSICR46_PIXEL_COUNTERS_SHIFT CSI_CR46_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR46_PIXEL_COUNTERS(x) CSI_CR46_PIXEL_COUNTERS(x)
#define CSI_CSICR47_PIXEL_COUNTERS_MASK CSI_CR47_PIXEL_COUNTERS_MASK
#define CSI_CSICR47_PIXEL_COUNTERS_SHIFT CSI_CR47_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR47_PIXEL_COUNTERS(x) CSI_CR47_PIXEL_COUNTERS(x)
#define CSI_CSICR48_PIXEL_COUNTERS_MASK CSI_CR48_PIXEL_COUNTERS_MASK
#define CSI_CSICR48_PIXEL_COUNTERS_SHIFT CSI_CR48_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR48_PIXEL_COUNTERS(x) CSI_CR48_PIXEL_COUNTERS(x)
#define CSI_CSICR49_PIXEL_COUNTERS_MASK CSI_CR49_PIXEL_COUNTERS_MASK
#define CSI_CSICR49_PIXEL_COUNTERS_SHIFT CSI_CR49_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR49_PIXEL_COUNTERS(x) CSI_CR49_PIXEL_COUNTERS(x)
#define CSI_CSICR50_PIXEL_COUNTERS_MASK CSI_CR50_PIXEL_COUNTERS_MASK
#define CSI_CSICR50_PIXEL_COUNTERS_SHIFT CSI_CR50_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR50_PIXEL_COUNTERS(x) CSI_CR50_PIXEL_COUNTERS(x)
#define CSI_CSICR51_PIXEL_COUNTERS_MASK CSI_CR51_PIXEL_COUNTERS_MASK
#define CSI_CSICR51_PIXEL_COUNTERS_SHIFT CSI_CR51_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR51_PIXEL_COUNTERS(x) CSI_CR51_PIXEL_COUNTERS(x)
#define CSI_CSICR52_PIXEL_COUNTERS_MASK CSI_CR52_PIXEL_COUNTERS_MASK
#define CSI_CSICR52_PIXEL_COUNTERS_SHIFT CSI_CR52_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR52_PIXEL_COUNTERS(x) CSI_CR52_PIXEL_COUNTERS(x)
#define CSI_CSICR53_PIXEL_COUNTERS_MASK CSI_CR53_PIXEL_COUNTERS_MASK
#define CSI_CSICR53_PIXEL_COUNTERS_SHIFT CSI_CR53_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR53_PIXEL_COUNTERS(x) CSI_CR53_PIXEL_COUNTERS(x)
#define CSI_CSICR54_PIXEL_COUNTERS_MASK CSI_CR54_PIXEL_COUNTERS_MASK
#define CSI_CSICR54_PIXEL_COUNTERS_SHIFT CSI_CR54_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR54_PIXEL_COUNTERS(x) CSI_CR54_PIXEL_COUNTERS(x)
#define CSI_CSICR55_PIXEL_COUNTERS_MASK CSI_CR55_PIXEL_COUNTERS_MASK
#define CSI_CSICR55_PIXEL_COUNTERS_SHIFT CSI_CR55_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR55_PIXEL_COUNTERS(x) CSI_CR55_PIXEL_COUNTERS(x)
#define CSI_CSICR56_PIXEL_COUNTERS_MASK CSI_CR56_PIXEL_COUNTERS_MASK
#define CSI_CSICR56_PIXEL_COUNTERS_SHIFT CSI_CR56_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR56_PIXEL_COUNTERS(x) CSI_CR56_PIXEL_COUNTERS(x)
#define CSI_CSICR57_PIXEL_COUNTERS_MASK CSI_CR57_PIXEL_COUNTERS_MASK
#define CSI_CSICR57_PIXEL_COUNTERS_SHIFT CSI_CR57_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR57_PIXEL_COUNTERS(x) CSI_CR57_PIXEL_COUNTERS(x)
#define CSI_CSICR58_PIXEL_COUNTERS_MASK CSI_CR58_PIXEL_COUNTERS_MASK
#define CSI_CSICR58_PIXEL_COUNTERS_SHIFT CSI_CR58_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR58_PIXEL_COUNTERS(x) CSI_CR58_PIXEL_COUNTERS(x)
#define CSI_CSICR59_PIXEL_COUNTERS_MASK CSI_CR59_PIXEL_COUNTERS_MASK
#define CSI_CSICR59_PIXEL_COUNTERS_SHIFT CSI_CR59_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR59_PIXEL_COUNTERS(x) CSI_CR59_PIXEL_COUNTERS(x)
#define CSI_CSICR60_PIXEL_COUNTERS_MASK CSI_CR60_PIXEL_COUNTERS_MASK
#define CSI_CSICR60_PIXEL_COUNTERS_SHIFT CSI_CR60_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR60_PIXEL_COUNTERS(x) CSI_CR60_PIXEL_COUNTERS(x)
#define CSI_CSICR61_PIXEL_COUNTERS_MASK CSI_CR61_PIXEL_COUNTERS_MASK
#define CSI_CSICR61_PIXEL_COUNTERS_SHIFT CSI_CR61_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR61_PIXEL_COUNTERS(x) CSI_CR61_PIXEL_COUNTERS(x)
#define CSI_CSICR62_PIXEL_COUNTERS_MASK CSI_CR62_PIXEL_COUNTERS_MASK
#define CSI_CSICR62_PIXEL_COUNTERS_SHIFT CSI_CR62_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR62_PIXEL_COUNTERS(x) CSI_CR62_PIXEL_COUNTERS(x)
#define CSI_CSICR63_PIXEL_COUNTERS_MASK CSI_CR63_PIXEL_COUNTERS_MASK
#define CSI_CSICR63_PIXEL_COUNTERS_SHIFT CSI_CR63_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR63_PIXEL_COUNTERS(x) CSI_CR63_PIXEL_COUNTERS(x)
#define CSI_CSICR64_PIXEL_COUNTERS_MASK CSI_CR64_PIXEL_COUNTERS_MASK
#define CSI_CSICR64_PIXEL_COUNTERS_SHIFT CSI_CR64_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR64_PIXEL_COUNTERS(x) CSI_CR64_PIXEL_COUNTERS(x)
#define CSI_CSICR65_PIXEL_COUNTERS_MASK CSI_CR65_PIXEL_COUNTERS_MASK
#define CSI_CSICR65_PIXEL_COUNTERS_SHIFT CSI_CR65_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR65_PIXEL_COUNTERS(x) CSI_CR65_PIXEL_COUNTERS(x)
#define CSI_CSICR66_PIXEL_COUNTERS_MASK CSI_CR66_PIXEL_COUNTERS_MASK
#define CSI_CSICR66_PIXEL_COUNTERS_SHIFT CSI_CR66_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR66_PIXEL_COUNTERS(x) CSI_CR66_PIXEL_COUNTERS(x)
#define CSI_CSICR67_PIXEL_COUNTERS_MASK CSI_CR67_PIXEL_COUNTERS_MASK
#define CSI_CSICR67_PIXEL_COUNTERS_SHIFT CSI_CR67_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR67_PIXEL_COUNTERS(x) CSI_CR67_PIXEL_COUNTERS(x)
#define CSI_CSICR68_PIXEL_COUNTERS_MASK CSI_CR68_PIXEL_COUNTERS_MASK
#define CSI_CSICR68_PIXEL_COUNTERS_SHIFT CSI_CR68_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR68_PIXEL_COUNTERS(x) CSI_CR68_PIXEL_COUNTERS(x)
#define CSI_CSICR69_PIXEL_COUNTERS_MASK CSI_CR69_PIXEL_COUNTERS_MASK
#define CSI_CSICR69_PIXEL_COUNTERS_SHIFT CSI_CR69_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR69_PIXEL_COUNTERS(x) CSI_CR69_PIXEL_COUNTERS(x)
#define CSI_CSICR70_PIXEL_COUNTERS_MASK CSI_CR70_PIXEL_COUNTERS_MASK
#define CSI_CSICR70_PIXEL_COUNTERS_SHIFT CSI_CR70_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR70_PIXEL_COUNTERS(x) CSI_CR70_PIXEL_COUNTERS(x)
#define CSI_CSICR71_PIXEL_COUNTERS_MASK CSI_CR71_PIXEL_COUNTERS_MASK
#define CSI_CSICR71_PIXEL_COUNTERS_SHIFT CSI_CR71_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR71_PIXEL_COUNTERS(x) CSI_CR71_PIXEL_COUNTERS(x)
#define CSI_CSICR72_PIXEL_COUNTERS_MASK CSI_CR72_PIXEL_COUNTERS_MASK
#define CSI_CSICR72_PIXEL_COUNTERS_SHIFT CSI_CR72_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR72_PIXEL_COUNTERS(x) CSI_CR72_PIXEL_COUNTERS(x)
#define CSI_CSICR73_PIXEL_COUNTERS_MASK CSI_CR73_PIXEL_COUNTERS_MASK
#define CSI_CSICR73_PIXEL_COUNTERS_SHIFT CSI_CR73_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR73_PIXEL_COUNTERS(x) CSI_CR73_PIXEL_COUNTERS(x)
#define CSI_CSICR74_PIXEL_COUNTERS_MASK CSI_CR74_PIXEL_COUNTERS_MASK
#define CSI_CSICR74_PIXEL_COUNTERS_SHIFT CSI_CR74_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR74_PIXEL_COUNTERS(x) CSI_CR74_PIXEL_COUNTERS(x)
#define CSI_CSICR75_PIXEL_COUNTERS_MASK CSI_CR75_PIXEL_COUNTERS_MASK
#define CSI_CSICR75_PIXEL_COUNTERS_SHIFT CSI_CR75_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR75_PIXEL_COUNTERS(x) CSI_CR75_PIXEL_COUNTERS(x)
#define CSI_CSICR76_PIXEL_COUNTERS_MASK CSI_CR76_PIXEL_COUNTERS_MASK
#define CSI_CSICR76_PIXEL_COUNTERS_SHIFT CSI_CR76_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR76_PIXEL_COUNTERS(x) CSI_CR76_PIXEL_COUNTERS(x)
#define CSI_CSICR77_PIXEL_COUNTERS_MASK CSI_CR77_PIXEL_COUNTERS_MASK
#define CSI_CSICR77_PIXEL_COUNTERS_SHIFT CSI_CR77_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR77_PIXEL_COUNTERS(x) CSI_CR77_PIXEL_COUNTERS(x)
#define CSI_CSICR78_PIXEL_COUNTERS_MASK CSI_CR78_PIXEL_COUNTERS_MASK
#define CSI_CSICR78_PIXEL_COUNTERS_SHIFT CSI_CR78_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR78_PIXEL_COUNTERS(x) CSI_CR78_PIXEL_COUNTERS(x)
#define CSI_CSICR79_PIXEL_COUNTERS_MASK CSI_CR79_PIXEL_COUNTERS_MASK
#define CSI_CSICR79_PIXEL_COUNTERS_SHIFT CSI_CR79_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR79_PIXEL_COUNTERS(x) CSI_CR79_PIXEL_COUNTERS(x)
#define CSI_CSICR80_PIXEL_COUNTERS_MASK CSI_CR80_PIXEL_COUNTERS_MASK
#define CSI_CSICR80_PIXEL_COUNTERS_SHIFT CSI_CR80_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR80_PIXEL_COUNTERS(x) CSI_CR80_PIXEL_COUNTERS(x)
#define CSI_CSICR81_PIXEL_COUNTERS_MASK CSI_CR81_PIXEL_COUNTERS_MASK
#define CSI_CSICR81_PIXEL_COUNTERS_SHIFT CSI_CR81_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR81_PIXEL_COUNTERS(x) CSI_CR81_PIXEL_COUNTERS(x)
#define CSI_CSICR82_PIXEL_COUNTERS_MASK CSI_CR82_PIXEL_COUNTERS_MASK
#define CSI_CSICR82_PIXEL_COUNTERS_SHIFT CSI_CR82_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR82_PIXEL_COUNTERS(x) CSI_CR82_PIXEL_COUNTERS(x)
#define CSI_CSICR83_PIXEL_COUNTERS_MASK CSI_CR83_PIXEL_COUNTERS_MASK
#define CSI_CSICR83_PIXEL_COUNTERS_SHIFT CSI_CR83_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR83_PIXEL_COUNTERS(x) CSI_CR83_PIXEL_COUNTERS(x)
#define CSI_CSICR84_PIXEL_COUNTERS_MASK CSI_CR84_PIXEL_COUNTERS_MASK
#define CSI_CSICR84_PIXEL_COUNTERS_SHIFT CSI_CR84_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR84_PIXEL_COUNTERS(x) CSI_CR84_PIXEL_COUNTERS(x)
#define CSI_CSICR85_PIXEL_COUNTERS_MASK CSI_CR85_PIXEL_COUNTERS_MASK
#define CSI_CSICR85_PIXEL_COUNTERS_SHIFT CSI_CR85_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR85_PIXEL_COUNTERS(x) CSI_CR85_PIXEL_COUNTERS(x)
#define CSI_CSICR86_PIXEL_COUNTERS_MASK CSI_CR86_PIXEL_COUNTERS_MASK
#define CSI_CSICR86_PIXEL_COUNTERS_SHIFT CSI_CR86_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR86_PIXEL_COUNTERS(x) CSI_CR86_PIXEL_COUNTERS(x)
#define CSI_CSICR87_PIXEL_COUNTERS_MASK CSI_CR87_PIXEL_COUNTERS_MASK
#define CSI_CSICR87_PIXEL_COUNTERS_SHIFT CSI_CR87_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR87_PIXEL_COUNTERS(x) CSI_CR87_PIXEL_COUNTERS(x)
#define CSI_CSICR88_PIXEL_COUNTERS_MASK CSI_CR88_PIXEL_COUNTERS_MASK
#define CSI_CSICR88_PIXEL_COUNTERS_SHIFT CSI_CR88_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR88_PIXEL_COUNTERS(x) CSI_CR88_PIXEL_COUNTERS(x)
#define CSI_CSICR89_PIXEL_COUNTERS_MASK CSI_CR89_PIXEL_COUNTERS_MASK
#define CSI_CSICR89_PIXEL_COUNTERS_SHIFT CSI_CR89_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR89_PIXEL_COUNTERS(x) CSI_CR89_PIXEL_COUNTERS(x)
#define CSI_CSICR90_PIXEL_COUNTERS_MASK CSI_CR90_PIXEL_COUNTERS_MASK
#define CSI_CSICR90_PIXEL_COUNTERS_SHIFT CSI_CR90_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR90_PIXEL_COUNTERS(x) CSI_CR90_PIXEL_COUNTERS(x)
#define CSI_CSICR91_PIXEL_COUNTERS_MASK CSI_CR91_PIXEL_COUNTERS_MASK
#define CSI_CSICR91_PIXEL_COUNTERS_SHIFT CSI_CR91_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR91_PIXEL_COUNTERS(x) CSI_CR91_PIXEL_COUNTERS(x)
#define CSI_CSICR92_PIXEL_COUNTERS_MASK CSI_CR92_PIXEL_COUNTERS_MASK
#define CSI_CSICR92_PIXEL_COUNTERS_SHIFT CSI_CR92_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR92_PIXEL_COUNTERS(x) CSI_CR92_PIXEL_COUNTERS(x)
#define CSI_CSICR93_PIXEL_COUNTERS_MASK CSI_CR93_PIXEL_COUNTERS_MASK
#define CSI_CSICR93_PIXEL_COUNTERS_SHIFT CSI_CR93_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR93_PIXEL_COUNTERS(x) CSI_CR93_PIXEL_COUNTERS(x)
#define CSI_CSICR94_PIXEL_COUNTERS_MASK CSI_CR94_PIXEL_COUNTERS_MASK
#define CSI_CSICR94_PIXEL_COUNTERS_SHIFT CSI_CR94_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR94_PIXEL_COUNTERS(x) CSI_CR94_PIXEL_COUNTERS(x)
#define CSI_CSICR95_PIXEL_COUNTERS_MASK CSI_CR95_PIXEL_COUNTERS_MASK
#define CSI_CSICR95_PIXEL_COUNTERS_SHIFT CSI_CR95_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR95_PIXEL_COUNTERS(x) CSI_CR95_PIXEL_COUNTERS(x)
#define CSI_CSICR96_PIXEL_COUNTERS_MASK CSI_CR96_PIXEL_COUNTERS_MASK
#define CSI_CSICR96_PIXEL_COUNTERS_SHIFT CSI_CR96_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR96_PIXEL_COUNTERS(x) CSI_CR96_PIXEL_COUNTERS(x)
#define CSI_CSICR97_PIXEL_COUNTERS_MASK CSI_CR97_PIXEL_COUNTERS_MASK
#define CSI_CSICR97_PIXEL_COUNTERS_SHIFT CSI_CR97_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR97_PIXEL_COUNTERS(x) CSI_CR97_PIXEL_COUNTERS(x)
#define CSI_CSICR98_PIXEL_COUNTERS_MASK CSI_CR98_PIXEL_COUNTERS_MASK
#define CSI_CSICR98_PIXEL_COUNTERS_SHIFT CSI_CR98_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR98_PIXEL_COUNTERS(x) CSI_CR98_PIXEL_COUNTERS(x)
#define CSI_CSICR99_PIXEL_COUNTERS_MASK CSI_CR99_PIXEL_COUNTERS_MASK
#define CSI_CSICR99_PIXEL_COUNTERS_SHIFT CSI_CR99_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR99_PIXEL_COUNTERS(x) CSI_CR99_PIXEL_COUNTERS(x)
#define CSI_CSICR100_PIXEL_COUNTERS_MASK CSI_CR100_PIXEL_COUNTERS_MASK
#define CSI_CSICR100_PIXEL_COUNTERS_SHIFT CSI_CR100_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR100_PIXEL_COUNTERS(x) CSI_CR100_PIXEL_COUNTERS(x)
#define CSI_CSICR101_PIXEL_COUNTERS_MASK CSI_CR101_PIXEL_COUNTERS_MASK
#define CSI_CSICR101_PIXEL_COUNTERS_SHIFT CSI_CR101_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR101_PIXEL_COUNTERS(x) CSI_CR101_PIXEL_COUNTERS(x)
#define CSI_CSICR102_PIXEL_COUNTERS_MASK CSI_CR102_PIXEL_COUNTERS_MASK
#define CSI_CSICR102_PIXEL_COUNTERS_SHIFT CSI_CR102_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR102_PIXEL_COUNTERS(x) CSI_CR102_PIXEL_COUNTERS(x)
#define CSI_CSICR103_PIXEL_COUNTERS_MASK CSI_CR103_PIXEL_COUNTERS_MASK
#define CSI_CSICR103_PIXEL_COUNTERS_SHIFT CSI_CR103_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR103_PIXEL_COUNTERS(x) CSI_CR103_PIXEL_COUNTERS(x)
#define CSI_CSICR104_PIXEL_COUNTERS_MASK CSI_CR104_PIXEL_COUNTERS_MASK
#define CSI_CSICR104_PIXEL_COUNTERS_SHIFT CSI_CR104_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR104_PIXEL_COUNTERS(x) CSI_CR104_PIXEL_COUNTERS(x)
#define CSI_CSICR105_PIXEL_COUNTERS_MASK CSI_CR105_PIXEL_COUNTERS_MASK
#define CSI_CSICR105_PIXEL_COUNTERS_SHIFT CSI_CR105_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR105_PIXEL_COUNTERS(x) CSI_CR105_PIXEL_COUNTERS(x)
#define CSI_CSICR106_PIXEL_COUNTERS_MASK CSI_CR106_PIXEL_COUNTERS_MASK
#define CSI_CSICR106_PIXEL_COUNTERS_SHIFT CSI_CR106_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR106_PIXEL_COUNTERS(x) CSI_CR106_PIXEL_COUNTERS(x)
#define CSI_CSICR107_PIXEL_COUNTERS_MASK CSI_CR107_PIXEL_COUNTERS_MASK
#define CSI_CSICR107_PIXEL_COUNTERS_SHIFT CSI_CR107_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR107_PIXEL_COUNTERS(x) CSI_CR107_PIXEL_COUNTERS(x)
#define CSI_CSICR108_PIXEL_COUNTERS_MASK CSI_CR108_PIXEL_COUNTERS_MASK
#define CSI_CSICR108_PIXEL_COUNTERS_SHIFT CSI_CR108_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR108_PIXEL_COUNTERS(x) CSI_CR108_PIXEL_COUNTERS(x)
#define CSI_CSICR109_PIXEL_COUNTERS_MASK CSI_CR109_PIXEL_COUNTERS_MASK
#define CSI_CSICR109_PIXEL_COUNTERS_SHIFT CSI_CR109_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR109_PIXEL_COUNTERS(x) CSI_CR109_PIXEL_COUNTERS(x)
#define CSI_CSICR110_PIXEL_COUNTERS_MASK CSI_CR110_PIXEL_COUNTERS_MASK
#define CSI_CSICR110_PIXEL_COUNTERS_SHIFT CSI_CR110_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR110_PIXEL_COUNTERS(x) CSI_CR110_PIXEL_COUNTERS(x)
#define CSI_CSICR111_PIXEL_COUNTERS_MASK CSI_CR111_PIXEL_COUNTERS_MASK
#define CSI_CSICR111_PIXEL_COUNTERS_SHIFT CSI_CR111_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR111_PIXEL_COUNTERS(x) CSI_CR111_PIXEL_COUNTERS(x)
#define CSI_CSICR112_PIXEL_COUNTERS_MASK CSI_CR112_PIXEL_COUNTERS_MASK
#define CSI_CSICR112_PIXEL_COUNTERS_SHIFT CSI_CR112_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR112_PIXEL_COUNTERS(x) CSI_CR112_PIXEL_COUNTERS(x)
#define CSI_CSICR113_PIXEL_COUNTERS_MASK CSI_CR113_PIXEL_COUNTERS_MASK
#define CSI_CSICR113_PIXEL_COUNTERS_SHIFT CSI_CR113_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR113_PIXEL_COUNTERS(x) CSI_CR113_PIXEL_COUNTERS(x)
#define CSI_CSICR114_PIXEL_COUNTERS_MASK CSI_CR114_PIXEL_COUNTERS_MASK
#define CSI_CSICR114_PIXEL_COUNTERS_SHIFT CSI_CR114_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR114_PIXEL_COUNTERS(x) CSI_CR114_PIXEL_COUNTERS(x)
#define CSI_CSICR115_PIXEL_COUNTERS_MASK CSI_CR115_PIXEL_COUNTERS_MASK
#define CSI_CSICR115_PIXEL_COUNTERS_SHIFT CSI_CR115_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR115_PIXEL_COUNTERS(x) CSI_CR115_PIXEL_COUNTERS(x)
#define CSI_CSICR116_PIXEL_COUNTERS_MASK CSI_CR116_PIXEL_COUNTERS_MASK
#define CSI_CSICR116_PIXEL_COUNTERS_SHIFT CSI_CR116_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR116_PIXEL_COUNTERS(x) CSI_CR116_PIXEL_COUNTERS(x)
#define CSI_CSICR117_PIXEL_COUNTERS_MASK CSI_CR117_PIXEL_COUNTERS_MASK
#define CSI_CSICR117_PIXEL_COUNTERS_SHIFT CSI_CR117_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR117_PIXEL_COUNTERS(x) CSI_CR117_PIXEL_COUNTERS(x)
#define CSI_CSICR118_PIXEL_COUNTERS_MASK CSI_CR118_PIXEL_COUNTERS_MASK
#define CSI_CSICR118_PIXEL_COUNTERS_SHIFT CSI_CR118_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR118_PIXEL_COUNTERS(x) CSI_CR118_PIXEL_COUNTERS(x)
#define CSI_CSICR119_PIXEL_COUNTERS_MASK CSI_CR119_PIXEL_COUNTERS_MASK
#define CSI_CSICR119_PIXEL_COUNTERS_SHIFT CSI_CR119_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR119_PIXEL_COUNTERS(x) CSI_CR119_PIXEL_COUNTERS(x)
#define CSI_CSICR120_PIXEL_COUNTERS_MASK CSI_CR120_PIXEL_COUNTERS_MASK
#define CSI_CSICR120_PIXEL_COUNTERS_SHIFT CSI_CR120_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR120_PIXEL_COUNTERS(x) CSI_CR120_PIXEL_COUNTERS(x)
#define CSI_CSICR121_PIXEL_COUNTERS_MASK CSI_CR121_PIXEL_COUNTERS_MASK
#define CSI_CSICR121_PIXEL_COUNTERS_SHIFT CSI_CR121_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR121_PIXEL_COUNTERS(x) CSI_CR121_PIXEL_COUNTERS(x)
#define CSI_CSICR122_PIXEL_COUNTERS_MASK CSI_CR122_PIXEL_COUNTERS_MASK
#define CSI_CSICR122_PIXEL_COUNTERS_SHIFT CSI_CR122_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR122_PIXEL_COUNTERS(x) CSI_CR122_PIXEL_COUNTERS(x)
#define CSI_CSICR123_PIXEL_COUNTERS_MASK CSI_CR123_PIXEL_COUNTERS_MASK
#define CSI_CSICR123_PIXEL_COUNTERS_SHIFT CSI_CR123_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR123_PIXEL_COUNTERS(x) CSI_CR123_PIXEL_COUNTERS(x)
#define CSI_CSICR124_PIXEL_COUNTERS_MASK CSI_CR124_PIXEL_COUNTERS_MASK
#define CSI_CSICR124_PIXEL_COUNTERS_SHIFT CSI_CR124_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR124_PIXEL_COUNTERS(x) CSI_CR124_PIXEL_COUNTERS(x)
#define CSI_CSICR125_PIXEL_COUNTERS_MASK CSI_CR125_PIXEL_COUNTERS_MASK
#define CSI_CSICR125_PIXEL_COUNTERS_SHIFT CSI_CR125_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR125_PIXEL_COUNTERS(x) CSI_CR125_PIXEL_COUNTERS(x)
#define CSI_CSICR126_PIXEL_COUNTERS_MASK CSI_CR126_PIXEL_COUNTERS_MASK
#define CSI_CSICR126_PIXEL_COUNTERS_SHIFT CSI_CR126_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR126_PIXEL_COUNTERS(x) CSI_CR126_PIXEL_COUNTERS(x)
#define CSI_CSICR127_PIXEL_COUNTERS_MASK CSI_CR127_PIXEL_COUNTERS_MASK
#define CSI_CSICR127_PIXEL_COUNTERS_SHIFT CSI_CR127_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR127_PIXEL_COUNTERS(x) CSI_CR127_PIXEL_COUNTERS(x)
#define CSI_CSICR128_PIXEL_COUNTERS_MASK CSI_CR128_PIXEL_COUNTERS_MASK
#define CSI_CSICR128_PIXEL_COUNTERS_SHIFT CSI_CR128_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR128_PIXEL_COUNTERS(x) CSI_CR128_PIXEL_COUNTERS(x)
#define CSI_CSICR129_PIXEL_COUNTERS_MASK CSI_CR129_PIXEL_COUNTERS_MASK
#define CSI_CSICR129_PIXEL_COUNTERS_SHIFT CSI_CR129_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR129_PIXEL_COUNTERS(x) CSI_CR129_PIXEL_COUNTERS(x)
#define CSI_CSICR130_PIXEL_COUNTERS_MASK CSI_CR130_PIXEL_COUNTERS_MASK
#define CSI_CSICR130_PIXEL_COUNTERS_SHIFT CSI_CR130_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR130_PIXEL_COUNTERS(x) CSI_CR130_PIXEL_COUNTERS(x)
#define CSI_CSICR131_PIXEL_COUNTERS_MASK CSI_CR131_PIXEL_COUNTERS_MASK
#define CSI_CSICR131_PIXEL_COUNTERS_SHIFT CSI_CR131_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR131_PIXEL_COUNTERS(x) CSI_CR131_PIXEL_COUNTERS(x)
#define CSI_CSICR132_PIXEL_COUNTERS_MASK CSI_CR132_PIXEL_COUNTERS_MASK
#define CSI_CSICR132_PIXEL_COUNTERS_SHIFT CSI_CR132_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR132_PIXEL_COUNTERS(x) CSI_CR132_PIXEL_COUNTERS(x)
#define CSI_CSICR133_PIXEL_COUNTERS_MASK CSI_CR133_PIXEL_COUNTERS_MASK
#define CSI_CSICR133_PIXEL_COUNTERS_SHIFT CSI_CR133_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR133_PIXEL_COUNTERS(x) CSI_CR133_PIXEL_COUNTERS(x)
#define CSI_CSICR134_PIXEL_COUNTERS_MASK CSI_CR134_PIXEL_COUNTERS_MASK
#define CSI_CSICR134_PIXEL_COUNTERS_SHIFT CSI_CR134_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR134_PIXEL_COUNTERS(x) CSI_CR134_PIXEL_COUNTERS(x)
#define CSI_CSICR135_PIXEL_COUNTERS_MASK CSI_CR135_PIXEL_COUNTERS_MASK
#define CSI_CSICR135_PIXEL_COUNTERS_SHIFT CSI_CR135_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR135_PIXEL_COUNTERS(x) CSI_CR135_PIXEL_COUNTERS(x)
#define CSI_CSICR136_PIXEL_COUNTERS_MASK CSI_CR136_PIXEL_COUNTERS_MASK
#define CSI_CSICR136_PIXEL_COUNTERS_SHIFT CSI_CR136_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR136_PIXEL_COUNTERS(x) CSI_CR136_PIXEL_COUNTERS(x)
#define CSI_CSICR137_PIXEL_COUNTERS_MASK CSI_CR137_PIXEL_COUNTERS_MASK
#define CSI_CSICR137_PIXEL_COUNTERS_SHIFT CSI_CR137_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR137_PIXEL_COUNTERS(x) CSI_CR137_PIXEL_COUNTERS(x)
#define CSI_CSICR138_PIXEL_COUNTERS_MASK CSI_CR138_PIXEL_COUNTERS_MASK
#define CSI_CSICR138_PIXEL_COUNTERS_SHIFT CSI_CR138_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR138_PIXEL_COUNTERS(x) CSI_CR138_PIXEL_COUNTERS(x)
#define CSI_CSICR139_PIXEL_COUNTERS_MASK CSI_CR139_PIXEL_COUNTERS_MASK
#define CSI_CSICR139_PIXEL_COUNTERS_SHIFT CSI_CR139_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR139_PIXEL_COUNTERS(x) CSI_CR139_PIXEL_COUNTERS(x)
#define CSI_CSICR140_PIXEL_COUNTERS_MASK CSI_CR140_PIXEL_COUNTERS_MASK
#define CSI_CSICR140_PIXEL_COUNTERS_SHIFT CSI_CR140_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR140_PIXEL_COUNTERS(x) CSI_CR140_PIXEL_COUNTERS(x)
#define CSI_CSICR141_PIXEL_COUNTERS_MASK CSI_CR141_PIXEL_COUNTERS_MASK
#define CSI_CSICR141_PIXEL_COUNTERS_SHIFT CSI_CR141_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR141_PIXEL_COUNTERS(x) CSI_CR141_PIXEL_COUNTERS(x)
#define CSI_CSICR142_PIXEL_COUNTERS_MASK CSI_CR142_PIXEL_COUNTERS_MASK
#define CSI_CSICR142_PIXEL_COUNTERS_SHIFT CSI_CR142_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR142_PIXEL_COUNTERS(x) CSI_CR142_PIXEL_COUNTERS(x)
#define CSI_CSICR143_PIXEL_COUNTERS_MASK CSI_CR143_PIXEL_COUNTERS_MASK
#define CSI_CSICR143_PIXEL_COUNTERS_SHIFT CSI_CR143_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR143_PIXEL_COUNTERS(x) CSI_CR143_PIXEL_COUNTERS(x)
#define CSI_CSICR144_PIXEL_COUNTERS_MASK CSI_CR144_PIXEL_COUNTERS_MASK
#define CSI_CSICR144_PIXEL_COUNTERS_SHIFT CSI_CR144_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR144_PIXEL_COUNTERS(x) CSI_CR144_PIXEL_COUNTERS(x)
#define CSI_CSICR145_PIXEL_COUNTERS_MASK CSI_CR145_PIXEL_COUNTERS_MASK
#define CSI_CSICR145_PIXEL_COUNTERS_SHIFT CSI_CR145_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR145_PIXEL_COUNTERS(x) CSI_CR145_PIXEL_COUNTERS(x)
#define CSI_CSICR146_PIXEL_COUNTERS_MASK CSI_CR146_PIXEL_COUNTERS_MASK
#define CSI_CSICR146_PIXEL_COUNTERS_SHIFT CSI_CR146_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR146_PIXEL_COUNTERS(x) CSI_CR146_PIXEL_COUNTERS(x)
#define CSI_CSICR147_PIXEL_COUNTERS_MASK CSI_CR147_PIXEL_COUNTERS_MASK
#define CSI_CSICR147_PIXEL_COUNTERS_SHIFT CSI_CR147_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR147_PIXEL_COUNTERS(x) CSI_CR147_PIXEL_COUNTERS(x)
#define CSI_CSICR148_PIXEL_COUNTERS_MASK CSI_CR148_PIXEL_COUNTERS_MASK
#define CSI_CSICR148_PIXEL_COUNTERS_SHIFT CSI_CR148_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR148_PIXEL_COUNTERS(x) CSI_CR148_PIXEL_COUNTERS(x)
#define CSI_CSICR149_PIXEL_COUNTERS_MASK CSI_CR149_PIXEL_COUNTERS_MASK
#define CSI_CSICR149_PIXEL_COUNTERS_SHIFT CSI_CR149_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR149_PIXEL_COUNTERS(x) CSI_CR149_PIXEL_COUNTERS(x)
#define CSI_CSICR150_PIXEL_COUNTERS_MASK CSI_CR150_PIXEL_COUNTERS_MASK
#define CSI_CSICR150_PIXEL_COUNTERS_SHIFT CSI_CR150_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR150_PIXEL_COUNTERS(x) CSI_CR150_PIXEL_COUNTERS(x)
#define CSI_CSICR151_PIXEL_COUNTERS_MASK CSI_CR151_PIXEL_COUNTERS_MASK
#define CSI_CSICR151_PIXEL_COUNTERS_SHIFT CSI_CR151_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR151_PIXEL_COUNTERS(x) CSI_CR151_PIXEL_COUNTERS(x)
#define CSI_CSICR152_PIXEL_COUNTERS_MASK CSI_CR152_PIXEL_COUNTERS_MASK
#define CSI_CSICR152_PIXEL_COUNTERS_SHIFT CSI_CR152_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR152_PIXEL_COUNTERS(x) CSI_CR152_PIXEL_COUNTERS(x)
#define CSI_CSICR153_PIXEL_COUNTERS_MASK CSI_CR153_PIXEL_COUNTERS_MASK
#define CSI_CSICR153_PIXEL_COUNTERS_SHIFT CSI_CR153_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR153_PIXEL_COUNTERS(x) CSI_CR153_PIXEL_COUNTERS(x)
#define CSI_CSICR154_PIXEL_COUNTERS_MASK CSI_CR154_PIXEL_COUNTERS_MASK
#define CSI_CSICR154_PIXEL_COUNTERS_SHIFT CSI_CR154_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR154_PIXEL_COUNTERS(x) CSI_CR154_PIXEL_COUNTERS(x)
#define CSI_CSICR155_PIXEL_COUNTERS_MASK CSI_CR155_PIXEL_COUNTERS_MASK
#define CSI_CSICR155_PIXEL_COUNTERS_SHIFT CSI_CR155_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR155_PIXEL_COUNTERS(x) CSI_CR155_PIXEL_COUNTERS(x)
#define CSI_CSICR156_PIXEL_COUNTERS_MASK CSI_CR156_PIXEL_COUNTERS_MASK
#define CSI_CSICR156_PIXEL_COUNTERS_SHIFT CSI_CR156_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR156_PIXEL_COUNTERS(x) CSI_CR156_PIXEL_COUNTERS(x)
#define CSI_CSICR157_PIXEL_COUNTERS_MASK CSI_CR157_PIXEL_COUNTERS_MASK
#define CSI_CSICR157_PIXEL_COUNTERS_SHIFT CSI_CR157_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR157_PIXEL_COUNTERS(x) CSI_CR157_PIXEL_COUNTERS(x)
#define CSI_CSICR158_PIXEL_COUNTERS_MASK CSI_CR158_PIXEL_COUNTERS_MASK
#define CSI_CSICR158_PIXEL_COUNTERS_SHIFT CSI_CR158_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR158_PIXEL_COUNTERS(x) CSI_CR158_PIXEL_COUNTERS(x)
#define CSI_CSICR159_PIXEL_COUNTERS_MASK CSI_CR159_PIXEL_COUNTERS_MASK
#define CSI_CSICR159_PIXEL_COUNTERS_SHIFT CSI_CR159_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR159_PIXEL_COUNTERS(x) CSI_CR159_PIXEL_COUNTERS(x)
#define CSI_CSICR160_PIXEL_COUNTERS_MASK CSI_CR160_PIXEL_COUNTERS_MASK
#define CSI_CSICR160_PIXEL_COUNTERS_SHIFT CSI_CR160_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR160_PIXEL_COUNTERS(x) CSI_CR160_PIXEL_COUNTERS(x)
#define CSI_CSICR161_PIXEL_COUNTERS_MASK CSI_CR161_PIXEL_COUNTERS_MASK
#define CSI_CSICR161_PIXEL_COUNTERS_SHIFT CSI_CR161_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR161_PIXEL_COUNTERS(x) CSI_CR161_PIXEL_COUNTERS(x)
#define CSI_CSICR162_PIXEL_COUNTERS_MASK CSI_CR162_PIXEL_COUNTERS_MASK
#define CSI_CSICR162_PIXEL_COUNTERS_SHIFT CSI_CR162_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR162_PIXEL_COUNTERS(x) CSI_CR162_PIXEL_COUNTERS(x)
#define CSI_CSICR163_PIXEL_COUNTERS_MASK CSI_CR163_PIXEL_COUNTERS_MASK
#define CSI_CSICR163_PIXEL_COUNTERS_SHIFT CSI_CR163_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR163_PIXEL_COUNTERS(x) CSI_CR163_PIXEL_COUNTERS(x)
#define CSI_CSICR164_PIXEL_COUNTERS_MASK CSI_CR164_PIXEL_COUNTERS_MASK
#define CSI_CSICR164_PIXEL_COUNTERS_SHIFT CSI_CR164_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR164_PIXEL_COUNTERS(x) CSI_CR164_PIXEL_COUNTERS(x)
#define CSI_CSICR165_PIXEL_COUNTERS_MASK CSI_CR165_PIXEL_COUNTERS_MASK
#define CSI_CSICR165_PIXEL_COUNTERS_SHIFT CSI_CR165_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR165_PIXEL_COUNTERS(x) CSI_CR165_PIXEL_COUNTERS(x)
#define CSI_CSICR166_PIXEL_COUNTERS_MASK CSI_CR166_PIXEL_COUNTERS_MASK
#define CSI_CSICR166_PIXEL_COUNTERS_SHIFT CSI_CR166_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR166_PIXEL_COUNTERS(x) CSI_CR166_PIXEL_COUNTERS(x)
#define CSI_CSICR167_PIXEL_COUNTERS_MASK CSI_CR167_PIXEL_COUNTERS_MASK
#define CSI_CSICR167_PIXEL_COUNTERS_SHIFT CSI_CR167_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR167_PIXEL_COUNTERS(x) CSI_CR167_PIXEL_COUNTERS(x)
#define CSI_CSICR168_PIXEL_COUNTERS_MASK CSI_CR168_PIXEL_COUNTERS_MASK
#define CSI_CSICR168_PIXEL_COUNTERS_SHIFT CSI_CR168_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR168_PIXEL_COUNTERS(x) CSI_CR168_PIXEL_COUNTERS(x)
#define CSI_CSICR169_PIXEL_COUNTERS_MASK CSI_CR169_PIXEL_COUNTERS_MASK
#define CSI_CSICR169_PIXEL_COUNTERS_SHIFT CSI_CR169_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR169_PIXEL_COUNTERS(x) CSI_CR169_PIXEL_COUNTERS(x)
#define CSI_CSICR170_PIXEL_COUNTERS_MASK CSI_CR170_PIXEL_COUNTERS_MASK
#define CSI_CSICR170_PIXEL_COUNTERS_SHIFT CSI_CR170_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR170_PIXEL_COUNTERS(x) CSI_CR170_PIXEL_COUNTERS(x)
#define CSI_CSICR171_PIXEL_COUNTERS_MASK CSI_CR171_PIXEL_COUNTERS_MASK
#define CSI_CSICR171_PIXEL_COUNTERS_SHIFT CSI_CR171_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR171_PIXEL_COUNTERS(x) CSI_CR171_PIXEL_COUNTERS(x)
#define CSI_CSICR172_PIXEL_COUNTERS_MASK CSI_CR172_PIXEL_COUNTERS_MASK
#define CSI_CSICR172_PIXEL_COUNTERS_SHIFT CSI_CR172_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR172_PIXEL_COUNTERS(x) CSI_CR172_PIXEL_COUNTERS(x)
#define CSI_CSICR173_PIXEL_COUNTERS_MASK CSI_CR173_PIXEL_COUNTERS_MASK
#define CSI_CSICR173_PIXEL_COUNTERS_SHIFT CSI_CR173_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR173_PIXEL_COUNTERS(x) CSI_CR173_PIXEL_COUNTERS(x)
#define CSI_CSICR174_PIXEL_COUNTERS_MASK CSI_CR174_PIXEL_COUNTERS_MASK
#define CSI_CSICR174_PIXEL_COUNTERS_SHIFT CSI_CR174_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR174_PIXEL_COUNTERS(x) CSI_CR174_PIXEL_COUNTERS(x)
#define CSI_CSICR175_PIXEL_COUNTERS_MASK CSI_CR175_PIXEL_COUNTERS_MASK
#define CSI_CSICR175_PIXEL_COUNTERS_SHIFT CSI_CR175_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR175_PIXEL_COUNTERS(x) CSI_CR175_PIXEL_COUNTERS(x)
#define CSI_CSICR176_PIXEL_COUNTERS_MASK CSI_CR176_PIXEL_COUNTERS_MASK
#define CSI_CSICR176_PIXEL_COUNTERS_SHIFT CSI_CR176_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR176_PIXEL_COUNTERS(x) CSI_CR176_PIXEL_COUNTERS(x)
#define CSI_CSICR177_PIXEL_COUNTERS_MASK CSI_CR177_PIXEL_COUNTERS_MASK
#define CSI_CSICR177_PIXEL_COUNTERS_SHIFT CSI_CR177_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR177_PIXEL_COUNTERS(x) CSI_CR177_PIXEL_COUNTERS(x)
#define CSI_CSICR178_PIXEL_COUNTERS_MASK CSI_CR178_PIXEL_COUNTERS_MASK
#define CSI_CSICR178_PIXEL_COUNTERS_SHIFT CSI_CR178_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR178_PIXEL_COUNTERS(x) CSI_CR178_PIXEL_COUNTERS(x)
#define CSI_CSICR179_PIXEL_COUNTERS_MASK CSI_CR179_PIXEL_COUNTERS_MASK
#define CSI_CSICR179_PIXEL_COUNTERS_SHIFT CSI_CR179_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR179_PIXEL_COUNTERS(x) CSI_CR179_PIXEL_COUNTERS(x)
#define CSI_CSICR180_PIXEL_COUNTERS_MASK CSI_CR180_PIXEL_COUNTERS_MASK
#define CSI_CSICR180_PIXEL_COUNTERS_SHIFT CSI_CR180_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR180_PIXEL_COUNTERS(x) CSI_CR180_PIXEL_COUNTERS(x)
#define CSI_CSICR181_PIXEL_COUNTERS_MASK CSI_CR181_PIXEL_COUNTERS_MASK
#define CSI_CSICR181_PIXEL_COUNTERS_SHIFT CSI_CR181_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR181_PIXEL_COUNTERS(x) CSI_CR181_PIXEL_COUNTERS(x)
#define CSI_CSICR182_PIXEL_COUNTERS_MASK CSI_CR182_PIXEL_COUNTERS_MASK
#define CSI_CSICR182_PIXEL_COUNTERS_SHIFT CSI_CR182_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR182_PIXEL_COUNTERS(x) CSI_CR182_PIXEL_COUNTERS(x)
#define CSI_CSICR183_PIXEL_COUNTERS_MASK CSI_CR183_PIXEL_COUNTERS_MASK
#define CSI_CSICR183_PIXEL_COUNTERS_SHIFT CSI_CR183_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR183_PIXEL_COUNTERS(x) CSI_CR183_PIXEL_COUNTERS(x)
#define CSI_CSICR184_PIXEL_COUNTERS_MASK CSI_CR184_PIXEL_COUNTERS_MASK
#define CSI_CSICR184_PIXEL_COUNTERS_SHIFT CSI_CR184_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR184_PIXEL_COUNTERS(x) CSI_CR184_PIXEL_COUNTERS(x)
#define CSI_CSICR185_PIXEL_COUNTERS_MASK CSI_CR185_PIXEL_COUNTERS_MASK
#define CSI_CSICR185_PIXEL_COUNTERS_SHIFT CSI_CR185_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR185_PIXEL_COUNTERS(x) CSI_CR185_PIXEL_COUNTERS(x)
#define CSI_CSICR186_PIXEL_COUNTERS_MASK CSI_CR186_PIXEL_COUNTERS_MASK
#define CSI_CSICR186_PIXEL_COUNTERS_SHIFT CSI_CR186_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR186_PIXEL_COUNTERS(x) CSI_CR186_PIXEL_COUNTERS(x)
#define CSI_CSICR187_PIXEL_COUNTERS_MASK CSI_CR187_PIXEL_COUNTERS_MASK
#define CSI_CSICR187_PIXEL_COUNTERS_SHIFT CSI_CR187_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR187_PIXEL_COUNTERS(x) CSI_CR187_PIXEL_COUNTERS(x)
#define CSI_CSICR188_PIXEL_COUNTERS_MASK CSI_CR188_PIXEL_COUNTERS_MASK
#define CSI_CSICR188_PIXEL_COUNTERS_SHIFT CSI_CR188_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR188_PIXEL_COUNTERS(x) CSI_CR188_PIXEL_COUNTERS(x)
#define CSI_CSICR189_PIXEL_COUNTERS_MASK CSI_CR189_PIXEL_COUNTERS_MASK
#define CSI_CSICR189_PIXEL_COUNTERS_SHIFT CSI_CR189_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR189_PIXEL_COUNTERS(x) CSI_CR189_PIXEL_COUNTERS(x)
#define CSI_CSICR190_PIXEL_COUNTERS_MASK CSI_CR190_PIXEL_COUNTERS_MASK
#define CSI_CSICR190_PIXEL_COUNTERS_SHIFT CSI_CR190_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR190_PIXEL_COUNTERS(x) CSI_CR190_PIXEL_COUNTERS(x)
#define CSI_CSICR191_PIXEL_COUNTERS_MASK CSI_CR191_PIXEL_COUNTERS_MASK
#define CSI_CSICR191_PIXEL_COUNTERS_SHIFT CSI_CR191_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR191_PIXEL_COUNTERS(x) CSI_CR191_PIXEL_COUNTERS(x)
#define CSI_CSICR192_PIXEL_COUNTERS_MASK CSI_CR192_PIXEL_COUNTERS_MASK
#define CSI_CSICR192_PIXEL_COUNTERS_SHIFT CSI_CR192_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR192_PIXEL_COUNTERS(x) CSI_CR192_PIXEL_COUNTERS(x)
#define CSI_CSICR193_PIXEL_COUNTERS_MASK CSI_CR193_PIXEL_COUNTERS_MASK
#define CSI_CSICR193_PIXEL_COUNTERS_SHIFT CSI_CR193_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR193_PIXEL_COUNTERS(x) CSI_CR193_PIXEL_COUNTERS(x)
#define CSI_CSICR194_PIXEL_COUNTERS_MASK CSI_CR194_PIXEL_COUNTERS_MASK
#define CSI_CSICR194_PIXEL_COUNTERS_SHIFT CSI_CR194_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR194_PIXEL_COUNTERS(x) CSI_CR194_PIXEL_COUNTERS(x)
#define CSI_CSICR195_PIXEL_COUNTERS_MASK CSI_CR195_PIXEL_COUNTERS_MASK
#define CSI_CSICR195_PIXEL_COUNTERS_SHIFT CSI_CR195_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR195_PIXEL_COUNTERS(x) CSI_CR195_PIXEL_COUNTERS(x)
#define CSI_CSICR196_PIXEL_COUNTERS_MASK CSI_CR196_PIXEL_COUNTERS_MASK
#define CSI_CSICR196_PIXEL_COUNTERS_SHIFT CSI_CR196_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR196_PIXEL_COUNTERS(x) CSI_CR196_PIXEL_COUNTERS(x)
#define CSI_CSICR197_PIXEL_COUNTERS_MASK CSI_CR197_PIXEL_COUNTERS_MASK
#define CSI_CSICR197_PIXEL_COUNTERS_SHIFT CSI_CR197_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR197_PIXEL_COUNTERS(x) CSI_CR197_PIXEL_COUNTERS(x)
#define CSI_CSICR198_PIXEL_COUNTERS_MASK CSI_CR198_PIXEL_COUNTERS_MASK
#define CSI_CSICR198_PIXEL_COUNTERS_SHIFT CSI_CR198_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR198_PIXEL_COUNTERS(x) CSI_CR198_PIXEL_COUNTERS(x)
#define CSI_CSICR199_PIXEL_COUNTERS_MASK CSI_CR199_PIXEL_COUNTERS_MASK
#define CSI_CSICR199_PIXEL_COUNTERS_SHIFT CSI_CR199_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR199_PIXEL_COUNTERS(x) CSI_CR199_PIXEL_COUNTERS(x)
#define CSI_CSICR200_PIXEL_COUNTERS_MASK CSI_CR200_PIXEL_COUNTERS_MASK
#define CSI_CSICR200_PIXEL_COUNTERS_SHIFT CSI_CR200_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR200_PIXEL_COUNTERS(x) CSI_CR200_PIXEL_COUNTERS(x)
#define CSI_CSICR201_PIXEL_COUNTERS_MASK CSI_CR201_PIXEL_COUNTERS_MASK
#define CSI_CSICR201_PIXEL_COUNTERS_SHIFT CSI_CR201_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR201_PIXEL_COUNTERS(x) CSI_CR201_PIXEL_COUNTERS(x)
#define CSI_CSICR202_PIXEL_COUNTERS_MASK CSI_CR202_PIXEL_COUNTERS_MASK
#define CSI_CSICR202_PIXEL_COUNTERS_SHIFT CSI_CR202_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR202_PIXEL_COUNTERS(x) CSI_CR202_PIXEL_COUNTERS(x)
#define CSI_CSICR203_PIXEL_COUNTERS_MASK CSI_CR203_PIXEL_COUNTERS_MASK
#define CSI_CSICR203_PIXEL_COUNTERS_SHIFT CSI_CR203_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR203_PIXEL_COUNTERS(x) CSI_CR203_PIXEL_COUNTERS(x)
#define CSI_CSICR204_PIXEL_COUNTERS_MASK CSI_CR204_PIXEL_COUNTERS_MASK
#define CSI_CSICR204_PIXEL_COUNTERS_SHIFT CSI_CR204_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR204_PIXEL_COUNTERS(x) CSI_CR204_PIXEL_COUNTERS(x)
#define CSI_CSICR205_PIXEL_COUNTERS_MASK CSI_CR205_PIXEL_COUNTERS_MASK
#define CSI_CSICR205_PIXEL_COUNTERS_SHIFT CSI_CR205_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR205_PIXEL_COUNTERS(x) CSI_CR205_PIXEL_COUNTERS(x)
#define CSI_CSICR206_PIXEL_COUNTERS_MASK CSI_CR206_PIXEL_COUNTERS_MASK
#define CSI_CSICR206_PIXEL_COUNTERS_SHIFT CSI_CR206_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR206_PIXEL_COUNTERS(x) CSI_CR206_PIXEL_COUNTERS(x)
#define CSI_CSICR207_PIXEL_COUNTERS_MASK CSI_CR207_PIXEL_COUNTERS_MASK
#define CSI_CSICR207_PIXEL_COUNTERS_SHIFT CSI_CR207_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR207_PIXEL_COUNTERS(x) CSI_CR207_PIXEL_COUNTERS(x)
#define CSI_CSICR208_PIXEL_COUNTERS_MASK CSI_CR208_PIXEL_COUNTERS_MASK
#define CSI_CSICR208_PIXEL_COUNTERS_SHIFT CSI_CR208_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR208_PIXEL_COUNTERS(x) CSI_CR208_PIXEL_COUNTERS(x)
#define CSI_CSICR209_PIXEL_COUNTERS_MASK CSI_CR209_PIXEL_COUNTERS_MASK
#define CSI_CSICR209_PIXEL_COUNTERS_SHIFT CSI_CR209_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR209_PIXEL_COUNTERS(x) CSI_CR209_PIXEL_COUNTERS(x)
#define CSI_CSICR210_PIXEL_COUNTERS_MASK CSI_CR210_PIXEL_COUNTERS_MASK
#define CSI_CSICR210_PIXEL_COUNTERS_SHIFT CSI_CR210_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR210_PIXEL_COUNTERS(x) CSI_CR210_PIXEL_COUNTERS(x)
#define CSI_CSICR211_PIXEL_COUNTERS_MASK CSI_CR211_PIXEL_COUNTERS_MASK
#define CSI_CSICR211_PIXEL_COUNTERS_SHIFT CSI_CR211_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR211_PIXEL_COUNTERS(x) CSI_CR211_PIXEL_COUNTERS(x)
#define CSI_CSICR212_PIXEL_COUNTERS_MASK CSI_CR212_PIXEL_COUNTERS_MASK
#define CSI_CSICR212_PIXEL_COUNTERS_SHIFT CSI_CR212_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR212_PIXEL_COUNTERS(x) CSI_CR212_PIXEL_COUNTERS(x)
#define CSI_CSICR213_PIXEL_COUNTERS_MASK CSI_CR213_PIXEL_COUNTERS_MASK
#define CSI_CSICR213_PIXEL_COUNTERS_SHIFT CSI_CR213_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR213_PIXEL_COUNTERS(x) CSI_CR213_PIXEL_COUNTERS(x)
#define CSI_CSICR214_PIXEL_COUNTERS_MASK CSI_CR214_PIXEL_COUNTERS_MASK
#define CSI_CSICR214_PIXEL_COUNTERS_SHIFT CSI_CR214_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR214_PIXEL_COUNTERS(x) CSI_CR214_PIXEL_COUNTERS(x)
#define CSI_CSICR215_PIXEL_COUNTERS_MASK CSI_CR215_PIXEL_COUNTERS_MASK
#define CSI_CSICR215_PIXEL_COUNTERS_SHIFT CSI_CR215_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR215_PIXEL_COUNTERS(x) CSI_CR215_PIXEL_COUNTERS(x)
#define CSI_CSICR216_PIXEL_COUNTERS_MASK CSI_CR216_PIXEL_COUNTERS_MASK
#define CSI_CSICR216_PIXEL_COUNTERS_SHIFT CSI_CR216_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR216_PIXEL_COUNTERS(x) CSI_CR216_PIXEL_COUNTERS(x)
#define CSI_CSICR217_PIXEL_COUNTERS_MASK CSI_CR217_PIXEL_COUNTERS_MASK
#define CSI_CSICR217_PIXEL_COUNTERS_SHIFT CSI_CR217_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR217_PIXEL_COUNTERS(x) CSI_CR217_PIXEL_COUNTERS(x)
#define CSI_CSICR218_PIXEL_COUNTERS_MASK CSI_CR218_PIXEL_COUNTERS_MASK
#define CSI_CSICR218_PIXEL_COUNTERS_SHIFT CSI_CR218_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR218_PIXEL_COUNTERS(x) CSI_CR218_PIXEL_COUNTERS(x)
#define CSI_CSICR219_PIXEL_COUNTERS_MASK CSI_CR219_PIXEL_COUNTERS_MASK
#define CSI_CSICR219_PIXEL_COUNTERS_SHIFT CSI_CR219_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR219_PIXEL_COUNTERS(x) CSI_CR219_PIXEL_COUNTERS(x)
#define CSI_CSICR220_PIXEL_COUNTERS_MASK CSI_CR220_PIXEL_COUNTERS_MASK
#define CSI_CSICR220_PIXEL_COUNTERS_SHIFT CSI_CR220_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR220_PIXEL_COUNTERS(x) CSI_CR220_PIXEL_COUNTERS(x)
#define CSI_CSICR221_PIXEL_COUNTERS_MASK CSI_CR221_PIXEL_COUNTERS_MASK
#define CSI_CSICR221_PIXEL_COUNTERS_SHIFT CSI_CR221_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR221_PIXEL_COUNTERS(x) CSI_CR221_PIXEL_COUNTERS(x)
#define CSI_CSICR222_PIXEL_COUNTERS_MASK CSI_CR222_PIXEL_COUNTERS_MASK
#define CSI_CSICR222_PIXEL_COUNTERS_SHIFT CSI_CR222_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR222_PIXEL_COUNTERS(x) CSI_CR222_PIXEL_COUNTERS(x)
#define CSI_CSICR223_PIXEL_COUNTERS_MASK CSI_CR223_PIXEL_COUNTERS_MASK
#define CSI_CSICR223_PIXEL_COUNTERS_SHIFT CSI_CR223_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR223_PIXEL_COUNTERS(x) CSI_CR223_PIXEL_COUNTERS(x)
#define CSI_CSICR224_PIXEL_COUNTERS_MASK CSI_CR224_PIXEL_COUNTERS_MASK
#define CSI_CSICR224_PIXEL_COUNTERS_SHIFT CSI_CR224_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR224_PIXEL_COUNTERS(x) CSI_CR224_PIXEL_COUNTERS(x)
#define CSI_CSICR225_PIXEL_COUNTERS_MASK CSI_CR225_PIXEL_COUNTERS_MASK
#define CSI_CSICR225_PIXEL_COUNTERS_SHIFT CSI_CR225_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR225_PIXEL_COUNTERS(x) CSI_CR225_PIXEL_COUNTERS(x)
#define CSI_CSICR226_PIXEL_COUNTERS_MASK CSI_CR226_PIXEL_COUNTERS_MASK
#define CSI_CSICR226_PIXEL_COUNTERS_SHIFT CSI_CR226_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR226_PIXEL_COUNTERS(x) CSI_CR226_PIXEL_COUNTERS(x)
#define CSI_CSICR227_PIXEL_COUNTERS_MASK CSI_CR227_PIXEL_COUNTERS_MASK
#define CSI_CSICR227_PIXEL_COUNTERS_SHIFT CSI_CR227_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR227_PIXEL_COUNTERS(x) CSI_CR227_PIXEL_COUNTERS(x)
#define CSI_CSICR228_PIXEL_COUNTERS_MASK CSI_CR228_PIXEL_COUNTERS_MASK
#define CSI_CSICR228_PIXEL_COUNTERS_SHIFT CSI_CR228_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR228_PIXEL_COUNTERS(x) CSI_CR228_PIXEL_COUNTERS(x)
#define CSI_CSICR229_PIXEL_COUNTERS_MASK CSI_CR229_PIXEL_COUNTERS_MASK
#define CSI_CSICR229_PIXEL_COUNTERS_SHIFT CSI_CR229_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR229_PIXEL_COUNTERS(x) CSI_CR229_PIXEL_COUNTERS(x)
#define CSI_CSICR230_PIXEL_COUNTERS_MASK CSI_CR230_PIXEL_COUNTERS_MASK
#define CSI_CSICR230_PIXEL_COUNTERS_SHIFT CSI_CR230_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR230_PIXEL_COUNTERS(x) CSI_CR230_PIXEL_COUNTERS(x)
#define CSI_CSICR231_PIXEL_COUNTERS_MASK CSI_CR231_PIXEL_COUNTERS_MASK
#define CSI_CSICR231_PIXEL_COUNTERS_SHIFT CSI_CR231_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR231_PIXEL_COUNTERS(x) CSI_CR231_PIXEL_COUNTERS(x)
#define CSI_CSICR232_PIXEL_COUNTERS_MASK CSI_CR232_PIXEL_COUNTERS_MASK
#define CSI_CSICR232_PIXEL_COUNTERS_SHIFT CSI_CR232_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR232_PIXEL_COUNTERS(x) CSI_CR232_PIXEL_COUNTERS(x)
#define CSI_CSICR233_PIXEL_COUNTERS_MASK CSI_CR233_PIXEL_COUNTERS_MASK
#define CSI_CSICR233_PIXEL_COUNTERS_SHIFT CSI_CR233_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR233_PIXEL_COUNTERS(x) CSI_CR233_PIXEL_COUNTERS(x)
#define CSI_CSICR234_PIXEL_COUNTERS_MASK CSI_CR234_PIXEL_COUNTERS_MASK
#define CSI_CSICR234_PIXEL_COUNTERS_SHIFT CSI_CR234_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR234_PIXEL_COUNTERS(x) CSI_CR234_PIXEL_COUNTERS(x)
#define CSI_CSICR235_PIXEL_COUNTERS_MASK CSI_CR235_PIXEL_COUNTERS_MASK
#define CSI_CSICR235_PIXEL_COUNTERS_SHIFT CSI_CR235_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR235_PIXEL_COUNTERS(x) CSI_CR235_PIXEL_COUNTERS(x)
#define CSI_CSICR236_PIXEL_COUNTERS_MASK CSI_CR236_PIXEL_COUNTERS_MASK
#define CSI_CSICR236_PIXEL_COUNTERS_SHIFT CSI_CR236_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR236_PIXEL_COUNTERS(x) CSI_CR236_PIXEL_COUNTERS(x)
#define CSI_CSICR237_PIXEL_COUNTERS_MASK CSI_CR237_PIXEL_COUNTERS_MASK
#define CSI_CSICR237_PIXEL_COUNTERS_SHIFT CSI_CR237_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR237_PIXEL_COUNTERS(x) CSI_CR237_PIXEL_COUNTERS(x)
#define CSI_CSICR238_PIXEL_COUNTERS_MASK CSI_CR238_PIXEL_COUNTERS_MASK
#define CSI_CSICR238_PIXEL_COUNTERS_SHIFT CSI_CR238_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR238_PIXEL_COUNTERS(x) CSI_CR238_PIXEL_COUNTERS(x)
#define CSI_CSICR239_PIXEL_COUNTERS_MASK CSI_CR239_PIXEL_COUNTERS_MASK
#define CSI_CSICR239_PIXEL_COUNTERS_SHIFT CSI_CR239_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR239_PIXEL_COUNTERS(x) CSI_CR239_PIXEL_COUNTERS(x)
#define CSI_CSICR240_PIXEL_COUNTERS_MASK CSI_CR240_PIXEL_COUNTERS_MASK
#define CSI_CSICR240_PIXEL_COUNTERS_SHIFT CSI_CR240_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR240_PIXEL_COUNTERS(x) CSI_CR240_PIXEL_COUNTERS(x)
#define CSI_CSICR241_PIXEL_COUNTERS_MASK CSI_CR241_PIXEL_COUNTERS_MASK
#define CSI_CSICR241_PIXEL_COUNTERS_SHIFT CSI_CR241_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR241_PIXEL_COUNTERS(x) CSI_CR241_PIXEL_COUNTERS(x)
#define CSI_CSICR242_PIXEL_COUNTERS_MASK CSI_CR242_PIXEL_COUNTERS_MASK
#define CSI_CSICR242_PIXEL_COUNTERS_SHIFT CSI_CR242_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR242_PIXEL_COUNTERS(x) CSI_CR242_PIXEL_COUNTERS(x)
#define CSI_CSICR243_PIXEL_COUNTERS_MASK CSI_CR243_PIXEL_COUNTERS_MASK
#define CSI_CSICR243_PIXEL_COUNTERS_SHIFT CSI_CR243_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR243_PIXEL_COUNTERS(x) CSI_CR243_PIXEL_COUNTERS(x)
#define CSI_CSICR244_PIXEL_COUNTERS_MASK CSI_CR244_PIXEL_COUNTERS_MASK
#define CSI_CSICR244_PIXEL_COUNTERS_SHIFT CSI_CR244_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR244_PIXEL_COUNTERS(x) CSI_CR244_PIXEL_COUNTERS(x)
#define CSI_CSICR245_PIXEL_COUNTERS_MASK CSI_CR245_PIXEL_COUNTERS_MASK
#define CSI_CSICR245_PIXEL_COUNTERS_SHIFT CSI_CR245_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR245_PIXEL_COUNTERS(x) CSI_CR245_PIXEL_COUNTERS(x)
#define CSI_CSICR246_PIXEL_COUNTERS_MASK CSI_CR246_PIXEL_COUNTERS_MASK
#define CSI_CSICR246_PIXEL_COUNTERS_SHIFT CSI_CR246_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR246_PIXEL_COUNTERS(x) CSI_CR246_PIXEL_COUNTERS(x)
#define CSI_CSICR247_PIXEL_COUNTERS_MASK CSI_CR247_PIXEL_COUNTERS_MASK
#define CSI_CSICR247_PIXEL_COUNTERS_SHIFT CSI_CR247_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR247_PIXEL_COUNTERS(x) CSI_CR247_PIXEL_COUNTERS(x)
#define CSI_CSICR248_PIXEL_COUNTERS_MASK CSI_CR248_PIXEL_COUNTERS_MASK
#define CSI_CSICR248_PIXEL_COUNTERS_SHIFT CSI_CR248_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR248_PIXEL_COUNTERS(x) CSI_CR248_PIXEL_COUNTERS(x)
#define CSI_CSICR249_PIXEL_COUNTERS_MASK CSI_CR249_PIXEL_COUNTERS_MASK
#define CSI_CSICR249_PIXEL_COUNTERS_SHIFT CSI_CR249_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR249_PIXEL_COUNTERS(x) CSI_CR249_PIXEL_COUNTERS(x)
#define CSI_CSICR250_PIXEL_COUNTERS_MASK CSI_CR250_PIXEL_COUNTERS_MASK
#define CSI_CSICR250_PIXEL_COUNTERS_SHIFT CSI_CR250_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR250_PIXEL_COUNTERS(x) CSI_CR250_PIXEL_COUNTERS(x)
#define CSI_CSICR251_PIXEL_COUNTERS_MASK CSI_CR251_PIXEL_COUNTERS_MASK
#define CSI_CSICR251_PIXEL_COUNTERS_SHIFT CSI_CR251_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR251_PIXEL_COUNTERS(x) CSI_CR251_PIXEL_COUNTERS(x)
#define CSI_CSICR252_PIXEL_COUNTERS_MASK CSI_CR252_PIXEL_COUNTERS_MASK
#define CSI_CSICR252_PIXEL_COUNTERS_SHIFT CSI_CR252_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR252_PIXEL_COUNTERS(x) CSI_CR252_PIXEL_COUNTERS(x)
#define CSI_CSICR253_PIXEL_COUNTERS_MASK CSI_CR253_PIXEL_COUNTERS_MASK
#define CSI_CSICR253_PIXEL_COUNTERS_SHIFT CSI_CR253_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR253_PIXEL_COUNTERS(x) CSI_CR253_PIXEL_COUNTERS(x)
#define CSI_CSICR254_PIXEL_COUNTERS_MASK CSI_CR254_PIXEL_COUNTERS_MASK
#define CSI_CSICR254_PIXEL_COUNTERS_SHIFT CSI_CR254_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR254_PIXEL_COUNTERS(x) CSI_CR254_PIXEL_COUNTERS(x)
#define CSI_CSICR255_PIXEL_COUNTERS_MASK CSI_CR255_PIXEL_COUNTERS_MASK
#define CSI_CSICR255_PIXEL_COUNTERS_SHIFT CSI_CR255_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR255_PIXEL_COUNTERS(x) CSI_CR255_PIXEL_COUNTERS(x)
#define CSI_CSICR256_PIXEL_COUNTERS_MASK CSI_CR256_PIXEL_COUNTERS_MASK
#define CSI_CSICR256_PIXEL_COUNTERS_SHIFT CSI_CR256_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR256_PIXEL_COUNTERS(x) CSI_CR256_PIXEL_COUNTERS(x)
#define CSI_CSICR257_PIXEL_COUNTERS_MASK CSI_CR257_PIXEL_COUNTERS_MASK
#define CSI_CSICR257_PIXEL_COUNTERS_SHIFT CSI_CR257_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR257_PIXEL_COUNTERS(x) CSI_CR257_PIXEL_COUNTERS(x)
#define CSI_CSICR258_PIXEL_COUNTERS_MASK CSI_CR258_PIXEL_COUNTERS_MASK
#define CSI_CSICR258_PIXEL_COUNTERS_SHIFT CSI_CR258_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR258_PIXEL_COUNTERS(x) CSI_CR258_PIXEL_COUNTERS(x)
#define CSI_CSICR259_PIXEL_COUNTERS_MASK CSI_CR259_PIXEL_COUNTERS_MASK
#define CSI_CSICR259_PIXEL_COUNTERS_SHIFT CSI_CR259_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR259_PIXEL_COUNTERS(x) CSI_CR259_PIXEL_COUNTERS(x)
#define CSI_CSICR260_PIXEL_COUNTERS_MASK CSI_CR260_PIXEL_COUNTERS_MASK
#define CSI_CSICR260_PIXEL_COUNTERS_SHIFT CSI_CR260_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR260_PIXEL_COUNTERS(x) CSI_CR260_PIXEL_COUNTERS(x)
#define CSI_CSICR261_PIXEL_COUNTERS_MASK CSI_CR261_PIXEL_COUNTERS_MASK
#define CSI_CSICR261_PIXEL_COUNTERS_SHIFT CSI_CR261_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR261_PIXEL_COUNTERS(x) CSI_CR261_PIXEL_COUNTERS(x)
#define CSI_CSICR262_PIXEL_COUNTERS_MASK CSI_CR262_PIXEL_COUNTERS_MASK
#define CSI_CSICR262_PIXEL_COUNTERS_SHIFT CSI_CR262_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR262_PIXEL_COUNTERS(x) CSI_CR262_PIXEL_COUNTERS(x)
#define CSI_CSICR263_PIXEL_COUNTERS_MASK CSI_CR263_PIXEL_COUNTERS_MASK
#define CSI_CSICR263_PIXEL_COUNTERS_SHIFT CSI_CR263_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR263_PIXEL_COUNTERS(x) CSI_CR263_PIXEL_COUNTERS(x)
#define CSI_CSICR264_PIXEL_COUNTERS_MASK CSI_CR264_PIXEL_COUNTERS_MASK
#define CSI_CSICR264_PIXEL_COUNTERS_SHIFT CSI_CR264_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR264_PIXEL_COUNTERS(x) CSI_CR264_PIXEL_COUNTERS(x)
#define CSI_CSICR265_PIXEL_COUNTERS_MASK CSI_CR265_PIXEL_COUNTERS_MASK
#define CSI_CSICR265_PIXEL_COUNTERS_SHIFT CSI_CR265_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR265_PIXEL_COUNTERS(x) CSI_CR265_PIXEL_COUNTERS(x)
#define CSI_CSICR266_PIXEL_COUNTERS_MASK CSI_CR266_PIXEL_COUNTERS_MASK
#define CSI_CSICR266_PIXEL_COUNTERS_SHIFT CSI_CR266_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR266_PIXEL_COUNTERS(x) CSI_CR266_PIXEL_COUNTERS(x)
#define CSI_CSICR267_PIXEL_COUNTERS_MASK CSI_CR267_PIXEL_COUNTERS_MASK
#define CSI_CSICR267_PIXEL_COUNTERS_SHIFT CSI_CR267_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR267_PIXEL_COUNTERS(x) CSI_CR267_PIXEL_COUNTERS(x)
#define CSI_CSICR268_PIXEL_COUNTERS_MASK CSI_CR268_PIXEL_COUNTERS_MASK
#define CSI_CSICR268_PIXEL_COUNTERS_SHIFT CSI_CR268_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR268_PIXEL_COUNTERS(x) CSI_CR268_PIXEL_COUNTERS(x)
#define CSI_CSICR269_PIXEL_COUNTERS_MASK CSI_CR269_PIXEL_COUNTERS_MASK
#define CSI_CSICR269_PIXEL_COUNTERS_SHIFT CSI_CR269_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR269_PIXEL_COUNTERS(x) CSI_CR269_PIXEL_COUNTERS(x)
#define CSI_CSICR270_PIXEL_COUNTERS_MASK CSI_CR270_PIXEL_COUNTERS_MASK
#define CSI_CSICR270_PIXEL_COUNTERS_SHIFT CSI_CR270_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR270_PIXEL_COUNTERS(x) CSI_CR270_PIXEL_COUNTERS(x)
#define CSI_CSICR271_PIXEL_COUNTERS_MASK CSI_CR271_PIXEL_COUNTERS_MASK
#define CSI_CSICR271_PIXEL_COUNTERS_SHIFT CSI_CR271_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR271_PIXEL_COUNTERS(x) CSI_CR271_PIXEL_COUNTERS(x)
#define CSI_CSICR272_PIXEL_COUNTERS_MASK CSI_CR272_PIXEL_COUNTERS_MASK
#define CSI_CSICR272_PIXEL_COUNTERS_SHIFT CSI_CR272_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR272_PIXEL_COUNTERS(x) CSI_CR272_PIXEL_COUNTERS(x)
#define CSI_CSICR273_PIXEL_COUNTERS_MASK CSI_CR273_PIXEL_COUNTERS_MASK
#define CSI_CSICR273_PIXEL_COUNTERS_SHIFT CSI_CR273_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR273_PIXEL_COUNTERS(x) CSI_CR273_PIXEL_COUNTERS(x)
#define CSI_CSICR274_PIXEL_COUNTERS_MASK CSI_CR274_PIXEL_COUNTERS_MASK
#define CSI_CSICR274_PIXEL_COUNTERS_SHIFT CSI_CR274_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR274_PIXEL_COUNTERS(x) CSI_CR274_PIXEL_COUNTERS(x)
#define CSI_CSICR275_PIXEL_COUNTERS_MASK CSI_CR275_PIXEL_COUNTERS_MASK
#define CSI_CSICR275_PIXEL_COUNTERS_SHIFT CSI_CR275_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR275_PIXEL_COUNTERS(x) CSI_CR275_PIXEL_COUNTERS(x)
#define CSI_CSICR276_PIXEL_COUNTERS_MASK CSI_CR276_PIXEL_COUNTERS_MASK
#define CSI_CSICR276_PIXEL_COUNTERS_SHIFT CSI_CR276_PIXEL_COUNTERS_SHIFT
#define CSI_CSICR276_PIXEL_COUNTERS(x) CSI_CR276_PIXEL_COUNTERS(x)
/*!
* @}
*/ /* end of group CSI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DAC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
* @{
*/
/** DAC - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version Identifier Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__O uint32_t DATA; /**< DAC Data Register, offset: 0x8 */
__IO uint32_t CR; /**< DAC Status and Control Register, offset: 0xC */
__I uint32_t PTR; /**< DAC FIFO Pointer Register, offset: 0x10 */
__IO uint32_t CR2; /**< DAC Status and Control Register 2, offset: 0x14 */
} DAC_Type;
/* ----------------------------------------------------------------------------
-- DAC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DAC_Register_Masks DAC Register Masks
* @{
*/
/*! @name VERID - Version Identifier Register */
/*! @{ */
#define DAC_VERID_FEATURE_MASK (0xFFFFU)
#define DAC_VERID_FEATURE_SHIFT (0U)
/*! FEATURE - Feature Identification Number
* 0b0000000000000000..Standard feature set
* 0b0000000000000001..C40 feature set
* 0b0000000000000010..5V DAC feature set
* 0b0000000000000100..ADC BIST feature set
*/
#define DAC_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_FEATURE_SHIFT)) & DAC_VERID_FEATURE_MASK)
#define DAC_VERID_MINOR_MASK (0xFF0000U)
#define DAC_VERID_MINOR_SHIFT (16U)
/*! MINOR - Minor version number
*/
#define DAC_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MINOR_SHIFT)) & DAC_VERID_MINOR_MASK)
#define DAC_VERID_MAJOR_MASK (0xFF000000U)
#define DAC_VERID_MAJOR_SHIFT (24U)
/*! MAJOR - Major version number
*/
#define DAC_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << DAC_VERID_MAJOR_SHIFT)) & DAC_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define DAC_PARAM_FIFOSZ_MASK (0x7U)
#define DAC_PARAM_FIFOSZ_SHIFT (0U)
/*! FIFOSZ - FIFO size
* 0b000..FIFO depth is 2
* 0b001..FIFO depth is 4
* 0b010..FIFO depth is 8
* 0b011..FIFO depth is 16
* 0b100..FIFO depth is 32
* 0b101..FIFO depth is 64
* 0b110..FIFO depth is 128
* 0b111..FIFO depth is 256
*/
#define DAC_PARAM_FIFOSZ(x) (((uint32_t)(((uint32_t)(x)) << DAC_PARAM_FIFOSZ_SHIFT)) & DAC_PARAM_FIFOSZ_MASK)
/*! @} */
/*! @name DATA - DAC Data Register */
/*! @{ */
#define DAC_DATA_DATA0_MASK (0xFFFU)
#define DAC_DATA_DATA0_SHIFT (0U)
/*! DATA0 - FIFO DATA0
*/
#define DAC_DATA_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DAC_DATA_DATA0_SHIFT)) & DAC_DATA_DATA0_MASK)
/*! @} */
/*! @name CR - DAC Status and Control Register */
/*! @{ */
#define DAC_CR_FULLF_MASK (0x1U)
#define DAC_CR_FULLF_SHIFT (0U)
/*! FULLF - Full Flag
* 0b0..FIFO is not full.
* 0b1..FIFO is full.
*/
#define DAC_CR_FULLF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLF_SHIFT)) & DAC_CR_FULLF_MASK)
#define DAC_CR_NEMPTF_MASK (0x2U)
#define DAC_CR_NEMPTF_SHIFT (1U)
/*! NEMPTF - Nearly Empty Flag
* 0b0..More than one data is available in the FIFO.
* 0b1..One data is available in the FIFO.
*/
#define DAC_CR_NEMPTF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_NEMPTF_SHIFT)) & DAC_CR_NEMPTF_MASK)
#define DAC_CR_WMF_MASK (0x4U)
#define DAC_CR_WMF_SHIFT (2U)
/*! WMF - FIFO Watermark Status Flag
* 0b0..The DAC buffer read pointer has not reached the watermark level.
* 0b1..The DAC buffer read pointer has reached the watermark level.
*/
#define DAC_CR_WMF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WMF_SHIFT)) & DAC_CR_WMF_MASK)
#define DAC_CR_UDFF_MASK (0x8U)
#define DAC_CR_UDFF_SHIFT (3U)
/*! UDFF - Underflow Flag
* 0b0..No underflow has occurred since the last time the flag was cleared.
* 0b1..At least one trigger underflow has occurred since the last time the flag was cleared.
*/
#define DAC_CR_UDFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UDFF_SHIFT)) & DAC_CR_UDFF_MASK)
#define DAC_CR_OVFF_MASK (0x10U)
#define DAC_CR_OVFF_SHIFT (4U)
/*! OVFF - Overflow Flag
* 0b0..No overflow has occurred since the last time the flag was cleared.
* 0b1..At least one FIFO overflow has occurred since the last time the flag was cleared.
*/
#define DAC_CR_OVFF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_OVFF_SHIFT)) & DAC_CR_OVFF_MASK)
#define DAC_CR_FULLIE_MASK (0x100U)
#define DAC_CR_FULLIE_SHIFT (8U)
/*! FULLIE - Full Interrupt Enable
* 0b0..FIFO Full interrupt is disabled.
* 0b1..FIFO Full interrupt is enabled.
*/
#define DAC_CR_FULLIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FULLIE_SHIFT)) & DAC_CR_FULLIE_MASK)
#define DAC_CR_EMPTIE_MASK (0x200U)
#define DAC_CR_EMPTIE_SHIFT (9U)
/*! EMPTIE - Nearly Empty Interrupt Enable
* 0b0..FIFO Nearly Empty interrupt is disabled.
* 0b1..FIFO Nearly Empty interrupt is enabled.
*/
#define DAC_CR_EMPTIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_EMPTIE_SHIFT)) & DAC_CR_EMPTIE_MASK)
#define DAC_CR_WTMIE_MASK (0x400U)
#define DAC_CR_WTMIE_SHIFT (10U)
/*! WTMIE - Watermark Interrupt Enable
* 0b0..Watermark interrupt is disabled.
* 0b1..Watermark interrupt is enabled.
*/
#define DAC_CR_WTMIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WTMIE_SHIFT)) & DAC_CR_WTMIE_MASK)
#define DAC_CR_SWTRG_MASK (0x1000U)
#define DAC_CR_SWTRG_SHIFT (12U)
/*! SWTRG - DAC Software Trigger
* 0b0..The DAC soft trigger is not valid.
* 0b1..The DAC soft trigger is valid.
*/
#define DAC_CR_SWTRG(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWTRG_SHIFT)) & DAC_CR_SWTRG_MASK)
#define DAC_CR_TRGSEL_MASK (0x2000U)
#define DAC_CR_TRGSEL_SHIFT (13U)
/*! TRGSEL - DAC Trigger Select
* 0b0..The DAC hardware trigger is selected.
* 0b1..The DAC software trigger is selected.
*/
#define DAC_CR_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_TRGSEL_SHIFT)) & DAC_CR_TRGSEL_MASK)
#define DAC_CR_DACRFS_MASK (0x4000U)
#define DAC_CR_DACRFS_SHIFT (14U)
/*! DACRFS - DAC Reference Select
* 0b0..The DAC selects DACREF_1 as the reference voltage.
* 0b1..The DAC selects DACREF_2 as the reference voltage.
*/
#define DAC_CR_DACRFS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACRFS_SHIFT)) & DAC_CR_DACRFS_MASK)
#define DAC_CR_DACEN_MASK (0x8000U)
#define DAC_CR_DACEN_SHIFT (15U)
/*! DACEN - DAC Enable
* 0b0..The DAC system is disabled.
* 0b1..The DAC system is enabled.
*/
#define DAC_CR_DACEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DACEN_SHIFT)) & DAC_CR_DACEN_MASK)
#define DAC_CR_FIFOEN_MASK (0x10000U)
#define DAC_CR_FIFOEN_SHIFT (16U)
/*! FIFOEN - FIFO Enable
* 0b0..FIFO is disabled and only one level buffer is enabled. Any data written from this buffer goes to conversion.
* 0b1..FIFO is enabled. Data will first read from FIFO to buffer then go to conversion.
*/
#define DAC_CR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFOEN_SHIFT)) & DAC_CR_FIFOEN_MASK)
#define DAC_CR_SWMD_MASK (0x20000U)
#define DAC_CR_SWMD_SHIFT (17U)
/*! SWMD - DAC FIFO Mode Select
* 0b0..Normal mode
* 0b1..Swing back mode
*/
#define DAC_CR_SWMD(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWMD_SHIFT)) & DAC_CR_SWMD_MASK)
#define DAC_CR_UVIE_MASK (0x40000U)
#define DAC_CR_UVIE_SHIFT (18U)
/*! UVIE - Underflow and overflow interrupt enable
* 0b0..Underflow and overflow interrupt is disabled.
* 0b1..Underflow and overflow interrupt is enabled.
*/
#define DAC_CR_UVIE(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_UVIE_SHIFT)) & DAC_CR_UVIE_MASK)
#define DAC_CR_FIFORST_MASK (0x200000U)
#define DAC_CR_FIFORST_SHIFT (21U)
/*! FIFORST - FIFO Reset
* 0b0..No effect
* 0b1..FIFO reset
*/
#define DAC_CR_FIFORST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_FIFORST_SHIFT)) & DAC_CR_FIFORST_MASK)
#define DAC_CR_SWRST_MASK (0x400000U)
#define DAC_CR_SWRST_SHIFT (22U)
/*! SWRST - Software reset
*/
#define DAC_CR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_SWRST_SHIFT)) & DAC_CR_SWRST_MASK)
#define DAC_CR_DMAEN_MASK (0x800000U)
#define DAC_CR_DMAEN_SHIFT (23U)
/*! DMAEN - DMA Enable Select
* 0b0..DMA is disabled.
* 0b1..DMA is enabled. When DMA is enabled, the DMA request will be generated by original interrupts. The
* interrupts will not be presented on this module at the same time.
*/
#define DAC_CR_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_DMAEN_SHIFT)) & DAC_CR_DMAEN_MASK)
#define DAC_CR_WML_MASK (0xFF000000U)
#define DAC_CR_WML_SHIFT (24U)
/*! WML - Watermark Level Select
*/
#define DAC_CR_WML(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR_WML_SHIFT)) & DAC_CR_WML_MASK)
/*! @} */
/*! @name PTR - DAC FIFO Pointer Register */
/*! @{ */
#define DAC_PTR_DACWFP_MASK (0xFFU)
#define DAC_PTR_DACWFP_SHIFT (0U)
/*! DACWFP - DACWFP
*/
#define DAC_PTR_DACWFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACWFP_SHIFT)) & DAC_PTR_DACWFP_MASK)
#define DAC_PTR_DACRFP_MASK (0xFF0000U)
#define DAC_PTR_DACRFP_SHIFT (16U)
/*! DACRFP - DACRFP
*/
#define DAC_PTR_DACRFP(x) (((uint32_t)(((uint32_t)(x)) << DAC_PTR_DACRFP_SHIFT)) & DAC_PTR_DACRFP_MASK)
/*! @} */
/*! @name CR2 - DAC Status and Control Register 2 */
/*! @{ */
#define DAC_CR2_BFEN_MASK (0x1U)
#define DAC_CR2_BFEN_SHIFT (0U)
/*! BFEN - Buffer Enable
* 0b0..Opamp is not used as buffer
* 0b1..Opamp is used as buffer
*/
#define DAC_CR2_BFEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFEN_SHIFT)) & DAC_CR2_BFEN_MASK)
#define DAC_CR2_OEN_MASK (0x2U)
#define DAC_CR2_OEN_SHIFT (1U)
/*! OEN - Optional Enable
* 0b0..Output buffer is not bypassed
* 0b1..Output buffer is bypassed
*/
#define DAC_CR2_OEN(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_OEN_SHIFT)) & DAC_CR2_OEN_MASK)
#define DAC_CR2_BFMS_MASK (0x4U)
#define DAC_CR2_BFMS_SHIFT (2U)
/*! BFMS - Buffer Middle Speed Select
* 0b0..Buffer middle speed not selected
* 0b1..Buffer middle speed selected
*/
#define DAC_CR2_BFMS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFMS_SHIFT)) & DAC_CR2_BFMS_MASK)
#define DAC_CR2_BFHS_MASK (0x8U)
#define DAC_CR2_BFHS_SHIFT (3U)
/*! BFHS - Buffer High Speed Select
* 0b0..Buffer high speed not selected
* 0b1..Buffer high speed selected
*/
#define DAC_CR2_BFHS(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_BFHS_SHIFT)) & DAC_CR2_BFHS_MASK)
#define DAC_CR2_IREF2_MASK (0x10U)
#define DAC_CR2_IREF2_SHIFT (4U)
/*! IREF2 - Internal PTAT (Proportional To Absolute Temperature) Current Reference Select
* 0b0..Internal PTAT Current Reference not selected
* 0b1..Internal PTAT Current Reference selected
*/
#define DAC_CR2_IREF2(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF2_SHIFT)) & DAC_CR2_IREF2_MASK)
#define DAC_CR2_IREF1_MASK (0x20U)
#define DAC_CR2_IREF1_SHIFT (5U)
/*! IREF1 - Internal ZTC (Zero Temperature Coefficient) Current Reference Select
* 0b0..Internal ZTC Current Reference not selected
* 0b1..Internal ZTC Current Reference selected
*/
#define DAC_CR2_IREF1(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF1_SHIFT)) & DAC_CR2_IREF1_MASK)
#define DAC_CR2_IREF_MASK (0x40U)
#define DAC_CR2_IREF_SHIFT (6U)
/*! IREF - Internal Current Reference Select
* 0b0..Internal Current Reference not selected
* 0b1..Internal Current Reference selected
*/
#define DAC_CR2_IREF(x) (((uint32_t)(((uint32_t)(x)) << DAC_CR2_IREF_SHIFT)) & DAC_CR2_IREF_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DAC_Register_Masks */
/* DAC - Peripheral instance base addresses */
/** Peripheral DAC base address */
#define DAC_BASE (0x40064000u)
/** Peripheral DAC base pointer */
#define DAC ((DAC_Type *)DAC_BASE)
/** Array initializer of DAC peripheral base addresses */
#define DAC_BASE_ADDRS { DAC_BASE }
/** Array initializer of DAC peripheral base pointers */
#define DAC_BASE_PTRS { DAC }
/** Interrupt vectors for the DAC peripheral type */
#define DAC_IRQS { DAC_IRQn }
/*!
* @}
*/ /* end of group DAC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DCDC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DCDC_Peripheral_Access_Layer DCDC Peripheral Access Layer
* @{
*/
/** DCDC - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL0; /**< DCDC Control Register 0, offset: 0x0 */
__IO uint32_t CTRL1; /**< DCDC Control Register 1, offset: 0x4 */
__IO uint32_t REG0; /**< DCDC Register 0, offset: 0x8 */
__IO uint32_t REG1; /**< DCDC Register 1, offset: 0xC */
__IO uint32_t REG2; /**< DCDC Register 2, offset: 0x10 */
__IO uint32_t REG3; /**< DCDC Register 3, offset: 0x14 */
__IO uint32_t REG4; /**< DCDC Register 4, offset: 0x18 */
__IO uint32_t REG5; /**< DCDC Register 5, offset: 0x1C */
__IO uint32_t REG6; /**< DCDC Register 6, offset: 0x20 */
__IO uint32_t REG7; /**< DCDC Register 7, offset: 0x24 */
__IO uint32_t REG7P; /**< DCDC Register 7 plus, offset: 0x28 */
__IO uint32_t REG8; /**< DCDC Register 8, offset: 0x2C */
__IO uint32_t REG9; /**< DCDC Register 9, offset: 0x30 */
__IO uint32_t REG10; /**< DCDC Register 10, offset: 0x34 */
__IO uint32_t REG11; /**< DCDC Register 11, offset: 0x38 */
__IO uint32_t REG12; /**< DCDC Register 12, offset: 0x3C */
__IO uint32_t REG13; /**< DCDC Register 13, offset: 0x40 */
__IO uint32_t REG14; /**< DCDC Register 14, offset: 0x44 */
__IO uint32_t REG15; /**< DCDC Register 15, offset: 0x48 */
__IO uint32_t REG16; /**< DCDC Register 16, offset: 0x4C */
__IO uint32_t REG17; /**< DCDC Register 17, offset: 0x50 */
__IO uint32_t REG18; /**< DCDC Register 18, offset: 0x54 */
__IO uint32_t REG19; /**< DCDC Register 19, offset: 0x58 */
__IO uint32_t REG20; /**< DCDC Register 20, offset: 0x5C */
__IO uint32_t REG21; /**< DCDC Register 21, offset: 0x60 */
__IO uint32_t REG22; /**< DCDC Register 22, offset: 0x64 */
__IO uint32_t REG23; /**< DCDC Register 23, offset: 0x68 */
__IO uint32_t REG24; /**< DCDC Register 24, offset: 0x6C */
} DCDC_Type;
/* ----------------------------------------------------------------------------
-- DCDC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DCDC_Register_Masks DCDC Register Masks
* @{
*/
/*! @name CTRL0 - DCDC Control Register 0 */
/*! @{ */
#define DCDC_CTRL0_ENABLE_MASK (0x1U)
#define DCDC_CTRL0_ENABLE_SHIFT (0U)
/*! ENABLE
* 0b0..Disable (Bypass)
* 0b1..Enable
*/
#define DCDC_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_SHIFT)) & DCDC_CTRL0_ENABLE_MASK)
#define DCDC_CTRL0_DIG_EN_MASK (0x2U)
#define DCDC_CTRL0_DIG_EN_SHIFT (1U)
/*! DIG_EN
* 0b0..Reserved
* 0b1..Enable
*/
#define DCDC_CTRL0_DIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DIG_EN_SHIFT)) & DCDC_CTRL0_DIG_EN_MASK)
#define DCDC_CTRL0_STBY_EN_MASK (0x4U)
#define DCDC_CTRL0_STBY_EN_SHIFT (2U)
/*! STBY_EN
* 0b1..Enter into standby mode
*/
#define DCDC_CTRL0_STBY_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_EN_SHIFT)) & DCDC_CTRL0_STBY_EN_MASK)
#define DCDC_CTRL0_LP_MODE_EN_MASK (0x8U)
#define DCDC_CTRL0_LP_MODE_EN_SHIFT (3U)
/*! LP_MODE_EN
* 0b1..Enter into low-power mode
*/
#define DCDC_CTRL0_LP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_LP_MODE_EN_MASK)
#define DCDC_CTRL0_STBY_LP_MODE_EN_MASK (0x10U)
#define DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT (4U)
/*! STBY_LP_MODE_EN
* 0b0..Disable DCDC entry into low-power mode from a GPC standby request
* 0b1..Enable DCDC to enter into low-power mode from a GPC standby request
*/
#define DCDC_CTRL0_STBY_LP_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_STBY_LP_MODE_EN_SHIFT)) & DCDC_CTRL0_STBY_LP_MODE_EN_MASK)
#define DCDC_CTRL0_ENABLE_DCDC_CNT_MASK (0x20U)
#define DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT (5U)
/*! ENABLE_DCDC_CNT - Enable internal count for DCDC_OK timeout
* 0b0..Wait DCDC_OK for ACK
* 0b1..Enable internal count for DCDC_OK timeout
*/
#define DCDC_CTRL0_ENABLE_DCDC_CNT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_ENABLE_DCDC_CNT_SHIFT)) & DCDC_CTRL0_ENABLE_DCDC_CNT_MASK)
#define DCDC_CTRL0_TRIM_HOLD_MASK (0x40U)
#define DCDC_CTRL0_TRIM_HOLD_SHIFT (6U)
/*! TRIM_HOLD - Hold trim input
* 0b0..Sample trim input
* 0b1..Hold trim input
*/
#define DCDC_CTRL0_TRIM_HOLD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_TRIM_HOLD_SHIFT)) & DCDC_CTRL0_TRIM_HOLD_MASK)
#define DCDC_CTRL0_DEBUG_BITS_MASK (0x7FF80000U)
#define DCDC_CTRL0_DEBUG_BITS_SHIFT (19U)
/*! DEBUG_BITS - DEBUG_BITS[11:0]
*/
#define DCDC_CTRL0_DEBUG_BITS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_DEBUG_BITS_SHIFT)) & DCDC_CTRL0_DEBUG_BITS_MASK)
#define DCDC_CTRL0_CONTROL_MODE_MASK (0x80000000U)
#define DCDC_CTRL0_CONTROL_MODE_SHIFT (31U)
/*! CONTROL_MODE - Control mode
* 0b0..Software control mode
* 0b1..Hardware control mode (controlled by GPC Setpoints)
*/
#define DCDC_CTRL0_CONTROL_MODE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL0_CONTROL_MODE_SHIFT)) & DCDC_CTRL0_CONTROL_MODE_MASK)
/*! @} */
/*! @name CTRL1 - DCDC Control Register 1 */
/*! @{ */
#define DCDC_CTRL1_VDD1P8CTRL_TRG_MASK (0x1FU)
#define DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT (0U)
/*! VDD1P8CTRL_TRG
* 0b11111..2.275V
* 0b01100..1.8V
* 0b00000..1.5V
*/
#define DCDC_CTRL1_VDD1P8CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_TRG_MASK)
#define DCDC_CTRL1_VDD1P0CTRL_TRG_MASK (0x1F00U)
#define DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT (8U)
/*! VDD1P0CTRL_TRG
* 0b11111..1.375V
* 0b10000..1.0V
* 0b00000..0.6V
*/
#define DCDC_CTRL1_VDD1P0CTRL_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_TRG_MASK)
#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK (0x1F0000U)
#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT (16U)
/*! VDD1P8CTRL_STBY_TRG
* 0b11111..2.3V
* 0b01011..1.8V
* 0b00000..1.525V
*/
#define DCDC_CTRL1_VDD1P8CTRL_STBY_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P8CTRL_STBY_TRG_MASK)
#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK (0x1F000000U)
#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT (24U)
/*! VDD1P0CTRL_STBY_TRG
* 0b11111..1.4V
* 0b01111..1.0V
* 0b00000..0.625V
*/
#define DCDC_CTRL1_VDD1P0CTRL_STBY_TRG(x) (((uint32_t)(((uint32_t)(x)) << DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_SHIFT)) & DCDC_CTRL1_VDD1P0CTRL_STBY_TRG_MASK)
/*! @} */
/*! @name REG0 - DCDC Register 0 */
/*! @{ */
#define DCDC_REG0_PWD_ZCD_MASK (0x1U)
#define DCDC_REG0_PWD_ZCD_SHIFT (0U)
/*! PWD_ZCD - Power Down Zero Cross Detection
* 0b0..Zero cross detetion function powered up
* 0b1..Zero cross detetion function powered down
*/
#define DCDC_REG0_PWD_ZCD(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_ZCD_SHIFT)) & DCDC_REG0_PWD_ZCD_MASK)
#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK (0x2U)
#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT (1U)
/*! DISABLE_AUTO_CLK_SWITCH - Disable Auto Clock Switch
* 0b0..If DISABLE_AUTO_CLK_SWITCH is set to 0 and 24M xtal is OK, the clock source will switch from internal
* ring oscillator to 24M xtal automatically
* 0b1..If DISABLE_AUTO_CLK_SWITCH is set to 1, SEL_CLK will determine which clock source the DCDC uses
*/
#define DCDC_REG0_DISABLE_AUTO_CLK_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_SHIFT)) & DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK)
#define DCDC_REG0_SEL_CLK_MASK (0x4U)
#define DCDC_REG0_SEL_CLK_SHIFT (2U)
/*! SEL_CLK - Select Clock
* 0b0..DCDC uses internal ring oscillator
* 0b1..DCDC uses 24M xtal
*/
#define DCDC_REG0_SEL_CLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_SEL_CLK_SHIFT)) & DCDC_REG0_SEL_CLK_MASK)
#define DCDC_REG0_PWD_OSC_INT_MASK (0x8U)
#define DCDC_REG0_PWD_OSC_INT_SHIFT (3U)
/*! PWD_OSC_INT - Power down internal ring oscillator
* 0b0..Internal ring oscillator powered up
* 0b1..Internal ring oscillator powered down
*/
#define DCDC_REG0_PWD_OSC_INT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OSC_INT_SHIFT)) & DCDC_REG0_PWD_OSC_INT_MASK)
#define DCDC_REG0_PWD_CUR_SNS_CMP_MASK (0x10U)
#define DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT (4U)
/*! PWD_CUR_SNS_CMP - Power down signal of the current detector
* 0b0..Current Detector powered up
* 0b1..Current Detector powered down
*/
#define DCDC_REG0_PWD_CUR_SNS_CMP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CUR_SNS_CMP_SHIFT)) & DCDC_REG0_PWD_CUR_SNS_CMP_MASK)
#define DCDC_REG0_CUR_SNS_THRSH_MASK (0xE0U)
#define DCDC_REG0_CUR_SNS_THRSH_SHIFT (5U)
/*! CUR_SNS_THRSH - Current Sense (detector) Threshold
*/
#define DCDC_REG0_CUR_SNS_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_CUR_SNS_THRSH_SHIFT)) & DCDC_REG0_CUR_SNS_THRSH_MASK)
#define DCDC_REG0_PWD_OVERCUR_DET_MASK (0x100U)
#define DCDC_REG0_PWD_OVERCUR_DET_SHIFT (8U)
/*! PWD_OVERCUR_DET - Power down overcurrent detection comparator
* 0b0..Overcurrent detection comparator is enabled
* 0b1..Overcurrent detection comparator is disabled
*/
#define DCDC_REG0_PWD_OVERCUR_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_OVERCUR_DET_SHIFT)) & DCDC_REG0_PWD_OVERCUR_DET_MASK)
#define DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK (0x800U)
#define DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT (11U)
/*! PWD_CMP_DCDC_IN_DET
* 0b0..Low voltage detection comparator is enabled
* 0b1..Low voltage detection comparator is disabled
*/
#define DCDC_REG0_PWD_CMP_DCDC_IN_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_DCDC_IN_DET_SHIFT)) & DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK)
#define DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK (0x10000U)
#define DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT (16U)
/*! PWD_HIGH_VDD1P8_DET - Power Down High Voltage Detection for VDD1P8
* 0b0..Overvoltage detection comparator for the VDD1P8 output is enabled
* 0b1..Overvoltage detection comparator for the VDD1P8 output is disabled
*/
#define DCDC_REG0_PWD_HIGH_VDD1P8_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P8_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK)
#define DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK (0x20000U)
#define DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT (17U)
/*! PWD_HIGH_VDD1P0_DET - Power Down High Voltage Detection for VDD1P0
* 0b0..Overvoltage detection comparator for the VDD1P0 output is enabled
* 0b1..Overvoltage detection comparator for the VDD1P0 output is disabled
*/
#define DCDC_REG0_PWD_HIGH_VDD1P0_DET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_HIGH_VDD1P0_DET_SHIFT)) & DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK)
#define DCDC_REG0_LP_HIGH_HYS_MASK (0x200000U)
#define DCDC_REG0_LP_HIGH_HYS_SHIFT (21U)
/*! LP_HIGH_HYS - Low Power High Hysteric Value
* 0b0..Adjust hysteretic value in low power to 12.5mV
* 0b1..Adjust hysteretic value in low power to 25mV
*/
#define DCDC_REG0_LP_HIGH_HYS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_LP_HIGH_HYS_SHIFT)) & DCDC_REG0_LP_HIGH_HYS_MASK)
#define DCDC_REG0_PWD_CMP_OFFSET_MASK (0x4000000U)
#define DCDC_REG0_PWD_CMP_OFFSET_SHIFT (26U)
/*! PWD_CMP_OFFSET - power down the out-of-range detection comparator
* 0b0..Out-of-range comparator powered up
* 0b1..Out-of-range comparator powered down
*/
#define DCDC_REG0_PWD_CMP_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_PWD_CMP_OFFSET_SHIFT)) & DCDC_REG0_PWD_CMP_OFFSET_MASK)
#define DCDC_REG0_XTALOK_DISABLE_MASK (0x8000000U)
#define DCDC_REG0_XTALOK_DISABLE_SHIFT (27U)
/*! XTALOK_DISABLE - Disable xtalok detection circuit
* 0b0..Enable xtalok detection circuit
* 0b1..Disable xtalok detection circuit and always outputs OK signal "1"
*/
#define DCDC_REG0_XTALOK_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTALOK_DISABLE_SHIFT)) & DCDC_REG0_XTALOK_DISABLE_MASK)
#define DCDC_REG0_XTAL_24M_OK_MASK (0x20000000U)
#define DCDC_REG0_XTAL_24M_OK_SHIFT (29U)
/*! XTAL_24M_OK - 24M XTAL OK
* 0b0..DCDC uses internal ring oscillator
* 0b1..DCDC uses xtal 24M
*/
#define DCDC_REG0_XTAL_24M_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_XTAL_24M_OK_SHIFT)) & DCDC_REG0_XTAL_24M_OK_MASK)
#define DCDC_REG0_STS_DC_OK_MASK (0x80000000U)
#define DCDC_REG0_STS_DC_OK_SHIFT (31U)
/*! STS_DC_OK - DCDC Output OK
* 0b0..DCDC is settling
* 0b1..DCDC already settled
*/
#define DCDC_REG0_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG0_STS_DC_OK_SHIFT)) & DCDC_REG0_STS_DC_OK_MASK)
/*! @} */
/*! @name REG1 - DCDC Register 1 */
/*! @{ */
#define DCDC_REG1_DM_CTRL_MASK (0x8U)
#define DCDC_REG1_DM_CTRL_SHIFT (3U)
/*! DM_CTRL - DM Control
* 0b0..No change to ripple when the discontinuous current is present in DCM.
* 0b1..Improves ripple when the inductor current goes to zero in DCM.
*/
#define DCDC_REG1_DM_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_DM_CTRL_SHIFT)) & DCDC_REG1_DM_CTRL_MASK)
#define DCDC_REG1_RLOAD_REG_EN_LPSR_MASK (0x10U)
#define DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT (4U)
/*! RLOAD_REG_EN_LPSR - Load Resistor Enable
* 0b0..Disconnect load resistor
* 0b1..Connect load resistor
*/
#define DCDC_REG1_RLOAD_REG_EN_LPSR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_RLOAD_REG_EN_LPSR_SHIFT)) & DCDC_REG1_RLOAD_REG_EN_LPSR_MASK)
#define DCDC_REG1_VBG_TRIM_MASK (0x7C0U)
#define DCDC_REG1_VBG_TRIM_SHIFT (6U)
/*! VBG_TRIM - Trim Bandgap Voltage
* 0b00000..0.452V
* 0b10000..0.5V
* 0b11111..0.545V
*/
#define DCDC_REG1_VBG_TRIM(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_VBG_TRIM_SHIFT)) & DCDC_REG1_VBG_TRIM_MASK)
#define DCDC_REG1_LP_CMP_ISRC_SEL_MASK (0x1800U)
#define DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT (11U)
/*! LP_CMP_ISRC_SEL - Low Power Comparator Current Bias
* 0b00..50nA
* 0b01..100nA
* 0b10..200nA
* 0b11..400nA
*/
#define DCDC_REG1_LP_CMP_ISRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LP_CMP_ISRC_SEL_SHIFT)) & DCDC_REG1_LP_CMP_ISRC_SEL_MASK)
#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK (0x8000000U)
#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT (27U)
/*! LOOPCTRL_CM_HST_THRESH - Increase Threshold Detection
*/
#define DCDC_REG1_LOOPCTRL_CM_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_CM_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK)
#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK (0x10000000U)
#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT (28U)
/*! LOOPCTRL_DF_HST_THRESH - Increase Threshold Detection
*/
#define DCDC_REG1_LOOPCTRL_DF_HST_THRESH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_DF_HST_THRESH_SHIFT)) & DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK)
#define DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK (0x20000000U)
#define DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT (29U)
/*! LOOPCTRL_EN_CM_HYST
* 0b0..Disable hysteresis in switching converter common mode analog comparators
* 0b1..Enable hysteresis in switching converter common mode analog comparators
*/
#define DCDC_REG1_LOOPCTRL_EN_CM_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_CM_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK)
#define DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK (0x40000000U)
#define DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT (30U)
/*! LOOPCTRL_EN_DF_HYST
* 0b0..Disable hysteresis in switching converter differential mode analog comparators
* 0b1..Enable hysteresis in switching converter differential mode analog comparators
*/
#define DCDC_REG1_LOOPCTRL_EN_DF_HYST(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG1_LOOPCTRL_EN_DF_HYST_SHIFT)) & DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK)
/*! @} */
/*! @name REG2 - DCDC Register 2 */
/*! @{ */
#define DCDC_REG2_LOOPCTRL_DC_C_MASK (0x3U)
#define DCDC_REG2_LOOPCTRL_DC_C_SHIFT (0U)
#define DCDC_REG2_LOOPCTRL_DC_C(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_C_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_C_MASK)
#define DCDC_REG2_LOOPCTRL_DC_R_MASK (0x3CU)
#define DCDC_REG2_LOOPCTRL_DC_R_SHIFT (2U)
#define DCDC_REG2_LOOPCTRL_DC_R(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_R_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_R_MASK)
#define DCDC_REG2_LOOPCTRL_DC_FF_MASK (0x1C0U)
#define DCDC_REG2_LOOPCTRL_DC_FF_SHIFT (6U)
#define DCDC_REG2_LOOPCTRL_DC_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_DC_FF_SHIFT)) & DCDC_REG2_LOOPCTRL_DC_FF_MASK)
#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK (0xE00U)
#define DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT (9U)
/*! LOOPCTRL_EN_RCSCALE - Enable RC Scale
*/
#define DCDC_REG2_LOOPCTRL_EN_RCSCALE(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_EN_RCSCALE_SHIFT)) & DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK)
#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK (0x1000U)
#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT (12U)
#define DCDC_REG2_LOOPCTRL_RCSCALE_THRSH(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_SHIFT)) & DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK)
#define DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK (0x2000U)
#define DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT (13U)
#define DCDC_REG2_LOOPCTRL_HYST_SIGN(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_HYST_SIGN_SHIFT)) & DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK)
#define DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK (0x8000U)
#define DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT (15U)
#define DCDC_REG2_BATTMONITOR_EN_BATADJ(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_EN_BATADJ_SHIFT)) & DCDC_REG2_BATTMONITOR_EN_BATADJ_MASK)
#define DCDC_REG2_BATTMONITOR_BATT_VAL_MASK (0x3FF0000U)
#define DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT (16U)
#define DCDC_REG2_BATTMONITOR_BATT_VAL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_BATTMONITOR_BATT_VAL_SHIFT)) & DCDC_REG2_BATTMONITOR_BATT_VAL_MASK)
#define DCDC_REG2_DCM_SET_CTRL_MASK (0x10000000U)
#define DCDC_REG2_DCM_SET_CTRL_SHIFT (28U)
/*! DCM_SET_CTRL - DCM Set Control
*/
#define DCDC_REG2_DCM_SET_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_DCM_SET_CTRL_SHIFT)) & DCDC_REG2_DCM_SET_CTRL_MASK)
#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK (0x40000000U)
#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT (30U)
#define DCDC_REG2_LOOPCTRL_TOGGLE_DIF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG2_LOOPCTRL_TOGGLE_DIF_SHIFT)) & DCDC_REG2_LOOPCTRL_TOGGLE_DIF_MASK)
/*! @} */
/*! @name REG3 - DCDC Register 3 */
/*! @{ */
#define DCDC_REG3_IN_BROWNOUT_MASK (0x4000U)
#define DCDC_REG3_IN_BROWNOUT_SHIFT (14U)
/*! IN_BROWNOUT
* 0b1..DCDC_IN is lower than 2.6V
*/
#define DCDC_REG3_IN_BROWNOUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_IN_BROWNOUT_SHIFT)) & DCDC_REG3_IN_BROWNOUT_MASK)
#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK (0x8000U)
#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT (15U)
/*! OVERVOLT_VDD1P8_DET_OUT
* 0b1..VDD1P8 Overvoltage
*/
#define DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P8_DET_OUT_MASK)
#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK (0x10000U)
#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT (16U)
/*! OVERVOLT_VDD1P0_DET_OUT
* 0b1..VDD1P0 Overvoltage
*/
#define DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_SHIFT)) & DCDC_REG3_OVERVOLT_VDD1P0_DET_OUT_MASK)
#define DCDC_REG3_OVERCUR_DETECT_OUT_MASK (0x20000U)
#define DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT (17U)
/*! OVERCUR_DETECT_OUT
* 0b1..Overcurrent
*/
#define DCDC_REG3_OVERCUR_DETECT_OUT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_OVERCUR_DETECT_OUT_SHIFT)) & DCDC_REG3_OVERCUR_DETECT_OUT_MASK)
#define DCDC_REG3_ENABLE_FF_MASK (0x40000U)
#define DCDC_REG3_ENABLE_FF_SHIFT (18U)
/*! ENABLE_FF
* 0b1..Enable feed-forward (FF) function that can speed up transient settling.
*/
#define DCDC_REG3_ENABLE_FF(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_ENABLE_FF_SHIFT)) & DCDC_REG3_ENABLE_FF_MASK)
#define DCDC_REG3_DISABLE_PULSE_SKIP_MASK (0x80000U)
#define DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT (19U)
/*! DISABLE_PULSE_SKIP - Disable Pulse Skip
* 0b0..Stop charging if the duty cycle is lower than what is set by NEGLIMIT_IN
*/
#define DCDC_REG3_DISABLE_PULSE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_PULSE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_PULSE_SKIP_MASK)
#define DCDC_REG3_DISABLE_IDLE_SKIP_MASK (0x100000U)
#define DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT (20U)
/*! DISABLE_IDLE_SKIP
* 0b0..Enable the idle skip function. The DCDC will be idle when out-of-range comparator detects the output
* voltage is higher than the target by 25mV. This function requires the out-of-range comparator to be enabled
* (PWD_CMP_OFFSET=0).
*/
#define DCDC_REG3_DISABLE_IDLE_SKIP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DISABLE_IDLE_SKIP_SHIFT)) & DCDC_REG3_DISABLE_IDLE_SKIP_MASK)
#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK (0x200000U)
#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT (21U)
/*! DOUBLE_IBIAS_CMP_LP_LPSR
* 0b1..Double the bias current of the comparator for low-voltage detector in LP (low-power) mode
*/
#define DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_SHIFT)) & DCDC_REG3_DOUBLE_IBIAS_CMP_LP_LPSR_MASK)
#define DCDC_REG3_REG_FBK_SEL_MASK (0xC00000U)
#define DCDC_REG3_REG_FBK_SEL_SHIFT (22U)
#define DCDC_REG3_REG_FBK_SEL(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_REG_FBK_SEL_SHIFT)) & DCDC_REG3_REG_FBK_SEL_MASK)
#define DCDC_REG3_MINPWR_DC_HALFCLK_MASK (0x1000000U)
#define DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT (24U)
/*! MINPWR_DC_HALFCLK
* 0b0..DCDC clock remains at full frequency for continuous mode
* 0b1..DCDC clock set to half frequency for continuous mode
*/
#define DCDC_REG3_MINPWR_DC_HALFCLK(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_DC_HALFCLK_SHIFT)) & DCDC_REG3_MINPWR_DC_HALFCLK_MASK)
#define DCDC_REG3_MINPWR_HALF_FETS_MASK (0x4000000U)
#define DCDC_REG3_MINPWR_HALF_FETS_SHIFT (26U)
#define DCDC_REG3_MINPWR_HALF_FETS(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MINPWR_HALF_FETS_SHIFT)) & DCDC_REG3_MINPWR_HALF_FETS_MASK)
#define DCDC_REG3_MISC_DELAY_TIMING_MASK (0x8000000U)
#define DCDC_REG3_MISC_DELAY_TIMING_SHIFT (27U)
/*! MISC_DELAY_TIMING - Miscellaneous Delay Timing
*/
#define DCDC_REG3_MISC_DELAY_TIMING(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_MISC_DELAY_TIMING_SHIFT)) & DCDC_REG3_MISC_DELAY_TIMING_MASK)
#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK (0x20000000U)
#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT (29U)
/*! VDD1P0CTRL_DISABLE_STEP - Disable Step for VDD1P0
* 0b0..Enable stepping for VDD1P0
* 0b1..Disable stepping for VDD1P0
*/
#define DCDC_REG3_VDD1P0CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P0CTRL_DISABLE_STEP_MASK)
#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK (0x40000000U)
#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT (30U)
/*! VDD1P8CTRL_DISABLE_STEP - Disable Step for VDD1P8
* 0b0..Enable stepping for VDD1P8
* 0b1..Disable stepping for VDD1P8
*/
#define DCDC_REG3_VDD1P8CTRL_DISABLE_STEP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_SHIFT)) & DCDC_REG3_VDD1P8CTRL_DISABLE_STEP_MASK)
/*! @} */
/*! @name REG4 - DCDC Register 4 */
/*! @{ */
#define DCDC_REG4_ENABLE_SP_MASK (0xFFFFU)
#define DCDC_REG4_ENABLE_SP_SHIFT (0U)
#define DCDC_REG4_ENABLE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG4_ENABLE_SP_SHIFT)) & DCDC_REG4_ENABLE_SP_MASK)
/*! @} */
/*! @name REG5 - DCDC Register 5 */
/*! @{ */
#define DCDC_REG5_DIG_EN_SP_MASK (0xFFFFU)
#define DCDC_REG5_DIG_EN_SP_SHIFT (0U)
#define DCDC_REG5_DIG_EN_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG5_DIG_EN_SP_SHIFT)) & DCDC_REG5_DIG_EN_SP_MASK)
/*! @} */
/*! @name REG6 - DCDC Register 6 */
/*! @{ */
#define DCDC_REG6_LP_MODE_SP_MASK (0xFFFFU)
#define DCDC_REG6_LP_MODE_SP_SHIFT (0U)
#define DCDC_REG6_LP_MODE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG6_LP_MODE_SP_SHIFT)) & DCDC_REG6_LP_MODE_SP_MASK)
/*! @} */
/*! @name REG7 - DCDC Register 7 */
/*! @{ */
#define DCDC_REG7_STBY_EN_SP_MASK (0xFFFFU)
#define DCDC_REG7_STBY_EN_SP_SHIFT (0U)
#define DCDC_REG7_STBY_EN_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7_STBY_EN_SP_SHIFT)) & DCDC_REG7_STBY_EN_SP_MASK)
/*! @} */
/*! @name REG7P - DCDC Register 7 plus */
/*! @{ */
#define DCDC_REG7P_STBY_LP_MODE_SP_MASK (0xFFFFU)
#define DCDC_REG7P_STBY_LP_MODE_SP_SHIFT (0U)
#define DCDC_REG7P_STBY_LP_MODE_SP(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG7P_STBY_LP_MODE_SP_SHIFT)) & DCDC_REG7P_STBY_LP_MODE_SP_MASK)
/*! @} */
/*! @name REG8 - DCDC Register 8 */
/*! @{ */
#define DCDC_REG8_ANA_TRG_SP0_MASK (0xFFFFFFFFU)
#define DCDC_REG8_ANA_TRG_SP0_SHIFT (0U)
#define DCDC_REG8_ANA_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG8_ANA_TRG_SP0_SHIFT)) & DCDC_REG8_ANA_TRG_SP0_MASK)
/*! @} */
/*! @name REG9 - DCDC Register 9 */
/*! @{ */
#define DCDC_REG9_ANA_TRG_SP1_MASK (0xFFFFFFFFU)
#define DCDC_REG9_ANA_TRG_SP1_SHIFT (0U)
#define DCDC_REG9_ANA_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG9_ANA_TRG_SP1_SHIFT)) & DCDC_REG9_ANA_TRG_SP1_MASK)
/*! @} */
/*! @name REG10 - DCDC Register 10 */
/*! @{ */
#define DCDC_REG10_ANA_TRG_SP2_MASK (0xFFFFFFFFU)
#define DCDC_REG10_ANA_TRG_SP2_SHIFT (0U)
#define DCDC_REG10_ANA_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG10_ANA_TRG_SP2_SHIFT)) & DCDC_REG10_ANA_TRG_SP2_MASK)
/*! @} */
/*! @name REG11 - DCDC Register 11 */
/*! @{ */
#define DCDC_REG11_ANA_TRG_SP3_MASK (0xFFFFFFFFU)
#define DCDC_REG11_ANA_TRG_SP3_SHIFT (0U)
#define DCDC_REG11_ANA_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG11_ANA_TRG_SP3_SHIFT)) & DCDC_REG11_ANA_TRG_SP3_MASK)
/*! @} */
/*! @name REG12 - DCDC Register 12 */
/*! @{ */
#define DCDC_REG12_DIG_TRG_SP0_MASK (0xFFFFFFFFU)
#define DCDC_REG12_DIG_TRG_SP0_SHIFT (0U)
#define DCDC_REG12_DIG_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG12_DIG_TRG_SP0_SHIFT)) & DCDC_REG12_DIG_TRG_SP0_MASK)
/*! @} */
/*! @name REG13 - DCDC Register 13 */
/*! @{ */
#define DCDC_REG13_DIG_TRG_SP1_MASK (0xFFFFFFFFU)
#define DCDC_REG13_DIG_TRG_SP1_SHIFT (0U)
#define DCDC_REG13_DIG_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG13_DIG_TRG_SP1_SHIFT)) & DCDC_REG13_DIG_TRG_SP1_MASK)
/*! @} */
/*! @name REG14 - DCDC Register 14 */
/*! @{ */
#define DCDC_REG14_DIG_TRG_SP2_MASK (0xFFFFFFFFU)
#define DCDC_REG14_DIG_TRG_SP2_SHIFT (0U)
#define DCDC_REG14_DIG_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG14_DIG_TRG_SP2_SHIFT)) & DCDC_REG14_DIG_TRG_SP2_MASK)
/*! @} */
/*! @name REG15 - DCDC Register 15 */
/*! @{ */
#define DCDC_REG15_DIG_TRG_SP3_MASK (0xFFFFFFFFU)
#define DCDC_REG15_DIG_TRG_SP3_SHIFT (0U)
#define DCDC_REG15_DIG_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG15_DIG_TRG_SP3_SHIFT)) & DCDC_REG15_DIG_TRG_SP3_MASK)
/*! @} */
/*! @name REG16 - DCDC Register 16 */
/*! @{ */
#define DCDC_REG16_ANA_STBY_TRG_SP0_MASK (0xFFFFFFFFU)
#define DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT (0U)
#define DCDC_REG16_ANA_STBY_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG16_ANA_STBY_TRG_SP0_SHIFT)) & DCDC_REG16_ANA_STBY_TRG_SP0_MASK)
/*! @} */
/*! @name REG17 - DCDC Register 17 */
/*! @{ */
#define DCDC_REG17_ANA_STBY_TRG_SP1_MASK (0xFFFFFFFFU)
#define DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT (0U)
#define DCDC_REG17_ANA_STBY_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG17_ANA_STBY_TRG_SP1_SHIFT)) & DCDC_REG17_ANA_STBY_TRG_SP1_MASK)
/*! @} */
/*! @name REG18 - DCDC Register 18 */
/*! @{ */
#define DCDC_REG18_ANA_STBY_TRG_SP2_MASK (0xFFFFFFFFU)
#define DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT (0U)
#define DCDC_REG18_ANA_STBY_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG18_ANA_STBY_TRG_SP2_SHIFT)) & DCDC_REG18_ANA_STBY_TRG_SP2_MASK)
/*! @} */
/*! @name REG19 - DCDC Register 19 */
/*! @{ */
#define DCDC_REG19_ANA_STBY_TRG_SP3_MASK (0xFFFFFFFFU)
#define DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT (0U)
#define DCDC_REG19_ANA_STBY_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG19_ANA_STBY_TRG_SP3_SHIFT)) & DCDC_REG19_ANA_STBY_TRG_SP3_MASK)
/*! @} */
/*! @name REG20 - DCDC Register 20 */
/*! @{ */
#define DCDC_REG20_DIG_STBY_TRG_SP0_MASK (0xFFFFFFFFU)
#define DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT (0U)
#define DCDC_REG20_DIG_STBY_TRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG20_DIG_STBY_TRG_SP0_SHIFT)) & DCDC_REG20_DIG_STBY_TRG_SP0_MASK)
/*! @} */
/*! @name REG21 - DCDC Register 21 */
/*! @{ */
#define DCDC_REG21_DIG_STBY_TRG_SP1_MASK (0xFFFFFFFFU)
#define DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT (0U)
#define DCDC_REG21_DIG_STBY_TRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG21_DIG_STBY_TRG_SP1_SHIFT)) & DCDC_REG21_DIG_STBY_TRG_SP1_MASK)
/*! @} */
/*! @name REG22 - DCDC Register 22 */
/*! @{ */
#define DCDC_REG22_DIG_STBY_TRG_SP2_MASK (0xFFFFFFFFU)
#define DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT (0U)
#define DCDC_REG22_DIG_STBY_TRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG22_DIG_STBY_TRG_SP2_SHIFT)) & DCDC_REG22_DIG_STBY_TRG_SP2_MASK)
/*! @} */
/*! @name REG23 - DCDC Register 23 */
/*! @{ */
#define DCDC_REG23_DIG_STBY_TRG_SP3_MASK (0xFFFFFFFFU)
#define DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT (0U)
#define DCDC_REG23_DIG_STBY_TRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG23_DIG_STBY_TRG_SP3_SHIFT)) & DCDC_REG23_DIG_STBY_TRG_SP3_MASK)
/*! @} */
/*! @name REG24 - DCDC Register 24 */
/*! @{ */
#define DCDC_REG24_OK_COUNT_MASK (0xFFFFFFFFU)
#define DCDC_REG24_OK_COUNT_SHIFT (0U)
#define DCDC_REG24_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DCDC_REG24_OK_COUNT_SHIFT)) & DCDC_REG24_OK_COUNT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DCDC_Register_Masks */
/* DCDC - Peripheral instance base addresses */
/** Peripheral DCDC base address */
#define DCDC_BASE (0x40CA8000u)
/** Peripheral DCDC base pointer */
#define DCDC ((DCDC_Type *)DCDC_BASE)
/** Array initializer of DCDC peripheral base addresses */
#define DCDC_BASE_ADDRS { DCDC_BASE }
/** Array initializer of DCDC peripheral base pointers */
#define DCDC_BASE_PTRS { DCDC }
/*!
* @}
*/ /* end of group DCDC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DCIC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DCIC_Peripheral_Access_Layer DCIC Peripheral Access Layer
* @{
*/
/** DCIC - Register Layout Typedef */
typedef struct {
__IO uint32_t DCICC; /**< DCIC Control Register, offset: 0x0 */
__IO uint32_t DCICIC; /**< DCIC Interrupt Control Register, offset: 0x4 */
__IO uint32_t DCICS; /**< DCIC Status Register, offset: 0x8 */
uint8_t RESERVED_0[4];
struct { /* offset: 0x10, array step: 0x10 */
__IO uint32_t DCICRC; /**< DCIC ROI Config Register, array offset: 0x10, array step: 0x10 */
__IO uint32_t DCICRS; /**< DCIC ROI Size Register, array offset: 0x14, array step: 0x10 */
__IO uint32_t DCICRRS; /**< DCIC ROI Reference Signature Register, array offset: 0x18, array step: 0x10 */
__I uint32_t DCICRCS; /**< DCIC ROI Calculated Signature Register, array offset: 0x1C, array step: 0x10 */
} REGION[16];
} DCIC_Type;
/* ----------------------------------------------------------------------------
-- DCIC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DCIC_Register_Masks DCIC Register Masks
* @{
*/
/*! @name DCICC - DCIC Control Register */
/*! @{ */
#define DCIC_DCICC_IC_EN_MASK (0x1U)
#define DCIC_DCICC_IC_EN_SHIFT (0U)
/*! IC_EN
* 0b0..Disabled
* 0b1..Enabled
*/
#define DCIC_DCICC_IC_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_IC_EN_SHIFT)) & DCIC_DCICC_IC_EN_MASK)
#define DCIC_DCICC_DE_POL_MASK (0x10U)
#define DCIC_DCICC_DE_POL_SHIFT (4U)
/*! DE_POL
* 0b0..Active High.
* 0b1..Active Low.
*/
#define DCIC_DCICC_DE_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_DE_POL_SHIFT)) & DCIC_DCICC_DE_POL_MASK)
#define DCIC_DCICC_HSYNC_POL_MASK (0x20U)
#define DCIC_DCICC_HSYNC_POL_SHIFT (5U)
/*! HSYNC_POL
* 0b0..Active High.
* 0b1..Active Low.
*/
#define DCIC_DCICC_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_HSYNC_POL_SHIFT)) & DCIC_DCICC_HSYNC_POL_MASK)
#define DCIC_DCICC_VSYNC_POL_MASK (0x40U)
#define DCIC_DCICC_VSYNC_POL_SHIFT (6U)
/*! VSYNC_POL
* 0b0..Active High.
* 0b1..Active Low.
*/
#define DCIC_DCICC_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_VSYNC_POL_SHIFT)) & DCIC_DCICC_VSYNC_POL_MASK)
#define DCIC_DCICC_CLK_POL_MASK (0x80U)
#define DCIC_DCICC_CLK_POL_SHIFT (7U)
/*! CLK_POL
* 0b0..Not inverted (default).
* 0b1..Inverted.
*/
#define DCIC_DCICC_CLK_POL(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICC_CLK_POL_SHIFT)) & DCIC_DCICC_CLK_POL_MASK)
/*! @} */
/*! @name DCICIC - DCIC Interrupt Control Register */
/*! @{ */
#define DCIC_DCICIC_EI_MASK_MASK (0x1U)
#define DCIC_DCICIC_EI_MASK_SHIFT (0U)
/*! EI_MASK
* 0b0..Mask disabled - Interrupt assertion enabled
* 0b1..Mask enabled - Interrupt assertion disabled
*/
#define DCIC_DCICIC_EI_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EI_MASK_SHIFT)) & DCIC_DCICIC_EI_MASK_MASK)
#define DCIC_DCICIC_FI_MASK_MASK (0x2U)
#define DCIC_DCICIC_FI_MASK_SHIFT (1U)
/*! FI_MASK
* 0b0..Mask disabled - Interrupt assertion enabled
* 0b1..Mask enabled - Interrupt assertion disabled
*/
#define DCIC_DCICIC_FI_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FI_MASK_SHIFT)) & DCIC_DCICIC_FI_MASK_MASK)
#define DCIC_DCICIC_FREEZE_MASK_MASK (0x8U)
#define DCIC_DCICIC_FREEZE_MASK_SHIFT (3U)
/*! FREEZE_MASK
* 0b0..Masks change allowed
* 0b1..Masks are frozen
*/
#define DCIC_DCICIC_FREEZE_MASK(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_FREEZE_MASK_SHIFT)) & DCIC_DCICIC_FREEZE_MASK_MASK)
#define DCIC_DCICIC_EXT_SIG_EN_MASK (0x10000U)
#define DCIC_DCICIC_EXT_SIG_EN_SHIFT (16U)
/*! EXT_SIG_EN
* 0b0..Disabled
* 0b1..Enabled
*/
#define DCIC_DCICIC_EXT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICIC_EXT_SIG_EN_SHIFT)) & DCIC_DCICIC_EXT_SIG_EN_MASK)
/*! @} */
/*! @name DCICS - DCIC Status Register */
/*! @{ */
#define DCIC_DCICS_ROI_MATCH_STAT_MASK (0xFFFFU)
#define DCIC_DCICS_ROI_MATCH_STAT_SHIFT (0U)
/*! ROI_MATCH_STAT
* 0b0000000000000000..ROI calculated CRC matches expected signature
* 0b0000000000000001..Mismatch at ROI calculated CRC
*/
#define DCIC_DCICS_ROI_MATCH_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_ROI_MATCH_STAT_SHIFT)) & DCIC_DCICS_ROI_MATCH_STAT_MASK)
#define DCIC_DCICS_EI_STAT_MASK (0x10000U)
#define DCIC_DCICS_EI_STAT_SHIFT (16U)
/*! EI_STAT
* 0b0..No pending Interrupt
* 0b1..Pending Interrupt
*/
#define DCIC_DCICS_EI_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_EI_STAT_SHIFT)) & DCIC_DCICS_EI_STAT_MASK)
#define DCIC_DCICS_FI_STAT_MASK (0x20000U)
#define DCIC_DCICS_FI_STAT_SHIFT (17U)
/*! FI_STAT
* 0b0..No pending Interrupt
* 0b1..Pending Interrupt
*/
#define DCIC_DCICS_FI_STAT(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICS_FI_STAT_SHIFT)) & DCIC_DCICS_FI_STAT_MASK)
/*! @} */
/*! @name DCICRC - DCIC ROI Config Register */
/*! @{ */
#define DCIC_DCICRC_START_OFFSET_X_MASK (0x1FFFU)
#define DCIC_DCICRC_START_OFFSET_X_SHIFT (0U)
#define DCIC_DCICRC_START_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_X_SHIFT)) & DCIC_DCICRC_START_OFFSET_X_MASK)
#define DCIC_DCICRC_START_OFFSET_Y_MASK (0xFFF0000U)
#define DCIC_DCICRC_START_OFFSET_Y_SHIFT (16U)
#define DCIC_DCICRC_START_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_START_OFFSET_Y_SHIFT)) & DCIC_DCICRC_START_OFFSET_Y_MASK)
#define DCIC_DCICRC_ROI_FREEZE_MASK (0x40000000U)
#define DCIC_DCICRC_ROI_FREEZE_SHIFT (30U)
/*! ROI_FREEZE
* 0b0..ROI configuration can be changed
* 0b1..ROI configuration is frozen
*/
#define DCIC_DCICRC_ROI_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_FREEZE_SHIFT)) & DCIC_DCICRC_ROI_FREEZE_MASK)
#define DCIC_DCICRC_ROI_EN_MASK (0x80000000U)
#define DCIC_DCICRC_ROI_EN_SHIFT (31U)
/*! ROI_EN
* 0b0..Disabled
* 0b1..Enabled
*/
#define DCIC_DCICRC_ROI_EN(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRC_ROI_EN_SHIFT)) & DCIC_DCICRC_ROI_EN_MASK)
/*! @} */
/* The count of DCIC_DCICRC */
#define DCIC_DCICRC_COUNT (16U)
/*! @name DCICRS - DCIC ROI Size Register */
/*! @{ */
#define DCIC_DCICRS_END_OFFSET_X_MASK (0x1FFFU)
#define DCIC_DCICRS_END_OFFSET_X_SHIFT (0U)
#define DCIC_DCICRS_END_OFFSET_X(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_X_SHIFT)) & DCIC_DCICRS_END_OFFSET_X_MASK)
#define DCIC_DCICRS_END_OFFSET_Y_MASK (0xFFF0000U)
#define DCIC_DCICRS_END_OFFSET_Y_SHIFT (16U)
#define DCIC_DCICRS_END_OFFSET_Y(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRS_END_OFFSET_Y_SHIFT)) & DCIC_DCICRS_END_OFFSET_Y_MASK)
/*! @} */
/* The count of DCIC_DCICRS */
#define DCIC_DCICRS_COUNT (16U)
/*! @name DCICRRS - DCIC ROI Reference Signature Register */
/*! @{ */
#define DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK (0xFFFFFFFFU)
#define DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT (0U)
#define DCIC_DCICRRS_REFERENCE_SIGNATURE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRRS_REFERENCE_SIGNATURE_SHIFT)) & DCIC_DCICRRS_REFERENCE_SIGNATURE_MASK)
/*! @} */
/* The count of DCIC_DCICRRS */
#define DCIC_DCICRRS_COUNT (16U)
/*! @name DCICRCS - DCIC ROI Calculated Signature Register */
/*! @{ */
#define DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK (0xFFFFFFFFU)
#define DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT (0U)
#define DCIC_DCICRCS_CALCULATED_SIGNATURE(x) (((uint32_t)(((uint32_t)(x)) << DCIC_DCICRCS_CALCULATED_SIGNATURE_SHIFT)) & DCIC_DCICRCS_CALCULATED_SIGNATURE_MASK)
/*! @} */
/* The count of DCIC_DCICRCS */
#define DCIC_DCICRCS_COUNT (16U)
/*!
* @}
*/ /* end of group DCIC_Register_Masks */
/* DCIC - Peripheral instance base addresses */
/** Peripheral DCIC1 base address */
#define DCIC1_BASE (0x40819000u)
/** Peripheral DCIC1 base pointer */
#define DCIC1 ((DCIC_Type *)DCIC1_BASE)
/** Peripheral DCIC2 base address */
#define DCIC2_BASE (0x4081A000u)
/** Peripheral DCIC2 base pointer */
#define DCIC2 ((DCIC_Type *)DCIC2_BASE)
/** Array initializer of DCIC peripheral base addresses */
#define DCIC_BASE_ADDRS { 0u, DCIC1_BASE, DCIC2_BASE }
/** Array initializer of DCIC peripheral base pointers */
#define DCIC_BASE_PTRS { (DCIC_Type *)0u, DCIC1, DCIC2 }
/*!
* @}
*/ /* end of group DCIC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
* @{
*/
/** DMA - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< Control, offset: 0x0 */
__I uint32_t ES; /**< Error Status, offset: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t ERQ; /**< Enable Request, offset: 0xC */
uint8_t RESERVED_1[4];
__IO uint32_t EEI; /**< Enable Error Interrupt, offset: 0x14 */
__O uint8_t CEEI; /**< Clear Enable Error Interrupt, offset: 0x18 */
__O uint8_t SEEI; /**< Set Enable Error Interrupt, offset: 0x19 */
__O uint8_t CERQ; /**< Clear Enable Request, offset: 0x1A */
__O uint8_t SERQ; /**< Set Enable Request, offset: 0x1B */
__O uint8_t CDNE; /**< Clear DONE Status Bit, offset: 0x1C */
__O uint8_t SSRT; /**< Set START Bit, offset: 0x1D */
__O uint8_t CERR; /**< Clear Error, offset: 0x1E */
__O uint8_t CINT; /**< Clear Interrupt Request, offset: 0x1F */
uint8_t RESERVED_2[4];
__IO uint32_t INT; /**< Interrupt Request, offset: 0x24 */
uint8_t RESERVED_3[4];
__IO uint32_t ERR; /**< Error, offset: 0x2C */
uint8_t RESERVED_4[4];
__I uint32_t HRS; /**< Hardware Request Status, offset: 0x34 */
uint8_t RESERVED_5[12];
__IO uint32_t EARS; /**< Enable Asynchronous Request in Stop, offset: 0x44 */
uint8_t RESERVED_6[184];
__IO uint8_t DCHPRI3; /**< Channel Priority, offset: 0x100 */
__IO uint8_t DCHPRI2; /**< Channel Priority, offset: 0x101 */
__IO uint8_t DCHPRI1; /**< Channel Priority, offset: 0x102 */
__IO uint8_t DCHPRI0; /**< Channel Priority, offset: 0x103 */
__IO uint8_t DCHPRI7; /**< Channel Priority, offset: 0x104 */
__IO uint8_t DCHPRI6; /**< Channel Priority, offset: 0x105 */
__IO uint8_t DCHPRI5; /**< Channel Priority, offset: 0x106 */
__IO uint8_t DCHPRI4; /**< Channel Priority, offset: 0x107 */
__IO uint8_t DCHPRI11; /**< Channel Priority, offset: 0x108 */
__IO uint8_t DCHPRI10; /**< Channel Priority, offset: 0x109 */
__IO uint8_t DCHPRI9; /**< Channel Priority, offset: 0x10A */
__IO uint8_t DCHPRI8; /**< Channel Priority, offset: 0x10B */
__IO uint8_t DCHPRI15; /**< Channel Priority, offset: 0x10C */
__IO uint8_t DCHPRI14; /**< Channel Priority, offset: 0x10D */
__IO uint8_t DCHPRI13; /**< Channel Priority, offset: 0x10E */
__IO uint8_t DCHPRI12; /**< Channel Priority, offset: 0x10F */
__IO uint8_t DCHPRI19; /**< Channel Priority, offset: 0x110 */
__IO uint8_t DCHPRI18; /**< Channel Priority, offset: 0x111 */
__IO uint8_t DCHPRI17; /**< Channel Priority, offset: 0x112 */
__IO uint8_t DCHPRI16; /**< Channel Priority, offset: 0x113 */
__IO uint8_t DCHPRI23; /**< Channel Priority, offset: 0x114 */
__IO uint8_t DCHPRI22; /**< Channel Priority, offset: 0x115 */
__IO uint8_t DCHPRI21; /**< Channel Priority, offset: 0x116 */
__IO uint8_t DCHPRI20; /**< Channel Priority, offset: 0x117 */
__IO uint8_t DCHPRI27; /**< Channel Priority, offset: 0x118 */
__IO uint8_t DCHPRI26; /**< Channel Priority, offset: 0x119 */
__IO uint8_t DCHPRI25; /**< Channel Priority, offset: 0x11A */
__IO uint8_t DCHPRI24; /**< Channel Priority, offset: 0x11B */
__IO uint8_t DCHPRI31; /**< Channel Priority, offset: 0x11C */
__IO uint8_t DCHPRI30; /**< Channel Priority, offset: 0x11D */
__IO uint8_t DCHPRI29; /**< Channel Priority, offset: 0x11E */
__IO uint8_t DCHPRI28; /**< Channel Priority, offset: 0x11F */
uint8_t RESERVED_7[3808];
struct { /* offset: 0x1000, array step: 0x20 */
__IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
__IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
__IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
union { /* offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Mapping Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
__IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled), array offset: 0x1008, array step: 0x20 */
};
__IO int32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
__IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
__IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
union { /* offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
__IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
};
__IO int32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
__IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
union { /* offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
__IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
};
} TCD[32];
} DMA_Type;
/* ----------------------------------------------------------------------------
-- DMA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMA_Register_Masks DMA Register Masks
* @{
*/
/*! @name CR - Control */
/*! @{ */
#define DMA_CR_EDBG_MASK (0x2U)
#define DMA_CR_EDBG_SHIFT (1U)
/*! EDBG - Enable Debug
* 0b0..When the chip is in Debug mode, the eDMA continues to operate.
* 0b1..When the chip is in debug mode, the DMA stalls the start of a new channel. Executing channels are allowed to complete.
*/
#define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
#define DMA_CR_ERCA_MASK (0x4U)
#define DMA_CR_ERCA_SHIFT (2U)
/*! ERCA - Enable Round Robin Channel Arbitration
* 0b0..Fixed priority arbitration within each group
* 0b1..Round robin arbitration within each group
*/
#define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
#define DMA_CR_ERGA_MASK (0x8U)
#define DMA_CR_ERGA_SHIFT (3U)
/*! ERGA - Enable Round Robin Group Arbitration
* 0b0..Fixed priority arbitration
* 0b1..Round robin arbitration
*/
#define DMA_CR_ERGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERGA_SHIFT)) & DMA_CR_ERGA_MASK)
#define DMA_CR_HOE_MASK (0x10U)
#define DMA_CR_HOE_SHIFT (4U)
/*! HOE - Halt On Error
* 0b0..Normal operation
* 0b1..Error causes HALT field to be automatically set to 1
*/
#define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
#define DMA_CR_HALT_MASK (0x20U)
#define DMA_CR_HALT_SHIFT (5U)
/*! HALT - Halt eDMA Operations
* 0b0..Normal operation
* 0b1..eDMA operations halted
*/
#define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
#define DMA_CR_CLM_MASK (0x40U)
#define DMA_CR_CLM_SHIFT (6U)
/*! CLM - Continuous Link Mode
* 0b0..Continuous link mode is off
* 0b1..Continuous link mode is on
*/
#define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
#define DMA_CR_EMLM_MASK (0x80U)
#define DMA_CR_EMLM_SHIFT (7U)
/*! EMLM - Enable Minor Loop Mapping
* 0b0..Disabled
* 0b1..Enabled
*/
#define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
#define DMA_CR_GRP0PRI_MASK (0x100U)
#define DMA_CR_GRP0PRI_SHIFT (8U)
/*! GRP0PRI - Channel Group 0 Priority
*/
#define DMA_CR_GRP0PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP0PRI_SHIFT)) & DMA_CR_GRP0PRI_MASK)
#define DMA_CR_GRP1PRI_MASK (0x400U)
#define DMA_CR_GRP1PRI_SHIFT (10U)
/*! GRP1PRI - Channel Group 1 Priority
*/
#define DMA_CR_GRP1PRI(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_GRP1PRI_SHIFT)) & DMA_CR_GRP1PRI_MASK)
#define DMA_CR_ECX_MASK (0x10000U)
#define DMA_CR_ECX_SHIFT (16U)
/*! ECX - Error Cancel Transfer
* 0b0..Normal operation
* 0b1..Cancel the remaining data transfer
*/
#define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
#define DMA_CR_CX_MASK (0x20000U)
#define DMA_CR_CX_SHIFT (17U)
/*! CX - Cancel Transfer
* 0b0..Normal operation
* 0b1..Cancel the remaining data transfer
*/
#define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
#define DMA_CR_VERSION_MASK (0x7F000000U)
#define DMA_CR_VERSION_SHIFT (24U)
/*! VERSION - eDMA version number
*/
#define DMA_CR_VERSION(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_VERSION_SHIFT)) & DMA_CR_VERSION_MASK)
#define DMA_CR_ACTIVE_MASK (0x80000000U)
#define DMA_CR_ACTIVE_SHIFT (31U)
/*! ACTIVE - eDMA Active Status
* 0b0..eDMA is idle
* 0b1..eDMA is executing a channel
*/
#define DMA_CR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ACTIVE_SHIFT)) & DMA_CR_ACTIVE_MASK)
/*! @} */
/*! @name ES - Error Status */
/*! @{ */
#define DMA_ES_DBE_MASK (0x1U)
#define DMA_ES_DBE_SHIFT (0U)
/*! DBE - Destination Bus Error
* 0b0..No destination bus error.
* 0b1..The most-recently recorded error was a bus error on a destination write.
*/
#define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
#define DMA_ES_SBE_MASK (0x2U)
#define DMA_ES_SBE_SHIFT (1U)
/*! SBE - Source Bus Error
* 0b0..No source bus error.
* 0b1..The most-recently recorded error was a bus error on a source read.
*/
#define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
#define DMA_ES_SGE_MASK (0x4U)
#define DMA_ES_SGE_SHIFT (2U)
/*! SGE - Scatter/Gather Configuration Error
* 0b0..No scatter/gather configuration error.
* 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DLASTSGA field.
*/
#define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
#define DMA_ES_NCE_MASK (0x8U)
#define DMA_ES_NCE_SHIFT (3U)
/*! NCE - NBYTES/CITER Configuration Error
* 0b0..No NBYTES/CITER configuration error.
* 0b1..The most-recently recorded error was a configuration error detected in the TCDn_NBYTES or TCDn_CITER
* fields. TCDn_NBYTES is not a multiple of TCDn_ATTR[SSIZE] and TCDn_ATTR[DSIZE], or TCDn_CITER[CITER] = 0, or
* TCDn_CITER[ELINK] is not equal to TCDn_BITER[ELINK].
*/
#define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
#define DMA_ES_DOE_MASK (0x10U)
#define DMA_ES_DOE_SHIFT (4U)
/*! DOE - Destination Offset Error
* 0b0..No destination offset configuration error.
* 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DOFF field. TCDn_DOFF is inconsistent with TCDn_ATTR[DSIZE].
*/
#define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
#define DMA_ES_DAE_MASK (0x20U)
#define DMA_ES_DAE_SHIFT (5U)
/*! DAE - Destination Address Error
* 0b0..No destination address configuration error.
* 0b1..The most-recently recorded error was a configuration error detected in the TCDn_DADDR field. TCDn_DADDR
* is inconsistent with TCDn_ATTR[DSIZE].
*/
#define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
#define DMA_ES_SOE_MASK (0x40U)
#define DMA_ES_SOE_SHIFT (6U)
/*! SOE - Source Offset Error
* 0b0..No source offset configuration error.
* 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SOFF field. TCDn_SOFF is inconsistent with TCDn_ATTR[SSIZE].
*/
#define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
#define DMA_ES_SAE_MASK (0x80U)
#define DMA_ES_SAE_SHIFT (7U)
/*! SAE - Source Address Error
* 0b0..No source address configuration error.
* 0b1..The most-recently recorded error was a configuration error detected in the TCDn_SADDR field. TCDn_SADDR
* is inconsistent with TCDn_ATTR[SSIZE].
*/
#define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
#define DMA_ES_ERRCHN_MASK (0x1F00U)
#define DMA_ES_ERRCHN_SHIFT (8U)
/*! ERRCHN - Error Channel Number or Canceled Channel Number
*/
#define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
#define DMA_ES_CPE_MASK (0x4000U)
#define DMA_ES_CPE_SHIFT (14U)
/*! CPE - Channel Priority Error
* 0b0..No channel priority error.
* 0b1..The most-recently recorded error was a configuration error in the channel priorities within a group.
* Channel priorities within a group are not unique.
*/
#define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
#define DMA_ES_GPE_MASK (0x8000U)
#define DMA_ES_GPE_SHIFT (15U)
/*! GPE - Group Priority Error
* 0b0..No group priority error.
* 0b1..The most-recently recorded error was a configuration error among the group priorities. All group priorities are not unique.
*/
#define DMA_ES_GPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_GPE_SHIFT)) & DMA_ES_GPE_MASK)
#define DMA_ES_ECX_MASK (0x10000U)
#define DMA_ES_ECX_SHIFT (16U)
/*! ECX - Transfer Canceled
* 0b0..No canceled transfers
* 0b1..The most-recently recorded entry was a canceled transfer initiated by the error cancel transfer field
*/
#define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
#define DMA_ES_VLD_MASK (0x80000000U)
#define DMA_ES_VLD_SHIFT (31U)
/*! VLD - Logical OR of all ERR status fields
* 0b0..No ERR fields are 1
* 0b1..At least one ERR field has a value of 1, indicating a valid error exists that has not been cleared
*/
#define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
/*! @} */
/*! @name ERQ - Enable Request */
/*! @{ */
#define DMA_ERQ_ERQ0_MASK (0x1U)
#define DMA_ERQ_ERQ0_SHIFT (0U)
/*! ERQ0 - Enable DMA Request 0
* 0b0..The DMA request signal for channel 0 is disabled
* 0b1..The DMA request signal for channel 0 is enabled
*/
#define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
#define DMA_ERQ_ERQ1_MASK (0x2U)
#define DMA_ERQ_ERQ1_SHIFT (1U)
/*! ERQ1 - Enable DMA Request 1
* 0b0..The DMA request signal for channel 1 is disabled
* 0b1..The DMA request signal for channel 1 is enabled
*/
#define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
#define DMA_ERQ_ERQ2_MASK (0x4U)
#define DMA_ERQ_ERQ2_SHIFT (2U)
/*! ERQ2 - Enable DMA Request 2
* 0b0..The DMA request signal for channel 2 is disabled
* 0b1..The DMA request signal for channel 2 is enabled
*/
#define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
#define DMA_ERQ_ERQ3_MASK (0x8U)
#define DMA_ERQ_ERQ3_SHIFT (3U)
/*! ERQ3 - Enable DMA Request 3
* 0b0..The DMA request signal for channel 3 is disabled
* 0b1..The DMA request signal for channel 3 is enabled
*/
#define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
#define DMA_ERQ_ERQ4_MASK (0x10U)
#define DMA_ERQ_ERQ4_SHIFT (4U)
/*! ERQ4 - Enable DMA Request 4
* 0b0..The DMA request signal for channel 4 is disabled
* 0b1..The DMA request signal for channel 4 is enabled
*/
#define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
#define DMA_ERQ_ERQ5_MASK (0x20U)
#define DMA_ERQ_ERQ5_SHIFT (5U)
/*! ERQ5 - Enable DMA Request 5
* 0b0..The DMA request signal for channel 5 is disabled
* 0b1..The DMA request signal for channel 5 is enabled
*/
#define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
#define DMA_ERQ_ERQ6_MASK (0x40U)
#define DMA_ERQ_ERQ6_SHIFT (6U)
/*! ERQ6 - Enable DMA Request 6
* 0b0..The DMA request signal for channel 6 is disabled
* 0b1..The DMA request signal for channel 6 is enabled
*/
#define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
#define DMA_ERQ_ERQ7_MASK (0x80U)
#define DMA_ERQ_ERQ7_SHIFT (7U)
/*! ERQ7 - Enable DMA Request 7
* 0b0..The DMA request signal for channel 7 is disabled
* 0b1..The DMA request signal for channel 7 is enabled
*/
#define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
#define DMA_ERQ_ERQ8_MASK (0x100U)
#define DMA_ERQ_ERQ8_SHIFT (8U)
/*! ERQ8 - Enable DMA Request 8
* 0b0..The DMA request signal for channel 8 is disabled
* 0b1..The DMA request signal for channel 8 is enabled
*/
#define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
#define DMA_ERQ_ERQ9_MASK (0x200U)
#define DMA_ERQ_ERQ9_SHIFT (9U)
/*! ERQ9 - Enable DMA Request 9
* 0b0..The DMA request signal for channel 9 is disabled
* 0b1..The DMA request signal for channel 9 is enabled
*/
#define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
#define DMA_ERQ_ERQ10_MASK (0x400U)
#define DMA_ERQ_ERQ10_SHIFT (10U)
/*! ERQ10 - Enable DMA Request 10
* 0b0..The DMA request signal for channel 10 is disabled
* 0b1..The DMA request signal for channel 10 is enabled
*/
#define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
#define DMA_ERQ_ERQ11_MASK (0x800U)
#define DMA_ERQ_ERQ11_SHIFT (11U)
/*! ERQ11 - Enable DMA Request 11
* 0b0..The DMA request signal for channel 11 is disabled
* 0b1..The DMA request signal for channel 11 is enabled
*/
#define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
#define DMA_ERQ_ERQ12_MASK (0x1000U)
#define DMA_ERQ_ERQ12_SHIFT (12U)
/*! ERQ12 - Enable DMA Request 12
* 0b0..The DMA request signal for channel 12 is disabled
* 0b1..The DMA request signal for channel 12 is enabled
*/
#define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
#define DMA_ERQ_ERQ13_MASK (0x2000U)
#define DMA_ERQ_ERQ13_SHIFT (13U)
/*! ERQ13 - Enable DMA Request 13
* 0b0..The DMA request signal for channel 13 is disabled
* 0b1..The DMA request signal for channel 13 is enabled
*/
#define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
#define DMA_ERQ_ERQ14_MASK (0x4000U)
#define DMA_ERQ_ERQ14_SHIFT (14U)
/*! ERQ14 - Enable DMA Request 14
* 0b0..The DMA request signal for channel 14 is disabled
* 0b1..The DMA request signal for channel 14 is enabled
*/
#define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
#define DMA_ERQ_ERQ15_MASK (0x8000U)
#define DMA_ERQ_ERQ15_SHIFT (15U)
/*! ERQ15 - Enable DMA Request 15
* 0b0..The DMA request signal for channel 15 is disabled
* 0b1..The DMA request signal for channel 15 is enabled
*/
#define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
#define DMA_ERQ_ERQ16_MASK (0x10000U)
#define DMA_ERQ_ERQ16_SHIFT (16U)
/*! ERQ16 - Enable DMA Request 16
* 0b0..The DMA request signal for channel 16 is disabled
* 0b1..The DMA request signal for channel 16 is enabled
*/
#define DMA_ERQ_ERQ16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ16_SHIFT)) & DMA_ERQ_ERQ16_MASK)
#define DMA_ERQ_ERQ17_MASK (0x20000U)
#define DMA_ERQ_ERQ17_SHIFT (17U)
/*! ERQ17 - Enable DMA Request 17
* 0b0..The DMA request signal for channel 17 is disabled
* 0b1..The DMA request signal for channel 17 is enabled
*/
#define DMA_ERQ_ERQ17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ17_SHIFT)) & DMA_ERQ_ERQ17_MASK)
#define DMA_ERQ_ERQ18_MASK (0x40000U)
#define DMA_ERQ_ERQ18_SHIFT (18U)
/*! ERQ18 - Enable DMA Request 18
* 0b0..The DMA request signal for channel 18 is disabled
* 0b1..The DMA request signal for channel 18 is enabled
*/
#define DMA_ERQ_ERQ18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ18_SHIFT)) & DMA_ERQ_ERQ18_MASK)
#define DMA_ERQ_ERQ19_MASK (0x80000U)
#define DMA_ERQ_ERQ19_SHIFT (19U)
/*! ERQ19 - Enable DMA Request 19
* 0b0..The DMA request signal for channel 19 is disabled
* 0b1..The DMA request signal for channel 19 is enabled
*/
#define DMA_ERQ_ERQ19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ19_SHIFT)) & DMA_ERQ_ERQ19_MASK)
#define DMA_ERQ_ERQ20_MASK (0x100000U)
#define DMA_ERQ_ERQ20_SHIFT (20U)
/*! ERQ20 - Enable DMA Request 20
* 0b0..The DMA request signal for channel 20 is disabled
* 0b1..The DMA request signal for channel 20 is enabled
*/
#define DMA_ERQ_ERQ20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ20_SHIFT)) & DMA_ERQ_ERQ20_MASK)
#define DMA_ERQ_ERQ21_MASK (0x200000U)
#define DMA_ERQ_ERQ21_SHIFT (21U)
/*! ERQ21 - Enable DMA Request 21
* 0b0..The DMA request signal for channel 21 is disabled
* 0b1..The DMA request signal for channel 21 is enabled
*/
#define DMA_ERQ_ERQ21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ21_SHIFT)) & DMA_ERQ_ERQ21_MASK)
#define DMA_ERQ_ERQ22_MASK (0x400000U)
#define DMA_ERQ_ERQ22_SHIFT (22U)
/*! ERQ22 - Enable DMA Request 22
* 0b0..The DMA request signal for channel 22 is disabled
* 0b1..The DMA request signal for channel 22 is enabled
*/
#define DMA_ERQ_ERQ22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ22_SHIFT)) & DMA_ERQ_ERQ22_MASK)
#define DMA_ERQ_ERQ23_MASK (0x800000U)
#define DMA_ERQ_ERQ23_SHIFT (23U)
/*! ERQ23 - Enable DMA Request 23
* 0b0..The DMA request signal for channel 23 is disabled
* 0b1..The DMA request signal for channel 23 is enabled
*/
#define DMA_ERQ_ERQ23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ23_SHIFT)) & DMA_ERQ_ERQ23_MASK)
#define DMA_ERQ_ERQ24_MASK (0x1000000U)
#define DMA_ERQ_ERQ24_SHIFT (24U)
/*! ERQ24 - Enable DMA Request 24
* 0b0..The DMA request signal for channel 24 is disabled
* 0b1..The DMA request signal for channel 24 is enabled
*/
#define DMA_ERQ_ERQ24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ24_SHIFT)) & DMA_ERQ_ERQ24_MASK)
#define DMA_ERQ_ERQ25_MASK (0x2000000U)
#define DMA_ERQ_ERQ25_SHIFT (25U)
/*! ERQ25 - Enable DMA Request 25
* 0b0..The DMA request signal for channel 25 is disabled
* 0b1..The DMA request signal for channel 25 is enabled
*/
#define DMA_ERQ_ERQ25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ25_SHIFT)) & DMA_ERQ_ERQ25_MASK)
#define DMA_ERQ_ERQ26_MASK (0x4000000U)
#define DMA_ERQ_ERQ26_SHIFT (26U)
/*! ERQ26 - Enable DMA Request 26
* 0b0..The DMA request signal for channel 26 is disabled
* 0b1..The DMA request signal for channel 26 is enabled
*/
#define DMA_ERQ_ERQ26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ26_SHIFT)) & DMA_ERQ_ERQ26_MASK)
#define DMA_ERQ_ERQ27_MASK (0x8000000U)
#define DMA_ERQ_ERQ27_SHIFT (27U)
/*! ERQ27 - Enable DMA Request 27
* 0b0..The DMA request signal for channel 27 is disabled
* 0b1..The DMA request signal for channel 27 is enabled
*/
#define DMA_ERQ_ERQ27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ27_SHIFT)) & DMA_ERQ_ERQ27_MASK)
#define DMA_ERQ_ERQ28_MASK (0x10000000U)
#define DMA_ERQ_ERQ28_SHIFT (28U)
/*! ERQ28 - Enable DMA Request 28
* 0b0..The DMA request signal for channel 28 is disabled
* 0b1..The DMA request signal for channel 28 is enabled
*/
#define DMA_ERQ_ERQ28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ28_SHIFT)) & DMA_ERQ_ERQ28_MASK)
#define DMA_ERQ_ERQ29_MASK (0x20000000U)
#define DMA_ERQ_ERQ29_SHIFT (29U)
/*! ERQ29 - Enable DMA Request 29
* 0b0..The DMA request signal for channel 29 is disabled
* 0b1..The DMA request signal for channel 29 is enabled
*/
#define DMA_ERQ_ERQ29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ29_SHIFT)) & DMA_ERQ_ERQ29_MASK)
#define DMA_ERQ_ERQ30_MASK (0x40000000U)
#define DMA_ERQ_ERQ30_SHIFT (30U)
/*! ERQ30 - Enable DMA Request 30
* 0b0..The DMA request signal for channel 30 is disabled
* 0b1..The DMA request signal for channel 30 is enabled
*/
#define DMA_ERQ_ERQ30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ30_SHIFT)) & DMA_ERQ_ERQ30_MASK)
#define DMA_ERQ_ERQ31_MASK (0x80000000U)
#define DMA_ERQ_ERQ31_SHIFT (31U)
/*! ERQ31 - Enable DMA Request 31
* 0b0..The DMA request signal for channel 31 is disabled
* 0b1..The DMA request signal for channel 31 is enabled
*/
#define DMA_ERQ_ERQ31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ31_SHIFT)) & DMA_ERQ_ERQ31_MASK)
/*! @} */
/*! @name EEI - Enable Error Interrupt */
/*! @{ */
#define DMA_EEI_EEI0_MASK (0x1U)
#define DMA_EEI_EEI0_SHIFT (0U)
/*! EEI0 - Enable Error Interrupt 0
* 0b0..An error on channel 0 does not generate an error interrupt
* 0b1..An error on channel 0 generates an error interrupt request
*/
#define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
#define DMA_EEI_EEI1_MASK (0x2U)
#define DMA_EEI_EEI1_SHIFT (1U)
/*! EEI1 - Enable Error Interrupt 1
* 0b0..An error on channel 1 does not generate an error interrupt
* 0b1..An error on channel 1 generates an error interrupt request
*/
#define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
#define DMA_EEI_EEI2_MASK (0x4U)
#define DMA_EEI_EEI2_SHIFT (2U)
/*! EEI2 - Enable Error Interrupt 2
* 0b0..An error on channel 2 does not generate an error interrupt
* 0b1..An error on channel 2 generates an error interrupt request
*/
#define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
#define DMA_EEI_EEI3_MASK (0x8U)
#define DMA_EEI_EEI3_SHIFT (3U)
/*! EEI3 - Enable Error Interrupt 3
* 0b0..An error on channel 3 does not generate an error interrupt
* 0b1..An error on channel 3 generates an error interrupt request
*/
#define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
#define DMA_EEI_EEI4_MASK (0x10U)
#define DMA_EEI_EEI4_SHIFT (4U)
/*! EEI4 - Enable Error Interrupt 4
* 0b0..An error on channel 4 does not generate an error interrupt
* 0b1..An error on channel 4 generates an error interrupt request
*/
#define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
#define DMA_EEI_EEI5_MASK (0x20U)
#define DMA_EEI_EEI5_SHIFT (5U)
/*! EEI5 - Enable Error Interrupt 5
* 0b0..An error on channel 5 does not generate an error interrupt
* 0b1..An error on channel 5 generates an error interrupt request
*/
#define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
#define DMA_EEI_EEI6_MASK (0x40U)
#define DMA_EEI_EEI6_SHIFT (6U)
/*! EEI6 - Enable Error Interrupt 6
* 0b0..An error on channel 6 does not generate an error interrupt
* 0b1..An error on channel 6 generates an error interrupt request
*/
#define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
#define DMA_EEI_EEI7_MASK (0x80U)
#define DMA_EEI_EEI7_SHIFT (7U)
/*! EEI7 - Enable Error Interrupt 7
* 0b0..An error on channel 7 does not generate an error interrupt
* 0b1..An error on channel 7 generates an error interrupt request
*/
#define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
#define DMA_EEI_EEI8_MASK (0x100U)
#define DMA_EEI_EEI8_SHIFT (8U)
/*! EEI8 - Enable Error Interrupt 8
* 0b0..An error on channel 8 does not generate an error interrupt
* 0b1..An error on channel 8 generates an error interrupt request
*/
#define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
#define DMA_EEI_EEI9_MASK (0x200U)
#define DMA_EEI_EEI9_SHIFT (9U)
/*! EEI9 - Enable Error Interrupt 9
* 0b0..An error on channel 9 does not generate an error interrupt
* 0b1..An error on channel 9 generates an error interrupt request
*/
#define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
#define DMA_EEI_EEI10_MASK (0x400U)
#define DMA_EEI_EEI10_SHIFT (10U)
/*! EEI10 - Enable Error Interrupt 10
* 0b0..An error on channel 10 does not generate an error interrupt
* 0b1..An error on channel 10 generates an error interrupt request
*/
#define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
#define DMA_EEI_EEI11_MASK (0x800U)
#define DMA_EEI_EEI11_SHIFT (11U)
/*! EEI11 - Enable Error Interrupt 11
* 0b0..An error on channel 11 does not generate an error interrupt
* 0b1..An error on channel 11 generates an error interrupt request
*/
#define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
#define DMA_EEI_EEI12_MASK (0x1000U)
#define DMA_EEI_EEI12_SHIFT (12U)
/*! EEI12 - Enable Error Interrupt 12
* 0b0..An error on channel 12 does not generate an error interrupt
* 0b1..An error on channel 12 generates an error interrupt request
*/
#define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
#define DMA_EEI_EEI13_MASK (0x2000U)
#define DMA_EEI_EEI13_SHIFT (13U)
/*! EEI13 - Enable Error Interrupt 13
* 0b0..An error on channel 13 does not generate an error interrupt
* 0b1..An error on channel 13 generates an error interrupt request
*/
#define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
#define DMA_EEI_EEI14_MASK (0x4000U)
#define DMA_EEI_EEI14_SHIFT (14U)
/*! EEI14 - Enable Error Interrupt 14
* 0b0..An error on channel 14 does not generate an error interrupt
* 0b1..An error on channel 14 generates an error interrupt request
*/
#define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
#define DMA_EEI_EEI15_MASK (0x8000U)
#define DMA_EEI_EEI15_SHIFT (15U)
/*! EEI15 - Enable Error Interrupt 15
* 0b0..An error on channel 15 does not generate an error interrupt
* 0b1..An error on channel 15 generates an error interrupt request
*/
#define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
#define DMA_EEI_EEI16_MASK (0x10000U)
#define DMA_EEI_EEI16_SHIFT (16U)
/*! EEI16 - Enable Error Interrupt 16
* 0b0..An error on channel 16 does not generate an error interrupt
* 0b1..An error on channel 16 generates an error interrupt request
*/
#define DMA_EEI_EEI16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI16_SHIFT)) & DMA_EEI_EEI16_MASK)
#define DMA_EEI_EEI17_MASK (0x20000U)
#define DMA_EEI_EEI17_SHIFT (17U)
/*! EEI17 - Enable Error Interrupt 17
* 0b0..An error on channel 17 does not generate an error interrupt
* 0b1..An error on channel 17 generates an error interrupt request
*/
#define DMA_EEI_EEI17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI17_SHIFT)) & DMA_EEI_EEI17_MASK)
#define DMA_EEI_EEI18_MASK (0x40000U)
#define DMA_EEI_EEI18_SHIFT (18U)
/*! EEI18 - Enable Error Interrupt 18
* 0b0..An error on channel 18 does not generate an error interrupt
* 0b1..An error on channel 18 generates an error interrupt request
*/
#define DMA_EEI_EEI18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI18_SHIFT)) & DMA_EEI_EEI18_MASK)
#define DMA_EEI_EEI19_MASK (0x80000U)
#define DMA_EEI_EEI19_SHIFT (19U)
/*! EEI19 - Enable Error Interrupt 19
* 0b0..An error on channel 19 does not generate an error interrupt
* 0b1..An error on channel 19 generates an error interrupt request
*/
#define DMA_EEI_EEI19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI19_SHIFT)) & DMA_EEI_EEI19_MASK)
#define DMA_EEI_EEI20_MASK (0x100000U)
#define DMA_EEI_EEI20_SHIFT (20U)
/*! EEI20 - Enable Error Interrupt 20
* 0b0..An error on channel 20 does not generate an error interrupt
* 0b1..An error on channel 20 generates an error interrupt request
*/
#define DMA_EEI_EEI20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI20_SHIFT)) & DMA_EEI_EEI20_MASK)
#define DMA_EEI_EEI21_MASK (0x200000U)
#define DMA_EEI_EEI21_SHIFT (21U)
/*! EEI21 - Enable Error Interrupt 21
* 0b0..An error on channel 21 does not generate an error interrupt
* 0b1..An error on channel 21 generates an error interrupt request
*/
#define DMA_EEI_EEI21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI21_SHIFT)) & DMA_EEI_EEI21_MASK)
#define DMA_EEI_EEI22_MASK (0x400000U)
#define DMA_EEI_EEI22_SHIFT (22U)
/*! EEI22 - Enable Error Interrupt 22
* 0b0..An error on channel 22 does not generate an error interrupt
* 0b1..An error on channel 22 generates an error interrupt request
*/
#define DMA_EEI_EEI22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI22_SHIFT)) & DMA_EEI_EEI22_MASK)
#define DMA_EEI_EEI23_MASK (0x800000U)
#define DMA_EEI_EEI23_SHIFT (23U)
/*! EEI23 - Enable Error Interrupt 23
* 0b0..An error on channel 23 does not generate an error interrupt
* 0b1..An error on channel 23 generates an error interrupt request
*/
#define DMA_EEI_EEI23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI23_SHIFT)) & DMA_EEI_EEI23_MASK)
#define DMA_EEI_EEI24_MASK (0x1000000U)
#define DMA_EEI_EEI24_SHIFT (24U)
/*! EEI24 - Enable Error Interrupt 24
* 0b0..An error on channel 24 does not generate an error interrupt
* 0b1..An error on channel 24 generates an error interrupt request
*/
#define DMA_EEI_EEI24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI24_SHIFT)) & DMA_EEI_EEI24_MASK)
#define DMA_EEI_EEI25_MASK (0x2000000U)
#define DMA_EEI_EEI25_SHIFT (25U)
/*! EEI25 - Enable Error Interrupt 25
* 0b0..An error on channel 25 does not generate an error interrupt
* 0b1..An error on channel 25 generates an error interrupt request
*/
#define DMA_EEI_EEI25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI25_SHIFT)) & DMA_EEI_EEI25_MASK)
#define DMA_EEI_EEI26_MASK (0x4000000U)
#define DMA_EEI_EEI26_SHIFT (26U)
/*! EEI26 - Enable Error Interrupt 26
* 0b0..An error on channel 26 does not generate an error interrupt
* 0b1..An error on channel 26 generates an error interrupt request
*/
#define DMA_EEI_EEI26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI26_SHIFT)) & DMA_EEI_EEI26_MASK)
#define DMA_EEI_EEI27_MASK (0x8000000U)
#define DMA_EEI_EEI27_SHIFT (27U)
/*! EEI27 - Enable Error Interrupt 27
* 0b0..An error on channel 27 does not generate an error interrupt
* 0b1..An error on channel 27 generates an error interrupt request
*/
#define DMA_EEI_EEI27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI27_SHIFT)) & DMA_EEI_EEI27_MASK)
#define DMA_EEI_EEI28_MASK (0x10000000U)
#define DMA_EEI_EEI28_SHIFT (28U)
/*! EEI28 - Enable Error Interrupt 28
* 0b0..An error on channel 28 does not generate an error interrupt
* 0b1..An error on channel 28 generates an error interrupt request
*/
#define DMA_EEI_EEI28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI28_SHIFT)) & DMA_EEI_EEI28_MASK)
#define DMA_EEI_EEI29_MASK (0x20000000U)
#define DMA_EEI_EEI29_SHIFT (29U)
/*! EEI29 - Enable Error Interrupt 29
* 0b0..An error on channel 29 does not generate an error interrupt
* 0b1..An error on channel 29 generates an error interrupt request
*/
#define DMA_EEI_EEI29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI29_SHIFT)) & DMA_EEI_EEI29_MASK)
#define DMA_EEI_EEI30_MASK (0x40000000U)
#define DMA_EEI_EEI30_SHIFT (30U)
/*! EEI30 - Enable Error Interrupt 30
* 0b0..An error on channel 30 does not generate an error interrupt
* 0b1..An error on channel 30 generates an error interrupt request
*/
#define DMA_EEI_EEI30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI30_SHIFT)) & DMA_EEI_EEI30_MASK)
#define DMA_EEI_EEI31_MASK (0x80000000U)
#define DMA_EEI_EEI31_SHIFT (31U)
/*! EEI31 - Enable Error Interrupt 31
* 0b0..An error on channel 31 does not generate an error interrupt
* 0b1..An error on channel 31 generates an error interrupt request
*/
#define DMA_EEI_EEI31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI31_SHIFT)) & DMA_EEI_EEI31_MASK)
/*! @} */
/*! @name CEEI - Clear Enable Error Interrupt */
/*! @{ */
#define DMA_CEEI_CEEI_MASK (0x1FU)
#define DMA_CEEI_CEEI_SHIFT (0U)
/*! CEEI - Clear Enable Error Interrupt
*/
#define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
#define DMA_CEEI_CAEE_MASK (0x40U)
#define DMA_CEEI_CAEE_SHIFT (6U)
/*! CAEE - Clear All Enable Error Interrupts
* 0b0..Write 0 only to the EEI field specified in the CEEI field
* 0b1..Write 0 to all fields in EEI
*/
#define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
#define DMA_CEEI_NOP_MASK (0x80U)
#define DMA_CEEI_NOP_SHIFT (7U)
/*! NOP - No Op Enable
* 0b0..Normal operation
* 0b1..No operation, ignore the other fields in this register
*/
#define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
/*! @} */
/*! @name SEEI - Set Enable Error Interrupt */
/*! @{ */
#define DMA_SEEI_SEEI_MASK (0x1FU)
#define DMA_SEEI_SEEI_SHIFT (0U)
/*! SEEI - Set Enable Error Interrupt
*/
#define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
#define DMA_SEEI_SAEE_MASK (0x40U)
#define DMA_SEEI_SAEE_SHIFT (6U)
/*! SAEE - Set All Enable Error Interrupts
* 0b0..Write 1 only to the EEI field specified in the SEEI field
* 0b1..Writes 1 to all fields in EEI
*/
#define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
#define DMA_SEEI_NOP_MASK (0x80U)
#define DMA_SEEI_NOP_SHIFT (7U)
/*! NOP - No Op Enable
* 0b0..Normal operation
* 0b1..No operation, ignore the other fields in this register
*/
#define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
/*! @} */
/*! @name CERQ - Clear Enable Request */
/*! @{ */
#define DMA_CERQ_CERQ_MASK (0x1FU)
#define DMA_CERQ_CERQ_SHIFT (0U)
/*! CERQ - Clear Enable Request
*/
#define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
#define DMA_CERQ_CAER_MASK (0x40U)
#define DMA_CERQ_CAER_SHIFT (6U)
/*! CAER - Clear All Enable Requests
* 0b0..Write 0 to only the ERQ field specified in the CERQ field
* 0b1..Write 0 to all fields in ERQ
*/
#define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
#define DMA_CERQ_NOP_MASK (0x80U)
#define DMA_CERQ_NOP_SHIFT (7U)
/*! NOP - No Op Enable
* 0b0..Normal operation
* 0b1..No operation, ignore the other fields in this register
*/
#define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
/*! @} */
/*! @name SERQ - Set Enable Request */
/*! @{ */
#define DMA_SERQ_SERQ_MASK (0x1FU)
#define DMA_SERQ_SERQ_SHIFT (0U)
/*! SERQ - Set Enable Request
*/
#define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
#define DMA_SERQ_SAER_MASK (0x40U)
#define DMA_SERQ_SAER_SHIFT (6U)
/*! SAER - Set All Enable Requests
* 0b0..Write 1 to only the ERQ field specified in the SERQ field
* 0b1..Write 1 to all fields in ERQ
*/
#define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
#define DMA_SERQ_NOP_MASK (0x80U)
#define DMA_SERQ_NOP_SHIFT (7U)
/*! NOP - No Op Enable
* 0b0..Normal operation
* 0b1..No operation, ignore the other fields in this register
*/
#define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
/*! @} */
/*! @name CDNE - Clear DONE Status Bit */
/*! @{ */
#define DMA_CDNE_CDNE_MASK (0x1FU)
#define DMA_CDNE_CDNE_SHIFT (0U)
/*! CDNE - Clear DONE field
*/
#define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
#define DMA_CDNE_CADN_MASK (0x40U)
#define DMA_CDNE_CADN_SHIFT (6U)
/*! CADN - Clears All DONE fields
* 0b0..Writes 0 to only the TCDn_CSR[DONE] field specified in the CDNE field
* 0b1..Writes 0 to all bits in TCDn_CSR[DONE]
*/
#define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
#define DMA_CDNE_NOP_MASK (0x80U)
#define DMA_CDNE_NOP_SHIFT (7U)
/*! NOP - No Op Enable
* 0b0..Normal operation
* 0b1..No operation; all other fields in this register are ignored.
*/
#define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
/*! @} */
/*! @name SSRT - Set START Bit */
/*! @{ */
#define DMA_SSRT_SSRT_MASK (0x1FU)
#define DMA_SSRT_SSRT_SHIFT (0U)
/*! SSRT - Set START field
*/
#define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
#define DMA_SSRT_SAST_MASK (0x40U)
#define DMA_SSRT_SAST_SHIFT (6U)
/*! SAST - Set All START fields (activates all channels)
* 0b0..Write 1 to only the TCDn_CSR[START] field specified in the SSRT field
* 0b1..Write 1 to all bits in TCDn_CSR[START]
*/
#define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
#define DMA_SSRT_NOP_MASK (0x80U)
#define DMA_SSRT_NOP_SHIFT (7U)
/*! NOP - No Op Enable
* 0b0..Normal operation
* 0b1..No operation; all other fields in this register are ignored.
*/
#define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
/*! @} */
/*! @name CERR - Clear Error */
/*! @{ */
#define DMA_CERR_CERR_MASK (0x1FU)
#define DMA_CERR_CERR_SHIFT (0U)
/*! CERR - Clear Error Indicator
*/
#define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
#define DMA_CERR_CAEI_MASK (0x40U)
#define DMA_CERR_CAEI_SHIFT (6U)
/*! CAEI - Clear All Error Indicators
* 0b0..Write 0 to only the ERR field specified in the CERR field
* 0b1..Write 0 to all fields in ERR
*/
#define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
#define DMA_CERR_NOP_MASK (0x80U)
#define DMA_CERR_NOP_SHIFT (7U)
/*! NOP - No Op Enable
* 0b0..Normal operation
* 0b1..No operation; all other fields in this register are ignored.
*/
#define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
/*! @} */
/*! @name CINT - Clear Interrupt Request */
/*! @{ */
#define DMA_CINT_CINT_MASK (0x1FU)
#define DMA_CINT_CINT_SHIFT (0U)
/*! CINT - Clear Interrupt Request
*/
#define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
#define DMA_CINT_CAIR_MASK (0x40U)
#define DMA_CINT_CAIR_SHIFT (6U)
/*! CAIR - Clear All Interrupt Requests
* 0b0..Clear only the INT field specified in the CINT field
* 0b1..Clear all bits in INT
*/
#define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
#define DMA_CINT_NOP_MASK (0x80U)
#define DMA_CINT_NOP_SHIFT (7U)
/*! NOP - No Op Enable
* 0b0..Normal operation
* 0b1..No operation; all other fields in this register are ignored.
*/
#define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
/*! @} */
/*! @name INT - Interrupt Request */
/*! @{ */
#define DMA_INT_INT0_MASK (0x1U)
#define DMA_INT_INT0_SHIFT (0U)
/*! INT0 - Interrupt Request 0
* 0b0..The interrupt request for channel 0 is cleared
* 0b1..The interrupt request for channel 0 is active
*/
#define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
#define DMA_INT_INT1_MASK (0x2U)
#define DMA_INT_INT1_SHIFT (1U)
/*! INT1 - Interrupt Request 1
* 0b0..The interrupt request for channel 1 is cleared
* 0b1..The interrupt request for channel 1 is active
*/
#define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
#define DMA_INT_INT2_MASK (0x4U)
#define DMA_INT_INT2_SHIFT (2U)
/*! INT2 - Interrupt Request 2
* 0b0..The interrupt request for channel 2 is cleared
* 0b1..The interrupt request for channel 2 is active
*/
#define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
#define DMA_INT_INT3_MASK (0x8U)
#define DMA_INT_INT3_SHIFT (3U)
/*! INT3 - Interrupt Request 3
* 0b0..The interrupt request for channel 3 is cleared
* 0b1..The interrupt request for channel 3 is active
*/
#define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
#define DMA_INT_INT4_MASK (0x10U)
#define DMA_INT_INT4_SHIFT (4U)
/*! INT4 - Interrupt Request 4
* 0b0..The interrupt request for channel 4 is cleared
* 0b1..The interrupt request for channel 4 is active
*/
#define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
#define DMA_INT_INT5_MASK (0x20U)
#define DMA_INT_INT5_SHIFT (5U)
/*! INT5 - Interrupt Request 5
* 0b0..The interrupt request for channel 5 is cleared
* 0b1..The interrupt request for channel 5 is active
*/
#define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
#define DMA_INT_INT6_MASK (0x40U)
#define DMA_INT_INT6_SHIFT (6U)
/*! INT6 - Interrupt Request 6
* 0b0..The interrupt request for channel 6 is cleared
* 0b1..The interrupt request for channel 6 is active
*/
#define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
#define DMA_INT_INT7_MASK (0x80U)
#define DMA_INT_INT7_SHIFT (7U)
/*! INT7 - Interrupt Request 7
* 0b0..The interrupt request for channel 7 is cleared
* 0b1..The interrupt request for channel 7 is active
*/
#define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
#define DMA_INT_INT8_MASK (0x100U)
#define DMA_INT_INT8_SHIFT (8U)
/*! INT8 - Interrupt Request 8
* 0b0..The interrupt request for channel 8 is cleared
* 0b1..The interrupt request for channel 8 is active
*/
#define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
#define DMA_INT_INT9_MASK (0x200U)
#define DMA_INT_INT9_SHIFT (9U)
/*! INT9 - Interrupt Request 9
* 0b0..The interrupt request for channel 9 is cleared
* 0b1..The interrupt request for channel 9 is active
*/
#define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
#define DMA_INT_INT10_MASK (0x400U)
#define DMA_INT_INT10_SHIFT (10U)
/*! INT10 - Interrupt Request 10
* 0b0..The interrupt request for channel 10 is cleared
* 0b1..The interrupt request for channel 10 is active
*/
#define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
#define DMA_INT_INT11_MASK (0x800U)
#define DMA_INT_INT11_SHIFT (11U)
/*! INT11 - Interrupt Request 11
* 0b0..The interrupt request for channel 11 is cleared
* 0b1..The interrupt request for channel 11 is active
*/
#define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
#define DMA_INT_INT12_MASK (0x1000U)
#define DMA_INT_INT12_SHIFT (12U)
/*! INT12 - Interrupt Request 12
* 0b0..The interrupt request for channel 12 is cleared
* 0b1..The interrupt request for channel 12 is active
*/
#define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
#define DMA_INT_INT13_MASK (0x2000U)
#define DMA_INT_INT13_SHIFT (13U)
/*! INT13 - Interrupt Request 13
* 0b0..The interrupt request for channel 13 is cleared
* 0b1..The interrupt request for channel 13 is active
*/
#define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
#define DMA_INT_INT14_MASK (0x4000U)
#define DMA_INT_INT14_SHIFT (14U)
/*! INT14 - Interrupt Request 14
* 0b0..The interrupt request for channel 14 is cleared
* 0b1..The interrupt request for channel 14 is active
*/
#define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
#define DMA_INT_INT15_MASK (0x8000U)
#define DMA_INT_INT15_SHIFT (15U)
/*! INT15 - Interrupt Request 15
* 0b0..The interrupt request for channel 15 is cleared
* 0b1..The interrupt request for channel 15 is active
*/
#define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
#define DMA_INT_INT16_MASK (0x10000U)
#define DMA_INT_INT16_SHIFT (16U)
/*! INT16 - Interrupt Request 16
* 0b0..The interrupt request for channel 16 is cleared
* 0b1..The interrupt request for channel 16 is active
*/
#define DMA_INT_INT16(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT16_SHIFT)) & DMA_INT_INT16_MASK)
#define DMA_INT_INT17_MASK (0x20000U)
#define DMA_INT_INT17_SHIFT (17U)
/*! INT17 - Interrupt Request 17
* 0b0..The interrupt request for channel 17 is cleared
* 0b1..The interrupt request for channel 17 is active
*/
#define DMA_INT_INT17(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT17_SHIFT)) & DMA_INT_INT17_MASK)
#define DMA_INT_INT18_MASK (0x40000U)
#define DMA_INT_INT18_SHIFT (18U)
/*! INT18 - Interrupt Request 18
* 0b0..The interrupt request for channel 18 is cleared
* 0b1..The interrupt request for channel 18 is active
*/
#define DMA_INT_INT18(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT18_SHIFT)) & DMA_INT_INT18_MASK)
#define DMA_INT_INT19_MASK (0x80000U)
#define DMA_INT_INT19_SHIFT (19U)
/*! INT19 - Interrupt Request 19
* 0b0..The interrupt request for channel 19 is cleared
* 0b1..The interrupt request for channel 19 is active
*/
#define DMA_INT_INT19(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT19_SHIFT)) & DMA_INT_INT19_MASK)
#define DMA_INT_INT20_MASK (0x100000U)
#define DMA_INT_INT20_SHIFT (20U)
/*! INT20 - Interrupt Request 20
* 0b0..The interrupt request for channel 20 is cleared
* 0b1..The interrupt request for channel 20 is active
*/
#define DMA_INT_INT20(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT20_SHIFT)) & DMA_INT_INT20_MASK)
#define DMA_INT_INT21_MASK (0x200000U)
#define DMA_INT_INT21_SHIFT (21U)
/*! INT21 - Interrupt Request 21
* 0b0..The interrupt request for channel 21 is cleared
* 0b1..The interrupt request for channel 21 is active
*/
#define DMA_INT_INT21(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT21_SHIFT)) & DMA_INT_INT21_MASK)
#define DMA_INT_INT22_MASK (0x400000U)
#define DMA_INT_INT22_SHIFT (22U)
/*! INT22 - Interrupt Request 22
* 0b0..The interrupt request for channel 22 is cleared
* 0b1..The interrupt request for channel 22 is active
*/
#define DMA_INT_INT22(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT22_SHIFT)) & DMA_INT_INT22_MASK)
#define DMA_INT_INT23_MASK (0x800000U)
#define DMA_INT_INT23_SHIFT (23U)
/*! INT23 - Interrupt Request 23
* 0b0..The interrupt request for channel 23 is cleared
* 0b1..The interrupt request for channel 23 is active
*/
#define DMA_INT_INT23(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT23_SHIFT)) & DMA_INT_INT23_MASK)
#define DMA_INT_INT24_MASK (0x1000000U)
#define DMA_INT_INT24_SHIFT (24U)
/*! INT24 - Interrupt Request 24
* 0b0..The interrupt request for channel 24 is cleared
* 0b1..The interrupt request for channel 24 is active
*/
#define DMA_INT_INT24(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT24_SHIFT)) & DMA_INT_INT24_MASK)
#define DMA_INT_INT25_MASK (0x2000000U)
#define DMA_INT_INT25_SHIFT (25U)
/*! INT25 - Interrupt Request 25
* 0b0..The interrupt request for channel 25 is cleared
* 0b1..The interrupt request for channel 25 is active
*/
#define DMA_INT_INT25(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT25_SHIFT)) & DMA_INT_INT25_MASK)
#define DMA_INT_INT26_MASK (0x4000000U)
#define DMA_INT_INT26_SHIFT (26U)
/*! INT26 - Interrupt Request 26
* 0b0..The interrupt request for channel 26 is cleared
* 0b1..The interrupt request for channel 26 is active
*/
#define DMA_INT_INT26(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT26_SHIFT)) & DMA_INT_INT26_MASK)
#define DMA_INT_INT27_MASK (0x8000000U)
#define DMA_INT_INT27_SHIFT (27U)
/*! INT27 - Interrupt Request 27
* 0b0..The interrupt request for channel 27 is cleared
* 0b1..The interrupt request for channel 27 is active
*/
#define DMA_INT_INT27(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT27_SHIFT)) & DMA_INT_INT27_MASK)
#define DMA_INT_INT28_MASK (0x10000000U)
#define DMA_INT_INT28_SHIFT (28U)
/*! INT28 - Interrupt Request 28
* 0b0..The interrupt request for channel 28 is cleared
* 0b1..The interrupt request for channel 28 is active
*/
#define DMA_INT_INT28(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT28_SHIFT)) & DMA_INT_INT28_MASK)
#define DMA_INT_INT29_MASK (0x20000000U)
#define DMA_INT_INT29_SHIFT (29U)
/*! INT29 - Interrupt Request 29
* 0b0..The interrupt request for channel 29 is cleared
* 0b1..The interrupt request for channel 29 is active
*/
#define DMA_INT_INT29(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT29_SHIFT)) & DMA_INT_INT29_MASK)
#define DMA_INT_INT30_MASK (0x40000000U)
#define DMA_INT_INT30_SHIFT (30U)
/*! INT30 - Interrupt Request 30
* 0b0..The interrupt request for channel 30 is cleared
* 0b1..The interrupt request for channel 30 is active
*/
#define DMA_INT_INT30(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT30_SHIFT)) & DMA_INT_INT30_MASK)
#define DMA_INT_INT31_MASK (0x80000000U)
#define DMA_INT_INT31_SHIFT (31U)
/*! INT31 - Interrupt Request 31
* 0b0..The interrupt request for channel 31 is cleared
* 0b1..The interrupt request for channel 31 is active
*/
#define DMA_INT_INT31(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT31_SHIFT)) & DMA_INT_INT31_MASK)
/*! @} */
/*! @name ERR - Error */
/*! @{ */
#define DMA_ERR_ERR0_MASK (0x1U)
#define DMA_ERR_ERR0_SHIFT (0U)
/*! ERR0 - Error In Channel 0
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
#define DMA_ERR_ERR1_MASK (0x2U)
#define DMA_ERR_ERR1_SHIFT (1U)
/*! ERR1 - Error In Channel 1
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
#define DMA_ERR_ERR2_MASK (0x4U)
#define DMA_ERR_ERR2_SHIFT (2U)
/*! ERR2 - Error In Channel 2
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
#define DMA_ERR_ERR3_MASK (0x8U)
#define DMA_ERR_ERR3_SHIFT (3U)
/*! ERR3 - Error In Channel 3
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
#define DMA_ERR_ERR4_MASK (0x10U)
#define DMA_ERR_ERR4_SHIFT (4U)
/*! ERR4 - Error In Channel 4
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
#define DMA_ERR_ERR5_MASK (0x20U)
#define DMA_ERR_ERR5_SHIFT (5U)
/*! ERR5 - Error In Channel 5
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
#define DMA_ERR_ERR6_MASK (0x40U)
#define DMA_ERR_ERR6_SHIFT (6U)
/*! ERR6 - Error In Channel 6
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
#define DMA_ERR_ERR7_MASK (0x80U)
#define DMA_ERR_ERR7_SHIFT (7U)
/*! ERR7 - Error In Channel 7
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
#define DMA_ERR_ERR8_MASK (0x100U)
#define DMA_ERR_ERR8_SHIFT (8U)
/*! ERR8 - Error In Channel 8
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
#define DMA_ERR_ERR9_MASK (0x200U)
#define DMA_ERR_ERR9_SHIFT (9U)
/*! ERR9 - Error In Channel 9
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
#define DMA_ERR_ERR10_MASK (0x400U)
#define DMA_ERR_ERR10_SHIFT (10U)
/*! ERR10 - Error In Channel 10
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
#define DMA_ERR_ERR11_MASK (0x800U)
#define DMA_ERR_ERR11_SHIFT (11U)
/*! ERR11 - Error In Channel 11
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
#define DMA_ERR_ERR12_MASK (0x1000U)
#define DMA_ERR_ERR12_SHIFT (12U)
/*! ERR12 - Error In Channel 12
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
#define DMA_ERR_ERR13_MASK (0x2000U)
#define DMA_ERR_ERR13_SHIFT (13U)
/*! ERR13 - Error In Channel 13
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
#define DMA_ERR_ERR14_MASK (0x4000U)
#define DMA_ERR_ERR14_SHIFT (14U)
/*! ERR14 - Error In Channel 14
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
#define DMA_ERR_ERR15_MASK (0x8000U)
#define DMA_ERR_ERR15_SHIFT (15U)
/*! ERR15 - Error In Channel 15
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
#define DMA_ERR_ERR16_MASK (0x10000U)
#define DMA_ERR_ERR16_SHIFT (16U)
/*! ERR16 - Error In Channel 16
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR16(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR16_SHIFT)) & DMA_ERR_ERR16_MASK)
#define DMA_ERR_ERR17_MASK (0x20000U)
#define DMA_ERR_ERR17_SHIFT (17U)
/*! ERR17 - Error In Channel 17
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR17(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR17_SHIFT)) & DMA_ERR_ERR17_MASK)
#define DMA_ERR_ERR18_MASK (0x40000U)
#define DMA_ERR_ERR18_SHIFT (18U)
/*! ERR18 - Error In Channel 18
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR18(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR18_SHIFT)) & DMA_ERR_ERR18_MASK)
#define DMA_ERR_ERR19_MASK (0x80000U)
#define DMA_ERR_ERR19_SHIFT (19U)
/*! ERR19 - Error In Channel 19
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR19(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR19_SHIFT)) & DMA_ERR_ERR19_MASK)
#define DMA_ERR_ERR20_MASK (0x100000U)
#define DMA_ERR_ERR20_SHIFT (20U)
/*! ERR20 - Error In Channel 20
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR20(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR20_SHIFT)) & DMA_ERR_ERR20_MASK)
#define DMA_ERR_ERR21_MASK (0x200000U)
#define DMA_ERR_ERR21_SHIFT (21U)
/*! ERR21 - Error In Channel 21
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR21(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR21_SHIFT)) & DMA_ERR_ERR21_MASK)
#define DMA_ERR_ERR22_MASK (0x400000U)
#define DMA_ERR_ERR22_SHIFT (22U)
/*! ERR22 - Error In Channel 22
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR22(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR22_SHIFT)) & DMA_ERR_ERR22_MASK)
#define DMA_ERR_ERR23_MASK (0x800000U)
#define DMA_ERR_ERR23_SHIFT (23U)
/*! ERR23 - Error In Channel 23
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR23(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR23_SHIFT)) & DMA_ERR_ERR23_MASK)
#define DMA_ERR_ERR24_MASK (0x1000000U)
#define DMA_ERR_ERR24_SHIFT (24U)
/*! ERR24 - Error In Channel 24
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR24(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR24_SHIFT)) & DMA_ERR_ERR24_MASK)
#define DMA_ERR_ERR25_MASK (0x2000000U)
#define DMA_ERR_ERR25_SHIFT (25U)
/*! ERR25 - Error In Channel 25
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR25(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR25_SHIFT)) & DMA_ERR_ERR25_MASK)
#define DMA_ERR_ERR26_MASK (0x4000000U)
#define DMA_ERR_ERR26_SHIFT (26U)
/*! ERR26 - Error In Channel 26
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR26(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR26_SHIFT)) & DMA_ERR_ERR26_MASK)
#define DMA_ERR_ERR27_MASK (0x8000000U)
#define DMA_ERR_ERR27_SHIFT (27U)
/*! ERR27 - Error In Channel 27
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR27(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR27_SHIFT)) & DMA_ERR_ERR27_MASK)
#define DMA_ERR_ERR28_MASK (0x10000000U)
#define DMA_ERR_ERR28_SHIFT (28U)
/*! ERR28 - Error In Channel 28
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR28(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR28_SHIFT)) & DMA_ERR_ERR28_MASK)
#define DMA_ERR_ERR29_MASK (0x20000000U)
#define DMA_ERR_ERR29_SHIFT (29U)
/*! ERR29 - Error In Channel 29
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR29(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR29_SHIFT)) & DMA_ERR_ERR29_MASK)
#define DMA_ERR_ERR30_MASK (0x40000000U)
#define DMA_ERR_ERR30_SHIFT (30U)
/*! ERR30 - Error In Channel 30
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR30(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR30_SHIFT)) & DMA_ERR_ERR30_MASK)
#define DMA_ERR_ERR31_MASK (0x80000000U)
#define DMA_ERR_ERR31_SHIFT (31U)
/*! ERR31 - Error In Channel 31
* 0b0..No error in this channel has occurred
* 0b1..An error in this channel has occurred
*/
#define DMA_ERR_ERR31(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR31_SHIFT)) & DMA_ERR_ERR31_MASK)
/*! @} */
/*! @name HRS - Hardware Request Status */
/*! @{ */
#define DMA_HRS_HRS0_MASK (0x1U)
#define DMA_HRS_HRS0_SHIFT (0U)
/*! HRS0 - Hardware Request Status Channel 0
* 0b0..A hardware service request for channel 0 is not present
* 0b1..A hardware service request for channel 0 is present
*/
#define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
#define DMA_HRS_HRS1_MASK (0x2U)
#define DMA_HRS_HRS1_SHIFT (1U)
/*! HRS1 - Hardware Request Status Channel 1
* 0b0..A hardware service request for channel 1 is not present
* 0b1..A hardware service request for channel 1 is present
*/
#define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
#define DMA_HRS_HRS2_MASK (0x4U)
#define DMA_HRS_HRS2_SHIFT (2U)
/*! HRS2 - Hardware Request Status Channel 2
* 0b0..A hardware service request for channel 2 is not present
* 0b1..A hardware service request for channel 2 is present
*/
#define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
#define DMA_HRS_HRS3_MASK (0x8U)
#define DMA_HRS_HRS3_SHIFT (3U)
/*! HRS3 - Hardware Request Status Channel 3
* 0b0..A hardware service request for channel 3 is not present
* 0b1..A hardware service request for channel 3 is present
*/
#define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
#define DMA_HRS_HRS4_MASK (0x10U)
#define DMA_HRS_HRS4_SHIFT (4U)
/*! HRS4 - Hardware Request Status Channel 4
* 0b0..A hardware service request for channel 4 is not present
* 0b1..A hardware service request for channel 4 is present
*/
#define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
#define DMA_HRS_HRS5_MASK (0x20U)
#define DMA_HRS_HRS5_SHIFT (5U)
/*! HRS5 - Hardware Request Status Channel 5
* 0b0..A hardware service request for channel 5 is not present
* 0b1..A hardware service request for channel 5 is present
*/
#define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
#define DMA_HRS_HRS6_MASK (0x40U)
#define DMA_HRS_HRS6_SHIFT (6U)
/*! HRS6 - Hardware Request Status Channel 6
* 0b0..A hardware service request for channel 6 is not present
* 0b1..A hardware service request for channel 6 is present
*/
#define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
#define DMA_HRS_HRS7_MASK (0x80U)
#define DMA_HRS_HRS7_SHIFT (7U)
/*! HRS7 - Hardware Request Status Channel 7
* 0b0..A hardware service request for channel 7 is not present
* 0b1..A hardware service request for channel 7 is present
*/
#define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
#define DMA_HRS_HRS8_MASK (0x100U)
#define DMA_HRS_HRS8_SHIFT (8U)
/*! HRS8 - Hardware Request Status Channel 8
* 0b0..A hardware service request for channel 8 is not present
* 0b1..A hardware service request for channel 8 is present
*/
#define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
#define DMA_HRS_HRS9_MASK (0x200U)
#define DMA_HRS_HRS9_SHIFT (9U)
/*! HRS9 - Hardware Request Status Channel 9
* 0b0..A hardware service request for channel 9 is not present
* 0b1..A hardware service request for channel 9 is present
*/
#define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
#define DMA_HRS_HRS10_MASK (0x400U)
#define DMA_HRS_HRS10_SHIFT (10U)
/*! HRS10 - Hardware Request Status Channel 10
* 0b0..A hardware service request for channel 10 is not present
* 0b1..A hardware service request for channel 10 is present
*/
#define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
#define DMA_HRS_HRS11_MASK (0x800U)
#define DMA_HRS_HRS11_SHIFT (11U)
/*! HRS11 - Hardware Request Status Channel 11
* 0b0..A hardware service request for channel 11 is not present
* 0b1..A hardware service request for channel 11 is present
*/
#define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
#define DMA_HRS_HRS12_MASK (0x1000U)
#define DMA_HRS_HRS12_SHIFT (12U)
/*! HRS12 - Hardware Request Status Channel 12
* 0b0..A hardware service request for channel 12 is not present
* 0b1..A hardware service request for channel 12 is present
*/
#define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
#define DMA_HRS_HRS13_MASK (0x2000U)
#define DMA_HRS_HRS13_SHIFT (13U)
/*! HRS13 - Hardware Request Status Channel 13
* 0b0..A hardware service request for channel 13 is not present
* 0b1..A hardware service request for channel 13 is present
*/
#define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
#define DMA_HRS_HRS14_MASK (0x4000U)
#define DMA_HRS_HRS14_SHIFT (14U)
/*! HRS14 - Hardware Request Status Channel 14
* 0b0..A hardware service request for channel 14 is not present
* 0b1..A hardware service request for channel 14 is present
*/
#define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
#define DMA_HRS_HRS15_MASK (0x8000U)
#define DMA_HRS_HRS15_SHIFT (15U)
/*! HRS15 - Hardware Request Status Channel 15
* 0b0..A hardware service request for channel 15 is not present
* 0b1..A hardware service request for channel 15 is present
*/
#define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
#define DMA_HRS_HRS16_MASK (0x10000U)
#define DMA_HRS_HRS16_SHIFT (16U)
/*! HRS16 - Hardware Request Status Channel 16
* 0b0..A hardware service request for channel 16 is not present
* 0b1..A hardware service request for channel 16 is present
*/
#define DMA_HRS_HRS16(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS16_SHIFT)) & DMA_HRS_HRS16_MASK)
#define DMA_HRS_HRS17_MASK (0x20000U)
#define DMA_HRS_HRS17_SHIFT (17U)
/*! HRS17 - Hardware Request Status Channel 17
* 0b0..A hardware service request for channel 17 is not present
* 0b1..A hardware service request for channel 17 is present
*/
#define DMA_HRS_HRS17(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS17_SHIFT)) & DMA_HRS_HRS17_MASK)
#define DMA_HRS_HRS18_MASK (0x40000U)
#define DMA_HRS_HRS18_SHIFT (18U)
/*! HRS18 - Hardware Request Status Channel 18
* 0b0..A hardware service request for channel 18 is not present
* 0b1..A hardware service request for channel 18 is present
*/
#define DMA_HRS_HRS18(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS18_SHIFT)) & DMA_HRS_HRS18_MASK)
#define DMA_HRS_HRS19_MASK (0x80000U)
#define DMA_HRS_HRS19_SHIFT (19U)
/*! HRS19 - Hardware Request Status Channel 19
* 0b0..A hardware service request for channel 19 is not present
* 0b1..A hardware service request for channel 19 is present
*/
#define DMA_HRS_HRS19(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS19_SHIFT)) & DMA_HRS_HRS19_MASK)
#define DMA_HRS_HRS20_MASK (0x100000U)
#define DMA_HRS_HRS20_SHIFT (20U)
/*! HRS20 - Hardware Request Status Channel 20
* 0b0..A hardware service request for channel 20 is not present
* 0b1..A hardware service request for channel 20 is present
*/
#define DMA_HRS_HRS20(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS20_SHIFT)) & DMA_HRS_HRS20_MASK)
#define DMA_HRS_HRS21_MASK (0x200000U)
#define DMA_HRS_HRS21_SHIFT (21U)
/*! HRS21 - Hardware Request Status Channel 21
* 0b0..A hardware service request for channel 21 is not present
* 0b1..A hardware service request for channel 21 is present
*/
#define DMA_HRS_HRS21(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS21_SHIFT)) & DMA_HRS_HRS21_MASK)
#define DMA_HRS_HRS22_MASK (0x400000U)
#define DMA_HRS_HRS22_SHIFT (22U)
/*! HRS22 - Hardware Request Status Channel 22
* 0b0..A hardware service request for channel 22 is not present
* 0b1..A hardware service request for channel 22 is present
*/
#define DMA_HRS_HRS22(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS22_SHIFT)) & DMA_HRS_HRS22_MASK)
#define DMA_HRS_HRS23_MASK (0x800000U)
#define DMA_HRS_HRS23_SHIFT (23U)
/*! HRS23 - Hardware Request Status Channel 23
* 0b0..A hardware service request for channel 23 is not present
* 0b1..A hardware service request for channel 23 is present
*/
#define DMA_HRS_HRS23(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS23_SHIFT)) & DMA_HRS_HRS23_MASK)
#define DMA_HRS_HRS24_MASK (0x1000000U)
#define DMA_HRS_HRS24_SHIFT (24U)
/*! HRS24 - Hardware Request Status Channel 24
* 0b0..A hardware service request for channel 24 is not present
* 0b1..A hardware service request for channel 24 is present
*/
#define DMA_HRS_HRS24(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS24_SHIFT)) & DMA_HRS_HRS24_MASK)
#define DMA_HRS_HRS25_MASK (0x2000000U)
#define DMA_HRS_HRS25_SHIFT (25U)
/*! HRS25 - Hardware Request Status Channel 25
* 0b0..A hardware service request for channel 25 is not present
* 0b1..A hardware service request for channel 25 is present
*/
#define DMA_HRS_HRS25(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS25_SHIFT)) & DMA_HRS_HRS25_MASK)
#define DMA_HRS_HRS26_MASK (0x4000000U)
#define DMA_HRS_HRS26_SHIFT (26U)
/*! HRS26 - Hardware Request Status Channel 26
* 0b0..A hardware service request for channel 26 is not present
* 0b1..A hardware service request for channel 26 is present
*/
#define DMA_HRS_HRS26(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS26_SHIFT)) & DMA_HRS_HRS26_MASK)
#define DMA_HRS_HRS27_MASK (0x8000000U)
#define DMA_HRS_HRS27_SHIFT (27U)
/*! HRS27 - Hardware Request Status Channel 27
* 0b0..A hardware service request for channel 27 is not present
* 0b1..A hardware service request for channel 27 is present
*/
#define DMA_HRS_HRS27(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS27_SHIFT)) & DMA_HRS_HRS27_MASK)
#define DMA_HRS_HRS28_MASK (0x10000000U)
#define DMA_HRS_HRS28_SHIFT (28U)
/*! HRS28 - Hardware Request Status Channel 28
* 0b0..A hardware service request for channel 28 is not present
* 0b1..A hardware service request for channel 28 is present
*/
#define DMA_HRS_HRS28(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS28_SHIFT)) & DMA_HRS_HRS28_MASK)
#define DMA_HRS_HRS29_MASK (0x20000000U)
#define DMA_HRS_HRS29_SHIFT (29U)
/*! HRS29 - Hardware Request Status Channel 29
* 0b0..A hardware service request for channel 29 is not preset
* 0b1..A hardware service request for channel 29 is present
*/
#define DMA_HRS_HRS29(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS29_SHIFT)) & DMA_HRS_HRS29_MASK)
#define DMA_HRS_HRS30_MASK (0x40000000U)
#define DMA_HRS_HRS30_SHIFT (30U)
/*! HRS30 - Hardware Request Status Channel 30
* 0b0..A hardware service request for channel 30 is not present
* 0b1..A hardware service request for channel 30 is present
*/
#define DMA_HRS_HRS30(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS30_SHIFT)) & DMA_HRS_HRS30_MASK)
#define DMA_HRS_HRS31_MASK (0x80000000U)
#define DMA_HRS_HRS31_SHIFT (31U)
/*! HRS31 - Hardware Request Status Channel 31
* 0b0..A hardware service request for channel 31 is not present
* 0b1..A hardware service request for channel 31 is present
*/
#define DMA_HRS_HRS31(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS31_SHIFT)) & DMA_HRS_HRS31_MASK)
/*! @} */
/*! @name EARS - Enable Asynchronous Request in Stop */
/*! @{ */
#define DMA_EARS_EDREQ_0_MASK (0x1U)
#define DMA_EARS_EDREQ_0_SHIFT (0U)
/*! EDREQ_0 - Enable asynchronous DMA request in stop mode for channel 0.
* 0b0..Disable asynchronous DMA request for channel 0
* 0b1..Enable asynchronous DMA request for channel 0
*/
#define DMA_EARS_EDREQ_0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_0_SHIFT)) & DMA_EARS_EDREQ_0_MASK)
#define DMA_EARS_EDREQ_1_MASK (0x2U)
#define DMA_EARS_EDREQ_1_SHIFT (1U)
/*! EDREQ_1 - Enable asynchronous DMA request in stop mode for channel 1.
* 0b0..Disable asynchronous DMA request for channel 1
* 0b1..Enable asynchronous DMA request for channel 1
*/
#define DMA_EARS_EDREQ_1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_1_SHIFT)) & DMA_EARS_EDREQ_1_MASK)
#define DMA_EARS_EDREQ_2_MASK (0x4U)
#define DMA_EARS_EDREQ_2_SHIFT (2U)
/*! EDREQ_2 - Enable asynchronous DMA request in stop mode for channel 2.
* 0b0..Disable asynchronous DMA request for channel 2
* 0b1..Enable asynchronous DMA request for channel 2
*/
#define DMA_EARS_EDREQ_2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_2_SHIFT)) & DMA_EARS_EDREQ_2_MASK)
#define DMA_EARS_EDREQ_3_MASK (0x8U)
#define DMA_EARS_EDREQ_3_SHIFT (3U)
/*! EDREQ_3 - Enable asynchronous DMA request in stop mode for channel 3.
* 0b0..Disable asynchronous DMA request for channel 3
* 0b1..Enable asynchronous DMA request for channel 3
*/
#define DMA_EARS_EDREQ_3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_3_SHIFT)) & DMA_EARS_EDREQ_3_MASK)
#define DMA_EARS_EDREQ_4_MASK (0x10U)
#define DMA_EARS_EDREQ_4_SHIFT (4U)
/*! EDREQ_4 - Enable asynchronous DMA request in stop mode for channel 4.
* 0b0..Disable asynchronous DMA request for channel 4
* 0b1..Enable asynchronous DMA request for channel 4
*/
#define DMA_EARS_EDREQ_4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_4_SHIFT)) & DMA_EARS_EDREQ_4_MASK)
#define DMA_EARS_EDREQ_5_MASK (0x20U)
#define DMA_EARS_EDREQ_5_SHIFT (5U)
/*! EDREQ_5 - Enable asynchronous DMA request in stop mode for channel 5.
* 0b0..Disable asynchronous DMA request for channel 5
* 0b1..Enable asynchronous DMA request for channel 5
*/
#define DMA_EARS_EDREQ_5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_5_SHIFT)) & DMA_EARS_EDREQ_5_MASK)
#define DMA_EARS_EDREQ_6_MASK (0x40U)
#define DMA_EARS_EDREQ_6_SHIFT (6U)
/*! EDREQ_6 - Enable asynchronous DMA request in stop mode for channel 6.
* 0b0..Disable asynchronous DMA request for channel 6
* 0b1..Enable asynchronous DMA request for channel 6
*/
#define DMA_EARS_EDREQ_6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_6_SHIFT)) & DMA_EARS_EDREQ_6_MASK)
#define DMA_EARS_EDREQ_7_MASK (0x80U)
#define DMA_EARS_EDREQ_7_SHIFT (7U)
/*! EDREQ_7 - Enable asynchronous DMA request in stop mode for channel 7.
* 0b0..Disable asynchronous DMA request for channel 7
* 0b1..Enable asynchronous DMA request for channel 7
*/
#define DMA_EARS_EDREQ_7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_7_SHIFT)) & DMA_EARS_EDREQ_7_MASK)
#define DMA_EARS_EDREQ_8_MASK (0x100U)
#define DMA_EARS_EDREQ_8_SHIFT (8U)
/*! EDREQ_8 - Enable asynchronous DMA request in stop mode for channel 8.
* 0b0..Disable asynchronous DMA request for channel 8
* 0b1..Enable asynchronous DMA request for channel 8
*/
#define DMA_EARS_EDREQ_8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_8_SHIFT)) & DMA_EARS_EDREQ_8_MASK)
#define DMA_EARS_EDREQ_9_MASK (0x200U)
#define DMA_EARS_EDREQ_9_SHIFT (9U)
/*! EDREQ_9 - Enable asynchronous DMA request in stop mode for channel 9.
* 0b0..Disable asynchronous DMA request for channel 9
* 0b1..Enable asynchronous DMA request for channel 9
*/
#define DMA_EARS_EDREQ_9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_9_SHIFT)) & DMA_EARS_EDREQ_9_MASK)
#define DMA_EARS_EDREQ_10_MASK (0x400U)
#define DMA_EARS_EDREQ_10_SHIFT (10U)
/*! EDREQ_10 - Enable asynchronous DMA request in stop mode for channel 10.
* 0b0..Disable asynchronous DMA request for channel 10
* 0b1..Enable asynchronous DMA request for channel 10
*/
#define DMA_EARS_EDREQ_10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_10_SHIFT)) & DMA_EARS_EDREQ_10_MASK)
#define DMA_EARS_EDREQ_11_MASK (0x800U)
#define DMA_EARS_EDREQ_11_SHIFT (11U)
/*! EDREQ_11 - Enable asynchronous DMA request in stop mode for channel 11.
* 0b0..Disable asynchronous DMA request for channel 11
* 0b1..Enable asynchronous DMA request for channel 11
*/
#define DMA_EARS_EDREQ_11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_11_SHIFT)) & DMA_EARS_EDREQ_11_MASK)
#define DMA_EARS_EDREQ_12_MASK (0x1000U)
#define DMA_EARS_EDREQ_12_SHIFT (12U)
/*! EDREQ_12 - Enable asynchronous DMA request in stop mode for channel 12.
* 0b0..Disable asynchronous DMA request for channel 12
* 0b1..Enable asynchronous DMA request for channel 12
*/
#define DMA_EARS_EDREQ_12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_12_SHIFT)) & DMA_EARS_EDREQ_12_MASK)
#define DMA_EARS_EDREQ_13_MASK (0x2000U)
#define DMA_EARS_EDREQ_13_SHIFT (13U)
/*! EDREQ_13 - Enable asynchronous DMA request in stop mode for channel 13.
* 0b0..Disable asynchronous DMA request for channel 13
* 0b1..Enable asynchronous DMA request for channel 13
*/
#define DMA_EARS_EDREQ_13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_13_SHIFT)) & DMA_EARS_EDREQ_13_MASK)
#define DMA_EARS_EDREQ_14_MASK (0x4000U)
#define DMA_EARS_EDREQ_14_SHIFT (14U)
/*! EDREQ_14 - Enable asynchronous DMA request in stop mode for channel 14.
* 0b0..Disable asynchronous DMA request for channel 14
* 0b1..Enable asynchronous DMA request for channel 14
*/
#define DMA_EARS_EDREQ_14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_14_SHIFT)) & DMA_EARS_EDREQ_14_MASK)
#define DMA_EARS_EDREQ_15_MASK (0x8000U)
#define DMA_EARS_EDREQ_15_SHIFT (15U)
/*! EDREQ_15 - Enable asynchronous DMA request in stop mode for channel 15.
* 0b0..Disable asynchronous DMA request for channel 15
* 0b1..Enable asynchronous DMA request for channel 15
*/
#define DMA_EARS_EDREQ_15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_15_SHIFT)) & DMA_EARS_EDREQ_15_MASK)
#define DMA_EARS_EDREQ_16_MASK (0x10000U)
#define DMA_EARS_EDREQ_16_SHIFT (16U)
/*! EDREQ_16 - Enable asynchronous DMA request in stop mode for channel 16.
* 0b0..Disable asynchronous DMA request for channel 16
* 0b1..Enable asynchronous DMA request for channel 16
*/
#define DMA_EARS_EDREQ_16(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_16_SHIFT)) & DMA_EARS_EDREQ_16_MASK)
#define DMA_EARS_EDREQ_17_MASK (0x20000U)
#define DMA_EARS_EDREQ_17_SHIFT (17U)
/*! EDREQ_17 - Enable asynchronous DMA request in stop mode for channel 17.
* 0b0..Disable asynchronous DMA request for channel 17
* 0b1..Enable asynchronous DMA request for channel 17
*/
#define DMA_EARS_EDREQ_17(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_17_SHIFT)) & DMA_EARS_EDREQ_17_MASK)
#define DMA_EARS_EDREQ_18_MASK (0x40000U)
#define DMA_EARS_EDREQ_18_SHIFT (18U)
/*! EDREQ_18 - Enable asynchronous DMA request in stop mode for channel 18.
* 0b0..Disable asynchronous DMA request for channel 18
* 0b1..Enable asynchronous DMA request for channel 18
*/
#define DMA_EARS_EDREQ_18(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_18_SHIFT)) & DMA_EARS_EDREQ_18_MASK)
#define DMA_EARS_EDREQ_19_MASK (0x80000U)
#define DMA_EARS_EDREQ_19_SHIFT (19U)
/*! EDREQ_19 - Enable asynchronous DMA request in stop mode for channel 19.
* 0b0..Disable asynchronous DMA request for channel 19
* 0b1..Enable asynchronous DMA request for channel 19
*/
#define DMA_EARS_EDREQ_19(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_19_SHIFT)) & DMA_EARS_EDREQ_19_MASK)
#define DMA_EARS_EDREQ_20_MASK (0x100000U)
#define DMA_EARS_EDREQ_20_SHIFT (20U)
/*! EDREQ_20 - Enable asynchronous DMA request in stop mode for channel 20.
* 0b0..Disable asynchronous DMA request for channel 20
* 0b1..Enable asynchronous DMA request for channel 20
*/
#define DMA_EARS_EDREQ_20(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_20_SHIFT)) & DMA_EARS_EDREQ_20_MASK)
#define DMA_EARS_EDREQ_21_MASK (0x200000U)
#define DMA_EARS_EDREQ_21_SHIFT (21U)
/*! EDREQ_21 - Enable asynchronous DMA request in stop mode for channel 21.
* 0b0..Disable asynchronous DMA request for channel 21
* 0b1..Enable asynchronous DMA request for channel 21
*/
#define DMA_EARS_EDREQ_21(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_21_SHIFT)) & DMA_EARS_EDREQ_21_MASK)
#define DMA_EARS_EDREQ_22_MASK (0x400000U)
#define DMA_EARS_EDREQ_22_SHIFT (22U)
/*! EDREQ_22 - Enable asynchronous DMA request in stop mode for channel 22.
* 0b0..Disable asynchronous DMA request for channel 22
* 0b1..Enable asynchronous DMA request for channel 22
*/
#define DMA_EARS_EDREQ_22(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_22_SHIFT)) & DMA_EARS_EDREQ_22_MASK)
#define DMA_EARS_EDREQ_23_MASK (0x800000U)
#define DMA_EARS_EDREQ_23_SHIFT (23U)
/*! EDREQ_23 - Enable asynchronous DMA request in stop mode for channel 23.
* 0b0..Disable asynchronous DMA request for channel 23
* 0b1..Enable asynchronous DMA request for channel 23
*/
#define DMA_EARS_EDREQ_23(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_23_SHIFT)) & DMA_EARS_EDREQ_23_MASK)
#define DMA_EARS_EDREQ_24_MASK (0x1000000U)
#define DMA_EARS_EDREQ_24_SHIFT (24U)
/*! EDREQ_24 - Enable asynchronous DMA request in stop mode for channel 24.
* 0b0..Disable asynchronous DMA request for channel 24
* 0b1..Enable asynchronous DMA request for channel 24
*/
#define DMA_EARS_EDREQ_24(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_24_SHIFT)) & DMA_EARS_EDREQ_24_MASK)
#define DMA_EARS_EDREQ_25_MASK (0x2000000U)
#define DMA_EARS_EDREQ_25_SHIFT (25U)
/*! EDREQ_25 - Enable asynchronous DMA request in stop mode for channel 25.
* 0b0..Disable asynchronous DMA request for channel 25
* 0b1..Enable asynchronous DMA request for channel 25
*/
#define DMA_EARS_EDREQ_25(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_25_SHIFT)) & DMA_EARS_EDREQ_25_MASK)
#define DMA_EARS_EDREQ_26_MASK (0x4000000U)
#define DMA_EARS_EDREQ_26_SHIFT (26U)
/*! EDREQ_26 - Enable asynchronous DMA request in stop mode for channel 26.
* 0b0..Disable asynchronous DMA request for channel 26
* 0b1..Enable asynchronous DMA request for channel 26
*/
#define DMA_EARS_EDREQ_26(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_26_SHIFT)) & DMA_EARS_EDREQ_26_MASK)
#define DMA_EARS_EDREQ_27_MASK (0x8000000U)
#define DMA_EARS_EDREQ_27_SHIFT (27U)
/*! EDREQ_27 - Enable asynchronous DMA request in stop mode for channel 27.
* 0b0..Disable asynchronous DMA request for channel 27
* 0b1..Enable asynchronous DMA request for channel 27
*/
#define DMA_EARS_EDREQ_27(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_27_SHIFT)) & DMA_EARS_EDREQ_27_MASK)
#define DMA_EARS_EDREQ_28_MASK (0x10000000U)
#define DMA_EARS_EDREQ_28_SHIFT (28U)
/*! EDREQ_28 - Enable asynchronous DMA request in stop mode for channel 28.
* 0b0..Disable asynchronous DMA request for channel 28
* 0b1..Enable asynchronous DMA request for channel 28
*/
#define DMA_EARS_EDREQ_28(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_28_SHIFT)) & DMA_EARS_EDREQ_28_MASK)
#define DMA_EARS_EDREQ_29_MASK (0x20000000U)
#define DMA_EARS_EDREQ_29_SHIFT (29U)
/*! EDREQ_29 - Enable asynchronous DMA request in stop mode for channel 29.
* 0b0..Disable asynchronous DMA request for channel 29
* 0b1..Enable asynchronous DMA request for channel 29
*/
#define DMA_EARS_EDREQ_29(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_29_SHIFT)) & DMA_EARS_EDREQ_29_MASK)
#define DMA_EARS_EDREQ_30_MASK (0x40000000U)
#define DMA_EARS_EDREQ_30_SHIFT (30U)
/*! EDREQ_30 - Enable asynchronous DMA request in stop mode for channel 30.
* 0b0..Disable asynchronous DMA request for channel 30
* 0b1..Enable asynchronous DMA request for channel 30
*/
#define DMA_EARS_EDREQ_30(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_30_SHIFT)) & DMA_EARS_EDREQ_30_MASK)
#define DMA_EARS_EDREQ_31_MASK (0x80000000U)
#define DMA_EARS_EDREQ_31_SHIFT (31U)
/*! EDREQ_31 - Enable asynchronous DMA request in stop mode for channel 31.
* 0b0..Disable asynchronous DMA request for channel 31
* 0b1..Enable asynchronous DMA request for channel 31
*/
#define DMA_EARS_EDREQ_31(x) (((uint32_t)(((uint32_t)(x)) << DMA_EARS_EDREQ_31_SHIFT)) & DMA_EARS_EDREQ_31_MASK)
/*! @} */
/*! @name DCHPRI3 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI3_CHPRI_MASK (0xFU)
#define DMA_DCHPRI3_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
#define DMA_DCHPRI3_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI3_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI3_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_GRPPRI_SHIFT)) & DMA_DCHPRI3_GRPPRI_MASK)
#define DMA_DCHPRI3_DPA_MASK (0x40U)
#define DMA_DCHPRI3_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
#define DMA_DCHPRI3_ECP_MASK (0x80U)
#define DMA_DCHPRI3_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
/*! @} */
/*! @name DCHPRI2 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI2_CHPRI_MASK (0xFU)
#define DMA_DCHPRI2_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
#define DMA_DCHPRI2_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI2_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI2_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_GRPPRI_SHIFT)) & DMA_DCHPRI2_GRPPRI_MASK)
#define DMA_DCHPRI2_DPA_MASK (0x40U)
#define DMA_DCHPRI2_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
#define DMA_DCHPRI2_ECP_MASK (0x80U)
#define DMA_DCHPRI2_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
/*! @} */
/*! @name DCHPRI1 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI1_CHPRI_MASK (0xFU)
#define DMA_DCHPRI1_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
#define DMA_DCHPRI1_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI1_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI1_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_GRPPRI_SHIFT)) & DMA_DCHPRI1_GRPPRI_MASK)
#define DMA_DCHPRI1_DPA_MASK (0x40U)
#define DMA_DCHPRI1_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
#define DMA_DCHPRI1_ECP_MASK (0x80U)
#define DMA_DCHPRI1_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
/*! @} */
/*! @name DCHPRI0 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI0_CHPRI_MASK (0xFU)
#define DMA_DCHPRI0_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
#define DMA_DCHPRI0_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI0_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI0_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_GRPPRI_SHIFT)) & DMA_DCHPRI0_GRPPRI_MASK)
#define DMA_DCHPRI0_DPA_MASK (0x40U)
#define DMA_DCHPRI0_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
#define DMA_DCHPRI0_ECP_MASK (0x80U)
#define DMA_DCHPRI0_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
/*! @} */
/*! @name DCHPRI7 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI7_CHPRI_MASK (0xFU)
#define DMA_DCHPRI7_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
#define DMA_DCHPRI7_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI7_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI7_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_GRPPRI_SHIFT)) & DMA_DCHPRI7_GRPPRI_MASK)
#define DMA_DCHPRI7_DPA_MASK (0x40U)
#define DMA_DCHPRI7_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
#define DMA_DCHPRI7_ECP_MASK (0x80U)
#define DMA_DCHPRI7_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
/*! @} */
/*! @name DCHPRI6 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI6_CHPRI_MASK (0xFU)
#define DMA_DCHPRI6_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
#define DMA_DCHPRI6_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI6_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI6_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_GRPPRI_SHIFT)) & DMA_DCHPRI6_GRPPRI_MASK)
#define DMA_DCHPRI6_DPA_MASK (0x40U)
#define DMA_DCHPRI6_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
#define DMA_DCHPRI6_ECP_MASK (0x80U)
#define DMA_DCHPRI6_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
/*! @} */
/*! @name DCHPRI5 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI5_CHPRI_MASK (0xFU)
#define DMA_DCHPRI5_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
#define DMA_DCHPRI5_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI5_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI5_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_GRPPRI_SHIFT)) & DMA_DCHPRI5_GRPPRI_MASK)
#define DMA_DCHPRI5_DPA_MASK (0x40U)
#define DMA_DCHPRI5_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
#define DMA_DCHPRI5_ECP_MASK (0x80U)
#define DMA_DCHPRI5_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
/*! @} */
/*! @name DCHPRI4 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI4_CHPRI_MASK (0xFU)
#define DMA_DCHPRI4_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
#define DMA_DCHPRI4_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI4_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI4_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_GRPPRI_SHIFT)) & DMA_DCHPRI4_GRPPRI_MASK)
#define DMA_DCHPRI4_DPA_MASK (0x40U)
#define DMA_DCHPRI4_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
#define DMA_DCHPRI4_ECP_MASK (0x80U)
#define DMA_DCHPRI4_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
/*! @} */
/*! @name DCHPRI11 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI11_CHPRI_MASK (0xFU)
#define DMA_DCHPRI11_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
#define DMA_DCHPRI11_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI11_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI11_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_GRPPRI_SHIFT)) & DMA_DCHPRI11_GRPPRI_MASK)
#define DMA_DCHPRI11_DPA_MASK (0x40U)
#define DMA_DCHPRI11_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
#define DMA_DCHPRI11_ECP_MASK (0x80U)
#define DMA_DCHPRI11_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
/*! @} */
/*! @name DCHPRI10 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI10_CHPRI_MASK (0xFU)
#define DMA_DCHPRI10_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
#define DMA_DCHPRI10_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI10_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI10_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_GRPPRI_SHIFT)) & DMA_DCHPRI10_GRPPRI_MASK)
#define DMA_DCHPRI10_DPA_MASK (0x40U)
#define DMA_DCHPRI10_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
#define DMA_DCHPRI10_ECP_MASK (0x80U)
#define DMA_DCHPRI10_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
/*! @} */
/*! @name DCHPRI9 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI9_CHPRI_MASK (0xFU)
#define DMA_DCHPRI9_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
#define DMA_DCHPRI9_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI9_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI9_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_GRPPRI_SHIFT)) & DMA_DCHPRI9_GRPPRI_MASK)
#define DMA_DCHPRI9_DPA_MASK (0x40U)
#define DMA_DCHPRI9_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
#define DMA_DCHPRI9_ECP_MASK (0x80U)
#define DMA_DCHPRI9_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
/*! @} */
/*! @name DCHPRI8 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI8_CHPRI_MASK (0xFU)
#define DMA_DCHPRI8_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
#define DMA_DCHPRI8_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI8_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI8_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_GRPPRI_SHIFT)) & DMA_DCHPRI8_GRPPRI_MASK)
#define DMA_DCHPRI8_DPA_MASK (0x40U)
#define DMA_DCHPRI8_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
#define DMA_DCHPRI8_ECP_MASK (0x80U)
#define DMA_DCHPRI8_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
/*! @} */
/*! @name DCHPRI15 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI15_CHPRI_MASK (0xFU)
#define DMA_DCHPRI15_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
#define DMA_DCHPRI15_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI15_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI15_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_GRPPRI_SHIFT)) & DMA_DCHPRI15_GRPPRI_MASK)
#define DMA_DCHPRI15_DPA_MASK (0x40U)
#define DMA_DCHPRI15_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
#define DMA_DCHPRI15_ECP_MASK (0x80U)
#define DMA_DCHPRI15_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
/*! @} */
/*! @name DCHPRI14 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI14_CHPRI_MASK (0xFU)
#define DMA_DCHPRI14_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
#define DMA_DCHPRI14_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI14_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI14_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_GRPPRI_SHIFT)) & DMA_DCHPRI14_GRPPRI_MASK)
#define DMA_DCHPRI14_DPA_MASK (0x40U)
#define DMA_DCHPRI14_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
#define DMA_DCHPRI14_ECP_MASK (0x80U)
#define DMA_DCHPRI14_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
/*! @} */
/*! @name DCHPRI13 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI13_CHPRI_MASK (0xFU)
#define DMA_DCHPRI13_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
#define DMA_DCHPRI13_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI13_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI13_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_GRPPRI_SHIFT)) & DMA_DCHPRI13_GRPPRI_MASK)
#define DMA_DCHPRI13_DPA_MASK (0x40U)
#define DMA_DCHPRI13_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
#define DMA_DCHPRI13_ECP_MASK (0x80U)
#define DMA_DCHPRI13_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
/*! @} */
/*! @name DCHPRI12 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI12_CHPRI_MASK (0xFU)
#define DMA_DCHPRI12_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
#define DMA_DCHPRI12_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI12_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI12_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_GRPPRI_SHIFT)) & DMA_DCHPRI12_GRPPRI_MASK)
#define DMA_DCHPRI12_DPA_MASK (0x40U)
#define DMA_DCHPRI12_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
#define DMA_DCHPRI12_ECP_MASK (0x80U)
#define DMA_DCHPRI12_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
/*! @} */
/*! @name DCHPRI19 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI19_CHPRI_MASK (0xFU)
#define DMA_DCHPRI19_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI19_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_CHPRI_SHIFT)) & DMA_DCHPRI19_CHPRI_MASK)
#define DMA_DCHPRI19_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI19_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI19_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_GRPPRI_SHIFT)) & DMA_DCHPRI19_GRPPRI_MASK)
#define DMA_DCHPRI19_DPA_MASK (0x40U)
#define DMA_DCHPRI19_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI19_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_DPA_SHIFT)) & DMA_DCHPRI19_DPA_MASK)
#define DMA_DCHPRI19_ECP_MASK (0x80U)
#define DMA_DCHPRI19_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI19_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI19_ECP_SHIFT)) & DMA_DCHPRI19_ECP_MASK)
/*! @} */
/*! @name DCHPRI18 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI18_CHPRI_MASK (0xFU)
#define DMA_DCHPRI18_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI18_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_CHPRI_SHIFT)) & DMA_DCHPRI18_CHPRI_MASK)
#define DMA_DCHPRI18_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI18_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI18_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_GRPPRI_SHIFT)) & DMA_DCHPRI18_GRPPRI_MASK)
#define DMA_DCHPRI18_DPA_MASK (0x40U)
#define DMA_DCHPRI18_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI18_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_DPA_SHIFT)) & DMA_DCHPRI18_DPA_MASK)
#define DMA_DCHPRI18_ECP_MASK (0x80U)
#define DMA_DCHPRI18_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI18_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI18_ECP_SHIFT)) & DMA_DCHPRI18_ECP_MASK)
/*! @} */
/*! @name DCHPRI17 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI17_CHPRI_MASK (0xFU)
#define DMA_DCHPRI17_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI17_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_CHPRI_SHIFT)) & DMA_DCHPRI17_CHPRI_MASK)
#define DMA_DCHPRI17_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI17_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI17_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_GRPPRI_SHIFT)) & DMA_DCHPRI17_GRPPRI_MASK)
#define DMA_DCHPRI17_DPA_MASK (0x40U)
#define DMA_DCHPRI17_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI17_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_DPA_SHIFT)) & DMA_DCHPRI17_DPA_MASK)
#define DMA_DCHPRI17_ECP_MASK (0x80U)
#define DMA_DCHPRI17_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI17_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI17_ECP_SHIFT)) & DMA_DCHPRI17_ECP_MASK)
/*! @} */
/*! @name DCHPRI16 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI16_CHPRI_MASK (0xFU)
#define DMA_DCHPRI16_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI16_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_CHPRI_SHIFT)) & DMA_DCHPRI16_CHPRI_MASK)
#define DMA_DCHPRI16_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI16_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI16_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_GRPPRI_SHIFT)) & DMA_DCHPRI16_GRPPRI_MASK)
#define DMA_DCHPRI16_DPA_MASK (0x40U)
#define DMA_DCHPRI16_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI16_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_DPA_SHIFT)) & DMA_DCHPRI16_DPA_MASK)
#define DMA_DCHPRI16_ECP_MASK (0x80U)
#define DMA_DCHPRI16_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI16_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI16_ECP_SHIFT)) & DMA_DCHPRI16_ECP_MASK)
/*! @} */
/*! @name DCHPRI23 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI23_CHPRI_MASK (0xFU)
#define DMA_DCHPRI23_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI23_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_CHPRI_SHIFT)) & DMA_DCHPRI23_CHPRI_MASK)
#define DMA_DCHPRI23_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI23_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI23_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_GRPPRI_SHIFT)) & DMA_DCHPRI23_GRPPRI_MASK)
#define DMA_DCHPRI23_DPA_MASK (0x40U)
#define DMA_DCHPRI23_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI23_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_DPA_SHIFT)) & DMA_DCHPRI23_DPA_MASK)
#define DMA_DCHPRI23_ECP_MASK (0x80U)
#define DMA_DCHPRI23_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI23_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI23_ECP_SHIFT)) & DMA_DCHPRI23_ECP_MASK)
/*! @} */
/*! @name DCHPRI22 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI22_CHPRI_MASK (0xFU)
#define DMA_DCHPRI22_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI22_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_CHPRI_SHIFT)) & DMA_DCHPRI22_CHPRI_MASK)
#define DMA_DCHPRI22_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI22_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI22_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_GRPPRI_SHIFT)) & DMA_DCHPRI22_GRPPRI_MASK)
#define DMA_DCHPRI22_DPA_MASK (0x40U)
#define DMA_DCHPRI22_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI22_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_DPA_SHIFT)) & DMA_DCHPRI22_DPA_MASK)
#define DMA_DCHPRI22_ECP_MASK (0x80U)
#define DMA_DCHPRI22_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI22_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI22_ECP_SHIFT)) & DMA_DCHPRI22_ECP_MASK)
/*! @} */
/*! @name DCHPRI21 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI21_CHPRI_MASK (0xFU)
#define DMA_DCHPRI21_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI21_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_CHPRI_SHIFT)) & DMA_DCHPRI21_CHPRI_MASK)
#define DMA_DCHPRI21_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI21_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI21_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_GRPPRI_SHIFT)) & DMA_DCHPRI21_GRPPRI_MASK)
#define DMA_DCHPRI21_DPA_MASK (0x40U)
#define DMA_DCHPRI21_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI21_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_DPA_SHIFT)) & DMA_DCHPRI21_DPA_MASK)
#define DMA_DCHPRI21_ECP_MASK (0x80U)
#define DMA_DCHPRI21_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI21_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI21_ECP_SHIFT)) & DMA_DCHPRI21_ECP_MASK)
/*! @} */
/*! @name DCHPRI20 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI20_CHPRI_MASK (0xFU)
#define DMA_DCHPRI20_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI20_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_CHPRI_SHIFT)) & DMA_DCHPRI20_CHPRI_MASK)
#define DMA_DCHPRI20_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI20_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI20_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_GRPPRI_SHIFT)) & DMA_DCHPRI20_GRPPRI_MASK)
#define DMA_DCHPRI20_DPA_MASK (0x40U)
#define DMA_DCHPRI20_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI20_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_DPA_SHIFT)) & DMA_DCHPRI20_DPA_MASK)
#define DMA_DCHPRI20_ECP_MASK (0x80U)
#define DMA_DCHPRI20_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI20_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI20_ECP_SHIFT)) & DMA_DCHPRI20_ECP_MASK)
/*! @} */
/*! @name DCHPRI27 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI27_CHPRI_MASK (0xFU)
#define DMA_DCHPRI27_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI27_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_CHPRI_SHIFT)) & DMA_DCHPRI27_CHPRI_MASK)
#define DMA_DCHPRI27_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI27_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI27_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_GRPPRI_SHIFT)) & DMA_DCHPRI27_GRPPRI_MASK)
#define DMA_DCHPRI27_DPA_MASK (0x40U)
#define DMA_DCHPRI27_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI27_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_DPA_SHIFT)) & DMA_DCHPRI27_DPA_MASK)
#define DMA_DCHPRI27_ECP_MASK (0x80U)
#define DMA_DCHPRI27_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI27_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI27_ECP_SHIFT)) & DMA_DCHPRI27_ECP_MASK)
/*! @} */
/*! @name DCHPRI26 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI26_CHPRI_MASK (0xFU)
#define DMA_DCHPRI26_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI26_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_CHPRI_SHIFT)) & DMA_DCHPRI26_CHPRI_MASK)
#define DMA_DCHPRI26_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI26_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI26_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_GRPPRI_SHIFT)) & DMA_DCHPRI26_GRPPRI_MASK)
#define DMA_DCHPRI26_DPA_MASK (0x40U)
#define DMA_DCHPRI26_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI26_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_DPA_SHIFT)) & DMA_DCHPRI26_DPA_MASK)
#define DMA_DCHPRI26_ECP_MASK (0x80U)
#define DMA_DCHPRI26_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI26_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI26_ECP_SHIFT)) & DMA_DCHPRI26_ECP_MASK)
/*! @} */
/*! @name DCHPRI25 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI25_CHPRI_MASK (0xFU)
#define DMA_DCHPRI25_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI25_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_CHPRI_SHIFT)) & DMA_DCHPRI25_CHPRI_MASK)
#define DMA_DCHPRI25_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI25_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI25_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_GRPPRI_SHIFT)) & DMA_DCHPRI25_GRPPRI_MASK)
#define DMA_DCHPRI25_DPA_MASK (0x40U)
#define DMA_DCHPRI25_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI25_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_DPA_SHIFT)) & DMA_DCHPRI25_DPA_MASK)
#define DMA_DCHPRI25_ECP_MASK (0x80U)
#define DMA_DCHPRI25_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI25_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI25_ECP_SHIFT)) & DMA_DCHPRI25_ECP_MASK)
/*! @} */
/*! @name DCHPRI24 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI24_CHPRI_MASK (0xFU)
#define DMA_DCHPRI24_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI24_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_CHPRI_SHIFT)) & DMA_DCHPRI24_CHPRI_MASK)
#define DMA_DCHPRI24_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI24_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI24_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_GRPPRI_SHIFT)) & DMA_DCHPRI24_GRPPRI_MASK)
#define DMA_DCHPRI24_DPA_MASK (0x40U)
#define DMA_DCHPRI24_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI24_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_DPA_SHIFT)) & DMA_DCHPRI24_DPA_MASK)
#define DMA_DCHPRI24_ECP_MASK (0x80U)
#define DMA_DCHPRI24_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI24_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI24_ECP_SHIFT)) & DMA_DCHPRI24_ECP_MASK)
/*! @} */
/*! @name DCHPRI31 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI31_CHPRI_MASK (0xFU)
#define DMA_DCHPRI31_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI31_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_CHPRI_SHIFT)) & DMA_DCHPRI31_CHPRI_MASK)
#define DMA_DCHPRI31_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI31_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI31_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_GRPPRI_SHIFT)) & DMA_DCHPRI31_GRPPRI_MASK)
#define DMA_DCHPRI31_DPA_MASK (0x40U)
#define DMA_DCHPRI31_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI31_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_DPA_SHIFT)) & DMA_DCHPRI31_DPA_MASK)
#define DMA_DCHPRI31_ECP_MASK (0x80U)
#define DMA_DCHPRI31_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI31_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI31_ECP_SHIFT)) & DMA_DCHPRI31_ECP_MASK)
/*! @} */
/*! @name DCHPRI30 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI30_CHPRI_MASK (0xFU)
#define DMA_DCHPRI30_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI30_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_CHPRI_SHIFT)) & DMA_DCHPRI30_CHPRI_MASK)
#define DMA_DCHPRI30_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI30_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI30_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_GRPPRI_SHIFT)) & DMA_DCHPRI30_GRPPRI_MASK)
#define DMA_DCHPRI30_DPA_MASK (0x40U)
#define DMA_DCHPRI30_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI30_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_DPA_SHIFT)) & DMA_DCHPRI30_DPA_MASK)
#define DMA_DCHPRI30_ECP_MASK (0x80U)
#define DMA_DCHPRI30_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI30_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI30_ECP_SHIFT)) & DMA_DCHPRI30_ECP_MASK)
/*! @} */
/*! @name DCHPRI29 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI29_CHPRI_MASK (0xFU)
#define DMA_DCHPRI29_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI29_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_CHPRI_SHIFT)) & DMA_DCHPRI29_CHPRI_MASK)
#define DMA_DCHPRI29_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI29_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI29_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_GRPPRI_SHIFT)) & DMA_DCHPRI29_GRPPRI_MASK)
#define DMA_DCHPRI29_DPA_MASK (0x40U)
#define DMA_DCHPRI29_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI29_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_DPA_SHIFT)) & DMA_DCHPRI29_DPA_MASK)
#define DMA_DCHPRI29_ECP_MASK (0x80U)
#define DMA_DCHPRI29_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI29_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI29_ECP_SHIFT)) & DMA_DCHPRI29_ECP_MASK)
/*! @} */
/*! @name DCHPRI28 - Channel Priority */
/*! @{ */
#define DMA_DCHPRI28_CHPRI_MASK (0xFU)
#define DMA_DCHPRI28_CHPRI_SHIFT (0U)
/*! CHPRI - Channel n Arbitration Priority
*/
#define DMA_DCHPRI28_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_CHPRI_SHIFT)) & DMA_DCHPRI28_CHPRI_MASK)
#define DMA_DCHPRI28_GRPPRI_MASK (0x30U)
#define DMA_DCHPRI28_GRPPRI_SHIFT (4U)
/*! GRPPRI - Channel n Current Group Priority
*/
#define DMA_DCHPRI28_GRPPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_GRPPRI_SHIFT)) & DMA_DCHPRI28_GRPPRI_MASK)
#define DMA_DCHPRI28_DPA_MASK (0x40U)
#define DMA_DCHPRI28_DPA_SHIFT (6U)
/*! DPA - Disable Preempt Ability. This field resets to 0.
* 0b0..Channel n can suspend a lower priority channel
* 0b1..Channel n cannot suspend any channel, regardless of channel priority
*/
#define DMA_DCHPRI28_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_DPA_SHIFT)) & DMA_DCHPRI28_DPA_MASK)
#define DMA_DCHPRI28_ECP_MASK (0x80U)
#define DMA_DCHPRI28_ECP_SHIFT (7U)
/*! ECP - Enable Channel Preemption. This field resets to 0.
* 0b0..Channel n cannot be suspended by a higher priority channel's service request
* 0b1..Channel n can be temporarily suspended by the service request of a higher priority channel
*/
#define DMA_DCHPRI28_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI28_ECP_SHIFT)) & DMA_DCHPRI28_ECP_MASK)
/*! @} */
/*! @name SADDR - TCD Source Address */
/*! @{ */
#define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
#define DMA_SADDR_SADDR_SHIFT (0U)
/*! SADDR - Source Address
*/
#define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
/*! @} */
/* The count of DMA_SADDR */
#define DMA_SADDR_COUNT (32U)
/*! @name SOFF - TCD Signed Source Address Offset */
/*! @{ */
#define DMA_SOFF_SOFF_MASK (0xFFFFU)
#define DMA_SOFF_SOFF_SHIFT (0U)
/*! SOFF - Source address signed offset
*/
#define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
/*! @} */
/* The count of DMA_SOFF */
#define DMA_SOFF_COUNT (32U)
/*! @name ATTR - TCD Transfer Attributes */
/*! @{ */
#define DMA_ATTR_DSIZE_MASK (0x7U)
#define DMA_ATTR_DSIZE_SHIFT (0U)
/*! DSIZE - Destination data transfer size
*/
#define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
#define DMA_ATTR_DMOD_MASK (0xF8U)
#define DMA_ATTR_DMOD_SHIFT (3U)
/*! DMOD - Destination Address Modulo
*/
#define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
#define DMA_ATTR_SSIZE_MASK (0x700U)
#define DMA_ATTR_SSIZE_SHIFT (8U)
/*! SSIZE - Source data transfer size
* 0b000..8-bit
* 0b001..16-bit
* 0b010..32-bit
* 0b011..64-bit
* 0b100..Reserved
* 0b101..32-byte burst (4 beats of 64 bits)
* 0b110..Reserved
* 0b111..Reserved
*/
#define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
#define DMA_ATTR_SMOD_MASK (0xF800U)
#define DMA_ATTR_SMOD_SHIFT (11U)
/*! SMOD - Source Address Modulo
* 0b00000..Source address modulo feature is disabled
* 0b00001-0b11111..Value defines address range used to set up circular data queue
*/
#define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
/*! @} */
/* The count of DMA_ATTR */
#define DMA_ATTR_COUNT (32U)
/*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Mapping Disabled) */
/*! @{ */
#define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
#define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
/*! NBYTES - Minor Byte Transfer Count
*/
#define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
/*! @} */
/* The count of DMA_NBYTES_MLNO */
#define DMA_NBYTES_MLNO_COUNT (32U)
/*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Mapping Enabled and Offset Disabled) */
/*! @{ */
#define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
#define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
/*! NBYTES - Minor Byte Transfer Count
*/
#define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
#define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
#define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
* 0b0..The minor loop offset is not applied to the DADDR
* 0b1..The minor loop offset is applied to the DADDR
*/
#define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
#define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
#define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
/*! SMLOE - Source Minor Loop Offset Enable
* 0b0..The minor loop offset is not applied to the SADDR
* 0b1..The minor loop offset is applied to the SADDR
*/
#define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
/*! @} */
/* The count of DMA_NBYTES_MLOFFNO */
#define DMA_NBYTES_MLOFFNO_COUNT (32U)
/*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop Mapping and Offset Enabled) */
/*! @{ */
#define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
#define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
/*! NBYTES - Minor Byte Transfer Count
*/
#define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
#define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
#define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
/*! MLOFF - If SMLOE = 1 or DMLOE = 1, this field represents a sign-extended offset applied to the
* source or destination address to form the next-state value after the minor loop completes.
*/
#define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
#define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
#define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
/*! DMLOE - Destination Minor Loop Offset Enable
* 0b0..The minor loop offset is not applied to the DADDR
* 0b1..The minor loop offset is applied to the DADDR
*/
#define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
#define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
#define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
/*! SMLOE - Source Minor Loop Offset Enable
* 0b0..The minor loop offset is not applied to the SADDR
* 0b1..The minor loop offset is applied to the SADDR
*/
#define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
/*! @} */
/* The count of DMA_NBYTES_MLOFFYES */
#define DMA_NBYTES_MLOFFYES_COUNT (32U)
/*! @name SLAST - TCD Last Source Address Adjustment */
/*! @{ */
#define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
#define DMA_SLAST_SLAST_SHIFT (0U)
/*! SLAST - Last Source Address Adjustment
*/
#define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
/*! @} */
/* The count of DMA_SLAST */
#define DMA_SLAST_COUNT (32U)
/*! @name DADDR - TCD Destination Address */
/*! @{ */
#define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
#define DMA_DADDR_DADDR_SHIFT (0U)
/*! DADDR - Destination Address
*/
#define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
/*! @} */
/* The count of DMA_DADDR */
#define DMA_DADDR_COUNT (32U)
/*! @name DOFF - TCD Signed Destination Address Offset */
/*! @{ */
#define DMA_DOFF_DOFF_MASK (0xFFFFU)
#define DMA_DOFF_DOFF_SHIFT (0U)
/*! DOFF - Destination Address Signed Offset
*/
#define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
/*! @} */
/* The count of DMA_DOFF */
#define DMA_DOFF_COUNT (32U)
/*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
/*! @{ */
#define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
#define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
/*! CITER - Current Major Iteration Count
*/
#define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
#define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
#define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
/*! ELINK - Enable channel-to-channel linking on minor-loop complete
* 0b0..Channel-to-channel linking is disabled
* 0b1..Channel-to-channel linking is enabled
*/
#define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
/*! @} */
/* The count of DMA_CITER_ELINKNO */
#define DMA_CITER_ELINKNO_COUNT (32U)
/*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
/*! @{ */
#define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
#define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
/*! CITER - Current Major Iteration Count
*/
#define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
#define DMA_CITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
/*! LINKCH - Minor Loop Link Channel Number
*/
#define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
#define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
#define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
/*! ELINK - Enable channel-to-channel linking on minor-loop complete
* 0b0..Channel-to-channel linking is disabled
* 0b1..Channel-to-channel linking is enabled
*/
#define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
/*! @} */
/* The count of DMA_CITER_ELINKYES */
#define DMA_CITER_ELINKYES_COUNT (32U)
/*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
/*! @{ */
#define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
#define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
/*! DLASTSGA - Destination last address adjustment, or next memory address TCD for channel (scatter/gather)
*/
#define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
/*! @} */
/* The count of DMA_DLAST_SGA */
#define DMA_DLAST_SGA_COUNT (32U)
/*! @name CSR - TCD Control and Status */
/*! @{ */
#define DMA_CSR_START_MASK (0x1U)
#define DMA_CSR_START_SHIFT (0U)
/*! START - Channel Start
* 0b0..Channel is not explicitly started
* 0b1..Channel is explicitly started via a software initiated service request
*/
#define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
#define DMA_CSR_INTMAJOR_MASK (0x2U)
#define DMA_CSR_INTMAJOR_SHIFT (1U)
/*! INTMAJOR - Enable an interrupt when major iteration count completes.
* 0b0..End of major loop interrupt is disabled
* 0b1..End of major loop interrupt is enabled
*/
#define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
#define DMA_CSR_INTHALF_MASK (0x4U)
#define DMA_CSR_INTHALF_SHIFT (2U)
/*! INTHALF - Enable an interrupt when major counter is half complete.
* 0b0..Half-point interrupt is disabled
* 0b1..Half-point interrupt is enabled
*/
#define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
#define DMA_CSR_DREQ_MASK (0x8U)
#define DMA_CSR_DREQ_SHIFT (3U)
/*! DREQ - Disable Request
* 0b0..The channel's ERQ field is not affected
* 0b1..The channel's ERQ field value changes to 0 when the major loop is complete
*/
#define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
#define DMA_CSR_ESG_MASK (0x10U)
#define DMA_CSR_ESG_SHIFT (4U)
/*! ESG - Enable Scatter/Gather Processing
* 0b0..The current channel's TCD is normal format
* 0b1..The current channel's TCD specifies a scatter gather format
*/
#define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
#define DMA_CSR_MAJORELINK_MASK (0x20U)
#define DMA_CSR_MAJORELINK_SHIFT (5U)
/*! MAJORELINK - Enable channel-to-channel linking on major loop complete
* 0b0..Channel-to-channel linking is disabled
* 0b1..Channel-to-channel linking is enabled
*/
#define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
#define DMA_CSR_ACTIVE_MASK (0x40U)
#define DMA_CSR_ACTIVE_SHIFT (6U)
/*! ACTIVE - Channel Active
*/
#define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
#define DMA_CSR_DONE_MASK (0x80U)
#define DMA_CSR_DONE_SHIFT (7U)
/*! DONE - Channel Done
*/
#define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
#define DMA_CSR_MAJORLINKCH_MASK (0x1F00U)
#define DMA_CSR_MAJORLINKCH_SHIFT (8U)
/*! MAJORLINKCH - Major Loop Link Channel Number
*/
#define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
#define DMA_CSR_BWC_MASK (0xC000U)
#define DMA_CSR_BWC_SHIFT (14U)
/*! BWC - Bandwidth Control
* 0b00..No eDMA engine stalls
* 0b01..Reserved
* 0b10..eDMA engine stalls for 4 cycles after each R/W
* 0b11..eDMA engine stalls for 8 cycles after each R/W
*/
#define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
/*! @} */
/* The count of DMA_CSR */
#define DMA_CSR_COUNT (32U)
/*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
/*! @{ */
#define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
#define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
/*! BITER - Starting Major Iteration Count
*/
#define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
#define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
#define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
/*! ELINK - Enables channel-to-channel linking on minor loop complete
* 0b0..Channel-to-channel linking is disabled
* 0b1..Channel-to-channel linking is enabled
*/
#define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
/*! @} */
/* The count of DMA_BITER_ELINKNO */
#define DMA_BITER_ELINKNO_COUNT (32U)
/*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
/*! @{ */
#define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
#define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
/*! BITER - Starting major iteration count
*/
#define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
#define DMA_BITER_ELINKYES_LINKCH_MASK (0x3E00U)
#define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
/*! LINKCH - Link Channel Number
*/
#define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
#define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
#define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
/*! ELINK - Enables channel-to-channel linking on minor loop complete
* 0b0..Channel-to-channel linking is disabled
* 0b1..Channel-to-channel linking is enabled
*/
#define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
/*! @} */
/* The count of DMA_BITER_ELINKYES */
#define DMA_BITER_ELINKYES_COUNT (32U)
/*!
* @}
*/ /* end of group DMA_Register_Masks */
/* DMA - Peripheral instance base addresses */
/** Peripheral DMA0 base address */
#define DMA0_BASE (0x40070000u)
/** Peripheral DMA0 base pointer */
#define DMA0 ((DMA_Type *)DMA0_BASE)
/** Array initializer of DMA peripheral base addresses */
#define DMA_BASE_ADDRS { DMA0_BASE }
/** Array initializer of DMA peripheral base pointers */
#define DMA_BASE_PTRS { DMA0 }
/** Interrupt vectors for the DMA peripheral type */
#define DMA_CHN_IRQS { { DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn, DMA0_DMA16_IRQn, DMA1_DMA17_IRQn, DMA2_DMA18_IRQn, DMA3_DMA19_IRQn, DMA4_DMA20_IRQn, DMA5_DMA21_IRQn, DMA6_DMA22_IRQn, DMA7_DMA23_IRQn, DMA8_DMA24_IRQn, DMA9_DMA25_IRQn, DMA10_DMA26_IRQn, DMA11_DMA27_IRQn, DMA12_DMA28_IRQn, DMA13_DMA29_IRQn, DMA14_DMA30_IRQn, DMA15_DMA31_IRQn } }
#define DMA_ERROR_IRQS { DMA_ERROR_IRQn }
/*!
* @}
*/ /* end of group DMA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DMAMUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
* @{
*/
/** DMAMUX - Register Layout Typedef */
typedef struct {
__IO uint32_t CHCFG[32]; /**< Channel 0 Configuration Register..Channel 31 Configuration Register, array offset: 0x0, array step: 0x4 */
} DMAMUX_Type;
/* ----------------------------------------------------------------------------
-- DMAMUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
* @{
*/
/*! @name CHCFG - Channel 0 Configuration Register..Channel 31 Configuration Register */
/*! @{ */
#define DMAMUX_CHCFG_SOURCE_MASK (0xFFU)
#define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
/*! SOURCE - DMA Channel Source (Slot Number)
*/
#define DMAMUX_CHCFG_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
#define DMAMUX_CHCFG_A_ON_MASK (0x20000000U)
#define DMAMUX_CHCFG_A_ON_SHIFT (29U)
/*! A_ON - DMA Channel Always Enable
* 0b0..DMA Channel Always ON function is disabled
* 0b1..DMA Channel Always ON function is enabled
*/
#define DMAMUX_CHCFG_A_ON(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_A_ON_SHIFT)) & DMAMUX_CHCFG_A_ON_MASK)
#define DMAMUX_CHCFG_TRIG_MASK (0x40000000U)
#define DMAMUX_CHCFG_TRIG_SHIFT (30U)
/*! TRIG - DMA Channel Trigger Enable
* 0b0..Triggering is disabled. If triggering is disabled and ENBL is set, the DMA Channel will simply route the
* specified source to the DMA channel. (Normal mode)
* 0b1..Triggering is enabled. If triggering is enabled and ENBL is set, the DMA_CH_MUX is in Periodic Trigger mode.
*/
#define DMAMUX_CHCFG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
#define DMAMUX_CHCFG_ENBL_MASK (0x80000000U)
#define DMAMUX_CHCFG_ENBL_SHIFT (31U)
/*! ENBL - DMA Mux Channel Enable
* 0b0..DMA Mux channel is disabled
* 0b1..DMA Mux channel is enabled
*/
#define DMAMUX_CHCFG_ENBL(x) (((uint32_t)(((uint32_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
/*! @} */
/* The count of DMAMUX_CHCFG */
#define DMAMUX_CHCFG_COUNT (32U)
/*!
* @}
*/ /* end of group DMAMUX_Register_Masks */
/* DMAMUX - Peripheral instance base addresses */
/** Peripheral DMAMUX0 base address */
#define DMAMUX0_BASE (0x40074000u)
/** Peripheral DMAMUX0 base pointer */
#define DMAMUX0 ((DMAMUX_Type *)DMAMUX0_BASE)
/** Array initializer of DMAMUX peripheral base addresses */
#define DMAMUX_BASE_ADDRS { DMAMUX0_BASE }
/** Array initializer of DMAMUX peripheral base pointers */
#define DMAMUX_BASE_PTRS { DMAMUX0 }
/*!
* @}
*/ /* end of group DMAMUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DSI_HOST Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DSI_HOST_Peripheral_Access_Layer DSI_HOST Peripheral Access Layer
* @{
*/
/** DSI_HOST - Register Layout Typedef */
typedef struct {
__IO uint32_t CFG_NUM_LANES; /**< CFG_NUM_LANES, offset: 0x0 */
__IO uint32_t CFG_NONCONTINUOUS_CLK; /**< CFG_NONCONTINUOUS_CLK, offset: 0x4 */
__IO uint32_t CFG_T_PRE; /**< CFG_T_PRE, offset: 0x8 */
__IO uint32_t CFG_T_POST; /**< CFG_T_POST, offset: 0xC */
__IO uint32_t CFG_TX_GAP; /**< CFG_TX_GAP, offset: 0x10 */
__IO uint32_t CFG_AUTOINSERT_EOTP; /**< CFG_AUTOINSERT_ETOP, offset: 0x14 */
__IO uint32_t CFG_EXTRA_CMDS_AFTER_EOTP; /**< CFG_EXTRA_CMDS_AFTER_ETOP, offset: 0x18 */
__IO uint32_t CFG_HTX_TO_COUNT; /**< CFG_HTX_TO_COUNT, offset: 0x1C */
__IO uint32_t CFG_LRX_H_TO_COUNT; /**< CFG_LRX_H_TO_COUNT, offset: 0x20 */
__IO uint32_t CFG_BTA_H_TO_COUNT; /**< CFG_BTA_H_TO_COUNT, offset: 0x24 */
__IO uint32_t CFG_TWAKEUP; /**< CFG_TWAKEUP, offset: 0x28 */
__I uint32_t CFG_STATUS_OUT; /**< CFG_STATUS_OUT, offset: 0x2C */
__I uint32_t RX_ERROR_STATUS; /**< RX_ERROR_STATUS, offset: 0x30 */
} DSI_HOST_Type;
/* ----------------------------------------------------------------------------
-- DSI_HOST Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DSI_HOST_Register_Masks DSI_HOST Register Masks
* @{
*/
/*! @name CFG_NUM_LANES - CFG_NUM_LANES */
/*! @{ */
#define DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK (0x3U)
#define DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT (0U)
/*! NUM_LANES - Sets the number of active lanes that are to be used for transmitting data.
* 0b00..1 lane
* 0b01..2 lanes
*/
#define DSI_HOST_CFG_NUM_LANES_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NUM_LANES_NUM_LANES_SHIFT)) & DSI_HOST_CFG_NUM_LANES_NUM_LANES_MASK)
/*! @} */
/*! @name CFG_NONCONTINUOUS_CLK - CFG_NONCONTINUOUS_CLK */
/*! @{ */
#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK (0x1U)
#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT (0U)
/*! CLK_MODE - Sets the Host Controller into non-continuous MIPI clock mode. When in non-continuous
* clock mode, the high speed clock will transition into low power mode between transmissions.
* 0b0..Continuous high speed clock
* 0b1..Non-Continuous high speed clock
*/
#define DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_SHIFT)) & DSI_HOST_CFG_NONCONTINUOUS_CLK_CLK_MODE_MASK)
/*! @} */
/*! @name CFG_T_PRE - CFG_T_PRE */
/*! @{ */
#define DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK (0xFFU)
#define DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT (0U)
/*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will
* wait after enabling the clock lane for HS operation before enabling the data lanes for HS
* operation. This setting represents the TCLK-PRE DPHY timing parameter. The minimum value for this
* port is 1.
*/
#define DSI_HOST_CFG_T_PRE_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_PRE_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_PRE_NUM_PERIODS_MASK)
/*! @} */
/*! @name CFG_T_POST - CFG_T_POST */
/*! @{ */
#define DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK (0xFFU)
#define DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT (0U)
/*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) to wait before putting
* the clock lane into LP mode after the data lanes have been detected to be in Stop State. This
* setting represents the DPHY timing parameters TLPX + TCLK-PREPARE + TCLK-ZERO + TCLK-PRE
* requirement for the clock lane before the data lane is allowed to change from LP11 to start a high
* speed transmission. The minimum value for this port is 1.
*/
#define DSI_HOST_CFG_T_POST_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_T_POST_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_T_POST_NUM_PERIODS_MASK)
/*! @} */
/*! @name CFG_TX_GAP - CFG_TX_GAP */
/*! @{ */
#define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK (0xFFU)
#define DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT (0U)
/*! NUM_PERIODS - Sets the number of byte clock periods ('clk_byte' input) that the controller will
* wait after the clock lane has been put into LP mode before enabling the clock lane for HS mode
* again. This setting represents the THS-EXIT DPHY timing parameter. The minimum value for this
* port is 1.
*/
#define DSI_HOST_CFG_TX_GAP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TX_GAP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TX_GAP_NUM_PERIODS_MASK)
/*! @} */
/*! @name CFG_AUTOINSERT_EOTP - CFG_AUTOINSERT_ETOP */
/*! @{ */
#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK (0x1U)
#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT (0U)
/*! AUTOINSERT - Enables the Host Controller to automatically insert an EoTp short packet when switching from HS to LP mode.
* 0b0..EoTp is not automatically inserted
* 0b1..EoTp is automatically inserted
*/
#define DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_SHIFT)) & DSI_HOST_CFG_AUTOINSERT_EOTP_AUTOINSERT_MASK)
/*! @} */
/*! @name CFG_EXTRA_CMDS_AFTER_EOTP - CFG_EXTRA_CMDS_AFTER_ETOP */
/*! @{ */
#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK (0xFFU)
#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT (0U)
/*! EXTRA_EOTP - Configures the DSI Host Controller to send extra End Of Transmission Packets after
* the end of a packet. The value is the number of extra EOTP packets sent.
*/
#define DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_SHIFT)) & DSI_HOST_CFG_EXTRA_CMDS_AFTER_EOTP_EXTRA_EOTP_MASK)
/*! @} */
/*! @name CFG_HTX_TO_COUNT - CFG_HTX_TO_COUNT */
/*! @{ */
#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK (0xFFFFFFU)
#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT (0U)
/*! COUNT - Sets the value of the DSI Host High Speed TX timeout count in clk_byte clock periods
* that once reached will initiate a timeout error and follow the recovery procedure documented in
* the DSI specification.
*/
#define DSI_HOST_CFG_HTX_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_HTX_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_HTX_TO_COUNT_COUNT_MASK)
/*! @} */
/*! @name CFG_LRX_H_TO_COUNT - CFG_LRX_H_TO_COUNT */
/*! @{ */
#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK (0xFFFFFFU)
#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT (0U)
/*! COUNT - Sets the value of the DSI Host low power RX timeout count in clk_byte clock periods that
* once reached will initiate a timeout error and follow the recovery procedure documented in
* the DSI specification.
*/
#define DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_LRX_H_TO_COUNT_COUNT_MASK)
/*! @} */
/*! @name CFG_BTA_H_TO_COUNT - CFG_BTA_H_TO_COUNT */
/*! @{ */
#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK (0xFFFFFFU)
#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT (0U)
/*! COUNT - Sets the value of the DSI Host Bus Turn Around (BTA) timeout in clk_byte clock periods
* that once reached will initiate a timeout error.
*/
#define DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_SHIFT)) & DSI_HOST_CFG_BTA_H_TO_COUNT_COUNT_MASK)
/*! @} */
/*! @name CFG_TWAKEUP - CFG_TWAKEUP */
/*! @{ */
#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK (0x7FFFFU)
#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT (0U)
/*! NUM_PERIODS - DPHY Twakeup timing parameter. Sets the number of clk_esc clock periods to keep a
* clock or data lane in Mark-1 state after exiting ULPS. The MIPI DPHY spec requires a minimum
* of 1ms in Mark-1 state after leaving ULPS.
*/
#define DSI_HOST_CFG_TWAKEUP_NUM_PERIODS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_SHIFT)) & DSI_HOST_CFG_TWAKEUP_NUM_PERIODS_MASK)
/*! @} */
/*! @name CFG_STATUS_OUT - CFG_STATUS_OUT */
/*! @{ */
#define DSI_HOST_CFG_STATUS_OUT_STATUS_MASK (0xFFFFFFFFU)
#define DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT (0U)
/*! STATUS - Status Register
*/
#define DSI_HOST_CFG_STATUS_OUT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_CFG_STATUS_OUT_STATUS_SHIFT)) & DSI_HOST_CFG_STATUS_OUT_STATUS_MASK)
/*! @} */
/*! @name RX_ERROR_STATUS - RX_ERROR_STATUS */
/*! @{ */
#define DSI_HOST_RX_ERROR_STATUS_STATUS_MASK (0x7FFU)
#define DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT (0U)
/*! STATUS - Status Register for Host receive error detection, ECC errors, CRC errors and for timeout indicators
*/
#define DSI_HOST_RX_ERROR_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_RX_ERROR_STATUS_STATUS_SHIFT)) & DSI_HOST_RX_ERROR_STATUS_STATUS_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DSI_HOST_Register_Masks */
/* DSI_HOST - Peripheral instance base addresses */
/** Peripheral DSI_HOST base address */
#define DSI_HOST_BASE (0x4080C000u)
/** Peripheral DSI_HOST base pointer */
#define DSI_HOST ((DSI_HOST_Type *)DSI_HOST_BASE)
/** Array initializer of DSI_HOST peripheral base addresses */
#define DSI_HOST_BASE_ADDRS { DSI_HOST_BASE }
/** Array initializer of DSI_HOST peripheral base pointers */
#define DSI_HOST_BASE_PTRS { DSI_HOST }
/** Interrupt vectors for the DSI_HOST peripheral type */
#define DSI_HOST_DSI_IRQS { MIPI_DSI_IRQn }
/*!
* @}
*/ /* end of group DSI_HOST_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DSI_HOST_APB_PKT_IF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer DSI_HOST_APB_PKT_IF Peripheral Access Layer
* @{
*/
/** DSI_HOST_APB_PKT_IF - Register Layout Typedef */
typedef struct {
__IO uint32_t TX_PAYLOAD; /**< TX_PAYLOAD, offset: 0x0 */
__IO uint32_t PKT_CONTROL; /**< PKT_CONTROL, offset: 0x4 */
__IO uint32_t SEND_PACKET; /**< SEND_PACKET, offset: 0x8 */
__I uint32_t PKT_STATUS; /**< PKT_STATUS, offset: 0xC */
__I uint32_t PKT_FIFO_WR_LEVEL; /**< PKT_FIFO_WR_LEVEL, offset: 0x10 */
__I uint32_t PKT_FIFO_RD_LEVEL; /**< PKT_FIFO_RD_LEVEL, offset: 0x14 */
__I uint32_t PKT_RX_PAYLOAD; /**< PKT_RX_PAYLOAD, offset: 0x18 */
__I uint32_t PKT_RX_PKT_HEADER; /**< PKT_RX_PKT_HEADER, offset: 0x1C */
__I uint32_t IRQ_STATUS; /**< IRQ_STATUS, offset: 0x20 */
__I uint32_t IRQ_STATUS2; /**< IRQ_STATUS2, offset: 0x24 */
__IO uint32_t IRQ_MASK; /**< IRQ_MASK, offset: 0x28 */
__IO uint32_t IRQ_MASK2; /**< IRQ_MASK2, offset: 0x2C */
} DSI_HOST_APB_PKT_IF_Type;
/* ----------------------------------------------------------------------------
-- DSI_HOST_APB_PKT_IF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DSI_HOST_APB_PKT_IF_Register_Masks DSI_HOST_APB_PKT_IF Register Masks
* @{
*/
/*! @name TX_PAYLOAD - TX_PAYLOAD */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
#define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT (0U)
/*! PAYLOAD - Tx Payload data write register. Write to this register loads the payload FIFO with 32 bit values.
*/
#define DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_TX_PAYLOAD_PAYLOAD_MASK)
/*! @} */
/*! @name PKT_CONTROL - PKT_CONTROL */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK (0x7FFFFFFU)
#define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT (0U)
/*! CTRL - Tx packet control
*/
#define DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_CONTROL_CTRL_MASK)
/*! @} */
/*! @name SEND_PACKET - SEND_PACKET */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK (0x1U)
#define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT (0U)
/*! TX_SEND - Tx send packet, writing to this register causes the packet described in dsi_host_pkt_control to be sent.
* 0b0..Packet not sent
* 0b1..Packet is sent
*/
#define DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_SHIFT)) & DSI_HOST_APB_PKT_IF_SEND_PACKET_TX_SEND_MASK)
/*! @} */
/*! @name PKT_STATUS - PKT_STATUS */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK (0x1FFU)
#define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT (0U)
/*! STATUS - Status of APB to packet interface.
*/
#define DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_STATUS_STATUS_MASK)
/*! @} */
/*! @name PKT_FIFO_WR_LEVEL - PKT_FIFO_WR_LEVEL */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK (0xFFFFU)
#define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT (0U)
/*! WR - Write level of APB to pkt interface FIFO
*/
#define DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_WR_LEVEL_WR_MASK)
/*! @} */
/*! @name PKT_FIFO_RD_LEVEL - PKT_FIFO_RD_LEVEL */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK (0xFFFFU)
#define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT (0U)
/*! RD - Read level of APB to pkt interface FIFO
*/
#define DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_FIFO_RD_LEVEL_RD_MASK)
/*! @} */
/*! @name PKT_RX_PAYLOAD - PKT_RX_PAYLOAD */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK (0xFFFFFFFFU)
#define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT (0U)
/*! PAYLOAD - APB to pkt interface Rx payload read
*/
#define DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PAYLOAD_PAYLOAD_MASK)
/*! @} */
/*! @name PKT_RX_PKT_HEADER - PKT_RX_PKT_HEADER */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK (0xFFFFFFU)
#define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT (0U)
/*! HEADER - APB to pkt interface Rx packet header
*/
#define DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_SHIFT)) & DSI_HOST_APB_PKT_IF_PKT_RX_PKT_HEADER_HEADER_MASK)
/*! @} */
/*! @name IRQ_STATUS - IRQ_STATUS */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK (0xFFFFFFFFU)
#define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT (0U)
/*! STATUS - Status of APB to packet interface.
*/
#define DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS_STATUS_MASK)
/*! @} */
/*! @name IRQ_STATUS2 - IRQ_STATUS2 */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK (0x7U)
#define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT (0U)
/*! STATUS2 - Status of APB to packet interface part 2, read part 2 first then dsi_host_irq_status.
* Reading dsi_host_irq_status will clear both status and status2.
*/
#define DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_STATUS2_STATUS2_MASK)
/*! @} */
/*! @name IRQ_MASK - IRQ_MASK */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK (0xFFFFFFFFU)
#define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT (0U)
/*! MASK - IRQ Mask
*/
#define DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK_MASK_MASK)
/*! @} */
/*! @name IRQ_MASK2 - IRQ_MASK2 */
/*! @{ */
#define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK (0x7U)
#define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT (0U)
/*! MASK2 - IRQ mask 2
*/
#define DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_SHIFT)) & DSI_HOST_APB_PKT_IF_IRQ_MASK2_MASK2_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DSI_HOST_APB_PKT_IF_Register_Masks */
/* DSI_HOST_APB_PKT_IF - Peripheral instance base addresses */
/** Peripheral DSI_HOST_APB_PKT_IF base address */
#define DSI_HOST_APB_PKT_IF_BASE (0x4080C280u)
/** Peripheral DSI_HOST_APB_PKT_IF base pointer */
#define DSI_HOST_APB_PKT_IF ((DSI_HOST_APB_PKT_IF_Type *)DSI_HOST_APB_PKT_IF_BASE)
/** Array initializer of DSI_HOST_APB_PKT_IF peripheral base addresses */
#define DSI_HOST_APB_PKT_IF_BASE_ADDRS { DSI_HOST_APB_PKT_IF_BASE }
/** Array initializer of DSI_HOST_APB_PKT_IF peripheral base pointers */
#define DSI_HOST_APB_PKT_IF_BASE_PTRS { DSI_HOST_APB_PKT_IF }
/*!
* @}
*/ /* end of group DSI_HOST_APB_PKT_IF_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DSI_HOST_DPI_INTFC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DSI_HOST_DPI_INTFC_Peripheral_Access_Layer DSI_HOST_DPI_INTFC Peripheral Access Layer
* @{
*/
/** DSI_HOST_DPI_INTFC - Register Layout Typedef */
typedef struct {
__IO uint32_t PIXEL_PAYLOAD_SIZE; /**< PEXEL_PAYLOAD_SIZE, offset: 0x0 */
__IO uint32_t PIXEL_FIFO_SEND_LEVEL; /**< PIXEL_FIFO_SEND_LEVEL, offset: 0x4 */
__IO uint32_t INTERFACE_COLOR_CODING; /**< INTERFACE_COLOR_CODING, offset: 0x8 */
__IO uint32_t PIXEL_FORMAT; /**< PIXEL_FORMAT, offset: 0xC */
__IO uint32_t VSYNC_POLARITY; /**< VSYNC_POLARITY, offset: 0x10 */
__IO uint32_t HSYNC_POLARITY; /**< HSYNC_POLARITY, offset: 0x14 */
__IO uint32_t VIDEO_MODE; /**< VIDEO_MODE, offset: 0x18 */
__IO uint32_t HFP; /**< HFP, offset: 0x1C */
__IO uint32_t HBP; /**< HBP, offset: 0x20 */
__IO uint32_t HSA; /**< HSA, offset: 0x24 */
__IO uint32_t ENABLE_MULT_PKTS; /**< ENABLE_MULT_PKTS, offset: 0x28 */
__IO uint32_t VBP; /**< VBP, offset: 0x2C */
__IO uint32_t VFP; /**< VFP, offset: 0x30 */
__IO uint32_t BLLP_MODE; /**< BLLP_MODE, offset: 0x34 */
__IO uint32_t USE_NULL_PKT_BLLP; /**< USE_NULL_PKT_BLLP, offset: 0x38 */
__IO uint32_t VACTIVE; /**< VACTIVE, offset: 0x3C */
} DSI_HOST_DPI_INTFC_Type;
/* ----------------------------------------------------------------------------
-- DSI_HOST_DPI_INTFC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DSI_HOST_DPI_INTFC_Register_Masks DSI_HOST_DPI_INTFC Register Masks
* @{
*/
/*! @name PIXEL_PAYLOAD_SIZE - PEXEL_PAYLOAD_SIZE */
/*! @{ */
#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK (0xFFFFU)
#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT (0U)
/*! PAYLOAD_SIZE - Maximum number of pixels that should be sent as one DSI packet. Recommended to be
* evenly divisible by the line size (in pixels).
*/
#define DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_PAYLOAD_SIZE_PAYLOAD_SIZE_MASK)
/*! @} */
/*! @name PIXEL_FIFO_SEND_LEVEL - PIXEL_FIFO_SEND_LEVEL */
/*! @{ */
#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK (0xFFFFU)
#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT (0U)
/*! FIFO_SEND_LEVEL - In order to optimize DSI utility, the DPI bridge buffers a certain number of
* DPI pixels before initiating a DSI packet. This configuration port controls the level at which
* the DPI Host bridge begins sending pixels.
*/
#define DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FIFO_SEND_LEVEL_FIFO_SEND_LEVEL_MASK)
/*! @} */
/*! @name INTERFACE_COLOR_CODING - INTERFACE_COLOR_CODING */
/*! @{ */
#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK (0x7U)
#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT (0U)
/*! RGB_CONFIG - Sets the distribution of RGB bits within the 24-bit d bus, as specified by the DPI specification.
* 0b000..16-bit Configuration 1
* 0b001..16-bit Configuration 2
* 0b010..16-bit Configuration 3
* 0b011..18-bit Configuration 1
* 0b100..18-bit Configuration 2
* 0b101..24-bit
* 0b110, 0b111..Reserved
*/
#define DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_SHIFT)) & DSI_HOST_DPI_INTFC_INTERFACE_COLOR_CODING_RGB_CONFIG_MASK)
/*! @} */
/*! @name PIXEL_FORMAT - PIXEL_FORMAT */
/*! @{ */
#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK (0x3U)
#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT (0U)
/*! PIXEL_FORMAT - Sets the DSI packet type of the pixels
* 0b00..16 bit
* 0b01..18 bit
* 0b10..18 bit loosely packed
* 0b11..24 bit
*/
#define DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_SHIFT)) & DSI_HOST_DPI_INTFC_PIXEL_FORMAT_PIXEL_FORMAT_MASK)
/*! @} */
/*! @name VSYNC_POLARITY - VSYNC_POLARITY */
/*! @{ */
#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK (0x1U)
#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT (0U)
/*! VSYNC_POLARITY - Sets polarity of dpi_vsync_input
* 0b0..active low
* 0b1..active high
*/
#define DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_VSYNC_POLARITY_VSYNC_POLARITY_MASK)
/*! @} */
/*! @name HSYNC_POLARITY - HSYNC_POLARITY */
/*! @{ */
#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK (0x1U)
#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT (0U)
/*! HSYNC_POLARITY - Sets polarity of dpi_hsync_input
* 0b0..active low
* 0b1..active high
*/
#define DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_SHIFT)) & DSI_HOST_DPI_INTFC_HSYNC_POLARITY_HSYNC_POLARITY_MASK)
/*! @} */
/*! @name VIDEO_MODE - VIDEO_MODE */
/*! @{ */
#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK (0x3U)
#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT (0U)
/*! VIDEO_MODE - Select DSI video mode that the host DPI module should generate packets for.
* 0b00..Non-Burst mode with Sync Pulses
* 0b01..Non-Burst mode with Sync Events
* 0b10..Burst mode
* 0b11..Reserved, not valid
*/
#define DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_SHIFT)) & DSI_HOST_DPI_INTFC_VIDEO_MODE_VIDEO_MODE_MASK)
/*! @} */
/*! @name HFP - HFP */
/*! @{ */
#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK (0xFFFFU)
#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT (0U)
/*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal front porch blanking packet.
*/
#define DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HFP_PAYLOAD_SIZE_MASK)
/*! @} */
/*! @name HBP - HBP */
/*! @{ */
#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK (0xFFFFU)
#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT (0U)
/*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal back porch blanking packet.
*/
#define DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HBP_PAYLOAD_SIZE_MASK)
/*! @} */
/*! @name HSA - HSA */
/*! @{ */
#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK (0xFFFFU)
#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT (0U)
/*! PAYLOAD_SIZE - Sets the DSI packet payload size, in bytes, of the horizontal sync width filler blanking packet.
*/
#define DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_SHIFT)) & DSI_HOST_DPI_INTFC_HSA_PAYLOAD_SIZE_MASK)
/*! @} */
/*! @name ENABLE_MULT_PKTS - ENABLE_MULT_PKTS */
/*! @{ */
#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK (0x1U)
#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT (0U)
/*! ENABLE_MULT_PKTS - Enable Multiple packets per video line. When enabled,
* PIXEL_PAYLOAD_SIZE[PAYLOAD_SIZE] must be set to exactly half the size of the video line
* 0b0..Video Line is sent in a single packet
* 0b1..Video Line is sent in two packets
*/
#define DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_SHIFT)) & DSI_HOST_DPI_INTFC_ENABLE_MULT_PKTS_ENABLE_MULT_PKTS_MASK)
/*! @} */
/*! @name VBP - VBP */
/*! @{ */
#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK (0xFFU)
#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT (0U)
/*! NUM_LINES - Sets the number of lines in the vertical back porch.
*/
#define DSI_HOST_DPI_INTFC_VBP_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VBP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VBP_NUM_LINES_MASK)
/*! @} */
/*! @name VFP - VFP */
/*! @{ */
#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK (0xFFU)
#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT (0U)
/*! NUM_LINES - Sets the number of lines in the vertical front porch.
*/
#define DSI_HOST_DPI_INTFC_VFP_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VFP_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VFP_NUM_LINES_MASK)
/*! @} */
/*! @name BLLP_MODE - BLLP_MODE */
/*! @{ */
#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK (0x1U)
#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT (0U)
/*! LP - Optimize bllp periods to Low Power mode when possible
* 0b0..Blanking packets are sent during BLLP periods
* 0b1..LP mode is used for BLLP periods
*/
#define DSI_HOST_DPI_INTFC_BLLP_MODE_LP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_BLLP_MODE_LP_SHIFT)) & DSI_HOST_DPI_INTFC_BLLP_MODE_LP_MASK)
/*! @} */
/*! @name USE_NULL_PKT_BLLP - USE_NULL_PKT_BLLP */
/*! @{ */
#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK (0x1U)
#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT (0U)
/*! NULL - Selects type of blanking packet to be sent during bllp
* 0b0..Blanking packet used in bllp region 1
* 0b1..Null packet used in bllp region
*/
#define DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_SHIFT)) & DSI_HOST_DPI_INTFC_USE_NULL_PKT_BLLP_NULL_MASK)
/*! @} */
/*! @name VACTIVE - VACTIVE */
/*! @{ */
#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK (0x3FFFU)
#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT (0U)
/*! NUM_LINES - Sets the number of lines in the vertical active aread.
*/
#define DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_SHIFT)) & DSI_HOST_DPI_INTFC_VACTIVE_NUM_LINES_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DSI_HOST_DPI_INTFC_Register_Masks */
/* DSI_HOST_DPI_INTFC - Peripheral instance base addresses */
/** Peripheral DSI_HOST_DPI_INTFC base address */
#define DSI_HOST_DPI_INTFC_BASE (0x4080C200u)
/** Peripheral DSI_HOST_DPI_INTFC base pointer */
#define DSI_HOST_DPI_INTFC ((DSI_HOST_DPI_INTFC_Type *)DSI_HOST_DPI_INTFC_BASE)
/** Array initializer of DSI_HOST_DPI_INTFC peripheral base addresses */
#define DSI_HOST_DPI_INTFC_BASE_ADDRS { DSI_HOST_DPI_INTFC_BASE }
/** Array initializer of DSI_HOST_DPI_INTFC peripheral base pointers */
#define DSI_HOST_DPI_INTFC_BASE_PTRS { DSI_HOST_DPI_INTFC }
/*!
* @}
*/ /* end of group DSI_HOST_DPI_INTFC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer DSI_HOST_NXP_FDSOI28_DPHY_INTFC Peripheral Access Layer
* @{
*/
/** DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Register Layout Typedef */
typedef struct {
__IO uint32_t PD_TX; /**< PD_TX, offset: 0x0 */
__IO uint32_t M_PRG_HS_PREPARE; /**< M_PRG_HS_PREPARE, offset: 0x4 */
__IO uint32_t MC_PRG_HS_PREPARE; /**< MC_PRG_HS_PREPARE, offset: 0x8 */
__IO uint32_t M_PRG_HS_ZERO; /**< M_PRG_HS_ZERO, offset: 0xC */
__IO uint32_t MC_PRG_HS_ZERO; /**< MC_PRG_HS_ZERO, offset: 0x10 */
__IO uint32_t M_PRG_HS_TRAIL; /**< M_PRG_HS_TRAIL, offset: 0x14 */
__IO uint32_t MC_PRG_HS_TRAIL; /**< MC_PRG_HS_TRAIL, offset: 0x18 */
__IO uint32_t PD_PLL; /**< PD_PLL, offset: 0x1C */
__IO uint32_t TST; /**< TST, offset: 0x20 */
__IO uint32_t CN; /**< CN, offset: 0x24 */
__IO uint32_t CM; /**< CM, offset: 0x28 */
__IO uint32_t CO; /**< CO, offset: 0x2C */
__I uint32_t LOCK; /**< LOCK, offset: 0x30 */
__IO uint32_t LOCK_BYP; /**< LOCK_BYP, offset: 0x34 */
__IO uint32_t TX_RCAL; /**< TX_RCAL, offset: 0x38 */
__IO uint32_t AUTO_PD_EN; /**< AUTO_PD_EN, offset: 0x3C */
__IO uint32_t RXLPRP; /**< RXLPRP, offset: 0x40 */
__IO uint32_t RXCDRP; /**< RXCDRP, offset: 0x44 */
} DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type;
/* ----------------------------------------------------------------------------
-- DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks DSI_HOST_NXP_FDSOI28_DPHY_INTFC Register Masks
* @{
*/
/*! @name PD_TX - PD_TX */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK (0x1U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT (0U)
/*! PD_TX - Power Down input for D-PHY
* 0b1..Power Down
* 0b0..Power Up
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_TX_PD_TX_MASK)
/*! @} */
/*! @name M_PRG_HS_PREPARE - M_PRG_HS_PREPARE */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK (0x3U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT (0U)
/*! M_PRG_HS_PREPARE - DPHY m_PRG_HS_PREPARE input
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_PREPARE_M_PRG_HS_PREPARE_MASK)
/*! @} */
/*! @name MC_PRG_HS_PREPARE - MC_PRG_HS_PREPARE */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK (0x1U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT (0U)
/*! MC_PRG_HS_PREPARE - DPHY mc_PRG_HS_PREPARE input
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_PREPARE_MC_PRG_HS_PREPARE_MASK)
/*! @} */
/*! @name M_PRG_HS_ZERO - M_PRG_HS_ZERO */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK (0x1FU)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT (0U)
/*! M_PRG_HS_ZERO - DPHY m_PRG_HS_ZERO input
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_ZERO_M_PRG_HS_ZERO_MASK)
/*! @} */
/*! @name MC_PRG_HS_ZERO - MC_PRG_HS_ZERO */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK (0x3FU)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT (0U)
/*! MC_PRG_HS_ZERO - DPHY mc_PRG_HS_ZERO input
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_ZERO_MC_PRG_HS_ZERO_MASK)
/*! @} */
/*! @name M_PRG_HS_TRAIL - M_PRG_HS_TRAIL */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK (0xFU)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT (0U)
/*! M_PRG_HS_TRAIL - DPHY m_PRG_HS_TRAIL input
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_M_PRG_HS_TRAIL_M_PRG_HS_TRAIL_MASK)
/*! @} */
/*! @name MC_PRG_HS_TRAIL - MC_PRG_HS_TRAIL */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK (0xFU)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT (0U)
/*! MC_PRG_HS_TRAIL - DPHY mc_PRG_HS_TRAIL input
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_MC_PRG_HS_TRAIL_MC_PRG_HS_TRAIL_MASK)
/*! @} */
/*! @name PD_PLL - PD_PLL */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK (0x1U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT (0U)
/*! PD_PLL - Power-down signal
* 0b1..Power down PLL
* 0b0..Power up PLL
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_PD_PLL_PD_PLL_MASK)
/*! @} */
/*! @name TST - TST */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK (0x3FU)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT (0U)
/*! TST - Test
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TST_TST_MASK)
/*! @} */
/*! @name CN - CN */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK (0x1FU)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT (0U)
/*! CN - Control N divider
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CN_CN_MASK)
/*! @} */
/*! @name CM - CM */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK (0xFFU)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT (0U)
/*! CM - Control M divider
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CM_CM_MASK)
/*! @} */
/*! @name CO - CO */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK (0x3U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT (0U)
/*! CO - Control O divider
* 0b00..Divide by 1
* 0b01..Divide by 2
* 0b10..Divide by 4
* 0b11..Divide by 8
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_CO_CO_MASK)
/*! @} */
/*! @name LOCK - LOCK */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK (0x1U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT (0U)
/*! LOCK - Lock Detect output
* 0b1..PLL has achieved frequency lock
* 0b0..PLL not locked
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_LOCK_MASK)
/*! @} */
/*! @name LOCK_BYP - LOCK_BYP */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK (0x1U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT (0U)
/*! LOCK_BYP - DPHY LOCK_BYP input
* 0b0..PLL LOCK signal will gate TxByteClkHS clock
* 0b1..PLL LOCK signal will not gate TxByteClkHS clock, CIL based counter will be used to gate the TxByteClkHS
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_LOCK_BYP_LOCK_BYP_MASK)
/*! @} */
/*! @name TX_RCAL - TX_RCAL */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK (0x3U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT (0U)
/*! TX_RCAL - On-chip termination control bits for manual calibration of HS-TX
* 0b00..20% higher than mid-range. Highest impedance setting
* 0b01..Mid-range impedance setting (default)
* 0b10..15% lower than mid-range
* 0b11..25% lower than mid-range. Lowest impedance setting
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_TX_RCAL_TX_RCAL_MASK)
/*! @} */
/*! @name AUTO_PD_EN - AUTO_PD_EN */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK (0x1U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT (0U)
/*! AUTO_PD_EN - DPHY AUTO_PD_EN input
* 0b0..Inactive lanes are powered up and driving LP11
* 0b1..inactive lanes are powered down
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_AUTO_PD_EN_AUTO_PD_EN_MASK)
/*! @} */
/*! @name RXLPRP - RXLPRP */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK (0x3U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT (0U)
/*! RXLPRP - DPHY RXLPRP input
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXLPRP_RXLPRP_MASK)
/*! @} */
/*! @name RXCDRP - RXCDRP */
/*! @{ */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK (0x3U)
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT (0U)
/*! RXCDRP - DPHY RXCDRP input
* 0b00..344mV
* 0b01..325mV (Default)
* 0b10..307mV
* 0b11..Invalid
*/
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_SHIFT)) & DSI_HOST_NXP_FDSOI28_DPHY_INTFC_RXCDRP_RXCDRP_MASK)
/*! @} */
/*!
* @}
*/ /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Register_Masks */
/* DSI_HOST_NXP_FDSOI28_DPHY_INTFC - Peripheral instance base addresses */
/** Peripheral DSI_HOST_DPHY_INTFC base address */
#define DSI_HOST_DPHY_INTFC_BASE (0x4080C300u)
/** Peripheral DSI_HOST_DPHY_INTFC base pointer */
#define DSI_HOST_DPHY_INTFC ((DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Type *)DSI_HOST_DPHY_INTFC_BASE)
/** Array initializer of DSI_HOST_NXP_FDSOI28_DPHY_INTFC peripheral base
* addresses */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_ADDRS { DSI_HOST_DPHY_INTFC_BASE }
/** Array initializer of DSI_HOST_NXP_FDSOI28_DPHY_INTFC peripheral base
* pointers */
#define DSI_HOST_NXP_FDSOI28_DPHY_INTFC_BASE_PTRS { DSI_HOST_DPHY_INTFC }
/*!
* @}
*/ /* end of group DSI_HOST_NXP_FDSOI28_DPHY_INTFC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- EMVSIM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup EMVSIM_Peripheral_Access_Layer EMVSIM Peripheral Access Layer
* @{
*/
/** EMVSIM - Register Layout Typedef */
typedef struct {
__I uint32_t VER_ID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t CLKCFG; /**< Clock Configuration Register, offset: 0x8 */
__IO uint32_t DIVISOR; /**< Baud Rate Divisor Register, offset: 0xC */
__IO uint32_t CTRL; /**< Control Register, offset: 0x10 */
__IO uint32_t INT_MASK; /**< Interrupt Mask Register, offset: 0x14 */
__IO uint32_t RX_THD; /**< Receiver Threshold Register, offset: 0x18 */
__IO uint32_t TX_THD; /**< Transmitter Threshold Register, offset: 0x1C */
__IO uint32_t RX_STATUS; /**< Receive Status Register, offset: 0x20 */
__IO uint32_t TX_STATUS; /**< Transmitter Status Register, offset: 0x24 */
__IO uint32_t PCSR; /**< Port Control and Status Register, offset: 0x28 */
__I uint32_t RX_BUF; /**< Receive Data Read Buffer, offset: 0x2C */
__O uint32_t TX_BUF; /**< Transmit Data Buffer, offset: 0x30 */
__IO uint32_t TX_GETU; /**< Transmitter Guard ETU Value Register, offset: 0x34 */
__IO uint32_t CWT_VAL; /**< Character Wait Time Value Register, offset: 0x38 */
__IO uint32_t BWT_VAL; /**< Block Wait Time Value Register, offset: 0x3C */
__IO uint32_t BGT_VAL; /**< Block Guard Time Value Register, offset: 0x40 */
__IO uint32_t GPCNT0_VAL; /**< General Purpose Counter 0 Timeout Value Register, offset: 0x44 */
__IO uint32_t GPCNT1_VAL; /**< General Purpose Counter 1 Timeout Value, offset: 0x48 */
} EMVSIM_Type;
/* ----------------------------------------------------------------------------
-- EMVSIM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup EMVSIM_Register_Masks EMVSIM Register Masks
* @{
*/
/*! @name VER_ID - Version ID Register */
/*! @{ */
#define EMVSIM_VER_ID_VER_MASK (0xFFFFFFFFU)
#define EMVSIM_VER_ID_VER_SHIFT (0U)
/*! VER - Version ID of the module
*/
#define EMVSIM_VER_ID_VER(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_VER_ID_VER_SHIFT)) & EMVSIM_VER_ID_VER_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define EMVSIM_PARAM_RX_FIFO_DEPTH_MASK (0xFFU)
#define EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT (0U)
/*! RX_FIFO_DEPTH - Receive FIFO Depth
*/
#define EMVSIM_PARAM_RX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_RX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_RX_FIFO_DEPTH_MASK)
#define EMVSIM_PARAM_TX_FIFO_DEPTH_MASK (0xFF00U)
#define EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT (8U)
/*! TX_FIFO_DEPTH - Transmit FIFO Depth
*/
#define EMVSIM_PARAM_TX_FIFO_DEPTH(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PARAM_TX_FIFO_DEPTH_SHIFT)) & EMVSIM_PARAM_TX_FIFO_DEPTH_MASK)
/*! @} */
/*! @name CLKCFG - Clock Configuration Register */
/*! @{ */
#define EMVSIM_CLKCFG_CLK_PRSC_MASK (0xFFU)
#define EMVSIM_CLKCFG_CLK_PRSC_SHIFT (0U)
/*! CLK_PRSC - Clock Prescaler Value
*/
#define EMVSIM_CLKCFG_CLK_PRSC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_CLK_PRSC_SHIFT)) & EMVSIM_CLKCFG_CLK_PRSC_MASK)
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK (0x300U)
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT (8U)
/*! GPCNT1_CLK_SEL - General Purpose Counter 1 Clock Select
* 0b00..Disabled / Reset
* 0b01..Card Clock
* 0b10..Receive Clock
* 0b11..ETU Clock (transmit clock)
*/
#define EMVSIM_CLKCFG_GPCNT1_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT1_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT1_CLK_SEL_MASK)
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK (0xC00U)
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT (10U)
/*! GPCNT0_CLK_SEL - General Purpose Counter 0 Clock Select
* 0b00..Disabled / Reset
* 0b01..Card Clock
* 0b10..Receive Clock
* 0b11..ETU Clock (transmit clock)
*/
#define EMVSIM_CLKCFG_GPCNT0_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CLKCFG_GPCNT0_CLK_SEL_SHIFT)) & EMVSIM_CLKCFG_GPCNT0_CLK_SEL_MASK)
/*! @} */
/*! @name DIVISOR - Baud Rate Divisor Register */
/*! @{ */
#define EMVSIM_DIVISOR_DIVISOR_VALUE_MASK (0x1FFU)
#define EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT (0U)
/*! DIVISOR_VALUE - Divisor (F/D) Value
* 0b000000000-0b000000100..Invalid. As per ISO 7816 specification, minimum value of F/D is 5
* 0b000000101-0b011111111..Divisor value F/D
*/
#define EMVSIM_DIVISOR_DIVISOR_VALUE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_DIVISOR_DIVISOR_VALUE_SHIFT)) & EMVSIM_DIVISOR_DIVISOR_VALUE_MASK)
/*! @} */
/*! @name CTRL - Control Register */
/*! @{ */
#define EMVSIM_CTRL_IC_MASK (0x1U)
#define EMVSIM_CTRL_IC_SHIFT (0U)
/*! IC - Inverse Convention
* 0b0..Direction convention transfers enabled
* 0b1..Inverse convention transfers enabled
*/
#define EMVSIM_CTRL_IC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_IC_SHIFT)) & EMVSIM_CTRL_IC_MASK)
#define EMVSIM_CTRL_ICM_MASK (0x2U)
#define EMVSIM_CTRL_ICM_SHIFT (1U)
/*! ICM - Initial Character Mode
* 0b0..Initial Character Mode disabled
* 0b1..Initial Character Mode enabled
*/
#define EMVSIM_CTRL_ICM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ICM_SHIFT)) & EMVSIM_CTRL_ICM_MASK)
#define EMVSIM_CTRL_ANACK_MASK (0x4U)
#define EMVSIM_CTRL_ANACK_SHIFT (2U)
/*! ANACK - Auto NACK Enable
* 0b0..NACK generation on errors disabled
* 0b1..NACK generation on errors enabled
*/
#define EMVSIM_CTRL_ANACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ANACK_SHIFT)) & EMVSIM_CTRL_ANACK_MASK)
#define EMVSIM_CTRL_ONACK_MASK (0x8U)
#define EMVSIM_CTRL_ONACK_SHIFT (3U)
/*! ONACK - Overrun NACK Enable
* 0b0..NACK generation on overrun is disabled
* 0b1..NACK generation on overrun is enabled
*/
#define EMVSIM_CTRL_ONACK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_ONACK_SHIFT)) & EMVSIM_CTRL_ONACK_MASK)
#define EMVSIM_CTRL_FLSH_RX_MASK (0x100U)
#define EMVSIM_CTRL_FLSH_RX_SHIFT (8U)
/*! FLSH_RX - Flush Receiver Bit
* 0b0..EMVSIM Receiver normal operation
* 0b1..EMVSIM Receiver held in Reset
*/
#define EMVSIM_CTRL_FLSH_RX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_RX_SHIFT)) & EMVSIM_CTRL_FLSH_RX_MASK)
#define EMVSIM_CTRL_FLSH_TX_MASK (0x200U)
#define EMVSIM_CTRL_FLSH_TX_SHIFT (9U)
/*! FLSH_TX - Flush Transmitter Bit
* 0b0..EMVSIM Transmitter normal operation
* 0b1..EMVSIM Transmitter held in Reset
*/
#define EMVSIM_CTRL_FLSH_TX(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_FLSH_TX_SHIFT)) & EMVSIM_CTRL_FLSH_TX_MASK)
#define EMVSIM_CTRL_SW_RST_MASK (0x400U)
#define EMVSIM_CTRL_SW_RST_SHIFT (10U)
/*! SW_RST - Software Reset Bit
* 0b0..EMVSIM Normal operation
* 0b1..EMVSIM held in Reset
*/
#define EMVSIM_CTRL_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_SW_RST_SHIFT)) & EMVSIM_CTRL_SW_RST_MASK)
#define EMVSIM_CTRL_KILL_CLOCKS_MASK (0x800U)
#define EMVSIM_CTRL_KILL_CLOCKS_SHIFT (11U)
/*! KILL_CLOCKS - Kill all internal clocks
* 0b0..EMVSIM input clock enabled
* 0b1..EMVSIM input clock is disabled
*/
#define EMVSIM_CTRL_KILL_CLOCKS(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_KILL_CLOCKS_SHIFT)) & EMVSIM_CTRL_KILL_CLOCKS_MASK)
#define EMVSIM_CTRL_DOZE_EN_MASK (0x1000U)
#define EMVSIM_CTRL_DOZE_EN_SHIFT (12U)
/*! DOZE_EN - Doze Enable
* 0b0..DOZE instruction gates all internal EMVSIM clocks as well as the Smart Card clock when the transmit FIFO is empty
* 0b1..DOZE instruction has no effect on EMVSIM module
*/
#define EMVSIM_CTRL_DOZE_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_DOZE_EN_SHIFT)) & EMVSIM_CTRL_DOZE_EN_MASK)
#define EMVSIM_CTRL_STOP_EN_MASK (0x2000U)
#define EMVSIM_CTRL_STOP_EN_SHIFT (13U)
/*! STOP_EN - STOP Enable
* 0b0..STOP instruction shuts down all EMVSIM clocks
* 0b1..STOP instruction shuts down all clocks except for the Smart Card Clock (SCK) (clock provided to Smart Card)
*/
#define EMVSIM_CTRL_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_STOP_EN_SHIFT)) & EMVSIM_CTRL_STOP_EN_MASK)
#define EMVSIM_CTRL_RCV_EN_MASK (0x10000U)
#define EMVSIM_CTRL_RCV_EN_SHIFT (16U)
/*! RCV_EN - Receiver Enable
* 0b0..EMVSIM Receiver disabled
* 0b1..EMVSIM Receiver enabled
*/
#define EMVSIM_CTRL_RCV_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCV_EN_SHIFT)) & EMVSIM_CTRL_RCV_EN_MASK)
#define EMVSIM_CTRL_XMT_EN_MASK (0x20000U)
#define EMVSIM_CTRL_XMT_EN_SHIFT (17U)
/*! XMT_EN - Transmitter Enable
* 0b0..EMVSIM Transmitter disabled
* 0b1..EMVSIM Transmitter enabled
*/
#define EMVSIM_CTRL_XMT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_EN_SHIFT)) & EMVSIM_CTRL_XMT_EN_MASK)
#define EMVSIM_CTRL_RCVR_11_MASK (0x40000U)
#define EMVSIM_CTRL_RCVR_11_SHIFT (18U)
/*! RCVR_11 - Receiver 11 ETU Mode Enable
* 0b0..Receiver configured for 12 ETU operation mode
* 0b1..Receiver configured for 11 ETU operation mode
*/
#define EMVSIM_CTRL_RCVR_11(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RCVR_11_SHIFT)) & EMVSIM_CTRL_RCVR_11_MASK)
#define EMVSIM_CTRL_RX_DMA_EN_MASK (0x80000U)
#define EMVSIM_CTRL_RX_DMA_EN_SHIFT (19U)
/*! RX_DMA_EN - Receive DMA Enable
* 0b0..No DMA Read Request asserted for Receiver
* 0b1..DMA Read Request asserted for Receiver
*/
#define EMVSIM_CTRL_RX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_RX_DMA_EN_SHIFT)) & EMVSIM_CTRL_RX_DMA_EN_MASK)
#define EMVSIM_CTRL_TX_DMA_EN_MASK (0x100000U)
#define EMVSIM_CTRL_TX_DMA_EN_SHIFT (20U)
/*! TX_DMA_EN - Transmit DMA Enable
* 0b0..No DMA Write Request asserted for Transmitter
* 0b1..DMA Write Request asserted for Transmitter
*/
#define EMVSIM_CTRL_TX_DMA_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_TX_DMA_EN_SHIFT)) & EMVSIM_CTRL_TX_DMA_EN_MASK)
#define EMVSIM_CTRL_INV_CRC_VAL_MASK (0x1000000U)
#define EMVSIM_CTRL_INV_CRC_VAL_SHIFT (24U)
/*! INV_CRC_VAL - Invert bits in the CRC Output Value
* 0b0..Bits in CRC Output value are not inverted.
* 0b1..Bits in CRC Output value are inverted.
*/
#define EMVSIM_CTRL_INV_CRC_VAL(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_INV_CRC_VAL_SHIFT)) & EMVSIM_CTRL_INV_CRC_VAL_MASK)
#define EMVSIM_CTRL_CRC_OUT_FLIP_MASK (0x2000000U)
#define EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT (25U)
/*! CRC_OUT_FLIP - CRC Output Value Bit Reversal or Flip
* 0b0..Bits within the CRC output bytes are not reversed i.e. 15:0 remains 15:0
* 0b1..Bits within the CRC output bytes are reversed i.e. 15:0 becomes {8:15,0:7}
*/
#define EMVSIM_CTRL_CRC_OUT_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_OUT_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_OUT_FLIP_MASK)
#define EMVSIM_CTRL_CRC_IN_FLIP_MASK (0x4000000U)
#define EMVSIM_CTRL_CRC_IN_FLIP_SHIFT (26U)
/*! CRC_IN_FLIP - CRC Input Byte's Bit Reversal or Flip Control
* 0b0..Bits in the input byte are not reversed (i.e. 7:0 remain 7:0) before the CRC calculation
* 0b1..Bits in the input byte are reversed (i.e. 7:0 becomes 0:7) before CRC calculation
*/
#define EMVSIM_CTRL_CRC_IN_FLIP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_IN_FLIP_SHIFT)) & EMVSIM_CTRL_CRC_IN_FLIP_MASK)
#define EMVSIM_CTRL_CWT_EN_MASK (0x8000000U)
#define EMVSIM_CTRL_CWT_EN_SHIFT (27U)
/*! CWT_EN - Character Wait Time Counter Enable
* 0b0..Character Wait time Counter is disabled
* 0b1..Character Wait time counter is enabled
*/
#define EMVSIM_CTRL_CWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CWT_EN_SHIFT)) & EMVSIM_CTRL_CWT_EN_MASK)
#define EMVSIM_CTRL_LRC_EN_MASK (0x10000000U)
#define EMVSIM_CTRL_LRC_EN_SHIFT (28U)
/*! LRC_EN - LRC Enable
* 0b0..8-bit Linear Redundancy Checking disabled
* 0b1..8-bit Linear Redundancy Checking enabled
*/
#define EMVSIM_CTRL_LRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_LRC_EN_SHIFT)) & EMVSIM_CTRL_LRC_EN_MASK)
#define EMVSIM_CTRL_CRC_EN_MASK (0x20000000U)
#define EMVSIM_CTRL_CRC_EN_SHIFT (29U)
/*! CRC_EN - CRC Enable
* 0b0..16-bit Cyclic Redundancy Checking disabled
* 0b1..16-bit Cyclic Redundancy Checking enabled
*/
#define EMVSIM_CTRL_CRC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_CRC_EN_SHIFT)) & EMVSIM_CTRL_CRC_EN_MASK)
#define EMVSIM_CTRL_XMT_CRC_LRC_MASK (0x40000000U)
#define EMVSIM_CTRL_XMT_CRC_LRC_SHIFT (30U)
/*! XMT_CRC_LRC - Transmit CRC or LRC Enable
* 0b0..No CRC or LRC value is transmitted
* 0b1..Transmit LRC or CRC info when FIFO empties (whichever is enabled)
*/
#define EMVSIM_CTRL_XMT_CRC_LRC(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_XMT_CRC_LRC_SHIFT)) & EMVSIM_CTRL_XMT_CRC_LRC_MASK)
#define EMVSIM_CTRL_BWT_EN_MASK (0x80000000U)
#define EMVSIM_CTRL_BWT_EN_SHIFT (31U)
/*! BWT_EN - Block Wait Time Counter Enable
* 0b0..Disable BWT, BGT Counters
* 0b1..Enable BWT, BGT Counters
*/
#define EMVSIM_CTRL_BWT_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CTRL_BWT_EN_SHIFT)) & EMVSIM_CTRL_BWT_EN_MASK)
/*! @} */
/*! @name INT_MASK - Interrupt Mask Register */
/*! @{ */
#define EMVSIM_INT_MASK_RDT_IM_MASK (0x1U)
#define EMVSIM_INT_MASK_RDT_IM_SHIFT (0U)
/*! RDT_IM - Receive Data Threshold Interrupt Mask
* 0b0..RDTF interrupt enabled
* 0b1..RDTF interrupt masked
*/
#define EMVSIM_INT_MASK_RDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RDT_IM_SHIFT)) & EMVSIM_INT_MASK_RDT_IM_MASK)
#define EMVSIM_INT_MASK_TC_IM_MASK (0x2U)
#define EMVSIM_INT_MASK_TC_IM_SHIFT (1U)
/*! TC_IM - Transmit Complete Interrupt Mask
* 0b0..TCF interrupt enabled
* 0b1..TCF interrupt masked
*/
#define EMVSIM_INT_MASK_TC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TC_IM_SHIFT)) & EMVSIM_INT_MASK_TC_IM_MASK)
#define EMVSIM_INT_MASK_RFO_IM_MASK (0x4U)
#define EMVSIM_INT_MASK_RFO_IM_SHIFT (2U)
/*! RFO_IM - Receive FIFO Overflow Interrupt Mask
* 0b0..RFO interrupt enabled
* 0b1..RFO interrupt masked
*/
#define EMVSIM_INT_MASK_RFO_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RFO_IM_SHIFT)) & EMVSIM_INT_MASK_RFO_IM_MASK)
#define EMVSIM_INT_MASK_ETC_IM_MASK (0x8U)
#define EMVSIM_INT_MASK_ETC_IM_SHIFT (3U)
/*! ETC_IM - Early Transmit Complete Interrupt Mask
* 0b0..ETC interrupt enabled
* 0b1..ETC interrupt masked
*/
#define EMVSIM_INT_MASK_ETC_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_ETC_IM_SHIFT)) & EMVSIM_INT_MASK_ETC_IM_MASK)
#define EMVSIM_INT_MASK_TFE_IM_MASK (0x10U)
#define EMVSIM_INT_MASK_TFE_IM_SHIFT (4U)
/*! TFE_IM - Transmit FIFO Empty Interrupt Mask
* 0b0..TFE interrupt enabled
* 0b1..TFE interrupt masked
*/
#define EMVSIM_INT_MASK_TFE_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFE_IM_SHIFT)) & EMVSIM_INT_MASK_TFE_IM_MASK)
#define EMVSIM_INT_MASK_TNACK_IM_MASK (0x20U)
#define EMVSIM_INT_MASK_TNACK_IM_SHIFT (5U)
/*! TNACK_IM - Transmit NACK Threshold Interrupt Mask
* 0b0..TNTE interrupt enabled
* 0b1..TNTE interrupt masked
*/
#define EMVSIM_INT_MASK_TNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TNACK_IM_SHIFT)) & EMVSIM_INT_MASK_TNACK_IM_MASK)
#define EMVSIM_INT_MASK_TFF_IM_MASK (0x40U)
#define EMVSIM_INT_MASK_TFF_IM_SHIFT (6U)
/*! TFF_IM - Transmit FIFO Full Interrupt Mask
* 0b0..TFF interrupt enabled
* 0b1..TFF interrupt masked
*/
#define EMVSIM_INT_MASK_TFF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TFF_IM_SHIFT)) & EMVSIM_INT_MASK_TFF_IM_MASK)
#define EMVSIM_INT_MASK_TDT_IM_MASK (0x80U)
#define EMVSIM_INT_MASK_TDT_IM_SHIFT (7U)
/*! TDT_IM - Transmit Data Threshold Interrupt Mask
* 0b0..TDTF interrupt enabled
* 0b1..TDTF interrupt masked
*/
#define EMVSIM_INT_MASK_TDT_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_TDT_IM_SHIFT)) & EMVSIM_INT_MASK_TDT_IM_MASK)
#define EMVSIM_INT_MASK_GPCNT0_IM_MASK (0x100U)
#define EMVSIM_INT_MASK_GPCNT0_IM_SHIFT (8U)
/*! GPCNT0_IM - General Purpose Timer 0 Timeout Interrupt Mask
* 0b0..GPCNT0_TO interrupt enabled
* 0b1..GPCNT0_TO interrupt masked
*/
#define EMVSIM_INT_MASK_GPCNT0_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT0_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT0_IM_MASK)
#define EMVSIM_INT_MASK_CWT_ERR_IM_MASK (0x200U)
#define EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT (9U)
/*! CWT_ERR_IM - Character Wait Time Error Interrupt Mask
* 0b0..CWT_ERR interrupt enabled
* 0b1..CWT_ERR interrupt masked
*/
#define EMVSIM_INT_MASK_CWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_CWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_CWT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_RNACK_IM_MASK (0x400U)
#define EMVSIM_INT_MASK_RNACK_IM_SHIFT (10U)
/*! RNACK_IM - Receiver NACK Threshold Interrupt Mask
* 0b0..RTE interrupt enabled
* 0b1..RTE interrupt masked
*/
#define EMVSIM_INT_MASK_RNACK_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RNACK_IM_SHIFT)) & EMVSIM_INT_MASK_RNACK_IM_MASK)
#define EMVSIM_INT_MASK_BWT_ERR_IM_MASK (0x800U)
#define EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT (11U)
/*! BWT_ERR_IM - Block Wait Time Error Interrupt Mask
* 0b0..BWT_ERR interrupt enabled
* 0b1..BWT_ERR interrupt masked
*/
#define EMVSIM_INT_MASK_BWT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BWT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BWT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_BGT_ERR_IM_MASK (0x1000U)
#define EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT (12U)
/*! BGT_ERR_IM - Block Guard Time Error Interrupt
* 0b0..BGT_ERR interrupt enabled
* 0b1..BGT_ERR interrupt masked
*/
#define EMVSIM_INT_MASK_BGT_ERR_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_BGT_ERR_IM_SHIFT)) & EMVSIM_INT_MASK_BGT_ERR_IM_MASK)
#define EMVSIM_INT_MASK_GPCNT1_IM_MASK (0x2000U)
#define EMVSIM_INT_MASK_GPCNT1_IM_SHIFT (13U)
/*! GPCNT1_IM - General Purpose Counter 1 Timeout Interrupt Mask
* 0b0..GPCNT1_TO interrupt enabled
* 0b1..GPCNT1_TO interrupt masked
*/
#define EMVSIM_INT_MASK_GPCNT1_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_GPCNT1_IM_SHIFT)) & EMVSIM_INT_MASK_GPCNT1_IM_MASK)
#define EMVSIM_INT_MASK_RX_DATA_IM_MASK (0x4000U)
#define EMVSIM_INT_MASK_RX_DATA_IM_SHIFT (14U)
/*! RX_DATA_IM - Receive Data Interrupt Mask
* 0b0..RX_DATA interrupt enabled
* 0b1..RX_DATA interrupt masked
*/
#define EMVSIM_INT_MASK_RX_DATA_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_RX_DATA_IM_SHIFT)) & EMVSIM_INT_MASK_RX_DATA_IM_MASK)
#define EMVSIM_INT_MASK_PEF_IM_MASK (0x8000U)
#define EMVSIM_INT_MASK_PEF_IM_SHIFT (15U)
/*! PEF_IM - Parity Error Interrupt Mask
* 0b0..PEF interrupt enabled
* 0b1..PEF interrupt masked
*/
#define EMVSIM_INT_MASK_PEF_IM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_INT_MASK_PEF_IM_SHIFT)) & EMVSIM_INT_MASK_PEF_IM_MASK)
/*! @} */
/*! @name RX_THD - Receiver Threshold Register */
/*! @{ */
#define EMVSIM_RX_THD_RDT_MASK (0xFU)
#define EMVSIM_RX_THD_RDT_SHIFT (0U)
/*! RDT - Receiver Data Threshold Value
*/
#define EMVSIM_RX_THD_RDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RDT_SHIFT)) & EMVSIM_RX_THD_RDT_MASK)
#define EMVSIM_RX_THD_RNCK_THD_MASK (0xF00U)
#define EMVSIM_RX_THD_RNCK_THD_SHIFT (8U)
/*! RNCK_THD - Receiver NACK Threshold Value
*/
#define EMVSIM_RX_THD_RNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_THD_RNCK_THD_SHIFT)) & EMVSIM_RX_THD_RNCK_THD_MASK)
/*! @} */
/*! @name TX_THD - Transmitter Threshold Register */
/*! @{ */
#define EMVSIM_TX_THD_TDT_MASK (0xFU)
#define EMVSIM_TX_THD_TDT_SHIFT (0U)
/*! TDT - Transmitter Data Threshold Value
*/
#define EMVSIM_TX_THD_TDT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TDT_SHIFT)) & EMVSIM_TX_THD_TDT_MASK)
#define EMVSIM_TX_THD_TNCK_THD_MASK (0xF00U)
#define EMVSIM_TX_THD_TNCK_THD_SHIFT (8U)
/*! TNCK_THD - Transmitter NACK Threshold Value
*/
#define EMVSIM_TX_THD_TNCK_THD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_THD_TNCK_THD_SHIFT)) & EMVSIM_TX_THD_TNCK_THD_MASK)
/*! @} */
/*! @name RX_STATUS - Receive Status Register */
/*! @{ */
#define EMVSIM_RX_STATUS_RFO_MASK (0x1U)
#define EMVSIM_RX_STATUS_RFO_SHIFT (0U)
/*! RFO - Receive FIFO Overflow Flag
* 0b0..No overrun error has occurred
* 0b1..A byte was received when the received FIFO was already full
*/
#define EMVSIM_RX_STATUS_RFO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RFO_SHIFT)) & EMVSIM_RX_STATUS_RFO_MASK)
#define EMVSIM_RX_STATUS_RX_DATA_MASK (0x10U)
#define EMVSIM_RX_STATUS_RX_DATA_SHIFT (4U)
/*! RX_DATA - Receive Data Interrupt Flag
* 0b0..No new byte is received
* 0b1..New byte is received ans stored in Receive FIFO
*/
#define EMVSIM_RX_STATUS_RX_DATA(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_DATA_SHIFT)) & EMVSIM_RX_STATUS_RX_DATA_MASK)
#define EMVSIM_RX_STATUS_RDTF_MASK (0x20U)
#define EMVSIM_RX_STATUS_RDTF_SHIFT (5U)
/*! RDTF - Receive Data Threshold Interrupt Flag
* 0b0..Number of unread bytes in receive FIFO less than the value set by RDT
* 0b1..Number of unread bytes in receive FIFO greater or than equal to value set by RDT.
*/
#define EMVSIM_RX_STATUS_RDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RDTF_SHIFT)) & EMVSIM_RX_STATUS_RDTF_MASK)
#define EMVSIM_RX_STATUS_LRC_OK_MASK (0x40U)
#define EMVSIM_RX_STATUS_LRC_OK_SHIFT (6U)
/*! LRC_OK - LRC Check OK Flag
* 0b0..Current LRC value does not match remainder.
* 0b1..Current calculated LRC value matches the expected result (i.e. zero).
*/
#define EMVSIM_RX_STATUS_LRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_LRC_OK_SHIFT)) & EMVSIM_RX_STATUS_LRC_OK_MASK)
#define EMVSIM_RX_STATUS_CRC_OK_MASK (0x80U)
#define EMVSIM_RX_STATUS_CRC_OK_SHIFT (7U)
/*! CRC_OK - CRC Check OK Flag
* 0b0..Current CRC value does not match remainder.
* 0b1..Current calculated CRC value matches the expected result.
*/
#define EMVSIM_RX_STATUS_CRC_OK(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CRC_OK_SHIFT)) & EMVSIM_RX_STATUS_CRC_OK_MASK)
#define EMVSIM_RX_STATUS_CWT_ERR_MASK (0x100U)
#define EMVSIM_RX_STATUS_CWT_ERR_SHIFT (8U)
/*! CWT_ERR - Character Wait Time Error Flag
* 0b0..No CWT violation has occurred
* 0b1..Time between two consecutive characters has exceeded the value in CWT_VAL.
*/
#define EMVSIM_RX_STATUS_CWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_CWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_CWT_ERR_MASK)
#define EMVSIM_RX_STATUS_RTE_MASK (0x200U)
#define EMVSIM_RX_STATUS_RTE_SHIFT (9U)
/*! RTE - Received NACK Threshold Error Flag
* 0b0..Number of NACKs generated by the receiver is less than the value programmed in RNCK_THD
* 0b1..Number of NACKs generated by the receiver is equal to the value programmed in RNCK_THD
*/
#define EMVSIM_RX_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RTE_SHIFT)) & EMVSIM_RX_STATUS_RTE_MASK)
#define EMVSIM_RX_STATUS_BWT_ERR_MASK (0x400U)
#define EMVSIM_RX_STATUS_BWT_ERR_SHIFT (10U)
/*! BWT_ERR - Block Wait Time Error Flag
* 0b0..Block wait time not exceeded
* 0b1..Block wait time was exceeded
*/
#define EMVSIM_RX_STATUS_BWT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BWT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BWT_ERR_MASK)
#define EMVSIM_RX_STATUS_BGT_ERR_MASK (0x800U)
#define EMVSIM_RX_STATUS_BGT_ERR_SHIFT (11U)
/*! BGT_ERR - Block Guard Time Error Flag
* 0b0..Block guard time was sufficient
* 0b1..Block guard time was too small
*/
#define EMVSIM_RX_STATUS_BGT_ERR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_BGT_ERR_SHIFT)) & EMVSIM_RX_STATUS_BGT_ERR_MASK)
#define EMVSIM_RX_STATUS_PEF_MASK (0x1000U)
#define EMVSIM_RX_STATUS_PEF_SHIFT (12U)
/*! PEF - Parity Error Flag
* 0b0..No parity error detected
* 0b1..Parity error detected
*/
#define EMVSIM_RX_STATUS_PEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_PEF_SHIFT)) & EMVSIM_RX_STATUS_PEF_MASK)
#define EMVSIM_RX_STATUS_FEF_MASK (0x2000U)
#define EMVSIM_RX_STATUS_FEF_SHIFT (13U)
/*! FEF - Frame Error Flag
* 0b0..No frame error detected
* 0b1..Frame error detected
*/
#define EMVSIM_RX_STATUS_FEF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_FEF_SHIFT)) & EMVSIM_RX_STATUS_FEF_MASK)
#define EMVSIM_RX_STATUS_RX_WPTR_MASK (0xF0000U)
#define EMVSIM_RX_STATUS_RX_WPTR_SHIFT (16U)
/*! RX_WPTR - Receive FIFO Write Pointer Value
*/
#define EMVSIM_RX_STATUS_RX_WPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_WPTR_SHIFT)) & EMVSIM_RX_STATUS_RX_WPTR_MASK)
#define EMVSIM_RX_STATUS_RX_CNT_MASK (0xF000000U)
#define EMVSIM_RX_STATUS_RX_CNT_SHIFT (24U)
/*! RX_CNT - Receive FIFO Byte Count
* 0b0000..FIFO is emtpy
*/
#define EMVSIM_RX_STATUS_RX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_STATUS_RX_CNT_SHIFT)) & EMVSIM_RX_STATUS_RX_CNT_MASK)
/*! @} */
/*! @name TX_STATUS - Transmitter Status Register */
/*! @{ */
#define EMVSIM_TX_STATUS_TNTE_MASK (0x1U)
#define EMVSIM_TX_STATUS_TNTE_SHIFT (0U)
/*! TNTE - Transmit NACK Threshold Error Flag
* 0b0..Transmit NACK threshold has not been reached
* 0b1..Transmit NACK threshold reached; transmitter frozen
*/
#define EMVSIM_TX_STATUS_TNTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TNTE_SHIFT)) & EMVSIM_TX_STATUS_TNTE_MASK)
#define EMVSIM_TX_STATUS_TFE_MASK (0x8U)
#define EMVSIM_TX_STATUS_TFE_SHIFT (3U)
/*! TFE - Transmit FIFO Empty Flag
* 0b0..Transmit FIFO is not empty
* 0b1..Transmit FIFO is empty
*/
#define EMVSIM_TX_STATUS_TFE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFE_SHIFT)) & EMVSIM_TX_STATUS_TFE_MASK)
#define EMVSIM_TX_STATUS_ETCF_MASK (0x10U)
#define EMVSIM_TX_STATUS_ETCF_SHIFT (4U)
/*! ETCF - Early Transmit Complete Flag
* 0b0..Transmit pending or in progress
* 0b1..Transmit complete
*/
#define EMVSIM_TX_STATUS_ETCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_ETCF_SHIFT)) & EMVSIM_TX_STATUS_ETCF_MASK)
#define EMVSIM_TX_STATUS_TCF_MASK (0x20U)
#define EMVSIM_TX_STATUS_TCF_SHIFT (5U)
/*! TCF - Transmit Complete Flag
* 0b0..Transmit pending or in progress
* 0b1..Transmit complete
*/
#define EMVSIM_TX_STATUS_TCF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TCF_SHIFT)) & EMVSIM_TX_STATUS_TCF_MASK)
#define EMVSIM_TX_STATUS_TFF_MASK (0x40U)
#define EMVSIM_TX_STATUS_TFF_SHIFT (6U)
/*! TFF - Transmit FIFO Full Flag
* 0b0..Transmit FIFO Full condition has not occurred
* 0b1..A Transmit FIFO Full condition has occurred
*/
#define EMVSIM_TX_STATUS_TFF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TFF_SHIFT)) & EMVSIM_TX_STATUS_TFF_MASK)
#define EMVSIM_TX_STATUS_TDTF_MASK (0x80U)
#define EMVSIM_TX_STATUS_TDTF_SHIFT (7U)
/*! TDTF - Transmit Data Threshold Flag
* 0b0..Number of bytes in FIFO is greater than TDT, or bit has been cleared
* 0b1..Number of bytes in FIFO is less than or equal to TDT
*/
#define EMVSIM_TX_STATUS_TDTF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TDTF_SHIFT)) & EMVSIM_TX_STATUS_TDTF_MASK)
#define EMVSIM_TX_STATUS_GPCNT0_TO_MASK (0x100U)
#define EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT (8U)
/*! GPCNT0_TO - General Purpose Counter 0 Timeout Flag
* 0b0..GPCNT0 time not reached, or bit has been cleared.
* 0b1..General Purpose counter has reached the GPCNT0 value
*/
#define EMVSIM_TX_STATUS_GPCNT0_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT0_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT0_TO_MASK)
#define EMVSIM_TX_STATUS_GPCNT1_TO_MASK (0x200U)
#define EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT (9U)
/*! GPCNT1_TO - General Purpose Counter 1 Timeout Flag
* 0b0..GPCNT1 time not reached, or bit has been cleared.
* 0b1..General Purpose counter has reached the GPCNT1 value
*/
#define EMVSIM_TX_STATUS_GPCNT1_TO(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_GPCNT1_TO_SHIFT)) & EMVSIM_TX_STATUS_GPCNT1_TO_MASK)
#define EMVSIM_TX_STATUS_TX_RPTR_MASK (0xF0000U)
#define EMVSIM_TX_STATUS_TX_RPTR_SHIFT (16U)
/*! TX_RPTR - Transmit FIFO Read Pointer
*/
#define EMVSIM_TX_STATUS_TX_RPTR(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_RPTR_SHIFT)) & EMVSIM_TX_STATUS_TX_RPTR_MASK)
#define EMVSIM_TX_STATUS_TX_CNT_MASK (0xF000000U)
#define EMVSIM_TX_STATUS_TX_CNT_SHIFT (24U)
/*! TX_CNT - Transmit FIFO Byte Count
* 0b0000..FIFO is emtpy
*/
#define EMVSIM_TX_STATUS_TX_CNT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_STATUS_TX_CNT_SHIFT)) & EMVSIM_TX_STATUS_TX_CNT_MASK)
/*! @} */
/*! @name PCSR - Port Control and Status Register */
/*! @{ */
#define EMVSIM_PCSR_SAPD_MASK (0x1U)
#define EMVSIM_PCSR_SAPD_SHIFT (0U)
/*! SAPD - Auto Power Down Enable
* 0b0..Auto power down disabled
* 0b1..Auto power down enabled
*/
#define EMVSIM_PCSR_SAPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SAPD_SHIFT)) & EMVSIM_PCSR_SAPD_MASK)
#define EMVSIM_PCSR_SVCC_EN_MASK (0x2U)
#define EMVSIM_PCSR_SVCC_EN_SHIFT (1U)
/*! SVCC_EN - Vcc Enable for Smart Card
* 0b0..Smart Card Voltage disabled
* 0b1..Smart Card Voltage enabled
*/
#define EMVSIM_PCSR_SVCC_EN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SVCC_EN_SHIFT)) & EMVSIM_PCSR_SVCC_EN_MASK)
#define EMVSIM_PCSR_VCCENP_MASK (0x4U)
#define EMVSIM_PCSR_VCCENP_SHIFT (2U)
/*! VCCENP - VCC Enable Polarity Control
* 0b0..SVCC_EN is active high. Polarity of SVCC_EN is unchanged.
* 0b1..SVCC_EN is active low. Polarity of SVCC_EN is inverted.
*/
#define EMVSIM_PCSR_VCCENP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_VCCENP_SHIFT)) & EMVSIM_PCSR_VCCENP_MASK)
#define EMVSIM_PCSR_SRST_MASK (0x8U)
#define EMVSIM_PCSR_SRST_SHIFT (3U)
/*! SRST - Reset to Smart Card
* 0b0..Smart Card Reset is asserted
* 0b1..Smart Card Reset is de-asserted
*/
#define EMVSIM_PCSR_SRST(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SRST_SHIFT)) & EMVSIM_PCSR_SRST_MASK)
#define EMVSIM_PCSR_SCEN_MASK (0x10U)
#define EMVSIM_PCSR_SCEN_SHIFT (4U)
/*! SCEN - Clock Enable for Smart Card
* 0b0..Smart Card Clock Disabled
* 0b1..Smart Card Clock Enabled
*/
#define EMVSIM_PCSR_SCEN(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCEN_SHIFT)) & EMVSIM_PCSR_SCEN_MASK)
#define EMVSIM_PCSR_SCSP_MASK (0x20U)
#define EMVSIM_PCSR_SCSP_SHIFT (5U)
/*! SCSP - Smart Card Clock Stop Polarity
* 0b0..Clock is logic 0 when stopped by SCEN
* 0b1..Clock is logic 1 when stopped by SCEN
*/
#define EMVSIM_PCSR_SCSP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SCSP_SHIFT)) & EMVSIM_PCSR_SCSP_MASK)
#define EMVSIM_PCSR_SPD_MASK (0x80U)
#define EMVSIM_PCSR_SPD_SHIFT (7U)
/*! SPD - Auto Power Down Control
* 0b0..No effect
* 0b1..Start Auto Powerdown or Power Down is in progress
*/
#define EMVSIM_PCSR_SPD(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPD_SHIFT)) & EMVSIM_PCSR_SPD_MASK)
#define EMVSIM_PCSR_SPDIM_MASK (0x1000000U)
#define EMVSIM_PCSR_SPDIM_SHIFT (24U)
/*! SPDIM - Smart Card Presence Detect Interrupt Mask
* 0b0..SIM presence detect interrupt is enabled
* 0b1..SIM presence detect interrupt is masked
*/
#define EMVSIM_PCSR_SPDIM(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIM_SHIFT)) & EMVSIM_PCSR_SPDIM_MASK)
#define EMVSIM_PCSR_SPDIF_MASK (0x2000000U)
#define EMVSIM_PCSR_SPDIF_SHIFT (25U)
/*! SPDIF - Smart Card Presence Detect Interrupt Flag
* 0b0..No insertion or removal of Smart Card detected on Port
* 0b1..Insertion or removal of Smart Card detected on Port
*/
#define EMVSIM_PCSR_SPDIF(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDIF_SHIFT)) & EMVSIM_PCSR_SPDIF_MASK)
#define EMVSIM_PCSR_SPDP_MASK (0x4000000U)
#define EMVSIM_PCSR_SPDP_SHIFT (26U)
/*! SPDP - Smart Card Presence Detect Pin Status
* 0b0..SIM Presence Detect pin is logic low
* 0b1..SIM Presence Detectpin is logic high
*/
#define EMVSIM_PCSR_SPDP(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDP_SHIFT)) & EMVSIM_PCSR_SPDP_MASK)
#define EMVSIM_PCSR_SPDES_MASK (0x8000000U)
#define EMVSIM_PCSR_SPDES_SHIFT (27U)
/*! SPDES - SIM Presence Detect Edge Select
* 0b0..Falling edge on the pin
* 0b1..Rising edge on the pin
*/
#define EMVSIM_PCSR_SPDES(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_PCSR_SPDES_SHIFT)) & EMVSIM_PCSR_SPDES_MASK)
/*! @} */
/*! @name RX_BUF - Receive Data Read Buffer */
/*! @{ */
#define EMVSIM_RX_BUF_RX_BYTE_MASK (0xFFU)
#define EMVSIM_RX_BUF_RX_BYTE_SHIFT (0U)
/*! RX_BYTE - Receive Data Byte Read
*/
#define EMVSIM_RX_BUF_RX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_RX_BUF_RX_BYTE_SHIFT)) & EMVSIM_RX_BUF_RX_BYTE_MASK)
/*! @} */
/*! @name TX_BUF - Transmit Data Buffer */
/*! @{ */
#define EMVSIM_TX_BUF_TX_BYTE_MASK (0xFFU)
#define EMVSIM_TX_BUF_TX_BYTE_SHIFT (0U)
/*! TX_BYTE - Transmit Data Byte
*/
#define EMVSIM_TX_BUF_TX_BYTE(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_BUF_TX_BYTE_SHIFT)) & EMVSIM_TX_BUF_TX_BYTE_MASK)
/*! @} */
/*! @name TX_GETU - Transmitter Guard ETU Value Register */
/*! @{ */
#define EMVSIM_TX_GETU_GETU_MASK (0xFFU)
#define EMVSIM_TX_GETU_GETU_SHIFT (0U)
/*! GETU - Transmitter Guard Time Value in ETU
*/
#define EMVSIM_TX_GETU_GETU(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_TX_GETU_GETU_SHIFT)) & EMVSIM_TX_GETU_GETU_MASK)
/*! @} */
/*! @name CWT_VAL - Character Wait Time Value Register */
/*! @{ */
#define EMVSIM_CWT_VAL_CWT_MASK (0xFFFFU)
#define EMVSIM_CWT_VAL_CWT_SHIFT (0U)
/*! CWT - Character Wait Time Value
*/
#define EMVSIM_CWT_VAL_CWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_CWT_VAL_CWT_SHIFT)) & EMVSIM_CWT_VAL_CWT_MASK)
/*! @} */
/*! @name BWT_VAL - Block Wait Time Value Register */
/*! @{ */
#define EMVSIM_BWT_VAL_BWT_MASK (0xFFFFFFFFU)
#define EMVSIM_BWT_VAL_BWT_SHIFT (0U)
/*! BWT - Block Wait Time Value
*/
#define EMVSIM_BWT_VAL_BWT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BWT_VAL_BWT_SHIFT)) & EMVSIM_BWT_VAL_BWT_MASK)
/*! @} */
/*! @name BGT_VAL - Block Guard Time Value Register */
/*! @{ */
#define EMVSIM_BGT_VAL_BGT_MASK (0xFFFFU)
#define EMVSIM_BGT_VAL_BGT_SHIFT (0U)
/*! BGT - Block Guard Time Value
*/
#define EMVSIM_BGT_VAL_BGT(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_BGT_VAL_BGT_SHIFT)) & EMVSIM_BGT_VAL_BGT_MASK)
/*! @} */
/*! @name GPCNT0_VAL - General Purpose Counter 0 Timeout Value Register */
/*! @{ */
#define EMVSIM_GPCNT0_VAL_GPCNT0_MASK (0xFFFFU)
#define EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT (0U)
/*! GPCNT0 - General Purpose Counter 0 Timeout Value
*/
#define EMVSIM_GPCNT0_VAL_GPCNT0(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT0_VAL_GPCNT0_SHIFT)) & EMVSIM_GPCNT0_VAL_GPCNT0_MASK)
/*! @} */
/*! @name GPCNT1_VAL - General Purpose Counter 1 Timeout Value */
/*! @{ */
#define EMVSIM_GPCNT1_VAL_GPCNT1_MASK (0xFFFFU)
#define EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT (0U)
/*! GPCNT1 - General Purpose Counter 1 Timeout Value
*/
#define EMVSIM_GPCNT1_VAL_GPCNT1(x) (((uint32_t)(((uint32_t)(x)) << EMVSIM_GPCNT1_VAL_GPCNT1_SHIFT)) & EMVSIM_GPCNT1_VAL_GPCNT1_MASK)
/*! @} */
/*!
* @}
*/ /* end of group EMVSIM_Register_Masks */
/* EMVSIM - Peripheral instance base addresses */
/** Peripheral EMVSIM1 base address */
#define EMVSIM1_BASE (0x40154000u)
/** Peripheral EMVSIM1 base pointer */
#define EMVSIM1 ((EMVSIM_Type *)EMVSIM1_BASE)
/** Peripheral EMVSIM2 base address */
#define EMVSIM2_BASE (0x40158000u)
/** Peripheral EMVSIM2 base pointer */
#define EMVSIM2 ((EMVSIM_Type *)EMVSIM2_BASE)
/** Array initializer of EMVSIM peripheral base addresses */
#define EMVSIM_BASE_ADDRS { 0u, EMVSIM1_BASE, EMVSIM2_BASE }
/** Array initializer of EMVSIM peripheral base pointers */
#define EMVSIM_BASE_PTRS { (EMVSIM_Type *)0u, EMVSIM1, EMVSIM2 }
/** Interrupt vectors for the EMVSIM peripheral type */
#define EMVSIM_IRQS { NotAvail_IRQn, EMVSIM1_IRQn, EMVSIM2_IRQn }
/*!
* @}
*/ /* end of group EMVSIM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ENC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENC_Peripheral_Access_Layer ENC Peripheral Access Layer
* @{
*/
/** ENC - Register Layout Typedef */
typedef struct {
__IO uint16_t CTRL; /**< Control Register, offset: 0x0 */
__IO uint16_t FILT; /**< Input Filter Register, offset: 0x2 */
__IO uint16_t WTR; /**< Watchdog Timeout Register, offset: 0x4 */
__IO uint16_t POSD; /**< Position Difference Counter Register, offset: 0x6 */
__I uint16_t POSDH; /**< Position Difference Hold Register, offset: 0x8 */
__IO uint16_t REV; /**< Revolution Counter Register, offset: 0xA */
__I uint16_t REVH; /**< Revolution Hold Register, offset: 0xC */
__IO uint16_t UPOS; /**< Upper Position Counter Register, offset: 0xE */
__IO uint16_t LPOS; /**< Lower Position Counter Register, offset: 0x10 */
__I uint16_t UPOSH; /**< Upper Position Hold Register, offset: 0x12 */
__I uint16_t LPOSH; /**< Lower Position Hold Register, offset: 0x14 */
__IO uint16_t UINIT; /**< Upper Initialization Register, offset: 0x16 */
__IO uint16_t LINIT; /**< Lower Initialization Register, offset: 0x18 */
__I uint16_t IMR; /**< Input Monitor Register, offset: 0x1A */
__IO uint16_t TST; /**< Test Register, offset: 0x1C */
__IO uint16_t CTRL2; /**< Control 2 Register, offset: 0x1E */
__IO uint16_t UMOD; /**< Upper Modulus Register, offset: 0x20 */
__IO uint16_t LMOD; /**< Lower Modulus Register, offset: 0x22 */
__IO uint16_t UCOMP; /**< Upper Position Compare Register, offset: 0x24 */
__IO uint16_t LCOMP; /**< Lower Position Compare Register, offset: 0x26 */
__I uint16_t LASTEDGE; /**< Last Edge Time Register, offset: 0x28 */
__I uint16_t LASTEDGEH; /**< Last Edge Time Hold Register, offset: 0x2A */
__I uint16_t POSDPER; /**< Position Difference Period Counter Register, offset: 0x2C */
__I uint16_t POSDPERBFR; /**< Position Difference Period Buffer Register, offset: 0x2E */
__I uint16_t POSDPERH; /**< Position Difference Period Hold Register, offset: 0x30 */
__IO uint16_t CTRL3; /**< Control 3 Register, offset: 0x32 */
} ENC_Type;
/* ----------------------------------------------------------------------------
-- ENC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENC_Register_Masks ENC Register Masks
* @{
*/
/*! @name CTRL - Control Register */
/*! @{ */
#define ENC_CTRL_CMPIE_MASK (0x1U)
#define ENC_CTRL_CMPIE_SHIFT (0U)
/*! CMPIE - Compare Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define ENC_CTRL_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIE_SHIFT)) & ENC_CTRL_CMPIE_MASK)
#define ENC_CTRL_CMPIRQ_MASK (0x2U)
#define ENC_CTRL_CMPIRQ_SHIFT (1U)
/*! CMPIRQ - Compare Interrupt Request
* 0b0..No match has occurred (the counter does not match the COMP value)
* 0b1..COMP match has occurred (the counter matches the COMP value)
*/
#define ENC_CTRL_CMPIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_CMPIRQ_SHIFT)) & ENC_CTRL_CMPIRQ_MASK)
#define ENC_CTRL_WDE_MASK (0x4U)
#define ENC_CTRL_WDE_SHIFT (2U)
/*! WDE - Watchdog Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define ENC_CTRL_WDE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_WDE_SHIFT)) & ENC_CTRL_WDE_MASK)
#define ENC_CTRL_DIE_MASK (0x8U)
#define ENC_CTRL_DIE_SHIFT (3U)
/*! DIE - Watchdog Timeout Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define ENC_CTRL_DIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIE_SHIFT)) & ENC_CTRL_DIE_MASK)
#define ENC_CTRL_DIRQ_MASK (0x10U)
#define ENC_CTRL_DIRQ_SHIFT (4U)
/*! DIRQ - Watchdog Timeout Interrupt Request
* 0b0..No Watchdog timeout interrupt has occurred
* 0b1..Watchdog timeout interrupt has occurred
*/
#define ENC_CTRL_DIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_DIRQ_SHIFT)) & ENC_CTRL_DIRQ_MASK)
#define ENC_CTRL_XNE_MASK (0x20U)
#define ENC_CTRL_XNE_SHIFT (5U)
/*! XNE - Use Negative Edge of INDEX Pulse
* 0b0..Use positive edge of INDEX pulse
* 0b1..Use negative edge of INDEX pulse
*/
#define ENC_CTRL_XNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XNE_SHIFT)) & ENC_CTRL_XNE_MASK)
#define ENC_CTRL_XIP_MASK (0x40U)
#define ENC_CTRL_XIP_SHIFT (6U)
/*! XIP - INDEX Triggered Initialization of Position Counters UPOS and LPOS
* 0b0..INDEX pulse does not initialize the position counter
* 0b1..INDEX pulse initializes the position counter
*/
#define ENC_CTRL_XIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIP_SHIFT)) & ENC_CTRL_XIP_MASK)
#define ENC_CTRL_XIE_MASK (0x80U)
#define ENC_CTRL_XIE_SHIFT (7U)
/*! XIE - INDEX Pulse Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define ENC_CTRL_XIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIE_SHIFT)) & ENC_CTRL_XIE_MASK)
#define ENC_CTRL_XIRQ_MASK (0x100U)
#define ENC_CTRL_XIRQ_SHIFT (8U)
/*! XIRQ - INDEX Pulse Interrupt Request
* 0b0..INDEX pulse has not occurred
* 0b1..INDEX pulse has occurred
*/
#define ENC_CTRL_XIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_XIRQ_SHIFT)) & ENC_CTRL_XIRQ_MASK)
#define ENC_CTRL_PH1_MASK (0x200U)
#define ENC_CTRL_PH1_SHIFT (9U)
/*! PH1 - Enable Signal Phase Count Mode
* 0b0..Use the standard quadrature decoder, where PHASEA and PHASEB represent a two-phase quadrature signal.
* 0b1..Bypass the quadrature decoder. A positive transition of the PHASEA input generates a count signal. The
* PHASEB input and the REV bit control the counter direction: If CTRL[REV] = 0, PHASEB = 0, then count up If
* CTRL[REV] = 1, PHASEB = 1, then count up If CTRL[REV] = 0, PHASEB = 1, then count down If CTRL[REV] = 1,
* PHASEB = 0, then count down
*/
#define ENC_CTRL_PH1(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_PH1_SHIFT)) & ENC_CTRL_PH1_MASK)
#define ENC_CTRL_REV_MASK (0x400U)
#define ENC_CTRL_REV_SHIFT (10U)
/*! REV - Enable Reverse Direction Counting
* 0b0..Count normally
* 0b1..Count in the reverse direction
*/
#define ENC_CTRL_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_REV_SHIFT)) & ENC_CTRL_REV_MASK)
#define ENC_CTRL_SWIP_MASK (0x800U)
#define ENC_CTRL_SWIP_SHIFT (11U)
/*! SWIP - Software-Triggered Initialization of Position Counters UPOS and LPOS
* 0b0..No action
* 0b1..Initialize position counter (using upper and lower initialization registers, UINIT and LINIT)
*/
#define ENC_CTRL_SWIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_SWIP_SHIFT)) & ENC_CTRL_SWIP_MASK)
#define ENC_CTRL_HNE_MASK (0x1000U)
#define ENC_CTRL_HNE_SHIFT (12U)
/*! HNE - Use Negative Edge of HOME Input
* 0b0..Use positive-going edge-to-trigger initialization of position counters UPOS and LPOS
* 0b1..Use negative-going edge-to-trigger initialization of position counters UPOS and LPOS
*/
#define ENC_CTRL_HNE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HNE_SHIFT)) & ENC_CTRL_HNE_MASK)
#define ENC_CTRL_HIP_MASK (0x2000U)
#define ENC_CTRL_HIP_SHIFT (13U)
/*! HIP - Enable HOME to Initialize Position Counters UPOS and LPOS
* 0b0..No action
* 0b1..HOME signal initializes the position counter
*/
#define ENC_CTRL_HIP(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIP_SHIFT)) & ENC_CTRL_HIP_MASK)
#define ENC_CTRL_HIE_MASK (0x4000U)
#define ENC_CTRL_HIE_SHIFT (14U)
/*! HIE - HOME Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define ENC_CTRL_HIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIE_SHIFT)) & ENC_CTRL_HIE_MASK)
#define ENC_CTRL_HIRQ_MASK (0x8000U)
#define ENC_CTRL_HIRQ_SHIFT (15U)
/*! HIRQ - HOME Signal Transition Interrupt Request
* 0b0..No transition on the HOME signal has occurred
* 0b1..A transition on the HOME signal has occurred
*/
#define ENC_CTRL_HIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL_HIRQ_SHIFT)) & ENC_CTRL_HIRQ_MASK)
/*! @} */
/*! @name FILT - Input Filter Register */
/*! @{ */
#define ENC_FILT_FILT_PER_MASK (0xFFU)
#define ENC_FILT_FILT_PER_SHIFT (0U)
/*! FILT_PER - Input Filter Sample Period
*/
#define ENC_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PER_SHIFT)) & ENC_FILT_FILT_PER_MASK)
#define ENC_FILT_FILT_CNT_MASK (0x700U)
#define ENC_FILT_FILT_CNT_SHIFT (8U)
/*! FILT_CNT - Input Filter Sample Count
*/
#define ENC_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_CNT_SHIFT)) & ENC_FILT_FILT_CNT_MASK)
#define ENC_FILT_FILT_PRSC_MASK (0xE000U)
#define ENC_FILT_FILT_PRSC_SHIFT (13U)
/*! FILT_PRSC - prescaler divide IPbus clock to FILT clk
*/
#define ENC_FILT_FILT_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_FILT_FILT_PRSC_SHIFT)) & ENC_FILT_FILT_PRSC_MASK)
/*! @} */
/*! @name WTR - Watchdog Timeout Register */
/*! @{ */
#define ENC_WTR_WDOG_MASK (0xFFFFU)
#define ENC_WTR_WDOG_SHIFT (0U)
/*! WDOG - WDOG
*/
#define ENC_WTR_WDOG(x) (((uint16_t)(((uint16_t)(x)) << ENC_WTR_WDOG_SHIFT)) & ENC_WTR_WDOG_MASK)
/*! @} */
/*! @name POSD - Position Difference Counter Register */
/*! @{ */
#define ENC_POSD_POSD_MASK (0xFFFFU)
#define ENC_POSD_POSD_SHIFT (0U)
/*! POSD - POSD
*/
#define ENC_POSD_POSD(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSD_POSD_SHIFT)) & ENC_POSD_POSD_MASK)
/*! @} */
/*! @name POSDH - Position Difference Hold Register */
/*! @{ */
#define ENC_POSDH_POSDH_MASK (0xFFFFU)
#define ENC_POSDH_POSDH_SHIFT (0U)
/*! POSDH - POSDH
*/
#define ENC_POSDH_POSDH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDH_POSDH_SHIFT)) & ENC_POSDH_POSDH_MASK)
/*! @} */
/*! @name REV - Revolution Counter Register */
/*! @{ */
#define ENC_REV_REV_MASK (0xFFFFU)
#define ENC_REV_REV_SHIFT (0U)
/*! REV - REV
*/
#define ENC_REV_REV(x) (((uint16_t)(((uint16_t)(x)) << ENC_REV_REV_SHIFT)) & ENC_REV_REV_MASK)
/*! @} */
/*! @name REVH - Revolution Hold Register */
/*! @{ */
#define ENC_REVH_REVH_MASK (0xFFFFU)
#define ENC_REVH_REVH_SHIFT (0U)
/*! REVH - REVH
*/
#define ENC_REVH_REVH(x) (((uint16_t)(((uint16_t)(x)) << ENC_REVH_REVH_SHIFT)) & ENC_REVH_REVH_MASK)
/*! @} */
/*! @name UPOS - Upper Position Counter Register */
/*! @{ */
#define ENC_UPOS_POS_MASK (0xFFFFU)
#define ENC_UPOS_POS_SHIFT (0U)
/*! POS - POS
*/
#define ENC_UPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOS_POS_SHIFT)) & ENC_UPOS_POS_MASK)
/*! @} */
/*! @name LPOS - Lower Position Counter Register */
/*! @{ */
#define ENC_LPOS_POS_MASK (0xFFFFU)
#define ENC_LPOS_POS_SHIFT (0U)
/*! POS - POS
*/
#define ENC_LPOS_POS(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOS_POS_SHIFT)) & ENC_LPOS_POS_MASK)
/*! @} */
/*! @name UPOSH - Upper Position Hold Register */
/*! @{ */
#define ENC_UPOSH_POSH_MASK (0xFFFFU)
#define ENC_UPOSH_POSH_SHIFT (0U)
/*! POSH - POSH
*/
#define ENC_UPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_UPOSH_POSH_SHIFT)) & ENC_UPOSH_POSH_MASK)
/*! @} */
/*! @name LPOSH - Lower Position Hold Register */
/*! @{ */
#define ENC_LPOSH_POSH_MASK (0xFFFFU)
#define ENC_LPOSH_POSH_SHIFT (0U)
/*! POSH - POSH
*/
#define ENC_LPOSH_POSH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LPOSH_POSH_SHIFT)) & ENC_LPOSH_POSH_MASK)
/*! @} */
/*! @name UINIT - Upper Initialization Register */
/*! @{ */
#define ENC_UINIT_INIT_MASK (0xFFFFU)
#define ENC_UINIT_INIT_SHIFT (0U)
/*! INIT - INIT
*/
#define ENC_UINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_UINIT_INIT_SHIFT)) & ENC_UINIT_INIT_MASK)
/*! @} */
/*! @name LINIT - Lower Initialization Register */
/*! @{ */
#define ENC_LINIT_INIT_MASK (0xFFFFU)
#define ENC_LINIT_INIT_SHIFT (0U)
/*! INIT - INIT
*/
#define ENC_LINIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << ENC_LINIT_INIT_SHIFT)) & ENC_LINIT_INIT_MASK)
/*! @} */
/*! @name IMR - Input Monitor Register */
/*! @{ */
#define ENC_IMR_HOME_MASK (0x1U)
#define ENC_IMR_HOME_SHIFT (0U)
/*! HOME - HOME
*/
#define ENC_IMR_HOME(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_HOME_SHIFT)) & ENC_IMR_HOME_MASK)
#define ENC_IMR_INDEX_MASK (0x2U)
#define ENC_IMR_INDEX_SHIFT (1U)
/*! INDEX - INDEX
*/
#define ENC_IMR_INDEX(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_INDEX_SHIFT)) & ENC_IMR_INDEX_MASK)
#define ENC_IMR_PHB_MASK (0x4U)
#define ENC_IMR_PHB_SHIFT (2U)
/*! PHB - PHB
*/
#define ENC_IMR_PHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHB_SHIFT)) & ENC_IMR_PHB_MASK)
#define ENC_IMR_PHA_MASK (0x8U)
#define ENC_IMR_PHA_SHIFT (3U)
/*! PHA - PHA
*/
#define ENC_IMR_PHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_PHA_SHIFT)) & ENC_IMR_PHA_MASK)
#define ENC_IMR_FHOM_MASK (0x10U)
#define ENC_IMR_FHOM_SHIFT (4U)
/*! FHOM - FHOM
*/
#define ENC_IMR_FHOM(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FHOM_SHIFT)) & ENC_IMR_FHOM_MASK)
#define ENC_IMR_FIND_MASK (0x20U)
#define ENC_IMR_FIND_SHIFT (5U)
/*! FIND - FIND
*/
#define ENC_IMR_FIND(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FIND_SHIFT)) & ENC_IMR_FIND_MASK)
#define ENC_IMR_FPHB_MASK (0x40U)
#define ENC_IMR_FPHB_SHIFT (6U)
/*! FPHB - FPHB
*/
#define ENC_IMR_FPHB(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHB_SHIFT)) & ENC_IMR_FPHB_MASK)
#define ENC_IMR_FPHA_MASK (0x80U)
#define ENC_IMR_FPHA_SHIFT (7U)
/*! FPHA - FPHA
*/
#define ENC_IMR_FPHA(x) (((uint16_t)(((uint16_t)(x)) << ENC_IMR_FPHA_SHIFT)) & ENC_IMR_FPHA_MASK)
/*! @} */
/*! @name TST - Test Register */
/*! @{ */
#define ENC_TST_TEST_COUNT_MASK (0xFFU)
#define ENC_TST_TEST_COUNT_SHIFT (0U)
/*! TEST_COUNT - TEST_COUNT
*/
#define ENC_TST_TEST_COUNT(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_COUNT_SHIFT)) & ENC_TST_TEST_COUNT_MASK)
#define ENC_TST_TEST_PERIOD_MASK (0x1F00U)
#define ENC_TST_TEST_PERIOD_SHIFT (8U)
/*! TEST_PERIOD - TEST_PERIOD
*/
#define ENC_TST_TEST_PERIOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEST_PERIOD_SHIFT)) & ENC_TST_TEST_PERIOD_MASK)
#define ENC_TST_QDN_MASK (0x2000U)
#define ENC_TST_QDN_SHIFT (13U)
/*! QDN - Quadrature Decoder Negative Signal
* 0b0..Generates a positive quadrature decoder signal
* 0b1..Generates a negative quadrature decoder signal
*/
#define ENC_TST_QDN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_QDN_SHIFT)) & ENC_TST_QDN_MASK)
#define ENC_TST_TCE_MASK (0x4000U)
#define ENC_TST_TCE_SHIFT (14U)
/*! TCE - Test Counter Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define ENC_TST_TCE(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TCE_SHIFT)) & ENC_TST_TCE_MASK)
#define ENC_TST_TEN_MASK (0x8000U)
#define ENC_TST_TEN_SHIFT (15U)
/*! TEN - Test Mode Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define ENC_TST_TEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_TST_TEN_SHIFT)) & ENC_TST_TEN_MASK)
/*! @} */
/*! @name CTRL2 - Control 2 Register */
/*! @{ */
#define ENC_CTRL2_UPDHLD_MASK (0x1U)
#define ENC_CTRL2_UPDHLD_SHIFT (0U)
/*! UPDHLD - Update Hold Registers
* 0b0..Disable updates of hold registers on the rising edge of TRIGGER input signal
* 0b1..Enable updates of hold registers on the rising edge of TRIGGER input signal
*/
#define ENC_CTRL2_UPDHLD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDHLD_SHIFT)) & ENC_CTRL2_UPDHLD_MASK)
#define ENC_CTRL2_UPDPOS_MASK (0x2U)
#define ENC_CTRL2_UPDPOS_SHIFT (1U)
/*! UPDPOS - Update Position Registers
* 0b0..No action for POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
* 0b1..Clear POSD, REV, UPOS and LPOS registers on rising edge of TRIGGER
*/
#define ENC_CTRL2_UPDPOS(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_UPDPOS_SHIFT)) & ENC_CTRL2_UPDPOS_MASK)
#define ENC_CTRL2_MOD_MASK (0x4U)
#define ENC_CTRL2_MOD_SHIFT (2U)
/*! MOD - Enable Modulo Counting
* 0b0..Disable modulo counting
* 0b1..Enable modulo counting
*/
#define ENC_CTRL2_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_MOD_SHIFT)) & ENC_CTRL2_MOD_MASK)
#define ENC_CTRL2_DIR_MASK (0x8U)
#define ENC_CTRL2_DIR_SHIFT (3U)
/*! DIR - Count Direction Flag
* 0b0..Last count was in the down direction
* 0b1..Last count was in the up direction
*/
#define ENC_CTRL2_DIR(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_DIR_SHIFT)) & ENC_CTRL2_DIR_MASK)
#define ENC_CTRL2_RUIE_MASK (0x10U)
#define ENC_CTRL2_RUIE_SHIFT (4U)
/*! RUIE - Roll-under Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define ENC_CTRL2_RUIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIE_SHIFT)) & ENC_CTRL2_RUIE_MASK)
#define ENC_CTRL2_RUIRQ_MASK (0x20U)
#define ENC_CTRL2_RUIRQ_SHIFT (5U)
/*! RUIRQ - Roll-under Interrupt Request
* 0b0..No roll-under has occurred
* 0b1..Roll-under has occurred
*/
#define ENC_CTRL2_RUIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_RUIRQ_SHIFT)) & ENC_CTRL2_RUIRQ_MASK)
#define ENC_CTRL2_ROIE_MASK (0x40U)
#define ENC_CTRL2_ROIE_SHIFT (6U)
/*! ROIE - Roll-over Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define ENC_CTRL2_ROIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIE_SHIFT)) & ENC_CTRL2_ROIE_MASK)
#define ENC_CTRL2_ROIRQ_MASK (0x80U)
#define ENC_CTRL2_ROIRQ_SHIFT (7U)
/*! ROIRQ - Roll-over Interrupt Request
* 0b0..No roll-over has occurred
* 0b1..Roll-over has occurred
*/
#define ENC_CTRL2_ROIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_ROIRQ_SHIFT)) & ENC_CTRL2_ROIRQ_MASK)
#define ENC_CTRL2_REVMOD_MASK (0x100U)
#define ENC_CTRL2_REVMOD_SHIFT (8U)
/*! REVMOD - Revolution Counter Modulus Enable
* 0b0..Use INDEX pulse to increment/decrement revolution counter (REV)
* 0b1..Use modulus counting roll-over/under to increment/decrement revolution counter (REV)
*/
#define ENC_CTRL2_REVMOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_REVMOD_SHIFT)) & ENC_CTRL2_REVMOD_MASK)
#define ENC_CTRL2_OUTCTL_MASK (0x200U)
#define ENC_CTRL2_OUTCTL_SHIFT (9U)
/*! OUTCTL - Output Control
* 0b0..POSMATCH pulses when a match occurs between the position counters (POS) and the corresponding compare value (COMP )
* 0b1..POSMATCH pulses when the UPOS, LPOS, REV, or POSD registers are read
*/
#define ENC_CTRL2_OUTCTL(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_OUTCTL_SHIFT)) & ENC_CTRL2_OUTCTL_MASK)
#define ENC_CTRL2_SABIE_MASK (0x400U)
#define ENC_CTRL2_SABIE_SHIFT (10U)
/*! SABIE - Simultaneous PHASEA and PHASEB Change Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define ENC_CTRL2_SABIE(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIE_SHIFT)) & ENC_CTRL2_SABIE_MASK)
#define ENC_CTRL2_SABIRQ_MASK (0x800U)
#define ENC_CTRL2_SABIRQ_SHIFT (11U)
/*! SABIRQ - Simultaneous PHASEA and PHASEB Change Interrupt Request
* 0b0..No simultaneous change of PHASEA and PHASEB has occurred
* 0b1..A simultaneous change of PHASEA and PHASEB has occurred
*/
#define ENC_CTRL2_SABIRQ(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL2_SABIRQ_SHIFT)) & ENC_CTRL2_SABIRQ_MASK)
/*! @} */
/*! @name UMOD - Upper Modulus Register */
/*! @{ */
#define ENC_UMOD_MOD_MASK (0xFFFFU)
#define ENC_UMOD_MOD_SHIFT (0U)
/*! MOD - MOD
*/
#define ENC_UMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_UMOD_MOD_SHIFT)) & ENC_UMOD_MOD_MASK)
/*! @} */
/*! @name LMOD - Lower Modulus Register */
/*! @{ */
#define ENC_LMOD_MOD_MASK (0xFFFFU)
#define ENC_LMOD_MOD_SHIFT (0U)
/*! MOD - MOD
*/
#define ENC_LMOD_MOD(x) (((uint16_t)(((uint16_t)(x)) << ENC_LMOD_MOD_SHIFT)) & ENC_LMOD_MOD_MASK)
/*! @} */
/*! @name UCOMP - Upper Position Compare Register */
/*! @{ */
#define ENC_UCOMP_COMP_MASK (0xFFFFU)
#define ENC_UCOMP_COMP_SHIFT (0U)
/*! COMP - COMP
*/
#define ENC_UCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_UCOMP_COMP_SHIFT)) & ENC_UCOMP_COMP_MASK)
/*! @} */
/*! @name LCOMP - Lower Position Compare Register */
/*! @{ */
#define ENC_LCOMP_COMP_MASK (0xFFFFU)
#define ENC_LCOMP_COMP_SHIFT (0U)
/*! COMP - COMP
*/
#define ENC_LCOMP_COMP(x) (((uint16_t)(((uint16_t)(x)) << ENC_LCOMP_COMP_SHIFT)) & ENC_LCOMP_COMP_MASK)
/*! @} */
/*! @name LASTEDGE - Last Edge Time Register */
/*! @{ */
#define ENC_LASTEDGE_LASTEDGE_MASK (0xFFFFU)
#define ENC_LASTEDGE_LASTEDGE_SHIFT (0U)
/*! LASTEDGE - Last Edge Time Counter
*/
#define ENC_LASTEDGE_LASTEDGE(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGE_LASTEDGE_SHIFT)) & ENC_LASTEDGE_LASTEDGE_MASK)
/*! @} */
/*! @name LASTEDGEH - Last Edge Time Hold Register */
/*! @{ */
#define ENC_LASTEDGEH_LASTEDGEH_MASK (0xFFFFU)
#define ENC_LASTEDGEH_LASTEDGEH_SHIFT (0U)
/*! LASTEDGEH - Last Edge Time Hold
*/
#define ENC_LASTEDGEH_LASTEDGEH(x) (((uint16_t)(((uint16_t)(x)) << ENC_LASTEDGEH_LASTEDGEH_SHIFT)) & ENC_LASTEDGEH_LASTEDGEH_MASK)
/*! @} */
/*! @name POSDPER - Position Difference Period Counter Register */
/*! @{ */
#define ENC_POSDPER_POSDPER_MASK (0xFFFFU)
#define ENC_POSDPER_POSDPER_SHIFT (0U)
/*! POSDPER - Position difference period
*/
#define ENC_POSDPER_POSDPER(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPER_POSDPER_SHIFT)) & ENC_POSDPER_POSDPER_MASK)
/*! @} */
/*! @name POSDPERBFR - Position Difference Period Buffer Register */
/*! @{ */
#define ENC_POSDPERBFR_POSDPERBFR_MASK (0xFFFFU)
#define ENC_POSDPERBFR_POSDPERBFR_SHIFT (0U)
/*! POSDPERBFR - Position difference period buffer
*/
#define ENC_POSDPERBFR_POSDPERBFR(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERBFR_POSDPERBFR_SHIFT)) & ENC_POSDPERBFR_POSDPERBFR_MASK)
/*! @} */
/*! @name POSDPERH - Position Difference Period Hold Register */
/*! @{ */
#define ENC_POSDPERH_POSDPERH_MASK (0xFFFFU)
#define ENC_POSDPERH_POSDPERH_SHIFT (0U)
/*! POSDPERH - Position difference period hold
*/
#define ENC_POSDPERH_POSDPERH(x) (((uint16_t)(((uint16_t)(x)) << ENC_POSDPERH_POSDPERH_SHIFT)) & ENC_POSDPERH_POSDPERH_MASK)
/*! @} */
/*! @name CTRL3 - Control 3 Register */
/*! @{ */
#define ENC_CTRL3_PMEN_MASK (0x1U)
#define ENC_CTRL3_PMEN_SHIFT (0U)
/*! PMEN - Period measurement function enable
* 0b0..Period measurement functions are not used. POSD is loaded to POSDH and then cleared whenever POSD, UPOS, LPOS, or REV is read.
* 0b1..Period measurement functions are used. POSD is loaded to POSDH and then cleared only when POSD is read.
*/
#define ENC_CTRL3_PMEN(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PMEN_SHIFT)) & ENC_CTRL3_PMEN_MASK)
#define ENC_CTRL3_PRSC_MASK (0xF0U)
#define ENC_CTRL3_PRSC_SHIFT (4U)
/*! PRSC - Prescaler
*/
#define ENC_CTRL3_PRSC(x) (((uint16_t)(((uint16_t)(x)) << ENC_CTRL3_PRSC_SHIFT)) & ENC_CTRL3_PRSC_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ENC_Register_Masks */
/* ENC - Peripheral instance base addresses */
/** Peripheral ENC1 base address */
#define ENC1_BASE (0x40174000u)
/** Peripheral ENC1 base pointer */
#define ENC1 ((ENC_Type *)ENC1_BASE)
/** Peripheral ENC2 base address */
#define ENC2_BASE (0x40178000u)
/** Peripheral ENC2 base pointer */
#define ENC2 ((ENC_Type *)ENC2_BASE)
/** Peripheral ENC3 base address */
#define ENC3_BASE (0x4017C000u)
/** Peripheral ENC3 base pointer */
#define ENC3 ((ENC_Type *)ENC3_BASE)
/** Peripheral ENC4 base address */
#define ENC4_BASE (0x40180000u)
/** Peripheral ENC4 base pointer */
#define ENC4 ((ENC_Type *)ENC4_BASE)
/** Array initializer of ENC peripheral base addresses */
#define ENC_BASE_ADDRS { 0u, ENC1_BASE, ENC2_BASE, ENC3_BASE, ENC4_BASE }
/** Array initializer of ENC peripheral base pointers */
#define ENC_BASE_PTRS { (ENC_Type *)0u, ENC1, ENC2, ENC3, ENC4 }
/** Interrupt vectors for the ENC peripheral type */
#define ENC_COMPARE_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define ENC_HOME_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define ENC_WDOG_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define ENC_INDEX_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
#define ENC_INPUT_SWITCH_IRQS { NotAvail_IRQn, ENC1_IRQn, ENC2_IRQn, ENC3_IRQn, ENC4_IRQn }
/*!
* @}
*/ /* end of group ENC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ENET Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
* @{
*/
/** ENET - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t EIR; /**< Interrupt Event Register, offset: 0x4 */
__IO uint32_t EIMR; /**< Interrupt Mask Register, offset: 0x8 */
uint8_t RESERVED_1[4];
__IO uint32_t RDAR; /**< Receive Descriptor Active Register - Ring 0, offset: 0x10 */
__IO uint32_t TDAR; /**< Transmit Descriptor Active Register - Ring 0, offset: 0x14 */
uint8_t RESERVED_2[12];
__IO uint32_t ECR; /**< Ethernet Control Register, offset: 0x24 */
uint8_t RESERVED_3[24];
__IO uint32_t MMFR; /**< MII Management Frame Register, offset: 0x40 */
__IO uint32_t MSCR; /**< MII Speed Control Register, offset: 0x44 */
uint8_t RESERVED_4[28];
__IO uint32_t MIBC; /**< MIB Control Register, offset: 0x64 */
uint8_t RESERVED_5[28];
__IO uint32_t RCR; /**< Receive Control Register, offset: 0x84 */
uint8_t RESERVED_6[60];
__IO uint32_t TCR; /**< Transmit Control Register, offset: 0xC4 */
uint8_t RESERVED_7[28];
__IO uint32_t PALR; /**< Physical Address Lower Register, offset: 0xE4 */
__IO uint32_t PAUR; /**< Physical Address Upper Register, offset: 0xE8 */
__IO uint32_t OPD; /**< Opcode/Pause Duration Register, offset: 0xEC */
__IO uint32_t TXIC[3]; /**< Transmit Interrupt Coalescing Register, array offset: 0xF0, array step: 0x4 */
uint8_t RESERVED_8[4];
__IO uint32_t RXIC[3]; /**< Receive Interrupt Coalescing Register, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_9[12];
__IO uint32_t IAUR; /**< Descriptor Individual Upper Address Register, offset: 0x118 */
__IO uint32_t IALR; /**< Descriptor Individual Lower Address Register, offset: 0x11C */
__IO uint32_t GAUR; /**< Descriptor Group Upper Address Register, offset: 0x120 */
__IO uint32_t GALR; /**< Descriptor Group Lower Address Register, offset: 0x124 */
uint8_t RESERVED_10[28];
__IO uint32_t TFWR; /**< Transmit FIFO Watermark Register, offset: 0x144 */
uint8_t RESERVED_11[24];
__IO uint32_t RDSR1; /**< Receive Descriptor Ring 1 Start Register, offset: 0x160 */
__IO uint32_t TDSR1; /**< Transmit Buffer Descriptor Ring 1 Start Register, offset: 0x164 */
__IO uint32_t MRBR1; /**< Maximum Receive Buffer Size Register - Ring 1, offset: 0x168 */
__IO uint32_t RDSR2; /**< Receive Descriptor Ring 2 Start Register, offset: 0x16C */
__IO uint32_t TDSR2; /**< Transmit Buffer Descriptor Ring 2 Start Register, offset: 0x170 */
__IO uint32_t MRBR2; /**< Maximum Receive Buffer Size Register - Ring 2, offset: 0x174 */
uint8_t RESERVED_12[8];
__IO uint32_t RDSR; /**< Receive Descriptor Ring 0 Start Register, offset: 0x180 */
__IO uint32_t TDSR; /**< Transmit Buffer Descriptor Ring 0 Start Register, offset: 0x184 */
__IO uint32_t MRBR; /**< Maximum Receive Buffer Size Register - Ring 0, offset: 0x188 */
uint8_t RESERVED_13[4];
__IO uint32_t RSFL; /**< Receive FIFO Section Full Threshold, offset: 0x190 */
__IO uint32_t RSEM; /**< Receive FIFO Section Empty Threshold, offset: 0x194 */
__IO uint32_t RAEM; /**< Receive FIFO Almost Empty Threshold, offset: 0x198 */
__IO uint32_t RAFL; /**< Receive FIFO Almost Full Threshold, offset: 0x19C */
__IO uint32_t TSEM; /**< Transmit FIFO Section Empty Threshold, offset: 0x1A0 */
__IO uint32_t TAEM; /**< Transmit FIFO Almost Empty Threshold, offset: 0x1A4 */
__IO uint32_t TAFL; /**< Transmit FIFO Almost Full Threshold, offset: 0x1A8 */
__IO uint32_t TIPG; /**< Transmit Inter-Packet Gap, offset: 0x1AC */
__IO uint32_t FTRL; /**< Frame Truncation Length, offset: 0x1B0 */
uint8_t RESERVED_14[12];
__IO uint32_t TACC; /**< Transmit Accelerator Function Configuration, offset: 0x1C0 */
__IO uint32_t RACC; /**< Receive Accelerator Function Configuration, offset: 0x1C4 */
__IO uint32_t RCMR[2]; /**< Receive Classification Match Register for Class n, array offset: 0x1C8, array step: 0x4 */
uint8_t RESERVED_15[8];
__IO uint32_t DMACFG[2]; /**< DMA Class Based Configuration, array offset: 0x1D8, array step: 0x4 */
__IO uint32_t RDAR1; /**< Receive Descriptor Active Register - Ring 1, offset: 0x1E0 */
__IO uint32_t TDAR1; /**< Transmit Descriptor Active Register - Ring 1, offset: 0x1E4 */
__IO uint32_t RDAR2; /**< Receive Descriptor Active Register - Ring 2, offset: 0x1E8 */
__IO uint32_t TDAR2; /**< Transmit Descriptor Active Register - Ring 2, offset: 0x1EC */
__IO uint32_t QOS; /**< QOS Scheme, offset: 0x1F0 */
uint8_t RESERVED_16[16];
__I uint32_t RMON_T_PACKETS; /**< Tx Packet Count Statistic Register, offset: 0x204 */
__I uint32_t RMON_T_BC_PKT; /**< Tx Broadcast Packets Statistic Register, offset: 0x208 */
__I uint32_t RMON_T_MC_PKT; /**< Tx Multicast Packets Statistic Register, offset: 0x20C */
__I uint32_t RMON_T_CRC_ALIGN; /**< Tx Packets with CRC/Align Error Statistic Register, offset: 0x210 */
__I uint32_t RMON_T_UNDERSIZE; /**< Tx Packets Less Than Bytes and Good CRC Statistic Register, offset: 0x214 */
__I uint32_t RMON_T_OVERSIZE; /**< Tx Packets GT MAX_FL bytes and Good CRC Statistic Register, offset: 0x218 */
__I uint32_t RMON_T_FRAG; /**< Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x21C */
__I uint32_t RMON_T_JAB; /**< Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register, offset: 0x220 */
__I uint32_t RMON_T_COL; /**< Tx Collision Count Statistic Register, offset: 0x224 */
__I uint32_t RMON_T_P64; /**< Tx 64-Byte Packets Statistic Register, offset: 0x228 */
__I uint32_t RMON_T_P65TO127; /**< Tx 65- to 127-byte Packets Statistic Register, offset: 0x22C */
__I uint32_t RMON_T_P128TO255; /**< Tx 128- to 255-byte Packets Statistic Register, offset: 0x230 */
__I uint32_t RMON_T_P256TO511; /**< Tx 256- to 511-byte Packets Statistic Register, offset: 0x234 */
__I uint32_t RMON_T_P512TO1023; /**< Tx 512- to 1023-byte Packets Statistic Register, offset: 0x238 */
__I uint32_t RMON_T_P1024TO2047; /**< Tx 1024- to 2047-byte Packets Statistic Register, offset: 0x23C */
__I uint32_t RMON_T_P_GTE2048; /**< Tx Packets Greater Than 2048 Bytes Statistic Register, offset: 0x240 */
__I uint32_t RMON_T_OCTETS; /**< Tx Octets Statistic Register, offset: 0x244 */
uint32_t IEEE_T_DROP; /**< Reserved Statistic Register, offset: 0x248 */
__I uint32_t IEEE_T_FRAME_OK; /**< Frames Transmitted OK Statistic Register, offset: 0x24C */
__I uint32_t IEEE_T_1COL; /**< Frames Transmitted with Single Collision Statistic Register, offset: 0x250 */
__I uint32_t IEEE_T_MCOL; /**< Frames Transmitted with Multiple Collisions Statistic Register, offset: 0x254 */
__I uint32_t IEEE_T_DEF; /**< Frames Transmitted after Deferral Delay Statistic Register, offset: 0x258 */
__I uint32_t IEEE_T_LCOL; /**< Frames Transmitted with Late Collision Statistic Register, offset: 0x25C */
__I uint32_t IEEE_T_EXCOL; /**< Frames Transmitted with Excessive Collisions Statistic Register, offset: 0x260 */
__I uint32_t IEEE_T_MACERR; /**< Frames Transmitted with Tx FIFO Underrun Statistic Register, offset: 0x264 */
__I uint32_t IEEE_T_CSERR; /**< Frames Transmitted with Carrier Sense Error Statistic Register, offset: 0x268 */
__I uint32_t IEEE_T_SQE; /**< Reserved Statistic Register, offset: 0x26C */
__I uint32_t IEEE_T_FDXFC; /**< Flow Control Pause Frames Transmitted Statistic Register, offset: 0x270 */
__I uint32_t IEEE_T_OCTETS_OK; /**< Octet Count for Frames Transmitted w/o Error Statistic Register, offset: 0x274 */
uint8_t RESERVED_17[12];
__I uint32_t RMON_R_PACKETS; /**< Rx Packet Count Statistic Register, offset: 0x284 */
__I uint32_t RMON_R_BC_PKT; /**< Rx Broadcast Packets Statistic Register, offset: 0x288 */
__I uint32_t RMON_R_MC_PKT; /**< Rx Multicast Packets Statistic Register, offset: 0x28C */
__I uint32_t RMON_R_CRC_ALIGN; /**< Rx Packets with CRC/Align Error Statistic Register, offset: 0x290 */
__I uint32_t RMON_R_UNDERSIZE; /**< Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register, offset: 0x294 */
__I uint32_t RMON_R_OVERSIZE; /**< Rx Packets Greater Than MAX_FL and Good CRC Statistic Register, offset: 0x298 */
__I uint32_t RMON_R_FRAG; /**< Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register, offset: 0x29C */
__I uint32_t RMON_R_JAB; /**< Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register, offset: 0x2A0 */
uint8_t RESERVED_18[4];
__I uint32_t RMON_R_P64; /**< Rx 64-Byte Packets Statistic Register, offset: 0x2A8 */
__I uint32_t RMON_R_P65TO127; /**< Rx 65- to 127-Byte Packets Statistic Register, offset: 0x2AC */
__I uint32_t RMON_R_P128TO255; /**< Rx 128- to 255-Byte Packets Statistic Register, offset: 0x2B0 */
__I uint32_t RMON_R_P256TO511; /**< Rx 256- to 511-Byte Packets Statistic Register, offset: 0x2B4 */
__I uint32_t RMON_R_P512TO1023; /**< Rx 512- to 1023-Byte Packets Statistic Register, offset: 0x2B8 */
__I uint32_t RMON_R_P1024TO2047; /**< Rx 1024- to 2047-Byte Packets Statistic Register, offset: 0x2BC */
__I uint32_t RMON_R_P_GTE2048; /**< Rx Packets Greater than 2048 Bytes Statistic Register, offset: 0x2C0 */
__I uint32_t RMON_R_OCTETS; /**< Rx Octets Statistic Register, offset: 0x2C4 */
__I uint32_t IEEE_R_DROP; /**< Frames not Counted Correctly Statistic Register, offset: 0x2C8 */
__I uint32_t IEEE_R_FRAME_OK; /**< Frames Received OK Statistic Register, offset: 0x2CC */
__I uint32_t IEEE_R_CRC; /**< Frames Received with CRC Error Statistic Register, offset: 0x2D0 */
__I uint32_t IEEE_R_ALIGN; /**< Frames Received with Alignment Error Statistic Register, offset: 0x2D4 */
__I uint32_t IEEE_R_MACERR; /**< Receive FIFO Overflow Count Statistic Register, offset: 0x2D8 */
__I uint32_t IEEE_R_FDXFC; /**< Flow Control Pause Frames Received Statistic Register, offset: 0x2DC */
__I uint32_t IEEE_R_OCTETS_OK; /**< Octet Count for Frames Received without Error Statistic Register, offset: 0x2E0 */
uint8_t RESERVED_19[284];
__IO uint32_t ATCR; /**< Adjustable Timer Control Register, offset: 0x400 */
__IO uint32_t ATVR; /**< Timer Value Register, offset: 0x404 */
__IO uint32_t ATOFF; /**< Timer Offset Register, offset: 0x408 */
__IO uint32_t ATPER; /**< Timer Period Register, offset: 0x40C */
__IO uint32_t ATCOR; /**< Timer Correction Register, offset: 0x410 */
__IO uint32_t ATINC; /**< Time-Stamping Clock Period Register, offset: 0x414 */
__I uint32_t ATSTMP; /**< Timestamp of Last Transmitted Frame, offset: 0x418 */
uint8_t RESERVED_20[488];
__IO uint32_t TGSR; /**< Timer Global Status Register, offset: 0x604 */
struct { /* offset: 0x608, array step: 0x8 */
__IO uint32_t TCSR; /**< Timer Control Status Register, array offset: 0x608, array step: 0x8 */
__IO uint32_t TCCR; /**< Timer Compare Capture Register, array offset: 0x60C, array step: 0x8 */
} CHANNEL[4];
} ENET_Type;
/* ----------------------------------------------------------------------------
-- ENET Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENET_Register_Masks ENET Register Masks
* @{
*/
/*! @name EIR - Interrupt Event Register */
/*! @{ */
#define ENET_EIR_RXB1_MASK (0x1U)
#define ENET_EIR_RXB1_SHIFT (0U)
/*! RXB1 - Receive buffer interrupt, class 1
*/
#define ENET_EIR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB1_SHIFT)) & ENET_EIR_RXB1_MASK)
#define ENET_EIR_RXF1_MASK (0x2U)
#define ENET_EIR_RXF1_SHIFT (1U)
/*! RXF1 - Receive frame interrupt, class 1
*/
#define ENET_EIR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF1_SHIFT)) & ENET_EIR_RXF1_MASK)
#define ENET_EIR_TXB1_MASK (0x4U)
#define ENET_EIR_TXB1_SHIFT (2U)
/*! TXB1 - Transmit buffer interrupt, class 1
*/
#define ENET_EIR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB1_SHIFT)) & ENET_EIR_TXB1_MASK)
#define ENET_EIR_TXF1_MASK (0x8U)
#define ENET_EIR_TXF1_SHIFT (3U)
/*! TXF1 - Transmit frame interrupt, class 1
*/
#define ENET_EIR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF1_SHIFT)) & ENET_EIR_TXF1_MASK)
#define ENET_EIR_RXB2_MASK (0x10U)
#define ENET_EIR_RXB2_SHIFT (4U)
/*! RXB2 - Receive buffer interrupt, class 2
*/
#define ENET_EIR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB2_SHIFT)) & ENET_EIR_RXB2_MASK)
#define ENET_EIR_RXF2_MASK (0x20U)
#define ENET_EIR_RXF2_SHIFT (5U)
/*! RXF2 - Receive frame interrupt, class 2
*/
#define ENET_EIR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF2_SHIFT)) & ENET_EIR_RXF2_MASK)
#define ENET_EIR_TXB2_MASK (0x40U)
#define ENET_EIR_TXB2_SHIFT (6U)
/*! TXB2 - Transmit buffer interrupt, class 2
*/
#define ENET_EIR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB2_SHIFT)) & ENET_EIR_TXB2_MASK)
#define ENET_EIR_TXF2_MASK (0x80U)
#define ENET_EIR_TXF2_SHIFT (7U)
/*! TXF2 - Transmit frame interrupt, class 2
*/
#define ENET_EIR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF2_SHIFT)) & ENET_EIR_TXF2_MASK)
#define ENET_EIR_RXFLUSH_0_MASK (0x1000U)
#define ENET_EIR_RXFLUSH_0_SHIFT (12U)
#define ENET_EIR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_0_SHIFT)) & ENET_EIR_RXFLUSH_0_MASK)
#define ENET_EIR_RXFLUSH_1_MASK (0x2000U)
#define ENET_EIR_RXFLUSH_1_SHIFT (13U)
#define ENET_EIR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_1_SHIFT)) & ENET_EIR_RXFLUSH_1_MASK)
#define ENET_EIR_RXFLUSH_2_MASK (0x4000U)
#define ENET_EIR_RXFLUSH_2_SHIFT (14U)
#define ENET_EIR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXFLUSH_2_SHIFT)) & ENET_EIR_RXFLUSH_2_MASK)
#define ENET_EIR_TS_TIMER_MASK (0x8000U)
#define ENET_EIR_TS_TIMER_SHIFT (15U)
/*! TS_TIMER - Timestamp Timer
*/
#define ENET_EIR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_TIMER_SHIFT)) & ENET_EIR_TS_TIMER_MASK)
#define ENET_EIR_TS_AVAIL_MASK (0x10000U)
#define ENET_EIR_TS_AVAIL_SHIFT (16U)
/*! TS_AVAIL - Transmit Timestamp Available
*/
#define ENET_EIR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TS_AVAIL_SHIFT)) & ENET_EIR_TS_AVAIL_MASK)
#define ENET_EIR_WAKEUP_MASK (0x20000U)
#define ENET_EIR_WAKEUP_SHIFT (17U)
/*! WAKEUP - Node Wakeup Request Indication
*/
#define ENET_EIR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_WAKEUP_SHIFT)) & ENET_EIR_WAKEUP_MASK)
#define ENET_EIR_PLR_MASK (0x40000U)
#define ENET_EIR_PLR_SHIFT (18U)
/*! PLR - Payload Receive Error
*/
#define ENET_EIR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_PLR_SHIFT)) & ENET_EIR_PLR_MASK)
#define ENET_EIR_UN_MASK (0x80000U)
#define ENET_EIR_UN_SHIFT (19U)
/*! UN - Transmit FIFO Underrun
*/
#define ENET_EIR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_UN_SHIFT)) & ENET_EIR_UN_MASK)
#define ENET_EIR_RL_MASK (0x100000U)
#define ENET_EIR_RL_SHIFT (20U)
/*! RL - Collision Retry Limit
*/
#define ENET_EIR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RL_SHIFT)) & ENET_EIR_RL_MASK)
#define ENET_EIR_LC_MASK (0x200000U)
#define ENET_EIR_LC_SHIFT (21U)
/*! LC - Late Collision
*/
#define ENET_EIR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_LC_SHIFT)) & ENET_EIR_LC_MASK)
#define ENET_EIR_EBERR_MASK (0x400000U)
#define ENET_EIR_EBERR_SHIFT (22U)
/*! EBERR - Ethernet Bus Error
*/
#define ENET_EIR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_EBERR_SHIFT)) & ENET_EIR_EBERR_MASK)
#define ENET_EIR_MII_MASK (0x800000U)
#define ENET_EIR_MII_SHIFT (23U)
/*! MII - MII Interrupt.
*/
#define ENET_EIR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_MII_SHIFT)) & ENET_EIR_MII_MASK)
#define ENET_EIR_RXB_MASK (0x1000000U)
#define ENET_EIR_RXB_SHIFT (24U)
/*! RXB - Receive Buffer Interrupt
*/
#define ENET_EIR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXB_SHIFT)) & ENET_EIR_RXB_MASK)
#define ENET_EIR_RXF_MASK (0x2000000U)
#define ENET_EIR_RXF_SHIFT (25U)
/*! RXF - Receive Frame Interrupt
*/
#define ENET_EIR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_RXF_SHIFT)) & ENET_EIR_RXF_MASK)
#define ENET_EIR_TXB_MASK (0x4000000U)
#define ENET_EIR_TXB_SHIFT (26U)
/*! TXB - Transmit Buffer Interrupt
*/
#define ENET_EIR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXB_SHIFT)) & ENET_EIR_TXB_MASK)
#define ENET_EIR_TXF_MASK (0x8000000U)
#define ENET_EIR_TXF_SHIFT (27U)
/*! TXF - Transmit Frame Interrupt
*/
#define ENET_EIR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_TXF_SHIFT)) & ENET_EIR_TXF_MASK)
#define ENET_EIR_GRA_MASK (0x10000000U)
#define ENET_EIR_GRA_SHIFT (28U)
/*! GRA - Graceful Stop Complete
*/
#define ENET_EIR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_GRA_SHIFT)) & ENET_EIR_GRA_MASK)
#define ENET_EIR_BABT_MASK (0x20000000U)
#define ENET_EIR_BABT_SHIFT (29U)
/*! BABT - Babbling Transmit Error
*/
#define ENET_EIR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABT_SHIFT)) & ENET_EIR_BABT_MASK)
#define ENET_EIR_BABR_MASK (0x40000000U)
#define ENET_EIR_BABR_SHIFT (30U)
/*! BABR - Babbling Receive Error
*/
#define ENET_EIR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIR_BABR_SHIFT)) & ENET_EIR_BABR_MASK)
/*! @} */
/*! @name EIMR - Interrupt Mask Register */
/*! @{ */
#define ENET_EIMR_RXB1_MASK (0x1U)
#define ENET_EIMR_RXB1_SHIFT (0U)
/*! RXB1 - Receive buffer interrupt, class 1
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_RXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB1_SHIFT)) & ENET_EIMR_RXB1_MASK)
#define ENET_EIMR_RXF1_MASK (0x2U)
#define ENET_EIMR_RXF1_SHIFT (1U)
/*! RXF1 - Receive frame interrupt, class 1
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_RXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF1_SHIFT)) & ENET_EIMR_RXF1_MASK)
#define ENET_EIMR_TXB1_MASK (0x4U)
#define ENET_EIMR_TXB1_SHIFT (2U)
/*! TXB1 - Transmit buffer interrupt, class 1
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_TXB1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB1_SHIFT)) & ENET_EIMR_TXB1_MASK)
#define ENET_EIMR_TXF1_MASK (0x8U)
#define ENET_EIMR_TXF1_SHIFT (3U)
/*! TXF1 - Transmit frame interrupt, class 1
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_TXF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF1_SHIFT)) & ENET_EIMR_TXF1_MASK)
#define ENET_EIMR_RXB2_MASK (0x10U)
#define ENET_EIMR_RXB2_SHIFT (4U)
/*! RXB2 - Receive buffer interrupt, class 2
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_RXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB2_SHIFT)) & ENET_EIMR_RXB2_MASK)
#define ENET_EIMR_RXF2_MASK (0x20U)
#define ENET_EIMR_RXF2_SHIFT (5U)
/*! RXF2 - Receive frame interrupt, class 2
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_RXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF2_SHIFT)) & ENET_EIMR_RXF2_MASK)
#define ENET_EIMR_TXB2_MASK (0x40U)
#define ENET_EIMR_TXB2_SHIFT (6U)
/*! TXB2 - Transmit buffer interrupt, class 2
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_TXB2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB2_SHIFT)) & ENET_EIMR_TXB2_MASK)
#define ENET_EIMR_TXF2_MASK (0x80U)
#define ENET_EIMR_TXF2_SHIFT (7U)
/*! TXF2 - Transmit frame interrupt, class 2
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_TXF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF2_SHIFT)) & ENET_EIMR_TXF2_MASK)
#define ENET_EIMR_RXFLUSH_0_MASK (0x1000U)
#define ENET_EIMR_RXFLUSH_0_SHIFT (12U)
/*! RXFLUSH_0
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_RXFLUSH_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_0_SHIFT)) & ENET_EIMR_RXFLUSH_0_MASK)
#define ENET_EIMR_RXFLUSH_1_MASK (0x2000U)
#define ENET_EIMR_RXFLUSH_1_SHIFT (13U)
/*! RXFLUSH_1
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_RXFLUSH_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_1_SHIFT)) & ENET_EIMR_RXFLUSH_1_MASK)
#define ENET_EIMR_RXFLUSH_2_MASK (0x4000U)
#define ENET_EIMR_RXFLUSH_2_SHIFT (14U)
/*! RXFLUSH_2
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_RXFLUSH_2(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXFLUSH_2_SHIFT)) & ENET_EIMR_RXFLUSH_2_MASK)
#define ENET_EIMR_TS_TIMER_MASK (0x8000U)
#define ENET_EIMR_TS_TIMER_SHIFT (15U)
/*! TS_TIMER - TS_TIMER Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_TS_TIMER(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_TIMER_SHIFT)) & ENET_EIMR_TS_TIMER_MASK)
#define ENET_EIMR_TS_AVAIL_MASK (0x10000U)
#define ENET_EIMR_TS_AVAIL_SHIFT (16U)
/*! TS_AVAIL - TS_AVAIL Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_TS_AVAIL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TS_AVAIL_SHIFT)) & ENET_EIMR_TS_AVAIL_MASK)
#define ENET_EIMR_WAKEUP_MASK (0x20000U)
#define ENET_EIMR_WAKEUP_SHIFT (17U)
/*! WAKEUP - WAKEUP Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_WAKEUP_SHIFT)) & ENET_EIMR_WAKEUP_MASK)
#define ENET_EIMR_PLR_MASK (0x40000U)
#define ENET_EIMR_PLR_SHIFT (18U)
/*! PLR - PLR Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_PLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_PLR_SHIFT)) & ENET_EIMR_PLR_MASK)
#define ENET_EIMR_UN_MASK (0x80000U)
#define ENET_EIMR_UN_SHIFT (19U)
/*! UN - UN Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_UN(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_UN_SHIFT)) & ENET_EIMR_UN_MASK)
#define ENET_EIMR_RL_MASK (0x100000U)
#define ENET_EIMR_RL_SHIFT (20U)
/*! RL - RL Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_RL(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RL_SHIFT)) & ENET_EIMR_RL_MASK)
#define ENET_EIMR_LC_MASK (0x200000U)
#define ENET_EIMR_LC_SHIFT (21U)
/*! LC - LC Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_LC_SHIFT)) & ENET_EIMR_LC_MASK)
#define ENET_EIMR_EBERR_MASK (0x400000U)
#define ENET_EIMR_EBERR_SHIFT (22U)
/*! EBERR - EBERR Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_EBERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_EBERR_SHIFT)) & ENET_EIMR_EBERR_MASK)
#define ENET_EIMR_MII_MASK (0x800000U)
#define ENET_EIMR_MII_SHIFT (23U)
/*! MII - MII Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_MII(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_MII_SHIFT)) & ENET_EIMR_MII_MASK)
#define ENET_EIMR_RXB_MASK (0x1000000U)
#define ENET_EIMR_RXB_SHIFT (24U)
/*! RXB - RXB Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_RXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXB_SHIFT)) & ENET_EIMR_RXB_MASK)
#define ENET_EIMR_RXF_MASK (0x2000000U)
#define ENET_EIMR_RXF_SHIFT (25U)
/*! RXF - RXF Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_RXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_RXF_SHIFT)) & ENET_EIMR_RXF_MASK)
#define ENET_EIMR_TXB_MASK (0x4000000U)
#define ENET_EIMR_TXB_SHIFT (26U)
/*! TXB - TXB Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_TXB(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXB_SHIFT)) & ENET_EIMR_TXB_MASK)
#define ENET_EIMR_TXF_MASK (0x8000000U)
#define ENET_EIMR_TXF_SHIFT (27U)
/*! TXF - TXF Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_TXF(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_TXF_SHIFT)) & ENET_EIMR_TXF_MASK)
#define ENET_EIMR_GRA_MASK (0x10000000U)
#define ENET_EIMR_GRA_SHIFT (28U)
/*! GRA - GRA Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_GRA(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_GRA_SHIFT)) & ENET_EIMR_GRA_MASK)
#define ENET_EIMR_BABT_MASK (0x20000000U)
#define ENET_EIMR_BABT_SHIFT (29U)
/*! BABT - BABT Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_BABT(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABT_SHIFT)) & ENET_EIMR_BABT_MASK)
#define ENET_EIMR_BABR_MASK (0x40000000U)
#define ENET_EIMR_BABR_SHIFT (30U)
/*! BABR - BABR Interrupt Mask
* 0b0..The corresponding interrupt source is masked.
* 0b1..The corresponding interrupt source is not masked.
*/
#define ENET_EIMR_BABR(x) (((uint32_t)(((uint32_t)(x)) << ENET_EIMR_BABR_SHIFT)) & ENET_EIMR_BABR_MASK)
/*! @} */
/*! @name RDAR - Receive Descriptor Active Register - Ring 0 */
/*! @{ */
#define ENET_RDAR_RDAR_MASK (0x1000000U)
#define ENET_RDAR_RDAR_SHIFT (24U)
/*! RDAR - Receive Descriptor Active
*/
#define ENET_RDAR_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR_RDAR_SHIFT)) & ENET_RDAR_RDAR_MASK)
/*! @} */
/*! @name TDAR - Transmit Descriptor Active Register - Ring 0 */
/*! @{ */
#define ENET_TDAR_TDAR_MASK (0x1000000U)
#define ENET_TDAR_TDAR_SHIFT (24U)
/*! TDAR - Transmit Descriptor Active
*/
#define ENET_TDAR_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR_TDAR_SHIFT)) & ENET_TDAR_TDAR_MASK)
/*! @} */
/*! @name ECR - Ethernet Control Register */
/*! @{ */
#define ENET_ECR_RESET_MASK (0x1U)
#define ENET_ECR_RESET_SHIFT (0U)
/*! RESET - Ethernet MAC Reset
*/
#define ENET_ECR_RESET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_RESET_SHIFT)) & ENET_ECR_RESET_MASK)
#define ENET_ECR_ETHEREN_MASK (0x2U)
#define ENET_ECR_ETHEREN_SHIFT (1U)
/*! ETHEREN - Ethernet Enable
* 0b0..Reception immediately stops and transmission stops after a bad CRC is appended to any currently transmitted frame.
* 0b1..MAC is enabled, and reception and transmission are possible.
*/
#define ENET_ECR_ETHEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_ETHEREN_SHIFT)) & ENET_ECR_ETHEREN_MASK)
#define ENET_ECR_MAGICEN_MASK (0x4U)
#define ENET_ECR_MAGICEN_SHIFT (2U)
/*! MAGICEN - Magic Packet Detection Enable
* 0b0..Magic detection logic disabled.
* 0b1..The MAC core detects magic packets and asserts EIR[WAKEUP] when a frame is detected.
*/
#define ENET_ECR_MAGICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_MAGICEN_SHIFT)) & ENET_ECR_MAGICEN_MASK)
#define ENET_ECR_SLEEP_MASK (0x8U)
#define ENET_ECR_SLEEP_SHIFT (3U)
/*! SLEEP - Sleep Mode Enable
* 0b0..Normal operating mode.
* 0b1..Sleep mode.
*/
#define ENET_ECR_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SLEEP_SHIFT)) & ENET_ECR_SLEEP_MASK)
#define ENET_ECR_EN1588_MASK (0x10U)
#define ENET_ECR_EN1588_SHIFT (4U)
/*! EN1588 - EN1588 Enable
* 0b0..Legacy FEC buffer descriptors and functions enabled.
* 0b1..Enhanced frame time-stamping functions enabled. Has no effect within the MAC besides controlling the DMA control bit ena_1588.
*/
#define ENET_ECR_EN1588(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_EN1588_SHIFT)) & ENET_ECR_EN1588_MASK)
#define ENET_ECR_SPEED_MASK (0x20U)
#define ENET_ECR_SPEED_SHIFT (5U)
/*! SPEED
* 0b0..10/100-Mbit/s mode
* 0b1..1000-Mbit/s mode
*/
#define ENET_ECR_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SPEED_SHIFT)) & ENET_ECR_SPEED_MASK)
#define ENET_ECR_DBGEN_MASK (0x40U)
#define ENET_ECR_DBGEN_SHIFT (6U)
/*! DBGEN - Debug Enable
* 0b0..MAC continues operation in debug mode.
* 0b1..MAC enters hardware freeze mode when the processor is in debug mode.
*/
#define ENET_ECR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBGEN_SHIFT)) & ENET_ECR_DBGEN_MASK)
#define ENET_ECR_DBSWP_MASK (0x100U)
#define ENET_ECR_DBSWP_SHIFT (8U)
/*! DBSWP - Descriptor Byte Swapping Enable
* 0b0..The buffer descriptor bytes are not swapped to support big-endian devices.
* 0b1..The buffer descriptor bytes are swapped to support little-endian devices.
*/
#define ENET_ECR_DBSWP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_DBSWP_SHIFT)) & ENET_ECR_DBSWP_MASK)
#define ENET_ECR_SVLANEN_MASK (0x200U)
#define ENET_ECR_SVLANEN_SHIFT (9U)
/*! SVLANEN - S-VLAN enable
* 0b0..Only the EtherType 0x8100 will be considered for VLAN detection.
* 0b1..The EtherType 0x88a8 will be considered in addition to 0x8100 (C-VLAN) to identify a VLAN frame in
* receive. When a VLAN frame is identified, the two bytes following the VLAN type are extracted and used by the
* classification match comparators, RCMRn.
*/
#define ENET_ECR_SVLANEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANEN_SHIFT)) & ENET_ECR_SVLANEN_MASK)
#define ENET_ECR_VLANUSE2ND_MASK (0x400U)
#define ENET_ECR_VLANUSE2ND_SHIFT (10U)
/*! VLANUSE2ND - VLAN use second tag
* 0b0..Always extract data from the first VLAN tag if it exists.
* 0b1..When a double-tagged frame is detected, the data of the second tag is extracted for further processing. A
* double-tagged frame is defined as: The first tag can be a C-VLAN or a S-VLAN (if SVLAN_ENA = 1) The
* second tag must be a C-VLAN
*/
#define ENET_ECR_VLANUSE2ND(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_VLANUSE2ND_SHIFT)) & ENET_ECR_VLANUSE2ND_MASK)
#define ENET_ECR_SVLANDBL_MASK (0x800U)
#define ENET_ECR_SVLANDBL_SHIFT (11U)
/*! SVLANDBL - S-VLAN double tag
* 0b0..Disable S-VLAN double tag
* 0b1..Enable S-VLAN double tag
*/
#define ENET_ECR_SVLANDBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_SVLANDBL_SHIFT)) & ENET_ECR_SVLANDBL_MASK)
#define ENET_ECR_TXC_DLY_MASK (0x10000U)
#define ENET_ECR_TXC_DLY_SHIFT (16U)
/*! TXC_DLY - Transmit clock delay
* 0b0..RGMII_TXC is not delayed.
* 0b1..Generate delayed version of RGMII_TXC.
*/
#define ENET_ECR_TXC_DLY(x) (((uint32_t)(((uint32_t)(x)) << ENET_ECR_TXC_DLY_SHIFT)) & ENET_ECR_TXC_DLY_MASK)
/*! @} */
/*! @name MMFR - MII Management Frame Register */
/*! @{ */
#define ENET_MMFR_DATA_MASK (0xFFFFU)
#define ENET_MMFR_DATA_SHIFT (0U)
/*! DATA - Management Frame Data
*/
#define ENET_MMFR_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_DATA_SHIFT)) & ENET_MMFR_DATA_MASK)
#define ENET_MMFR_TA_MASK (0x30000U)
#define ENET_MMFR_TA_SHIFT (16U)
/*! TA - Turn Around
*/
#define ENET_MMFR_TA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_TA_SHIFT)) & ENET_MMFR_TA_MASK)
#define ENET_MMFR_RA_MASK (0x7C0000U)
#define ENET_MMFR_RA_SHIFT (18U)
/*! RA - Register Address
*/
#define ENET_MMFR_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_RA_SHIFT)) & ENET_MMFR_RA_MASK)
#define ENET_MMFR_PA_MASK (0xF800000U)
#define ENET_MMFR_PA_SHIFT (23U)
/*! PA - PHY Address
*/
#define ENET_MMFR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_PA_SHIFT)) & ENET_MMFR_PA_MASK)
#define ENET_MMFR_OP_MASK (0x30000000U)
#define ENET_MMFR_OP_SHIFT (28U)
/*! OP - Operation Code
*/
#define ENET_MMFR_OP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_OP_SHIFT)) & ENET_MMFR_OP_MASK)
#define ENET_MMFR_ST_MASK (0xC0000000U)
#define ENET_MMFR_ST_SHIFT (30U)
/*! ST - Start Of Frame Delimiter
*/
#define ENET_MMFR_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MMFR_ST_SHIFT)) & ENET_MMFR_ST_MASK)
/*! @} */
/*! @name MSCR - MII Speed Control Register */
/*! @{ */
#define ENET_MSCR_MII_SPEED_MASK (0x7EU)
#define ENET_MSCR_MII_SPEED_SHIFT (1U)
/*! MII_SPEED - MII Speed
*/
#define ENET_MSCR_MII_SPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_MII_SPEED_SHIFT)) & ENET_MSCR_MII_SPEED_MASK)
#define ENET_MSCR_DIS_PRE_MASK (0x80U)
#define ENET_MSCR_DIS_PRE_SHIFT (7U)
/*! DIS_PRE - Disable Preamble
* 0b0..Preamble enabled.
* 0b1..Preamble (32 ones) is not prepended to the MII management frame.
*/
#define ENET_MSCR_DIS_PRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_DIS_PRE_SHIFT)) & ENET_MSCR_DIS_PRE_MASK)
#define ENET_MSCR_HOLDTIME_MASK (0x700U)
#define ENET_MSCR_HOLDTIME_SHIFT (8U)
/*! HOLDTIME - Hold time On MDIO Output
* 0b000..1 internal module clock cycle
* 0b001..2 internal module clock cycles
* 0b010..3 internal module clock cycles
* 0b111..8 internal module clock cycles
*/
#define ENET_MSCR_HOLDTIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_MSCR_HOLDTIME_SHIFT)) & ENET_MSCR_HOLDTIME_MASK)
/*! @} */
/*! @name MIBC - MIB Control Register */
/*! @{ */
#define ENET_MIBC_MIB_CLEAR_MASK (0x20000000U)
#define ENET_MIBC_MIB_CLEAR_SHIFT (29U)
/*! MIB_CLEAR - MIB Clear
* 0b0..See note above.
* 0b1..All statistics counters are reset to 0.
*/
#define ENET_MIBC_MIB_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_CLEAR_SHIFT)) & ENET_MIBC_MIB_CLEAR_MASK)
#define ENET_MIBC_MIB_IDLE_MASK (0x40000000U)
#define ENET_MIBC_MIB_IDLE_SHIFT (30U)
/*! MIB_IDLE - MIB Idle
* 0b0..The MIB block is updating MIB counters.
* 0b1..The MIB block is not currently updating any MIB counters.
*/
#define ENET_MIBC_MIB_IDLE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_IDLE_SHIFT)) & ENET_MIBC_MIB_IDLE_MASK)
#define ENET_MIBC_MIB_DIS_MASK (0x80000000U)
#define ENET_MIBC_MIB_DIS_SHIFT (31U)
/*! MIB_DIS - Disable MIB Logic
* 0b0..MIB logic is enabled.
* 0b1..MIB logic is disabled. The MIB logic halts and does not update any MIB counters.
*/
#define ENET_MIBC_MIB_DIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MIBC_MIB_DIS_SHIFT)) & ENET_MIBC_MIB_DIS_MASK)
/*! @} */
/*! @name RCR - Receive Control Register */
/*! @{ */
#define ENET_RCR_LOOP_MASK (0x1U)
#define ENET_RCR_LOOP_SHIFT (0U)
/*! LOOP - Internal Loopback
* 0b0..Loopback disabled.
* 0b1..Transmitted frames are looped back internal to the device and transmit MII output signals are not asserted. DRT must be cleared.
*/
#define ENET_RCR_LOOP(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_LOOP_SHIFT)) & ENET_RCR_LOOP_MASK)
#define ENET_RCR_DRT_MASK (0x2U)
#define ENET_RCR_DRT_SHIFT (1U)
/*! DRT - Disable Receive On Transmit
* 0b0..Receive path operates independently of transmit (i.e., full-duplex mode). Can also be used to monitor transmit activity in half-duplex mode.
* 0b1..Disable reception of frames while transmitting. (Normally used for half-duplex mode.)
*/
#define ENET_RCR_DRT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_DRT_SHIFT)) & ENET_RCR_DRT_MASK)
#define ENET_RCR_MII_MODE_MASK (0x4U)
#define ENET_RCR_MII_MODE_SHIFT (2U)
/*! MII_MODE - Media Independent Interface Mode
* 0b0..Reserved.
* 0b1..MII or RMII mode, as indicated by the RMII_MODE field.
*/
#define ENET_RCR_MII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MII_MODE_SHIFT)) & ENET_RCR_MII_MODE_MASK)
#define ENET_RCR_PROM_MASK (0x8U)
#define ENET_RCR_PROM_SHIFT (3U)
/*! PROM - Promiscuous Mode
* 0b0..Disabled.
* 0b1..Enabled.
*/
#define ENET_RCR_PROM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PROM_SHIFT)) & ENET_RCR_PROM_MASK)
#define ENET_RCR_BC_REJ_MASK (0x10U)
#define ENET_RCR_BC_REJ_SHIFT (4U)
/*! BC_REJ - Broadcast Frame Reject
* 0b0..Will not reject frames as described above
* 0b1..Will reject frames as described above
*/
#define ENET_RCR_BC_REJ(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_BC_REJ_SHIFT)) & ENET_RCR_BC_REJ_MASK)
#define ENET_RCR_FCE_MASK (0x20U)
#define ENET_RCR_FCE_SHIFT (5U)
/*! FCE - Flow Control Enable
* 0b0..Disable flow control
* 0b1..Enable flow control
*/
#define ENET_RCR_FCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_FCE_SHIFT)) & ENET_RCR_FCE_MASK)
#define ENET_RCR_RGMII_EN_MASK (0x40U)
#define ENET_RCR_RGMII_EN_SHIFT (6U)
/*! RGMII_EN - RGMII Mode Enable
* 0b0..MAC configured for non-RGMII operation
* 0b1..MAC configured for RGMII operation. If ECR[SPEED] is set, the MAC is in RGMII 1000-Mbit/s mode. If
* ECR[SPEED] is cleared, the MAC is in RGMII 10/100-Mbit/s mode.
*/
#define ENET_RCR_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RGMII_EN_SHIFT)) & ENET_RCR_RGMII_EN_MASK)
#define ENET_RCR_RMII_MODE_MASK (0x100U)
#define ENET_RCR_RMII_MODE_SHIFT (8U)
/*! RMII_MODE - RMII Mode Enable
* 0b0..MAC configured for MII mode.
* 0b1..MAC configured for RMII operation.
*/
#define ENET_RCR_RMII_MODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_MODE_SHIFT)) & ENET_RCR_RMII_MODE_MASK)
#define ENET_RCR_RMII_10T_MASK (0x200U)
#define ENET_RCR_RMII_10T_SHIFT (9U)
/*! RMII_10T
* 0b0..100-Mbit/s or 1-Gbit/s operation.
* 0b1..10-Mbit/s operation.
*/
#define ENET_RCR_RMII_10T(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_RMII_10T_SHIFT)) & ENET_RCR_RMII_10T_MASK)
#define ENET_RCR_PADEN_MASK (0x1000U)
#define ENET_RCR_PADEN_SHIFT (12U)
/*! PADEN - Enable Frame Padding Remove On Receive
* 0b0..No padding is removed on receive by the MAC.
* 0b1..Padding is removed from received frames.
*/
#define ENET_RCR_PADEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PADEN_SHIFT)) & ENET_RCR_PADEN_MASK)
#define ENET_RCR_PAUFWD_MASK (0x2000U)
#define ENET_RCR_PAUFWD_SHIFT (13U)
/*! PAUFWD - Terminate/Forward Pause Frames
* 0b0..Pause frames are terminated and discarded in the MAC.
* 0b1..Pause frames are forwarded to the user application.
*/
#define ENET_RCR_PAUFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_PAUFWD_SHIFT)) & ENET_RCR_PAUFWD_MASK)
#define ENET_RCR_CRCFWD_MASK (0x4000U)
#define ENET_RCR_CRCFWD_SHIFT (14U)
/*! CRCFWD - Terminate/Forward Received CRC
* 0b0..The CRC field of received frames is transmitted to the user application.
* 0b1..The CRC field is stripped from the frame.
*/
#define ENET_RCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CRCFWD_SHIFT)) & ENET_RCR_CRCFWD_MASK)
#define ENET_RCR_CFEN_MASK (0x8000U)
#define ENET_RCR_CFEN_SHIFT (15U)
/*! CFEN - MAC Control Frame Enable
* 0b0..MAC control frames with any opcode other than 0x0001 (pause frame) are accepted and forwarded to the client interface.
* 0b1..MAC control frames with any opcode other than 0x0001 (pause frame) are silently discarded.
*/
#define ENET_RCR_CFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_CFEN_SHIFT)) & ENET_RCR_CFEN_MASK)
#define ENET_RCR_MAX_FL_MASK (0x3FFF0000U)
#define ENET_RCR_MAX_FL_SHIFT (16U)
/*! MAX_FL - Maximum Frame Length
*/
#define ENET_RCR_MAX_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_MAX_FL_SHIFT)) & ENET_RCR_MAX_FL_MASK)
#define ENET_RCR_NLC_MASK (0x40000000U)
#define ENET_RCR_NLC_SHIFT (30U)
/*! NLC - Payload Length Check Disable
* 0b0..The payload length check is disabled.
* 0b1..The core checks the frame's payload length with the frame length/type field. Errors are indicated in the EIR[PLR] field.
*/
#define ENET_RCR_NLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_NLC_SHIFT)) & ENET_RCR_NLC_MASK)
#define ENET_RCR_GRS_MASK (0x80000000U)
#define ENET_RCR_GRS_SHIFT (31U)
/*! GRS - Graceful Receive Stopped
* 0b0..Receive not stopped
* 0b1..Receive stopped
*/
#define ENET_RCR_GRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCR_GRS_SHIFT)) & ENET_RCR_GRS_MASK)
/*! @} */
/*! @name TCR - Transmit Control Register */
/*! @{ */
#define ENET_TCR_GTS_MASK (0x1U)
#define ENET_TCR_GTS_SHIFT (0U)
/*! GTS - Graceful Transmit Stop
* 0b0..Disable graceful transmit stop
* 0b1..Enable graceful transmit stop
*/
#define ENET_TCR_GTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_GTS_SHIFT)) & ENET_TCR_GTS_MASK)
#define ENET_TCR_FDEN_MASK (0x4U)
#define ENET_TCR_FDEN_SHIFT (2U)
/*! FDEN - Full-Duplex Enable
* 0b0..Disable full-duplex
* 0b1..Enable full-duplex
*/
#define ENET_TCR_FDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_FDEN_SHIFT)) & ENET_TCR_FDEN_MASK)
#define ENET_TCR_TFC_PAUSE_MASK (0x8U)
#define ENET_TCR_TFC_PAUSE_SHIFT (3U)
/*! TFC_PAUSE - Transmit Frame Control Pause
* 0b0..No PAUSE frame transmitted.
* 0b1..The MAC stops transmission of data frames after the current transmission is complete.
*/
#define ENET_TCR_TFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_TFC_PAUSE_SHIFT)) & ENET_TCR_TFC_PAUSE_MASK)
#define ENET_TCR_RFC_PAUSE_MASK (0x10U)
#define ENET_TCR_RFC_PAUSE_SHIFT (4U)
/*! RFC_PAUSE - Receive Frame Control Pause
*/
#define ENET_TCR_RFC_PAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_RFC_PAUSE_SHIFT)) & ENET_TCR_RFC_PAUSE_MASK)
#define ENET_TCR_ADDSEL_MASK (0xE0U)
#define ENET_TCR_ADDSEL_SHIFT (5U)
/*! ADDSEL - Source MAC Address Select On Transmit
* 0b000..Node MAC address programmed on PADDR1/2 registers.
* 0b100..Reserved.
* 0b101..Reserved.
* 0b110..Reserved.
*/
#define ENET_TCR_ADDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDSEL_SHIFT)) & ENET_TCR_ADDSEL_MASK)
#define ENET_TCR_ADDINS_MASK (0x100U)
#define ENET_TCR_ADDINS_SHIFT (8U)
/*! ADDINS - Set MAC Address On Transmit
* 0b0..The source MAC address is not modified by the MAC.
* 0b1..The MAC overwrites the source MAC address with the programmed MAC address according to ADDSEL.
*/
#define ENET_TCR_ADDINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_ADDINS_SHIFT)) & ENET_TCR_ADDINS_MASK)
#define ENET_TCR_CRCFWD_MASK (0x200U)
#define ENET_TCR_CRCFWD_SHIFT (9U)
/*! CRCFWD - Forward Frame From Application With CRC
* 0b0..TxBD[TC] controls whether the frame has a CRC from the application.
* 0b1..The transmitter does not append any CRC to transmitted frames, as it is expecting a frame with CRC from the application.
*/
#define ENET_TCR_CRCFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCR_CRCFWD_SHIFT)) & ENET_TCR_CRCFWD_MASK)
/*! @} */
/*! @name PALR - Physical Address Lower Register */
/*! @{ */
#define ENET_PALR_PADDR1_MASK (0xFFFFFFFFU)
#define ENET_PALR_PADDR1_SHIFT (0U)
/*! PADDR1 - Pause Address
*/
#define ENET_PALR_PADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_PALR_PADDR1_SHIFT)) & ENET_PALR_PADDR1_MASK)
/*! @} */
/*! @name PAUR - Physical Address Upper Register */
/*! @{ */
#define ENET_PAUR_TYPE_MASK (0xFFFFU)
#define ENET_PAUR_TYPE_SHIFT (0U)
/*! TYPE - Type Field In PAUSE Frames
*/
#define ENET_PAUR_TYPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_TYPE_SHIFT)) & ENET_PAUR_TYPE_MASK)
#define ENET_PAUR_PADDR2_MASK (0xFFFF0000U)
#define ENET_PAUR_PADDR2_SHIFT (16U)
#define ENET_PAUR_PADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_PAUR_PADDR2_SHIFT)) & ENET_PAUR_PADDR2_MASK)
/*! @} */
/*! @name OPD - Opcode/Pause Duration Register */
/*! @{ */
#define ENET_OPD_PAUSE_DUR_MASK (0xFFFFU)
#define ENET_OPD_PAUSE_DUR_SHIFT (0U)
/*! PAUSE_DUR - Pause Duration
*/
#define ENET_OPD_PAUSE_DUR(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_PAUSE_DUR_SHIFT)) & ENET_OPD_PAUSE_DUR_MASK)
#define ENET_OPD_OPCODE_MASK (0xFFFF0000U)
#define ENET_OPD_OPCODE_SHIFT (16U)
/*! OPCODE - Opcode Field In PAUSE Frames
*/
#define ENET_OPD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_OPD_OPCODE_SHIFT)) & ENET_OPD_OPCODE_MASK)
/*! @} */
/*! @name TXIC - Transmit Interrupt Coalescing Register */
/*! @{ */
#define ENET_TXIC_ICTT_MASK (0xFFFFU)
#define ENET_TXIC_ICTT_SHIFT (0U)
/*! ICTT - Interrupt coalescing timer threshold
*/
#define ENET_TXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICTT_SHIFT)) & ENET_TXIC_ICTT_MASK)
#define ENET_TXIC_ICFT_MASK (0xFF00000U)
#define ENET_TXIC_ICFT_SHIFT (20U)
/*! ICFT - Interrupt coalescing frame count threshold
*/
#define ENET_TXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICFT_SHIFT)) & ENET_TXIC_ICFT_MASK)
#define ENET_TXIC_ICCS_MASK (0x40000000U)
#define ENET_TXIC_ICCS_SHIFT (30U)
/*! ICCS - Interrupt Coalescing Timer Clock Source Select
* 0b0..Use MII/GMII TX clocks.
* 0b1..Use ENET system clock.
*/
#define ENET_TXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICCS_SHIFT)) & ENET_TXIC_ICCS_MASK)
#define ENET_TXIC_ICEN_MASK (0x80000000U)
#define ENET_TXIC_ICEN_SHIFT (31U)
/*! ICEN - Interrupt Coalescing Enable
* 0b0..Disable Interrupt coalescing.
* 0b1..Enable Interrupt coalescing.
*/
#define ENET_TXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_TXIC_ICEN_SHIFT)) & ENET_TXIC_ICEN_MASK)
/*! @} */
/* The count of ENET_TXIC */
#define ENET_TXIC_COUNT (3U)
/*! @name RXIC - Receive Interrupt Coalescing Register */
/*! @{ */
#define ENET_RXIC_ICTT_MASK (0xFFFFU)
#define ENET_RXIC_ICTT_SHIFT (0U)
/*! ICTT - Interrupt coalescing timer threshold
*/
#define ENET_RXIC_ICTT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICTT_SHIFT)) & ENET_RXIC_ICTT_MASK)
#define ENET_RXIC_ICFT_MASK (0xFF00000U)
#define ENET_RXIC_ICFT_SHIFT (20U)
/*! ICFT - Interrupt coalescing frame count threshold
*/
#define ENET_RXIC_ICFT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICFT_SHIFT)) & ENET_RXIC_ICFT_MASK)
#define ENET_RXIC_ICCS_MASK (0x40000000U)
#define ENET_RXIC_ICCS_SHIFT (30U)
/*! ICCS - Interrupt Coalescing Timer Clock Source Select
* 0b0..Use MII/GMII TX clocks.
* 0b1..Use ENET system clock.
*/
#define ENET_RXIC_ICCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICCS_SHIFT)) & ENET_RXIC_ICCS_MASK)
#define ENET_RXIC_ICEN_MASK (0x80000000U)
#define ENET_RXIC_ICEN_SHIFT (31U)
/*! ICEN - Interrupt Coalescing Enable
* 0b0..Disable Interrupt coalescing.
* 0b1..Enable Interrupt coalescing.
*/
#define ENET_RXIC_ICEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RXIC_ICEN_SHIFT)) & ENET_RXIC_ICEN_MASK)
/*! @} */
/* The count of ENET_RXIC */
#define ENET_RXIC_COUNT (3U)
/*! @name IAUR - Descriptor Individual Upper Address Register */
/*! @{ */
#define ENET_IAUR_IADDR1_MASK (0xFFFFFFFFU)
#define ENET_IAUR_IADDR1_SHIFT (0U)
#define ENET_IAUR_IADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_IAUR_IADDR1_SHIFT)) & ENET_IAUR_IADDR1_MASK)
/*! @} */
/*! @name IALR - Descriptor Individual Lower Address Register */
/*! @{ */
#define ENET_IALR_IADDR2_MASK (0xFFFFFFFFU)
#define ENET_IALR_IADDR2_SHIFT (0U)
#define ENET_IALR_IADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_IALR_IADDR2_SHIFT)) & ENET_IALR_IADDR2_MASK)
/*! @} */
/*! @name GAUR - Descriptor Group Upper Address Register */
/*! @{ */
#define ENET_GAUR_GADDR1_MASK (0xFFFFFFFFU)
#define ENET_GAUR_GADDR1_SHIFT (0U)
#define ENET_GAUR_GADDR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_GAUR_GADDR1_SHIFT)) & ENET_GAUR_GADDR1_MASK)
/*! @} */
/*! @name GALR - Descriptor Group Lower Address Register */
/*! @{ */
#define ENET_GALR_GADDR2_MASK (0xFFFFFFFFU)
#define ENET_GALR_GADDR2_SHIFT (0U)
#define ENET_GALR_GADDR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_GALR_GADDR2_SHIFT)) & ENET_GALR_GADDR2_MASK)
/*! @} */
/*! @name TFWR - Transmit FIFO Watermark Register */
/*! @{ */
#define ENET_TFWR_TFWR_MASK (0x3FU)
#define ENET_TFWR_TFWR_SHIFT (0U)
/*! TFWR - Transmit FIFO Write
* 0b000000..64 bytes written.
* 0b000001..64 bytes written.
* 0b000010..128 bytes written.
* 0b000011..192 bytes written.
* 0b011111..1984 bytes written.
*/
#define ENET_TFWR_TFWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_TFWR_SHIFT)) & ENET_TFWR_TFWR_MASK)
#define ENET_TFWR_STRFWD_MASK (0x100U)
#define ENET_TFWR_STRFWD_SHIFT (8U)
/*! STRFWD - Store And Forward Enable
* 0b0..Reset. The transmission start threshold is programmed in TFWR[TFWR].
* 0b1..Enabled.
*/
#define ENET_TFWR_STRFWD(x) (((uint32_t)(((uint32_t)(x)) << ENET_TFWR_STRFWD_SHIFT)) & ENET_TFWR_STRFWD_MASK)
/*! @} */
/*! @name RDSR1 - Receive Descriptor Ring 1 Start Register */
/*! @{ */
#define ENET_RDSR1_R_DES_START_MASK (0xFFFFFFF8U)
#define ENET_RDSR1_R_DES_START_SHIFT (3U)
#define ENET_RDSR1_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR1_R_DES_START_SHIFT)) & ENET_RDSR1_R_DES_START_MASK)
/*! @} */
/*! @name TDSR1 - Transmit Buffer Descriptor Ring 1 Start Register */
/*! @{ */
#define ENET_TDSR1_X_DES_START_MASK (0xFFFFFFF8U)
#define ENET_TDSR1_X_DES_START_SHIFT (3U)
#define ENET_TDSR1_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR1_X_DES_START_SHIFT)) & ENET_TDSR1_X_DES_START_MASK)
/*! @} */
/*! @name MRBR1 - Maximum Receive Buffer Size Register - Ring 1 */
/*! @{ */
#define ENET_MRBR1_R_BUF_SIZE_MASK (0x7F0U)
#define ENET_MRBR1_R_BUF_SIZE_SHIFT (4U)
#define ENET_MRBR1_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR1_R_BUF_SIZE_SHIFT)) & ENET_MRBR1_R_BUF_SIZE_MASK)
/*! @} */
/*! @name RDSR2 - Receive Descriptor Ring 2 Start Register */
/*! @{ */
#define ENET_RDSR2_R_DES_START_MASK (0xFFFFFFF8U)
#define ENET_RDSR2_R_DES_START_SHIFT (3U)
#define ENET_RDSR2_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR2_R_DES_START_SHIFT)) & ENET_RDSR2_R_DES_START_MASK)
/*! @} */
/*! @name TDSR2 - Transmit Buffer Descriptor Ring 2 Start Register */
/*! @{ */
#define ENET_TDSR2_X_DES_START_MASK (0xFFFFFFF8U)
#define ENET_TDSR2_X_DES_START_SHIFT (3U)
#define ENET_TDSR2_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR2_X_DES_START_SHIFT)) & ENET_TDSR2_X_DES_START_MASK)
/*! @} */
/*! @name MRBR2 - Maximum Receive Buffer Size Register - Ring 2 */
/*! @{ */
#define ENET_MRBR2_R_BUF_SIZE_MASK (0x7F0U)
#define ENET_MRBR2_R_BUF_SIZE_SHIFT (4U)
#define ENET_MRBR2_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR2_R_BUF_SIZE_SHIFT)) & ENET_MRBR2_R_BUF_SIZE_MASK)
/*! @} */
/*! @name RDSR - Receive Descriptor Ring 0 Start Register */
/*! @{ */
#define ENET_RDSR_R_DES_START_MASK (0xFFFFFFF8U)
#define ENET_RDSR_R_DES_START_SHIFT (3U)
#define ENET_RDSR_R_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDSR_R_DES_START_SHIFT)) & ENET_RDSR_R_DES_START_MASK)
/*! @} */
/*! @name TDSR - Transmit Buffer Descriptor Ring 0 Start Register */
/*! @{ */
#define ENET_TDSR_X_DES_START_MASK (0xFFFFFFF8U)
#define ENET_TDSR_X_DES_START_SHIFT (3U)
#define ENET_TDSR_X_DES_START(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDSR_X_DES_START_SHIFT)) & ENET_TDSR_X_DES_START_MASK)
/*! @} */
/*! @name MRBR - Maximum Receive Buffer Size Register - Ring 0 */
/*! @{ */
#define ENET_MRBR_R_BUF_SIZE_MASK (0x3FF0U) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */
#define ENET_MRBR_R_BUF_SIZE_SHIFT (4U)
#define ENET_MRBR_R_BUF_SIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MRBR_R_BUF_SIZE_SHIFT)) & ENET_MRBR_R_BUF_SIZE_MASK) /* Merged from fields with different position or width, of widths (7, 10), largest definition used */
/*! @} */
/*! @name RSFL - Receive FIFO Section Full Threshold */
/*! @{ */
#define ENET_RSFL_RX_SECTION_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
#define ENET_RSFL_RX_SECTION_FULL_SHIFT (0U)
/*! RX_SECTION_FULL - Value Of Receive FIFO Section Full Threshold
*/
#define ENET_RSFL_RX_SECTION_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSFL_RX_SECTION_FULL_SHIFT)) & ENET_RSFL_RX_SECTION_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
/*! @} */
/*! @name RSEM - Receive FIFO Section Empty Threshold */
/*! @{ */
#define ENET_RSEM_RX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
#define ENET_RSEM_RX_SECTION_EMPTY_SHIFT (0U)
/*! RX_SECTION_EMPTY - Value Of The Receive FIFO Section Empty Threshold
*/
#define ENET_RSEM_RX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_RX_SECTION_EMPTY_SHIFT)) & ENET_RSEM_RX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
#define ENET_RSEM_STAT_SECTION_EMPTY_MASK (0x1F0000U)
#define ENET_RSEM_STAT_SECTION_EMPTY_SHIFT (16U)
/*! STAT_SECTION_EMPTY - RX Status FIFO Section Empty Threshold
*/
#define ENET_RSEM_STAT_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RSEM_STAT_SECTION_EMPTY_SHIFT)) & ENET_RSEM_STAT_SECTION_EMPTY_MASK)
/*! @} */
/*! @name RAEM - Receive FIFO Almost Empty Threshold */
/*! @{ */
#define ENET_RAEM_RX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
#define ENET_RAEM_RX_ALMOST_EMPTY_SHIFT (0U)
/*! RX_ALMOST_EMPTY - Value Of The Receive FIFO Almost Empty Threshold
*/
#define ENET_RAEM_RX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAEM_RX_ALMOST_EMPTY_SHIFT)) & ENET_RAEM_RX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
/*! @} */
/*! @name RAFL - Receive FIFO Almost Full Threshold */
/*! @{ */
#define ENET_RAFL_RX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
#define ENET_RAFL_RX_ALMOST_FULL_SHIFT (0U)
/*! RX_ALMOST_FULL - Value Of The Receive FIFO Almost Full Threshold
*/
#define ENET_RAFL_RX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_RAFL_RX_ALMOST_FULL_SHIFT)) & ENET_RAFL_RX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
/*! @} */
/*! @name TSEM - Transmit FIFO Section Empty Threshold */
/*! @{ */
#define ENET_TSEM_TX_SECTION_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
#define ENET_TSEM_TX_SECTION_EMPTY_SHIFT (0U)
/*! TX_SECTION_EMPTY - Value Of The Transmit FIFO Section Empty Threshold
*/
#define ENET_TSEM_TX_SECTION_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TSEM_TX_SECTION_EMPTY_SHIFT)) & ENET_TSEM_TX_SECTION_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
/*! @} */
/*! @name TAEM - Transmit FIFO Almost Empty Threshold */
/*! @{ */
#define ENET_TAEM_TX_ALMOST_EMPTY_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
#define ENET_TAEM_TX_ALMOST_EMPTY_SHIFT (0U)
/*! TX_ALMOST_EMPTY - Value of Transmit FIFO Almost Empty Threshold
*/
#define ENET_TAEM_TX_ALMOST_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAEM_TX_ALMOST_EMPTY_SHIFT)) & ENET_TAEM_TX_ALMOST_EMPTY_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
/*! @} */
/*! @name TAFL - Transmit FIFO Almost Full Threshold */
/*! @{ */
#define ENET_TAFL_TX_ALMOST_FULL_MASK (0x3FFU) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
#define ENET_TAFL_TX_ALMOST_FULL_SHIFT (0U)
/*! TX_ALMOST_FULL - Value Of The Transmit FIFO Almost Full Threshold
*/
#define ENET_TAFL_TX_ALMOST_FULL(x) (((uint32_t)(((uint32_t)(x)) << ENET_TAFL_TX_ALMOST_FULL_SHIFT)) & ENET_TAFL_TX_ALMOST_FULL_MASK) /* Merged from fields with different position or width, of widths (8, 10), largest definition used */
/*! @} */
/*! @name TIPG - Transmit Inter-Packet Gap */
/*! @{ */
#define ENET_TIPG_IPG_MASK (0x1FU)
#define ENET_TIPG_IPG_SHIFT (0U)
/*! IPG - Transmit Inter-Packet Gap
*/
#define ENET_TIPG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_TIPG_IPG_SHIFT)) & ENET_TIPG_IPG_MASK)
/*! @} */
/*! @name FTRL - Frame Truncation Length */
/*! @{ */
#define ENET_FTRL_TRUNC_FL_MASK (0x3FFFU)
#define ENET_FTRL_TRUNC_FL_SHIFT (0U)
/*! TRUNC_FL - Frame Truncation Length
*/
#define ENET_FTRL_TRUNC_FL(x) (((uint32_t)(((uint32_t)(x)) << ENET_FTRL_TRUNC_FL_SHIFT)) & ENET_FTRL_TRUNC_FL_MASK)
/*! @} */
/*! @name TACC - Transmit Accelerator Function Configuration */
/*! @{ */
#define ENET_TACC_SHIFT16_MASK (0x1U)
#define ENET_TACC_SHIFT16_SHIFT (0U)
/*! SHIFT16 - TX FIFO Shift-16
* 0b0..Disabled.
* 0b1..Indicates to the transmit data FIFO that the written frames contain two additional octets before the
* frame data. This means the actual frame begins at bit 16 of the first word written into the FIFO. This
* function allows putting the frame payload on a 32-bit boundary in memory, as the 14-byte Ethernet header is
* extended to a 16-byte header.
*/
#define ENET_TACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_SHIFT16_SHIFT)) & ENET_TACC_SHIFT16_MASK)
#define ENET_TACC_IPCHK_MASK (0x8U)
#define ENET_TACC_IPCHK_SHIFT (3U)
/*! IPCHK
* 0b0..Checksum is not inserted.
* 0b1..If an IP frame is transmitted, the checksum is inserted automatically. The IP header checksum field must
* be cleared. If a non-IP frame is transmitted the frame is not modified.
*/
#define ENET_TACC_IPCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_IPCHK_SHIFT)) & ENET_TACC_IPCHK_MASK)
#define ENET_TACC_PROCHK_MASK (0x10U)
#define ENET_TACC_PROCHK_SHIFT (4U)
/*! PROCHK
* 0b0..Checksum not inserted.
* 0b1..If an IP frame with a known protocol is transmitted, the checksum is inserted automatically into the
* frame. The checksum field must be cleared. The other frames are not modified.
*/
#define ENET_TACC_PROCHK(x) (((uint32_t)(((uint32_t)(x)) << ENET_TACC_PROCHK_SHIFT)) & ENET_TACC_PROCHK_MASK)
/*! @} */
/*! @name RACC - Receive Accelerator Function Configuration */
/*! @{ */
#define ENET_RACC_PADREM_MASK (0x1U)
#define ENET_RACC_PADREM_SHIFT (0U)
/*! PADREM - Enable Padding Removal For Short IP Frames
* 0b0..Padding not removed.
* 0b1..Any bytes following the IP payload section of the frame are removed from the frame.
*/
#define ENET_RACC_PADREM(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PADREM_SHIFT)) & ENET_RACC_PADREM_MASK)
#define ENET_RACC_IPDIS_MASK (0x2U)
#define ENET_RACC_IPDIS_SHIFT (1U)
/*! IPDIS - Enable Discard Of Frames With Wrong IPv4 Header Checksum
* 0b0..Frames with wrong IPv4 header checksum are not discarded.
* 0b1..If an IPv4 frame is received with a mismatching header checksum, the frame is discarded. IPv6 has no
* header checksum and is not affected by this setting. Discarding is only available when the RX FIFO operates in
* store and forward mode (RSFL cleared).
*/
#define ENET_RACC_IPDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_IPDIS_SHIFT)) & ENET_RACC_IPDIS_MASK)
#define ENET_RACC_PRODIS_MASK (0x4U)
#define ENET_RACC_PRODIS_SHIFT (2U)
/*! PRODIS - Enable Discard Of Frames With Wrong Protocol Checksum
* 0b0..Frames with wrong checksum are not discarded.
* 0b1..If a TCP/IP, UDP/IP, or ICMP/IP frame is received that has a wrong TCP, UDP, or ICMP checksum, the frame
* is discarded. Discarding is only available when the RX FIFO operates in store and forward mode (RSFL
* cleared).
*/
#define ENET_RACC_PRODIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_PRODIS_SHIFT)) & ENET_RACC_PRODIS_MASK)
#define ENET_RACC_LINEDIS_MASK (0x40U)
#define ENET_RACC_LINEDIS_SHIFT (6U)
/*! LINEDIS - Enable Discard Of Frames With MAC Layer Errors
* 0b0..Frames with errors are not discarded.
* 0b1..Any frame received with a CRC, length, or PHY error is automatically discarded and not forwarded to the user application interface.
*/
#define ENET_RACC_LINEDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_LINEDIS_SHIFT)) & ENET_RACC_LINEDIS_MASK)
#define ENET_RACC_SHIFT16_MASK (0x80U)
#define ENET_RACC_SHIFT16_SHIFT (7U)
/*! SHIFT16 - RX FIFO Shift-16
* 0b0..Disabled.
* 0b1..Instructs the MAC to write two additional bytes in front of each frame received into the RX FIFO.
*/
#define ENET_RACC_SHIFT16(x) (((uint32_t)(((uint32_t)(x)) << ENET_RACC_SHIFT16_SHIFT)) & ENET_RACC_SHIFT16_MASK)
/*! @} */
/*! @name RCMR - Receive Classification Match Register for Class n */
/*! @{ */
#define ENET_RCMR_CMP0_MASK (0x7U)
#define ENET_RCMR_CMP0_SHIFT (0U)
/*! CMP0 - Compare 0
*/
#define ENET_RCMR_CMP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP0_SHIFT)) & ENET_RCMR_CMP0_MASK)
#define ENET_RCMR_CMP1_MASK (0x70U)
#define ENET_RCMR_CMP1_SHIFT (4U)
/*! CMP1 - Compare 1
*/
#define ENET_RCMR_CMP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP1_SHIFT)) & ENET_RCMR_CMP1_MASK)
#define ENET_RCMR_CMP2_MASK (0x700U)
#define ENET_RCMR_CMP2_SHIFT (8U)
/*! CMP2 - Compare 2
*/
#define ENET_RCMR_CMP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP2_SHIFT)) & ENET_RCMR_CMP2_MASK)
#define ENET_RCMR_CMP3_MASK (0x7000U)
#define ENET_RCMR_CMP3_SHIFT (12U)
/*! CMP3 - Compare 3
*/
#define ENET_RCMR_CMP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_CMP3_SHIFT)) & ENET_RCMR_CMP3_MASK)
#define ENET_RCMR_MATCHEN_MASK (0x10000U)
#define ENET_RCMR_MATCHEN_SHIFT (16U)
/*! MATCHEN - Match Enable
* 0b0..Disabled (default): no compares will occur and the classification indicator for this class will never assert.
* 0b1..The register contents are valid and a comparison with all compare values is done when a VLAN frame is received.
*/
#define ENET_RCMR_MATCHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_RCMR_MATCHEN_SHIFT)) & ENET_RCMR_MATCHEN_MASK)
/*! @} */
/* The count of ENET_RCMR */
#define ENET_RCMR_COUNT (2U)
/*! @name DMACFG - DMA Class Based Configuration */
/*! @{ */
#define ENET_DMACFG_IDLE_SLOPE_MASK (0xFFFFU)
#define ENET_DMACFG_IDLE_SLOPE_SHIFT (0U)
/*! IDLE_SLOPE - Idle slope
*/
#define ENET_DMACFG_IDLE_SLOPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_IDLE_SLOPE_SHIFT)) & ENET_DMACFG_IDLE_SLOPE_MASK)
#define ENET_DMACFG_DMA_CLASS_EN_MASK (0x10000U)
#define ENET_DMACFG_DMA_CLASS_EN_SHIFT (16U)
/*! DMA_CLASS_EN - DMA class enable
* 0b0..The DMA controller's channel for the class is not used. Disabling the DMA controller of a class also
* requires disabling the class match comparator for the class (see registers RCMRn). When class 1 and class 2
* queues are disabled then their frames will be placed in queue 0.
* 0b1..Enable the DMA controller to support the corresponding descriptor ring for this class of traffic.
*/
#define ENET_DMACFG_DMA_CLASS_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_DMA_CLASS_EN_SHIFT)) & ENET_DMACFG_DMA_CLASS_EN_MASK)
#define ENET_DMACFG_CALC_NOIPG_MASK (0x20000U)
#define ENET_DMACFG_CALC_NOIPG_SHIFT (17U)
/*! CALC_NOIPG - Calculate no IPG
* 0b0..The traffic shaper function should consider 12 octets of IPG in addition to the frame data transferred
* for a frame when doing bandwidth calculations. This is the default.
* 0b1..Addition of 12 bytes for the IPG should be omitted when calculating the bandwidth (for traffic shaping,
* when writing a frame into the transmit FIFO, the shaper will usually consider 12 bytes of IPG for every
* frame as part of the bandwidth allocated by the frame. This addition can be suppressed, meaning short frames
* will become more bandwidth than large frames due to the relation of data to IPG overhead).
*/
#define ENET_DMACFG_CALC_NOIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMACFG_CALC_NOIPG_SHIFT)) & ENET_DMACFG_CALC_NOIPG_MASK)
/*! @} */
/* The count of ENET_DMACFG */
#define ENET_DMACFG_COUNT (2U)
/*! @name RDAR1 - Receive Descriptor Active Register - Ring 1 */
/*! @{ */
#define ENET_RDAR1_RDAR_MASK (0x1000000U)
#define ENET_RDAR1_RDAR_SHIFT (24U)
/*! RDAR - Receive Descriptor Active
*/
#define ENET_RDAR1_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR1_RDAR_SHIFT)) & ENET_RDAR1_RDAR_MASK)
/*! @} */
/*! @name TDAR1 - Transmit Descriptor Active Register - Ring 1 */
/*! @{ */
#define ENET_TDAR1_TDAR_MASK (0x1000000U)
#define ENET_TDAR1_TDAR_SHIFT (24U)
/*! TDAR - Transmit Descriptor Active
*/
#define ENET_TDAR1_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR1_TDAR_SHIFT)) & ENET_TDAR1_TDAR_MASK)
/*! @} */
/*! @name RDAR2 - Receive Descriptor Active Register - Ring 2 */
/*! @{ */
#define ENET_RDAR2_RDAR_MASK (0x1000000U)
#define ENET_RDAR2_RDAR_SHIFT (24U)
/*! RDAR - Receive Descriptor Active
*/
#define ENET_RDAR2_RDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_RDAR2_RDAR_SHIFT)) & ENET_RDAR2_RDAR_MASK)
/*! @} */
/*! @name TDAR2 - Transmit Descriptor Active Register - Ring 2 */
/*! @{ */
#define ENET_TDAR2_TDAR_MASK (0x1000000U)
#define ENET_TDAR2_TDAR_SHIFT (24U)
/*! TDAR - Transmit Descriptor Active
*/
#define ENET_TDAR2_TDAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_TDAR2_TDAR_SHIFT)) & ENET_TDAR2_TDAR_MASK)
/*! @} */
/*! @name QOS - QOS Scheme */
/*! @{ */
#define ENET_QOS_TX_SCHEME_MASK (0x7U)
#define ENET_QOS_TX_SCHEME_SHIFT (0U)
/*! TX_SCHEME - TX scheme configuration
* 0b000..Credit-based scheme
* 0b001..Round-robin scheme
* 0b010-0b111..Reserved
*/
#define ENET_QOS_TX_SCHEME(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_TX_SCHEME_SHIFT)) & ENET_QOS_TX_SCHEME_MASK)
#define ENET_QOS_RX_FLUSH0_MASK (0x8U)
#define ENET_QOS_RX_FLUSH0_SHIFT (3U)
/*! RX_FLUSH0 - RX Flush Ring 0
* 0b0..Disable
* 0b1..Enable
*/
#define ENET_QOS_RX_FLUSH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH0_SHIFT)) & ENET_QOS_RX_FLUSH0_MASK)
#define ENET_QOS_RX_FLUSH1_MASK (0x10U)
#define ENET_QOS_RX_FLUSH1_SHIFT (4U)
/*! RX_FLUSH1 - RX Flush Ring 1
* 0b0..Disable
* 0b1..Enable
*/
#define ENET_QOS_RX_FLUSH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH1_SHIFT)) & ENET_QOS_RX_FLUSH1_MASK)
#define ENET_QOS_RX_FLUSH2_MASK (0x20U)
#define ENET_QOS_RX_FLUSH2_SHIFT (5U)
/*! RX_FLUSH2 - RX Flush Ring 2
* 0b0..Disable
* 0b1..Enable
*/
#define ENET_QOS_RX_FLUSH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_RX_FLUSH2_SHIFT)) & ENET_QOS_RX_FLUSH2_MASK)
/*! @} */
/*! @name RMON_T_PACKETS - Tx Packet Count Statistic Register */
/*! @{ */
#define ENET_RMON_T_PACKETS_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_PACKETS_TXPKTS_SHIFT (0U)
/*! TXPKTS - Packet count
*/
#define ENET_RMON_T_PACKETS_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_PACKETS_TXPKTS_SHIFT)) & ENET_RMON_T_PACKETS_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_BC_PKT - Tx Broadcast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_BC_PKT_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_BC_PKT_TXPKTS_SHIFT (0U)
/*! TXPKTS - Broadcast packets
*/
#define ENET_RMON_T_BC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_BC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_BC_PKT_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_MC_PKT - Tx Multicast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_MC_PKT_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_MC_PKT_TXPKTS_SHIFT (0U)
/*! TXPKTS - Multicast packets
*/
#define ENET_RMON_T_MC_PKT_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_MC_PKT_TXPKTS_SHIFT)) & ENET_RMON_T_MC_PKT_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_CRC_ALIGN - Tx Packets with CRC/Align Error Statistic Register */
/*! @{ */
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT (0U)
/*! TXPKTS - Packets with CRC/align error
*/
#define ENET_RMON_T_CRC_ALIGN_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_CRC_ALIGN_TXPKTS_SHIFT)) & ENET_RMON_T_CRC_ALIGN_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_UNDERSIZE - Tx Packets Less Than Bytes and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_UNDERSIZE_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of transmit packets less than 64 bytes with good CRC
*/
#define ENET_RMON_T_UNDERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_UNDERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_UNDERSIZE_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_OVERSIZE - Tx Packets GT MAX_FL bytes and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_OVERSIZE_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes with good CRC
*/
#define ENET_RMON_T_OVERSIZE_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OVERSIZE_TXPKTS_SHIFT)) & ENET_RMON_T_OVERSIZE_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_FRAG - Tx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_FRAG_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_FRAG_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of packets less than 64 bytes with bad CRC
*/
#define ENET_RMON_T_FRAG_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_FRAG_TXPKTS_SHIFT)) & ENET_RMON_T_FRAG_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_JAB - Tx Packets Greater Than MAX_FL bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_T_JAB_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_JAB_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of transmit packets greater than MAX_FL bytes and bad CRC
*/
#define ENET_RMON_T_JAB_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_JAB_TXPKTS_SHIFT)) & ENET_RMON_T_JAB_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_COL - Tx Collision Count Statistic Register */
/*! @{ */
#define ENET_RMON_T_COL_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_COL_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of transmit collisions
*/
#define ENET_RMON_T_COL_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_COL_TXPKTS_SHIFT)) & ENET_RMON_T_COL_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P64 - Tx 64-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P64_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P64_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 64-byte transmit packets
*/
#define ENET_RMON_T_P64_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P64_TXPKTS_SHIFT)) & ENET_RMON_T_P64_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P65TO127 - Tx 65- to 127-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P65TO127_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P65TO127_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 65- to 127-byte transmit packets
*/
#define ENET_RMON_T_P65TO127_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P65TO127_TXPKTS_SHIFT)) & ENET_RMON_T_P65TO127_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P128TO255 - Tx 128- to 255-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P128TO255_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P128TO255_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 128- to 255-byte transmit packets
*/
#define ENET_RMON_T_P128TO255_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P128TO255_TXPKTS_SHIFT)) & ENET_RMON_T_P128TO255_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P256TO511 - Tx 256- to 511-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P256TO511_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P256TO511_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 256- to 511-byte transmit packets
*/
#define ENET_RMON_T_P256TO511_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P256TO511_TXPKTS_SHIFT)) & ENET_RMON_T_P256TO511_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P512TO1023 - Tx 512- to 1023-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P512TO1023_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P512TO1023_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 512- to 1023-byte transmit packets
*/
#define ENET_RMON_T_P512TO1023_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P512TO1023_TXPKTS_SHIFT)) & ENET_RMON_T_P512TO1023_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P1024TO2047 - Tx 1024- to 2047-byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_T_P1024TO2047_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of 1024- to 2047-byte transmit packets
*/
#define ENET_RMON_T_P1024TO2047_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P1024TO2047_TXPKTS_SHIFT)) & ENET_RMON_T_P1024TO2047_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_P_GTE2048 - Tx Packets Greater Than 2048 Bytes Statistic Register */
/*! @{ */
#define ENET_RMON_T_P_GTE2048_TXPKTS_MASK (0xFFFFU)
#define ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT (0U)
/*! TXPKTS - Number of transmit packets greater than 2048 bytes
*/
#define ENET_RMON_T_P_GTE2048_TXPKTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_P_GTE2048_TXPKTS_SHIFT)) & ENET_RMON_T_P_GTE2048_TXPKTS_MASK)
/*! @} */
/*! @name RMON_T_OCTETS - Tx Octets Statistic Register */
/*! @{ */
#define ENET_RMON_T_OCTETS_TXOCTS_MASK (0xFFFFFFFFU)
#define ENET_RMON_T_OCTETS_TXOCTS_SHIFT (0U)
/*! TXOCTS - Number of transmit octets
*/
#define ENET_RMON_T_OCTETS_TXOCTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_T_OCTETS_TXOCTS_SHIFT)) & ENET_RMON_T_OCTETS_TXOCTS_MASK)
/*! @} */
/*! @name IEEE_T_FRAME_OK - Frames Transmitted OK Statistic Register */
/*! @{ */
#define ENET_IEEE_T_FRAME_OK_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_FRAME_OK_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted OK
*/
#define ENET_IEEE_T_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_T_FRAME_OK_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_1COL - Frames Transmitted with Single Collision Statistic Register */
/*! @{ */
#define ENET_IEEE_T_1COL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_1COL_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with one collision
*/
#define ENET_IEEE_T_1COL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_1COL_COUNT_SHIFT)) & ENET_IEEE_T_1COL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_MCOL - Frames Transmitted with Multiple Collisions Statistic Register */
/*! @{ */
#define ENET_IEEE_T_MCOL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_MCOL_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with multiple collisions
*/
#define ENET_IEEE_T_MCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MCOL_COUNT_SHIFT)) & ENET_IEEE_T_MCOL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_DEF - Frames Transmitted after Deferral Delay Statistic Register */
/*! @{ */
#define ENET_IEEE_T_DEF_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_DEF_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with deferral delay
*/
#define ENET_IEEE_T_DEF_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_DEF_COUNT_SHIFT)) & ENET_IEEE_T_DEF_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_LCOL - Frames Transmitted with Late Collision Statistic Register */
/*! @{ */
#define ENET_IEEE_T_LCOL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_LCOL_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with late collision
*/
#define ENET_IEEE_T_LCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_LCOL_COUNT_SHIFT)) & ENET_IEEE_T_LCOL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_EXCOL - Frames Transmitted with Excessive Collisions Statistic Register */
/*! @{ */
#define ENET_IEEE_T_EXCOL_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_EXCOL_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with excessive collisions
*/
#define ENET_IEEE_T_EXCOL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_EXCOL_COUNT_SHIFT)) & ENET_IEEE_T_EXCOL_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_MACERR - Frames Transmitted with Tx FIFO Underrun Statistic Register */
/*! @{ */
#define ENET_IEEE_T_MACERR_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_MACERR_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with transmit FIFO underrun
*/
#define ENET_IEEE_T_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_MACERR_COUNT_SHIFT)) & ENET_IEEE_T_MACERR_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_CSERR - Frames Transmitted with Carrier Sense Error Statistic Register */
/*! @{ */
#define ENET_IEEE_T_CSERR_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_CSERR_COUNT_SHIFT (0U)
/*! COUNT - Number of frames transmitted with carrier sense error
*/
#define ENET_IEEE_T_CSERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_CSERR_COUNT_SHIFT)) & ENET_IEEE_T_CSERR_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_SQE - Reserved Statistic Register */
/*! @{ */
#define ENET_IEEE_T_SQE_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_SQE_COUNT_SHIFT (0U)
/*! COUNT - This read-only field is reserved and always has the value 0
*/
#define ENET_IEEE_T_SQE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_SQE_COUNT_SHIFT)) & ENET_IEEE_T_SQE_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_FDXFC - Flow Control Pause Frames Transmitted Statistic Register */
/*! @{ */
#define ENET_IEEE_T_FDXFC_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_T_FDXFC_COUNT_SHIFT (0U)
/*! COUNT - Number of flow-control pause frames transmitted
*/
#define ENET_IEEE_T_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_FDXFC_COUNT_SHIFT)) & ENET_IEEE_T_FDXFC_COUNT_MASK)
/*! @} */
/*! @name IEEE_T_OCTETS_OK - Octet Count for Frames Transmitted w/o Error Statistic Register */
/*! @{ */
#define ENET_IEEE_T_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
#define ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT (0U)
/*! COUNT - Octet count for frames transmitted without error Counts total octets (includes header and FCS fields).
*/
#define ENET_IEEE_T_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_T_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_T_OCTETS_OK_COUNT_MASK)
/*! @} */
/*! @name RMON_R_PACKETS - Rx Packet Count Statistic Register */
/*! @{ */
#define ENET_RMON_R_PACKETS_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_PACKETS_COUNT_SHIFT (0U)
/*! COUNT - Number of packets received
*/
#define ENET_RMON_R_PACKETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_PACKETS_COUNT_SHIFT)) & ENET_RMON_R_PACKETS_COUNT_MASK)
/*! @} */
/*! @name RMON_R_BC_PKT - Rx Broadcast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_BC_PKT_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_BC_PKT_COUNT_SHIFT (0U)
/*! COUNT - Number of receive broadcast packets
*/
#define ENET_RMON_R_BC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_BC_PKT_COUNT_SHIFT)) & ENET_RMON_R_BC_PKT_COUNT_MASK)
/*! @} */
/*! @name RMON_R_MC_PKT - Rx Multicast Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_MC_PKT_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_MC_PKT_COUNT_SHIFT (0U)
/*! COUNT - Number of receive multicast packets
*/
#define ENET_RMON_R_MC_PKT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_MC_PKT_COUNT_SHIFT)) & ENET_RMON_R_MC_PKT_COUNT_MASK)
/*! @} */
/*! @name RMON_R_CRC_ALIGN - Rx Packets with CRC/Align Error Statistic Register */
/*! @{ */
#define ENET_RMON_R_CRC_ALIGN_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT (0U)
/*! COUNT - Number of receive packets with CRC or align error
*/
#define ENET_RMON_R_CRC_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_CRC_ALIGN_COUNT_SHIFT)) & ENET_RMON_R_CRC_ALIGN_COUNT_MASK)
/*! @} */
/*! @name RMON_R_UNDERSIZE - Rx Packets with Less Than 64 Bytes and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_UNDERSIZE_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_UNDERSIZE_COUNT_SHIFT (0U)
/*! COUNT - Number of receive packets with less than 64 bytes and good CRC
*/
#define ENET_RMON_R_UNDERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_UNDERSIZE_COUNT_SHIFT)) & ENET_RMON_R_UNDERSIZE_COUNT_MASK)
/*! @} */
/*! @name RMON_R_OVERSIZE - Rx Packets Greater Than MAX_FL and Good CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_OVERSIZE_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_OVERSIZE_COUNT_SHIFT (0U)
/*! COUNT - Number of receive packets greater than MAX_FL and good CRC
*/
#define ENET_RMON_R_OVERSIZE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OVERSIZE_COUNT_SHIFT)) & ENET_RMON_R_OVERSIZE_COUNT_MASK)
/*! @} */
/*! @name RMON_R_FRAG - Rx Packets Less Than 64 Bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_FRAG_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_FRAG_COUNT_SHIFT (0U)
/*! COUNT - Number of receive packets with less than 64 bytes and bad CRC
*/
#define ENET_RMON_R_FRAG_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_FRAG_COUNT_SHIFT)) & ENET_RMON_R_FRAG_COUNT_MASK)
/*! @} */
/*! @name RMON_R_JAB - Rx Packets Greater Than MAX_FL Bytes and Bad CRC Statistic Register */
/*! @{ */
#define ENET_RMON_R_JAB_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_JAB_COUNT_SHIFT (0U)
/*! COUNT - Number of receive packets greater than MAX_FL and bad CRC
*/
#define ENET_RMON_R_JAB_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_JAB_COUNT_SHIFT)) & ENET_RMON_R_JAB_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P64 - Rx 64-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P64_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P64_COUNT_SHIFT (0U)
/*! COUNT - Number of 64-byte receive packets
*/
#define ENET_RMON_R_P64_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P64_COUNT_SHIFT)) & ENET_RMON_R_P64_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P65TO127 - Rx 65- to 127-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P65TO127_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P65TO127_COUNT_SHIFT (0U)
/*! COUNT - Number of 65- to 127-byte recieve packets
*/
#define ENET_RMON_R_P65TO127_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P65TO127_COUNT_SHIFT)) & ENET_RMON_R_P65TO127_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P128TO255 - Rx 128- to 255-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P128TO255_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P128TO255_COUNT_SHIFT (0U)
/*! COUNT - Number of 128- to 255-byte recieve packets
*/
#define ENET_RMON_R_P128TO255_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P128TO255_COUNT_SHIFT)) & ENET_RMON_R_P128TO255_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P256TO511 - Rx 256- to 511-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P256TO511_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P256TO511_COUNT_SHIFT (0U)
/*! COUNT - Number of 256- to 511-byte recieve packets
*/
#define ENET_RMON_R_P256TO511_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P256TO511_COUNT_SHIFT)) & ENET_RMON_R_P256TO511_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P512TO1023 - Rx 512- to 1023-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P512TO1023_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P512TO1023_COUNT_SHIFT (0U)
/*! COUNT - Number of 512- to 1023-byte recieve packets
*/
#define ENET_RMON_R_P512TO1023_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P512TO1023_COUNT_SHIFT)) & ENET_RMON_R_P512TO1023_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P1024TO2047 - Rx 1024- to 2047-Byte Packets Statistic Register */
/*! @{ */
#define ENET_RMON_R_P1024TO2047_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P1024TO2047_COUNT_SHIFT (0U)
/*! COUNT - Number of 1024- to 2047-byte recieve packets
*/
#define ENET_RMON_R_P1024TO2047_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P1024TO2047_COUNT_SHIFT)) & ENET_RMON_R_P1024TO2047_COUNT_MASK)
/*! @} */
/*! @name RMON_R_P_GTE2048 - Rx Packets Greater than 2048 Bytes Statistic Register */
/*! @{ */
#define ENET_RMON_R_P_GTE2048_COUNT_MASK (0xFFFFU)
#define ENET_RMON_R_P_GTE2048_COUNT_SHIFT (0U)
/*! COUNT - Number of greater-than-2048-byte recieve packets
*/
#define ENET_RMON_R_P_GTE2048_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_P_GTE2048_COUNT_SHIFT)) & ENET_RMON_R_P_GTE2048_COUNT_MASK)
/*! @} */
/*! @name RMON_R_OCTETS - Rx Octets Statistic Register */
/*! @{ */
#define ENET_RMON_R_OCTETS_COUNT_MASK (0xFFFFFFFFU)
#define ENET_RMON_R_OCTETS_COUNT_SHIFT (0U)
/*! COUNT - Number of receive octets
*/
#define ENET_RMON_R_OCTETS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_RMON_R_OCTETS_COUNT_SHIFT)) & ENET_RMON_R_OCTETS_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_DROP - Frames not Counted Correctly Statistic Register */
/*! @{ */
#define ENET_IEEE_R_DROP_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_DROP_COUNT_SHIFT (0U)
/*! COUNT - Frame count
*/
#define ENET_IEEE_R_DROP_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_DROP_COUNT_SHIFT)) & ENET_IEEE_R_DROP_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_FRAME_OK - Frames Received OK Statistic Register */
/*! @{ */
#define ENET_IEEE_R_FRAME_OK_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_FRAME_OK_COUNT_SHIFT (0U)
/*! COUNT - Number of frames received OK
*/
#define ENET_IEEE_R_FRAME_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FRAME_OK_COUNT_SHIFT)) & ENET_IEEE_R_FRAME_OK_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_CRC - Frames Received with CRC Error Statistic Register */
/*! @{ */
#define ENET_IEEE_R_CRC_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_CRC_COUNT_SHIFT (0U)
/*! COUNT - Number of frames received with CRC error
*/
#define ENET_IEEE_R_CRC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_CRC_COUNT_SHIFT)) & ENET_IEEE_R_CRC_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_ALIGN - Frames Received with Alignment Error Statistic Register */
/*! @{ */
#define ENET_IEEE_R_ALIGN_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_ALIGN_COUNT_SHIFT (0U)
/*! COUNT - Number of frames received with alignment error
*/
#define ENET_IEEE_R_ALIGN_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_ALIGN_COUNT_SHIFT)) & ENET_IEEE_R_ALIGN_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_MACERR - Receive FIFO Overflow Count Statistic Register */
/*! @{ */
#define ENET_IEEE_R_MACERR_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_MACERR_COUNT_SHIFT (0U)
/*! COUNT - Receive FIFO overflow count
*/
#define ENET_IEEE_R_MACERR_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_MACERR_COUNT_SHIFT)) & ENET_IEEE_R_MACERR_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_FDXFC - Flow Control Pause Frames Received Statistic Register */
/*! @{ */
#define ENET_IEEE_R_FDXFC_COUNT_MASK (0xFFFFU)
#define ENET_IEEE_R_FDXFC_COUNT_SHIFT (0U)
/*! COUNT - Number of flow-control pause frames received
*/
#define ENET_IEEE_R_FDXFC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_FDXFC_COUNT_SHIFT)) & ENET_IEEE_R_FDXFC_COUNT_MASK)
/*! @} */
/*! @name IEEE_R_OCTETS_OK - Octet Count for Frames Received without Error Statistic Register */
/*! @{ */
#define ENET_IEEE_R_OCTETS_OK_COUNT_MASK (0xFFFFFFFFU)
#define ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT (0U)
/*! COUNT - Number of octets for frames received without error
*/
#define ENET_IEEE_R_OCTETS_OK_COUNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_IEEE_R_OCTETS_OK_COUNT_SHIFT)) & ENET_IEEE_R_OCTETS_OK_COUNT_MASK)
/*! @} */
/*! @name ATCR - Adjustable Timer Control Register */
/*! @{ */
#define ENET_ATCR_EN_MASK (0x1U)
#define ENET_ATCR_EN_SHIFT (0U)
/*! EN - Enable Timer
* 0b0..The timer stops at the current value.
* 0b1..The timer starts incrementing.
*/
#define ENET_ATCR_EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_EN_SHIFT)) & ENET_ATCR_EN_MASK)
#define ENET_ATCR_OFFEN_MASK (0x4U)
#define ENET_ATCR_OFFEN_SHIFT (2U)
/*! OFFEN - Enable One-Shot Offset Event
* 0b0..Disable.
* 0b1..The timer can be reset to zero when the given offset time is reached (offset event). The field is cleared
* when the offset event is reached, so no further event occurs until the field is set again. The timer
* offset value must be set before setting this field.
*/
#define ENET_ATCR_OFFEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFEN_SHIFT)) & ENET_ATCR_OFFEN_MASK)
#define ENET_ATCR_OFFRST_MASK (0x8U)
#define ENET_ATCR_OFFRST_SHIFT (3U)
/*! OFFRST - Reset Timer On Offset Event
* 0b0..The timer is not affected and no action occurs, besides clearing OFFEN, when the offset is reached.
* 0b1..If OFFEN is set, the timer resets to zero when the offset setting is reached. The offset event does not cause a timer interrupt.
*/
#define ENET_ATCR_OFFRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_OFFRST_SHIFT)) & ENET_ATCR_OFFRST_MASK)
#define ENET_ATCR_PEREN_MASK (0x10U)
#define ENET_ATCR_PEREN_SHIFT (4U)
/*! PEREN - Enable Periodical Event
* 0b0..Disable.
* 0b1..A period event interrupt can be generated (EIR[TS_TIMER]) and the event signal output is asserted when
* the timer wraps around according to the periodic setting ATPER. The timer period value must be set before
* setting this bit. Not all devices contain the event signal output. See the chip configuration details.
*/
#define ENET_ATCR_PEREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PEREN_SHIFT)) & ENET_ATCR_PEREN_MASK)
#define ENET_ATCR_PINPER_MASK (0x80U)
#define ENET_ATCR_PINPER_SHIFT (7U)
/*! PINPER - Enables event signal output external pin frc_evt_period assertion on period event
* 0b0..Disable.
* 0b1..Enable.
*/
#define ENET_ATCR_PINPER(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_PINPER_SHIFT)) & ENET_ATCR_PINPER_MASK)
#define ENET_ATCR_RESTART_MASK (0x200U)
#define ENET_ATCR_RESTART_SHIFT (9U)
/*! RESTART - Reset Timer
*/
#define ENET_ATCR_RESTART(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_RESTART_SHIFT)) & ENET_ATCR_RESTART_MASK)
#define ENET_ATCR_CAPTURE_MASK (0x800U)
#define ENET_ATCR_CAPTURE_SHIFT (11U)
/*! CAPTURE - Capture Timer Value
* 0b0..No effect.
* 0b1..The current time is captured and can be read from the ATVR register.
*/
#define ENET_ATCR_CAPTURE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_CAPTURE_SHIFT)) & ENET_ATCR_CAPTURE_MASK)
#define ENET_ATCR_SLAVE_MASK (0x2000U)
#define ENET_ATCR_SLAVE_SHIFT (13U)
/*! SLAVE - Enable Timer Slave Mode
* 0b0..The timer is active and all configuration fields in this register are relevant.
* 0b1..The internal timer is disabled and the externally provided timer value is used. All other fields, except
* CAPTURE, in this register have no effect. CAPTURE can still be used to capture the current timer value.
*/
#define ENET_ATCR_SLAVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCR_SLAVE_SHIFT)) & ENET_ATCR_SLAVE_MASK)
/*! @} */
/*! @name ATVR - Timer Value Register */
/*! @{ */
#define ENET_ATVR_ATIME_MASK (0xFFFFFFFFU)
#define ENET_ATVR_ATIME_SHIFT (0U)
#define ENET_ATVR_ATIME(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATVR_ATIME_SHIFT)) & ENET_ATVR_ATIME_MASK)
/*! @} */
/*! @name ATOFF - Timer Offset Register */
/*! @{ */
#define ENET_ATOFF_OFFSET_MASK (0xFFFFFFFFU)
#define ENET_ATOFF_OFFSET_SHIFT (0U)
#define ENET_ATOFF_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATOFF_OFFSET_SHIFT)) & ENET_ATOFF_OFFSET_MASK)
/*! @} */
/*! @name ATPER - Timer Period Register */
/*! @{ */
#define ENET_ATPER_PERIOD_MASK (0xFFFFFFFFU)
#define ENET_ATPER_PERIOD_SHIFT (0U)
/*! PERIOD - Value for generating periodic events
*/
#define ENET_ATPER_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATPER_PERIOD_SHIFT)) & ENET_ATPER_PERIOD_MASK)
/*! @} */
/*! @name ATCOR - Timer Correction Register */
/*! @{ */
#define ENET_ATCOR_COR_MASK (0x7FFFFFFFU)
#define ENET_ATCOR_COR_SHIFT (0U)
/*! COR - Correction Counter Wrap-Around Value
*/
#define ENET_ATCOR_COR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATCOR_COR_SHIFT)) & ENET_ATCOR_COR_MASK)
/*! @} */
/*! @name ATINC - Time-Stamping Clock Period Register */
/*! @{ */
#define ENET_ATINC_INC_MASK (0x7FU)
#define ENET_ATINC_INC_SHIFT (0U)
/*! INC - Clock Period Of The Timestamping Clock (ts_clk) In Nanoseconds
*/
#define ENET_ATINC_INC(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_SHIFT)) & ENET_ATINC_INC_MASK)
#define ENET_ATINC_INC_CORR_MASK (0x7F00U)
#define ENET_ATINC_INC_CORR_SHIFT (8U)
/*! INC_CORR - Correction Increment Value
*/
#define ENET_ATINC_INC_CORR(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATINC_INC_CORR_SHIFT)) & ENET_ATINC_INC_CORR_MASK)
/*! @} */
/*! @name ATSTMP - Timestamp of Last Transmitted Frame */
/*! @{ */
#define ENET_ATSTMP_TIMESTAMP_MASK (0xFFFFFFFFU)
#define ENET_ATSTMP_TIMESTAMP_SHIFT (0U)
/*! TIMESTAMP - Timestamp of the last frame transmitted by the core that had TxBD[TS] set the
* ff_tx_ts_frm signal asserted from the user application
*/
#define ENET_ATSTMP_TIMESTAMP(x) (((uint32_t)(((uint32_t)(x)) << ENET_ATSTMP_TIMESTAMP_SHIFT)) & ENET_ATSTMP_TIMESTAMP_MASK)
/*! @} */
/*! @name TGSR - Timer Global Status Register */
/*! @{ */
#define ENET_TGSR_TF0_MASK (0x1U)
#define ENET_TGSR_TF0_SHIFT (0U)
/*! TF0 - Copy Of Timer Flag For Channel 0
* 0b0..Timer Flag for Channel 0 is clear
* 0b1..Timer Flag for Channel 0 is set
*/
#define ENET_TGSR_TF0(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF0_SHIFT)) & ENET_TGSR_TF0_MASK)
#define ENET_TGSR_TF1_MASK (0x2U)
#define ENET_TGSR_TF1_SHIFT (1U)
/*! TF1 - Copy Of Timer Flag For Channel 1
* 0b0..Timer Flag for Channel 1 is clear
* 0b1..Timer Flag for Channel 1 is set
*/
#define ENET_TGSR_TF1(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF1_SHIFT)) & ENET_TGSR_TF1_MASK)
#define ENET_TGSR_TF2_MASK (0x4U)
#define ENET_TGSR_TF2_SHIFT (2U)
/*! TF2 - Copy Of Timer Flag For Channel 2
* 0b0..Timer Flag for Channel 2 is clear
* 0b1..Timer Flag for Channel 2 is set
*/
#define ENET_TGSR_TF2(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF2_SHIFT)) & ENET_TGSR_TF2_MASK)
#define ENET_TGSR_TF3_MASK (0x8U)
#define ENET_TGSR_TF3_SHIFT (3U)
/*! TF3 - Copy Of Timer Flag For Channel 3
* 0b0..Timer Flag for Channel 3 is clear
* 0b1..Timer Flag for Channel 3 is set
*/
#define ENET_TGSR_TF3(x) (((uint32_t)(((uint32_t)(x)) << ENET_TGSR_TF3_SHIFT)) & ENET_TGSR_TF3_MASK)
/*! @} */
/*! @name TCSR - Timer Control Status Register */
/*! @{ */
#define ENET_TCSR_TDRE_MASK (0x1U)
#define ENET_TCSR_TDRE_SHIFT (0U)
/*! TDRE - Timer DMA Request Enable
* 0b0..DMA request is disabled
* 0b1..DMA request is enabled
*/
#define ENET_TCSR_TDRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TDRE_SHIFT)) & ENET_TCSR_TDRE_MASK)
#define ENET_TCSR_TMODE_MASK (0x3CU)
#define ENET_TCSR_TMODE_SHIFT (2U)
/*! TMODE - Timer Mode
* 0b0000..Timer Channel is disabled.
* 0b0001..Timer Channel is configured for Input Capture on rising edge.
* 0b0010..Timer Channel is configured for Input Capture on falling edge.
* 0b0011..Timer Channel is configured for Input Capture on both edges.
* 0b0100..Timer Channel is configured for Output Compare - software only.
* 0b0101..Timer Channel is configured for Output Compare - toggle output on compare.
* 0b0110..Timer Channel is configured for Output Compare - clear output on compare.
* 0b0111..Timer Channel is configured for Output Compare - set output on compare.
* 0b1000..Reserved
* 0b1010..Timer Channel is configured for Output Compare - clear output on compare, set output on overflow.
* 0b10x1..Timer Channel is configured for Output Compare - set output on compare, clear output on overflow.
* 0b110x..Reserved
* 0b1110..Timer Channel is configured for Output Compare - pulse output low on compare for 1 to 32 1588-clock cycles as specified by TPWC.
* 0b1111..Timer Channel is configured for Output Compare - pulse output high on compare for 1 to 32 1588-clock cycles as specified by TPWC.
*/
#define ENET_TCSR_TMODE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TMODE_SHIFT)) & ENET_TCSR_TMODE_MASK)
#define ENET_TCSR_TIE_MASK (0x40U)
#define ENET_TCSR_TIE_SHIFT (6U)
/*! TIE - Timer Interrupt Enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define ENET_TCSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TIE_SHIFT)) & ENET_TCSR_TIE_MASK)
#define ENET_TCSR_TF_MASK (0x80U)
#define ENET_TCSR_TF_SHIFT (7U)
/*! TF - Timer Flag
* 0b0..Input Capture or Output Compare has not occurred.
* 0b1..Input Capture or Output Compare has occurred.
*/
#define ENET_TCSR_TF(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TF_SHIFT)) & ENET_TCSR_TF_MASK)
#define ENET_TCSR_TPWC_MASK (0xF800U)
#define ENET_TCSR_TPWC_SHIFT (11U)
/*! TPWC - Timer PulseWidth Control
* 0b00000..Pulse width is one 1588-clock cycle.
* 0b00001..Pulse width is two 1588-clock cycles.
* 0b00010..Pulse width is three 1588-clock cycles.
* 0b00011..Pulse width is four 1588-clock cycles.
* 0b11111..Pulse width is 32 1588-clock cycles.
*/
#define ENET_TCSR_TPWC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCSR_TPWC_SHIFT)) & ENET_TCSR_TPWC_MASK)
/*! @} */
/* The count of ENET_TCSR */
#define ENET_TCSR_COUNT (4U)
/*! @name TCCR - Timer Compare Capture Register */
/*! @{ */
#define ENET_TCCR_TCC_MASK (0xFFFFFFFFU)
#define ENET_TCCR_TCC_SHIFT (0U)
/*! TCC - Timer Capture Compare
*/
#define ENET_TCCR_TCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_TCCR_TCC_SHIFT)) & ENET_TCCR_TCC_MASK)
/*! @} */
/* The count of ENET_TCCR */
#define ENET_TCCR_COUNT (4U)
/*!
* @}
*/ /* end of group ENET_Register_Masks */
/* ENET - Peripheral instance base addresses */
/** Peripheral ENET base address */
#define ENET_BASE (0x40424000u)
/** Peripheral ENET base pointer */
#define ENET ((ENET_Type *)ENET_BASE)
/** Peripheral ENET_1G base address */
#define ENET_1G_BASE (0x40420000u)
/** Peripheral ENET_1G base pointer */
#define ENET_1G ((ENET_Type *)ENET_1G_BASE)
/** Array initializer of ENET peripheral base addresses */
#define ENET_BASE_ADDRS { ENET_BASE, ENET_1G_BASE }
/** Array initializer of ENET peripheral base pointers */
#define ENET_BASE_PTRS { ENET, ENET_1G }
/** Interrupt vectors for the ENET peripheral type */
#define ENET_Transmit_IRQS { ENET_IRQn, ENET_1G_IRQn }
#define ENET_Receive_IRQS { ENET_IRQn, ENET_1G_IRQn }
#define ENET_Error_IRQS { ENET_IRQn, ENET_1G_IRQn }
#define ENET_1588_Timer_IRQS { ENET_1588_Timer_IRQn, ENET_1G_1588_Timer_IRQn }
#define ENET_Ts_IRQS { ENET_IRQn, ENET_1G_IRQn }
/* ENET Buffer Descriptor and Buffer Address Alignment. */
#define ENET_BUFF_ALIGNMENT (64U)
/*!
* @}
*/ /* end of group ENET_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ENET_QOS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENET_QOS_Peripheral_Access_Layer ENET_QOS Peripheral Access Layer
* @{
*/
/** ENET_QOS - Register Layout Typedef */
typedef struct {
__IO uint32_t MAC_CONFIGURATION; /**< MAC Configuration Register, offset: 0x0 */
__IO uint32_t MAC_EXT_CONFIGURATION; /**< MAC Extended Configuration Register, offset: 0x4 */
__IO uint32_t MAC_PACKET_FILTER; /**< MAC Packet Filter, offset: 0x8 */
__IO uint32_t MAC_WATCHDOG_TIMEOUT; /**< Watchdog Timeout, offset: 0xC */
__IO uint32_t MAC_HASH_TABLE_REG0; /**< MAC Hash Table Register 0, offset: 0x10 */
__IO uint32_t MAC_HASH_TABLE_REG1; /**< MAC Hash Table Register 1, offset: 0x14 */
uint8_t RESERVED_0[56];
__IO uint32_t MAC_VLAN_TAG_CTRL; /**< MAC VLAN Tag Control, offset: 0x50 */
__IO uint32_t MAC_VLAN_TAG_DATA; /**< MAC VLAN Tag Data, offset: 0x54 */
__IO uint32_t MAC_VLAN_HASH_TABLE; /**< MAC VLAN Hash Table, offset: 0x58 */
uint8_t RESERVED_1[4];
__IO uint32_t MAC_VLAN_INCL; /**< VLAN Tag Inclusion or Replacement, offset: 0x60 */
__IO uint32_t MAC_INNER_VLAN_INCL; /**< MAC Inner VLAN Tag Inclusion or Replacement, offset: 0x64 */
uint8_t RESERVED_2[8];
__IO uint32_t MAC_TX_FLOW_CTRL_Q[5]; /**< MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control, array offset: 0x70, array step: 0x4 */
uint8_t RESERVED_3[12];
__IO uint32_t MAC_RX_FLOW_CTRL; /**< MAC Rx Flow Control, offset: 0x90 */
__IO uint32_t MAC_RXQ_CTRL4; /**< Receive Queue Control 4, offset: 0x94 */
__IO uint32_t MAC_TXQ_PRTY_MAP0; /**< Transmit Queue Priority Mapping 0, offset: 0x98 */
__IO uint32_t MAC_TXQ_PRTY_MAP1; /**< Transmit Queue Priority Mapping 1, offset: 0x9C */
__IO uint32_t MAC_RXQ_CTRL[4]; /**< Receive Queue Control 0..Receive Queue Control 3, array offset: 0xA0, array step: 0x4 */
__I uint32_t MAC_INTERRUPT_STATUS; /**< Interrupt Status, offset: 0xB0 */
__IO uint32_t MAC_INTERRUPT_ENABLE; /**< Interrupt Enable, offset: 0xB4 */
__I uint32_t MAC_RX_TX_STATUS; /**< Receive Transmit Status, offset: 0xB8 */
uint8_t RESERVED_4[4];
__IO uint32_t MAC_PMT_CONTROL_STATUS; /**< PMT Control and Status, offset: 0xC0 */
__IO uint32_t MAC_RWK_PACKET_FILTER; /**< Remote Wakeup Filter, offset: 0xC4 */
uint8_t RESERVED_5[8];
__IO uint32_t MAC_LPI_CONTROL_STATUS; /**< LPI Control and Status, offset: 0xD0 */
__IO uint32_t MAC_LPI_TIMERS_CONTROL; /**< LPI Timers Control, offset: 0xD4 */
__IO uint32_t MAC_LPI_ENTRY_TIMER; /**< Tx LPI Entry Timer Control, offset: 0xD8 */
__IO uint32_t MAC_ONEUS_TIC_COUNTER; /**< One-microsecond Reference Timer, offset: 0xDC */
uint8_t RESERVED_6[24];
__IO uint32_t MAC_PHYIF_CONTROL_STATUS; /**< PHY Interface Control and Status, offset: 0xF8 */
uint8_t RESERVED_7[20];
__I uint32_t MAC_VERSION; /**< MAC Version, offset: 0x110 */
__I uint32_t MAC_DEBUG; /**< MAC Debug, offset: 0x114 */
uint8_t RESERVED_8[4];
__I uint32_t MAC_HW_FEAT[4]; /**< Optional Features or Functions 0..Optional Features or Functions 3, array offset: 0x11C, array step: 0x4 */
uint8_t RESERVED_9[212];
__IO uint32_t MAC_MDIO_ADDRESS; /**< MDIO Address, offset: 0x200 */
__IO uint32_t MAC_MDIO_DATA; /**< MAC MDIO Data, offset: 0x204 */
uint8_t RESERVED_10[40];
__IO uint32_t MAC_CSR_SW_CTRL; /**< CSR Software Control, offset: 0x230 */
__IO uint32_t MAC_FPE_CTRL_STS; /**< Frame Preemption Control, offset: 0x234 */
uint8_t RESERVED_11[8];
__I uint32_t MAC_PRESN_TIME_NS; /**< 32-bit Binary Rollover Equivalent Time, offset: 0x240 */
__IO uint32_t MAC_PRESN_TIME_UPDT; /**< MAC 1722 Presentation Time, offset: 0x244 */
uint8_t RESERVED_12[184];
struct { /* offset: 0x300, array step: 0x8 */
__IO uint32_t HIGH; /**< MAC Address0 High..MAC Address63 High, array offset: 0x300, array step: 0x8 */
__IO uint32_t LOW; /**< MAC Address0 Low..MAC Address63 Low, array offset: 0x304, array step: 0x8 */
} MAC_ADDRESS[64];
uint8_t RESERVED_13[512];
__IO uint32_t MAC_MMC_CONTROL; /**< MMC Control, offset: 0x700 */
__I uint32_t MAC_MMC_RX_INTERRUPT; /**< MMC Rx Interrupt, offset: 0x704 */
__I uint32_t MAC_MMC_TX_INTERRUPT; /**< MMC Tx Interrupt, offset: 0x708 */
__IO uint32_t MAC_MMC_RX_INTERRUPT_MASK; /**< MMC Rx Interrupt Mask, offset: 0x70C */
__IO uint32_t MAC_MMC_TX_INTERRUPT_MASK; /**< MMC Tx Interrupt Mask, offset: 0x710 */
__I uint32_t MAC_TX_OCTET_COUNT_GOOD_BAD; /**< Tx Octet Count Good and Bad, offset: 0x714 */
__I uint32_t MAC_TX_PACKET_COUNT_GOOD_BAD; /**< Tx Packet Count Good and Bad, offset: 0x718 */
__I uint32_t MAC_TX_BROADCAST_PACKETS_GOOD; /**< Tx Broadcast Packets Good, offset: 0x71C */
__I uint32_t MAC_TX_MULTICAST_PACKETS_GOOD; /**< Tx Multicast Packets Good, offset: 0x720 */
__I uint32_t MAC_TX_64OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 64-Byte Packets, offset: 0x724 */
__I uint32_t MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 65 to 127-Byte Packets, offset: 0x728 */
__I uint32_t MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 128 to 255-Byte Packets, offset: 0x72C */
__I uint32_t MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 256 to 511-Byte Packets, offset: 0x730 */
__I uint32_t MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 512 to 1023-Byte Packets, offset: 0x734 */
__I uint32_t MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Tx Good and Bad 1024 to Max-Byte Packets, offset: 0x738 */
__I uint32_t MAC_TX_UNICAST_PACKETS_GOOD_BAD; /**< Good and Bad Unicast Packets Transmitted, offset: 0x73C */
__I uint32_t MAC_TX_MULTICAST_PACKETS_GOOD_BAD; /**< Good and Bad Multicast Packets Transmitted, offset: 0x740 */
__I uint32_t MAC_TX_BROADCAST_PACKETS_GOOD_BAD; /**< Good and Bad Broadcast Packets Transmitted, offset: 0x744 */
__I uint32_t MAC_TX_UNDERFLOW_ERROR_PACKETS; /**< Tx Packets Aborted By Underflow Error, offset: 0x748 */
__I uint32_t MAC_TX_SINGLE_COLLISION_GOOD_PACKETS; /**< Single Collision Good Packets Transmitted, offset: 0x74C */
__I uint32_t MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS; /**< Multiple Collision Good Packets Transmitted, offset: 0x750 */
__I uint32_t MAC_TX_DEFERRED_PACKETS; /**< Deferred Packets Transmitted, offset: 0x754 */
__I uint32_t MAC_TX_LATE_COLLISION_PACKETS; /**< Late Collision Packets Transmitted, offset: 0x758 */
__I uint32_t MAC_TX_EXCESSIVE_COLLISION_PACKETS; /**< Excessive Collision Packets Transmitted, offset: 0x75C */
__I uint32_t MAC_TX_CARRIER_ERROR_PACKETS; /**< Carrier Error Packets Transmitted, offset: 0x760 */
__I uint32_t MAC_TX_OCTET_COUNT_GOOD; /**< Bytes Transmitted in Good Packets, offset: 0x764 */
__I uint32_t MAC_TX_PACKET_COUNT_GOOD; /**< Good Packets Transmitted, offset: 0x768 */
__I uint32_t MAC_TX_EXCESSIVE_DEFERRAL_ERROR; /**< Packets Aborted By Excessive Deferral Error, offset: 0x76C */
__I uint32_t MAC_TX_PAUSE_PACKETS; /**< Pause Packets Transmitted, offset: 0x770 */
__I uint32_t MAC_TX_VLAN_PACKETS_GOOD; /**< Good VLAN Packets Transmitted, offset: 0x774 */
__I uint32_t MAC_TX_OSIZE_PACKETS_GOOD; /**< Good Oversize Packets Transmitted, offset: 0x778 */
uint8_t RESERVED_14[4];
__I uint32_t MAC_RX_PACKETS_COUNT_GOOD_BAD; /**< Good and Bad Packets Received, offset: 0x780 */
__I uint32_t MAC_RX_OCTET_COUNT_GOOD_BAD; /**< Bytes in Good and Bad Packets Received, offset: 0x784 */
__I uint32_t MAC_RX_OCTET_COUNT_GOOD; /**< Bytes in Good Packets Received, offset: 0x788 */
__I uint32_t MAC_RX_BROADCAST_PACKETS_GOOD; /**< Good Broadcast Packets Received, offset: 0x78C */
__I uint32_t MAC_RX_MULTICAST_PACKETS_GOOD; /**< Good Multicast Packets Received, offset: 0x790 */
__I uint32_t MAC_RX_CRC_ERROR_PACKETS; /**< CRC Error Packets Received, offset: 0x794 */
__I uint32_t MAC_RX_ALIGNMENT_ERROR_PACKETS; /**< Alignment Error Packets Received, offset: 0x798 */
__I uint32_t MAC_RX_RUNT_ERROR_PACKETS; /**< Runt Error Packets Received, offset: 0x79C */
__I uint32_t MAC_RX_JABBER_ERROR_PACKETS; /**< Jabber Error Packets Received, offset: 0x7A0 */
__I uint32_t MAC_RX_UNDERSIZE_PACKETS_GOOD; /**< Good Undersize Packets Received, offset: 0x7A4 */
__I uint32_t MAC_RX_OVERSIZE_PACKETS_GOOD; /**< Good Oversize Packets Received, offset: 0x7A8 */
__I uint32_t MAC_RX_64OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-Byte Packets Received, offset: 0x7AC */
__I uint32_t MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 64-to-127 Byte Packets Received, offset: 0x7B0 */
__I uint32_t MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 128-to-255 Byte Packets Received, offset: 0x7B4 */
__I uint32_t MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 256-to-511 Byte Packets Received, offset: 0x7B8 */
__I uint32_t MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 512-to-1023 Byte Packets Received, offset: 0x7BC */
__I uint32_t MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD; /**< Good and Bad 1024-to-Max Byte Packets Received, offset: 0x7C0 */
__I uint32_t MAC_RX_UNICAST_PACKETS_GOOD; /**< Good Unicast Packets Received, offset: 0x7C4 */
__I uint32_t MAC_RX_LENGTH_ERROR_PACKETS; /**< Length Error Packets Received, offset: 0x7C8 */
__I uint32_t MAC_RX_OUT_OF_RANGE_TYPE_PACKETS; /**< Out-of-range Type Packets Received, offset: 0x7CC */
__I uint32_t MAC_RX_PAUSE_PACKETS; /**< Pause Packets Received, offset: 0x7D0 */
__I uint32_t MAC_RX_FIFO_OVERFLOW_PACKETS; /**< Missed Packets Due to FIFO Overflow, offset: 0x7D4 */
__I uint32_t MAC_RX_VLAN_PACKETS_GOOD_BAD; /**< Good and Bad VLAN Packets Received, offset: 0x7D8 */
__I uint32_t MAC_RX_WATCHDOG_ERROR_PACKETS; /**< Watchdog Error Packets Received, offset: 0x7DC */
__I uint32_t MAC_RX_RECEIVE_ERROR_PACKETS; /**< Receive Error Packets Received, offset: 0x7E0 */
__I uint32_t MAC_RX_CONTROL_PACKETS_GOOD; /**< Good Control Packets Received, offset: 0x7E4 */
uint8_t RESERVED_15[4];
__I uint32_t MAC_TX_LPI_USEC_CNTR; /**< Microseconds Tx LPI Asserted, offset: 0x7EC */
__I uint32_t MAC_TX_LPI_TRAN_CNTR; /**< Number of Times Tx LPI Asserted, offset: 0x7F0 */
__I uint32_t MAC_RX_LPI_USEC_CNTR; /**< Microseconds Rx LPI Sampled, offset: 0x7F4 */
__I uint32_t MAC_RX_LPI_TRAN_CNTR; /**< Number of Times Rx LPI Entered, offset: 0x7F8 */
uint8_t RESERVED_16[4];
__IO uint32_t MAC_MMC_IPC_RX_INTERRUPT_MASK; /**< MMC IPC Receive Interrupt Mask, offset: 0x800 */
uint8_t RESERVED_17[4];
__I uint32_t MAC_MMC_IPC_RX_INTERRUPT; /**< MMC IPC Receive Interrupt, offset: 0x808 */
uint8_t RESERVED_18[4];
__I uint32_t MAC_RXIPV4_GOOD_PACKETS; /**< Good IPv4 Datagrams Received, offset: 0x810 */
__I uint32_t MAC_RXIPV4_HEADER_ERROR_PACKETS; /**< IPv4 Datagrams Received with Header Errors, offset: 0x814 */
__I uint32_t MAC_RXIPV4_NO_PAYLOAD_PACKETS; /**< IPv4 Datagrams Received with No Payload, offset: 0x818 */
__I uint32_t MAC_RXIPV4_FRAGMENTED_PACKETS; /**< IPv4 Datagrams Received with Fragmentation, offset: 0x81C */
__I uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS; /**< IPv4 Datagrams Received with UDP Checksum Disabled, offset: 0x820 */
__I uint32_t MAC_RXIPV6_GOOD_PACKETS; /**< Good IPv6 Datagrams Received, offset: 0x824 */
__I uint32_t MAC_RXIPV6_HEADER_ERROR_PACKETS; /**< IPv6 Datagrams Received with Header Errors, offset: 0x828 */
__I uint32_t MAC_RXIPV6_NO_PAYLOAD_PACKETS; /**< IPv6 Datagrams Received with No Payload, offset: 0x82C */
__I uint32_t MAC_RXUDP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good UDP, offset: 0x830 */
__I uint32_t MAC_RXUDP_ERROR_PACKETS; /**< IPv6 Datagrams Received with UDP Checksum Error, offset: 0x834 */
__I uint32_t MAC_RXTCP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good TCP Payload, offset: 0x838 */
__I uint32_t MAC_RXTCP_ERROR_PACKETS; /**< IPv6 Datagrams Received with TCP Checksum Error, offset: 0x83C */
__I uint32_t MAC_RXICMP_GOOD_PACKETS; /**< IPv6 Datagrams Received with Good ICMP Payload, offset: 0x840 */
__I uint32_t MAC_RXICMP_ERROR_PACKETS; /**< IPv6 Datagrams Received with ICMP Checksum Error, offset: 0x844 */
uint8_t RESERVED_19[8];
__I uint32_t MAC_RXIPV4_GOOD_OCTETS; /**< Good Bytes Received in IPv4 Datagrams, offset: 0x850 */
__I uint32_t MAC_RXIPV4_HEADER_ERROR_OCTETS; /**< Bytes Received in IPv4 Datagrams with Header Errors, offset: 0x854 */
__I uint32_t MAC_RXIPV4_NO_PAYLOAD_OCTETS; /**< Bytes Received in IPv4 Datagrams with No Payload, offset: 0x858 */
__I uint32_t MAC_RXIPV4_FRAGMENTED_OCTETS; /**< Bytes Received in Fragmented IPv4 Datagrams, offset: 0x85C */
__I uint32_t MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS; /**< Bytes Received with UDP Checksum Disabled, offset: 0x860 */
__I uint32_t MAC_RXIPV6_GOOD_OCTETS; /**< Bytes Received in Good IPv6 Datagrams, offset: 0x864 */
__I uint32_t MAC_RXIPV6_HEADER_ERROR_OCTETS; /**< Bytes Received in IPv6 Datagrams with Data Errors, offset: 0x868 */
__I uint32_t MAC_RXIPV6_NO_PAYLOAD_OCTETS; /**< Bytes Received in IPv6 Datagrams with No Payload, offset: 0x86C */
__I uint32_t MAC_RXUDP_GOOD_OCTETS; /**< Bytes Received in Good UDP Segment, offset: 0x870 */
__I uint32_t MAC_RXUDP_ERROR_OCTETS; /**< Bytes Received in UDP Segment with Checksum Errors, offset: 0x874 */
__I uint32_t MAC_RXTCP_GOOD_OCTETS; /**< Bytes Received in Good TCP Segment, offset: 0x878 */
__I uint32_t MAC_RXTCP_ERROR_OCTETS; /**< Bytes Received in TCP Segment with Checksum Errors, offset: 0x87C */
__I uint32_t MAC_RXICMP_GOOD_OCTETS; /**< Bytes Received in Good ICMP Segment, offset: 0x880 */
__I uint32_t MAC_RXICMP_ERROR_OCTETS; /**< Bytes Received in ICMP Segment with Checksum Errors, offset: 0x884 */
uint8_t RESERVED_20[24];
__I uint32_t MAC_MMC_FPE_TX_INTERRUPT; /**< MMC FPE Transmit Interrupt, offset: 0x8A0 */
__IO uint32_t MAC_MMC_FPE_TX_INTERRUPT_MASK; /**< MMC FPE Transmit Mask Interrupt, offset: 0x8A4 */
__I uint32_t MAC_MMC_TX_FPE_FRAGMENT_CNTR; /**< MMC FPE Transmitted Fragment Counter, offset: 0x8A8 */
__I uint32_t MAC_MMC_TX_HOLD_REQ_CNTR; /**< MMC FPE Transmitted Hold Request Counter, offset: 0x8AC */
uint8_t RESERVED_21[16];
__I uint32_t MAC_MMC_FPE_RX_INTERRUPT; /**< MMC FPE Receive Interrupt, offset: 0x8C0 */
__IO uint32_t MAC_MMC_FPE_RX_INTERRUPT_MASK; /**< MMC FPE Receive Interrupt Mask, offset: 0x8C4 */
__I uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR; /**< MMC Receive Packet Reassembly Error Counter, offset: 0x8C8 */
__I uint32_t MAC_MMC_RX_PACKET_SMD_ERR_CNTR; /**< MMC Receive Packet SMD Error Counter, offset: 0x8CC */
__I uint32_t MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR; /**< MMC Receive Packet Successful Reassembly Counter, offset: 0x8D0 */
__I uint32_t MAC_MMC_RX_FPE_FRAGMENT_CNTR; /**< MMC FPE Received Fragment Counter, offset: 0x8D4 */
uint8_t RESERVED_22[40];
__IO uint32_t MAC_L3_L4_CONTROL0; /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0x900 */
__IO uint32_t MAC_LAYER4_ADDRESS0; /**< Layer 4 Address 0, offset: 0x904 */
uint8_t RESERVED_23[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG0; /**< Layer 3 Address 0 Register 0, offset: 0x910 */
__IO uint32_t MAC_LAYER3_ADDR1_REG0; /**< Layer 3 Address 1 Register 0, offset: 0x914 */
__IO uint32_t MAC_LAYER3_ADDR2_REG0; /**< Layer 3 Address 2 Register 0, offset: 0x918 */
__IO uint32_t MAC_LAYER3_ADDR3_REG0; /**< Layer 3 Address 3 Register 0, offset: 0x91C */
uint8_t RESERVED_24[16];
__IO uint32_t MAC_L3_L4_CONTROL1; /**< Layer 3 and Layer 4 Control of Filter 1, offset: 0x930 */
__IO uint32_t MAC_LAYER4_ADDRESS1; /**< Layer 4 Address 0, offset: 0x934 */
uint8_t RESERVED_25[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG1; /**< Layer 3 Address 0 Register 1, offset: 0x940 */
__IO uint32_t MAC_LAYER3_ADDR1_REG1; /**< Layer 3 Address 1 Register 1, offset: 0x944 */
__IO uint32_t MAC_LAYER3_ADDR2_REG1; /**< Layer 3 Address 2 Register 1, offset: 0x948 */
__IO uint32_t MAC_LAYER3_ADDR3_REG1; /**< Layer 3 Address 3 Register 1, offset: 0x94C */
uint8_t RESERVED_26[16];
__IO uint32_t MAC_L3_L4_CONTROL2; /**< Layer 3 and Layer 4 Control of Filter 2, offset: 0x960 */
__IO uint32_t MAC_LAYER4_ADDRESS2; /**< Layer 4 Address 2, offset: 0x964 */
uint8_t RESERVED_27[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG2; /**< Layer 3 Address 0 Register 2, offset: 0x970 */
__IO uint32_t MAC_LAYER3_ADDR1_REG2; /**< Layer 3 Address 0 Register 2, offset: 0x974 */
__IO uint32_t MAC_LAYER3_ADDR2_REG2; /**< Layer 3 Address 2 Register 2, offset: 0x978 */
__IO uint32_t MAC_LAYER3_ADDR3_REG2; /**< Layer 3 Address 3 Register 2, offset: 0x97C */
uint8_t RESERVED_28[16];
__IO uint32_t MAC_L3_L4_CONTROL3; /**< Layer 3 and Layer 4 Control of Filter 3, offset: 0x990 */
__IO uint32_t MAC_LAYER4_ADDRESS3; /**< Layer 4 Address 3, offset: 0x994 */
uint8_t RESERVED_29[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG3; /**< Layer 3 Address 0 Register 3, offset: 0x9A0 */
__IO uint32_t MAC_LAYER3_ADDR1_REG3; /**< Layer 3 Address 1 Register 3, offset: 0x9A4 */
__IO uint32_t MAC_LAYER3_ADDR2_REG3; /**< Layer 3 Address 2 Register 3, offset: 0x9A8 */
__IO uint32_t MAC_LAYER3_ADDR3_REG3; /**< Layer 3 Address 3 Register 3, offset: 0x9AC */
uint8_t RESERVED_30[16];
__IO uint32_t MAC_L3_L4_CONTROL4; /**< Layer 3 and Layer 4 Control of Filter 4, offset: 0x9C0 */
__IO uint32_t MAC_LAYER4_ADDRESS4; /**< Layer 4 Address 4, offset: 0x9C4 */
uint8_t RESERVED_31[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG4; /**< Layer 3 Address 0 Register 4, offset: 0x9D0 */
__IO uint32_t MAC_LAYER3_ADDR1_REG4; /**< Layer 3 Address 1 Register 4, offset: 0x9D4 */
__IO uint32_t MAC_LAYER3_ADDR2_REG4; /**< Layer 3 Address 2 Register 4, offset: 0x9D8 */
__IO uint32_t MAC_LAYER3_ADDR3_REG4; /**< Layer 3 Address 3 Register 4, offset: 0x9DC */
uint8_t RESERVED_32[16];
__IO uint32_t MAC_L3_L4_CONTROL5; /**< Layer 3 and Layer 4 Control of Filter 5, offset: 0x9F0 */
__IO uint32_t MAC_LAYER4_ADDRESS5; /**< Layer 4 Address 5, offset: 0x9F4 */
uint8_t RESERVED_33[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG5; /**< Layer 3 Address 0 Register 5, offset: 0xA00 */
__IO uint32_t MAC_LAYER3_ADDR1_REG5; /**< Layer 3 Address 1 Register 5, offset: 0xA04 */
__IO uint32_t MAC_LAYER3_ADDR2_REG5; /**< Layer 3 Address 2 Register 5, offset: 0xA08 */
__IO uint32_t MAC_LAYER3_ADDR3_REG5; /**< Layer 3 Address 3 Register 5, offset: 0xA0C */
uint8_t RESERVED_34[16];
__IO uint32_t MAC_L3_L4_CONTROL6; /**< Layer 3 and Layer 4 Control of Filter 6, offset: 0xA20 */
__IO uint32_t MAC_LAYER4_ADDRESS6; /**< Layer 4 Address 6, offset: 0xA24 */
uint8_t RESERVED_35[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG6; /**< Layer 3 Address 0 Register 6, offset: 0xA30 */
__IO uint32_t MAC_LAYER3_ADDR1_REG6; /**< Layer 3 Address 1 Register 6, offset: 0xA34 */
__IO uint32_t MAC_LAYER3_ADDR2_REG6; /**< Layer 3 Address 2 Register 6, offset: 0xA38 */
__IO uint32_t MAC_LAYER3_ADDR3_REG6; /**< Layer 3 Address 3 Register 6, offset: 0xA3C */
uint8_t RESERVED_36[16];
__IO uint32_t MAC_L3_L4_CONTROL7; /**< Layer 3 and Layer 4 Control of Filter 0, offset: 0xA50 */
__IO uint32_t MAC_LAYER4_ADDRESS7; /**< Layer 4 Address 7, offset: 0xA54 */
uint8_t RESERVED_37[8];
__IO uint32_t MAC_LAYER3_ADDR0_REG7; /**< Layer 3 Address 0 Register 7, offset: 0xA60 */
__IO uint32_t MAC_LAYER3_ADDR1_REG7; /**< Layer 3 Address 1 Register 7, offset: 0xA64 */
__IO uint32_t MAC_LAYER3_ADDR2_REG7; /**< Layer 3 Address 2 Register 7, offset: 0xA68 */
__IO uint32_t MAC_LAYER3_ADDR3_REG7; /**< Layer 3 Address 3 Register 7, offset: 0xA6C */
uint8_t RESERVED_38[144];
__IO uint32_t MAC_TIMESTAMP_CONTROL; /**< Timestamp Control, offset: 0xB00 */
__IO uint32_t MAC_SUB_SECOND_INCREMENT; /**< Subsecond Increment, offset: 0xB04 */
__I uint32_t MAC_SYSTEM_TIME_SECONDS; /**< System Time Seconds, offset: 0xB08 */
__I uint32_t MAC_SYSTEM_TIME_NANOSECONDS; /**< System Time Nanoseconds, offset: 0xB0C */
__IO uint32_t MAC_SYSTEM_TIME_SECONDS_UPDATE; /**< System Time Seconds Update, offset: 0xB10 */
__IO uint32_t MAC_SYSTEM_TIME_NANOSECONDS_UPDATE; /**< System Time Nanoseconds Update, offset: 0xB14 */
__IO uint32_t MAC_TIMESTAMP_ADDEND; /**< Timestamp Addend, offset: 0xB18 */
__IO uint32_t MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS; /**< System Time - Higher Word Seconds, offset: 0xB1C */
__I uint32_t MAC_TIMESTAMP_STATUS; /**< Timestamp Status, offset: 0xB20 */
uint8_t RESERVED_39[12];
__I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Transmit Timestamp Status Nanoseconds, offset: 0xB30 */
__I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Transmit Timestamp Status Seconds, offset: 0xB34 */
uint8_t RESERVED_40[8];
__IO uint32_t MAC_AUXILIARY_CONTROL; /**< Auxiliary Timestamp Control, offset: 0xB40 */
uint8_t RESERVED_41[4];
__I uint32_t MAC_AUXILIARY_TIMESTAMP_NANOSECONDS; /**< Auxiliary Timestamp Nanoseconds, offset: 0xB48 */
__I uint32_t MAC_AUXILIARY_TIMESTAMP_SECONDS; /**< Auxiliary Timestamp Seconds, offset: 0xB4C */
__IO uint32_t MAC_TIMESTAMP_INGRESS_ASYM_CORR; /**< Timestamp Ingress Asymmetry Correction, offset: 0xB50 */
__IO uint32_t MAC_TIMESTAMP_EGRESS_ASYM_CORR; /**< imestamp Egress Asymmetry Correction, offset: 0xB54 */
__IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp Ingress Correction Nanosecond, offset: 0xB58 */
__IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp Egress Correction Nanosecond, offset: 0xB5C */
__IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC; /**< Timestamp Ingress Correction Subnanosecond, offset: 0xB60 */
__IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC; /**< Timestamp Egress Correction Subnanosecond, offset: 0xB64 */
__I uint32_t MAC_TIMESTAMP_INGRESS_LATENCY; /**< Timestamp Ingress Latency, offset: 0xB68 */
__I uint32_t MAC_TIMESTAMP_EGRESS_LATENCY; /**< Timestamp Egress Latency, offset: 0xB6C */
__IO uint32_t MAC_PPS_CONTROL; /**< PPS Control, offset: 0xB70 */
uint8_t RESERVED_42[12];
__IO uint32_t MAC_PPS0_TARGET_TIME_SECONDS; /**< PPS0 Target Time Seconds, offset: 0xB80 */
__IO uint32_t MAC_PPS0_TARGET_TIME_NANOSECONDS; /**< PPS0 Target Time Nanoseconds, offset: 0xB84 */
__IO uint32_t MAC_PPS0_INTERVAL; /**< PPS0 Interval, offset: 0xB88 */
__IO uint32_t MAC_PPS0_WIDTH; /**< PPS0 Width, offset: 0xB8C */
__IO uint32_t MAC_PPS1_TARGET_TIME_SECONDS; /**< PPS1 Target Time Seconds, offset: 0xB90 */
__IO uint32_t MAC_PPS1_TARGET_TIME_NANOSECONDS; /**< PPS1 Target Time Nanoseconds, offset: 0xB94 */
__IO uint32_t MAC_PPS1_INTERVAL; /**< PPS1 Interval, offset: 0xB98 */
__IO uint32_t MAC_PPS1_WIDTH; /**< PPS1 Width, offset: 0xB9C */
__IO uint32_t MAC_PPS2_TARGET_TIME_SECONDS; /**< PPS2 Target Time Seconds, offset: 0xBA0 */
__IO uint32_t MAC_PPS2_TARGET_TIME_NANOSECONDS; /**< PPS2 Target Time Nanoseconds, offset: 0xBA4 */
__IO uint32_t MAC_PPS2_INTERVAL; /**< PPS2 Interval, offset: 0xBA8 */
__IO uint32_t MAC_PPS2_WIDTH; /**< PPS2 Width, offset: 0xBAC */
__IO uint32_t MAC_PPS3_TARGET_TIME_SECONDS; /**< PPS3 Target Time Seconds, offset: 0xBB0 */
__IO uint32_t MAC_PPS3_TARGET_TIME_NANOSECONDS; /**< PPS3 Target Time Nanoseconds, offset: 0xBB4 */
__IO uint32_t MAC_PPS3_INTERVAL; /**< PPS3 Interval, offset: 0xBB8 */
__IO uint32_t MAC_PPS3_WIDTH; /**< PPS3 Width, offset: 0xBBC */
__IO uint32_t MAC_PTO_CONTROL; /**< PTP Offload Engine Control, offset: 0xBC0 */
__IO uint32_t MAC_SOURCE_PORT_IDENTITY0; /**< Source Port Identity 0, offset: 0xBC4 */
__IO uint32_t MAC_SOURCE_PORT_IDENTITY1; /**< Source Port Identity 1, offset: 0xBC8 */
__IO uint32_t MAC_SOURCE_PORT_IDENTITY2; /**< Source Port Identity 2, offset: 0xBCC */
__IO uint32_t MAC_LOG_MESSAGE_INTERVAL; /**< Log Message Interval, offset: 0xBD0 */
uint8_t RESERVED_43[44];
__IO uint32_t MTL_OPERATION_MODE; /**< MTL Operation Mode, offset: 0xC00 */
uint8_t RESERVED_44[4];
__IO uint32_t MTL_DBG_CTL; /**< FIFO Debug Access Control and Status, offset: 0xC08 */
__IO uint32_t MTL_DBG_STS; /**< FIFO Debug Status, offset: 0xC0C */
__IO uint32_t MTL_FIFO_DEBUG_DATA; /**< FIFO Debug Data, offset: 0xC10 */
uint8_t RESERVED_45[12];
__I uint32_t MTL_INTERRUPT_STATUS; /**< MTL Interrupt Status, offset: 0xC20 */
uint8_t RESERVED_46[12];
__IO uint32_t MTL_RXQ_DMA_MAP0; /**< Receive Queue and DMA Channel Mapping 0, offset: 0xC30 */
__IO uint32_t MTL_RXQ_DMA_MAP1; /**< Receive Queue and DMA Channel Mapping 1, offset: 0xC34 */
uint8_t RESERVED_47[8];
__IO uint32_t MTL_TBS_CTRL; /**< Time Based Scheduling Control, offset: 0xC40 */
uint8_t RESERVED_48[12];
__IO uint32_t MTL_EST_CONTROL; /**< Enhancements to Scheduled Transmission Control, offset: 0xC50 */
uint8_t RESERVED_49[4];
__IO uint32_t MTL_EST_STATUS; /**< Enhancements to Scheduled Transmission Status, offset: 0xC58 */
uint8_t RESERVED_50[4];
__IO uint32_t MTL_EST_SCH_ERROR; /**< EST Scheduling Error, offset: 0xC60 */
__IO uint32_t MTL_EST_FRM_SIZE_ERROR; /**< EST Frame Size Error, offset: 0xC64 */
__I uint32_t MTL_EST_FRM_SIZE_CAPTURE; /**< EST Frame Size Capture, offset: 0xC68 */
uint8_t RESERVED_51[4];
__IO uint32_t MTL_EST_INTR_ENABLE; /**< EST Interrupt Enable, offset: 0xC70 */
uint8_t RESERVED_52[12];
__IO uint32_t MTL_EST_GCL_CONTROL; /**< EST GCL Control, offset: 0xC80 */
__IO uint32_t MTL_EST_GCL_DATA; /**< EST GCL Data, offset: 0xC84 */
uint8_t RESERVED_53[8];
__IO uint32_t MTL_FPE_CTRL_STS; /**< Frame Preemption Control and Status, offset: 0xC90 */
__IO uint32_t MTL_FPE_ADVANCE; /**< Frame Preemption Hold and Release Advance, offset: 0xC94 */
uint8_t RESERVED_54[8];
__IO uint32_t MTL_RXP_CONTROL_STATUS; /**< RXP Control Status, offset: 0xCA0 */
__IO uint32_t MTL_RXP_INTERRUPT_CONTROL_STATUS; /**< RXP Interrupt Control Status, offset: 0xCA4 */
__I uint32_t MTL_RXP_DROP_CNT; /**< RXP Drop Count, offset: 0xCA8 */
__I uint32_t MTL_RXP_ERROR_CNT; /**< RXP Error Count, offset: 0xCAC */
__IO uint32_t MTL_RXP_INDIRECT_ACC_CONTROL_STATUS; /**< RXP Indirect Access Control and Status, offset: 0xCB0 */
__IO uint32_t MTL_RXP_INDIRECT_ACC_DATA; /**< RXP Indirect Access Data, offset: 0xCB4 */
uint8_t RESERVED_55[72];
struct { /* offset: 0xD00, array step: 0x40 */
__IO uint32_t MTL_TXQX_OP_MODE; /**< Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode, array offset: 0xD00, array step: 0x40 */
__I uint32_t MTL_TXQX_UNDRFLW; /**< Queue 0 Underflow Counter..Queue 4 Underflow Counter, array offset: 0xD04, array step: 0x40 */
__I uint32_t MTL_TXQX_DBG; /**< Queue 0 Transmit Debug..Queue 4 Transmit Debug, array offset: 0xD08, array step: 0x40 */
uint8_t RESERVED_0[4];
__IO uint32_t MTL_TXQX_ETS_CTRL; /**< Queue 1 ETS Control..Queue 4 ETS Control, array offset: 0xD10, array step: 0x40 */
__I uint32_t MTL_TXQX_ETS_STAT; /**< Queue 0 ETS Status..Queue 4 ETS Status, array offset: 0xD14, array step: 0x40 */
__IO uint32_t MTL_TXQX_QNTM_WGHT; /**< Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights, array offset: 0xD18, array step: 0x40 */
__IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit, array offset: 0xD1C, array step: 0x40 */
__IO uint32_t MTL_TXQX_HI_CRDT; /**< Queue 1 hiCredit..Queue 4 hiCredit, array offset: 0xD20, array step: 0x40 */
__IO uint32_t MTL_TXQX_LO_CRDT; /**< Queue 1 loCredit..Queue 4 loCredit, array offset: 0xD24, array step: 0x40 */
uint8_t RESERVED_1[4];
__IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status, array offset: 0xD2C, array step: 0x40 */
__IO uint32_t MTL_RXQX_OP_MODE; /**< Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode, array offset: 0xD30, array step: 0x40 */
__I uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter, array offset: 0xD34, array step: 0x40 */
__I uint32_t MTL_RXQX_DBG; /**< Queue 0 Receive Debug..Queue 4 Receive Debug, array offset: 0xD38, array step: 0x40 */
__IO uint32_t MTL_RXQX_CTRL; /**< Queue 0 Receive Control..Queue 4 Receive Control, array offset: 0xD3C, array step: 0x40 */
} MTL_QUEUE[5];
uint8_t RESERVED_56[448];
__IO uint32_t DMA_MODE; /**< DMA Bus Mode, offset: 0x1000 */
__IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus Mode, offset: 0x1004 */
__I uint32_t DMA_INTERRUPT_STATUS; /**< DMA Interrupt Status, offset: 0x1008 */
__I uint32_t DMA_DEBUG_STATUS0; /**< DMA Debug Status 0, offset: 0x100C */
__I uint32_t DMA_DEBUG_STATUS1; /**< DMA Debug Status 1, offset: 0x1010 */
uint8_t RESERVED_57[44];
__IO uint32_t DMA_AXI_LPI_ENTRY_INTERVAL; /**< AXI LPI Entry Interval Control, offset: 0x1040 */
uint8_t RESERVED_58[12];
__IO uint32_t DMA_TBS_CTRL; /**< TBS Control, offset: 0x1050 */
uint8_t RESERVED_59[172];
struct { /* offset: 0x1100, array step: 0x80 */
__IO uint32_t DMA_CHX_CTRL; /**< DMA Channel 0 Control..DMA Channel 4 Control, array offset: 0x1100, array step: 0x80 */
__IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control, array offset: 0x1104, array step: 0x80 */
__IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channel 0 Receive Control..DMA Channel 4 Receive Control, array offset: 0x1108, array step: 0x80 */
uint8_t RESERVED_0[8];
__IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address, array offset: 0x1114, array step: 0x80 */
uint8_t RESERVED_1[4];
__IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address, array offset: 0x111C, array step: 0x80 */
__IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer, array offset: 0x1120, array step: 0x80 */
uint8_t RESERVED_2[4];
__IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer, array offset: 0x1128, array step: 0x80 */
__IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length, array offset: 0x112C, array step: 0x80 */
__IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
__IO uint32_t DMA_CHX_INT_EN; /**< Channel 0 Interrupt Enable..Channel 4 Interrupt Enable, array offset: 0x1134, array step: 0x80 */
__IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
__IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
uint8_t RESERVED_3[4];
__I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor, array offset: 0x1144, array step: 0x80 */
uint8_t RESERVED_4[4];
__I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor, array offset: 0x114C, array step: 0x80 */
uint8_t RESERVED_5[4];
__I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address, array offset: 0x1154, array step: 0x80 */
uint8_t RESERVED_6[4];
__I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
__IO uint32_t DMA_CHX_STAT; /**< DMA Channel 0 Status..DMA Channel 4 Status, array offset: 0x1160, array step: 0x80 */
__I uint32_t DMA_CHX_MISS_FRAME_CNT; /**< Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter, array offset: 0x1164, array step: 0x80 */
__I uint32_t DMA_CHX_RXP_ACCEPT_CNT; /**< Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter, array offset: 0x1168, array step: 0x80 */
__I uint32_t DMA_CHX_RX_ERI_CNT; /**< Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter, array offset: 0x116C, array step: 0x80 */
uint8_t RESERVED_7[16];
} DMA_CH[5];
} ENET_QOS_Type;
/* ----------------------------------------------------------------------------
-- ENET_QOS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ENET_QOS_Register_Masks ENET_QOS Register Masks
* @{
*/
/*! @name MAC_CONFIGURATION - MAC Configuration Register */
/*! @{ */
#define ENET_QOS_MAC_CONFIGURATION_RE_MASK (0x1U)
#define ENET_QOS_MAC_CONFIGURATION_RE_SHIFT (0U)
/*! RE - Receiver Enable
* 0b0..Receiver is disabled
* 0b1..Receiver is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_RE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_RE_MASK)
#define ENET_QOS_MAC_CONFIGURATION_TE_MASK (0x2U)
#define ENET_QOS_MAC_CONFIGURATION_TE_SHIFT (1U)
/*! TE - Transmitter Enable
* 0b0..Transmitter is disabled
* 0b1..Transmitter is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_TE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_TE_MASK)
#define ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK (0xCU)
#define ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT (2U)
/*! PRELEN - Preamble Length for Transmit packets
* 0b10..3 bytes of preamble
* 0b01..5 bytes of preamble
* 0b00..7 bytes of preamble
* 0b11..Reserved
*/
#define ENET_QOS_MAC_CONFIGURATION_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PRELEN_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PRELEN_MASK)
#define ENET_QOS_MAC_CONFIGURATION_DC_MASK (0x10U)
#define ENET_QOS_MAC_CONFIGURATION_DC_SHIFT (4U)
/*! DC - Deferral Check
* 0b0..Deferral check function is disabled
* 0b1..Deferral check function is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DC_MASK)
#define ENET_QOS_MAC_CONFIGURATION_BL_MASK (0x60U)
#define ENET_QOS_MAC_CONFIGURATION_BL_SHIFT (5U)
/*! BL - Back-Off Limit
* 0b11..k = min(n,1)
* 0b00..k = min(n,10)
* 0b10..k = min(n,4)
* 0b01..k = min(n,8)
*/
#define ENET_QOS_MAC_CONFIGURATION_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BL_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BL_MASK)
#define ENET_QOS_MAC_CONFIGURATION_DR_MASK (0x100U)
#define ENET_QOS_MAC_CONFIGURATION_DR_SHIFT (8U)
/*! DR - Disable Retry
* 0b1..Disable Retry
* 0b0..Enable Retry
*/
#define ENET_QOS_MAC_CONFIGURATION_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DR_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DR_MASK)
#define ENET_QOS_MAC_CONFIGURATION_DCRS_MASK (0x200U)
#define ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT (9U)
/*! DCRS - Disable Carrier Sense During Transmission
* 0b1..Disable Carrier Sense During Transmission
* 0b0..Enable Carrier Sense During Transmission
*/
#define ENET_QOS_MAC_CONFIGURATION_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DCRS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DCRS_MASK)
#define ENET_QOS_MAC_CONFIGURATION_DO_MASK (0x400U)
#define ENET_QOS_MAC_CONFIGURATION_DO_SHIFT (10U)
/*! DO - Disable Receive Own
* 0b1..Disable Receive Own
* 0b0..Enable Receive Own
*/
#define ENET_QOS_MAC_CONFIGURATION_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DO_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DO_MASK)
#define ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK (0x800U)
#define ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT (11U)
/*! ECRSFD - Enable Carrier Sense Before Transmission in Full-Duplex Mode
* 0b0..ECRSFD is disabled
* 0b1..ECRSFD is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ECRSFD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ECRSFD_MASK)
#define ENET_QOS_MAC_CONFIGURATION_LM_MASK (0x1000U)
#define ENET_QOS_MAC_CONFIGURATION_LM_SHIFT (12U)
/*! LM - Loopback Mode
* 0b0..Loopback is disabled
* 0b1..Loopback is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_LM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_LM_MASK)
#define ENET_QOS_MAC_CONFIGURATION_DM_MASK (0x2000U)
#define ENET_QOS_MAC_CONFIGURATION_DM_SHIFT (13U)
/*! DM - Duplex Mode
* 0b1..Full-duplex mode
* 0b0..Half-duplex mode
*/
#define ENET_QOS_MAC_CONFIGURATION_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_DM_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_DM_MASK)
#define ENET_QOS_MAC_CONFIGURATION_FES_MASK (0x4000U)
#define ENET_QOS_MAC_CONFIGURATION_FES_SHIFT (14U)
/*! FES - Speed
* 0b1..100 Mbps when PS bit is 1 and 2.5 Gbps when PS bit is 0
* 0b0..10 Mbps when PS bit is 1 and 1 Gbps when PS bit is 0
*/
#define ENET_QOS_MAC_CONFIGURATION_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_FES_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_FES_MASK)
#define ENET_QOS_MAC_CONFIGURATION_PS_MASK (0x8000U)
#define ENET_QOS_MAC_CONFIGURATION_PS_SHIFT (15U)
/*! PS - Port Select
* 0b0..For 1000 or 2500 Mbps operations
* 0b1..For 10 or 100 Mbps operations
*/
#define ENET_QOS_MAC_CONFIGURATION_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_PS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_PS_MASK)
#define ENET_QOS_MAC_CONFIGURATION_JE_MASK (0x10000U)
#define ENET_QOS_MAC_CONFIGURATION_JE_SHIFT (16U)
/*! JE - Jumbo Packet Enable When this bit is set, the MAC allows jumbo packets of 9,018 bytes
* (9,022 bytes for VLAN tagged packets) without reporting a giant packet error in the Rx packet
* status.
* 0b0..Jumbo packet is disabled
* 0b1..Jumbo packet is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JE_MASK)
#define ENET_QOS_MAC_CONFIGURATION_JD_MASK (0x20000U)
#define ENET_QOS_MAC_CONFIGURATION_JD_SHIFT (17U)
/*! JD - Jabber Disable
* 0b1..Jabber is disabled
* 0b0..Jabber is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_JD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_JD_MASK)
#define ENET_QOS_MAC_CONFIGURATION_BE_MASK (0x40000U)
#define ENET_QOS_MAC_CONFIGURATION_BE_SHIFT (18U)
/*! BE - Packet Burst Enable When this bit is set, the MAC allows packet bursting during
* transmission in the GMII half-duplex mode.
* 0b0..Packet Burst is disabled
* 0b1..Packet Burst is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_BE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_BE_MASK)
#define ENET_QOS_MAC_CONFIGURATION_WD_MASK (0x80000U)
#define ENET_QOS_MAC_CONFIGURATION_WD_SHIFT (19U)
/*! WD - Watchdog Disable
* 0b1..Watchdog is disabled
* 0b0..Watchdog is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_WD_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_WD_MASK)
#define ENET_QOS_MAC_CONFIGURATION_ACS_MASK (0x100000U)
#define ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT (20U)
/*! ACS - Automatic Pad or CRC Stripping When this bit is set, the MAC strips the Pad or FCS field
* on the incoming packets only if the value of the length field is less than 1,536 bytes.
* 0b0..Automatic Pad or CRC Stripping is disabled
* 0b1..Automatic Pad or CRC Stripping is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_ACS_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_ACS_MASK)
#define ENET_QOS_MAC_CONFIGURATION_CST_MASK (0x200000U)
#define ENET_QOS_MAC_CONFIGURATION_CST_SHIFT (21U)
/*! CST - CRC stripping for Type packets When this bit is set, the last four bytes (FCS) of all
* packets of Ether type (type field greater than 1,536) are stripped and dropped before forwarding
* the packet to the application.
* 0b0..CRC stripping for Type packets is disabled
* 0b1..CRC stripping for Type packets is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_CST_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_CST_MASK)
#define ENET_QOS_MAC_CONFIGURATION_S2KP_MASK (0x400000U)
#define ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT (22U)
/*! S2KP - IEEE 802.
* 0b0..Support upto 2K packet is disabled
* 0b1..Support upto 2K packet is Enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_S2KP_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_S2KP_MASK)
#define ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK (0x800000U)
#define ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT (23U)
/*! GPSLCE - Giant Packet Size Limit Control Enable
* 0b0..Giant Packet Size Limit Control is disabled
* 0b1..Giant Packet Size Limit Control is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_GPSLCE_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_GPSLCE_MASK)
#define ENET_QOS_MAC_CONFIGURATION_IPG_MASK (0x7000000U)
#define ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT (24U)
/*! IPG - Inter-Packet Gap These bits control the minimum IPG between packets during transmission.
* 0b111..40 bit times IPG
* 0b110..48 bit times IPG
* 0b101..56 bit times IPG
* 0b100..64 bit times IPG
* 0b011..72 bit times IPG
* 0b010..80 bit times IPG
* 0b001..88 bit times IPG
* 0b000..96 bit times IPG
*/
#define ENET_QOS_MAC_CONFIGURATION_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPG_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPG_MASK)
#define ENET_QOS_MAC_CONFIGURATION_IPC_MASK (0x8000000U)
#define ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT (27U)
/*! IPC - Checksum Offload
* 0b0..IP header/payload checksum checking is disabled
* 0b1..IP header/payload checksum checking is enabled
*/
#define ENET_QOS_MAC_CONFIGURATION_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_IPC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_IPC_MASK)
#define ENET_QOS_MAC_CONFIGURATION_SARC_MASK (0x70000000U)
#define ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT (28U)
/*! SARC - Source Address Insertion or Replacement Control
* 0b010..Contents of MAC Addr-0 inserted in SA field
* 0b011..Contents of MAC Addr-0 replaces SA field
* 0b110..Contents of MAC Addr-1 inserted in SA field
* 0b111..Contents of MAC Addr-1 replaces SA field
* 0b000..mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation
*/
#define ENET_QOS_MAC_CONFIGURATION_SARC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CONFIGURATION_SARC_SHIFT)) & ENET_QOS_MAC_CONFIGURATION_SARC_MASK)
/*! @} */
/*! @name MAC_EXT_CONFIGURATION - MAC Extended Configuration Register */
/*! @{ */
#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK (0x3FFFU)
#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT (0U)
/*! GPSL - Giant Packet Size Limit
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_GPSL_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK (0x10000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT (16U)
/*! DCRCC - Disable CRC Checking for Received Packets
* 0b1..CRC Checking is disabled
* 0b0..CRC Checking is enabled
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_DCRCC_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK (0x20000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT (17U)
/*! SPEN - Slow Protocol Detection Enable
* 0b0..Slow Protocol Detection is disabled
* 0b1..Slow Protocol Detection is enabled
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_SPEN_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK (0x40000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT (18U)
/*! USP - Unicast Slow Protocol Packet Detect
* 0b0..Unicast Slow Protocol Packet Detection is disabled
* 0b1..Unicast Slow Protocol Packet Detection is enabled
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_USP_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_USP_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK (0x80000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT (19U)
/*! PDC - Packet Duplication Control
* 0b0..Packet Duplication Control is disabled
* 0b1..Packet Duplication Control is enabled
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_PDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_PDC_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_PDC_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK (0x1000000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT (24U)
/*! EIPGEN - Extended Inter-Packet Gap Enable
* 0b0..Extended Inter-Packet Gap is disabled
* 0b1..Extended Inter-Packet Gap is enabled
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPGEN_MASK)
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK (0x3E000000U)
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT (25U)
/*! EIPG - Extended Inter-Packet Gap
*/
#define ENET_QOS_MAC_EXT_CONFIGURATION_EIPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_SHIFT)) & ENET_QOS_MAC_EXT_CONFIGURATION_EIPG_MASK)
/*! @} */
/*! @name MAC_PACKET_FILTER - MAC Packet Filter */
/*! @{ */
#define ENET_QOS_MAC_PACKET_FILTER_PR_MASK (0x1U)
#define ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT (0U)
/*! PR - Promiscuous Mode
* 0b0..Promiscuous Mode is disabled
* 0b1..Promiscuous Mode is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PR_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PR_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_HUC_MASK (0x2U)
#define ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT (1U)
/*! HUC - Hash Unicast
* 0b0..Hash Unicast is disabled
* 0b1..Hash Unicast is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_HUC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HUC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HUC_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_HMC_MASK (0x4U)
#define ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT (2U)
/*! HMC - Hash Multicast
* 0b0..Hash Multicast is disabled
* 0b1..Hash Multicast is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_HMC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HMC_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HMC_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK (0x8U)
#define ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT (3U)
/*! DAIF - DA Inverse Filtering
* 0b0..DA Inverse Filtering is disabled
* 0b1..DA Inverse Filtering is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DAIF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_PM_MASK (0x10U)
#define ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT (4U)
/*! PM - Pass All Multicast
* 0b0..Pass All Multicast is disabled
* 0b1..Pass All Multicast is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PM_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PM_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_DBF_MASK (0x20U)
#define ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT (5U)
/*! DBF - Disable Broadcast Packets
* 0b1..Disable Broadcast Packets
* 0b0..Enable Broadcast Packets
*/
#define ENET_QOS_MAC_PACKET_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DBF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DBF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_PCF_MASK (0xC0U)
#define ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT (6U)
/*! PCF - Pass Control Packets These bits control the forwarding of all control packets (including
* unicast and multicast Pause packets).
* 0b00..MAC filters all control packets from reaching the application
* 0b10..MAC forwards all control packets to the application even if they fail the Address filter
* 0b11..MAC forwards the control packets that pass the Address filter
* 0b01..MAC forwards all control packets except Pause packets to the application even if they fail the Address filter
*/
#define ENET_QOS_MAC_PACKET_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_PCF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_PCF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK (0x100U)
#define ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT (8U)
/*! SAIF - SA Inverse Filtering
* 0b0..SA Inverse Filtering is disabled
* 0b1..SA Inverse Filtering is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAIF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAIF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_SAF_MASK (0x200U)
#define ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT (9U)
/*! SAF - Source Address Filter Enable
* 0b0..SA Filtering is disabled
* 0b1..SA Filtering is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_SAF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_SAF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_HPF_MASK (0x400U)
#define ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT (10U)
/*! HPF - Hash or Perfect Filter
* 0b0..Hash or Perfect Filter is disabled
* 0b1..Hash or Perfect Filter is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_HPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_HPF_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_HPF_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK (0x10000U)
#define ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT (16U)
/*! VTFE - VLAN Tag Filter Enable
* 0b0..VLAN Tag Filter is disabled
* 0b1..VLAN Tag Filter is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_VTFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_VTFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_VTFE_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK (0x100000U)
#define ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT (20U)
/*! IPFE - Layer 3 and Layer 4 Filter Enable
* 0b0..Layer 3 and Layer 4 Filters are disabled
* 0b1..Layer 3 and Layer 4 Filters are enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_IPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_IPFE_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_IPFE_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK (0x200000U)
#define ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT (21U)
/*! DNTU - Drop Non-TCP/UDP over IP Packets
* 0b1..Drop Non-TCP/UDP over IP Packets
* 0b0..Forward Non-TCP/UDP over IP Packets
*/
#define ENET_QOS_MAC_PACKET_FILTER_DNTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_DNTU_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_DNTU_MASK)
#define ENET_QOS_MAC_PACKET_FILTER_RA_MASK (0x80000000U)
#define ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT (31U)
/*! RA - Receive All
* 0b0..Receive All is disabled
* 0b1..Receive All is enabled
*/
#define ENET_QOS_MAC_PACKET_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PACKET_FILTER_RA_SHIFT)) & ENET_QOS_MAC_PACKET_FILTER_RA_MASK)
/*! @} */
/*! @name MAC_WATCHDOG_TIMEOUT - Watchdog Timeout */
/*! @{ */
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK (0xFU)
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT (0U)
/*! WTO - Watchdog Timeout
* 0b1000..10 KB
* 0b1001..11 KB
* 0b1010..12 KB
* 0b1011..13 KB
* 0b1100..14 KB
* 0b1101..15 KB
* 0b1110..16383 Bytes
* 0b0000..2 KB
* 0b0001..3 KB
* 0b0010..4 KB
* 0b0011..5 KB
* 0b0100..6 KB
* 0b0101..7 KB
* 0b0110..8 KB
* 0b0111..9 KB
* 0b1111..Reserved
*/
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_WTO_MASK)
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK (0x100U)
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT (8U)
/*! PWE - Programmable Watchdog Enable
* 0b0..Programmable Watchdog is disabled
* 0b1..Programmable Watchdog is enabled
*/
#define ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_SHIFT)) & ENET_QOS_MAC_WATCHDOG_TIMEOUT_PWE_MASK)
/*! @} */
/*! @name MAC_HASH_TABLE_REG0 - MAC Hash Table Register 0 */
/*! @{ */
#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT (0U)
/*! HT31T0 - MAC Hash Table First 32 Bits This field contains the first 32 Bits [31:0] of the Hash table.
*/
#define ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG0_HT31T0_MASK)
/*! @} */
/*! @name MAC_HASH_TABLE_REG1 - MAC Hash Table Register 1 */
/*! @{ */
#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT (0U)
/*! HT63T32 - MAC Hash Table Second 32 Bits This field contains the second 32 Bits [63:32] of the Hash table.
*/
#define ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_SHIFT)) & ENET_QOS_MAC_HASH_TABLE_REG1_HT63T32_MASK)
/*! @} */
/*! @name MAC_VLAN_TAG_CTRL - MAC VLAN Tag Control */
/*! @{ */
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK (0x1U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT (0U)
/*! OB - Operation Busy
* 0b0..Operation Busy is disabled
* 0b1..Operation Busy is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OB_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OB_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK (0x2U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT (1U)
/*! CT - Command Type
* 0b1..Read operation
* 0b0..Write operation
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_CT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_CT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_CT_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK (0x7CU)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT (2U)
/*! OFS - Offset
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_OFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_OFS_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK (0x20000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT (17U)
/*! VTIM - VLAN Tag Inverse Match Enable
* 0b0..VLAN Tag Inverse Match is disabled
* 0b1..VLAN Tag Inverse Match is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTIM_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK (0x40000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT (18U)
/*! ESVL - Enable S-VLAN When this bit is set, the MAC transmitter and receiver consider the S-VLAN
* packets (Type = 0x88A8) as valid VLAN tagged packets.
* 0b0..S-VLAN is disabled
* 0b1..S-VLAN is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ESVL_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK (0x600000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT (21U)
/*! EVLS - Enable VLAN Tag Stripping on Receive This field indicates the stripping operation on the
* outer VLAN Tag in received packet.
* 0b11..Always strip
* 0b00..Do not strip
* 0b10..Strip if VLAN filter fails
* 0b01..Strip if VLAN filter passes
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLS_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK (0x1000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT (24U)
/*! EVLRXS - Enable VLAN Tag in Rx status
* 0b0..VLAN Tag in Rx status is disabled
* 0b1..VLAN Tag in Rx status is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EVLRXS_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK (0x2000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT (25U)
/*! VTHM - VLAN Tag Hash Table Match Enable
* 0b0..VLAN Tag Hash Table Match is disabled
* 0b1..VLAN Tag Hash Table Match is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_VTHM_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK (0x4000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT (26U)
/*! EDVLP - Enable Double VLAN Processing
* 0b0..Double VLAN Processing is disabled
* 0b1..Double VLAN Processing is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EDVLP_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK (0x8000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT (27U)
/*! ERIVLT - ERIVLT
* 0b0..Inner VLAN tag is disabled
* 0b1..Inner VLAN tag is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_ERIVLT_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK (0x30000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT (28U)
/*! EIVLS - Enable Inner VLAN Tag Stripping on Receive This field indicates the stripping operation
* on inner VLAN Tag in received packet.
* 0b11..Always strip
* 0b00..Do not strip
* 0b10..Strip if VLAN filter fails
* 0b01..Strip if VLAN filter passes
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLS_MASK)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK (0x80000000U)
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT (31U)
/*! EIVLRXS - Enable Inner VLAN Tag in Rx Status
* 0b0..Inner VLAN Tag in Rx status is disabled
* 0b1..Inner VLAN Tag in Rx status is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_CTRL_EIVLRXS_MASK)
/*! @} */
/*! @name MAC_VLAN_TAG_DATA - MAC VLAN Tag Data */
/*! @{ */
#define ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK (0xFFFFU)
#define ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT (0U)
/*! VID - VLAN Tag ID
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_VID(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VID_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VID_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK (0x10000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT (16U)
/*! VEN - VLAN Tag Enable
* 0b0..VLAN Tag is disabled
* 0b1..VLAN Tag is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_VEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_VEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_VEN_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK (0x20000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT (17U)
/*! ETV - 12bits or 16bits VLAN comparison
* 0b1..12 bit VLAN comparison
* 0b0..16 bit VLAN comparison
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ETV_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ETV_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK (0x40000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT (18U)
/*! DOVLTC - Disable VLAN Type Comparison
* 0b1..VLAN type comparison is disabled
* 0b0..VLAN type comparison is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DOVLTC_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK (0x80000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT (19U)
/*! ERSVLM - Enable S-VLAN Match for received Frames
* 0b0..Receive S-VLAN Match is disabled
* 0b1..Receive S-VLAN Match is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERSVLM_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK (0x100000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT (20U)
/*! ERIVLT - Enable Inner VLAN Tag Comparison
* 0b0..Inner VLAN tag comparison is disabled
* 0b1..Inner VLAN tag comparison is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_ERIVLT_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK (0x1000000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT (24U)
/*! DMACHEN - DMA Channel Number Enable
* 0b0..DMA Channel Number is disabled
* 0b1..DMA Channel Number is enabled
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHEN_MASK)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK (0xE000000U)
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT (25U)
/*! DMACHN - DMA Channel Number
*/
#define ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_SHIFT)) & ENET_QOS_MAC_VLAN_TAG_DATA_DMACHN_MASK)
/*! @} */
/*! @name MAC_VLAN_HASH_TABLE - MAC VLAN Hash Table */
/*! @{ */
#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK (0xFFFFU)
#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT (0U)
/*! VLHT - VLAN Hash Table This field contains the 16-bit VLAN Hash Table.
*/
#define ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_SHIFT)) & ENET_QOS_MAC_VLAN_HASH_TABLE_VLHT_MASK)
/*! @} */
/*! @name MAC_VLAN_INCL - VLAN Tag Inclusion or Replacement */
/*! @{ */
#define ENET_QOS_MAC_VLAN_INCL_VLT_MASK (0xFFFFU)
#define ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT (0U)
/*! VLT - VLAN Tag for Transmit Packets
*/
#define ENET_QOS_MAC_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLT_MASK)
#define ENET_QOS_MAC_VLAN_INCL_VLC_MASK (0x30000U)
#define ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT (16U)
/*! VLC - VLAN Tag Control in Transmit Packets - 2'b00: No VLAN tag deletion, insertion, or
* replacement - 2'b01: VLAN tag deletion The MAC removes the VLAN type (bytes 13 and 14) and VLAN tag
* (bytes 15 and 16) of all transmitted packets with VLAN tags.
* 0b01..VLAN tag deletion
* 0b10..VLAN tag insertion
* 0b00..No VLAN tag deletion, insertion, or replacement
* 0b11..VLAN tag replacement
*/
#define ENET_QOS_MAC_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLC_MASK)
#define ENET_QOS_MAC_VLAN_INCL_VLP_MASK (0x40000U)
#define ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT (18U)
/*! VLP - VLAN Priority Control
* 0b0..VLAN Priority Control is disabled
* 0b1..VLAN Priority Control is enabled
*/
#define ENET_QOS_MAC_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLP_MASK)
#define ENET_QOS_MAC_VLAN_INCL_CSVL_MASK (0x80000U)
#define ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT (19U)
/*! CSVL - C-VLAN or S-VLAN
* 0b0..C-VLAN type (0x8100) is inserted or replaced
* 0b1..S-VLAN type (0x88A8) is inserted or replaced
*/
#define ENET_QOS_MAC_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CSVL_MASK)
#define ENET_QOS_MAC_VLAN_INCL_VLTI_MASK (0x100000U)
#define ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT (20U)
/*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
* replaced in Tx packet should be taken from: - The Tx descriptor
* 0b0..VLAN Tag Input is disabled
* 0b1..VLAN Tag Input is enabled
*/
#define ENET_QOS_MAC_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_VLTI_MASK)
#define ENET_QOS_MAC_VLAN_INCL_CBTI_MASK (0x200000U)
#define ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT (21U)
/*! CBTI - Channel based tag insertion
* 0b0..Channel based tag insertion is disabled
* 0b1..Channel based tag insertion is enabled
*/
#define ENET_QOS_MAC_VLAN_INCL_CBTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_CBTI_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_CBTI_MASK)
#define ENET_QOS_MAC_VLAN_INCL_ADDR_MASK (0x7000000U)
#define ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT (24U)
/*! ADDR - Address
*/
#define ENET_QOS_MAC_VLAN_INCL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_ADDR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_ADDR_MASK)
#define ENET_QOS_MAC_VLAN_INCL_RDWR_MASK (0x40000000U)
#define ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT (30U)
/*! RDWR - Read write control
* 0b0..Read operation of indirect access
* 0b1..Write operation of indirect access
*/
#define ENET_QOS_MAC_VLAN_INCL_RDWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_RDWR_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_RDWR_MASK)
#define ENET_QOS_MAC_VLAN_INCL_BUSY_MASK (0x80000000U)
#define ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT (31U)
/*! BUSY - Busy
* 0b1..Busy status detected
* 0b0..Busy status not detected
*/
#define ENET_QOS_MAC_VLAN_INCL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VLAN_INCL_BUSY_SHIFT)) & ENET_QOS_MAC_VLAN_INCL_BUSY_MASK)
/*! @} */
/*! @name MAC_INNER_VLAN_INCL - MAC Inner VLAN Tag Inclusion or Replacement */
/*! @{ */
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK (0xFFFFU)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT (0U)
/*! VLT - VLAN Tag for Transmit Packets
*/
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLT_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLT_MASK)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK (0x30000U)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT (16U)
/*! VLC - VLAN Tag Control in Transmit Packets
* 0b01..VLAN tag deletion
* 0b10..VLAN tag insertion
* 0b00..No VLAN tag deletion, insertion, or replacement
* 0b11..VLAN tag replacement
*/
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLC_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLC_MASK)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK (0x40000U)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT (18U)
/*! VLP - VLAN Priority Control
* 0b0..VLAN Priority Control is disabled
* 0b1..VLAN Priority Control is enabled
*/
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLP_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLP_MASK)
#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK (0x80000U)
#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT (19U)
/*! CSVL - C-VLAN or S-VLAN
* 0b0..C-VLAN type (0x8100) is inserted
* 0b1..S-VLAN type (0x88A8) is inserted
*/
#define ENET_QOS_MAC_INNER_VLAN_INCL_CSVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_CSVL_MASK)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK (0x100000U)
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT (20U)
/*! VLTI - VLAN Tag Input When this bit is set, it indicates that the VLAN tag to be inserted or
* replaced in Tx packet should be taken from: - The Tx descriptor
* 0b0..VLAN Tag Input is disabled
* 0b1..VLAN Tag Input is enabled
*/
#define ENET_QOS_MAC_INNER_VLAN_INCL_VLTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_SHIFT)) & ENET_QOS_MAC_INNER_VLAN_INCL_VLTI_MASK)
/*! @} */
/*! @name MAC_TX_FLOW_CTRL_Q - MAC Q0 Tx Flow Control..MAC Q4 Tx Flow Control */
/*! @{ */
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK (0x1U)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT (0U)
/*! FCB_BPA - Flow Control Busy or Backpressure Activate
* 0b0..Flow Control Busy or Backpressure Activate is disabled
* 0b1..Flow Control Busy or Backpressure Activate is enabled
*/
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_FCB_BPA_MASK)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)
/*! TFE - Transmit Flow Control Enable
* 0b0..Transmit Flow Control is disabled
* 0b1..Transmit Flow Control is enabled
*/
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)
/*! PLT - Pause Low Threshold
* 0b011..Pause Time minus 144 Slot Times (PT -144 slot times)
* 0b100..Pause Time minus 256 Slot Times (PT -256 slot times)
* 0b001..Pause Time minus 28 Slot Times (PT -28 slot times)
* 0b010..Pause Time minus 36 Slot Times (PT -36 slot times)
* 0b000..Pause Time minus 4 Slot Times (PT -4 slot times)
* 0b101..Pause Time minus 512 Slot Times (PT -512 slot times)
* 0b110..Reserved
*/
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)
/*! DZPQ - Disable Zero-Quanta Pause
* 0b1..Zero-Quanta Pause packet generation is disabled
* 0b0..Zero-Quanta Pause packet generation is enabled
*/
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)
/*! PT - Pause Time
*/
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_QOS_MAC_TX_FLOW_CTRL_Q_PT_MASK)
/*! @} */
/* The count of ENET_QOS_MAC_TX_FLOW_CTRL_Q */
#define ENET_QOS_MAC_TX_FLOW_CTRL_Q_COUNT (5U)
/*! @name MAC_RX_FLOW_CTRL - MAC Rx Flow Control */
/*! @{ */
#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)
#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
/*! RFE - Receive Flow Control Enable
* 0b0..Receive Flow Control is disabled
* 0b1..Receive Flow Control is enabled
*/
#define ENET_QOS_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_RFE_MASK)
#define ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)
#define ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
/*! UP - Unicast Pause Packet Detect
* 0b0..Unicast Pause Packet Detect disabled
* 0b1..Unicast Pause Packet Detect enabled
*/
#define ENET_QOS_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_UP_MASK)
#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK (0x100U)
#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT (8U)
/*! PFCE - Priority Based Flow Control Enable
* 0b0..Priority Based Flow Control is disabled
* 0b1..Priority Based Flow Control is enabled
*/
#define ENET_QOS_MAC_RX_FLOW_CTRL_PFCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_SHIFT)) & ENET_QOS_MAC_RX_FLOW_CTRL_PFCE_MASK)
/*! @} */
/*! @name MAC_RXQ_CTRL4 - Receive Queue Control 4 */
/*! @{ */
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK (0x1U)
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT (0U)
/*! UFFQE - Unicast Address Filter Fail Packets Queuing Enable.
* 0b0..Unicast Address Filter Fail Packets Queuing is disabled
* 0b1..Unicast Address Filter Fail Packets Queuing is enabled
*/
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQE_MASK)
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK (0xEU)
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT (1U)
/*! UFFQ - Unicast Address Filter Fail Packets Queue.
*/
#define ENET_QOS_MAC_RXQ_CTRL4_UFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_UFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_UFFQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK (0x100U)
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT (8U)
/*! MFFQE - Multicast Address Filter Fail Packets Queuing Enable.
* 0b0..Multicast Address Filter Fail Packets Queuing is disabled
* 0b1..Multicast Address Filter Fail Packets Queuing is enabled
*/
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQE_MASK)
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK (0xE00U)
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT (9U)
/*! MFFQ - Multicast Address Filter Fail Packets Queue.
*/
#define ENET_QOS_MAC_RXQ_CTRL4_MFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_MFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_MFFQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK (0x10000U)
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT (16U)
/*! VFFQE - VLAN Tag Filter Fail Packets Queuing Enable
* 0b0..VLAN tag Filter Fail Packets Queuing is disabled
* 0b1..VLAN tag Filter Fail Packets Queuing is enabled
*/
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQE_MASK)
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK (0xE0000U)
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT (17U)
/*! VFFQ - VLAN Tag Filter Fail Packets Queue
*/
#define ENET_QOS_MAC_RXQ_CTRL4_VFFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL4_VFFQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL4_VFFQ_MASK)
/*! @} */
/*! @name MAC_TXQ_PRTY_MAP0 - Transmit Queue Priority Mapping 0 */
/*! @{ */
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK (0xFFU)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT (0U)
/*! PSTQ0 - Priorities Selected in Transmit Queue 0
*/
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK (0xFF00U)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT (8U)
/*! PSTQ1 - Priorities Selected in Transmit Queue 1 This bit is similar to the PSTQ0 bit.
*/
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ1_MASK)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK (0xFF0000U)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT (16U)
/*! PSTQ2 - Priorities Selected in Transmit Queue 2 This bit is similar to the PSTQ0 bit.
*/
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ2_MASK)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK (0xFF000000U)
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT (24U)
/*! PSTQ3 - Priorities Selected in Transmit Queue 3 This bit is similar to the PSTQ0 bit.
*/
#define ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP0_PSTQ3_MASK)
/*! @} */
/*! @name MAC_TXQ_PRTY_MAP1 - Transmit Queue Priority Mapping 1 */
/*! @{ */
#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK (0xFFU)
#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT (0U)
/*! PSTQ4 - Priorities Selected in Transmit Queue 4
*/
#define ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_SHIFT)) & ENET_QOS_MAC_TXQ_PRTY_MAP1_PSTQ4_MASK)
/*! @} */
/*! @name MAC_RXQ_CTRL - Receive Queue Control 0..Receive Queue Control 3 */
/*! @{ */
#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)
#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)
/*! AVCPQ - AV Untagged Control Packets Queue
* 0b000..Receive Queue 0
* 0b001..Receive Queue 1
* 0b010..Receive Queue 2
* 0b011..Receive Queue 3
* 0b100..Receive Queue 4
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_AVCPQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)
/*! PSRQ0 - Priorities Selected in the Receive Queue 0
*/
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ0_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK (0xFFU)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT (0U)
/*! PSRQ4 - Priorities Selected in the Receive Queue 4
*/
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ4_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ4_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)
/*! RXQ0EN - Receive Queue 0 Enable This field indicates whether Rx Queue 0 is enabled for AV or DCB.
* 0b00..Queue not enabled
* 0b01..Queue enabled for AV
* 0b10..Queue enabled for DCB/Generic
* 0b11..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ0EN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)
/*! RXQ1EN - Receive Queue 1 Enable This field is similar to the RXQ0EN field.
* 0b00..Queue not enabled
* 0b01..Queue enabled for AV
* 0b10..Queue enabled for DCB/Generic
* 0b11..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ1EN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK (0x70U)
#define ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT (4U)
/*! PTPQ - PTP Packets Queue
* 0b000..Receive Queue 0
* 0b001..Receive Queue 1
* 0b010..Receive Queue 2
* 0b011..Receive Queue 3
* 0b100..Receive Queue 4
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_PTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PTPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PTPQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK (0x30U)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT (4U)
/*! RXQ2EN - Receive Queue 2 Enable This field is similar to the RXQ0EN field.
* 0b00..Queue not enabled
* 0b01..Queue enabled for AV
* 0b10..Queue enabled for DCB/Generic
* 0b11..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_RXQ2EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ2EN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK (0xC0U)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT (6U)
/*! RXQ3EN - Receive Queue 3 Enable This field is similar to the RXQ0EN field.
* 0b00..Queue not enabled
* 0b01..Queue enabled for AV
* 0b10..Queue enabled for DCB/Generic
* 0b11..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_RXQ3EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ3EN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK (0x700U)
#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT (8U)
/*! DCBCPQ - DCB Control Packets Queue
* 0b000..Receive Queue 0
* 0b001..Receive Queue 1
* 0b010..Receive Queue 2
* 0b011..Receive Queue 3
* 0b100..Receive Queue 4
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_DCBCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_DCBCPQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)
/*! PSRQ1 - Priorities Selected in the Receive Queue 1
*/
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ1_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK (0x300U)
#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT (8U)
/*! RXQ4EN - Receive Queue 4 Enable This field is similar to the RXQ0EN field.
* 0b00..Queue not enabled
* 0b01..Queue enabled for AV
* 0b10..Queue enabled for DCB/Generic
* 0b11..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_RXQ4EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_RXQ4EN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)
#define ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT (12U)
/*! UPQ - Untagged Packet Queue
* 0b000..Receive Queue 0
* 0b001..Receive Queue 1
* 0b010..Receive Queue 2
* 0b011..Receive Queue 3
* 0b100..Receive Queue 4
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_UPQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)
/*! MCBCQ - Multicast and Broadcast Queue
* 0b000..Receive Queue 0
* 0b001..Receive Queue 1
* 0b010..Receive Queue 2
* 0b011..Receive Queue 3
* 0b100..Receive Queue 4
* 0b101..Reserved
* 0b110..Reserved
* 0b111..Reserved
*/
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)
/*! PSRQ2 - Priorities Selected in the Receive Queue 2
*/
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ2_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)
/*! MCBCQEN - Multicast and Broadcast Queue Enable This bit specifies that Multicast or Broadcast
* packets routing to the Rx Queue is enabled and the Multicast or Broadcast packets must be routed
* to Rx Queue specified in MCBCQ field.
* 0b0..Multicast and Broadcast Queue is disabled
* 0b1..Multicast and Broadcast Queue is enabled
*/
#define ENET_QOS_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_MCBCQEN_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK (0x200000U)
#define ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT (21U)
/*! TACPQE - Tagged AV Control Packets Queuing Enable.
* 0b0..Tagged AV Control Packets Queuing is disabled
* 0b1..Tagged AV Control Packets Queuing is enabled
*/
#define ENET_QOS_MAC_RXQ_CTRL_TACPQE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TACPQE_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TACPQE_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK (0xC00000U)
#define ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT (22U)
/*! TPQC - Tagged PTP over Ethernet Packets Queuing Control.
*/
#define ENET_QOS_MAC_RXQ_CTRL_TPQC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_TPQC_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_TPQC_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK (0x7000000U)
#define ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT (24U)
/*! FPRQ - Frame Preemption Residue Queue
*/
#define ENET_QOS_MAC_RXQ_CTRL_FPRQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_FPRQ_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_FPRQ_MASK)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)
/*! PSRQ3 - Priorities Selected in the Receive Queue 3
*/
#define ENET_QOS_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_QOS_MAC_RXQ_CTRL_PSRQ3_MASK)
/*! @} */
/* The count of ENET_QOS_MAC_RXQ_CTRL */
#define ENET_QOS_MAC_RXQ_CTRL_COUNT (4U)
/*! @name MAC_INTERRUPT_STATUS - Interrupt Status */
/*! @{ */
#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK (0x1U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT (0U)
/*! RGSMIIIS - RGMII or SMII Interrupt Status
* 0b1..RGMII or SMII Interrupt Status is active
* 0b0..RGMII or SMII Interrupt Status is not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RGSMIIIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK (0x8U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT (3U)
/*! PHYIS - PHY Interrupt
* 0b1..PHY Interrupt detected
* 0b0..PHY Interrupt not detected
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PHYIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK (0x10U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT (4U)
/*! PMTIS - PMT Interrupt Status
* 0b1..PMT Interrupt status active
* 0b0..PMT Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_PMTIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK (0x20U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT (5U)
/*! LPIIS - LPI Interrupt Status
* 0b1..LPI Interrupt status active
* 0b0..LPI Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_LPIIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK (0x100U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT (8U)
/*! MMCIS - MMC Interrupt Status
* 0b1..MMC Interrupt status active
* 0b0..MMC Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK (0x200U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT (9U)
/*! MMCRXIS - MMC Receive Interrupt Status
* 0b1..MMC Receive Interrupt status active
* 0b0..MMC Receive Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK (0x400U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT (10U)
/*! MMCTXIS - MMC Transmit Interrupt Status
* 0b1..MMC Transmit Interrupt status active
* 0b0..MMC Transmit Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCTXIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK (0x800U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT (11U)
/*! MMCRXIPIS - MMC Receive Checksum Offload Interrupt Status
* 0b1..MMC Receive Checksum Offload Interrupt status active
* 0b0..MMC Receive Checksum Offload Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MMCRXIPIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK (0x1000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT (12U)
/*! TSIS - Timestamp Interrupt Status
* 0b1..Timestamp Interrupt status active
* 0b0..Timestamp Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TSIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK (0x2000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT (13U)
/*! TXSTSIS - Transmit Status Interrupt
* 0b1..Transmit Interrupt status active
* 0b0..Transmit Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_TXSTSIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK (0x4000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT (14U)
/*! RXSTSIS - Receive Status Interrupt
* 0b1..Receive Interrupt status active
* 0b0..Receive Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_RXSTSIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK (0x20000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT (17U)
/*! FPEIS - Frame Preemption Interrupt Status
* 0b1..Frame Preemption Interrupt status active
* 0b0..Frame Preemption Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_FPEIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK (0x40000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT (18U)
/*! MDIOIS - MDIO Interrupt Status
* 0b1..MDIO Interrupt status active
* 0b0..MDIO Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MDIOIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK (0x80000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT (19U)
/*! MFTIS - MMC FPE Transmit Interrupt Status
* 0b1..MMC FPE Transmit Interrupt status active
* 0b0..MMC FPE Transmit Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFTIS_MASK)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK (0x100000U)
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT (20U)
/*! MFRIS - MMC FPE Receive Interrupt Status
* 0b1..MMC FPE Receive Interrupt status active
* 0b0..MMC FPE Receive Interrupt status not active
*/
#define ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_SHIFT)) & ENET_QOS_MAC_INTERRUPT_STATUS_MFRIS_MASK)
/*! @} */
/*! @name MAC_INTERRUPT_ENABLE - Interrupt Enable */
/*! @{ */
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK (0x1U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT (0U)
/*! RGSMIIIE - RGMII or SMII Interrupt Enable When this bit is set, it enables the assertion of the
* interrupt signal because of the setting of RGSMIIIS bit in MAC_INTERRUPT_STATUS register.
* 0b0..RGMII or SMII Interrupt is disabled
* 0b1..RGMII or SMII Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RGSMIIIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK (0x8U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT (3U)
/*! PHYIE - PHY Interrupt Enable When this bit is set, it enables the assertion of the interrupt
* signal because of the setting of MAC_INTERRUPT_STATUS[PHYIS].
* 0b0..PHY Interrupt is disabled
* 0b1..PHY Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PHYIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK (0x10U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT (4U)
/*! PMTIE - PMT Interrupt Enable When this bit is set, it enables the assertion of the interrupt
* signal because of the setting of MAC_INTERRUPT_STATUS[PMTIS].
* 0b0..PMT Interrupt is disabled
* 0b1..PMT Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_PMTIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK (0x20U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT (5U)
/*! LPIIE - LPI Interrupt Enable When this bit is set, it enables the assertion of the interrupt
* signal because of the setting of MAC_INTERRUPT_STATUS[LPIIS].
* 0b0..LPI Interrupt is disabled
* 0b1..LPI Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_LPIIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK (0x1000U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT (12U)
/*! TSIE - Timestamp Interrupt Enable When this bit is set, it enables the assertion of the
* interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TSIS].
* 0b0..Timestamp Interrupt is disabled
* 0b1..Timestamp Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TSIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK (0x2000U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT (13U)
/*! TXSTSIE - Transmit Status Interrupt Enable When this bit is set, it enables the assertion of the
* interrupt signal because of the setting of MAC_INTERRUPT_STATUS[TXSTSIS].
* 0b0..Timestamp Status Interrupt is disabled
* 0b1..Timestamp Status Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_TXSTSIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK (0x4000U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT (14U)
/*! RXSTSIE - Receive Status Interrupt Enable When this bit is set, it enables the assertion of the
* interrupt signal because of the setting of MAC_INTERRUPT_STATUS[RXSTSIS].
* 0b0..Receive Status Interrupt is disabled
* 0b1..Receive Status Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_RXSTSIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK (0x20000U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT (17U)
/*! FPEIE - Frame Preemption Interrupt Enable When this bit is set, it enables the assertion of the
* interrupt when FPEIS field is set in the MAC_INTERRUPT_STATUS.
* 0b0..Frame Preemption Interrupt is disabled
* 0b1..Frame Preemption Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_FPEIE_MASK)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK (0x40000U)
#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT (18U)
/*! MDIOIE - MDIO Interrupt Enable When this bit is set, it enables the assertion of the interrupt
* when MDIOIS field is set in the MAC_INTERRUPT_STATUS register.
* 0b0..MDIO Interrupt is disabled
* 0b1..MDIO Interrupt is enabled
*/
#define ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_SHIFT)) & ENET_QOS_MAC_INTERRUPT_ENABLE_MDIOIE_MASK)
/*! @} */
/*! @name MAC_RX_TX_STATUS - Receive Transmit Status */
/*! @{ */
#define ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK (0x1U)
#define ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT (0U)
/*! TJT - Transmit Jabber Timeout This bit indicates that the Transmit Jabber Timer expired which
* happens when the packet size exceeds 2,048 bytes (10,240 bytes when the Jumbo packet is enabled)
* and JD bit is reset in the MAC_CONFIGURATION register.
* 0b1..Transmit Jabber Timeout occurred
* 0b0..No Transmit Jabber Timeout
*/
#define ENET_QOS_MAC_RX_TX_STATUS_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_TJT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_TJT_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK (0x2U)
#define ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT (1U)
/*! NCARR - No Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
* indicates that the carrier signal from the PHY is not present at the end of preamble transmission.
* 0b1..No carrier
* 0b0..Carrier is present
*/
#define ENET_QOS_MAC_RX_TX_STATUS_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_NCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_NCARR_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK (0x4U)
#define ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT (2U)
/*! LCARR - Loss of Carrier When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
* indicates that the loss of carrier occurred during packet transmission, that is, the phy_crs_i
* signal was inactive for one or more transmission clock periods during packet transmission.
* 0b1..Loss of carrier
* 0b0..Carrier is present
*/
#define ENET_QOS_MAC_RX_TX_STATUS_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCARR_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCARR_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK (0x8U)
#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT (3U)
/*! EXDEF - Excessive Deferral When the DTXSTS bit is set in the MAC_OPERATION_MODE register and the
* DC bit is set in the MAC_CONFIGURATION register, this bit indicates that the transmission
* ended because of excessive deferral of over 24,288 bit times (155,680 in 1000/2500 Mbps mode or
* when Jumbo packet is enabled).
* 0b1..Excessive deferral
* 0b0..No Excessive deferral
*/
#define ENET_QOS_MAC_RX_TX_STATUS_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXDEF_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXDEF_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK (0x10U)
#define ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT (4U)
/*! LCOL - Late Collision When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this bit
* indicates that the packet transmission aborted because a collision occurred after the collision
* window (64 bytes including Preamble in MII mode; 512 bytes including Preamble and Carrier
* Extension in GMII mode).
* 0b1..Late collision is sensed
* 0b0..No collision
*/
#define ENET_QOS_MAC_RX_TX_STATUS_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_LCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_LCOL_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK (0x20U)
#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT (5U)
/*! EXCOL - Excessive Collisions When the DTXSTS bit is set in the MAC_OPERATION_MODE register, this
* bit indicates that the transmission aborted after 16 successive collisions while attempting
* to transmit the current packet.
* 0b1..Excessive collision is sensed
* 0b0..No collision
*/
#define ENET_QOS_MAC_RX_TX_STATUS_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_EXCOL_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_EXCOL_MASK)
#define ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK (0x100U)
#define ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT (8U)
/*! RWT - Receive Watchdog Timeout This bit is set when a packet with length greater than 2,048
* bytes is received (10, 240 bytes when Jumbo Packet mode is enabled) and the WD bit is reset in the
* MAC_CONFIGURATION register.
* 0b1..Receive watchdog timed out
* 0b0..No receive watchdog timeout
*/
#define ENET_QOS_MAC_RX_TX_STATUS_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_TX_STATUS_RWT_SHIFT)) & ENET_QOS_MAC_RX_TX_STATUS_RWT_MASK)
/*! @} */
/*! @name MAC_PMT_CONTROL_STATUS - PMT Control and Status */
/*! @{ */
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK (0x1U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT (0U)
/*! PWRDWN - Power Down When this bit is set, the MAC receiver drops all received packets until it
* receives the expected magic packet or remote wake-up packet.
* 0b0..Power down is disabled
* 0b1..Power down is enabled
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_PWRDWN_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK (0x2U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT (1U)
/*! MGKPKTEN - Magic Packet Enable When this bit is set, a power management event is generated when the MAC receives a magic packet.
* 0b0..Magic Packet is disabled
* 0b1..Magic Packet is enabled
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPKTEN_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK (0x4U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT (2U)
/*! RWKPKTEN - Remote Wake-Up Packet Enable When this bit is set, a power management event is
* generated when the MAC receives a remote wake-up packet.
* 0b0..Remote wake-up packet is disabled
* 0b1..Remote wake-up packet is enabled
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPKTEN_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK (0x20U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT (5U)
/*! MGKPRCVD - Magic Packet Received When this bit is set, it indicates that the power management
* event is generated because of the reception of a magic packet.
* 0b1..Magic packet is received
* 0b0..No Magic packet is received
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_MGKPRCVD_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK (0x40U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT (6U)
/*! RWKPRCVD - Remote Wake-Up Packet Received When this bit is set, it indicates that the power
* management event is generated because of the reception of a remote wake-up packet.
* 0b1..Remote wake-up packet is received
* 0b0..Remote wake-up packet is received
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPRCVD_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK (0x200U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT (9U)
/*! GLBLUCAST - Global Unicast When this bit set, any unicast packet filtered by the MAC (DAF)
* address recognition is detected as a remote wake-up packet.
* 0b0..Global unicast is disabled
* 0b1..Global unicast is enabled
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_GLBLUCAST_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK (0x400U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT (10U)
/*! RWKPFE - Remote Wake-up Packet Forwarding Enable When this bit is set along with RWKPKTEN, the
* MAC receiver drops all received frames until it receives the expected Wake-up frame.
* 0b0..Remote Wake-up Packet Forwarding is disabled
* 0b1..Remote Wake-up Packet Forwarding is enabled
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPFE_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK (0x1F000000U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT (24U)
/*! RWKPTR - Remote Wake-up FIFO Pointer This field gives the current value (0 to 7, 15, or 31 when
* 4, 8, or 16 Remote Wake-up Packet Filters are selected) of the Remote Wake-up Packet Filter
* register pointer.
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKPTR_MASK)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK (0x80000000U)
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT (31U)
/*! RWKFILTRST - Remote Wake-Up Packet Filter Register Pointer Reset When this bit is set, the
* remote wake-up packet filter register pointer is reset to 3'b000.
* 0b0..Remote Wake-Up Packet Filter Register Pointer is not Reset
* 0b1..Remote Wake-Up Packet Filter Register Pointer is Reset
*/
#define ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_SHIFT)) & ENET_QOS_MAC_PMT_CONTROL_STATUS_RWKFILTRST_MASK)
/*! @} */
/*! @name MAC_RWK_PACKET_FILTER - Remote Wakeup Filter */
/*! @{ */
#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT (0U)
/*! WKUPFRMFTR - RWK Packet Filter This field contains the various controls of RWK Packet filter.
*/
#define ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_SHIFT)) & ENET_QOS_MAC_RWK_PACKET_FILTER_WKUPFRMFTR_MASK)
/*! @} */
/*! @name MAC_LPI_CONTROL_STATUS - LPI Control and Status */
/*! @{ */
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK (0x1U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT (0U)
/*! TLPIEN - Transmit LPI Entry When this bit is set, it indicates that the MAC Transmitter has
* entered the LPI state because of the setting of the LPIEN bit.
* 0b1..Transmit LPI entry detected
* 0b0..Transmit LPI entry not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEN_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK (0x2U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT (1U)
/*! TLPIEX - Transmit LPI Exit When this bit is set, it indicates that the MAC transmitter exited
* the LPI state after the application cleared the LPIEN bit and the LPI TW Timer has expired.
* 0b1..Transmit LPI exit detected
* 0b0..Transmit LPI exit not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIEX_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK (0x4U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT (2U)
/*! RLPIEN - Receive LPI Entry When this bit is set, it indicates that the MAC Receiver has received
* an LPI pattern and entered the LPI state.
* 0b1..Receive LPI entry detected
* 0b0..Receive LPI entry not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEN_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK (0x8U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT (3U)
/*! RLPIEX - Receive LPI Exit When this bit is set, it indicates that the MAC Receiver has stopped
* receiving the LPI pattern on the GMII or MII interface, exited the LPI state, and resumed the
* normal reception.
* 0b1..Receive LPI exit detected
* 0b0..Receive LPI exit not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIEX_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK (0x100U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT (8U)
/*! TLPIST - Transmit LPI State When this bit is set, it indicates that the MAC is transmitting the
* LPI pattern on the GMII or MII interface.
* 0b1..Transmit LPI state detected
* 0b0..Transmit LPI state not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_TLPIST_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK (0x200U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT (9U)
/*! RLPIST - Receive LPI State When this bit is set, it indicates that the MAC is receiving the LPI
* pattern on the GMII or MII interface.
* 0b1..Receive LPI state detected
* 0b0..Receive LPI state not detected
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_RLPIST_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK (0x10000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT (16U)
/*! LPIEN - LPI Enable When this bit is set, it instructs the MAC Transmitter to enter the LPI state.
* 0b0..LPI state is disabled
* 0b1..LPI state is enabled
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIEN_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK (0x20000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT (17U)
/*! PLS - PHY Link Status This bit indicates the link status of the PHY.
* 0b0..link is down
* 0b1..link is okay (UP)
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLS_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK (0x40000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT (18U)
/*! PLSEN - PHY Link Status Enable This bit enables the link status received on the RGMII, SGMII, or
* SMII Receive paths to be used for activating the LPI LS TIMER.
* 0b0..PHY Link Status is disabled
* 0b1..PHY Link Status is enabled
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_PLSEN_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK (0x80000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT (19U)
/*! LPITXA - LPI Tx Automate This bit controls the behavior of the MAC when it is entering or coming
* out of the LPI mode on the Transmit side.
* 0b0..LPI Tx Automate is disabled
* 0b1..LPI Tx Automate is enabled
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITXA_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK (0x100000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT (20U)
/*! LPIATE - LPI Timer Enable This bit controls the automatic entry of the MAC Transmitter into and exit out of the LPI state.
* 0b0..LPI Timer is disabled
* 0b1..LPI Timer is enabled
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPIATE_MASK)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK (0x200000U)
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT (21U)
/*! LPITCSE - LPI Tx Clock Stop Enable When this bit is set, the MAC asserts
* sbd_tx_clk_gating_ctrl_o signal high after it enters Tx LPI mode to indicate that the Tx clock to MAC can be stopped.
* 0b0..LPI Tx Clock Stop is disabled
* 0b1..LPI Tx Clock Stop is enabled
*/
#define ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_SHIFT)) & ENET_QOS_MAC_LPI_CONTROL_STATUS_LPITCSE_MASK)
/*! @} */
/*! @name MAC_LPI_TIMERS_CONTROL - LPI Timers Control */
/*! @{ */
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK (0xFFFFU)
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT (0U)
/*! TWT - LPI TW Timer This field specifies the minimum time (in microseconds) for which the MAC
* waits after it stops transmitting the LPI pattern to the PHY and before it resumes the normal
* transmission.
*/
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_TWT_MASK)
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK (0x3FF0000U)
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT (16U)
/*! LST - LPI LS Timer This field specifies the minimum time (in milliseconds) for which the link
* status from the PHY should be up (OKAY) before the LPI pattern can be transmitted to the PHY.
*/
#define ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_SHIFT)) & ENET_QOS_MAC_LPI_TIMERS_CONTROL_LST_MASK)
/*! @} */
/*! @name MAC_LPI_ENTRY_TIMER - Tx LPI Entry Timer Control */
/*! @{ */
#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK (0xFFFF8U)
#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT (3U)
/*! LPIET - LPI Entry Timer This field specifies the time in microseconds the MAC waits to enter LPI
* mode, after it has transmitted all the frames.
*/
#define ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_SHIFT)) & ENET_QOS_MAC_LPI_ENTRY_TIMER_LPIET_MASK)
/*! @} */
/*! @name MAC_ONEUS_TIC_COUNTER - One-microsecond Reference Timer */
/*! @{ */
#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK (0xFFFU)
#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT (0U)
/*! TIC_1US_CNTR - 1US TIC Counter The application must program this counter so that the number of clock cycles of CSR clock is 1us.
*/
#define ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_SHIFT)) & ENET_QOS_MAC_ONEUS_TIC_COUNTER_TIC_1US_CNTR_MASK)
/*! @} */
/*! @name MAC_PHYIF_CONTROL_STATUS - PHY Interface Control and Status */
/*! @{ */
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK (0x1U)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT (0U)
/*! TC - Transmit Configuration in RGMII, SGMII, or SMII When set, this bit enables the transmission
* of duplex mode, link speed, and link up or down information to the PHY in the RGMII, SMII, or
* SGMII port.
* 0b0..Disable Transmit Configuration in RGMII, SGMII, or SMII
* 0b1..Enable Transmit Configuration in RGMII, SGMII, or SMII
*/
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_TC_MASK)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK (0x2U)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT (1U)
/*! LUD - Link Up or Down This bit indicates whether the link is up or down during transmission of
* configuration in the RGMII, SGMII, or SMII interface.
* 0b0..Link down
* 0b1..Link up
*/
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LUD_MASK)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK (0x10000U)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT (16U)
/*! LNKMOD - Link Mode This bit indicates the current mode of operation of the link.
* 0b1..Full-duplex mode
* 0b0..Half-duplex mode
*/
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKMOD_MASK)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK (0x60000U)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT (17U)
/*! LNKSPEED - Link Speed This bit indicates the current speed of the link.
* 0b10..125 MHz
* 0b00..2.5 MHz
* 0b01..25 MHz
* 0b11..Reserved
*/
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSPEED_MASK)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK (0x80000U)
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT (19U)
/*! LNKSTS - Link Status This bit indicates whether the link is up (1'b1) or down (1'b0).
* 0b1..Link up
* 0b0..Link down
*/
#define ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_SHIFT)) & ENET_QOS_MAC_PHYIF_CONTROL_STATUS_LNKSTS_MASK)
/*! @} */
/*! @name MAC_VERSION - MAC Version */
/*! @{ */
#define ENET_QOS_MAC_VERSION_SNPSVER_MASK (0xFFU)
#define ENET_QOS_MAC_VERSION_SNPSVER_SHIFT (0U)
/*! SNPSVER - Synopsys-defined Version
*/
#define ENET_QOS_MAC_VERSION_SNPSVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_SNPSVER_SHIFT)) & ENET_QOS_MAC_VERSION_SNPSVER_MASK)
#define ENET_QOS_MAC_VERSION_USERVER_MASK (0xFF00U)
#define ENET_QOS_MAC_VERSION_USERVER_SHIFT (8U)
/*! USERVER - User-defined Version (8'h10)
*/
#define ENET_QOS_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_VERSION_USERVER_SHIFT)) & ENET_QOS_MAC_VERSION_USERVER_MASK)
/*! @} */
/*! @name MAC_DEBUG - MAC Debug */
/*! @{ */
#define ENET_QOS_MAC_DEBUG_RPESTS_MASK (0x1U)
#define ENET_QOS_MAC_DEBUG_RPESTS_SHIFT (0U)
/*! RPESTS - MAC GMII or MII Receive Protocol Engine Status When this bit is set, it indicates that
* the MAC GMII or MII receive protocol engine is actively receiving data, and it is not in the
* Idle state.
* 0b1..MAC GMII or MII Receive Protocol Engine Status detected
* 0b0..MAC GMII or MII Receive Protocol Engine Status not detected
*/
#define ENET_QOS_MAC_DEBUG_RPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RPESTS_MASK)
#define ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK (0x6U)
#define ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT (1U)
/*! RFCFCSTS - MAC Receive Packet Controller FIFO Status When this bit is set, this field indicates
* the active state of the small FIFO Read and Write controllers of the MAC Receive Packet
* Controller module.
*/
#define ENET_QOS_MAC_DEBUG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_RFCFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_RFCFCSTS_MASK)
#define ENET_QOS_MAC_DEBUG_TPESTS_MASK (0x10000U)
#define ENET_QOS_MAC_DEBUG_TPESTS_SHIFT (16U)
/*! TPESTS - MAC GMII or MII Transmit Protocol Engine Status When this bit is set, it indicates that
* the MAC GMII or MII transmit protocol engine is actively transmitting data, and it is not in
* the Idle state.
* 0b1..MAC GMII or MII Transmit Protocol Engine Status detected
* 0b0..MAC GMII or MII Transmit Protocol Engine Status not detected
*/
#define ENET_QOS_MAC_DEBUG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TPESTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TPESTS_MASK)
#define ENET_QOS_MAC_DEBUG_TFCSTS_MASK (0x60000U)
#define ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT (17U)
/*! TFCSTS - MAC Transmit Packet Controller Status This field indicates the state of the MAC Transmit Packet Controller module.
* 0b10..Generating and transmitting a Pause control packet (in full-duplex mode)
* 0b00..Idle state
* 0b11..Transferring input packet for transmission
* 0b01..Waiting for one of the following: Status of the previous packet OR IPG or back off period to be over
*/
#define ENET_QOS_MAC_DEBUG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_DEBUG_TFCSTS_SHIFT)) & ENET_QOS_MAC_DEBUG_TFCSTS_MASK)
/*! @} */
/*! @name MAC_HW_FEAT - Optional Features or Functions 0..Optional Features or Functions 3 */
/*! @{ */
#define ENET_QOS_MAC_HW_FEAT_MIISEL_MASK (0x1U)
#define ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT (0U)
/*! MIISEL - 10 or 100 Mbps Support This bit is set to 1 when 10/100 Mbps is selected as the Mode of Operation
* 0b1..10 or 100 Mbps support
* 0b0..No 10 or 100 Mbps support
*/
#define ENET_QOS_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MIISEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_NRVF_MASK (0x7U)
#define ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT (0U)
/*! NRVF - Number of Extended VLAN Tag Filters Enabled This field indicates the Number of Extended VLAN Tag Filters selected:
* 0b011..16 Extended Rx VLAN Filters
* 0b100..24 Extended Rx VLAN Filters
* 0b101..32 Extended Rx VLAN Filters
* 0b001..4 Extended Rx VLAN Filters
* 0b010..8 Extended Rx VLAN Filters
* 0b000..No Extended Rx VLAN Filters
* 0b110..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_NRVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_NRVF_SHIFT)) & ENET_QOS_MAC_HW_FEAT_NRVF_MASK)
#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)
#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)
/*! RXFIFOSIZE - MTL Receive FIFO Size This field contains the configured value of MTL Rx FIFO in
* bytes expressed as Log to base 2 minus 7, that is, Log2(RXFIFO_SIZE) -7:
* 0b00011..1024 bytes
* 0b00000..128 bytes
* 0b01010..128 KB
* 0b00111..16384 bytes
* 0b00100..2048 bytes
* 0b00001..256 bytes
* 0b01011..256 KB
* 0b01000..32 KB
* 0b00101..4096 bytes
* 0b00010..512 bytes
* 0b01001..64 KB
* 0b00110..8192 bytes
* 0b01100..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXFIFOSIZE_MASK)
#define ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK (0xFU)
#define ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT (0U)
/*! RXQCNT - Number of MTL Receive Queues This field indicates the number of MTL Receive queues:
* 0b0000..1 MTL Rx Queue
* 0b0001..2 MTL Rx Queues
* 0b0010..3 MTL Rx Queues
* 0b0011..4 MTL Rx Queues
* 0b0100..5 MTL Rx Queues
* 0b0101..Reserved
* 0b0110..Reserved
* 0b0111..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXQCNT_MASK)
#define ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK (0x2U)
#define ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT (1U)
/*! GMIISEL - 1000 Mbps Support This bit is set to 1 when 1000 Mbps is selected as the Mode of Operation
* 0b1..1000 Mbps support
* 0b0..No 1000 Mbps support
*/
#define ENET_QOS_MAC_HW_FEAT_GMIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_GMIISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_GMIISEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_HDSEL_MASK (0x4U)
#define ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT (2U)
/*! HDSEL - Half-duplex Support This bit is set to 1 when the half-duplex mode is selected
* 0b1..Half-duplex support
* 0b0..No Half-duplex support
*/
#define ENET_QOS_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HDSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK (0x8U)
#define ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT (3U)
/*! PCSSEL - PCS Registers (TBI, SGMII, or RTBI PHY interface) This bit is set to 1 when the TBI,
* SGMII, or RTBI PHY interface option is selected
* 0b1..PCS Registers (TBI, SGMII, or RTBI PHY interface)
* 0b0..No PCS Registers (TBI, SGMII, or RTBI PHY interface)
*/
#define ENET_QOS_MAC_HW_FEAT_PCSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PCSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PCSSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK (0x10U)
#define ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT (4U)
/*! CBTISEL - Queue/Channel based VLAN tag insertion on Tx Enable This bit is set to 1 when the
* Enable Queue/Channel based VLAN tag insertion on Tx Feature is selected.
* 0b1..Enable Queue/Channel based VLAN tag insertion on Tx feature is selected
* 0b0..Enable Queue/Channel based VLAN tag insertion on Tx feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_CBTISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_CBTISEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_CBTISEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_VLHASH_MASK (0x10U)
#define ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT (4U)
/*! VLHASH - VLAN Hash Filter Selected This bit is set to 1 when the Enable VLAN Hash Table Based Filtering option is selected
* 0b1..VLAN Hash Filter selected
* 0b0..VLAN Hash Filter not selected
*/
#define ENET_QOS_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_QOS_MAC_HW_FEAT_VLHASH_MASK)
#define ENET_QOS_MAC_HW_FEAT_DVLAN_MASK (0x20U)
#define ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT (5U)
/*! DVLAN - Double VLAN Tag Processing Selected This bit is set to 1 when the Enable Double VLAN Processing Feature is selected.
* 0b1..Double VLAN option is selected
* 0b0..Double VLAN option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_DVLAN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DVLAN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DVLAN_MASK)
#define ENET_QOS_MAC_HW_FEAT_SMASEL_MASK (0x20U)
#define ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT (5U)
/*! SMASEL - SMA (MDIO) Interface This bit is set to 1 when the Enable Station Management (MDIO Interface) option is selected
* 0b1..SMA (MDIO) Interface selected
* 0b0..SMA (MDIO) Interface not selected
*/
#define ENET_QOS_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SMASEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_SPRAM_MASK (0x20U)
#define ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT (5U)
/*! SPRAM - Single Port RAM Enable This bit is set to 1 when the Use single port RAM Feature is selected.
* 0b1..Single Port RAM feature is selected
* 0b0..Single Port RAM feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_SPRAM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPRAM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPRAM_MASK)
#define ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK (0x40U)
#define ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT (6U)
/*! RWKSEL - PMT Remote Wake-up Packet Enable This bit is set to 1 when the Enable Remote Wake-Up Packet Detection option is selected
* 0b1..PMT Remote Wake-up Packet Enable option is selected
* 0b0..PMT Remote Wake-up Packet Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RWKSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)
#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)
/*! TXFIFOSIZE - MTL Transmit FIFO Size This field contains the configured value of MTL Tx FIFO in
* bytes expressed as Log to base 2 minus 7, that is, Log2(TXFIFO_SIZE) -7:
* 0b00011..1024 bytes
* 0b00000..128 bytes
* 0b01010..128 KB
* 0b00111..16384 bytes
* 0b00100..2048 bytes
* 0b00001..256 bytes
* 0b01000..32 KB
* 0b00101..4096 bytes
* 0b00010..512 bytes
* 0b01001..64 KB
* 0b00110..8192 bytes
* 0b01011..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXFIFOSIZE_MASK)
#define ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)
#define ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT (6U)
/*! TXQCNT - Number of MTL Transmit Queues This field indicates the number of MTL Transmit queues:
* 0b0000..1 MTL Tx Queue
* 0b0001..2 MTL Tx Queues
* 0b0010..3 MTL Tx Queues
* 0b0011..4 MTL Tx Queues
* 0b0100..5 MTL Tx Queues
* 0b0101..Reserved
* 0b0110..Reserved
* 0b0111..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXQCNT_MASK)
#define ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK (0x80U)
#define ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT (7U)
/*! MGKSEL - PMT Magic Packet Enable This bit is set to 1 when the Enable Magic Packet Detection option is selected
* 0b1..PMT Magic Packet Enable option is selected
* 0b0..PMT Magic Packet Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MGKSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK (0x100U)
#define ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT (8U)
/*! MMCSEL - RMON Module Enable This bit is set to 1 when the Enable MAC Management Counters (MMC) option is selected
* 0b1..RMON Module Enable option is selected
* 0b0..RMON Module Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MMCSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)
#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)
/*! ARPOFFSEL - ARP Offload Enabled This bit is set to 1 when the Enable IPv4 ARP Offload option is selected
* 0b1..ARP Offload Enable option is selected
* 0b0..ARP Offload Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ARPOFFSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK (0x200U)
#define ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT (9U)
/*! PDUPSEL - Broadcast/Multicast Packet Duplication This bit is set to 1 when the
* Broadcast/Multicast Packet Duplication feature is selected.
* 0b1..Broadcast/Multicast Packet Duplication feature is selected
* 0b0..Broadcast/Multicast Packet Duplication feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_PDUPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PDUPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PDUPSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK (0x400U)
#define ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT (10U)
/*! FRPSEL - Flexible Receive Parser Selected This bit is set to 1 when the Enable Flexible
* Programmable Receive Parser option is selected.
* 0b1..Flexible Receive Parser feature is selected
* 0b0..Flexible Receive Parser feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_FRPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_FRPBS_MASK (0x1800U)
#define ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT (11U)
/*! FRPBS - Flexible Receive Parser Buffer size This field indicates the supported Max Number of
* bytes of the packet data to be Parsed by Flexible Receive Parser.
* 0b01..128 Bytes
* 0b10..256 Bytes
* 0b00..64 Bytes
* 0b11..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_FRPBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPBS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPBS_MASK)
#define ENET_QOS_MAC_HW_FEAT_OSTEN_MASK (0x800U)
#define ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT (11U)
/*! OSTEN - One-Step Timestamping Enable This bit is set to 1 when the Enable One-Step Timestamp Feature is selected.
* 0b1..One-Step Timestamping feature is selected
* 0b0..One-Step Timestamping feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_OSTEN_MASK)
#define ENET_QOS_MAC_HW_FEAT_PTOEN_MASK (0x1000U)
#define ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT (12U)
/*! PTOEN - PTP Offload Enable This bit is set to 1 when the Enable PTP Timestamp Offload Feature is selected.
* 0b1..PTP Offload feature is selected
* 0b0..PTP Offload feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PTOEN_MASK)
#define ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)
#define ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)
/*! RXCHCNT - Number of DMA Receive Channels This field indicates the number of DMA Receive channels:
* 0b0000..1 MTL Rx Channel
* 0b0001..2 MTL Rx Channels
* 0b0010..3 MTL Rx Channels
* 0b0011..4 MTL Rx Channels
* 0b0100..5 MTL Rx Channels
* 0b0101..Reserved
* 0b0110..Reserved
* 0b0111..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCHCNT_MASK)
#define ENET_QOS_MAC_HW_FEAT_TSSEL_MASK (0x1000U)
#define ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT (12U)
/*! TSSEL - IEEE 1588-2008 Timestamp Enabled This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
* 0b1..IEEE 1588-2008 Timestamp Enable option is selected
* 0b0..IEEE 1588-2008 Timestamp Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)
#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)
/*! ADVTHWORD - IEEE 1588 High Word Register Enable This bit is set to 1 when the Add IEEE 1588 Higher Word Register option is selected
* 0b1..IEEE 1588 High Word Register option is selected
* 0b0..IEEE 1588 High Word Register option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADVTHWORD_MASK)
#define ENET_QOS_MAC_HW_FEAT_EEESEL_MASK (0x2000U)
#define ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT (13U)
/*! EEESEL - Energy Efficient Ethernet Enabled This bit is set to 1 when the Enable Energy Efficient
* Ethernet (EEE) option is selected
* 0b1..Energy Efficient Ethernet Enable option is selected
* 0b0..Energy Efficient Ethernet Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_EEESEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_FRPES_MASK (0x6000U)
#define ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT (13U)
/*! FRPES - Flexible Receive Parser Table Entries size This field indicates the Max Number of Parser
* Entries supported by Flexible Receive Parser.
* 0b01..128 Entries
* 0b10..256 Entries
* 0b00..64 Entries
* 0b11..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_FRPES(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FRPES_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FRPES_MASK)
#define ENET_QOS_MAC_HW_FEAT_ADDR64_MASK (0xC000U)
#define ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT (14U)
/*! ADDR64 - Address Width.
* 0b00..32
* 0b01..40
* 0b10..48
* 0b11..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDR64_MASK)
#define ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)
#define ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)
/*! TXCOESEL - Transmit Checksum Offload Enabled This bit is set to 1 when the Enable Transmit
* TCP/IP Checksum Insertion option is selected
* 0b1..Transmit Checksum Offload Enable option is selected
* 0b0..Transmit Checksum Offload Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCOESEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_DCBEN_MASK (0x10000U)
#define ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT (16U)
/*! DCBEN - DCB Feature Enable This bit is set to 1 when the Enable Data Center Bridging option is selected
* 0b1..DCB Feature is selected
* 0b0..DCB Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DCBEN_MASK)
#define ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK (0x10000U)
#define ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT (16U)
/*! ESTSEL - Enhancements to Scheduling Traffic Enable This bit is set to 1 when the Enable
* Enhancements to Scheduling Traffic feature is selected.
* 0b1..Enable Enhancements to Scheduling Traffic feature is selected
* 0b0..Enable Enhancements to Scheduling Traffic feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_ESTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)
#define ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)
/*! RXCOESEL - Receive Checksum Offload Enabled This bit is set to 1 when the Enable Receive TCP/IP Checksum Check option is selected
* 0b1..Receive Checksum Offload Enable option is selected
* 0b0..Receive Checksum Offload Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RXCOESEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK (0xE0000U)
#define ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT (17U)
/*! ESTDEP - Depth of the Gate Control List This field indicates the depth of Gate Control list expressed as Log2(DWC_EQOS_EST_DEP)-5
* 0b101..1024
* 0b010..128
* 0b011..256
* 0b100..512
* 0b001..64
* 0b000..No Depth configured
* 0b110..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_ESTDEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTDEP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTDEP_MASK)
#define ENET_QOS_MAC_HW_FEAT_SPHEN_MASK (0x20000U)
#define ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT (17U)
/*! SPHEN - Split Header Feature Enable This bit is set to 1 when the Enable Split Header Structure option is selected
* 0b1..Split Header Feature is selected
* 0b0..Split Header Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_SPHEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SPHEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SPHEN_MASK)
#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK (0x7C0000U)
#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT (18U)
/*! ADDMACADRSEL - MAC Addresses 1-31 Selected This bit is set to 1 when the non-zero value is
* selected for Enable Additional 1-31 MAC Address Registers option
*/
#define ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ADDMACADRSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_TSOEN_MASK (0x40000U)
#define ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT (18U)
/*! TSOEN - TCP Segmentation Offload Enable This bit is set to 1 when the Enable TCP Segmentation
* Offloading for TCP/IP Packets option is selected
* 0b1..TCP Segmentation Offload Feature is selected
* 0b0..TCP Segmentation Offload Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSOEN_MASK)
#define ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)
#define ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)
/*! TXCHCNT - Number of DMA Transmit Channels This field indicates the number of DMA Transmit channels:
* 0b0000..1 MTL Tx Channel
* 0b0001..2 MTL Tx Channels
* 0b0010..3 MTL Tx Channels
* 0b0011..4 MTL Tx Channels
* 0b0100..5 MTL Tx Channels
* 0b0101..Reserved
* 0b0110..Reserved
* 0b0111..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TXCHCNT_MASK)
#define ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)
#define ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)
/*! DBGMEMA - DMA Debug Registers Enable This bit is set to 1 when the Debug Mode Enable option is selected
* 0b1..DMA Debug Registers option is selected
* 0b0..DMA Debug Registers option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_QOS_MAC_HW_FEAT_DBGMEMA_MASK)
#define ENET_QOS_MAC_HW_FEAT_AVSEL_MASK (0x100000U)
#define ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT (20U)
/*! AVSEL - AV Feature Enable This bit is set to 1 when the Enable Audio Video Bridging option is selected.
* 0b1..AV Feature is selected
* 0b0..AV Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AVSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ESTWID_MASK (0x300000U)
#define ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT (20U)
/*! ESTWID - Width of the Time Interval field in the Gate Control List This field indicates the
* width of the Configured Time Interval Field
* 0b00..Width not configured
* 0b01..16
* 0b10..20
* 0b11..24
*/
#define ENET_QOS_MAC_HW_FEAT_ESTWID(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ESTWID_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ESTWID_MASK)
#define ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK (0x200000U)
#define ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT (21U)
/*! RAVSEL - Rx Side Only AV Feature Enable This bit is set to 1 when the Enable Audio Video
* Bridging option on Rx Side Only is selected.
* 0b1..Rx Side Only AV Feature is selected
* 0b0..Rx Side Only AV Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_RAVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_RAVSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_RAVSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK (0x800000U)
#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT (23U)
/*! MACADR32SEL - MAC Addresses 32-63 Selected This bit is set to 1 when the Enable Additional 32
* MAC Address Registers (32-63) option is selected
* 0b1..MAC Addresses 32-63 Select option is selected
* 0b0..MAC Addresses 32-63 Select option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_MACADR32SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR32SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR32SEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_POUOST_MASK (0x800000U)
#define ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT (23U)
/*! POUOST - One Step for PTP over UDP/IP Feature Enable This bit is set to 1 when the Enable One
* step timestamp for PTP over UDP/IP feature is selected.
* 0b1..One Step for PTP over UDP/IP Feature is selected
* 0b0..One Step for PTP over UDP/IP Feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_POUOST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_POUOST_SHIFT)) & ENET_QOS_MAC_HW_FEAT_POUOST_MASK)
#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)
#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)
/*! HASHTBLSZ - Hash Table Size This field indicates the size of the hash table:
* 0b10..128
* 0b11..256
* 0b01..64
* 0b00..No hash table
*/
#define ENET_QOS_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_QOS_MAC_HW_FEAT_HASHTBLSZ_MASK)
#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK (0x1000000U)
#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT (24U)
/*! MACADR64SEL - MAC Addresses 64-127 Selected This bit is set to 1 when the Enable Additional 64
* MAC Address Registers (64-127) option is selected
* 0b1..MAC Addresses 64-127 Select option is selected
* 0b0..MAC Addresses 64-127 Select option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_MACADR64SEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_MACADR64SEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_MACADR64SEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)
#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)
/*! PPSOUTNUM - Number of PPS Outputs This field indicates the number of PPS outputs:
* 0b001..1 PPS output
* 0b010..2 PPS output
* 0b011..3 PPS output
* 0b100..4 PPS output
* 0b000..No PPS output
* 0b101..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_PPSOUTNUM_MASK)
#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)
#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)
/*! TSSTSSEL - Timestamp System Time Source This bit indicates the source of the Timestamp system
* time: This bit is set to 1 when the Enable IEEE 1588 Timestamp Support option is selected
* 0b10..Both
* 0b01..External
* 0b00..Internal
* 0b11..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TSSTSSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_FPESEL_MASK (0x4000000U)
#define ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT (26U)
/*! FPESEL - Frame Preemption Enable This bit is set to 1 when the Enable Frame preemption feature is selected.
* 0b1..Frame Preemption Enable feature is selected
* 0b0..Frame Preemption Enable feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_FPESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_FPESEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_FPESEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK (0x78000000U)
#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT (27U)
/*! L3L4FNUM - Total number of L3 or L4 Filters This field indicates the total number of L3 or L4 filters:
* 0b0001..1 L3 or L4 Filter
* 0b0010..2 L3 or L4 Filters
* 0b0011..3 L3 or L4 Filters
* 0b0100..4 L3 or L4 Filters
* 0b0101..5 L3 or L4 Filters
* 0b0110..6 L3 or L4 Filters
* 0b0111..7 L3 or L4 Filters
* 0b1000..8 L3 or L4 Filters
* 0b0000..No L3 or L4 Filter
*/
#define ENET_QOS_MAC_HW_FEAT_L3L4FNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_L3L4FNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_L3L4FNUM_MASK)
#define ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK (0x8000000U)
#define ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT (27U)
/*! SAVLANINS - Source Address or VLAN Insertion Enable This bit is set to 1 when the Enable SA and
* VLAN Insertion on Tx option is selected
* 0b1..Source Address or VLAN Insertion Enable option is selected
* 0b0..Source Address or VLAN Insertion Enable option is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_SAVLANINS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_SAVLANINS_SHIFT)) & ENET_QOS_MAC_HW_FEAT_SAVLANINS_MASK)
#define ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK (0x8000000U)
#define ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT (27U)
/*! TBSSEL - Time Based Scheduling Enable This bit is set to 1 when the Time Based Scheduling feature is selected.
* 0b1..Time Based Scheduling Enable feature is selected
* 0b0..Time Based Scheduling Enable feature is not selected
*/
#define ENET_QOS_MAC_HW_FEAT_TBSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_TBSSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_TBSSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)
#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)
/*! ACTPHYSEL - Active PHY Selected When you have multiple PHY interfaces in your configuration,
* this field indicates the sampled value of phy_intf_sel_i during reset de-assertion.
* 0b000..GMII or MII
* 0b111..RevMII
* 0b001..RGMII
* 0b100..RMII
* 0b101..RTBI
* 0b010..SGMII
* 0b110..SMII
* 0b011..TBI
*/
#define ENET_QOS_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ACTPHYSEL_MASK)
#define ENET_QOS_MAC_HW_FEAT_ASP_MASK (0x30000000U)
#define ENET_QOS_MAC_HW_FEAT_ASP_SHIFT (28U)
/*! ASP - Automotive Safety Package Following are the encoding for the different Safety features
* 0b10..All the Automotive Safety features are selected without the "Parity Port Enable for external interface" feature
* 0b11..All the Automotive Safety features are selected with the "Parity Port Enable for external interface" feature
* 0b01..Only "ECC protection for external memory" feature is selected
* 0b00..No Safety features selected
*/
#define ENET_QOS_MAC_HW_FEAT_ASP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_ASP_SHIFT)) & ENET_QOS_MAC_HW_FEAT_ASP_MASK)
#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)
#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)
/*! AUXSNAPNUM - Number of Auxiliary Snapshot Inputs This field indicates the number of auxiliary snapshot inputs:
* 0b001..1 auxiliary input
* 0b010..2 auxiliary input
* 0b011..3 auxiliary input
* 0b100..4 auxiliary input
* 0b000..No auxiliary input
* 0b101..Reserved
*/
#define ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_QOS_MAC_HW_FEAT_AUXSNAPNUM_MASK)
/*! @} */
/* The count of ENET_QOS_MAC_HW_FEAT */
#define ENET_QOS_MAC_HW_FEAT_COUNT (4U)
/*! @name MAC_MDIO_ADDRESS - MDIO Address */
/*! @{ */
#define ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK (0x1U)
#define ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT (0U)
/*! GB - GMII Busy The application sets this bit to instruct the SMA to initiate a Read or Write access to the MDIO slave.
* 0b0..GMII Busy is disabled
* 0b1..GMII Busy is enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_GB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GB_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK (0x2U)
#define ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT (1U)
/*! C45E - Clause 45 PHY Enable When this bit is set, Clause 45 capable PHY is connected to MDIO.
* 0b0..Clause 45 PHY is disabled
* 0b1..Clause 45 PHY is enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_C45E(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_C45E_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_C45E_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK (0x4U)
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT (2U)
/*! GOC_0 - GMII Operation Command 0 This is the lower bit of the operation command to the PHY or RevMII.
* 0b0..GMII Operation Command 0 is disabled
* 0b1..GMII Operation Command 0 is enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_0_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK (0x8U)
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT (3U)
/*! GOC_1 - GMII Operation Command 1 This bit is higher bit of the operation command to the PHY or
* RevMII, GOC_1 and GOC_O is encoded as follows: - 00: Reserved - 01: Write - 10: Post Read
* Increment Address for Clause 45 PHY - 11: Read When Clause 22 PHY or RevMII is enabled, only Write
* and Read commands are valid.
* 0b0..GMII Operation Command 1 is disabled
* 0b1..GMII Operation Command 1 is enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_GOC_1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_GOC_1_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK (0x10U)
#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT (4U)
/*! SKAP - Skip Address Packet When this bit is set, the SMA does not send the address packets
* before read, write, or post-read increment address packets.
* 0b0..Skip Address Packet is disabled
* 0b1..Skip Address Packet is enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_SKAP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_SKAP_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_SKAP_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK (0xF00U)
#define ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT (8U)
/*! CR - CSR Clock Range The CSR Clock Range selection determines the frequency of the MDC clock
* according to the CSR clock frequency used in your design: - 0000: CSR clock = 60-100 MHz; MDC
* clock = CSR clock/42 - 0001: CSR clock = 100-150 MHz; MDC clock = CSR clock/62 - 0010: CSR clock
* = 20-35 MHz; MDC clock = CSR clock/16 - 0011: CSR clock = 35-60 MHz; MDC clock = CSR clock/26
* - 0100: CSR clock = 150-250 MHz; MDC clock = CSR clock/102 - 0101: CSR clock = 250-300 MHz;
* MDC clock = CSR clock/124 - 0110: CSR clock = 300-500 MHz; MDC clock = CSR clock/204 - 0111: CSR
* clock = 500-800 MHz; MDC clock = CSR clock/324 The suggested range of CSR clock frequency
* applicable for each value (when Bit 11 = 0) ensures that the MDC clock is approximately between 1.
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_CR_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_CR_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK (0x7000U)
#define ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT (12U)
/*! NTC - Number of Trailing Clocks This field controls the number of trailing clock cycles
* generated on gmii_mdc_o (MDC) after the end of transmission of MDIO frame.
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_NTC_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_NTC_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK (0x1F0000U)
#define ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT (16U)
/*! RDA - Register/Device Address These bits select the PHY register in selected Clause 22 PHY device.
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_RDA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_RDA_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK (0x3E00000U)
#define ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT (21U)
/*! PA - Physical Layer Address This field indicates which Clause 22 PHY devices (out of 32 devices) the MAC is accessing.
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PA_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PA_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK (0x4000000U)
#define ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT (26U)
/*! BTB - Back to Back transactions When this bit is set and the NTC has value greater than 0, then
* the MAC informs the completion of a read or write command at the end of frame transfer (before
* the trailing clocks are transmitted).
* 0b0..Back to Back transactions disabled
* 0b1..Back to Back transactions enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_BTB_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_BTB_MASK)
#define ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK (0x8000000U)
#define ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT (27U)
/*! PSE - Preamble Suppression Enable When this bit is set, the SMA suppresses the 32-bit preamble
* and transmits MDIO frames with only 1 preamble bit.
* 0b0..Preamble Suppression disabled
* 0b1..Preamble Suppression enabled
*/
#define ENET_QOS_MAC_MDIO_ADDRESS_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_ADDRESS_PSE_SHIFT)) & ENET_QOS_MAC_MDIO_ADDRESS_PSE_MASK)
/*! @} */
/*! @name MAC_MDIO_DATA - MAC MDIO Data */
/*! @{ */
#define ENET_QOS_MAC_MDIO_DATA_GD_MASK (0xFFFFU)
#define ENET_QOS_MAC_MDIO_DATA_GD_SHIFT (0U)
/*! GD - GMII Data This field contains the 16-bit data value read from the PHY or RevMII after a
* Management Read operation or the 16-bit data value to be written to the PHY or RevMII before a
* Management Write operation.
*/
#define ENET_QOS_MAC_MDIO_DATA_GD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_GD_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_GD_MASK)
#define ENET_QOS_MAC_MDIO_DATA_RA_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_MDIO_DATA_RA_SHIFT (16U)
/*! RA - Register Address This field is valid only when C45E is set.
*/
#define ENET_QOS_MAC_MDIO_DATA_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MDIO_DATA_RA_SHIFT)) & ENET_QOS_MAC_MDIO_DATA_RA_MASK)
/*! @} */
/*! @name MAC_CSR_SW_CTRL - CSR Software Control */
/*! @{ */
#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK (0x1U)
#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT (0U)
/*! RCWE - Register Clear on Write 1 Enable When this bit is set, the access mode of some register
* fields changes to Clear on Write 1, the application needs to set that respective bit to 1 to
* clear it.
* 0b0..Register Clear on Write 1 is disabled
* 0b1..Register Clear on Write 1 is enabled
*/
#define ENET_QOS_MAC_CSR_SW_CTRL_RCWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_CSR_SW_CTRL_RCWE_SHIFT)) & ENET_QOS_MAC_CSR_SW_CTRL_RCWE_MASK)
/*! @} */
/*! @name MAC_FPE_CTRL_STS - Frame Preemption Control */
/*! @{ */
#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK (0x1U)
#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT (0U)
/*! EFPE - Enable Tx Frame Preemption When set Frame Preemption Tx functionality is enabled.
* 0b0..Tx Frame Preemption is disabled
* 0b1..Tx Frame Preemption is enabled
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_EFPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_EFPE_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_EFPE_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK (0x2U)
#define ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT (1U)
/*! SVER - Send Verify mPacket When set indicates hardware to send a verify mPacket.
* 0b0..Send Verify mPacket is disabled
* 0b1..Send Verify mPacket is enabled
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_SVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SVER_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK (0x4U)
#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT (2U)
/*! SRSP - Send Respond mPacket When set indicates hardware to send a Respond mPacket.
* 0b0..Send Respond mPacket is disabled
* 0b1..Send Respond mPacket is enabled
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_SRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_SRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_SRSP_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK (0x8U)
#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT (3U)
/*! S1_SET_0 - Synopsys Reserved, Must be set to "0".
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_S1_SET_0_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK (0x10000U)
#define ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT (16U)
/*! RVER - Received Verify Frame Set when a Verify mPacket is received.
* 0b1..Received Verify Frame
* 0b0..Not received Verify Frame
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_RVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RVER_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK (0x20000U)
#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT (17U)
/*! RRSP - Received Respond Frame Set when a Respond mPacket is received.
* 0b1..Received Respond Frame
* 0b0..Not received Respond Frame
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_RRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_RRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_RRSP_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK (0x40000U)
#define ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT (18U)
/*! TVER - Transmitted Verify Frame Set when a Verify mPacket is transmitted (triggered by setting SVER field).
* 0b1..transmitted Verify Frame
* 0b0..Not transmitted Verify Frame
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_TVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TVER_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TVER_MASK)
#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK (0x80000U)
#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT (19U)
/*! TRSP - Transmitted Respond Frame Set when a Respond mPacket is transmitted (triggered by setting SRSP field).
* 0b1..transmitted Respond Frame
* 0b0..Not transmitted Respond Frame
*/
#define ENET_QOS_MAC_FPE_CTRL_STS_TRSP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_FPE_CTRL_STS_TRSP_SHIFT)) & ENET_QOS_MAC_FPE_CTRL_STS_TRSP_MASK)
/*! @} */
/*! @name MAC_PRESN_TIME_NS - 32-bit Binary Rollover Equivalent Time */
/*! @{ */
#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT (0U)
/*! MPTN - MAC 1722 Presentation Time in ns These bits indicate the value of the 32-bit binary
* rollover equivalent time of the PTP System Time in ns
*/
#define ENET_QOS_MAC_PRESN_TIME_NS_MPTN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_NS_MPTN_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_NS_MPTN_MASK)
/*! @} */
/*! @name MAC_PRESN_TIME_UPDT - MAC 1722 Presentation Time */
/*! @{ */
#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT (0U)
/*! MPTU - MAC 1722 Presentation Time Update This field holds the init value or the update value for the presentation time.
*/
#define ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_SHIFT)) & ENET_QOS_MAC_PRESN_TIME_UPDT_MPTU_MASK)
/*! @} */
/*! @name HIGH - MAC Address0 High..MAC Address63 High */
/*! @{ */
#define ENET_QOS_HIGH_ADDRHI_MASK (0xFFFFU)
#define ENET_QOS_HIGH_ADDRHI_SHIFT (0U)
/*! ADDRHI - MAC ADDRESS32 [47:32] This field contains the upper 16 bits (47:32) of the 33rd 6-byte MAC address.
*/
#define ENET_QOS_HIGH_ADDRHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_ADDRHI_SHIFT)) & ENET_QOS_HIGH_ADDRHI_MASK)
#define ENET_QOS_HIGH_DCS_MASK (0x1F0000U) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define ENET_QOS_HIGH_DCS_SHIFT (16U)
/*! DCS - DMA Channel Select If the PDC bit of MAC_EXT_CONFIGURATION register is not set: This field
* contains the binary representation of the DMA Channel number to which an Rx packet whose DA
* matches the MAC Address(#i) content is routed.
*/
#define ENET_QOS_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_DCS_SHIFT)) & ENET_QOS_HIGH_DCS_MASK) /* Merged from fields with different position or width, of widths (3, 5), largest definition used */
#define ENET_QOS_HIGH_MBC_MASK (0x3F000000U)
#define ENET_QOS_HIGH_MBC_SHIFT (24U)
/*! MBC - Mask Byte Control These bits are mask control bits for comparing each of the MAC Address bytes.
*/
#define ENET_QOS_HIGH_MBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_MBC_SHIFT)) & ENET_QOS_HIGH_MBC_MASK)
#define ENET_QOS_HIGH_SA_MASK (0x40000000U)
#define ENET_QOS_HIGH_SA_SHIFT (30U)
/*! SA - Source Address When this bit is set, the MAC ADDRESS1[47:0] is used to compare with the SA
* fields of the received packet.
* 0b0..Compare with Destination Address
* 0b1..Compare with Source Address
*/
#define ENET_QOS_HIGH_SA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_SA_SHIFT)) & ENET_QOS_HIGH_SA_MASK)
#define ENET_QOS_HIGH_AE_MASK (0x80000000U)
#define ENET_QOS_HIGH_AE_SHIFT (31U)
/*! AE - Address Enable When this bit is set, the address filter module uses the second MAC address for perfect filtering.
* 0b0..INVALID : This bit must be always set to 1
* 0b1..This bit is always set to 1
*/
#define ENET_QOS_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_HIGH_AE_SHIFT)) & ENET_QOS_HIGH_AE_MASK)
/*! @} */
/* The count of ENET_QOS_HIGH */
#define ENET_QOS_HIGH_COUNT (64U)
/*! @name LOW - MAC Address0 Low..MAC Address63 Low */
/*! @{ */
#define ENET_QOS_LOW_ADDRLO_MASK (0xFFFFFFFFU)
#define ENET_QOS_LOW_ADDRLO_SHIFT (0U)
/*! ADDRLO - MAC ADDRESS32 [31:0] This field contains the lower 32 bits of the 33rd 6-byte MAC address.
*/
#define ENET_QOS_LOW_ADDRLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_LOW_ADDRLO_SHIFT)) & ENET_QOS_LOW_ADDRLO_MASK)
/*! @} */
/* The count of ENET_QOS_LOW */
#define ENET_QOS_LOW_COUNT (64U)
/*! @name MAC_MMC_CONTROL - MMC Control */
/*! @{ */
#define ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK (0x1U)
#define ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT (0U)
/*! CNTRST - Counters Reset When this bit is set, all counters are reset.
* 0b0..Counters are not reset
* 0b1..All counters are reset
*/
#define ENET_QOS_MAC_MMC_CONTROL_CNTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTRST_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK (0x2U)
#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT (1U)
/*! CNTSTOPRO - Counter Stop Rollover When this bit is set, the counter does not roll over to zero after reaching the maximum value.
* 0b0..Counter Stop Rollover is disabled
* 0b1..Counter Stop Rollover is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTSTOPRO_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK (0x4U)
#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT (2U)
/*! RSTONRD - Reset on Read When this bit is set, the MMC counters are reset to zero after Read (self-clearing after reset).
* 0b0..Reset on Read is disabled
* 0b1..Reset on Read is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_RSTONRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_RSTONRD_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_RSTONRD_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK (0x8U)
#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT (3U)
/*! CNTFREEZ - MMC Counter Freeze When this bit is set, it freezes all MMC counters to their current value.
* 0b0..MMC Counter Freeze is disabled
* 0b1..MMC Counter Freeze is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTFREEZ_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK (0x10U)
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT (4U)
/*! CNTPRST - Counters Preset When this bit is set, all counters are initialized or preset to almost
* full or almost half according to the CNTPRSTLVL bit.
* 0b0..Counters Preset is disabled
* 0b1..Counters Preset is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRST_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRST_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK (0x20U)
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT (5U)
/*! CNTPRSTLVL - Full-Half Preset When this bit is low and the CNTPRST bit is set, all MMC counters get preset to almost-half value.
* 0b0..Full-Half Preset is disabled
* 0b1..Full-Half Preset is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_CNTPRSTLVL_MASK)
#define ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK (0x100U)
#define ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT (8U)
/*! UCDBC - Update MMC Counters for Dropped Broadcast Packets Note: The CNTRST bit has a higher priority than the CNTPRST bit.
* 0b0..Update MMC Counters for Dropped Broadcast Packets is disabled
* 0b1..Update MMC Counters for Dropped Broadcast Packets is enabled
*/
#define ENET_QOS_MAC_MMC_CONTROL_UCDBC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_CONTROL_UCDBC_SHIFT)) & ENET_QOS_MAC_MMC_CONTROL_UCDBC_MASK)
/*! @} */
/*! @name MAC_MMC_RX_INTERRUPT - MMC Rx Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK (0x1U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT (0U)
/*! RXGBPKTIS - MMC Receive Good Bad Packet Counter Interrupt Status This bit is set when the
* rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBPKTIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK (0x2U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT (1U)
/*! RXGBOCTIS - MMC Receive Good Bad Octet Counter Interrupt Status This bit is set when the
* rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Good Bad Octet Counter Interrupt Status detected
* 0b0..MMC Receive Good Bad Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGBOCTIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK (0x4U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT (2U)
/*! RXGOCTIS - MMC Receive Good Octet Counter Interrupt Status This bit is set when the
* rxoctetcount_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXGOCTIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK (0x8U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT (3U)
/*! RXBCGPIS - MMC Receive Broadcast Good Packet Counter Interrupt Status This bit is set when the
* rxbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive Broadcast Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXBCGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK (0x10U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT (4U)
/*! RXMCGPIS - MMC Receive Multicast Good Packet Counter Interrupt Status This bit is set when the
* rxmulticastpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Multicast Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive Multicast Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXMCGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK (0x20U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT (5U)
/*! RXCRCERPIS - MMC Receive CRC Error Packet Counter Interrupt Status This bit is set when the
* rxcrcerror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive CRC Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive CRC Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCRCERPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK (0x40U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT (6U)
/*! RXALGNERPIS - MMC Receive Alignment Error Packet Counter Interrupt Status This bit is set when
* the rxalignmenterror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Alignment Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Alignment Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXALGNERPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK (0x80U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT (7U)
/*! RXRUNTPIS - MMC Receive Runt Packet Counter Interrupt Status This bit is set when the
* rxrunterror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Runt Packet Counter Interrupt Status detected
* 0b0..MMC Receive Runt Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRUNTPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK (0x100U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT (8U)
/*! RXJABERPIS - MMC Receive Jabber Error Packet Counter Interrupt Status This bit is set when the
* rxjabbererror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Jabber Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Jabber Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXJABERPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK (0x200U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT (9U)
/*! RXUSIZEGPIS - MMC Receive Undersize Good Packet Counter Interrupt Status This bit is set when
* the rxundersize_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Undersize Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive Undersize Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUSIZEGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK (0x400U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT (10U)
/*! RXOSIZEGPIS - MMC Receive Oversize Good Packet Counter Interrupt Status This bit is set when the
* rxoversize_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Oversize Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive Oversize Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXOSIZEGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK (0x800U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT (11U)
/*! RX64OCTGBPIS - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
* when the rx64octets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX64OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT (12U)
/*! RX65T127OCTGBPIS - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status This bit
* is set when the rx65to127octets_gb counter reaches half of the maximum value or the maximum
* value.
* 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX65T127OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT (13U)
/*! RX128T255OCTGBPIS - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the rx128to255octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX128T255OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK (0x4000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT (14U)
/*! RX256T511OCTGBPIS - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the rx256to511octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX256T511OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK (0x8000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT (15U)
/*! RX512T1023OCTGBPIS - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the rx512to1023octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX512T1023OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT (16U)
/*! RX1024TMAXOCTGBPIS - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
* This bit is set when the rx1024tomaxoctets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RX1024TMAXOCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT (17U)
/*! RXUCGPIS - MMC Receive Unicast Good Packet Counter Interrupt Status This bit is set when the
* rxunicastpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Unicast Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive Unicast Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXUCGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT (18U)
/*! RXLENERPIS - MMC Receive Length Error Packet Counter Interrupt Status This bit is set when the
* rxlengtherror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Length Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Length Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLENERPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT (19U)
/*! RXORANGEPIS - MMC Receive Out Of Range Error Packet Counter Interrupt Status.
* 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXORANGEPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT (20U)
/*! RXPAUSPIS - MMC Receive Pause Packet Counter Interrupt Status This bit is set when the
* rxpausepackets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Pause Packet Counter Interrupt Status detected
* 0b0..MMC Receive Pause Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXPAUSPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT (21U)
/*! RXFOVPIS - MMC Receive FIFO Overflow Packet Counter Interrupt Status This bit is set when the
* rxfifooverflow counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Status detected
* 0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXFOVPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT (22U)
/*! RXVLANGBPIS - MMC Receive VLAN Good Bad Packet Counter Interrupt Status This bit is set when the
* rxvlanpackets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXVLANGBPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT (23U)
/*! RXWDOGPIS - MMC Receive Watchdog Error Packet Counter Interrupt Status This bit is set when the
* rxwatchdog error counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Watchdog Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXWDOGPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT (24U)
/*! RXRCVERRPIS - MMC Receive Error Packet Counter Interrupt Status This bit is set when the
* rxrcverror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXRCVERRPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT (25U)
/*! RXCTRLPIS - MMC Receive Control Packet Counter Interrupt Status This bit is set when the
* rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive Control Packet Counter Interrupt Status detected
* 0b0..MMC Receive Control Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXCTRLPIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT (26U)
/*! RXLPIUSCIS - MMC Receive LPI microsecond counter interrupt status This bit is set when the
* Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive LPI microsecond Counter Interrupt Status detected
* 0b0..MMC Receive LPI microsecond Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPIUSCIS_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT (27U)
/*! RXLPITRCIS - MMC Receive LPI transition counter interrupt status This bit is set when the
* Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive LPI transition Counter Interrupt Status detected
* 0b0..MMC Receive LPI transition Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_RXLPITRCIS_MASK)
/*! @} */
/*! @name MAC_MMC_TX_INTERRUPT - MMC Tx Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK (0x1U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT (0U)
/*! TXGBOCTIS - MMC Transmit Good Bad Octet Counter Interrupt Status This bit is set when the
* txoctetcount_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Good Bad Octet Counter Interrupt Status detected
* 0b0..MMC Transmit Good Bad Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBOCTIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK (0x2U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT (1U)
/*! TXGBPKTIS - MMC Transmit Good Bad Packet Counter Interrupt Status This bit is set when the
* txpacketcount_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGBPKTIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK (0x4U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT (2U)
/*! TXBCGPIS - MMC Transmit Broadcast Good Packet Counter Interrupt Status This bit is set when the
* txbroadcastpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK (0x8U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT (3U)
/*! TXMCGPIS - MMC Transmit Multicast Good Packet Counter Interrupt Status This bit is set when the
* txmulticastpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Multicast Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK (0x10U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT (4U)
/*! TX64OCTGBPIS - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status This bit is set
* when the tx64octets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX64OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK (0x20U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT (5U)
/*! TX65T127OCTGBPIS - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the tx65to127octets_gb counter reaches half the maximum value, and also when it
* reaches the maximum value.
* 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX65T127OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK (0x40U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT (6U)
/*! TX128T255OCTGBPIS - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the tx128to255octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX128T255OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK (0x80U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT (7U)
/*! TX256T511OCTGBPIS - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status This
* bit is set when the tx256to511octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX256T511OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK (0x100U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT (8U)
/*! TX512T1023OCTGBPIS - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status
* This bit is set when the tx512to1023octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX512T1023OCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK (0x200U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT (9U)
/*! TX1024TMAXOCTGBPIS - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status
* This bit is set when the tx1024tomaxoctets_gb counter reaches half of the maximum value or
* the maximum value.
* 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TX1024TMAXOCTGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK (0x400U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT (10U)
/*! TXUCGBPIS - MMC Transmit Unicast Good Bad Packet Counter Interrupt Status This bit is set when
* the txunicastpackets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUCGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK (0x800U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT (11U)
/*! TXMCGBPIS - MMC Transmit Multicast Good Bad Packet Counter Interrupt Status The bit is set when
* the txmulticastpackets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT (12U)
/*! TXBCGBPIS - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status This bit is set when
* the txbroadcastpackets_gb counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXBCGBPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT (13U)
/*! TXUFLOWERPIS - MMC Transmit Underflow Error Packet Counter Interrupt Status This bit is set when
* the txunderflowerror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Underflow Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXUFLOWERPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK (0x4000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT (14U)
/*! TXSCOLGPIS - MMC Transmit Single Collision Good Packet Counter Interrupt Status This bit is set
* when the txsinglecol_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXSCOLGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK (0x8000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT (15U)
/*! TXMCOLGPIS - MMC Transmit Multiple Collision Good Packet Counter Interrupt Status This bit is
* set when the txmulticol_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXMCOLGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT (16U)
/*! TXDEFPIS - MMC Transmit Deferred Packet Counter Interrupt Status This bit is set when the
* txdeferred counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Deferred Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Deferred Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXDEFPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT (17U)
/*! TXLATCOLPIS - MMC Transmit Late Collision Packet Counter Interrupt Status This bit is set when
* the txlatecol counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Late Collision Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Late Collision Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLATCOLPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT (18U)
/*! TXEXCOLPIS - MMC Transmit Excessive Collision Packet Counter Interrupt Status This bit is set
* when the txexesscol counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXCOLPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT (19U)
/*! TXCARERPIS - MMC Transmit Carrier Error Packet Counter Interrupt Status This bit is set when the
* txcarriererror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Carrier Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXCARERPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT (20U)
/*! TXGOCTIS - MMC Transmit Good Octet Counter Interrupt Status This bit is set when the
* txoctetcount_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Good Octet Counter Interrupt Status detected
* 0b0..MMC Transmit Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGOCTIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT (21U)
/*! TXGPKTIS - MMC Transmit Good Packet Counter Interrupt Status This bit is set when the
* txpacketcount_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXGPKTIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT (22U)
/*! TXEXDEFPIS - MMC Transmit Excessive Deferral Packet Counter Interrupt Status This bit is set
* when the txexcessdef counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXEXDEFPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT (23U)
/*! TXPAUSPIS - MMC Transmit Pause Packet Counter Interrupt Status This bit is set when the
* txpausepacketserror counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Pause Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Pause Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXPAUSPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT (24U)
/*! TXVLANGPIS - MMC Transmit VLAN Good Packet Counter Interrupt Status This bit is set when the
* txvlanpackets_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit VLAN Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXVLANGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT (25U)
/*! TXOSIZEGPIS - MMC Transmit Oversize Good Packet Counter Interrupt Status This bit is set when
* the txoversize_g counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Status detected
* 0b0..MMC Transmit Oversize Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXOSIZEGPIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT (26U)
/*! TXLPIUSCIS - MMC Transmit LPI microsecond counter interrupt status This bit is set when the
* Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit LPI microsecond Counter Interrupt Status detected
* 0b0..MMC Transmit LPI microsecond Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPIUSCIS_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT (27U)
/*! TXLPITRCIS - MMC Transmit LPI transition counter interrupt status This bit is set when the
* Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Transmit LPI transition Counter Interrupt Status detected
* 0b0..MMC Transmit LPI transition Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_TXLPITRCIS_MASK)
/*! @} */
/*! @name MAC_MMC_RX_INTERRUPT_MASK - MMC Rx Interrupt Mask */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK (0x1U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT (0U)
/*! RXGBPKTIM - MMC Receive Good Bad Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxpacketcount_gb counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBPKTIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK (0x2U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT (1U)
/*! RXGBOCTIM - MMC Receive Good Bad Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxoctetcount_gb counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Good Bad Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Good Bad Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGBOCTIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK (0x4U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT (2U)
/*! RXGOCTIM - MMC Receive Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
* when the rxoctetcount_g counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXGOCTIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK (0x8U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT (3U)
/*! RXBCGPIM - MMC Receive Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxbroadcastpackets_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive Broadcast Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Broadcast Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXBCGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK (0x10U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT (4U)
/*! RXMCGPIM - MMC Receive Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxmulticastpackets_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive Multicast Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Multicast Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXMCGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK (0x20U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT (5U)
/*! RXCRCERPIM - MMC Receive CRC Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxcrcerror counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive CRC Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive CRC Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCRCERPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK (0x40U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT (6U)
/*! RXALGNERPIM - MMC Receive Alignment Error Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxalignmenterror counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive Alignment Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Alignment Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXALGNERPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK (0x80U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT (7U)
/*! RXRUNTPIM - MMC Receive Runt Packet Counter Interrupt Mask Setting this bit masks the interrupt
* when the rxrunterror counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Runt Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Runt Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRUNTPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK (0x100U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT (8U)
/*! RXJABERPIM - MMC Receive Jabber Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxjabbererror counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Jabber Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Jabber Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXJABERPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK (0x200U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT (9U)
/*! RXUSIZEGPIM - MMC Receive Undersize Good Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxundersize_g counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive Undersize Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Undersize Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUSIZEGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK (0x400U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT (10U)
/*! RXOSIZEGPIM - MMC Receive Oversize Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxoversize_g counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive Oversize Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Oversize Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXOSIZEGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK (0x800U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT (11U)
/*! RX64OCTGBPIM - MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rx64octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX64OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT (12U)
/*! RX65T127OCTGBPIM - MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the rx65to127octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX65T127OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT (13U)
/*! RX128T255OCTGBPIM - MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the rx128to255octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX128T255OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK (0x4000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT (14U)
/*! RX256T511OCTGBPIM - MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the rx256to511octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX256T511OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK (0x8000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT (15U)
/*! RX512T1023OCTGBPIM - MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
* Setting this bit masks the interrupt when the rx512to1023octets_gb counter reaches half of the
* maximum value or the maximum value.
* 0b0..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX512T1023OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT (16U)
/*! RX1024TMAXOCTGBPIM - MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask.
* 0b0..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RX1024TMAXOCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT (17U)
/*! RXUCGPIM - MMC Receive Unicast Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxunicastpackets_g counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive Unicast Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Unicast Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXUCGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT (18U)
/*! RXLENERPIM - MMC Receive Length Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxlengtherror counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Length Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Length Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLENERPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT (19U)
/*! RXORANGEPIM - MMC Receive Out Of Range Error Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxoutofrangetype counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Out Of Range Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXORANGEPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT (20U)
/*! RXPAUSPIM - MMC Receive Pause Packet Counter Interrupt Mask Setting this bit masks the interrupt
* when the rxpausepackets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Pause Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Pause Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXPAUSPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT (21U)
/*! RXFOVPIM - MMC Receive FIFO Overflow Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxfifooverflow counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive FIFO Overflow Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXFOVPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT (22U)
/*! RXVLANGBPIM - MMC Receive VLAN Good Bad Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxvlanpackets_gb counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive VLAN Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXVLANGBPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT (23U)
/*! RXWDOGPIM - MMC Receive Watchdog Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxwatchdog counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Watchdog Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Watchdog Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXWDOGPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT (24U)
/*! RXRCVERRPIM - MMC Receive Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxrcverror counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXRCVERRPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT (25U)
/*! RXCTRLPIM - MMC Receive Control Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxctrlpackets_g counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive Control Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive Control Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXCTRLPIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT (26U)
/*! RXLPIUSCIM - MMC Receive LPI microsecond counter interrupt Mask Setting this bit masks the
* interrupt when the Rx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive LPI microsecond counter interrupt Mask is disabled
* 0b1..MMC Receive LPI microsecond counter interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPIUSCIM_MASK)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT (27U)
/*! RXLPITRCIM - MMC Receive LPI transition counter interrupt Mask Setting this bit masks the
* interrupt when the Rx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive LPI transition counter interrupt Mask is disabled
* 0b1..MMC Receive LPI transition counter interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_RX_INTERRUPT_MASK_RXLPITRCIM_MASK)
/*! @} */
/*! @name MAC_MMC_TX_INTERRUPT_MASK - MMC Tx Interrupt Mask */
/*! @{ */
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK (0x1U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT (0U)
/*! TXGBOCTIM - MMC Transmit Good Bad Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txoctetcount_gb counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Good Bad Octet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Good Bad Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBOCTIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK (0x2U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT (1U)
/*! TXGBPKTIM - MMC Transmit Good Bad Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txpacketcount_gb counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGBPKTIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK (0x4U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT (2U)
/*! TXBCGPIM - MMC Transmit Broadcast Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txbroadcastpackets_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Broadcast Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK (0x8U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT (3U)
/*! TXMCGPIM - MMC Transmit Multicast Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txmulticastpackets_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Multicast Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Multicast Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK (0x10U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT (4U)
/*! TX64OCTGBPIM - MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the tx64octets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 64 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX64OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK (0x20U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT (5U)
/*! TX65T127OCTGBPIM - MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the tx65to127octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 65 to 127 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX65T127OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK (0x40U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT (6U)
/*! TX128T255OCTGBPIM - MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the tx128to255octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 128 to 255 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX128T255OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK (0x80U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT (7U)
/*! TX256T511OCTGBPIM - MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the tx256to511octets_gb counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 256 to 511 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX256T511OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK (0x100U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT (8U)
/*! TX512T1023OCTGBPIM - MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask
* Setting this bit masks the interrupt when the tx512to1023octets_gb counter reaches half of the
* maximum value or the maximum value.
* 0b0..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 512 to 1023 Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX512T1023OCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK (0x200U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT (9U)
/*! TX1024TMAXOCTGBPIM - MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask
* Setting this bit masks the interrupt when the tx1024tomaxoctets_gb counter reaches half of the
* maximum value or the maximum value.
* 0b0..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit 1024 to Maximum Octet Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TX1024TMAXOCTGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK (0x400U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT (10U)
/*! TXUCGBPIM - MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txunicastpackets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Unicast Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUCGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK (0x800U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT (11U)
/*! TXMCGBPIM - MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txmulticastpackets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Multicast Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT (12U)
/*! TXBCGBPIM - MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txbroadcastpackets_gb counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Broadcast Good Bad Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXBCGBPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT (13U)
/*! TXUFLOWERPIM - MMC Transmit Underflow Error Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txunderflowerror counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Underflow Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Underflow Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXUFLOWERPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK (0x4000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT (14U)
/*! TXSCOLGPIM - MMC Transmit Single Collision Good Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the txsinglecol_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Single Collision Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXSCOLGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK (0x8000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT (15U)
/*! TXMCOLGPIM - MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the txmulticol_g counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXMCOLGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT (16U)
/*! TXDEFPIM - MMC Transmit Deferred Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txdeferred counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Deferred Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Deferred Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXDEFPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT (17U)
/*! TXLATCOLPIM - MMC Transmit Late Collision Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txlatecol counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Late Collision Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Late Collision Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLATCOLPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT (18U)
/*! TXEXCOLPIM - MMC Transmit Excessive Collision Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the txexcesscol counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Excessive Collision Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXCOLPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT (19U)
/*! TXCARERPIM - MMC Transmit Carrier Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txcarriererror counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Transmit Carrier Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Carrier Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXCARERPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT (20U)
/*! TXGOCTIM - MMC Transmit Good Octet Counter Interrupt Mask Setting this bit masks the interrupt
* when the txoctetcount_g counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGOCTIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT (21U)
/*! TXGPKTIM - MMC Transmit Good Packet Counter Interrupt Mask Setting this bit masks the interrupt
* when the txpacketcount_g counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXGPKTIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT (22U)
/*! TXEXDEFPIM - MMC Transmit Excessive Deferral Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the txexcessdef counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Excessive Deferral Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXEXDEFPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT (23U)
/*! TXPAUSPIM - MMC Transmit Pause Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txpausepackets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Pause Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Pause Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXPAUSPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT (24U)
/*! TXVLANGPIM - MMC Transmit VLAN Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the txvlanpackets_g counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit VLAN Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit VLAN Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXVLANGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT (25U)
/*! TXOSIZEGPIM - MMC Transmit Oversize Good Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the txoversize_g counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Transmit Oversize Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Oversize Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXOSIZEGPIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT (26U)
/*! TXLPIUSCIM - MMC Transmit LPI microsecond counter interrupt Mask Setting this bit masks the
* interrupt when the Tx_LPI_USEC_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit LPI microsecond counter interrupt Mask is disabled
* 0b1..MMC Transmit LPI microsecond counter interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPIUSCIM_MASK)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT (27U)
/*! TXLPITRCIM - MMC Transmit LPI transition counter interrupt Mask Setting this bit masks the
* interrupt when the Tx_LPI_Tran_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit LPI transition counter interrupt Mask is disabled
* 0b1..MMC Transmit LPI transition counter interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_SHIFT)) & ENET_QOS_MAC_MMC_TX_INTERRUPT_MASK_TXLPITRCIM_MASK)
/*! @} */
/*! @name MAC_TX_OCTET_COUNT_GOOD_BAD - Tx Octet Count Good and Bad */
/*! @{ */
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT (0U)
/*! TXOCTGB - Tx Octet Count Good Bad This field indicates the number of bytes transmitted,
* exclusive of preamble and retried bytes, in good and bad packets.
*/
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_BAD_TXOCTGB_MASK)
/*! @} */
/*! @name MAC_TX_PACKET_COUNT_GOOD_BAD - Tx Packet Count Good and Bad */
/*! @{ */
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT (0U)
/*! TXPKTGB - Tx Packet Count Good Bad This field indicates the number of good and bad packets
* transmitted, exclusive of retried packets.
*/
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_BAD_TXPKTGB_MASK)
/*! @} */
/*! @name MAC_TX_BROADCAST_PACKETS_GOOD - Tx Broadcast Packets Good */
/*! @{ */
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT (0U)
/*! TXBCASTG - Tx Broadcast Packets Good This field indicates the number of good broadcast packets transmitted.
*/
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_TXBCASTG_MASK)
/*! @} */
/*! @name MAC_TX_MULTICAST_PACKETS_GOOD - Tx Multicast Packets Good */
/*! @{ */
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT (0U)
/*! TXMCASTG - Tx Multicast Packets Good This field indicates the number of good multicast packets transmitted.
*/
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_TXMCASTG_MASK)
/*! @} */
/*! @name MAC_TX_64OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 64-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT (0U)
/*! TX64OCTGB - Tx 64Octets Packets Good_Bad This field indicates the number of good and bad packets
* transmitted with length 64 bytes, exclusive of preamble and retried packets.
*/
#define ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_SHIFT)) & ENET_QOS_MAC_TX_64OCTETS_PACKETS_GOOD_BAD_TX64OCTGB_MASK)
/*! @} */
/*! @name MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 65 to 127-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT (0U)
/*! TX65_127OCTGB - Tx 65To127Octets Packets Good Bad This field indicates the number of good and
* bad packets transmitted with length between 65 and 127 (inclusive) bytes, exclusive of preamble
* and retried packets.
*/
#define ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_TX_65TO127OCTETS_PACKETS_GOOD_BAD_TX65_127OCTGB_MASK)
/*! @} */
/*! @name MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 128 to 255-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT (0U)
/*! TX128_255OCTGB - Tx 128To255Octets Packets Good Bad This field indicates the number of good and
* bad packets transmitted with length between 128 and 255 (inclusive) bytes, exclusive of
* preamble and retried packets.
*/
#define ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_TX_128TO255OCTETS_PACKETS_GOOD_BAD_TX128_255OCTGB_MASK)
/*! @} */
/*! @name MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 256 to 511-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT (0U)
/*! TX256_511OCTGB - Tx 256To511Octets Packets Good Bad This field indicates the number of good and
* bad packets transmitted with length between 256 and 511 (inclusive) bytes, exclusive of
* preamble and retried packets.
*/
#define ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_TX_256TO511OCTETS_PACKETS_GOOD_BAD_TX256_511OCTGB_MASK)
/*! @} */
/*! @name MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 512 to 1023-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT (0U)
/*! TX512_1023OCTGB - Tx 512To1023Octets Packets Good Bad This field indicates the number of good
* and bad packets transmitted with length between 512 and 1023 (inclusive) bytes, exclusive of
* preamble and retried packets.
*/
#define ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_TX_512TO1023OCTETS_PACKETS_GOOD_BAD_TX512_1023OCTGB_MASK)
/*! @} */
/*! @name MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Tx Good and Bad 1024 to Max-Byte Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT (0U)
/*! TX1024_MAXOCTGB - Tx 1024ToMaxOctets Packets Good Bad This field indicates the number of good
* and bad packets transmitted with length between 1024 and maxsize (inclusive) bytes, exclusive of
* preamble and retried packets.
*/
#define ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_TX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_TX1024_MAXOCTGB_MASK)
/*! @} */
/*! @name MAC_TX_UNICAST_PACKETS_GOOD_BAD - Good and Bad Unicast Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT (0U)
/*! TXUCASTGB - Tx Unicast Packets Good Bad This field indicates the number of good and bad unicast packets transmitted.
*/
#define ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_SHIFT)) & ENET_QOS_MAC_TX_UNICAST_PACKETS_GOOD_BAD_TXUCASTGB_MASK)
/*! @} */
/*! @name MAC_TX_MULTICAST_PACKETS_GOOD_BAD - Good and Bad Multicast Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT (0U)
/*! TXMCASTGB - Tx Multicast Packets Good Bad This field indicates the number of good and bad multicast packets transmitted.
*/
#define ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_SHIFT)) & ENET_QOS_MAC_TX_MULTICAST_PACKETS_GOOD_BAD_TXMCASTGB_MASK)
/*! @} */
/*! @name MAC_TX_BROADCAST_PACKETS_GOOD_BAD - Good and Bad Broadcast Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT (0U)
/*! TXBCASTGB - Tx Broadcast Packets Good Bad This field indicates the number of good and bad broadcast packets transmitted.
*/
#define ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_SHIFT)) & ENET_QOS_MAC_TX_BROADCAST_PACKETS_GOOD_BAD_TXBCASTGB_MASK)
/*! @} */
/*! @name MAC_TX_UNDERFLOW_ERROR_PACKETS - Tx Packets Aborted By Underflow Error */
/*! @{ */
#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT (0U)
/*! TXUNDRFLW - Tx Underflow Error Packets This field indicates the number of packets aborted because of packets underflow error.
*/
#define ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_SHIFT)) & ENET_QOS_MAC_TX_UNDERFLOW_ERROR_PACKETS_TXUNDRFLW_MASK)
/*! @} */
/*! @name MAC_TX_SINGLE_COLLISION_GOOD_PACKETS - Single Collision Good Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT (0U)
/*! TXSNGLCOLG - Tx Single Collision Good Packets This field indicates the number of successfully
* transmitted packets after a single collision in the half-duplex mode.
*/
#define ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_SHIFT)) & ENET_QOS_MAC_TX_SINGLE_COLLISION_GOOD_PACKETS_TXSNGLCOLG_MASK)
/*! @} */
/*! @name MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS - Multiple Collision Good Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT (0U)
/*! TXMULTCOLG - Tx Multiple Collision Good Packets This field indicates the number of successfully
* transmitted packets after multiple collisions in the half-duplex mode.
*/
#define ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_SHIFT)) & ENET_QOS_MAC_TX_MULTIPLE_COLLISION_GOOD_PACKETS_TXMULTCOLG_MASK)
/*! @} */
/*! @name MAC_TX_DEFERRED_PACKETS - Deferred Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT (0U)
/*! TXDEFRD - Tx Deferred Packets This field indicates the number of successfully transmitted after
* a deferral in the half-duplex mode.
*/
#define ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_SHIFT)) & ENET_QOS_MAC_TX_DEFERRED_PACKETS_TXDEFRD_MASK)
/*! @} */
/*! @name MAC_TX_LATE_COLLISION_PACKETS - Late Collision Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT (0U)
/*! TXLATECOL - Tx Late Collision Packets This field indicates the number of packets aborted because of late collision error.
*/
#define ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_SHIFT)) & ENET_QOS_MAC_TX_LATE_COLLISION_PACKETS_TXLATECOL_MASK)
/*! @} */
/*! @name MAC_TX_EXCESSIVE_COLLISION_PACKETS - Excessive Collision Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT (0U)
/*! TXEXSCOL - Tx Excessive Collision Packets This field indicates the number of packets aborted
* because of excessive (16) collision errors.
*/
#define ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_COLLISION_PACKETS_TXEXSCOL_MASK)
/*! @} */
/*! @name MAC_TX_CARRIER_ERROR_PACKETS - Carrier Error Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT (0U)
/*! TXCARR - Tx Carrier Error Packets This field indicates the number of packets aborted because of
* carrier sense error (no carrier or loss of carrier).
*/
#define ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_SHIFT)) & ENET_QOS_MAC_TX_CARRIER_ERROR_PACKETS_TXCARR_MASK)
/*! @} */
/*! @name MAC_TX_OCTET_COUNT_GOOD - Bytes Transmitted in Good Packets */
/*! @{ */
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT (0U)
/*! TXOCTG - Tx Octet Count Good This field indicates the number of bytes transmitted, exclusive of preamble, only in good packets.
*/
#define ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_SHIFT)) & ENET_QOS_MAC_TX_OCTET_COUNT_GOOD_TXOCTG_MASK)
/*! @} */
/*! @name MAC_TX_PACKET_COUNT_GOOD - Good Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT (0U)
/*! TXPKTG - Tx Packet Count Good This field indicates the number of good packets transmitted.
*/
#define ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_SHIFT)) & ENET_QOS_MAC_TX_PACKET_COUNT_GOOD_TXPKTG_MASK)
/*! @} */
/*! @name MAC_TX_EXCESSIVE_DEFERRAL_ERROR - Packets Aborted By Excessive Deferral Error */
/*! @{ */
#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT (0U)
/*! TXEXSDEF - Tx Excessive Deferral Error This field indicates the number of packets aborted
* because of excessive deferral error (deferred for more than two max-sized packet times).
*/
#define ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_SHIFT)) & ENET_QOS_MAC_TX_EXCESSIVE_DEFERRAL_ERROR_TXEXSDEF_MASK)
/*! @} */
/*! @name MAC_TX_PAUSE_PACKETS - Pause Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT (0U)
/*! TXPAUSE - Tx Pause Packets This field indicates the number of good Pause packets transmitted.
*/
#define ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_SHIFT)) & ENET_QOS_MAC_TX_PAUSE_PACKETS_TXPAUSE_MASK)
/*! @} */
/*! @name MAC_TX_VLAN_PACKETS_GOOD - Good VLAN Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT (0U)
/*! TXVLANG - Tx VLAN Packets Good This field provides the number of good VLAN packets transmitted.
*/
#define ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_SHIFT)) & ENET_QOS_MAC_TX_VLAN_PACKETS_GOOD_TXVLANG_MASK)
/*! @} */
/*! @name MAC_TX_OSIZE_PACKETS_GOOD - Good Oversize Packets Transmitted */
/*! @{ */
#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT (0U)
/*! TXOSIZG - Tx OSize Packets Good This field indicates the number of packets transmitted without
* errors and with length greater than the maxsize (1,518 or 1,522 bytes for VLAN tagged packets;
* 2000 bytes if enabled in S2KP bit of the CONFIGURATION register).
*/
#define ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_SHIFT)) & ENET_QOS_MAC_TX_OSIZE_PACKETS_GOOD_TXOSIZG_MASK)
/*! @} */
/*! @name MAC_RX_PACKETS_COUNT_GOOD_BAD - Good and Bad Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT (0U)
/*! RXPKTGB - Rx Packets Count Good Bad This field indicates the number of good and bad packets received.
*/
#define ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_SHIFT)) & ENET_QOS_MAC_RX_PACKETS_COUNT_GOOD_BAD_RXPKTGB_MASK)
/*! @} */
/*! @name MAC_RX_OCTET_COUNT_GOOD_BAD - Bytes in Good and Bad Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT (0U)
/*! RXOCTGB - Rx Octet Count Good Bad This field indicates the number of bytes received, exclusive
* of preamble, in good and bad packets.
*/
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_BAD_RXOCTGB_MASK)
/*! @} */
/*! @name MAC_RX_OCTET_COUNT_GOOD - Bytes in Good Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT (0U)
/*! RXOCTG - Rx Octet Count Good This field indicates the number of bytes received, exclusive of preamble, only in good packets.
*/
#define ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_SHIFT)) & ENET_QOS_MAC_RX_OCTET_COUNT_GOOD_RXOCTG_MASK)
/*! @} */
/*! @name MAC_RX_BROADCAST_PACKETS_GOOD - Good Broadcast Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT (0U)
/*! RXBCASTG - Rx Broadcast Packets Good This field indicates the number of good broadcast packets received.
*/
#define ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_SHIFT)) & ENET_QOS_MAC_RX_BROADCAST_PACKETS_GOOD_RXBCASTG_MASK)
/*! @} */
/*! @name MAC_RX_MULTICAST_PACKETS_GOOD - Good Multicast Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT (0U)
/*! RXMCASTG - Rx Multicast Packets Good This field indicates the number of good multicast packets received.
*/
#define ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_SHIFT)) & ENET_QOS_MAC_RX_MULTICAST_PACKETS_GOOD_RXMCASTG_MASK)
/*! @} */
/*! @name MAC_RX_CRC_ERROR_PACKETS - CRC Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT (0U)
/*! RXCRCERR - Rx CRC Error Packets This field indicates the number of packets received with CRC error.
*/
#define ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_SHIFT)) & ENET_QOS_MAC_RX_CRC_ERROR_PACKETS_RXCRCERR_MASK)
/*! @} */
/*! @name MAC_RX_ALIGNMENT_ERROR_PACKETS - Alignment Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT (0U)
/*! RXALGNERR - Rx Alignment Error Packets This field indicates the number of packets received with alignment (dribble) error.
*/
#define ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_SHIFT)) & ENET_QOS_MAC_RX_ALIGNMENT_ERROR_PACKETS_RXALGNERR_MASK)
/*! @} */
/*! @name MAC_RX_RUNT_ERROR_PACKETS - Runt Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT (0U)
/*! RXRUNTERR - Rx Runt Error Packets This field indicates the number of packets received with runt
* (length less than 64 bytes and CRC error) error.
*/
#define ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_SHIFT)) & ENET_QOS_MAC_RX_RUNT_ERROR_PACKETS_RXRUNTERR_MASK)
/*! @} */
/*! @name MAC_RX_JABBER_ERROR_PACKETS - Jabber Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT (0U)
/*! RXJABERR - Rx Jabber Error Packets This field indicates the number of giant packets received
* with length (including CRC) greater than 1,518 bytes (1,522 bytes for VLAN tagged) and with CRC
* error.
*/
#define ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_SHIFT)) & ENET_QOS_MAC_RX_JABBER_ERROR_PACKETS_RXJABERR_MASK)
/*! @} */
/*! @name MAC_RX_UNDERSIZE_PACKETS_GOOD - Good Undersize Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT (0U)
/*! RXUNDERSZG - Rx Undersize Packets Good This field indicates the number of packets received with
* length less than 64 bytes, without any errors.
*/
#define ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_SHIFT)) & ENET_QOS_MAC_RX_UNDERSIZE_PACKETS_GOOD_RXUNDERSZG_MASK)
/*! @} */
/*! @name MAC_RX_OVERSIZE_PACKETS_GOOD - Good Oversize Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT (0U)
/*! RXOVERSZG - Rx Oversize Packets Good This field indicates the number of packets received without
* errors, with length greater than the maxsize (1,518 bytes or 1,522 bytes for VLAN tagged
* packets; 2000 bytes if enabled in the S2KP bit of the MAC_CONFIGURATION register).
*/
#define ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_SHIFT)) & ENET_QOS_MAC_RX_OVERSIZE_PACKETS_GOOD_RXOVERSZG_MASK)
/*! @} */
/*! @name MAC_RX_64OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT (0U)
/*! RX64OCTGB - Rx 64 Octets Packets Good Bad This field indicates the number of good and bad
* packets received with length 64 bytes, exclusive of the preamble.
*/
#define ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_SHIFT)) & ENET_QOS_MAC_RX_64OCTETS_PACKETS_GOOD_BAD_RX64OCTGB_MASK)
/*! @} */
/*! @name MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD - Good and Bad 64-to-127 Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT (0U)
/*! RX65_127OCTGB - Rx 65-127 Octets Packets Good Bad This field indicates the number of good and
* bad packets received with length between 65 and 127 (inclusive) bytes, exclusive of the preamble.
*/
#define ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_SHIFT)) & ENET_QOS_MAC_RX_65TO127OCTETS_PACKETS_GOOD_BAD_RX65_127OCTGB_MASK)
/*! @} */
/*! @name MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD - Good and Bad 128-to-255 Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT (0U)
/*! RX128_255OCTGB - Rx 128-255 Octets Packets Good Bad This field indicates the number of good and
* bad packets received with length between 128 and 255 (inclusive) bytes, exclusive of the
* preamble.
*/
#define ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_SHIFT)) & ENET_QOS_MAC_RX_128TO255OCTETS_PACKETS_GOOD_BAD_RX128_255OCTGB_MASK)
/*! @} */
/*! @name MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD - Good and Bad 256-to-511 Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT (0U)
/*! RX256_511OCTGB - Rx 256-511 Octets Packets Good Bad This field indicates the number of good and
* bad packets received with length between 256 and 511 (inclusive) bytes, exclusive of the
* preamble.
*/
#define ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_SHIFT)) & ENET_QOS_MAC_RX_256TO511OCTETS_PACKETS_GOOD_BAD_RX256_511OCTGB_MASK)
/*! @} */
/*! @name MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD - Good and Bad 512-to-1023 Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT (0U)
/*! RX512_1023OCTGB - RX 512-1023 Octets Packets Good Bad This field indicates the number of good
* and bad packets received with length between 512 and 1023 (inclusive) bytes, exclusive of the
* preamble.
*/
#define ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_SHIFT)) & ENET_QOS_MAC_RX_512TO1023OCTETS_PACKETS_GOOD_BAD_RX512_1023OCTGB_MASK)
/*! @} */
/*! @name MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD - Good and Bad 1024-to-Max Byte Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT (0U)
/*! RX1024_MAXOCTGB - Rx 1024-Max Octets Good Bad This field indicates the number of good and bad
* packets received with length between 1024 and maxsize (inclusive) bytes, exclusive of the
* preamble.
*/
#define ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_SHIFT)) & ENET_QOS_MAC_RX_1024TOMAXOCTETS_PACKETS_GOOD_BAD_RX1024_MAXOCTGB_MASK)
/*! @} */
/*! @name MAC_RX_UNICAST_PACKETS_GOOD - Good Unicast Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT (0U)
/*! RXUCASTG - Rx Unicast Packets Good This field indicates the number of good unicast packets received.
*/
#define ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_SHIFT)) & ENET_QOS_MAC_RX_UNICAST_PACKETS_GOOD_RXUCASTG_MASK)
/*! @} */
/*! @name MAC_RX_LENGTH_ERROR_PACKETS - Length Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT (0U)
/*! RXLENERR - Rx Length Error Packets This field indicates the number of packets received with
* length error (Length Type field not equal to packet size), for all packets with valid length field.
*/
#define ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_SHIFT)) & ENET_QOS_MAC_RX_LENGTH_ERROR_PACKETS_RXLENERR_MASK)
/*! @} */
/*! @name MAC_RX_OUT_OF_RANGE_TYPE_PACKETS - Out-of-range Type Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT (0U)
/*! RXOUTOFRNG - Rx Out of Range Type Packet This field indicates the number of packets received
* with length field not equal to the valid packet size (greater than 1,500 but less than 1,536).
*/
#define ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_SHIFT)) & ENET_QOS_MAC_RX_OUT_OF_RANGE_TYPE_PACKETS_RXOUTOFRNG_MASK)
/*! @} */
/*! @name MAC_RX_PAUSE_PACKETS - Pause Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT (0U)
/*! RXPAUSEPKT - Rx Pause Packets This field indicates the number of good and valid Pause packets received.
*/
#define ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_SHIFT)) & ENET_QOS_MAC_RX_PAUSE_PACKETS_RXPAUSEPKT_MASK)
/*! @} */
/*! @name MAC_RX_FIFO_OVERFLOW_PACKETS - Missed Packets Due to FIFO Overflow */
/*! @{ */
#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT (0U)
/*! RXFIFOOVFL - Rx FIFO Overflow Packets This field indicates the number of missed received packets because of FIFO overflow.
*/
#define ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_SHIFT)) & ENET_QOS_MAC_RX_FIFO_OVERFLOW_PACKETS_RXFIFOOVFL_MASK)
/*! @} */
/*! @name MAC_RX_VLAN_PACKETS_GOOD_BAD - Good and Bad VLAN Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT (0U)
/*! RXVLANPKTGB - Rx VLAN Packets Good Bad This field indicates the number of good and bad VLAN packets received.
*/
#define ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_SHIFT)) & ENET_QOS_MAC_RX_VLAN_PACKETS_GOOD_BAD_RXVLANPKTGB_MASK)
/*! @} */
/*! @name MAC_RX_WATCHDOG_ERROR_PACKETS - Watchdog Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT (0U)
/*! RXWDGERR - Rx Watchdog Error Packets This field indicates the number of packets received with
* error because of watchdog timeout error (packets with a data load larger than 2,048 bytes (when
* JE and WD bits are reset in MAC_CONFIGURATION register), 10,240 bytes (when JE bit is set and
* WD bit is reset in MAC_CONFIGURATION register), 16,384 bytes (when WD bit is set in
* MAC_CONFIGURATION register) or the value programmed in the MAC_WATCHDOG_TIMEOUT register).
*/
#define ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_SHIFT)) & ENET_QOS_MAC_RX_WATCHDOG_ERROR_PACKETS_RXWDGERR_MASK)
/*! @} */
/*! @name MAC_RX_RECEIVE_ERROR_PACKETS - Receive Error Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT (0U)
/*! RXRCVERR - Rx Receive Error Packets This field indicates the number of packets received with
* Receive error or Packet Extension error on the GMII or MII interface.
*/
#define ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_SHIFT)) & ENET_QOS_MAC_RX_RECEIVE_ERROR_PACKETS_RXRCVERR_MASK)
/*! @} */
/*! @name MAC_RX_CONTROL_PACKETS_GOOD - Good Control Packets Received */
/*! @{ */
#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT (0U)
/*! RXCTRLG - Rx Control Packets Good This field indicates the number of good control packets received.
*/
#define ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_SHIFT)) & ENET_QOS_MAC_RX_CONTROL_PACKETS_GOOD_RXCTRLG_MASK)
/*! @} */
/*! @name MAC_TX_LPI_USEC_CNTR - Microseconds Tx LPI Asserted */
/*! @{ */
#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT (0U)
/*! TXLPIUSC - Tx LPI Microseconds Counter This field indicates the number of microseconds Tx LPI is asserted.
*/
#define ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_SHIFT)) & ENET_QOS_MAC_TX_LPI_USEC_CNTR_TXLPIUSC_MASK)
/*! @} */
/*! @name MAC_TX_LPI_TRAN_CNTR - Number of Times Tx LPI Asserted */
/*! @{ */
#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT (0U)
/*! TXLPITRC - Tx LPI Transition counter This field indicates the number of times Tx LPI Entry has occurred.
*/
#define ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_SHIFT)) & ENET_QOS_MAC_TX_LPI_TRAN_CNTR_TXLPITRC_MASK)
/*! @} */
/*! @name MAC_RX_LPI_USEC_CNTR - Microseconds Rx LPI Sampled */
/*! @{ */
#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT (0U)
/*! RXLPIUSC - Rx LPI Microseconds Counter This field indicates the number of microseconds Rx LPI is asserted.
*/
#define ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_SHIFT)) & ENET_QOS_MAC_RX_LPI_USEC_CNTR_RXLPIUSC_MASK)
/*! @} */
/*! @name MAC_RX_LPI_TRAN_CNTR - Number of Times Rx LPI Entered */
/*! @{ */
#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT (0U)
/*! RXLPITRC - Rx LPI Transition counter This field indicates the number of times Rx LPI Entry has occurred.
*/
#define ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_SHIFT)) & ENET_QOS_MAC_RX_LPI_TRAN_CNTR_RXLPITRC_MASK)
/*! @} */
/*! @name MAC_MMC_IPC_RX_INTERRUPT_MASK - MMC IPC Receive Interrupt Mask */
/*! @{ */
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK (0x1U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT (0U)
/*! RXIPV4GPIM - MMC Receive IPV4 Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive IPV4 Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK (0x2U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT (1U)
/*! RXIPV4HERPIM - MMC Receive IPV4 Header Error Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HERPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK (0x4U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT (2U)
/*! RXIPV4NOPAYPIM - MMC Receive IPV4 No Payload Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxipv4_nopay_pkts counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK (0x8U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT (3U)
/*! RXIPV4FRAGPIM - MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxipv4_frag_pkts counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK (0x10U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT (4U)
/*! RXIPV4UDSBLPIM - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask Setting
* this bit masks the interrupt when the rxipv4_udsbl_pkts counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK (0x20U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT (5U)
/*! RXIPV6GPIM - MMC Receive IPV6 Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive IPV6 Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK (0x40U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT (6U)
/*! RXIPV6HERPIM - MMC Receive IPV6 Header Error Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HERPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK (0x80U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT (7U)
/*! RXIPV6NOPAYPIM - MMC Receive IPV6 No Payload Packet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxipv6_nopay_pkts counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK (0x100U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT (8U)
/*! RXUDPGPIM - MMC Receive UDP Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive UDP Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive UDP Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK (0x200U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT (9U)
/*! RXUDPERPIM - MMC Receive UDP Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive UDP Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive UDP Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPERPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK (0x400U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT (10U)
/*! RXTCPGPIM - MMC Receive TCP Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive TCP Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive TCP Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK (0x800U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT (11U)
/*! RXTCPERPIM - MMC Receive TCP Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive TCP Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive TCP Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPERPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT (12U)
/*! RXICMPGPIM - MMC Receive ICMP Good Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive ICMP Good Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive ICMP Good Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT (13U)
/*! RXICMPERPIM - MMC Receive ICMP Error Packet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxicmp_err_pkts counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive ICMP Error Packet Counter Interrupt Mask is disabled
* 0b1..MMC Receive ICMP Error Packet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPERPIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT (16U)
/*! RXIPV4GOIM - MMC Receive IPV4 Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive IPV4 Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4GOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT (17U)
/*! RXIPV4HEROIM - MMC Receive IPV4 Header Error Octet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxipv4_hdrerr_octets counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4HEROIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT (18U)
/*! RXIPV4NOPAYOIM - MMC Receive IPV4 No Payload Octet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxipv4_nopay_octets counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4NOPAYOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT (19U)
/*! RXIPV4FRAGOIM - MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask Setting this bit masks
* the interrupt when the rxipv4_frag_octets counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4FRAGOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT (20U)
/*! RXIPV4UDSBLOIM - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask Setting
* this bit masks the interrupt when the rxipv4_udsbl_octets counter reaches half of the maximum
* value or the maximum value.
* 0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV4UDSBLOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT (21U)
/*! RXIPV6GOIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6GOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT (22U)
/*! RXIPV6HEROIM - MMC Receive IPV6 Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6HEROIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT (23U)
/*! RXIPV6NOPAYOIM - MMC Receive IPV6 Header Error Octet Counter Interrupt Mask Setting this bit
* masks the interrupt when the rxipv6_nopay_octets counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXIPV6NOPAYOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT (24U)
/*! RXUDPGOIM - MMC Receive IPV6 No Payload Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxudp_gd_octets counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPGOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT (25U)
/*! RXUDPEROIM - MMC Receive UDP Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxudp_err_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive UDP Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive UDP Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXUDPEROIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT (26U)
/*! RXTCPGOIM - MMC Receive TCP Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive TCP Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive TCP Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPGOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT (27U)
/*! RXTCPEROIM - MMC Receive TCP Error Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive TCP Error Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive TCP Error Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXTCPEROIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK (0x10000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT (28U)
/*! RXICMPGOIM - MMC Receive ICMP Good Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Receive ICMP Good Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive ICMP Good Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPGOIM_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK (0x20000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT (29U)
/*! RXICMPEROIM - MMC Receive ICMP Error Octet Counter Interrupt Mask Setting this bit masks the
* interrupt when the rxicmp_err_octets counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Receive ICMP Error Octet Counter Interrupt Mask is disabled
* 0b1..MMC Receive ICMP Error Octet Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_MASK_RXICMPEROIM_MASK)
/*! @} */
/*! @name MAC_MMC_IPC_RX_INTERRUPT - MMC IPC Receive Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK (0x1U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT (0U)
/*! RXIPV4GPIS - MMC Receive IPV4 Good Packet Counter Interrupt Status This bit is set when the
* rxipv4_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK (0x2U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT (1U)
/*! RXIPV4HERPIS - MMC Receive IPV4 Header Error Packet Counter Interrupt Status This bit is set
* when the rxipv4_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Header Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Header Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HERPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK (0x4U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT (2U)
/*! RXIPV4NOPAYPIS - MMC Receive IPV4 No Payload Packet Counter Interrupt Status This bit is set
* when the rxipv4_nopay_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 No Payload Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 No Payload Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK (0x8U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT (3U)
/*! RXIPV4FRAGPIS - MMC Receive IPV4 Fragmented Packet Counter Interrupt Status This bit is set when
* the rxipv4_frag_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Fragmented Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK (0x10U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT (4U)
/*! RXIPV4UDSBLPIS - MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status This bit
* is set when the rxipv4_udsbl_pkts counter reaches half of the maximum value or the maximum
* value.
* 0b1..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 UDP Checksum Disabled Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK (0x20U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT (5U)
/*! RXIPV6GPIS - MMC Receive IPV6 Good Packet Counter Interrupt Status This bit is set when the
* rxipv6_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK (0x40U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT (6U)
/*! RXIPV6HERPIS - MMC Receive IPV6 Header Error Packet Counter Interrupt Status This bit is set
* when the rxipv6_hdrerr_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 Header Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 Header Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HERPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK (0x80U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT (7U)
/*! RXIPV6NOPAYPIS - MMC Receive IPV6 No Payload Packet Counter Interrupt Status This bit is set
* when the rxipv6_nopay_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 No Payload Packet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 No Payload Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK (0x100U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT (8U)
/*! RXUDPGPIS - MC Receive UDP Good Packet Counter Interrupt Status This bit is set when the
* rxudp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive UDP Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive UDP Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK (0x200U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT (9U)
/*! RXUDPERPIS - MMC Receive UDP Error Packet Counter Interrupt Status This bit is set when the
* rxudp_err_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive UDP Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive UDP Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPERPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK (0x400U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT (10U)
/*! RXTCPGPIS - MMC Receive TCP Good Packet Counter Interrupt Status This bit is set when the
* rxtcp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive TCP Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive TCP Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK (0x800U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT (11U)
/*! RXTCPERPIS - MMC Receive TCP Error Packet Counter Interrupt Status This bit is set when the
* rxtcp_err_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive TCP Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive TCP Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPERPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK (0x1000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT (12U)
/*! RXICMPGPIS - MMC Receive ICMP Good Packet Counter Interrupt Status This bit is set when the
* rxicmp_gd_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive ICMP Good Packet Counter Interrupt Status detected
* 0b0..MMC Receive ICMP Good Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK (0x2000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT (13U)
/*! RXICMPERPIS - MMC Receive ICMP Error Packet Counter Interrupt Status This bit is set when the
* rxicmp_err_pkts counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive ICMP Error Packet Counter Interrupt Status detected
* 0b0..MMC Receive ICMP Error Packet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPERPIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK (0x10000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT (16U)
/*! RXIPV4GOIS - MMC Receive IPV4 Good Octet Counter Interrupt Status This bit is set when the
* rxipv4_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4GOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK (0x20000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT (17U)
/*! RXIPV4HEROIS - MMC Receive IPV4 Header Error Octet Counter Interrupt Status This bit is set when
* the rxipv4_hdrerr_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Header Error Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Header Error Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4HEROIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK (0x40000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT (18U)
/*! RXIPV4NOPAYOIS - MMC Receive IPV4 No Payload Octet Counter Interrupt Status This bit is set when
* the rxipv4_nopay_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 No Payload Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 No Payload Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4NOPAYOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK (0x80000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT (19U)
/*! RXIPV4FRAGOIS - MMC Receive IPV4 Fragmented Octet Counter Interrupt Status This bit is set when
* the rxipv4_frag_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 Fragmented Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4FRAGOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK (0x100000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT (20U)
/*! RXIPV4UDSBLOIS - MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status This bit
* is set when the rxipv4_udsbl_octets counter reaches half of the maximum value or the maximum
* value.
* 0b1..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV4 UDP Checksum Disabled Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV4UDSBLOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK (0x200000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT (21U)
/*! RXIPV6GOIS - MMC Receive IPV6 Good Octet Counter Interrupt Status This bit is set when the
* rxipv6_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6GOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK (0x400000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT (22U)
/*! RXIPV6HEROIS - MMC Receive IPV6 Header Error Octet Counter Interrupt Status This bit is set when
* the rxipv6_hdrerr_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 Header Error Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 Header Error Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6HEROIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK (0x800000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT (23U)
/*! RXIPV6NOPAYOIS - MMC Receive IPV6 No Payload Octet Counter Interrupt Status This bit is set when
* the rxipv6_nopay_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive IPV6 No Payload Octet Counter Interrupt Status detected
* 0b0..MMC Receive IPV6 No Payload Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXIPV6NOPAYOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK (0x1000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT (24U)
/*! RXUDPGOIS - MMC Receive UDP Good Octet Counter Interrupt Status This bit is set when the
* rxudp_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive UDP Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive UDP Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPGOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK (0x2000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT (25U)
/*! RXUDPEROIS - MMC Receive UDP Error Octet Counter Interrupt Status This bit is set when the
* rxudp_err_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive UDP Error Octet Counter Interrupt Status detected
* 0b0..MMC Receive UDP Error Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXUDPEROIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK (0x4000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT (26U)
/*! RXTCPGOIS - MMC Receive TCP Good Octet Counter Interrupt Status This bit is set when the
* rxtcp_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive TCP Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive TCP Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPGOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK (0x8000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT (27U)
/*! RXTCPEROIS - MMC Receive TCP Error Octet Counter Interrupt Status This bit is set when the
* rxtcp_err_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive TCP Error Octet Counter Interrupt Status detected
* 0b0..MMC Receive TCP Error Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXTCPEROIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK (0x10000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT (28U)
/*! RXICMPGOIS - MMC Receive ICMP Good Octet Counter Interrupt Status This bit is set when the
* rxicmp_gd_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive ICMP Good Octet Counter Interrupt Status detected
* 0b0..MMC Receive ICMP Good Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPGOIS_MASK)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK (0x20000000U)
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT (29U)
/*! RXICMPEROIS - MMC Receive ICMP Error Octet Counter Interrupt Status This bit is set when the
* rxicmp_err_octets counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Receive ICMP Error Octet Counter Interrupt Status detected
* 0b0..MMC Receive ICMP Error Octet Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_SHIFT)) & ENET_QOS_MAC_MMC_IPC_RX_INTERRUPT_RXICMPEROIS_MASK)
/*! @} */
/*! @name MAC_RXIPV4_GOOD_PACKETS - Good IPv4 Datagrams Received */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT (0U)
/*! RXIPV4GDPKT - RxIPv4 Good Packets This field indicates the number of good IPv4 datagrams received with the TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_PACKETS_RXIPV4GDPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_HEADER_ERROR_PACKETS - IPv4 Datagrams Received with Header Errors */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT (0U)
/*! RXIPV4HDRERRPKT - RxIPv4 Header Error Packets This field indicates the number of IPv4 datagrams
* received with header (checksum, length, or version mismatch) errors.
*/
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_PACKETS_RXIPV4HDRERRPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_NO_PAYLOAD_PACKETS - IPv4 Datagrams Received with No Payload */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT (0U)
/*! RXIPV4NOPAYPKT - RxIPv4 Payload Packets This field indicates the number of IPv4 datagram packets
* received that did not have a TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_PACKETS_RXIPV4NOPAYPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_FRAGMENTED_PACKETS - IPv4 Datagrams Received with Fragmentation */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT (0U)
/*! RXIPV4FRAGPKT - RxIPv4 Fragmented Packets This field indicates the number of good IPv4 datagrams received with fragmentation.
*/
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_PACKETS_RXIPV4FRAGPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS - IPv4 Datagrams Received with UDP Checksum Disabled */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT (0U)
/*! RXIPV4UDSBLPKT - RxIPv4 UDP Checksum Disabled Packets This field indicates the number of good
* IPv4 datagrams received that had a UDP payload with checksum disabled.
*/
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLED_PACKETS_RXIPV4UDSBLPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_GOOD_PACKETS - Good IPv6 Datagrams Received */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT (0U)
/*! RXIPV6GDPKT - RxIPv6 Good Packets This field indicates the number of good IPv6 datagrams received with the TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_PACKETS_RXIPV6GDPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_HEADER_ERROR_PACKETS - IPv6 Datagrams Received with Header Errors */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT (0U)
/*! RXIPV6HDRERRPKT - RxIPv6 Header Error Packets This field indicates the number of IPv6 datagrams
* received with header (length or version mismatch) errors.
*/
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_PACKETS_RXIPV6HDRERRPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_NO_PAYLOAD_PACKETS - IPv6 Datagrams Received with No Payload */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT (0U)
/*! RXIPV6NOPAYPKT - RxIPv6 Payload Packets This field indicates the number of IPv6 datagram packets
* received that did not have a TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_PACKETS_RXIPV6NOPAYPKT_MASK)
/*! @} */
/*! @name MAC_RXUDP_GOOD_PACKETS - IPv6 Datagrams Received with Good UDP */
/*! @{ */
#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT (0U)
/*! RXUDPGDPKT - RxUDP Good Packets This field indicates the number of good IP datagrams received with a good UDP payload.
*/
#define ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_PACKETS_RXUDPGDPKT_MASK)
/*! @} */
/*! @name MAC_RXUDP_ERROR_PACKETS - IPv6 Datagrams Received with UDP Checksum Error */
/*! @{ */
#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT (0U)
/*! RXUDPERRPKT - RxUDP Error Packets This field indicates the number of good IP datagrams received
* whose UDP payload has a checksum error.
*/
#define ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_PACKETS_RXUDPERRPKT_MASK)
/*! @} */
/*! @name MAC_RXTCP_GOOD_PACKETS - IPv6 Datagrams Received with Good TCP Payload */
/*! @{ */
#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT (0U)
/*! RXTCPGDPKT - RxTCP Good Packets This field indicates the number of good IP datagrams received with a good TCP payload.
*/
#define ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_PACKETS_RXTCPGDPKT_MASK)
/*! @} */
/*! @name MAC_RXTCP_ERROR_PACKETS - IPv6 Datagrams Received with TCP Checksum Error */
/*! @{ */
#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT (0U)
/*! RXTCPERRPKT - RxTCP Error Packets This field indicates the number of good IP datagrams received
* whose TCP payload has a checksum error.
*/
#define ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_PACKETS_RXTCPERRPKT_MASK)
/*! @} */
/*! @name MAC_RXICMP_GOOD_PACKETS - IPv6 Datagrams Received with Good ICMP Payload */
/*! @{ */
#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT (0U)
/*! RXICMPGDPKT - RxICMP Good Packets This field indicates the number of good IP datagrams received with a good ICMP payload.
*/
#define ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_PACKETS_RXICMPGDPKT_MASK)
/*! @} */
/*! @name MAC_RXICMP_ERROR_PACKETS - IPv6 Datagrams Received with ICMP Checksum Error */
/*! @{ */
#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT (0U)
/*! RXICMPERRPKT - RxICMP Error Packets This field indicates the number of good IP datagrams
* received whose ICMP payload has a checksum error.
*/
#define ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_PACKETS_RXICMPERRPKT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_GOOD_OCTETS - Good Bytes Received in IPv4 Datagrams */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT (0U)
/*! RXIPV4GDOCT - RxIPv4 Good Octets This field indicates the number of bytes received in good IPv4
* datagrams encapsulating TCP, UDP, or ICMP data.
*/
#define ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_GOOD_OCTETS_RXIPV4GDOCT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_HEADER_ERROR_OCTETS - Bytes Received in IPv4 Datagrams with Header Errors */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT (0U)
/*! RXIPV4HDRERROCT - RxIPv4 Header Error Octets This field indicates the number of bytes received
* in IPv4 datagrams with header errors (checksum, length, version mismatch).
*/
#define ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_HEADER_ERROR_OCTETS_RXIPV4HDRERROCT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_NO_PAYLOAD_OCTETS - Bytes Received in IPv4 Datagrams with No Payload */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT (0U)
/*! RXIPV4NOPAYOCT - RxIPv4 Payload Octets This field indicates the number of bytes received in IPv4
* datagrams that did not have a TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_NO_PAYLOAD_OCTETS_RXIPV4NOPAYOCT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_FRAGMENTED_OCTETS - Bytes Received in Fragmented IPv4 Datagrams */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT (0U)
/*! RXIPV4FRAGOCT - RxIPv4 Fragmented Octets This field indicates the number of bytes received in fragmented IPv4 datagrams.
*/
#define ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_FRAGMENTED_OCTETS_RXIPV4FRAGOCT_MASK)
/*! @} */
/*! @name MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS - Bytes Received with UDP Checksum Disabled */
/*! @{ */
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT (0U)
/*! RXIPV4UDSBLOCT - RxIPv4 UDP Checksum Disable Octets This field indicates the number of bytes
* received in a UDP segment that had the UDP checksum disabled.
*/
#define ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_SHIFT)) & ENET_QOS_MAC_RXIPV4_UDP_CHECKSUM_DISABLE_OCTETS_RXIPV4UDSBLOCT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_GOOD_OCTETS - Bytes Received in Good IPv6 Datagrams */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT (0U)
/*! RXIPV6GDOCT - RxIPv6 Good Octets This field indicates the number of bytes received in good IPv6
* datagrams encapsulating TCP, UDP, or ICMP data.
*/
#define ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_GOOD_OCTETS_RXIPV6GDOCT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_HEADER_ERROR_OCTETS - Bytes Received in IPv6 Datagrams with Data Errors */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT (0U)
/*! RXIPV6HDRERROCT - RxIPv6 Header Error Octets This field indicates the number of bytes received
* in IPv6 datagrams with header errors (length, version mismatch).
*/
#define ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_HEADER_ERROR_OCTETS_RXIPV6HDRERROCT_MASK)
/*! @} */
/*! @name MAC_RXIPV6_NO_PAYLOAD_OCTETS - Bytes Received in IPv6 Datagrams with No Payload */
/*! @{ */
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT (0U)
/*! RXIPV6NOPAYOCT - RxIPv6 Payload Octets This field indicates the number of bytes received in IPv6
* datagrams that did not have a TCP, UDP, or ICMP payload.
*/
#define ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_SHIFT)) & ENET_QOS_MAC_RXIPV6_NO_PAYLOAD_OCTETS_RXIPV6NOPAYOCT_MASK)
/*! @} */
/*! @name MAC_RXUDP_GOOD_OCTETS - Bytes Received in Good UDP Segment */
/*! @{ */
#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT (0U)
/*! RXUDPGDOCT - RxUDP Good Octets This field indicates the number of bytes received in a good UDP segment.
*/
#define ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_SHIFT)) & ENET_QOS_MAC_RXUDP_GOOD_OCTETS_RXUDPGDOCT_MASK)
/*! @} */
/*! @name MAC_RXUDP_ERROR_OCTETS - Bytes Received in UDP Segment with Checksum Errors */
/*! @{ */
#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT (0U)
/*! RXUDPERROCT - RxUDP Error Octets This field indicates the number of bytes received in a UDP segment that had checksum errors.
*/
#define ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_SHIFT)) & ENET_QOS_MAC_RXUDP_ERROR_OCTETS_RXUDPERROCT_MASK)
/*! @} */
/*! @name MAC_RXTCP_GOOD_OCTETS - Bytes Received in Good TCP Segment */
/*! @{ */
#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT (0U)
/*! RXTCPGDOCT - RxTCP Good Octets This field indicates the number of bytes received in a good TCP segment.
*/
#define ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_SHIFT)) & ENET_QOS_MAC_RXTCP_GOOD_OCTETS_RXTCPGDOCT_MASK)
/*! @} */
/*! @name MAC_RXTCP_ERROR_OCTETS - Bytes Received in TCP Segment with Checksum Errors */
/*! @{ */
#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT (0U)
/*! RXTCPERROCT - RxTCP Error Octets This field indicates the number of bytes received in a TCP segment that had checksum errors.
*/
#define ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_SHIFT)) & ENET_QOS_MAC_RXTCP_ERROR_OCTETS_RXTCPERROCT_MASK)
/*! @} */
/*! @name MAC_RXICMP_GOOD_OCTETS - Bytes Received in Good ICMP Segment */
/*! @{ */
#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT (0U)
/*! RXICMPGDOCT - RxICMP Good Octets This field indicates the number of bytes received in a good ICMP segment.
*/
#define ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_SHIFT)) & ENET_QOS_MAC_RXICMP_GOOD_OCTETS_RXICMPGDOCT_MASK)
/*! @} */
/*! @name MAC_RXICMP_ERROR_OCTETS - Bytes Received in ICMP Segment with Checksum Errors */
/*! @{ */
#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT (0U)
/*! RXICMPERROCT - RxICMP Error Octets This field indicates the number of bytes received in a ICMP segment that had checksum errors.
*/
#define ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_SHIFT)) & ENET_QOS_MAC_RXICMP_ERROR_OCTETS_RXICMPERROCT_MASK)
/*! @} */
/*! @name MAC_MMC_FPE_TX_INTERRUPT - MMC FPE Transmit Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK (0x1U)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT (0U)
/*! FCIS - MMC Tx FPE Fragment Counter Interrupt status This bit is set when the
* Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Tx FPE Fragment Counter Interrupt status detected
* 0b0..MMC Tx FPE Fragment Counter Interrupt status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_FCIS_MASK)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK (0x2U)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT (1U)
/*! HRCIS - MMC Tx Hold Request Counter Interrupt Status This bit is set when the Tx_Hold_Req_Cntr
* counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Tx Hold Request Counter Interrupt Status detected
* 0b0..MMC Tx Hold Request Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_HRCIS_MASK)
/*! @} */
/*! @name MAC_MMC_FPE_TX_INTERRUPT_MASK - MMC FPE Transmit Mask Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK (0x1U)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT (0U)
/*! FCIM - MMC Transmit Fragment Counter Interrupt Mask Setting this bit masks the interrupt when
* the Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Fragment Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Fragment Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_FCIM_MASK)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK (0x2U)
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT (1U)
/*! HRCIM - MMC Transmit Hold Request Counter Interrupt Mask Setting this bit masks the interrupt
* when the Tx_Hold_Req_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Transmit Hold Request Counter Interrupt Mask is disabled
* 0b1..MMC Transmit Hold Request Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_TX_INTERRUPT_MASK_HRCIM_MASK)
/*! @} */
/*! @name MAC_MMC_TX_FPE_FRAGMENT_CNTR - MMC FPE Transmitted Fragment Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT (0U)
/*! TXFFC - Tx FPE Fragment counter This field indicates the number of additional mPackets that has
* been transmitted due to preemption Exists when any one of the RX/TX MMC counters are enabled
* during FPE Enabled configuration.
*/
#define ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_SHIFT)) & ENET_QOS_MAC_MMC_TX_FPE_FRAGMENT_CNTR_TXFFC_MASK)
/*! @} */
/*! @name MAC_MMC_TX_HOLD_REQ_CNTR - MMC FPE Transmitted Hold Request Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT (0U)
/*! TXHRC - Tx Hold Request Counter This field indicates count of number of a hold request is given to MAC.
*/
#define ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_SHIFT)) & ENET_QOS_MAC_MMC_TX_HOLD_REQ_CNTR_TXHRC_MASK)
/*! @} */
/*! @name MAC_MMC_FPE_RX_INTERRUPT - MMC FPE Receive Interrupt */
/*! @{ */
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK (0x1U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT (0U)
/*! PAECIS - MMC Rx Packet Assembly Error Counter Interrupt Status This bit is set when the
* Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Rx Packet Assembly Error Counter Interrupt Status detected
* 0b0..MMC Rx Packet Assembly Error Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAECIS_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK (0x2U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT (1U)
/*! PSECIS - MMC Rx Packet SMD Error Counter Interrupt Status This bit is set when the
* Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Rx Packet SMD Error Counter Interrupt Status detected
* 0b0..MMC Rx Packet SMD Error Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PSECIS_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK (0x4U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT (2U)
/*! PAOCIS - MMC Rx Packet Assembly OK Counter Interrupt Status This bit is set when the
* Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Rx Packet Assembly OK Counter Interrupt Status detected
* 0b0..MMC Rx Packet Assembly OK Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_PAOCIS_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK (0x8U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT (3U)
/*! FCIS - MMC Rx FPE Fragment Counter Interrupt Status This bit is set when the
* Rx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
* 0b1..MMC Rx FPE Fragment Counter Interrupt Status detected
* 0b0..MMC Rx FPE Fragment Counter Interrupt Status not detected
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_FCIS_MASK)
/*! @} */
/*! @name MAC_MMC_FPE_RX_INTERRUPT_MASK - MMC FPE Receive Interrupt Mask */
/*! @{ */
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK (0x1U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT (0U)
/*! PAECIM - MMC Rx Packet Assembly Error Counter Interrupt Mask Setting this bit masks the
* interrupt when the R Rx_Packet_Assemble_Err_Cntr counter reaches half of the maximum value or the
* maximum value.
* 0b0..MMC Rx Packet Assembly Error Counter Interrupt Mask is disabled
* 0b1..MMC Rx Packet Assembly Error Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAECIM_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK (0x2U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT (1U)
/*! PSECIM - MMC Rx Packet SMD Error Counter Interrupt Mask Setting this bit masks the interrupt
* when the R Rx_Packet_SMD_Err_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Rx Packet SMD Error Counter Interrupt Mask is disabled
* 0b1..MMC Rx Packet SMD Error Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PSECIM_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK (0x4U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT (2U)
/*! PAOCIM - MMC Rx Packet Assembly OK Counter Interrupt Mask Setting this bit masks the interrupt
* when the Rx_Packet_Assemble_Ok_Cntr counter reaches half of the maximum value or the maximum
* value.
* 0b0..MMC Rx Packet Assembly OK Counter Interrupt Mask is disabled
* 0b1..MMC Rx Packet Assembly OK Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_PAOCIM_MASK)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK (0x8U)
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT (3U)
/*! FCIM - MMC Rx FPE Fragment Counter Interrupt Mask Setting this bit masks the interrupt when the
* Tx_FPE_Fragment_Cntr counter reaches half of the maximum value or the maximum value.
* 0b0..MMC Rx FPE Fragment Counter Interrupt Mask is disabled
* 0b1..MMC Rx FPE Fragment Counter Interrupt Mask is enabled
*/
#define ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_SHIFT)) & ENET_QOS_MAC_MMC_FPE_RX_INTERRUPT_MASK_FCIM_MASK)
/*! @} */
/*! @name MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR - MMC Receive Packet Reassembly Error Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT (0U)
/*! PAEC - Rx Packet Assembly Error Counter This field indicates the number of MAC frames with
* reassembly errors on the Receiver, due to mismatch in the Fragment Count value.
*/
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_ERR_CNTR_PAEC_MASK)
/*! @} */
/*! @name MAC_MMC_RX_PACKET_SMD_ERR_CNTR - MMC Receive Packet SMD Error Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT (0U)
/*! PSEC - Rx Packet SMD Error Counter This field indicates the number of MAC frames rejected due to
* unknown SMD value and MAC frame fragments rejected due to arriving with an SMD-C when there
* was no preceding preempted frame.
*/
#define ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_SMD_ERR_CNTR_PSEC_MASK)
/*! @} */
/*! @name MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR - MMC Receive Packet Successful Reassembly Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT (0U)
/*! PAOC - Rx Packet Assembly OK Counter This field indicates the number of MAC frames that were
* successfully reassembled and delivered to MAC.
*/
#define ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_SHIFT)) & ENET_QOS_MAC_MMC_RX_PACKET_ASSEMBLY_OK_CNTR_PAOC_MASK)
/*! @} */
/*! @name MAC_MMC_RX_FPE_FRAGMENT_CNTR - MMC FPE Received Fragment Counter */
/*! @{ */
#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT (0U)
/*! FFC - Rx FPE Fragment Counter This field indicates the number of additional mPackets received
* due to preemption Exists when at least one of the RX/TX MMC counters are enabled during FPE
* Enabled configuration.
*/
#define ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_SHIFT)) & ENET_QOS_MAC_MMC_RX_FPE_FRAGMENT_CNTR_FFC_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL0 - Layer 3 and Layer 4 Control of Filter 0 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT (0U)
/*! L3PEN0 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3PEN0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT (2U)
/*! L3SAM0 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT (3U)
/*! L3SAIM0 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3SAIM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT (4U)
/*! L3DAM0 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT (5U)
/*! L3DAIM0 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3DAIM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT (6U)
/*! L3HSBM0 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HSBM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT (11U)
/*! L3HDBM0 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L3HDBM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT (16U)
/*! L4PEN0 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4PEN0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT (18U)
/*! L4SPM0 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT (19U)
/*! L4SPIM0 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4SPIM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT (20U)
/*! L4DPM0 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT (21U)
/*! L4DPIM0 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_L4DPIM0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT (24U)
/*! DMCHN0 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHN0_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT (28U)
/*! DMCHEN0 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL0_DMCHEN0_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS0 - Layer 4 Address 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT (0U)
/*! L4SP0 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4SP0_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT (16U)
/*! L4DP0 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS0_L4DP0_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG0 - Layer 3 Address 0 Register 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT (0U)
/*! L3A00 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG0_L3A00_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG0 - Layer 3 Address 1 Register 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT (0U)
/*! L3A10 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG0_L3A10_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG0 - Layer 3 Address 2 Register 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT (0U)
/*! L3A20 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG0_L3A20_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG0 - Layer 3 Address 3 Register 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT (0U)
/*! L3A30 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG0_L3A30_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL1 - Layer 3 and Layer 4 Control of Filter 1 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT (0U)
/*! L3PEN1 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3PEN1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT (2U)
/*! L3SAM1 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT (3U)
/*! L3SAIM1 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3SAIM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT (4U)
/*! L3DAM1 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT (5U)
/*! L3DAIM1 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3DAIM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT (6U)
/*! L3HSBM1 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HSBM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT (11U)
/*! L3HDBM1 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L3HDBM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT (16U)
/*! L4PEN1 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4PEN1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT (18U)
/*! L4SPM1 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT (19U)
/*! L4SPIM1 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4SPIM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT (20U)
/*! L4DPM1 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT (21U)
/*! L4DPIM1 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_L4DPIM1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT (24U)
/*! DMCHN1 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHN1_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT (28U)
/*! DMCHEN1 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL1_DMCHEN1_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS1 - Layer 4 Address 0 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT (0U)
/*! L4SP1 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4SP1_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT (16U)
/*! L4DP1 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS1_L4DP1_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG1 - Layer 3 Address 0 Register 1 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT (0U)
/*! L3A01 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG1_L3A01_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG1 - Layer 3 Address 1 Register 1 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT (0U)
/*! L3A11 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG1_L3A11_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG1 - Layer 3 Address 2 Register 1 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT (0U)
/*! L3A21 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG1_L3A21_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG1 - Layer 3 Address 3 Register 1 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT (0U)
/*! L3A31 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG1_L3A31_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL2 - Layer 3 and Layer 4 Control of Filter 2 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT (0U)
/*! L3PEN2 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3PEN2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT (2U)
/*! L3SAM2 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT (3U)
/*! L3SAIM2 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3SAIM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT (4U)
/*! L3DAM2 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT (5U)
/*! L3DAIM2 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3DAIM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT (6U)
/*! L3HSBM2 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HSBM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT (11U)
/*! L3HDBM2 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L3HDBM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT (16U)
/*! L4PEN2 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4PEN2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT (18U)
/*! L4SPM2 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT (19U)
/*! L4SPIM2 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4SPIM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT (20U)
/*! L4DPM2 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT (21U)
/*! L4DPIM2 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_L4DPIM2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT (24U)
/*! DMCHN2 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHN2_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT (28U)
/*! DMCHEN2 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL2_DMCHEN2_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS2 - Layer 4 Address 2 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT (0U)
/*! L4SP2 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4SP2_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT (16U)
/*! L4DP2 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS2_L4DP2_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG2 - Layer 3 Address 0 Register 2 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT (0U)
/*! L3A02 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG2_L3A02_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG2 - Layer 3 Address 0 Register 2 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT (0U)
/*! L3A12 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG2_L3A12_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG2 - Layer 3 Address 2 Register 2 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT (0U)
/*! L3A22 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG2_L3A22_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG2 - Layer 3 Address 3 Register 2 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT (0U)
/*! L3A32 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG2_L3A32_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL3 - Layer 3 and Layer 4 Control of Filter 3 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT (0U)
/*! L3PEN3 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3PEN3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT (2U)
/*! L3SAM3 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT (3U)
/*! L3SAIM3 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3SAIM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT (4U)
/*! L3DAM3 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT (5U)
/*! L3DAIM3 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3DAIM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT (6U)
/*! L3HSBM3 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HSBM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT (11U)
/*! L3HDBM3 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L3HDBM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT (16U)
/*! L4PEN3 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4PEN3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT (18U)
/*! L4SPM3 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT (19U)
/*! L4SPIM3 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4SPIM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT (20U)
/*! L4DPM3 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT (21U)
/*! L4DPIM3 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_L4DPIM3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT (24U)
/*! DMCHN3 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHN3_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT (28U)
/*! DMCHEN3 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL3_DMCHEN3_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS3 - Layer 4 Address 3 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT (0U)
/*! L4SP3 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4SP3_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT (16U)
/*! L4DP3 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS3_L4DP3_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG3 - Layer 3 Address 0 Register 3 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT (0U)
/*! L3A03 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG3_L3A03_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG3 - Layer 3 Address 1 Register 3 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT (0U)
/*! L3A13 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG3_L3A13_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG3 - Layer 3 Address 2 Register 3 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT (0U)
/*! L3A23 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG3_L3A23_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG3 - Layer 3 Address 3 Register 3 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT (0U)
/*! L3A33 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG3_L3A33_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL4 - Layer 3 and Layer 4 Control of Filter 4 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT (0U)
/*! L3PEN4 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3PEN4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT (2U)
/*! L3SAM4 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT (3U)
/*! L3SAIM4 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3SAIM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT (4U)
/*! L3DAM4 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT (5U)
/*! L3DAIM4 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3DAIM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT (6U)
/*! L3HSBM4 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HSBM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT (11U)
/*! L3HDBM4 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L3HDBM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT (16U)
/*! L4PEN4 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4PEN4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT (18U)
/*! L4SPM4 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT (19U)
/*! L4SPIM4 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4SPIM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT (20U)
/*! L4DPM4 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT (21U)
/*! L4DPIM4 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_L4DPIM4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT (24U)
/*! DMCHN4 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHN4_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT (28U)
/*! DMCHEN4 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL4_DMCHEN4_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS4 - Layer 4 Address 4 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT (0U)
/*! L4SP4 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4SP4_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT (16U)
/*! L4DP4 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS4_L4DP4_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG4 - Layer 3 Address 0 Register 4 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT (0U)
/*! L3A04 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG4_L3A04_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG4 - Layer 3 Address 1 Register 4 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT (0U)
/*! L3A14 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG4_L3A14_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG4 - Layer 3 Address 2 Register 4 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT (0U)
/*! L3A24 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG4_L3A24_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG4 - Layer 3 Address 3 Register 4 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT (0U)
/*! L3A34 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG4_L3A34_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL5 - Layer 3 and Layer 4 Control of Filter 5 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT (0U)
/*! L3PEN5 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3PEN5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT (2U)
/*! L3SAM5 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT (3U)
/*! L3SAIM5 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3SAIM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT (4U)
/*! L3DAM5 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT (5U)
/*! L3DAIM5 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3DAIM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT (6U)
/*! L3HSBM5 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HSBM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT (11U)
/*! L3HDBM5 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L3HDBM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT (16U)
/*! L4PEN5 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4PEN5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT (18U)
/*! L4SPM5 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT (19U)
/*! L4SPIM5 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4SPIM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT (20U)
/*! L4DPM5 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT (21U)
/*! L4DPIM5 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_L4DPIM5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT (24U)
/*! DMCHN5 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHN5_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT (28U)
/*! DMCHEN5 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL5_DMCHEN5_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS5 - Layer 4 Address 5 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT (0U)
/*! L4SP5 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4SP5_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT (16U)
/*! L4DP5 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS5_L4DP5_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG5 - Layer 3 Address 0 Register 5 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT (0U)
/*! L3A05 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG5_L3A05_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG5 - Layer 3 Address 1 Register 5 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT (0U)
/*! L3A15 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG5_L3A15_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG5 - Layer 3 Address 2 Register 5 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT (0U)
/*! L3A25 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG5_L3A25_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG5 - Layer 3 Address 3 Register 5 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT (0U)
/*! L3A35 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG5_L3A35_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL6 - Layer 3 and Layer 4 Control of Filter 6 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT (0U)
/*! L3PEN6 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3PEN6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT (2U)
/*! L3SAM6 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT (3U)
/*! L3SAIM6 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3SAIM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT (4U)
/*! L3DAM6 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT (5U)
/*! L3DAIM6 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3DAIM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT (6U)
/*! L3HSBM6 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HSBM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT (11U)
/*! L3HDBM6 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L3HDBM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT (16U)
/*! L4PEN6 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4PEN6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT (18U)
/*! L4SPM6 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT (19U)
/*! L4SPIM6 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4SPIM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT (20U)
/*! L4DPM6 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT (21U)
/*! L4DPIM6 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_L4DPIM6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT (24U)
/*! DMCHN6 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHN6_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT (28U)
/*! DMCHEN6 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL6_DMCHEN6_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS6 - Layer 4 Address 6 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT (0U)
/*! L4SP6 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4SP6_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT (16U)
/*! L4DP6 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS6_L4DP6_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG6 - Layer 3 Address 0 Register 6 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT (0U)
/*! L3A06 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG6_L3A06_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG6 - Layer 3 Address 1 Register 6 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT (0U)
/*! L3A16 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG6_L3A16_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG6 - Layer 3 Address 2 Register 6 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT (0U)
/*! L3A26 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG6_L3A26_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG6 - Layer 3 Address 3 Register 6 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT (0U)
/*! L3A36 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG6_L3A36_MASK)
/*! @} */
/*! @name MAC_L3_L4_CONTROL7 - Layer 3 and Layer 4 Control of Filter 0 */
/*! @{ */
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK (0x1U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT (0U)
/*! L3PEN7 - Layer 3 Protocol Enable When this bit is set, the Layer 3 IP Source or Destination
* Address matching is enabled for IPv6 packets.
* 0b0..Layer 3 Protocol is disabled
* 0b1..Layer 3 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3PEN7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK (0x4U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT (2U)
/*! L3SAM7 - Layer 3 IP SA Match Enable When this bit is set, the Layer 3 IP Source Address field is enabled for matching.
* 0b0..Layer 3 IP SA Match is disabled
* 0b1..Layer 3 IP SA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK (0x8U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT (3U)
/*! L3SAIM7 - Layer 3 IP SA Inverse Match Enable When this bit is set, the Layer 3 IP Source Address
* field is enabled for inverse matching.
* 0b0..Layer 3 IP SA Inverse Match is disabled
* 0b1..Layer 3 IP SA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3SAIM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK (0x10U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT (4U)
/*! L3DAM7 - Layer 3 IP DA Match Enable When this bit is set, the Layer 3 IP Destination Address field is enabled for matching.
* 0b0..Layer 3 IP DA Match is disabled
* 0b1..Layer 3 IP DA Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK (0x20U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT (5U)
/*! L3DAIM7 - Layer 3 IP DA Inverse Match Enable When this bit is set, the Layer 3 IP Destination
* Address field is enabled for inverse matching.
* 0b0..Layer 3 IP DA Inverse Match is disabled
* 0b1..Layer 3 IP DA Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3DAIM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK (0x7C0U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT (6U)
/*! L3HSBM7 - Layer 3 IP SA Higher Bits Match IPv4 Packets: This field contains the number of lower
* bits of IP Source Address that are masked for matching in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HSBM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK (0xF800U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT (11U)
/*! L3HDBM7 - Layer 3 IP DA Higher Bits Match IPv4 Packets: This field contains the number of higher
* bits of IP Destination Address that are matched in the IPv4 packets.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L3HDBM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK (0x10000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT (16U)
/*! L4PEN7 - Layer 4 Protocol Enable When this bit is set, the Source and Destination Port number
* fields of UDP packets are used for matching.
* 0b0..Layer 4 Protocol is disabled
* 0b1..Layer 4 Protocol is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4PEN7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK (0x40000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT (18U)
/*! L4SPM7 - Layer 4 Source Port Match Enable When this bit is set, the Layer 4 Source Port number field is enabled for matching.
* 0b0..Layer 4 Source Port Match is disabled
* 0b1..Layer 4 Source Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK (0x80000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT (19U)
/*! L4SPIM7 - Layer 4 Source Port Inverse Match Enable When this bit is set, the Layer 4 Source Port
* number field is enabled for inverse matching.
* 0b0..Layer 4 Source Port Inverse Match is disabled
* 0b1..Layer 4 Source Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4SPIM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK (0x100000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT (20U)
/*! L4DPM7 - Layer 4 Destination Port Match Enable When this bit is set, the Layer 4 Destination
* Port number field is enabled for matching.
* 0b0..Layer 4 Destination Port Match is disabled
* 0b1..Layer 4 Destination Port Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK (0x200000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT (21U)
/*! L4DPIM7 - Layer 4 Destination Port Inverse Match Enable When this bit is set, the Layer 4
* Destination Port number field is enabled for inverse matching.
* 0b0..Layer 4 Destination Port Inverse Match is disabled
* 0b1..Layer 4 Destination Port Inverse Match is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_L4DPIM7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK (0x7000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT (24U)
/*! DMCHN7 - DMA Channel Number When DMCHEN is set high, this field selects the DMA Channel number
* to which the packet passed by this filter is routed.
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHN7_MASK)
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK (0x10000000U)
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT (28U)
/*! DMCHEN7 - DMA Channel Select Enable When set, this bit enables the selection of the DMA channel
* number for the packet that is passed by this L3_L4 filter.
* 0b0..DMA Channel Select is disabled
* 0b1..DMA Channel Select is enabled
*/
#define ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_SHIFT)) & ENET_QOS_MAC_L3_L4_CONTROL7_DMCHEN7_MASK)
/*! @} */
/*! @name MAC_LAYER4_ADDRESS7 - Layer 4 Address 7 */
/*! @{ */
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK (0xFFFFU)
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT (0U)
/*! L4SP7 - Layer 4 Source Port Number Field When the L4PEN0 bit is reset and the L4SPM0 bit is set
* in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the TCP
* Source Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4SP7_MASK)
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK (0xFFFF0000U)
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT (16U)
/*! L4DP7 - Layer 4 Destination Port Number Field When the L4PEN0 bit is reset and the L4DPM0 bit is
* set in the MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with the
* TCP Destination Port Number field in the IPv4 or IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_SHIFT)) & ENET_QOS_MAC_LAYER4_ADDRESS7_L4DP7_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR0_REG7 - Layer 3 Address 0 Register 7 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT (0U)
/*! L3A07 - Layer 3 Address 0 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[31:0] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR0_REG7_L3A07_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR1_REG7 - Layer 3 Address 1 Register 7 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT (0U)
/*! L3A17 - Layer 3 Address 1 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[63:32] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR1_REG7_L3A17_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR2_REG7 - Layer 3 Address 2 Register 7 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT (0U)
/*! L3A27 - Layer 3 Address 2 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[95:64] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR2_REG7_L3A27_MASK)
/*! @} */
/*! @name MAC_LAYER3_ADDR3_REG7 - Layer 3 Address 3 Register 7 */
/*! @{ */
#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT (0U)
/*! L3A37 - Layer 3 Address 3 Field When the L3PEN0 and L3SAM0 bits are set in the
* MAC_L3_L4_CONTROL0 register, this field contains the value to be matched with Bits[127:96] of the IP Source
* Address field in the IPv6 packets.
*/
#define ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_SHIFT)) & ENET_QOS_MAC_LAYER3_ADDR3_REG7_L3A37_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_CONTROL - Timestamp Control */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK (0x1U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT (0U)
/*! TSENA - Enable Timestamp When this bit is set, the timestamp is added for Transmit and Receive packets.
* 0b0..Timestamp is disabled
* 0b1..Timestamp is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK (0x2U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT (1U)
/*! TSCFUPDT - Fine or Coarse Timestamp Update When this bit is set, the Fine method is used to update system timestamp.
* 0b0..Coarse method is used to update system timestamp
* 0b1..Fine method is used to update system timestamp
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCFUPDT_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK (0x4U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT (2U)
/*! TSINIT - Initialize Timestamp When this bit is set, the system time is initialized (overwritten)
* with the value specified in the MAC_System_Time_Seconds_Update and
* MAC_System_Time_Nanoseconds_Update registers.
* 0b0..Timestamp is not initialized
* 0b1..Timestamp is initialized
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSINIT_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK (0x8U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT (3U)
/*! TSUPDT - Update Timestamp When this bit is set, the system time is updated (added or subtracted)
* with the value specified in MAC_System_Time_Seconds_Update and
* MAC_System_Time_Nanoseconds_Update registers.
* 0b0..Timestamp is not updated
* 0b1..Timestamp is updated
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSUPDT_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK (0x20U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT (5U)
/*! TSADDREG - Update Addend Register When this bit is set, the content of the Timestamp Addend
* register is updated in the PTP block for fine correction.
* 0b0..Addend Register is not updated
* 0b1..Addend Register is updated
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSADDREG_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK (0x40U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT (6U)
/*! PTGE - Presentation Time Generation Enable When this bit is set the Presentation Time generation will be enabled.
* 0b0..Presentation Time Generation is disabled
* 0b1..Presentation Time Generation is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_PTGE_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK (0x100U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT (8U)
/*! TSENALL - Enable Timestamp for All Packets When this bit is set, the timestamp snapshot is
* enabled for all packets received by the MAC.
* 0b0..Timestamp for All Packets disabled
* 0b1..Timestamp for All Packets enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENALL_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK (0x200U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT (9U)
/*! TSCTRLSSR - Timestamp Digital or Binary Rollover Control When this bit is set, the Timestamp Low
* register rolls over after 0x3B9A_C9FF value (that is, 1 nanosecond accuracy) and increments
* the timestamp (High) seconds.
* 0b0..Timestamp Digital or Binary Rollover Control is disabled
* 0b1..Timestamp Digital or Binary Rollover Control is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSCTRLSSR_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK (0x400U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT (10U)
/*! TSVER2ENA - Enable PTP Packet Processing for Version 2 Format When this bit is set, the IEEE
* 1588 version 2 format is used to process the PTP packets.
* 0b0..PTP Packet Processing for Version 2 Format is disabled
* 0b1..PTP Packet Processing for Version 2 Format is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSVER2ENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK (0x800U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT (11U)
/*! TSIPENA - Enable Processing of PTP over Ethernet Packets When this bit is set, the MAC receiver
* processes the PTP packets encapsulated directly in the Ethernet packets.
* 0b0..Processing of PTP over Ethernet Packets is disabled
* 0b1..Processing of PTP over Ethernet Packets is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK (0x1000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT (12U)
/*! TSIPV6ENA - Enable Processing of PTP Packets Sent over IPv6-UDP When this bit is set, the MAC
* receiver processes the PTP packets encapsulated in IPv6-UDP packets.
* 0b0..Processing of PTP Packets Sent over IPv6-UDP is disabled
* 0b1..Processing of PTP Packets Sent over IPv6-UDP is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV6ENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK (0x2000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT (13U)
/*! TSIPV4ENA - Enable Processing of PTP Packets Sent over IPv4-UDP When this bit is set, the MAC
* receiver processes the PTP packets encapsulated in IPv4-UDP packets.
* 0b0..Processing of PTP Packets Sent over IPv4-UDP is disabled
* 0b1..Processing of PTP Packets Sent over IPv4-UDP is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSIPV4ENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK (0x4000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT (14U)
/*! TSEVNTENA - Enable Timestamp Snapshot for Event Messages When this bit is set, the timestamp
* snapshot is taken only for event messages (SYNC, Delay_Req, Pdelay_Req, or Pdelay_Resp).
* 0b0..Timestamp Snapshot for Event Messages is disabled
* 0b1..Timestamp Snapshot for Event Messages is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSEVNTENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK (0x8000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT (15U)
/*! TSMSTRENA - Enable Snapshot for Messages Relevant to Master When this bit is set, the snapshot
* is taken only for the messages that are relevant to the master node.
* 0b0..Snapshot for Messages Relevant to Master is disabled
* 0b1..Snapshot for Messages Relevant to Master is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSMSTRENA_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK (0x30000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT (16U)
/*! SNAPTYPSEL - Select PTP packets for Taking Snapshots These bits, along with Bits 15 and 14,
* decide the set of PTP packet types for which snapshot needs to be taken.
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_SNAPTYPSEL_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK (0x40000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT (18U)
/*! TSENMACADDR - Enable MAC Address for PTP Packet Filtering When this bit is set, the DA MAC
* address (that matches any MAC Address register) is used to filter the PTP packets when PTP is
* directly sent over Ethernet.
* 0b0..MAC Address for PTP Packet Filtering is disabled
* 0b1..MAC Address for PTP Packet Filtering is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TSENMACADDR_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK (0x80000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT (19U)
/*! CSC - Enable checksum correction during OST for PTP over UDP/IPv4 packets When this bit is set,
* the last two bytes of PTP message sent over UDP/IPv4 is updated to keep the UDP checksum
* correct, for changes made to origin timestamp and/or correction field as part of one step timestamp
* operation.
* 0b0..checksum correction during OST for PTP over UDP/IPv4 packets is disabled
* 0b1..checksum correction during OST for PTP over UDP/IPv4 packets is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_CSC_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK (0x100000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT (20U)
/*! ESTI - External System Time Input When this bit is set, the MAC uses the external 64-bit
* reference System Time input for the following: - To take the timestamp provided as status - To insert
* the timestamp in transmit PTP packets when One-step Timestamp or Timestamp Offload feature is
* enabled.
* 0b0..External System Time Input is disabled
* 0b1..External System Time Input is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_ESTI_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK (0x1000000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT (24U)
/*! TXTSSTSM - Transmit Timestamp Status Mode When this bit is set, the MAC overwrites the earlier
* transmit timestamp status even if it is not read by the software.
* 0b0..Transmit Timestamp Status Mode is disabled
* 0b1..Transmit Timestamp Status Mode is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_TXTSSTSM_MASK)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK (0x10000000U)
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT (28U)
/*! AV8021ASMEN - AV 802.
* 0b0..AV 802.1AS Mode is disabled
* 0b1..AV 802.1AS Mode is enabled
*/
#define ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_CONTROL_AV8021ASMEN_MASK)
/*! @} */
/*! @name MAC_SUB_SECOND_INCREMENT - Subsecond Increment */
/*! @{ */
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK (0xFF00U)
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT (8U)
/*! SNSINC - Sub-nanosecond Increment Value This field contains the sub-nanosecond increment value,
* represented in nanoseconds multiplied by 2^8.
*/
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SNSINC_MASK)
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK (0xFF0000U)
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT (16U)
/*! SSINC - Sub-second Increment Value The value programmed in this field is accumulated every clock
* cycle (of clk_ptp_i) with the contents of the sub-second register.
*/
#define ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_SHIFT)) & ENET_QOS_MAC_SUB_SECOND_INCREMENT_SSINC_MASK)
/*! @} */
/*! @name MAC_SYSTEM_TIME_SECONDS - System Time Seconds */
/*! @{ */
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT (0U)
/*! TSS - Timestamp Second The value in this field indicates the current value in seconds of the
* System Time maintained by the MAC.
*/
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_TSS_MASK)
/*! @} */
/*! @name MAC_SYSTEM_TIME_NANOSECONDS - System Time Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT (0U)
/*! TSSS - Timestamp Sub Seconds The value in this field has the sub-second representation of time, with an accuracy of 0.
*/
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_TSSS_MASK)
/*! @} */
/*! @name MAC_SYSTEM_TIME_SECONDS_UPDATE - System Time Seconds Update */
/*! @{ */
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT (0U)
/*! TSS - Timestamp Seconds The value in this field is the seconds part of the update.
*/
#define ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_SECONDS_UPDATE_TSS_MASK)
/*! @} */
/*! @name MAC_SYSTEM_TIME_NANOSECONDS_UPDATE - System Time Nanoseconds Update */
/*! @{ */
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT (0U)
/*! TSSS - Timestamp Sub Seconds The value in this field is the sub-seconds part of the update.
*/
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_TSSS_MASK)
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK (0x80000000U)
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT (31U)
/*! ADDSUB - Add or Subtract Time When this bit is set, the time value is subtracted with the contents of the update register.
* 0b0..Add time
* 0b1..Subtract time
*/
#define ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_NANOSECONDS_UPDATE_ADDSUB_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_ADDEND - Timestamp Addend */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT (0U)
/*! TSAR - Timestamp Addend Register This field indicates the 32-bit time value to be added to the
* Accumulator register to achieve time synchronization.
*/
#define ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_ADDEND_TSAR_MASK)
/*! @} */
/*! @name MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS - System Time - Higher Word Seconds */
/*! @{ */
#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK (0xFFFFU)
#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT (0U)
/*! TSHWR - Timestamp Higher Word Register This field contains the most-significant 16-bits of timestamp seconds value.
*/
#define ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_SHIFT)) & ENET_QOS_MAC_SYSTEM_TIME_HIGHER_WORD_SECONDS_TSHWR_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_STATUS - Timestamp Status */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK (0x1U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT (0U)
/*! TSSOVF - Timestamp Seconds Overflow When this bit is set, it indicates that the seconds value of
* the timestamp (when supporting version 2 format) has overflowed beyond 32'hFFFF_FFFF.
* 0b1..Timestamp Seconds Overflow status detected
* 0b0..Timestamp Seconds Overflow status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSSOVF_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK (0x2U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT (1U)
/*! TSTARGT0 - Timestamp Target Time Reached When set, this bit indicates that the value of system
* time is greater than or equal to the value specified in the MAC_PPS0_Target_Time_Seconds and
* MAC_PPS0_Target_Time_Nanoseconds registers.
* 0b1..Timestamp Target Time Reached status detected
* 0b0..Timestamp Target Time Reached status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT0_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK (0x4U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT (2U)
/*! AUXTSTRIG - Auxiliary Timestamp Trigger Snapshot This bit is set high when the auxiliary snapshot is written to the FIFO.
* 0b1..Auxiliary Timestamp Trigger Snapshot status detected
* 0b0..Auxiliary Timestamp Trigger Snapshot status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_AUXTSTRIG_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK (0x8U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT (3U)
/*! TSTRGTERR0 - Timestamp Target Time Error This bit is set when the latest target time programmed
* in the MAC_PPS0_Target_Time_Seconds and MAC_PPS0_Target_Time_Nanoseconds registers elapses.
* 0b1..Timestamp Target Time Error status detected
* 0b0..Timestamp Target Time Error status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR0_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK (0x10U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT (4U)
/*! TSTARGT1 - Timestamp Target Time Reached for Target Time PPS1 When set, this bit indicates that
* the value of system time is greater than or equal to the value specified in the
* MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers.
* 0b1..Timestamp Target Time Reached for Target Time PPS1 status detected
* 0b0..Timestamp Target Time Reached for Target Time PPS1 status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT1_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK (0x20U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT (5U)
/*! TSTRGTERR1 - Timestamp Target Time Error This bit is set when the latest target time programmed
* in the MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS registers elapses.
* 0b1..Timestamp Target Time Error status detected
* 0b0..Timestamp Target Time Error status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR1_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK (0x40U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT (6U)
/*! TSTARGT2 - Timestamp Target Time Reached for Target Time PPS2 When set, this bit indicates that
* the value of system time is greater than or equal to the value specified in the
* MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers.
* 0b1..Timestamp Target Time Reached for Target Time PPS2 status detected
* 0b0..Timestamp Target Time Reached for Target Time PPS2 status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT2_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK (0x80U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT (7U)
/*! TSTRGTERR2 - Timestamp Target Time Error This bit is set when the latest target time programmed
* in the MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS registers elapses.
* 0b1..Timestamp Target Time Error status detected
* 0b0..Timestamp Target Time Error status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR2_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK (0x100U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT (8U)
/*! TSTARGT3 - Timestamp Target Time Reached for Target Time PPS3 When this bit is set, it indicates
* that the value of system time is greater than or equal to the value specified in the
* MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers.
* 0b1..Timestamp Target Time Reached for Target Time PPS3 status detected
* 0b0..Timestamp Target Time Reached for Target Time PPS3 status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTARGT3_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK (0x200U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT (9U)
/*! TSTRGTERR3 - Timestamp Target Time Error This bit is set when the latest target time programmed
* in the MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS registers elapses.
* 0b1..Timestamp Target Time Error status detected
* 0b0..Timestamp Target Time Error status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TSTRGTERR3_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK (0x8000U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT (15U)
/*! TXTSSIS - Tx Timestamp Status Interrupt Status In non-EQOS_CORE configurations when drop
* transmit status is enabled in MTL, this bit is set when the captured transmit timestamp is updated in
* the MAC_TX_TIMESTAMP_STATUS_NANOSECONDS and MAC_TX_TIMESTAMP_STATUS_SECONDS registers.
* 0b1..Tx Timestamp Status Interrupt status detected
* 0b0..Tx Timestamp Status Interrupt status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_TXTSSIS_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK (0xF0000U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT (16U)
/*! ATSSTN - Auxiliary Timestamp Snapshot Trigger Identifier These bits identify the Auxiliary
* trigger inputs for which the timestamp available in the Auxiliary Snapshot Register is applicable.
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTN_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK (0x1000000U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT (24U)
/*! ATSSTM - Auxiliary Timestamp Snapshot Trigger Missed This bit is set when the Auxiliary
* timestamp snapshot FIFO is full and external trigger was set.
* 0b1..Auxiliary Timestamp Snapshot Trigger Missed status detected
* 0b0..Auxiliary Timestamp Snapshot Trigger Missed status not detected
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSSTM_MASK)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK (0x3E000000U)
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT (25U)
/*! ATSNS - Number of Auxiliary Timestamp Snapshots This field indicates the number of Snapshots available in the FIFO.
*/
#define ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_STATUS_ATSNS_MASK)
/*! @} */
/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Transmit Timestamp Status Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT (0U)
/*! TXTSSLO - Transmit Timestamp Status Low This field contains the 31 bits of the Nanoseconds field
* of the Transmit packet's captured timestamp.
*/
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSLO_MASK)
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK (0x80000000U)
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT (31U)
/*! TXTSSMIS - Transmit Timestamp Status Missed When this bit is set, it indicates one of the
* following: - The timestamp of the current packet is ignored if TXTSSTSM bit of the TIMESTAMP_CONTROL
* register is reset - The timestamp of the previous packet is overwritten with timestamp of the
* current packet if TXTSSTSM bit of the MAC_TIMESTAMP_CONTROL register is set.
* 0b1..Transmit Timestamp Status Missed status detected
* 0b0..Transmit Timestamp Status Missed status not detected
*/
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSMIS_MASK)
/*! @} */
/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Transmit Timestamp Status Seconds */
/*! @{ */
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT (0U)
/*! TXTSSHI - Transmit Timestamp Status High This field contains the lower 32 bits of the Seconds
* field of Transmit packet's captured timestamp.
*/
#define ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_SHIFT)) & ENET_QOS_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSHI_MASK)
/*! @} */
/*! @name MAC_AUXILIARY_CONTROL - Auxiliary Timestamp Control */
/*! @{ */
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK (0x1U)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT (0U)
/*! ATSFC - Auxiliary Snapshot FIFO Clear When set, this bit resets the pointers of the Auxiliary Snapshot FIFO.
* 0b0..Auxiliary Snapshot FIFO Clear is disabled
* 0b1..Auxiliary Snapshot FIFO Clear is enabled
*/
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSFC_MASK)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK (0x10U)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT (4U)
/*! ATSEN0 - Auxiliary Snapshot 0 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 0.
* 0b0..Auxiliary Snapshot $i is disabled
* 0b1..Auxiliary Snapshot $i is enabled
*/
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN0_MASK)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK (0x20U)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT (5U)
/*! ATSEN1 - Auxiliary Snapshot 1 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 1.
* 0b0..Auxiliary Snapshot $i is disabled
* 0b1..Auxiliary Snapshot $i is enabled
*/
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN1_MASK)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK (0x40U)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT (6U)
/*! ATSEN2 - Auxiliary Snapshot 2 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 2.
* 0b0..Auxiliary Snapshot $i is disabled
* 0b1..Auxiliary Snapshot $i is enabled
*/
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN2_MASK)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK (0x80U)
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT (7U)
/*! ATSEN3 - Auxiliary Snapshot 3 Enable This bit controls the capturing of Auxiliary Snapshot Trigger 3.
* 0b0..Auxiliary Snapshot $i is disabled
* 0b1..Auxiliary Snapshot $i is enabled
*/
#define ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_SHIFT)) & ENET_QOS_MAC_AUXILIARY_CONTROL_ATSEN3_MASK)
/*! @} */
/*! @name MAC_AUXILIARY_TIMESTAMP_NANOSECONDS - Auxiliary Timestamp Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT (0U)
/*! AUXTSLO - Auxiliary Timestamp Contains the lower 31 bits (nanoseconds field) of the auxiliary timestamp.
*/
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_NANOSECONDS_AUXTSLO_MASK)
/*! @} */
/*! @name MAC_AUXILIARY_TIMESTAMP_SECONDS - Auxiliary Timestamp Seconds */
/*! @{ */
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT (0U)
/*! AUXTSHI - Auxiliary Timestamp Contains the lower 32 bits of the Seconds field of the auxiliary timestamp.
*/
#define ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_SHIFT)) & ENET_QOS_MAC_AUXILIARY_TIMESTAMP_SECONDS_AUXTSHI_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_INGRESS_ASYM_CORR - Timestamp Ingress Asymmetry Correction */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT (0U)
/*! OSTIAC - One-Step Timestamp Ingress Asymmetry Correction This field contains the ingress path
* asymmetry value to be added to correctionField of Pdelay_Resp PTP packet.
*/
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_ASYM_CORR_OSTIAC_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_EGRESS_ASYM_CORR - imestamp Egress Asymmetry Correction */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT (0U)
/*! OSTEAC - One-Step Timestamp Egress Asymmetry Correction This field contains the egress path
* asymmetry value to be subtracted from correctionField of Pdelay_Resp PTP packet.
*/
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_ASYM_CORR_OSTEAC_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp Ingress Correction Nanosecond */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
/*! TSIC - Timestamp Ingress Correction This field contains the ingress path correction value as
* defined by the Ingress Correction expression.
*/
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp Egress Correction Nanosecond */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
/*! TSEC - Timestamp Egress Correction This field contains the nanoseconds part of the egress path
* correction value as defined by the Egress Correction expression.
*/
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC - Timestamp Ingress Correction Subnanosecond */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK (0xFF00U)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT (8U)
/*! TSICSNS - Timestamp Ingress Correction, sub-nanoseconds This field contains the sub-nanoseconds
* part of the ingress path correction value as defined by the "Ingress Correction" expression.
*/
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_CORR_SUBNANOSEC_TSICSNS_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC - Timestamp Egress Correction Subnanosecond */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK (0xFF00U)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT (8U)
/*! TSECSNS - Timestamp Egress Correction, sub-nanoseconds This field contains the sub-nanoseconds
* part of the egress path correction value as defined by the "Egress Correction" expression.
*/
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_CORR_SUBNANOSEC_TSECSNS_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_INGRESS_LATENCY - Timestamp Ingress Latency */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK (0xFF00U)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT (8U)
/*! ITLSNS - Ingress Timestamp Latency, in nanoseconds This register holds the average latency in
* nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII) where the
* ingress timestamp is taken.
*/
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLSNS_MASK)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK (0xFFF0000U)
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT (16U)
/*! ITLNS - Ingress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
* sub-nanoseconds between the input ports (phy_rxd_i) of MAC and the actual point (GMII/MII)
* where the ingress timestamp is taken.
*/
#define ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_INGRESS_LATENCY_ITLNS_MASK)
/*! @} */
/*! @name MAC_TIMESTAMP_EGRESS_LATENCY - Timestamp Egress Latency */
/*! @{ */
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK (0xFF00U)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT (8U)
/*! ETLSNS - Egress Timestamp Latency, in sub-nanoseconds This register holds the average latency in
* sub-nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and
* the output ports (phy_txd_o) of the MAC.
*/
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLSNS_MASK)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK (0xFFF0000U)
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT (16U)
/*! ETLNS - Egress Timestamp Latency, in nanoseconds This register holds the average latency in
* nanoseconds between the actual point (GMII/MII) where the egress timestamp is taken and the output
* ports (phy_txd_o) of the MAC.
*/
#define ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_SHIFT)) & ENET_QOS_MAC_TIMESTAMP_EGRESS_LATENCY_ETLNS_MASK)
/*! @} */
/*! @name MAC_PPS_CONTROL - PPS Control */
/*! @{ */
#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK (0xFU)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT (0U)
/*! PPSCTRL_PPSCMD - PPS Output Frequency Control This field controls the frequency of the PPS0 output (ptp_pps_o[0]) signal.
*/
#define ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCTRL_PPSCMD_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK (0x10U)
#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT (4U)
/*! PPSEN0 - Flexible PPS Output Mode Enable When this bit is set, Bits[3:0] function as PPSCMD.
* 0b0..Flexible PPS Output Mode is disabled
* 0b1..Flexible PPS Output Mode is enabled
*/
#define ENET_QOS_MAC_PPS_CONTROL_PPSEN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSEN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSEN0_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK (0x60U)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT (5U)
/*! TRGTMODSEL0 - Target Time Register Mode for PPS0 Output This field indicates the Target Time
* registers (MAC_PPS0_TARGET_TIME_SECONDS and MAC_PPS0_TARGET_TIME_NANOSECONDS) mode for PPS0
* output signal:
* 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
* 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
* must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
* ptp_pps_o output port
* 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
* 0b01..Reserved
*/
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL0_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK (0x80U)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT (7U)
/*! MCGREN0 - MCGR Mode Enable for PPS0 Output This field enables the 0th PPS instance to operate in PPS or MCGR mode.
* 0b1..0th PPS instance is enabled to operate in MCGR mode
* 0b0..0th PPS instance is enabled to operate in PPS mode
*/
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN0_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN0_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK (0xF00U)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT (8U)
/*! PPSCMD1 - Flexible PPS1 Output Control This field controls the flexible PPS1 output (ptp_pps_o[1]) signal.
*/
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD1_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK (0x6000U)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT (13U)
/*! TRGTMODSEL1 - Target Time Register Mode for PPS1 Output This field indicates the Target Time
* registers (MAC_PPS1_TARGET_TIME_SECONDS and MAC_PPS1_TARGET_TIME_NANOSECONDS) mode for PPS1
* output signal.
* 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
* 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
* must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
* ptp_pps_o output port
* 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
* 0b01..Reserved
*/
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL1_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK (0x8000U)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT (15U)
/*! MCGREN1 - MCGR Mode Enable for PPS1 Output This field enables the 1st PPS instance to operate in PPS or MCGR mode.
* 0b0..1st PPS instance is disabled to operate in PPS or MCGR mode
* 0b1..1st PPS instance is enabled to operate in PPS or MCGR mode
*/
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN1_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN1_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK (0xF0000U)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT (16U)
/*! PPSCMD2 - Flexible PPS2 Output Control This field controls the flexible PPS2 output (ptp_pps_o[2]) signal.
*/
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD2_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK (0x600000U)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT (21U)
/*! TRGTMODSEL2 - Target Time Register Mode for PPS2 Output This field indicates the Target Time
* registers (MAC_PPS2_TARGET_TIME_SECONDS and MAC_PPS2_TARGET_TIME_NANOSECONDS) mode for PPS2
* output signal.
* 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
* 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
* must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
* ptp_pps_o output port
* 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
* 0b01..Reserved
*/
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL2_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK (0x800000U)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT (23U)
/*! MCGREN2 - MCGR Mode Enable for PPS2 Output This field enables the 2nd PPS instance to operate in PPS or MCGR mode.
* 0b0..2nd PPS instance is disabled to operate in PPS or MCGR mode
* 0b1..2nd PPS instance is enabled to operate in PPS or MCGR mode
*/
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN2_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN2_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK (0xF000000U)
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT (24U)
/*! PPSCMD3 - Flexible PPS3 Output Control This field controls the flexible PPS3 output (ptp_pps_o[3]) signal.
*/
#define ENET_QOS_MAC_PPS_CONTROL_PPSCMD3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_PPSCMD3_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK (0x60000000U)
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT (29U)
/*! TRGTMODSEL3 - Target Time Register Mode for PPS3 Output This field indicates the Target Time
* registers (MAC_PPS3_TARGET_TIME_SECONDS and MAC_PPS3_TARGET_TIME_NANOSECONDS) mode for PPS3
* output signal.
* 0b10..Target Time registers are programmed for generating the interrupt event and starting or stopping the PPS0 output signal generation
* 0b00..Target Time registers are programmed only for generating the interrupt event. The Flexible PPS function
* must not be enabled in this mode, otherwise spurious transitions may be observed on the corresponding
* ptp_pps_o output port
* 0b11..Target Time registers are programmed only for starting or stopping the PPS0 output signal generation. No interrupt is asserted
* 0b01..Reserved
*/
#define ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_TRGTMODSEL3_MASK)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK (0x80000000U)
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT (31U)
/*! MCGREN3 - MCGR Mode Enable for PPS3 Output This field enables the 3rd PPS instance to operate in PPS or MCGR mode.
*/
#define ENET_QOS_MAC_PPS_CONTROL_MCGREN3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS_CONTROL_MCGREN3_SHIFT)) & ENET_QOS_MAC_PPS_CONTROL_MCGREN3_MASK)
/*! @} */
/*! @name MAC_PPS0_TARGET_TIME_SECONDS - PPS0 Target Time Seconds */
/*! @{ */
#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT (0U)
/*! TSTRH0 - PPS Target Time Seconds Register This field stores the time in seconds.
*/
#define ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_SECONDS_TSTRH0_MASK)
/*! @} */
/*! @name MAC_PPS0_TARGET_TIME_NANOSECONDS - PPS0 Target Time Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT (0U)
/*! TTSL0 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
*/
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TTSL0_MASK)
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK (0x80000000U)
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT (31U)
/*! TRGTBUSY0 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
* PPS_CONTROL register is programmed to 010 or 011.
* 0b1..PPS Target Time Register Busy is detected
* 0b0..PPS Target Time Register Busy status is not detected
*/
#define ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_SHIFT)) & ENET_QOS_MAC_PPS0_TARGET_TIME_NANOSECONDS_TRGTBUSY0_MASK)
/*! @} */
/*! @name MAC_PPS0_INTERVAL - PPS0 Interval */
/*! @{ */
#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT (0U)
/*! PPSINT0 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_SHIFT)) & ENET_QOS_MAC_PPS0_INTERVAL_PPSINT0_MASK)
/*! @} */
/*! @name MAC_PPS0_WIDTH - PPS0 Width */
/*! @{ */
#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT (0U)
/*! PPSWIDTH0 - PPS Output Signal Width These bits store the width between the rising edge and
* corresponding falling edge of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_SHIFT)) & ENET_QOS_MAC_PPS0_WIDTH_PPSWIDTH0_MASK)
/*! @} */
/*! @name MAC_PPS1_TARGET_TIME_SECONDS - PPS1 Target Time Seconds */
/*! @{ */
#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT (0U)
/*! TSTRH1 - PPS Target Time Seconds Register This field stores the time in seconds.
*/
#define ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_SECONDS_TSTRH1_MASK)
/*! @} */
/*! @name MAC_PPS1_TARGET_TIME_NANOSECONDS - PPS1 Target Time Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT (0U)
/*! TTSL1 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
*/
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TTSL1_MASK)
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK (0x80000000U)
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT (31U)
/*! TRGTBUSY1 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
* PPS_CONTROL register is programmed to 010 or 011.
* 0b1..PPS Target Time Register Busy is detected
* 0b0..PPS Target Time Register Busy status is not detected
*/
#define ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_SHIFT)) & ENET_QOS_MAC_PPS1_TARGET_TIME_NANOSECONDS_TRGTBUSY1_MASK)
/*! @} */
/*! @name MAC_PPS1_INTERVAL - PPS1 Interval */
/*! @{ */
#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT (0U)
/*! PPSINT1 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_SHIFT)) & ENET_QOS_MAC_PPS1_INTERVAL_PPSINT1_MASK)
/*! @} */
/*! @name MAC_PPS1_WIDTH - PPS1 Width */
/*! @{ */
#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT (0U)
/*! PPSWIDTH1 - PPS Output Signal Width These bits store the width between the rising edge and
* corresponding falling edge of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_SHIFT)) & ENET_QOS_MAC_PPS1_WIDTH_PPSWIDTH1_MASK)
/*! @} */
/*! @name MAC_PPS2_TARGET_TIME_SECONDS - PPS2 Target Time Seconds */
/*! @{ */
#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT (0U)
/*! TSTRH2 - PPS Target Time Seconds Register This field stores the time in seconds.
*/
#define ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_SECONDS_TSTRH2_MASK)
/*! @} */
/*! @name MAC_PPS2_TARGET_TIME_NANOSECONDS - PPS2 Target Time Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT (0U)
/*! TTSL2 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
*/
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TTSL2_MASK)
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK (0x80000000U)
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT (31U)
/*! TRGTBUSY2 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
* PPS_CONTROL register is programmed to 010 or 011.
* 0b1..PPS Target Time Register Busy is detected
* 0b0..PPS Target Time Register Busy status is not detected
*/
#define ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_SHIFT)) & ENET_QOS_MAC_PPS2_TARGET_TIME_NANOSECONDS_TRGTBUSY2_MASK)
/*! @} */
/*! @name MAC_PPS2_INTERVAL - PPS2 Interval */
/*! @{ */
#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT (0U)
/*! PPSINT2 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_SHIFT)) & ENET_QOS_MAC_PPS2_INTERVAL_PPSINT2_MASK)
/*! @} */
/*! @name MAC_PPS2_WIDTH - PPS2 Width */
/*! @{ */
#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT (0U)
/*! PPSWIDTH2 - PPS Output Signal Width These bits store the width between the rising edge and
* corresponding falling edge of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_SHIFT)) & ENET_QOS_MAC_PPS2_WIDTH_PPSWIDTH2_MASK)
/*! @} */
/*! @name MAC_PPS3_TARGET_TIME_SECONDS - PPS3 Target Time Seconds */
/*! @{ */
#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT (0U)
/*! TSTRH3 - PPS Target Time Seconds Register This field stores the time in seconds.
*/
#define ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_SECONDS_TSTRH3_MASK)
/*! @} */
/*! @name MAC_PPS3_TARGET_TIME_NANOSECONDS - PPS3 Target Time Nanoseconds */
/*! @{ */
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK (0x7FFFFFFFU)
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT (0U)
/*! TTSL3 - Target Time Low for PPS Register This register stores the time in (signed) nanoseconds.
*/
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TTSL3_MASK)
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK (0x80000000U)
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT (31U)
/*! TRGTBUSY3 - PPS Target Time Register Busy The MAC sets this bit when the PPSCMD0 field in the
* PPS_CONTROL register is programmed to 010 or 011.
* 0b1..PPS Target Time Register Busy is detected
* 0b0..PPS Target Time Register Busy status is not detected
*/
#define ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_SHIFT)) & ENET_QOS_MAC_PPS3_TARGET_TIME_NANOSECONDS_TRGTBUSY3_MASK)
/*! @} */
/*! @name MAC_PPS3_INTERVAL - PPS3 Interval */
/*! @{ */
#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT (0U)
/*! PPSINT3 - PPS Output Signal Interval These bits store the interval between the rising edges of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_SHIFT)) & ENET_QOS_MAC_PPS3_INTERVAL_PPSINT3_MASK)
/*! @} */
/*! @name MAC_PPS3_WIDTH - PPS3 Width */
/*! @{ */
#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT (0U)
/*! PPSWIDTH3 - PPS Output Signal Width These bits store the width between the rising edge and
* corresponding falling edge of PPS0 signal output.
*/
#define ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_SHIFT)) & ENET_QOS_MAC_PPS3_WIDTH_PPSWIDTH3_MASK)
/*! @} */
/*! @name MAC_PTO_CONTROL - PTP Offload Engine Control */
/*! @{ */
#define ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK (0x1U)
#define ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT (0U)
/*! PTOEN - PTP Offload Enable When this bit is set, the PTP Offload feature is enabled.
* 0b0..PTP Offload feature is disabled
* 0b1..PTP Offload feature is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PTOEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PTOEN_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK (0x2U)
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT (1U)
/*! ASYNCEN - Automatic PTP SYNC message Enable When this bit is set, PTP SYNC message is generated
* periodically based on interval programmed or trigger from application, when the MAC is
* programmed to be in Clock Master mode.
* 0b0..Automatic PTP SYNC message is disabled
* 0b1..Automatic PTP SYNC message is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCEN_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK (0x4U)
#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT (2U)
/*! APDREQEN - Automatic PTP Pdelay_Req message Enable When this bit is set, PTP Pdelay_Req message
* is generated periodically based on interval programmed or trigger from application, when the
* MAC is programmed to be in Peer-to-Peer Transparent mode.
* 0b0..Automatic PTP Pdelay_Req message is disabled
* 0b1..Automatic PTP Pdelay_Req message is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_APDREQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQEN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQEN_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK (0x10U)
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT (4U)
/*! ASYNCTRIG - Automatic PTP SYNC message Trigger When this bit is set, one PTP SYNC message is transmitted.
* 0b0..Automatic PTP SYNC message Trigger is disabled
* 0b1..Automatic PTP SYNC message Trigger is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_ASYNCTRIG_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK (0x20U)
#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT (5U)
/*! APDREQTRIG - Automatic PTP Pdelay_Req message Trigger When this bit is set, one PTP Pdelay_Req message is transmitted.
* 0b0..Automatic PTP Pdelay_Req message Trigger is disabled
* 0b1..Automatic PTP Pdelay_Req message Trigger is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_APDREQTRIG_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK (0x40U)
#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT (6U)
/*! DRRDIS - Disable PTO Delay Request/Response response generation When this bit is set, the Delay
* Request and Delay response is not generated for received SYNC and Delay request packet
* respectively, as required by the programmed mode.
* 0b1..PTO Delay Request/Response response generation is disabled
* 0b0..PTO Delay Request/Response response generation is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_DRRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DRRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DRRDIS_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK (0x80U)
#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT (7U)
/*! PDRDIS - Disable Peer Delay Response response generation When this bit is set, the Peer Delay
* Response (Pdelay_Resp) response is not be generated for received Peer Delay Request (Pdelay_Req)
* request packet, as required by the programmed mode.
* 0b1..Peer Delay Response response generation is disabled
* 0b0..Peer Delay Response response generation is enabled
*/
#define ENET_QOS_MAC_PTO_CONTROL_PDRDIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_PDRDIS_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_PDRDIS_MASK)
#define ENET_QOS_MAC_PTO_CONTROL_DN_MASK (0xFF00U)
#define ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT (8U)
/*! DN - Domain Number This field indicates the domain Number in which the PTP node is operating.
*/
#define ENET_QOS_MAC_PTO_CONTROL_DN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_PTO_CONTROL_DN_SHIFT)) & ENET_QOS_MAC_PTO_CONTROL_DN_MASK)
/*! @} */
/*! @name MAC_SOURCE_PORT_IDENTITY0 - Source Port Identity 0 */
/*! @{ */
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT (0U)
/*! SPI0 - Source Port Identity 0 This field indicates bits [31:0] of sourcePortIdentity of PTP node.
*/
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY0_SPI0_MASK)
/*! @} */
/*! @name MAC_SOURCE_PORT_IDENTITY1 - Source Port Identity 1 */
/*! @{ */
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK (0xFFFFFFFFU)
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT (0U)
/*! SPI1 - Source Port Identity 1 This field indicates bits [63:32] of sourcePortIdentity of PTP node.
*/
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY1_SPI1_MASK)
/*! @} */
/*! @name MAC_SOURCE_PORT_IDENTITY2 - Source Port Identity 2 */
/*! @{ */
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK (0xFFFFU)
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT (0U)
/*! SPI2 - Source Port Identity 2 This field indicates bits [79:64] of sourcePortIdentity of PTP node.
*/
#define ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_SHIFT)) & ENET_QOS_MAC_SOURCE_PORT_IDENTITY2_SPI2_MASK)
/*! @} */
/*! @name MAC_LOG_MESSAGE_INTERVAL - Log Message Interval */
/*! @{ */
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK (0xFFU)
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT (0U)
/*! LSI - Log Sync Interval This field indicates the periodicity of the automatically generated SYNC
* message when the PTP node is Master.
*/
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LSI_MASK)
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK (0x700U)
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT (8U)
/*! DRSYNCR - Delay_Req to SYNC Ratio In Slave mode, it is used for controlling frequency of Delay_Req messages transmitted.
* 0b110..Reserved
* 0b000..DelayReq generated for every received SYNC
* 0b100..for every 16 SYNC messages
* 0b001..DelayReq generated every alternate reception of SYNC
* 0b101..for every 32 SYNC messages
* 0b010..for every 4 SYNC messages
* 0b011..for every 8 SYNC messages
*/
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_DRSYNCR_MASK)
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK (0xFF000000U)
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT (24U)
/*! LMPDRI - Log Min Pdelay_Req Interval This field indicates logMinPdelayReqInterval of PTP node.
*/
#define ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_SHIFT)) & ENET_QOS_MAC_LOG_MESSAGE_INTERVAL_LMPDRI_MASK)
/*! @} */
/*! @name MTL_OPERATION_MODE - MTL Operation Mode */
/*! @{ */
#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK (0x2U)
#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT (1U)
/*! DTXSTS - Drop Transmit Status When this bit is set, the Tx packet status received from the MAC is dropped in the MTL.
* 0b0..Drop Transmit Status is disabled
* 0b1..Drop Transmit Status is enabled
*/
#define ENET_QOS_MTL_OPERATION_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_DTXSTS_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_DTXSTS_MASK)
#define ENET_QOS_MTL_OPERATION_MODE_RAA_MASK (0x4U)
#define ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT (2U)
/*! RAA - Receive Arbitration Algorithm This field is used to select the arbitration algorithm for the Rx side.
* 0b0..Strict priority (SP)
* 0b1..Weighted Strict Priority (WSP)
*/
#define ENET_QOS_MTL_OPERATION_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_RAA_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_RAA_MASK)
#define ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK (0x60U)
#define ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT (5U)
/*! SCHALG - Tx Scheduling Algorithm This field indicates the algorithm for Tx scheduling:
* 0b10..DWRR algorithm when DCB feature is selected.Otherwise, Reserved
* 0b11..Strict priority algorithm
* 0b01..WFQ algorithm when DCB feature is selected.Otherwise, Reserved
* 0b00..WRR algorithm
*/
#define ENET_QOS_MTL_OPERATION_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_SCHALG_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_SCHALG_MASK)
#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK (0x100U)
#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT (8U)
/*! CNTPRST - Counters Preset When this bit is set, - MTL_TxQ[0-7]_Underflow register is initialized/preset to 12'h7F0.
* 0b0..Counters Preset is disabled
* 0b1..Counters Preset is enabled
*/
#define ENET_QOS_MTL_OPERATION_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTPRST_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTPRST_MASK)
#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK (0x200U)
#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT (9U)
/*! CNTCLR - Counters Reset When this bit is set, all counters are reset.
* 0b0..Counters are not reset
* 0b1..All counters are reset
*/
#define ENET_QOS_MTL_OPERATION_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_CNTCLR_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_CNTCLR_MASK)
#define ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK (0x8000U)
#define ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT (15U)
/*! FRPE - Flexible Rx parser Enable When this bit is set to 1, the Programmable Rx Parser functionality is enabled.
* 0b0..Flexible Rx parser is disabled
* 0b1..Flexible Rx parser is enabled
*/
#define ENET_QOS_MTL_OPERATION_MODE_FRPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_OPERATION_MODE_FRPE_SHIFT)) & ENET_QOS_MTL_OPERATION_MODE_FRPE_MASK)
/*! @} */
/*! @name MTL_DBG_CTL - FIFO Debug Access Control and Status */
/*! @{ */
#define ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK (0x1U)
#define ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT (0U)
/*! FDBGEN - FIFO Debug Access Enable When this bit is set, it indicates that the debug mode access to the FIFO is enabled.
* 0b0..FIFO Debug Access is disabled
* 0b1..FIFO Debug Access is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_FDBGEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FDBGEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FDBGEN_MASK)
#define ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK (0x2U)
#define ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT (1U)
/*! DBGMOD - Debug Mode Access to FIFO When this bit is set, it indicates that the current access to
* the FIFO is read, write, and debug access.
* 0b0..Debug Mode Access to FIFO is disabled
* 0b1..Debug Mode Access to FIFO is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_DBGMOD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_DBGMOD_SHIFT)) & ENET_QOS_MTL_DBG_CTL_DBGMOD_MASK)
#define ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK (0xCU)
#define ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT (2U)
/*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Write operation.
* 0b11..All four bytes are valid
* 0b10..Byte 0, Byte 1, and Byte 2 are valid
* 0b01..Byte 0 and Byte 1 are valid
* 0b00..Byte 0 valid
*/
#define ENET_QOS_MTL_DBG_CTL_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_BYTEEN_MASK)
#define ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK (0x60U)
#define ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT (5U)
/*! PKTSTATE - Encoded Packet State This field is used to write the control information to the Tx FIFO or Rx FIFO.
* 0b01..Control Word/Normal Status
* 0b11..EOP Data/EOP
* 0b00..Packet Data
* 0b10..SOP Data/Last Status
*/
#define ENET_QOS_MTL_DBG_CTL_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTSTATE_MASK)
#define ENET_QOS_MTL_DBG_CTL_RSTALL_MASK (0x100U)
#define ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT (8U)
/*! RSTALL - Reset All Pointers When this bit is set, the pointers of all FIFOs are reset when FIFO Debug Access is enabled.
* 0b0..Reset All Pointers is disabled
* 0b1..Reset All Pointers is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_RSTALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTALL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTALL_MASK)
#define ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK (0x200U)
#define ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT (9U)
/*! RSTSEL - Reset Pointers of Selected FIFO When this bit is set, the pointers of the
* currently-selected FIFO are reset when FIFO Debug Access is enabled.
* 0b0..Reset Pointers of Selected FIFO is disabled
* 0b1..Reset Pointers of Selected FIFO is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_RSTSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_RSTSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_RSTSEL_MASK)
#define ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK (0x400U)
#define ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT (10U)
/*! FIFORDEN - FIFO Read Enable When this bit is set, it enables the Read operation on selected FIFO when FIFO Debug Access is enabled.
* 0b0..FIFO Read is disabled
* 0b1..FIFO Read is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_FIFORDEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFORDEN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFORDEN_MASK)
#define ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK (0x800U)
#define ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT (11U)
/*! FIFOWREN - FIFO Write Enable When this bit is set, it enables the Write operation on selected
* FIFO when FIFO Debug Access is enabled.
* 0b0..FIFO Write is disabled
* 0b1..FIFO Write is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_FIFOWREN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOWREN_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOWREN_MASK)
#define ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK (0x3000U)
#define ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT (12U)
/*! FIFOSEL - FIFO Selected for Access This field indicates the FIFO selected for debug access:
* 0b11..Rx FIFO
* 0b10..TSO FIFO (cannot be accessed when SLVMOD is set)
* 0b00..Tx FIFO
* 0b01..Tx Status FIFO (only read access when SLVMOD is set)
*/
#define ENET_QOS_MTL_DBG_CTL_FIFOSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_FIFOSEL_SHIFT)) & ENET_QOS_MTL_DBG_CTL_FIFOSEL_MASK)
#define ENET_QOS_MTL_DBG_CTL_PKTIE_MASK (0x4000U)
#define ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT (14U)
/*! PKTIE - Receive Packet Available Interrupt Status Enable When this bit is set, an interrupt is
* generated when EOP of received packet is written to the Rx FIFO.
* 0b0..Receive Packet Available Interrupt Status is disabled
* 0b1..Receive Packet Available Interrupt Status is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_PKTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_PKTIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_PKTIE_MASK)
#define ENET_QOS_MTL_DBG_CTL_STSIE_MASK (0x8000U)
#define ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT (15U)
/*! STSIE - Transmit Status Available Interrupt Status Enable When this bit is set, an interrupt is
* generated when Transmit status is available in slave mode.
* 0b0..Transmit Packet Available Interrupt Status is disabled
* 0b1..Transmit Packet Available Interrupt Status is enabled
*/
#define ENET_QOS_MTL_DBG_CTL_STSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_CTL_STSIE_SHIFT)) & ENET_QOS_MTL_DBG_CTL_STSIE_MASK)
/*! @} */
/*! @name MTL_DBG_STS - FIFO Debug Status */
/*! @{ */
#define ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK (0x1U)
#define ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT (0U)
/*! FIFOBUSY - FIFO Busy When set, this bit indicates that a FIFO operation is in progress in the
* MAC and content of the following fields is not valid: - All other fields of this register - All
* fields of the MTL_FIFO_DEBUG_DATA register
* 0b1..FIFO Busy detected
* 0b0..FIFO Busy not detected
*/
#define ENET_QOS_MTL_DBG_STS_FIFOBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_FIFOBUSY_SHIFT)) & ENET_QOS_MTL_DBG_STS_FIFOBUSY_MASK)
#define ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK (0x6U)
#define ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT (1U)
/*! PKTSTATE - Encoded Packet State This field is used to get the control or status information of the selected FIFO.
* 0b01..Control Word/Normal Status
* 0b11..EOP Data/EOP
* 0b00..Packet Data
* 0b10..SOP Data/Last Status
*/
#define ENET_QOS_MTL_DBG_STS_PKTSTATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTSTATE_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTSTATE_MASK)
#define ENET_QOS_MTL_DBG_STS_BYTEEN_MASK (0x18U)
#define ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT (3U)
/*! BYTEEN - Byte Enables This field indicates the number of data bytes valid in the data register during Read operation.
* 0b11..All four bytes are valid
* 0b10..Byte 0, Byte 1, and Byte 2 are valid
* 0b01..Byte 0 and Byte 1 are valid
* 0b00..Byte 0 valid
*/
#define ENET_QOS_MTL_DBG_STS_BYTEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_BYTEEN_SHIFT)) & ENET_QOS_MTL_DBG_STS_BYTEEN_MASK)
#define ENET_QOS_MTL_DBG_STS_PKTI_MASK (0x100U)
#define ENET_QOS_MTL_DBG_STS_PKTI_SHIFT (8U)
/*! PKTI - Receive Packet Available Interrupt Status When set, this bit indicates that MAC layer has
* written the EOP of received packet to the Rx FIFO.
* 0b1..Receive Packet Available Interrupt Status detected
* 0b0..Receive Packet Available Interrupt Status not detected
*/
#define ENET_QOS_MTL_DBG_STS_PKTI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_PKTI_SHIFT)) & ENET_QOS_MTL_DBG_STS_PKTI_MASK)
#define ENET_QOS_MTL_DBG_STS_STSI_MASK (0x200U)
#define ENET_QOS_MTL_DBG_STS_STSI_SHIFT (9U)
/*! STSI - Transmit Status Available Interrupt Status When set, this bit indicates that the Slave
* mode Tx packet is transmitted, and the status is available in Tx Status FIFO.
* 0b1..Transmit Status Available Interrupt Status detected
* 0b0..Transmit Status Available Interrupt Status not detected
*/
#define ENET_QOS_MTL_DBG_STS_STSI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_STSI_SHIFT)) & ENET_QOS_MTL_DBG_STS_STSI_MASK)
#define ENET_QOS_MTL_DBG_STS_LOCR_MASK (0xFFFF8000U)
#define ENET_QOS_MTL_DBG_STS_LOCR_SHIFT (15U)
/*! LOCR - Remaining Locations in the FIFO Slave Access Mode: This field indicates the space available in selected FIFO.
*/
#define ENET_QOS_MTL_DBG_STS_LOCR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_DBG_STS_LOCR_SHIFT)) & ENET_QOS_MTL_DBG_STS_LOCR_MASK)
/*! @} */
/*! @name MTL_FIFO_DEBUG_DATA - FIFO Debug Data */
/*! @{ */
#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK (0xFFFFFFFFU)
#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT (0U)
/*! FDBGDATA - FIFO Debug Data During debug or slave access write operation, this field contains the
* data to be written to the Tx FIFO, Rx FIFO, or TSO FIFO.
*/
#define ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_SHIFT)) & ENET_QOS_MTL_FIFO_DEBUG_DATA_FDBGDATA_MASK)
/*! @} */
/*! @name MTL_INTERRUPT_STATUS - MTL Interrupt Status */
/*! @{ */
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK (0x1U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT (0U)
/*! Q0IS - Queue 0 Interrupt status This bit indicates that there is an interrupt from Queue 0.
* 0b1..Queue 0 Interrupt status detected
* 0b0..Queue 0 Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q0IS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK (0x2U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT (1U)
/*! Q1IS - Queue 1 Interrupt status This bit indicates that there is an interrupt from Queue 1.
* 0b1..Queue 1 Interrupt status detected
* 0b0..Queue 1 Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q1IS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK (0x4U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT (2U)
/*! Q2IS - Queue 2 Interrupt status This bit indicates that there is an interrupt from Queue 2.
* 0b1..Queue 2 Interrupt status detected
* 0b0..Queue 2 Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q2IS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK (0x8U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT (3U)
/*! Q3IS - Queue 3 Interrupt status This bit indicates that there is an interrupt from Queue 3.
* 0b1..Queue 3 Interrupt status detected
* 0b0..Queue 3 Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q3IS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK (0x10U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT (4U)
/*! Q4IS - Queue 4 Interrupt status This bit indicates that there is an interrupt from Queue 4.
* 0b1..Queue 4 Interrupt status detected
* 0b0..Queue 4 Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_Q4IS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK (0x20000U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT (17U)
/*! DBGIS - Debug Interrupt status This bit indicates an interrupt event during the slave access.
* 0b1..Debug Interrupt status detected
* 0b0..Debug Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_DBGIS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK (0x40000U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT (18U)
/*! ESTIS - EST (TAS- 802.
* 0b1..EST (TAS- 802.1Qbv) Interrupt status detected
* 0b0..EST (TAS- 802.1Qbv) Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_ESTIS_MASK)
#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK (0x800000U)
#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT (23U)
/*! MTLPIS - MTL Rx Parser Interrupt Status This bit indicates that there is an interrupt from Rx Parser Block.
* 0b1..MTL Rx Parser Interrupt status detected
* 0b0..MTL Rx Parser Interrupt status not detected
*/
#define ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_SHIFT)) & ENET_QOS_MTL_INTERRUPT_STATUS_MTLPIS_MASK)
/*! @} */
/*! @name MTL_RXQ_DMA_MAP0 - Receive Queue and DMA Channel Mapping 0 */
/*! @{ */
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK (0x7U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT (0U)
/*! Q0MDMACH - Queue 0 Mapped to DMA Channel This field controls the routing of the packet received
* in Queue 0 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
* - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
* field is valid when the Q0DDMACH field is reset.
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0MDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK (0x10U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT (4U)
/*! Q0DDMACH - Queue 0 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
* the packets received in Queue 0 are routed to a particular DMA channel as decided in the MAC
* Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
* Ethernet DA address.
* 0b0..Queue 0 disabled for DA-based DMA Channel Selection
* 0b1..Queue 0 enabled for DA-based DMA Channel Selection
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q0DDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK (0x700U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT (8U)
/*! Q1MDMACH - Queue 1 Mapped to DMA Channel This field controls the routing of the received packet
* in Queue 1 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
* - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
* field is valid when the Q1DDMACH field is reset.
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1MDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK (0x1000U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT (12U)
/*! Q1DDMACH - Queue 1 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
* the packets received in Queue 1 are routed to a particular DMA channel as decided in the MAC
* Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
* Ethernet DA address.
* 0b0..Queue 1 disabled for DA-based DMA Channel Selection
* 0b1..Queue 1 enabled for DA-based DMA Channel Selection
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q1DDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK (0x70000U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT (16U)
/*! Q2MDMACH - Queue 2 Mapped to DMA Channel This field controls the routing of the received packet
* in Queue 2 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
* - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
* field is valid when the Q2DDMACH field is reset.
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2MDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK (0x100000U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT (20U)
/*! Q2DDMACH - Queue 2 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
* the packets received in Queue 2 are routed to a particular DMA channel as decided in the MAC
* Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
* Ethernet DA address.
* 0b0..Queue 2 disabled for DA-based DMA Channel Selection
* 0b1..Queue 2 enabled for DA-based DMA Channel Selection
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q2DDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK (0x7000000U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT (24U)
/*! Q3MDMACH - Queue 3 Mapped to DMA Channel This field controls the routing of the received packet
* in Queue 3 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
* - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
* field is valid when the Q3DDMACH field is reset.
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3MDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK (0x10000000U)
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT (28U)
/*! Q3DDMACH - Queue 3 Enabled for Dynamic (per packet) DMA Channel Selection When set, this bit
* indicates that the packets received in Queue 3 are routed to a particular DMA channel as decided
* in the MAC Receiver based on the DMA channel number programmed in the L3-L4 filter registers,
* or the Ethernet DA address.
* 0b0..Queue 3 disabled for DA-based DMA Channel Selection
* 0b1..Queue 3 enabled for DA-based DMA Channel Selection
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP0_Q3DDMACH_MASK)
/*! @} */
/*! @name MTL_RXQ_DMA_MAP1 - Receive Queue and DMA Channel Mapping 1 */
/*! @{ */
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK (0x7U)
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT (0U)
/*! Q4MDMACH - Queue 4 Mapped to DMA Channel This field controls the routing of the packet received
* in Queue 4 to the DMA channel: - 000: DMA Channel 0 - 001: DMA Channel 1 - 010: DMA Channel 2
* - 011: DMA Channel 3 - 100: DMA Channel 4 - 101: Reserved - 110: Reserved - 111: Reserved This
* field is valid when the Q4DDMACH field is reset.
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4MDMACH_MASK)
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK (0x10U)
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT (4U)
/*! Q4DDMACH - Queue 4 Enabled for DA-based DMA Channel Selection When set, this bit indicates that
* the packets received in Queue 4 are routed to a particular DMA channel as decided in the MAC
* Receiver based on the DMA channel number programmed in the L3-L4 filter registers, or the
* Ethernet DA address.
* 0b0..Queue 4 disabled for DA-based DMA Channel Selection
* 0b1..Queue 4 enabled for DA-based DMA Channel Selection
*/
#define ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_SHIFT)) & ENET_QOS_MTL_RXQ_DMA_MAP1_Q4DDMACH_MASK)
/*! @} */
/*! @name MTL_TBS_CTRL - Time Based Scheduling Control */
/*! @{ */
#define ENET_QOS_MTL_TBS_CTRL_ESTM_MASK (0x1U)
#define ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT (0U)
/*! ESTM - EST offset Mode When this bit is set, the Launch Time value used in Time Based Scheduling
* is interpreted as an EST offset value and is added to the Base Time Register (BTR) of the
* current list.
* 0b0..EST offset Mode is disabled
* 0b1..EST offset Mode is enabled
*/
#define ENET_QOS_MTL_TBS_CTRL_ESTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_ESTM_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_ESTM_MASK)
#define ENET_QOS_MTL_TBS_CTRL_LEOV_MASK (0x2U)
#define ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT (1U)
/*! LEOV - Launch Expiry Offset Valid When set indicates the LEOS field is valid.
* 0b0..LEOS field is invalid
* 0b1..LEOS field is valid
*/
#define ENET_QOS_MTL_TBS_CTRL_LEOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOV_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOV_MASK)
#define ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK (0x70U)
#define ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT (4U)
/*! LEGOS - Launch Expiry GSN Offset The number GSN slots that has to be added to the Launch GSN to compute the Launch Expiry time.
*/
#define ENET_QOS_MTL_TBS_CTRL_LEGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEGOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEGOS_MASK)
#define ENET_QOS_MTL_TBS_CTRL_LEOS_MASK (0xFFFFFF00U)
#define ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT (8U)
/*! LEOS - Launch Expiry Offset The value in units of 256 nanoseconds that has to be added to the
* Launch time to compute the Launch Expiry time.
*/
#define ENET_QOS_MTL_TBS_CTRL_LEOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TBS_CTRL_LEOS_SHIFT)) & ENET_QOS_MTL_TBS_CTRL_LEOS_MASK)
/*! @} */
/*! @name MTL_EST_CONTROL - Enhancements to Scheduled Transmission Control */
/*! @{ */
#define ENET_QOS_MTL_EST_CONTROL_EEST_MASK (0x1U)
#define ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT (0U)
/*! EEST - Enable EST When reset, the gate control list processing is halted and all gates are assumed to be in Open state.
* 0b0..EST is disabled
* 0b1..EST is enabled
*/
#define ENET_QOS_MTL_EST_CONTROL_EEST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_EEST_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_EEST_MASK)
#define ENET_QOS_MTL_EST_CONTROL_SSWL_MASK (0x2U)
#define ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT (1U)
/*! SSWL - Switch to S/W owned list When set indicates that the software has programmed that list
* that it currently owns (SWOL) and the hardware should switch to the new list based on the new
* BTR.
* 0b0..Switch to S/W owned list is disabled
* 0b1..Switch to S/W owned list is enabled
*/
#define ENET_QOS_MTL_EST_CONTROL_SSWL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_SSWL_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_SSWL_MASK)
#define ENET_QOS_MTL_EST_CONTROL_DDBF_MASK (0x10U)
#define ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT (4U)
/*! DDBF - Do not Drop frames during Frame Size Error When set, frames are not be dropped during
* Head-of-Line blocking due to Frame Size Error (HLBF field of MTL_EST_STATUS register).
* 0b1..Do not Drop frames during Frame Size Error
* 0b0..Drop frames during Frame Size Error
*/
#define ENET_QOS_MTL_EST_CONTROL_DDBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DDBF_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DDBF_MASK)
#define ENET_QOS_MTL_EST_CONTROL_DFBS_MASK (0x20U)
#define ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT (5U)
/*! DFBS - Drop Frames causing Scheduling Error When set frames reported to cause HOL Blocking due
* to not getting scheduled (HLBS field of EST_STATUS register) after 4,8,16,32 (based on LCSE
* field of this register) GCL iterations are dropped.
* 0b0..Do not Drop Frames causing Scheduling Error
* 0b1..Drop Frames causing Scheduling Error
*/
#define ENET_QOS_MTL_EST_CONTROL_DFBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_DFBS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_DFBS_MASK)
#define ENET_QOS_MTL_EST_CONTROL_LCSE_MASK (0xC0U)
#define ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT (6U)
/*! LCSE - Loop Count to report Scheduling Error Programmable number of GCL list iterations before
* reporting an HLBS error defined in EST_STATUS register.
* 0b10..16 iterations
* 0b11..32 iterations
* 0b00..4 iterations
* 0b01..8 iterations
*/
#define ENET_QOS_MTL_EST_CONTROL_LCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_LCSE_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_LCSE_MASK)
#define ENET_QOS_MTL_EST_CONTROL_TILS_MASK (0x700U)
#define ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT (8U)
/*! TILS - Time Interval Left Shift Amount This field provides the left shift amount for the
* programmed Time Interval values used in the Gate Control Lists.
*/
#define ENET_QOS_MTL_EST_CONTROL_TILS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_TILS_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_TILS_MASK)
#define ENET_QOS_MTL_EST_CONTROL_CTOV_MASK (0xFFF000U)
#define ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT (12U)
/*! CTOV - Current Time Offset Value Provides a 12 bit time offset value in nano second that is
* added to the current time to compensate for all the implementation pipeline delays such as the CDC
* sync delay, buffering delays, data path delays etc.
*/
#define ENET_QOS_MTL_EST_CONTROL_CTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_CTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_CTOV_MASK)
#define ENET_QOS_MTL_EST_CONTROL_PTOV_MASK (0xFF000000U)
#define ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT (24U)
/*! PTOV - PTP Time Offset Value The value of PTP Clock period multiplied by 6 in nanoseconds.
*/
#define ENET_QOS_MTL_EST_CONTROL_PTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_CONTROL_PTOV_SHIFT)) & ENET_QOS_MTL_EST_CONTROL_PTOV_MASK)
/*! @} */
/*! @name MTL_EST_STATUS - Enhancements to Scheduled Transmission Status */
/*! @{ */
#define ENET_QOS_MTL_EST_STATUS_SWLC_MASK (0x1U)
#define ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT (0U)
/*! SWLC - Switch to S/W owned list Complete When "1" indicates the hardware has successfully
* switched to the SWOL, and the SWOL bit has been updated to that effect.
* 0b1..Switch to S/W owned list Complete detected
* 0b0..Switch to S/W owned list Complete not detected
*/
#define ENET_QOS_MTL_EST_STATUS_SWLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWLC_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWLC_MASK)
#define ENET_QOS_MTL_EST_STATUS_BTRE_MASK (0x2U)
#define ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT (1U)
/*! BTRE - BTR Error When "1" indicates a programming error in the BTR of SWOL where the programmed
* value is less than current time.
* 0b1..BTR Error detected
* 0b0..BTR Error not detected
*/
#define ENET_QOS_MTL_EST_STATUS_BTRE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRE_MASK)
#define ENET_QOS_MTL_EST_STATUS_HLBF_MASK (0x4U)
#define ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT (2U)
/*! HLBF - Head-Of-Line Blocking due to Frame Size Set when HOL Blocking is noticed on one or more
* Queues as a result of none of the Time Intervals of gate open in the GCL being greater than or
* equal to the duration needed for frame size (or frame fragment size when preemption is
* enabled) transmission.
* 0b1..Head-Of-Line Blocking due to Frame Size detected
* 0b0..Head-Of-Line Blocking due to Frame Size not detected
*/
#define ENET_QOS_MTL_EST_STATUS_HLBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBF_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBF_MASK)
#define ENET_QOS_MTL_EST_STATUS_HLBS_MASK (0x8U)
#define ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT (3U)
/*! HLBS - Head-Of-Line Blocking due to Scheduling Set when the frame is not able to win arbitration
* and get scheduled even after 4 iterations of the GCL.
* 0b1..Head-Of-Line Blocking due to Scheduling detected
* 0b0..Head-Of-Line Blocking due to Scheduling not detected
*/
#define ENET_QOS_MTL_EST_STATUS_HLBS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_HLBS_SHIFT)) & ENET_QOS_MTL_EST_STATUS_HLBS_MASK)
#define ENET_QOS_MTL_EST_STATUS_CGCE_MASK (0x10U)
#define ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT (4U)
/*! CGCE - Constant Gate Control Error This error occurs when the list length (LLR) is 1 and the
* programmed Time Interval (TI) value after the optional Left Shifting is less than or equal to the
* Cycle Time (CTR).
* 0b1..Constant Gate Control Error detected
* 0b0..Constant Gate Control Error not detected
*/
#define ENET_QOS_MTL_EST_STATUS_CGCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGCE_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGCE_MASK)
#define ENET_QOS_MTL_EST_STATUS_SWOL_MASK (0x80U)
#define ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT (7U)
/*! SWOL - S/W owned list When '0' indicates Gate control list number "0" is owned by software and
* when "1" indicates the Gate Control list "1" is owned by the software.
* 0b1..Gate control list number "1" is owned by software
* 0b0..Gate control list number "0" is owned by software
*/
#define ENET_QOS_MTL_EST_STATUS_SWOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_SWOL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_SWOL_MASK)
#define ENET_QOS_MTL_EST_STATUS_BTRL_MASK (0xF00U)
#define ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT (8U)
/*! BTRL - BTR Error Loop Count Provides the minimum count (N) for which the equation Current Time
* =< New BTR + (N * New Cycle Time) becomes true.
*/
#define ENET_QOS_MTL_EST_STATUS_BTRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_BTRL_SHIFT)) & ENET_QOS_MTL_EST_STATUS_BTRL_MASK)
#define ENET_QOS_MTL_EST_STATUS_CGSN_MASK (0xF0000U)
#define ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT (16U)
/*! CGSN - Current GCL Slot Number Indicates the slot number of the GCL list.
*/
#define ENET_QOS_MTL_EST_STATUS_CGSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_STATUS_CGSN_SHIFT)) & ENET_QOS_MTL_EST_STATUS_CGSN_MASK)
/*! @} */
/*! @name MTL_EST_SCH_ERROR - EST Scheduling Error */
/*! @{ */
#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK (0x1FU)
#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT (0U)
/*! SEQN - Schedule Error Queue Number The One Hot Encoded Queue Numbers that have experienced
* error/timeout described in HLBS field of status register.
*/
#define ENET_QOS_MTL_EST_SCH_ERROR_SEQN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_SCH_ERROR_SEQN_SHIFT)) & ENET_QOS_MTL_EST_SCH_ERROR_SEQN_MASK)
/*! @} */
/*! @name MTL_EST_FRM_SIZE_ERROR - EST Frame Size Error */
/*! @{ */
#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK (0x1FU)
#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT (0U)
/*! FEQN - Frame Size Error Queue Number The One Hot Encoded Queue Numbers that have experienced
* error described in HLBF field of status register.
*/
#define ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_ERROR_FEQN_MASK)
/*! @} */
/*! @name MTL_EST_FRM_SIZE_CAPTURE - EST Frame Size Capture */
/*! @{ */
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK (0x7FFFU)
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT (0U)
/*! HBFS - Frame Size of HLBF Captures the Frame Size of the dropped frame related to queue number
* indicated in HBFQ field of this register.
*/
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFS_MASK)
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK (0x70000U)
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT (16U)
/*! HBFQ - Queue Number of HLBF Captures the binary value of the of the first Queue (number)
* experiencing HLBF error (see HLBF field of status register).
*/
#define ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_SHIFT)) & ENET_QOS_MTL_EST_FRM_SIZE_CAPTURE_HBFQ_MASK)
/*! @} */
/*! @name MTL_EST_INTR_ENABLE - EST Interrupt Enable */
/*! @{ */
#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK (0x1U)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT (0U)
/*! IECC - Interrupt Enable for Switch List When set, generates interrupt when the configuration
* change is successful and the hardware has switched to the new list.
* 0b0..Interrupt for Switch List is disabled
* 0b1..Interrupt for Switch List is enabled
*/
#define ENET_QOS_MTL_EST_INTR_ENABLE_IECC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IECC_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IECC_MASK)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK (0x2U)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT (1U)
/*! IEBE - Interrupt Enable for BTR Error When set, generates interrupt when the BTR Error occurs and is indicated in the status.
* 0b0..Interrupt for BTR Error is disabled
* 0b1..Interrupt for BTR Error is enabled
*/
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEBE_MASK)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK (0x4U)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT (2U)
/*! IEHF - Interrupt Enable for HLBF When set, generates interrupt when the Head-of-Line Blocking
* due to Frame Size error occurs and is indicated in the status.
* 0b0..Interrupt for HLBF is disabled
* 0b1..Interrupt for HLBF is enabled
*/
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHF_MASK)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK (0x8U)
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT (3U)
/*! IEHS - Interrupt Enable for HLBS When set, generates interrupt when the Head-of-Line Blocking
* due to Scheduling issue and is indicated in the status.
* 0b0..Interrupt for HLBS is disabled
* 0b1..Interrupt for HLBS is enabled
*/
#define ENET_QOS_MTL_EST_INTR_ENABLE_IEHS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_IEHS_MASK)
#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK (0x10U)
#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT (4U)
/*! CGCE - Interrupt Enable for CGCE When set, generates interrupt when the Constant Gate Control
* Error occurs and is indicated in the status.
* 0b0..Interrupt for CGCE is disabled
* 0b1..Interrupt for CGCE is enabled
*/
#define ENET_QOS_MTL_EST_INTR_ENABLE_CGCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_SHIFT)) & ENET_QOS_MTL_EST_INTR_ENABLE_CGCE_MASK)
/*! @} */
/*! @name MTL_EST_GCL_CONTROL - EST GCL Control */
/*! @{ */
#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK (0x1U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT (0U)
/*! SRWO - Start Read/Write Op When set indicates a Read/Write Op has started and is in progress.
* 0b0..Start Read/Write Op disabled
* 0b1..Start Read/Write Op enabled
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_SRWO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_SRWO_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK (0x2U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT (1U)
/*! R1W0 - Read '1', Write '0': When set to '1': Read Operation When set to '0': Write Operation.
* 0b1..Read Operation
* 0b0..Write Operation
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_R1W0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_R1W0_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK (0x4U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT (2U)
/*! GCRR - Gate Control Related Registers When set to "1" indicates the R/W access is for the GCL
* related registers (BTR, CTR, TER, LLR) whose address is provided by GCRA.
* 0b0..Gate Control Related Registers are disabled
* 0b1..Gate Control Related Registers are enabled
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_GCRR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_GCRR_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK (0x10U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT (4U)
/*! DBGM - Debug Mode When set to "1" indicates R/W in debug mode where the memory bank (for GCL and
* Time related registers) is explicitly provided by DBGB value, when set to "0" SWOL bit is
* used to determine which bank to use.
* 0b0..Debug Mode is disabled
* 0b1..Debug Mode is enabled
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGM_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK (0x20U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT (5U)
/*! DBGB - Debug Mode Bank Select When set to "0" indicates R/W in debug mode should be directed to
* Bank 0 (GCL0 and corresponding Time related registers).
* 0b0..R/W in debug mode should be directed to Bank 0
* 0b1..R/W in debug mode should be directed to Bank 1
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_DBGB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_DBGB_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK (0x1FF00U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT (8U)
/*! ADDR - Gate Control List Address: (GCLA when GCRR is "0").
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ADDR_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK (0x100000U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT (20U)
/*! ERR0 - When set indicates the last write operation was aborted as software writes to GCL and GCL
* registers is prohibited when SSWL bit of MTL_EST_CONTROL Register is set.
* 0b0..ERR0 is disabled
* 0b1..ERR1 is enabled
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_ERR0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ERR0_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK (0x200000U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT (21U)
/*! ESTEIEE - EST ECC Inject Error Enable When set along with EEST bit of MTL_EST_CONTROL register,
* enables the ECC error injection feature.
* 0b0..EST ECC Inject Error is disabled
* 0b1..EST ECC Inject Error is enabled
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEE_MASK)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK (0xC00000U)
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT (22U)
/*! ESTEIEC - ECC Inject Error Control for EST Memory When EIEE bit of this register is set,
* following are the errors inserted based on the value encoded in this field.
* 0b00..Insert 1 bit error
* 0b11..Insert 1 bit error in address field
* 0b01..Insert 2 bit errors
* 0b10..Insert 3 bit errors
*/
#define ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_SHIFT)) & ENET_QOS_MTL_EST_GCL_CONTROL_ESTEIEC_MASK)
/*! @} */
/*! @name MTL_EST_GCL_DATA - EST GCL Data */
/*! @{ */
#define ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK (0xFFFFFFFFU)
#define ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT (0U)
/*! GCD - Gate Control Data The data corresponding to the address selected in the MTL_GCL_CONTROL register.
*/
#define ENET_QOS_MTL_EST_GCL_DATA_GCD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_EST_GCL_DATA_GCD_SHIFT)) & ENET_QOS_MTL_EST_GCL_DATA_GCD_MASK)
/*! @} */
/*! @name MTL_FPE_CTRL_STS - Frame Preemption Control and Status */
/*! @{ */
#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK (0x3U)
#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT (0U)
/*! AFSZ - Additional Fragment Size used to indicate, in units of 64 bytes, the minimum number of
* bytes over 64 bytes required in non-final fragments of preempted frames.
*/
#define ENET_QOS_MTL_FPE_CTRL_STS_AFSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_AFSZ_MASK)
#define ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK (0x1F00U)
#define ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT (8U)
/*! PEC - Preemption Classification When set indicates the corresponding Queue must be classified as
* preemptable, when '0' Queue is classified as express.
*/
#define ENET_QOS_MTL_FPE_CTRL_STS_PEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_PEC_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_PEC_MASK)
#define ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK (0x10000000U)
#define ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT (28U)
/*! HRS - Hold/Release Status - 1: Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State.
* 0b1..Indicates a Set-and-Hold-MAC operation was last executed and the pMAC is in Hold State
* 0b0..Indicates a Set-and-Release-MAC operation was last executed and the pMAC is in Release State
*/
#define ENET_QOS_MTL_FPE_CTRL_STS_HRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_CTRL_STS_HRS_SHIFT)) & ENET_QOS_MTL_FPE_CTRL_STS_HRS_MASK)
/*! @} */
/*! @name MTL_FPE_ADVANCE - Frame Preemption Hold and Release Advance */
/*! @{ */
#define ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK (0xFFFFU)
#define ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT (0U)
/*! HADV - Hold Advance The maximum time in nanoseconds that can elapse between issuing a HOLD to
* the MAC and the MAC ceasing to transmit any preemptable frame that is in the process of
* transmission or any preemptable frames that are queued for transmission.
*/
#define ENET_QOS_MTL_FPE_ADVANCE_HADV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_HADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_HADV_MASK)
#define ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK (0xFFFF0000U)
#define ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT (16U)
/*! RADV - Release Advance The maximum time in nanoseconds that can elapse between issuing a RELEASE
* to the MAC and the MAC being ready to resume transmission of preemptable frames, in the
* absence of there being any express frames available for transmission.
*/
#define ENET_QOS_MTL_FPE_ADVANCE_RADV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_FPE_ADVANCE_RADV_SHIFT)) & ENET_QOS_MTL_FPE_ADVANCE_RADV_MASK)
/*! @} */
/*! @name MTL_RXP_CONTROL_STATUS - RXP Control Status */
/*! @{ */
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK (0xFFU)
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT (0U)
/*! NVE - Number of valid entries in the Instruction table This control indicates the number of
* valid entries in the Instruction Memory.
*/
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NVE_MASK)
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK (0xFF0000U)
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT (16U)
/*! NPE - Number of parsable entries in the Instruction table This control indicates the number of
* parsable entries in the Instruction Memory.
*/
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_NPE_MASK)
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK (0x80000000U)
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT (31U)
/*! RXPI - RX Parser in Idle state This status bit is set to 1 when the Rx parser is in Idle State
* and waiting for a new packet for processing.
* 0b1..RX Parser in Idle state
* 0b0..RX Parser not in Idle state
*/
#define ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_SHIFT)) & ENET_QOS_MTL_RXP_CONTROL_STATUS_RXPI_MASK)
/*! @} */
/*! @name MTL_RXP_INTERRUPT_CONTROL_STATUS - RXP Interrupt Control Status */
/*! @{ */
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK (0x1U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT (0U)
/*! NVEOVIS - Number of Valid Entries Overflow Interrupt Status While parsing if the Instruction
* address found to be more than NVE (Number of Valid Entries in MTL_RXP_CONTROL register), then
* this bit is set to 1.
* 0b1..Number of Valid Entries Overflow Interrupt Status detected
* 0b0..Number of Valid Entries Overflow Interrupt Status not detected
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIS_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK (0x2U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT (1U)
/*! NPEOVIS - Number of Parsable Entries Overflow Interrupt Status While parsing a packet if the
* number of parsed entries found to be more than NPE[] (Number of Parseable Entries in
* MTL_RXP_CONTROL register),then this bit is set to 1.
* 0b1..Number of Parsable Entries Overflow Interrupt Status detected
* 0b0..Number of Parsable Entries Overflow Interrupt Status not detected
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIS_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK (0x4U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT (2U)
/*! FOOVIS - Frame Offset Overflow Interrupt Status While parsing if the Instruction table entry's
* 'Frame Offset' found to be more than EOF offset, then then this bit is set.
* 0b1..Frame Offset Overflow Interrupt Status detected
* 0b0..Frame Offset Overflow Interrupt Status not detected
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIS_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK (0x8U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT (3U)
/*! PDRFIS - Packet Dropped due to RF Interrupt Status If the Rx Parser result says to drop the
* packet by setting RF=1 in the instruction memory, then this bit is set to 1.
* 0b1..Packet Dropped due to RF Interrupt Status detected
* 0b0..Packet Dropped due to RF Interrupt Status not detected
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIS_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK (0x10000U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT (16U)
/*! NVEOVIE - Number of Valid Entries Overflow Interrupt Enable When this bit is set, the NVEOVIS interrupt is enabled.
* 0b0..Number of Valid Entries Overflow Interrupt is disabled
* 0b1..Number of Valid Entries Overflow Interrupt is enabled
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NVEOVIE_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK (0x20000U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT (17U)
/*! NPEOVIE - Number of Parsable Entries Overflow Interrupt Enable When this bit is set, the NPEOVIS interrupt is enabled.
* 0b0..Number of Parsable Entries Overflow Interrupt is disabled
* 0b1..Number of Parsable Entries Overflow Interrupt is enabled
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_NPEOVIE_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK (0x40000U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT (18U)
/*! FOOVIE - Frame Offset Overflow Interrupt Enable When this bit is set, the FOOVIS interrupt is enabled.
* 0b0..Frame Offset Overflow Interrupt is disabled
* 0b1..Frame Offset Overflow Interrupt is enabled
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_FOOVIE_MASK)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK (0x80000U)
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT (19U)
/*! PDRFIE - Packet Drop due to RF Interrupt Enable When this bit is set, the PDRFIS interrupt is enabled.
* 0b0..Packet Drop due to RF Interrupt is disabled
* 0b1..Packet Drop due to RF Interrupt is enabled
*/
#define ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_SHIFT)) & ENET_QOS_MTL_RXP_INTERRUPT_CONTROL_STATUS_PDRFIE_MASK)
/*! @} */
/*! @name MTL_RXP_DROP_CNT - RXP Drop Count */
/*! @{ */
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK (0x7FFFFFFFU)
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT (0U)
/*! RXPDC - Rx Parser Drop count This 31-bit counter is implemented whenever a Rx Parser Drops a packet due to RF =1.
*/
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDC_MASK)
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK (0x80000000U)
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT (31U)
/*! RXPDCOVF - Rx Parser Drop Counter Overflow Bit When set, this bit indicates that the
* MTL_RXP_DROP_CNT (RXPDC) Counter field crossed the maximum limit.
* 0b1..Rx Parser Drop count overflow occurred
* 0b0..Rx Parser Drop count overflow not occurred
*/
#define ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_SHIFT)) & ENET_QOS_MTL_RXP_DROP_CNT_RXPDCOVF_MASK)
/*! @} */
/*! @name MTL_RXP_ERROR_CNT - RXP Error Count */
/*! @{ */
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK (0x7FFFFFFFU)
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT (0U)
/*! RXPEC - Rx Parser Error count This 31-bit counter is implemented whenever a Rx Parser encounters
* following Error scenarios - Entry address >= NVE[] - Number Parsed Entries >= NPE[] - Entry
* address > EOF data entry address The counter is cleared when the register is read.
*/
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPEC_MASK)
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK (0x80000000U)
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT (31U)
/*! RXPECOVF - Rx Parser Error Counter Overflow Bit When set, this bit indicates that the
* MTL_RXP_ERROR_CNT (RXPEC) Counter field crossed the maximum limit.
* 0b1..Rx Parser Error count overflow occurred
* 0b0..Rx Parser Error count overflow not occurred
*/
#define ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_SHIFT)) & ENET_QOS_MTL_RXP_ERROR_CNT_RXPECOVF_MASK)
/*! @} */
/*! @name MTL_RXP_INDIRECT_ACC_CONTROL_STATUS - RXP Indirect Access Control and Status */
/*! @{ */
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK (0x3FFU)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT (0U)
/*! ADDR - FRP Instruction Table Offset Address This field indicates the ADDR of the 32-bit entry in Rx parser instruction table.
*/
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_ADDR_MASK)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK (0x10000U)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT (16U)
/*! WRRDN - Read Write Control When this bit is set to 1 indicates the write operation to the Rx Parser Memory.
* 0b0..Read operation to the Rx Parser Memory
* 0b1..Write operation to the Rx Parser Memory
*/
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_WRRDN_MASK)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK (0x80000000U)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT (31U)
/*! STARTBUSY - FRP Instruction Table Access Busy When this bit is set to 1 by the software then it
* indicates to start the Read/Write operation from/to the Rx Parser Memory.
* 0b1..hardware is busy (Read/Write operation from/to the Rx Parser Memory)
* 0b0..hardware not busy
*/
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_CONTROL_STATUS_STARTBUSY_MASK)
/*! @} */
/*! @name MTL_RXP_INDIRECT_ACC_DATA - RXP Indirect Access Data */
/*! @{ */
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK (0xFFFFFFFFU)
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT (0U)
/*! DATA - FRP Instruction Table Write/Read Data Software should write this register before issuing any write command.
*/
#define ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_SHIFT)) & ENET_QOS_MTL_RXP_INDIRECT_ACC_DATA_DATA_MASK)
/*! @} */
/*! @name MTL_TXQX_OP_MODE - Queue 0 Transmit Operation Mode..Queue 4 Transmit Operation Mode */
/*! @{ */
#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
/*! FTQ - Flush Transmit Queue When this bit is set, the Tx queue controller logic is reset to its default values.
* 0b0..Flush Transmit Queue is disabled
* 0b1..Flush Transmit Queue is enabled
*/
#define ENET_QOS_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_FTQ_MASK)
#define ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
#define ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
/*! TSF - Transmit Store and Forward When this bit is set, the transmission starts when a full packet resides in the MTL Tx queue.
* 0b0..Transmit Store and Forward is disabled
* 0b1..Transmit Store and Forward is enabled
*/
#define ENET_QOS_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TSF_MASK)
#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
/*! TXQEN - Transmit Queue Enable This field is used to enable/disable the transmit queue 0.
* 0b00..Not enabled
* 0b10..Enabled
* 0b01..Enable in AV mode (Reserved in non-AV)
* 0b11..Reserved
*/
#define ENET_QOS_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TXQEN_MASK)
#define ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
#define ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
/*! TTC - Transmit Threshold Control These bits control the threshold level of the MTL Tx Queue.
* 0b011..128
* 0b100..192
* 0b101..256
* 0b000..32
* 0b110..384
* 0b111..512
* 0b001..64
* 0b010..96
*/
#define ENET_QOS_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TTC_MASK)
#define ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK (0x1F0000U)
#define ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
/*! TQS - Transmit Queue Size This field indicates the size of the allocated Transmit queues in blocks of 256 bytes.
*/
#define ENET_QOS_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_QOS_MTL_TXQX_OP_MODE_TQS_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_OP_MODE */
#define ENET_QOS_MTL_TXQX_OP_MODE_COUNT (5U)
/*! @name MTL_TXQX_UNDRFLW - Queue 0 Underflow Counter..Queue 4 Underflow Counter */
/*! @{ */
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
/*! UFFRMCNT - Underflow Packet Counter This field indicates the number of packets aborted by the
* controller because of Tx Queue Underflow.
*/
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
/*! UFCNTOVF - Overflow Bit for Underflow Packet Counter This bit is set every time the Tx queue
* Underflow Packet Counter field overflows, that is, it has crossed the maximum count.
* 0b1..Overflow detected for Underflow Packet Counter
* 0b0..Overflow not detected for Underflow Packet Counter
*/
#define ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_QOS_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_UNDRFLW */
#define ENET_QOS_MTL_TXQX_UNDRFLW_COUNT (5U)
/*! @name MTL_TXQX_DBG - Queue 0 Transmit Debug..Queue 4 Transmit Debug */
/*! @{ */
#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
/*! TXQPAUSED - Transmit Queue in Pause When this bit is high and the Rx flow control is enabled, it
* indicates that the Tx Queue is in the Pause condition (in the full-duplex only mode) because
* of the following: - Reception of the PFC packet for the priorities assigned to the Tx Queue
* when PFC is enabled - Reception of 802.
* 0b1..Transmit Queue in Pause status is detected
* 0b0..Transmit Queue in Pause status is not detected
*/
#define ENET_QOS_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQPAUSED_MASK)
#define ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)
#define ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
/*! TRCSTS - MTL Tx Queue Read Controller Status This field indicates the state of the Tx Queue Read Controller:
* 0b11..Flushing the Tx queue because of the Packet Abort request from the MAC
* 0b00..Idle state
* 0b01..Read state (transferring data to the MAC transmitter)
* 0b10..Waiting for pending Tx Status from the MAC transmitter
*/
#define ENET_QOS_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TRCSTS_MASK)
#define ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)
#define ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
/*! TWCSTS - MTL Tx Queue Write Controller Status When high, this bit indicates that the MTL Tx
* Queue Write Controller is active, and it is transferring the data to the Tx Queue.
* 0b1..MTL Tx Queue Write Controller status is detected
* 0b0..MTL Tx Queue Write Controller status is not detected
*/
#define ENET_QOS_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TWCSTS_MASK)
#define ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)
#define ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
/*! TXQSTS - MTL Tx Queue Not Empty Status When this bit is high, it indicates that the MTL Tx Queue
* is not empty and some data is left for transmission.
* 0b1..MTL Tx Queue Not Empty status is detected
* 0b0..MTL Tx Queue Not Empty status is not detected
*/
#define ENET_QOS_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXQSTS_MASK)
#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
/*! TXSTSFSTS - MTL Tx Status FIFO Full Status When high, this bit indicates that the MTL Tx Status FIFO is full.
* 0b1..MTL Tx Status FIFO Full status is detected
* 0b0..MTL Tx Status FIFO Full status is not detected
*/
#define ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_TXSTSFSTS_MASK)
#define ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)
#define ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT (16U)
/*! PTXQ - Number of Packets in the Transmit Queue This field indicates the current number of packets in the Tx Queue.
*/
#define ENET_QOS_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_PTXQ_MASK)
#define ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK (0x700000U)
#define ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT (20U)
/*! STXSTSF - Number of Status Words in Tx Status FIFO of Queue This field indicates the current
* number of status in the Tx Status FIFO of this queue.
*/
#define ENET_QOS_MTL_TXQX_DBG_STXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_DBG_STXSTSF_SHIFT)) & ENET_QOS_MTL_TXQX_DBG_STXSTSF_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_DBG */
#define ENET_QOS_MTL_TXQX_DBG_COUNT (5U)
/*! @name MTL_TXQX_ETS_CTRL - Queue 1 ETS Control..Queue 4 ETS Control */
/*! @{ */
#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
/*! AVALG - AV Algorithm When Queue 1 is programmed for AV, this field configures the scheduling
* algorithm for this queue: This bit when set, indicates credit based shaper algorithm (CBS) is
* selected for Queue 1 traffic.
* 0b0..CBS Algorithm is disabled
* 0b1..CBS Algorithm is enabled
*/
#define ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_AVALG_MASK)
#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
/*! CC - Credit Control When this bit is set, the accumulated credit parameter in the credit-based
* shaper algorithm logic is not reset to zero when there is positive credit and no packet to
* transmit in Channel 1.
* 0b0..Credit Control is disabled
* 0b1..Credit Control is enabled
*/
#define ENET_QOS_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_CC_MASK)
#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
/*! SLC - Slot Count If the credit-based shaper algorithm is enabled, the software can program the
* number of slots (of duration programmed in DMA_CH[n]_Slot_Interval register) over which the
* average transmitted bits per slot, provided in the MTL_TXQ[N]_ETS_STATUS register, need to be
* computed for Queue.
* 0b100..16 slots
* 0b000..1 slot
* 0b001..2 slots
* 0b010..4 slots
* 0b011..8 slots
* 0b101..Reserved
*/
#define ENET_QOS_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_CTRL_SLC_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_ETS_CTRL */
#define ENET_QOS_MTL_TXQX_ETS_CTRL_COUNT (5U)
/*! @name MTL_TXQX_ETS_STAT - Queue 0 ETS Status..Queue 4 ETS Status */
/*! @{ */
#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
/*! ABS - Average Bits per Slot This field contains the average transmitted bits per slot.
*/
#define ENET_QOS_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_QOS_MTL_TXQX_ETS_STAT_ABS_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_ETS_STAT */
#define ENET_QOS_MTL_TXQX_ETS_STAT_COUNT (5U)
/*! @name MTL_TXQX_QNTM_WGHT - Queue 0 Quantum or Weights..Queue 4 idleSlopeCredit, Quantum or Weights */
/*! @{ */
#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
/*! ISCQW - Quantum or Weights When the DCB operation is enabled with DWRR algorithm for Queue 0
* traffic, this field contains the quantum value in bytes to be added to credit during every queue
* scanning cycle.
*/
#define ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_QOS_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_QNTM_WGHT */
#define ENET_QOS_MTL_TXQX_QNTM_WGHT_COUNT (5U)
/*! @name MTL_TXQX_SNDSLP_CRDT - Queue 1 sendSlopeCredit..Queue 4 sendSlopeCredit */
/*! @{ */
#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
/*! SSC - sendSlopeCredit Value When AV operation is enabled, this field contains the
* sendSlopeCredit value required for credit-based shaper algorithm for Queue 1.
*/
#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_QOS_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_SNDSLP_CRDT */
#define ENET_QOS_MTL_TXQX_SNDSLP_CRDT_COUNT (5U)
/*! @name MTL_TXQX_HI_CRDT - Queue 1 hiCredit..Queue 4 hiCredit */
/*! @{ */
#define ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)
#define ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
/*! HC - hiCredit Value When the AV feature is enabled, this field contains the hiCredit value
* required for the credit-based shaper algorithm.
*/
#define ENET_QOS_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_QOS_MTL_TXQX_HI_CRDT_HC_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_HI_CRDT */
#define ENET_QOS_MTL_TXQX_HI_CRDT_COUNT (5U)
/*! @name MTL_TXQX_LO_CRDT - Queue 1 loCredit..Queue 4 loCredit */
/*! @{ */
#define ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)
#define ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
/*! LC - loCredit Value When AV operation is enabled, this field contains the loCredit value
* required for the credit-based shaper algorithm.
*/
#define ENET_QOS_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_QOS_MTL_TXQX_LO_CRDT_LC_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_LO_CRDT */
#define ENET_QOS_MTL_TXQX_LO_CRDT_COUNT (5U)
/*! @name MTL_TXQX_INTCTRL_STAT - Queue 0 Interrupt Control Status..Queue 4 Interrupt Control Status */
/*! @{ */
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
/*! TXUNFIS - Transmit Queue Underflow Interrupt Status This bit indicates that the Transmit Queue
* had an underflow while transmitting the packet.
* 0b1..Transmit Queue Underflow Interrupt Status detected
* 0b0..Transmit Queue Underflow Interrupt Status not detected
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
/*! ABPSIS - Average Bits Per Slot Interrupt Status When set, this bit indicates that the MAC has updated the ABS value.
* 0b1..Average Bits Per Slot Interrupt Status detected
* 0b0..Average Bits Per Slot Interrupt Status not detected
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
/*! TXUIE - Transmit Queue Underflow Interrupt Enable When this bit is set, the Transmit Queue Underflow interrupt is enabled.
* 0b0..Transmit Queue Underflow Interrupt Status is disabled
* 0b1..Transmit Queue Underflow Interrupt Status is enabled
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
/*! ABPSIE - Average Bits Per Slot Interrupt Enable When this bit is set, the MAC asserts the
* sbd_intr_o or mci_intr_o interrupt when the average bits per slot status is updated.
* 0b0..Average Bits Per Slot Interrupt is disabled
* 0b1..Average Bits Per Slot Interrupt is enabled
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
/*! RXOVFIS - Receive Queue Overflow Interrupt Status This bit indicates that the Receive Queue had
* an overflow while receiving the packet.
* 0b1..Receive Queue Overflow Interrupt Status detected
* 0b0..Receive Queue Overflow Interrupt Status not detected
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
/*! RXOIE - Receive Queue Overflow Interrupt Enable When this bit is set, the Receive Queue Overflow interrupt is enabled.
* 0b0..Receive Queue Overflow Interrupt is disabled
* 0b1..Receive Queue Overflow Interrupt is enabled
*/
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_QOS_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_TXQX_INTCTRL_STAT */
#define ENET_QOS_MTL_TXQX_INTCTRL_STAT_COUNT (5U)
/*! @name MTL_RXQX_OP_MODE - Queue 0 Receive Operation Mode..Queue 4 Receive Operation Mode */
/*! @{ */
#define ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
#define ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
/*! RTC - Receive Queue Threshold Control These bits control the threshold level of the MTL Rx queue
* (in bytes): The received packet is transferred to the application or DMA when the packet size
* within the MTL Rx queue is larger than the threshold.
* 0b11..128
* 0b01..32
* 0b00..64
* 0b10..96
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RTC_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
#define ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
/*! FUP - Forward Undersized Good Packets When this bit is set, the Rx queue forwards the undersized
* good packets (packets with no error and length less than 64 bytes), including pad-bytes and
* CRC.
* 0b0..Forward Undersized Good Packets is disabled
* 0b1..Forward Undersized Good Packets is enabled
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FUP_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
#define ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
/*! FEP - Forward Error Packets When this bit is reset, the Rx queue drops packets with error status
* (CRC error, GMII_ER, watchdog timeout, or overflow).
* 0b0..Forward Error Packets is disabled
* 0b1..Forward Error Packets is enabled
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_FEP_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
#define ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
/*! RSF - Receive Queue Store and Forward When this bit is set, the DWC_ether_qos reads a packet
* from the Rx queue only after the complete packet has been written to it, ignoring the RTC field
* of this register.
* 0b0..Receive Queue Store and Forward is disabled
* 0b1..Receive Queue Store and Forward is enabled
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RSF_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
/*! DIS_TCP_EF - Disable Dropping of TCP/IP Checksum Error Packets When this bit is set, the MAC
* does not drop the packets which only have the errors detected by the Receive Checksum Offload
* engine.
* 0b1..Dropping of TCP/IP Checksum Error Packets is disabled
* 0b0..Dropping of TCP/IP Checksum Error Packets is enabled
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK (0x80U)
#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT (7U)
/*! EHFC - Enable Hardware Flow Control When this bit is set, the flow control signal operation,
* based on the fill-level of Rx queue, is enabled.
* 0b0..Hardware Flow Control is disabled
* 0b1..Hardware Flow Control is enabled
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_EHFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_EHFC_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_EHFC_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK (0xF00U)
#define ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT (8U)
/*! RFA - Threshold for Activating Flow Control (in half-duplex and full-duplex These bits control
* the threshold (fill-level of Rx queue) at which the flow control is activated: For more
* information on encoding for this field, see RFD.
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_RFA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFA_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFA_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK (0x3C000U)
#define ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT (14U)
/*! RFD - Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) These bits
* control the threshold (fill-level of Rx queue) at which the flow control is de-asserted after
* activation: - 0: Full minus 1 KB, that is, FULL 1 KB - 1: Full minus 1.
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_RFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RFD_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RFD_MASK)
#define ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK (0x1F00000U)
#define ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
/*! RQS - Receive Queue Size This field indicates the size of the allocated Receive queues in blocks of 256 bytes.
*/
#define ENET_QOS_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_QOS_MTL_RXQX_OP_MODE_RQS_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_RXQX_OP_MODE */
#define ENET_QOS_MTL_RXQX_OP_MODE_COUNT (5U)
/*! @name MTL_RXQX_MISSPKT_OVRFLW_CNT - Queue 0 Missed Packet and Overflow Counter..Queue 4 Missed Packet and Overflow Counter */
/*! @{ */
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
/*! OVFPKTCNT - Overflow Packet Counter This field indicates the number of packets discarded by the
* DWC_ether_qos because of Receive queue overflow.
*/
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
/*! OVFCNTOVF - Overflow Counter Overflow Bit When set, this bit indicates that the Rx Queue
* Overflow Packet Counter field crossed the maximum limit.
* 0b1..Overflow Counter overflow detected
* 0b0..Overflow Counter overflow not detected
*/
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK (0x7FF0000U)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT (16U)
/*! MISPKTCNT - Missed Packet Counter This field indicates the number of packets missed by the
* DWC_ether_qos because the application asserted ari_pkt_flush_i[] for this queue.
*/
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISPKTCNT_MASK)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK (0x8000000U)
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT (27U)
/*! MISCNTOVF - Missed Packet Counter Overflow Bit When set, this bit indicates that the Rx Queue
* Missed Packet Counter crossed the maximum limit.
* 0b1..Missed Packet Counter overflow detected
* 0b0..Missed Packet Counter overflow not detected
*/
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_SHIFT)) & ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_MISCNTOVF_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT */
#define ENET_QOS_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (5U)
/*! @name MTL_RXQX_DBG - Queue 0 Receive Debug..Queue 4 Receive Debug */
/*! @{ */
#define ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)
#define ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
/*! RWCSTS - MTL Rx Queue Write Controller Active Status When high, this bit indicates that the MTL
* Rx queue Write controller is active, and it is transferring a received packet to the Rx Queue.
* 0b1..MTL Rx Queue Write Controller Active Status detected
* 0b0..MTL Rx Queue Write Controller Active Status not detected
*/
#define ENET_QOS_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RWCSTS_MASK)
#define ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)
#define ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
/*! RRCSTS - MTL Rx Queue Read Controller State This field gives the state of the Rx queue Read controller:
* 0b11..Flushing the packet data and status
* 0b00..Idle state
* 0b01..Reading packet data
* 0b10..Reading packet status (or timestamp)
*/
#define ENET_QOS_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RRCSTS_MASK)
#define ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)
#define ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
/*! RXQSTS - MTL Rx Queue Fill-Level Status This field gives the status of the fill-level of the Rx Queue:
* 0b10..Rx Queue fill-level above flow-control activate threshold
* 0b01..Rx Queue fill-level below flow-control deactivate threshold
* 0b00..Rx Queue empty
* 0b11..Rx Queue full
*/
#define ENET_QOS_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_RXQSTS_MASK)
#define ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)
#define ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT (16U)
/*! PRXQ - Number of Packets in Receive Queue This field indicates the current number of packets in the Rx Queue.
*/
#define ENET_QOS_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_QOS_MTL_RXQX_DBG_PRXQ_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_RXQX_DBG */
#define ENET_QOS_MTL_RXQX_DBG_COUNT (5U)
/*! @name MTL_RXQX_CTRL - Queue 0 Receive Control..Queue 4 Receive Control */
/*! @{ */
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
/*! RXQ_WEGT - Receive Queue Weight This field indicates the weight assigned to the Rx Queue 0.
*/
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
/*! RXQ_FRM_ARBIT - Receive Queue Packet Arbitration When this bit is set, the DWC_ether_qos drives
* the packet data to the ARI interface such that the entire packet data of currently-selected
* queue is transmitted before switching to other queue.
* 0b0..Receive Queue Packet Arbitration is disabled
* 0b1..Receive Queue Packet Arbitration is enabled
*/
#define ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_QOS_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
/*! @} */
/* The count of ENET_QOS_MTL_RXQX_CTRL */
#define ENET_QOS_MTL_RXQX_CTRL_COUNT (5U)
/*! @name DMA_MODE - DMA Bus Mode */
/*! @{ */
#define ENET_QOS_DMA_MODE_SWR_MASK (0x1U)
#define ENET_QOS_DMA_MODE_SWR_SHIFT (0U)
/*! SWR - Software Reset When this bit is set, the MAC and the DMA controller reset the logic and
* all internal registers of the DMA, MTL, and MAC.
* 0b0..Software Reset is disabled
* 0b1..Software Reset is enabled
*/
#define ENET_QOS_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_SWR_SHIFT)) & ENET_QOS_DMA_MODE_SWR_MASK)
#define ENET_QOS_DMA_MODE_DSPW_MASK (0x100U)
#define ENET_QOS_DMA_MODE_DSPW_SHIFT (8U)
/*! DSPW - Descriptor Posted Write When this bit is set to 0, the descriptor writes are always non-posted.
* 0b0..Descriptor Posted Write is disabled
* 0b1..Descriptor Posted Write is enabled
*/
#define ENET_QOS_DMA_MODE_DSPW(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_DSPW_SHIFT)) & ENET_QOS_DMA_MODE_DSPW_MASK)
#define ENET_QOS_DMA_MODE_INTM_MASK (0x30000U)
#define ENET_QOS_DMA_MODE_INTM_SHIFT (16U)
/*! INTM - Interrupt Mode This field defines the interrupt mode of DWC_ether_qos.
* 0b00..See above description
* 0b01..See above description
* 0b10..See above description
* 0b11..Reserved
*/
#define ENET_QOS_DMA_MODE_INTM(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_MODE_INTM_SHIFT)) & ENET_QOS_DMA_MODE_INTM_MASK)
/*! @} */
/*! @name DMA_SYSBUS_MODE - DMA System Bus Mode */
/*! @{ */
#define ENET_QOS_DMA_SYSBUS_MODE_FB_MASK (0x1U)
#define ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT (0U)
/*! FB - Fixed Burst Length When this bit is set to 1, the EQOS-AXI master initiates burst transfers
* of specified lengths as given below.
* 0b0..Fixed Burst Length is disabled
* 0b1..Fixed Burst Length is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_FB_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK (0x2U)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT (1U)
/*! BLEN4 - AXI Burst Length 4 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
* master can select a burst length of 4 on the AXI interface.
* 0b0..No effect
* 0b1..AXI Burst Length 4
*/
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN4_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN4_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK (0x4U)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT (2U)
/*! BLEN8 - AXI Burst Length 8 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
* master can select a burst length of 8 on the AXI interface.
* 0b0..No effect
* 0b1..AXI Burst Length 8
*/
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN8(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN8_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN8_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK (0x8U)
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT (3U)
/*! BLEN16 - AXI Burst Length 16 When this bit is set to 1 or the FB bit is set to 0, the EQOS-AXI
* master can select a burst length of 16 on the AXI interface.
* 0b0..No effect
* 0b1..AXI Burst Length 16
*/
#define ENET_QOS_DMA_SYSBUS_MODE_BLEN16(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_BLEN16_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_BLEN16_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK (0x400U)
#define ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT (10U)
/*! AALE - Automatic AXI LPI enable When set to 1, enables the AXI master to enter into LPI state
* when there is no activity in the DWC_ether_qos for number of system clock cycles programmed in
* the LPIEI field of DMA_AXI_LPI_ENTRY_INTERVAL register.
* 0b0..Automatic AXI LPI is disabled
* 0b1..Automatic AXI LPI is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_AALE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AALE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AALE_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)
#define ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
/*! AAL - Address-Aligned Beats When this bit is set to 1, the EQOS-AXI or EQOS-AHB master performs
* address-aligned burst transfers on Read and Write channels.
* 0b0..Address-Aligned Beats is disabled
* 0b1..Address-Aligned Beats is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_AAL_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK (0x2000U)
#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT (13U)
/*! ONEKBBE - 1 KB Boundary Crossing Enable for the EQOS-AXI Master When set, the burst transfers
* performed by the EQOS-AXI master do not cross 1 KB boundary.
* 0b0..1 KB Boundary Crossing for the EQOS-AXI Master Beats is disabled
* 0b1..1 KB Boundary Crossing for the EQOS-AXI Master Beats is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_ONEKBBE_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK (0xF0000U)
#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT (16U)
/*! RD_OSR_LMT - AXI Maximum Read Outstanding Request Limit This value limits the maximum outstanding request on the AXI read interface.
*/
#define ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK (0xF000000U)
#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT (24U)
/*! WR_OSR_LMT - AXI Maximum Write Outstanding Request Limit This value limits the maximum
* outstanding request on the AXI write interface.
*/
#define ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_WR_OSR_LMT_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK (0x40000000U)
#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT (30U)
/*! LPI_XIT_PKT - Unlock on Magic Packet or Remote Wake-Up Packet When set to 1, this bit enables
* the AXI master to come out of the LPI mode only when the magic packet or remote wake-up packet
* is received.
* 0b0..Unlock on Magic Packet or Remote Wake-Up Packet is disabled
* 0b1..Unlock on Magic Packet or Remote Wake-Up Packet is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_LPI_XIT_PKT_MASK)
#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK (0x80000000U)
#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT (31U)
/*! EN_LPI - Enable Low Power Interface (LPI) When set to 1, this bit enables the LPI mode supported
* by the EQOS-AXI configuration and accepts the LPI request from the AXI System Clock
* controller.
* 0b0..Low Power Interface (LPI) is disabled
* 0b1..Low Power Interface (LPI) is enabled
*/
#define ENET_QOS_DMA_SYSBUS_MODE_EN_LPI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_SHIFT)) & ENET_QOS_DMA_SYSBUS_MODE_EN_LPI_MASK)
/*! @} */
/*! @name DMA_INTERRUPT_STATUS - DMA Interrupt Status */
/*! @{ */
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK (0x1U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT (0U)
/*! DC0IS - DMA Channel 0 Interrupt Status This bit indicates an interrupt event in DMA Channel 0.
* 0b1..DMA Channel 0 Interrupt Status detected
* 0b0..DMA Channel 0 Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC0IS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK (0x2U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT (1U)
/*! DC1IS - DMA Channel 1 Interrupt Status This bit indicates an interrupt event in DMA Channel 1.
* 0b1..DMA Channel 1 Interrupt Status detected
* 0b0..DMA Channel 1 Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC1IS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK (0x4U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT (2U)
/*! DC2IS - DMA Channel 2 Interrupt Status This bit indicates an interrupt event in DMA Channel 2.
* 0b1..DMA Channel 2 Interrupt Status detected
* 0b0..DMA Channel 2 Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC2IS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK (0x8U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT (3U)
/*! DC3IS - DMA Channel 3 Interrupt Status This bit indicates an interrupt event in DMA Channel 3.
* 0b1..DMA Channel 3 Interrupt Status detected
* 0b0..DMA Channel 3 Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC3IS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK (0x10U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT (4U)
/*! DC4IS - DMA Channel 4 Interrupt Status This bit indicates an interrupt event in DMA Channel 4.
* 0b1..DMA Channel 4 Interrupt Status detected
* 0b0..DMA Channel 4 Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_DC4IS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK (0x10000U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT (16U)
/*! MTLIS - MTL Interrupt Status This bit indicates an interrupt event in the MTL.
* 0b1..MTL Interrupt Status detected
* 0b0..MTL Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MTLIS_MASK)
#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK (0x20000U)
#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT (17U)
/*! MACIS - MAC Interrupt Status This bit indicates an interrupt event in the MAC.
* 0b1..MAC Interrupt Status detected
* 0b0..MAC Interrupt Status not detected
*/
#define ENET_QOS_DMA_INTERRUPT_STATUS_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_SHIFT)) & ENET_QOS_DMA_INTERRUPT_STATUS_MACIS_MASK)
/*! @} */
/*! @name DMA_DEBUG_STATUS0 - DMA Debug Status 0 */
/*! @{ */
#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK (0x1U)
#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT (0U)
/*! AXWHSTS - AXI Master Write Channel When high, this bit indicates that the write channel of the
* AXI master is active, and it is transferring data.
* 0b1..AXI Master Write Channel or AHB Master Status detected
* 0b0..AXI Master Write Channel or AHB Master Status not detected
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXWHSTS_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK (0x2U)
#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT (1U)
/*! AXRHSTS - AXI Master Read Channel Status When high, this bit indicates that the read channel of
* the AXI master is active, and it is transferring the data.
* 0b1..AXI Master Read Channel Status detected
* 0b0..AXI Master Read Channel Status not detected
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_AXRHSTS_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK (0xF00U)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT (8U)
/*! RPS0 - DMA Channel 0 Receive Process State This field indicates the Rx DMA FSM state for Channel 0.
* 0b0010..Reserved for future use
* 0b0101..Running (Closing the Rx Descriptor)
* 0b0001..Running (Fetching Rx Transfer Descriptor)
* 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
* 0b0011..Running (Waiting for Rx packet)
* 0b0000..Stopped (Reset or Stop Receive Command issued)
* 0b0100..Suspended (Rx Descriptor Unavailable)
* 0b0110..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS0_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK (0xF000U)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT (12U)
/*! TPS0 - DMA Channel 0 Transmit Process State This field indicates the Tx DMA FSM state for Channel 0.
* 0b0101..Reserved for future use
* 0b0111..Running (Closing Tx Descriptor)
* 0b0001..Running (Fetching Tx Transfer Descriptor)
* 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
* 0b0010..Running (Waiting for status)
* 0b0000..Stopped (Reset or Stop Transmit Command issued)
* 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
* 0b0100..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS0_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS0_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK (0xF0000U)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT (16U)
/*! RPS1 - DMA Channel 1 Receive Process State This field indicates the Rx DMA FSM state for Channel 1.
* 0b0010..Reserved for future use
* 0b0101..Running (Closing the Rx Descriptor)
* 0b0001..Running (Fetching Rx Transfer Descriptor)
* 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
* 0b0011..Running (Waiting for Rx packet)
* 0b0000..Stopped (Reset or Stop Receive Command issued)
* 0b0100..Suspended (Rx Descriptor Unavailable)
* 0b0110..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS1_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK (0xF00000U)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT (20U)
/*! TPS1 - DMA Channel 1 Transmit Process State This field indicates the Tx DMA FSM state for Channel 1.
* 0b0101..Reserved for future use
* 0b0111..Running (Closing Tx Descriptor)
* 0b0001..Running (Fetching Tx Transfer Descriptor)
* 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
* 0b0010..Running (Waiting for status)
* 0b0000..Stopped (Reset or Stop Transmit Command issued)
* 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
* 0b0100..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS1_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS1_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK (0xF000000U)
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT (24U)
/*! RPS2 - DMA Channel 2 Receive Process State This field indicates the Rx DMA FSM state for Channel 2.
* 0b0010..Reserved for future use
* 0b0101..Running (Closing the Rx Descriptor)
* 0b0001..Running (Fetching Rx Transfer Descriptor)
* 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
* 0b0011..Running (Waiting for Rx packet)
* 0b0000..Stopped (Reset or Stop Receive Command issued)
* 0b0100..Suspended (Rx Descriptor Unavailable)
* 0b0110..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_RPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_RPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_RPS2_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK (0xF0000000U)
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT (28U)
/*! TPS2 - DMA Channel 2 Transmit Process State This field indicates the Tx DMA FSM state for Channel 2.
* 0b0101..Reserved for future use
* 0b0111..Running (Closing Tx Descriptor)
* 0b0001..Running (Fetching Tx Transfer Descriptor)
* 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
* 0b0010..Running (Waiting for status)
* 0b0000..Stopped (Reset or Stop Transmit Command issued)
* 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
* 0b0100..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS0_TPS2(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS0_TPS2_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS0_TPS2_MASK)
/*! @} */
/*! @name DMA_DEBUG_STATUS1 - DMA Debug Status 1 */
/*! @{ */
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK (0xFU)
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT (0U)
/*! RPS3 - DMA Channel 3 Receive Process State This field indicates the Rx DMA FSM state for Channel 3.
* 0b0010..Reserved for future use
* 0b0101..Running (Closing the Rx Descriptor)
* 0b0001..Running (Fetching Rx Transfer Descriptor)
* 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
* 0b0011..Running (Waiting for Rx packet)
* 0b0000..Stopped (Reset or Stop Receive Command issued)
* 0b0100..Suspended (Rx Descriptor Unavailable)
* 0b0110..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS3_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK (0xF0U)
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT (4U)
/*! TPS3 - DMA Channel 3 Transmit Process State This field indicates the Tx DMA FSM state for Channel 3.
* 0b0101..Reserved for future use
* 0b0111..Running (Closing Tx Descriptor)
* 0b0001..Running (Fetching Tx Transfer Descriptor)
* 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
* 0b0010..Running (Waiting for status)
* 0b0000..Stopped (Reset or Stop Transmit Command issued)
* 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
* 0b0100..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS3(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS3_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS3_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK (0xF00U)
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT (8U)
/*! RPS4 - DMA Channel 4 Receive Process State This field indicates the Rx DMA FSM state for Channel 4.
* 0b0010..Reserved for future use
* 0b0101..Running (Closing the Rx Descriptor)
* 0b0001..Running (Fetching Rx Transfer Descriptor)
* 0b0111..Running (Transferring the received packet data from the Rx buffer to the system memory)
* 0b0011..Running (Waiting for Rx packet)
* 0b0000..Stopped (Reset or Stop Receive Command issued)
* 0b0100..Suspended (Rx Descriptor Unavailable)
* 0b0110..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS1_RPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_RPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_RPS4_MASK)
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK (0xF000U)
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT (12U)
/*! TPS4 - DMA Channel 4 Transmit Process State This field indicates the Tx DMA FSM state for Channel 4.
* 0b0101..Reserved for future use
* 0b0111..Running (Closing Tx Descriptor)
* 0b0001..Running (Fetching Tx Transfer Descriptor)
* 0b0011..Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO))
* 0b0010..Running (Waiting for status)
* 0b0000..Stopped (Reset or Stop Transmit Command issued)
* 0b0110..Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow)
* 0b0100..Timestamp write state
*/
#define ENET_QOS_DMA_DEBUG_STATUS1_TPS4(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_DEBUG_STATUS1_TPS4_SHIFT)) & ENET_QOS_DMA_DEBUG_STATUS1_TPS4_MASK)
/*! @} */
/*! @name DMA_AXI_LPI_ENTRY_INTERVAL - AXI LPI Entry Interval Control */
/*! @{ */
#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK (0xFU)
#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT (0U)
/*! LPIEI - LPI Entry Interval Contains the number of system clock cycles, multiplied by 64, to wait
* for an activity in the DWC_ether_qos to enter into the AXI low power state 0 indicates 64
* clock cycles
*/
#define ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_SHIFT)) & ENET_QOS_DMA_AXI_LPI_ENTRY_INTERVAL_LPIEI_MASK)
/*! @} */
/*! @name DMA_TBS_CTRL - TBS Control */
/*! @{ */
#define ENET_QOS_DMA_TBS_CTRL_FTOV_MASK (0x1U)
#define ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT (0U)
/*! FTOV - Fetch Time Offset Valid When set indicates the FTOS field is valid.
* 0b0..Fetch Time Offset is invalid
* 0b1..Fetch Time Offset is valid
*/
#define ENET_QOS_DMA_TBS_CTRL_FTOV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOV_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOV_MASK)
#define ENET_QOS_DMA_TBS_CTRL_FGOS_MASK (0x70U)
#define ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT (4U)
/*! FGOS - Fetch GSN Offset The number GSN slots that must be deducted from the Launch GSN to compute the Fetch GSN.
*/
#define ENET_QOS_DMA_TBS_CTRL_FGOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FGOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FGOS_MASK)
#define ENET_QOS_DMA_TBS_CTRL_FTOS_MASK (0xFFFFFF00U)
#define ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT (8U)
/*! FTOS - Fetch Time Offset The value in units of 256 nanoseconds, that has to be deducted from the
* Launch time to compute the Fetch Time.
*/
#define ENET_QOS_DMA_TBS_CTRL_FTOS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_TBS_CTRL_FTOS_SHIFT)) & ENET_QOS_DMA_TBS_CTRL_FTOS_MASK)
/*! @} */
/*! @name DMA_CHX_CTRL - DMA Channel 0 Control..DMA Channel 4 Control */
/*! @{ */
#define ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)
#define ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT (16U)
/*! PBLx8 - 8xPBL mode When this bit is set, the PBL value programmed in Bits[21:16] in
* DMA_CH4_TX_CONTROL and Bits[21:16] in DMA_CH4_RX_CONTROL is multiplied by eight times.
* 0b0..8xPBL mode is disabled
* 0b1..8xPBL mode is enabled
*/
#define ENET_QOS_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_PBLx8_MASK)
#define ENET_QOS_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)
#define ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT (18U)
/*! DSL - Descriptor Skip Length This bit specifies the Word, Dword, or Lword number (depending on
* the 32-bit, 64-bit, or 128-bit bus) to skip between two unchained descriptors.
*/
#define ENET_QOS_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_QOS_DMA_CHX_CTRL_DSL_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_CTRL */
#define ENET_QOS_DMA_CHX_CTRL_COUNT (5U)
/*! @name DMA_CHX_TX_CTRL - DMA Channel 0 Transmit Control..DMA Channel 4 Transmit Control */
/*! @{ */
#define ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK (0x1U)
#define ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT (0U)
/*! ST - Start or Stop Transmission Command When this bit is set, transmission is placed in the Running state.
* 0b1..Start Transmission Command
* 0b0..Stop Transmission Command
*/
#define ENET_QOS_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_ST_MASK)
#define ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)
#define ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)
/*! OSF - Operate on Second Packet When this bit is set, it instructs the DMA to process the second
* packet of the Transmit data even before the status for the first packet is obtained.
* 0b0..Operate on Second Packet disabled
* 0b1..Operate on Second Packet enabled
*/
#define ENET_QOS_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_OSF_MASK)
#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK (0x8000U)
#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT (15U)
/*! IPBL - Ignore PBL Requirement When this bit is set, the DMA does not check for PBL number of
* locations in the MTL before initiating a transfer.
* 0b0..Ignore PBL Requirement is disabled
* 0b1..Ignore PBL Requirement is enabled
*/
#define ENET_QOS_DMA_CHX_TX_CTRL_IPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_IPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_IPBL_MASK)
#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)
#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)
/*! TxPBL - Transmit Programmable Burst Length These bits indicate the maximum number of beats to be
* transferred in one DMA block data transfer.
*/
#define ENET_QOS_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_TxPBL_MASK)
#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK (0x10000000U)
#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT (28U)
/*! EDSE - Enhanced Descriptor Enable When this bit is set, the corresponding channel uses Enhanced
* Descriptors that are 32 Bytes for both Normal and Context Descriptors.
* 0b0..Enhanced Descriptor is disabled
* 0b1..Enhanced Descriptor is enabled
*/
#define ENET_QOS_DMA_CHX_TX_CTRL_EDSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TX_CTRL_EDSE_SHIFT)) & ENET_QOS_DMA_CHX_TX_CTRL_EDSE_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_TX_CTRL */
#define ENET_QOS_DMA_CHX_TX_CTRL_COUNT (5U)
/*! @name DMA_CHX_RX_CTRL - DMA Channel 0 Receive Control..DMA Channel 4 Receive Control */
/*! @{ */
#define ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK (0x1U)
#define ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT (0U)
/*! SR - Start or Stop Receive When this bit is set, the DMA tries to acquire the descriptor from
* the Receive list and processes the incoming packets.
* 0b1..Start Receive
* 0b0..Stop Receive
*/
#define ENET_QOS_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_SR_MASK)
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK (0xEU)
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT (1U)
/*! RBSZ_x_0 - Receive Buffer size Low RBSZ[13:0] is split into two fields RBSZ_13_y and RBSZ_x_0.
*/
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_x_0_MASK)
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK (0x7FF0U)
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT (4U)
/*! RBSZ_13_y - Receive Buffer size High RBSZ[13:0] is split into two fields higher RBSZ_13_y and lower RBSZ_x_0.
*/
#define ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RBSZ_13_y_MASK)
#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)
#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)
/*! RxPBL - Receive Programmable Burst Length These bits indicate the maximum number of beats to be
* transferred in one DMA block data transfer.
*/
#define ENET_QOS_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RxPBL_MASK)
#define ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)
#define ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)
/*! RPF - Rx Packet Flush.
* 0b0..Rx Packet Flush is disabled
* 0b1..Rx Packet Flush is enabled
*/
#define ENET_QOS_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_QOS_DMA_CHX_RX_CTRL_RPF_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RX_CTRL */
#define ENET_QOS_DMA_CHX_RX_CTRL_COUNT (5U)
/*! @name DMA_CHX_TXDESC_LIST_ADDR - Channel 0 Tx Descriptor List Address register..Channel 4 Tx Descriptor List Address */
/*! @{ */
#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK (0xFFFFFFF8U)
#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT (3U)
/*! TDESLA - Start of Transmit List This field contains the base address of the first descriptor in the Transmit descriptor list.
*/
#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_TDESLA_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR */
#define ENET_QOS_DMA_CHX_TXDESC_LIST_ADDR_COUNT (5U)
/*! @name DMA_CHX_RXDESC_LIST_ADDR - Channel 0 Rx Descriptor List Address register..Channel 4 Rx Descriptor List Address */
/*! @{ */
#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK (0xFFFFFFF8U)
#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT (3U)
/*! RDESLA - Start of Receive List This field contains the base address of the first descriptor in the Rx Descriptor list.
*/
#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_RDESLA_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR */
#define ENET_QOS_DMA_CHX_RXDESC_LIST_ADDR_COUNT (5U)
/*! @name DMA_CHX_TXDESC_TAIL_PTR - Channel 0 Tx Descriptor Tail Pointer..Channel 4 Tx Descriptor Tail Pointer */
/*! @{ */
#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFF8U)
#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (3U)
/*! TDTP - Transmit Descriptor Tail Pointer This field contains the tail pointer for the Tx descriptor ring.
*/
#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR */
#define ENET_QOS_DMA_CHX_TXDESC_TAIL_PTR_COUNT (5U)
/*! @name DMA_CHX_RXDESC_TAIL_PTR - Channel 0 Rx Descriptor Tail Pointer..Channel 4 Rx Descriptor Tail Pointer */
/*! @{ */
#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFF8U)
#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (3U)
/*! RDTP - Receive Descriptor Tail Pointer This field contains the tail pointer for the Rx descriptor ring.
*/
#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR */
#define ENET_QOS_DMA_CHX_RXDESC_TAIL_PTR_COUNT (5U)
/*! @name DMA_CHX_TXDESC_RING_LENGTH - Channel 0 Tx Descriptor Ring Length..Channel 4 Tx Descriptor Ring Length */
/*! @{ */
#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
/*! TDRL - Transmit Descriptor Ring Length This field sets the maximum number of Tx descriptors in the circular descriptor ring.
*/
#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH */
#define ENET_QOS_DMA_CHX_TXDESC_RING_LENGTH_COUNT (5U)
/*! @name DMA_CHX_RXDESC_RING_LENGTH - Channel 0 Rx Descriptor Ring Length..Channel 4 Rx Descriptor Ring Length */
/*! @{ */
#define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
#define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
/*! RDRL - Receive Descriptor Ring Length This register sets the maximum number of Rx descriptors in the circular descriptor ring.
*/
#define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH */
#define ENET_QOS_DMA_CHX_RXDESC_RING_LENGTH_COUNT (5U)
/*! @name DMA_CHX_INT_EN - Channel 0 Interrupt Enable..Channel 4 Interrupt Enable */
/*! @{ */
#define ENET_QOS_DMA_CHX_INT_EN_TIE_MASK (0x1U)
#define ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT (0U)
/*! TIE - Transmit Interrupt Enable When this bit is set along with the NIE bit, the Transmit Interrupt is enabled.
* 0b0..Transmit Interrupt is disabled
* 0b1..Transmit Interrupt is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TIE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK (0x2U)
#define ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT (1U)
/*! TXSE - Transmit Stopped Enable When this bit is set along with the AIE bit, the Transmission Stopped interrupt is enabled.
* 0b0..Transmit Stopped is disabled
* 0b1..Transmit Stopped is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_TXSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TXSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TXSE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK (0x4U)
#define ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT (2U)
/*! TBUE - Transmit Buffer Unavailable Enable When this bit is set along with the NIE bit, the
* Transmit Buffer Unavailable interrupt is enabled.
* 0b0..Transmit Buffer Unavailable is disabled
* 0b1..Transmit Buffer Unavailable is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_TBUE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_RIE_MASK (0x40U)
#define ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT (6U)
/*! RIE - Receive Interrupt Enable When this bit is set along with the NIE bit, the Receive Interrupt is enabled.
* 0b0..Receive Interrupt is disabled
* 0b1..Receive Interrupt is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RIE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK (0x80U)
#define ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT (7U)
/*! RBUE - Receive Buffer Unavailable Enable When this bit is set along with the AIE bit, the
* Receive Buffer Unavailable interrupt is enabled.
* 0b0..Receive Buffer Unavailable is disabled
* 0b1..Receive Buffer Unavailable is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RBUE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_RSE_MASK (0x100U)
#define ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT (8U)
/*! RSE - Receive Stopped Enable When this bit is set along with the AIE bit, the Receive Stopped Interrupt is enabled.
* 0b0..Receive Stopped is disabled
* 0b1..Receive Stopped is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RSE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK (0x200U)
#define ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT (9U)
/*! RWTE - Receive Watchdog Timeout Enable When this bit is set along with the AIE bit, the Receive
* Watchdog Timeout interrupt is enabled.
* 0b0..Receive Watchdog Timeout is disabled
* 0b1..Receive Watchdog Timeout is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_RWTE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK (0x400U)
#define ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT (10U)
/*! ETIE - Early Transmit Interrupt Enable When this bit is set along with the AIE bit, the Early Transmit interrupt is enabled.
* 0b0..Early Transmit Interrupt is disabled
* 0b1..Early Transmit Interrupt is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ETIE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK (0x800U)
#define ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT (11U)
/*! ERIE - Early Receive Interrupt Enable When this bit is set along with the NIE bit, the Early Receive interrupt is enabled.
* 0b0..Early Receive Interrupt is disabled
* 0b1..Early Receive Interrupt is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_ERIE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)
#define ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT (12U)
/*! FBEE - Fatal Bus Error Enable When this bit is set along with the AIE bit, the Fatal Bus error interrupt is enabled.
* 0b0..Fatal Bus Error is disabled
* 0b1..Fatal Bus Error is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_FBEE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK (0x2000U)
#define ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT (13U)
/*! CDEE - Context Descriptor Error Enable When this bit is set along with the AIE bit, the Descriptor error interrupt is enabled.
* 0b0..Context Descriptor Error is disabled
* 0b1..Context Descriptor Error is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_CDEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_CDEE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_CDEE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_AIE_MASK (0x4000U)
#define ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT (14U)
/*! AIE - Abnormal Interrupt Summary Enable When this bit is set, the abnormal interrupt summary is enabled.
* 0b0..Abnormal Interrupt Summary is disabled
* 0b1..Abnormal Interrupt Summary is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_AIE_MASK)
#define ENET_QOS_DMA_CHX_INT_EN_NIE_MASK (0x8000U)
#define ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT (15U)
/*! NIE - Normal Interrupt Summary Enable When this bit is set, the normal interrupt summary is enabled.
* 0b0..Normal Interrupt Summary is disabled
* 0b1..Normal Interrupt Summary is enabled
*/
#define ENET_QOS_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_QOS_DMA_CHX_INT_EN_NIE_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_INT_EN */
#define ENET_QOS_DMA_CHX_INT_EN_COUNT (5U)
/*! @name DMA_CHX_RX_INT_WDTIMER - Channel 0 Receive Interrupt Watchdog Timer..Channel 4 Receive Interrupt Watchdog Timer */
/*! @{ */
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK (0xFFU)
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT (0U)
/*! RWT - Receive Interrupt Watchdog Timer Count This field indicates the number of system clock
* cycles, multiplied by factor indicated in RWTU field, for which the watchdog timer is set.
*/
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWT_MASK)
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK (0x30000U)
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT (16U)
/*! RWTU - Receive Interrupt Watchdog Timer Count Units This fields indicates the number of system
* clock cycles corresponding to one unit in RWT field.
*/
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_SHIFT)) & ENET_QOS_DMA_CHX_RX_INT_WDTIMER_RWTU_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RX_INT_WDTIMER */
#define ENET_QOS_DMA_CHX_RX_INT_WDTIMER_COUNT (5U)
/*! @name DMA_CHX_SLOT_FUNC_CTRL_STAT - Channel 0 Slot Function Control and Status..Channel 4 Slot Function Control and Status */
/*! @{ */
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
/*! ESC - Enable Slot Comparison When set, this bit enables the checking of the slot numbers
* programmed in the Tx descriptor with the current reference given in the RSN field.
* 0b0..Slot Comparison is disabled
* 0b1..Slot Comparison is enabled
*/
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
/*! ASC - Advance Slot Check When set, this bit enables the DMA to fetch the data from the buffer
* when the slot number (SLOTNUM) programmed in the Tx descriptor is - equal to the reference slot
* number given in the RSN field or - ahead of the reference slot number by up to two slots This
* bit is applicable only when the ESC bit is set.
* 0b0..Advance Slot Check is disabled
* 0b1..Advance Slot Check is enabled
*/
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK (0xFFF0U)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT (4U)
/*! SIV - Slot Interval Value This field controls the period of the slot interval in which the TxDMA
* fetches the scheduled packets.
*/
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_SIV_MASK)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
/*! RSN - Reference Slot Number This field gives the current value of the reference slot number in the DMA.
*/
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT */
#define ENET_QOS_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (5U)
/*! @name DMA_CHX_CUR_HST_TXDESC - Channel 0 Current Application Transmit Descriptor..Channel 4 Current Application Transmit Descriptor */
/*! @{ */
#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK (0xFFFFFFFFU)
#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT (0U)
/*! CURTDESAPTR - Application Transmit Descriptor Address Pointer The DMA updates this pointer during Tx operation.
*/
#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXDESC_CURTDESAPTR_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_CUR_HST_TXDESC */
#define ENET_QOS_DMA_CHX_CUR_HST_TXDESC_COUNT (5U)
/*! @name DMA_CHX_CUR_HST_RXDESC - Channel 0 Current Application Receive Descriptor..Channel 4 Current Application Receive Descriptor */
/*! @{ */
#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK (0xFFFFFFFFU)
#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT (0U)
/*! CURRDESAPTR - Application Receive Descriptor Address Pointer The DMA updates this pointer during Rx operation.
*/
#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXDESC_CURRDESAPTR_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_CUR_HST_RXDESC */
#define ENET_QOS_DMA_CHX_CUR_HST_RXDESC_COUNT (5U)
/*! @name DMA_CHX_CUR_HST_TXBUF - Channel 0 Current Application Transmit Buffer Address..Channel 4 Current Application Transmit Buffer Address */
/*! @{ */
#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK (0xFFFFFFFFU)
#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT (0U)
/*! CURTBUFAPTR - Application Transmit Buffer Address Pointer The DMA updates this pointer during Tx operation.
*/
#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_TXBUF_CURTBUFAPTR_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_CUR_HST_TXBUF */
#define ENET_QOS_DMA_CHX_CUR_HST_TXBUF_COUNT (5U)
/*! @name DMA_CHX_CUR_HST_RXBUF - Channel 0 Current Application Receive Buffer Address..Channel 4 Current Application Receive Buffer Address */
/*! @{ */
#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK (0xFFFFFFFFU)
#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT (0U)
/*! CURRBUFAPTR - Application Receive Buffer Address Pointer The DMA updates this pointer during Rx operation.
*/
#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_SHIFT)) & ENET_QOS_DMA_CHX_CUR_HST_RXBUF_CURRBUFAPTR_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_CUR_HST_RXBUF */
#define ENET_QOS_DMA_CHX_CUR_HST_RXBUF_COUNT (5U)
/*! @name DMA_CHX_STAT - DMA Channel 0 Status..DMA Channel 4 Status */
/*! @{ */
#define ENET_QOS_DMA_CHX_STAT_TI_MASK (0x1U)
#define ENET_QOS_DMA_CHX_STAT_TI_SHIFT (0U)
/*! TI - Transmit Interrupt This bit indicates that the packet transmission is complete.
* 0b1..Transmit Interrupt status detected
* 0b0..Transmit Interrupt status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TI_MASK)
#define ENET_QOS_DMA_CHX_STAT_TPS_MASK (0x2U)
#define ENET_QOS_DMA_CHX_STAT_TPS_SHIFT (1U)
/*! TPS - Transmit Process Stopped This bit is set when the transmission is stopped.
* 0b1..Transmit Process Stopped status detected
* 0b0..Transmit Process Stopped status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TPS_MASK)
#define ENET_QOS_DMA_CHX_STAT_TBU_MASK (0x4U)
#define ENET_QOS_DMA_CHX_STAT_TBU_SHIFT (2U)
/*! TBU - Transmit Buffer Unavailable This bit indicates that the application owns the next
* descriptor in the Transmit list, and the DMA cannot acquire it.
* 0b1..Transmit Buffer Unavailable status detected
* 0b0..Transmit Buffer Unavailable status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TBU_MASK)
#define ENET_QOS_DMA_CHX_STAT_RI_MASK (0x40U)
#define ENET_QOS_DMA_CHX_STAT_RI_SHIFT (6U)
/*! RI - Receive Interrupt This bit indicates that the packet reception is complete.
* 0b1..Receive Interrupt status detected
* 0b0..Receive Interrupt status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RI_MASK)
#define ENET_QOS_DMA_CHX_STAT_RBU_MASK (0x80U)
#define ENET_QOS_DMA_CHX_STAT_RBU_SHIFT (7U)
/*! RBU - Receive Buffer Unavailable This bit indicates that the application owns the next
* descriptor in the Receive list, and the DMA cannot acquire it.
* 0b1..Receive Buffer Unavailable status detected
* 0b0..Receive Buffer Unavailable status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RBU_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RBU_MASK)
#define ENET_QOS_DMA_CHX_STAT_RPS_MASK (0x100U)
#define ENET_QOS_DMA_CHX_STAT_RPS_SHIFT (8U)
/*! RPS - Receive Process Stopped This bit is asserted when the Rx process enters the Stopped state.
* 0b1..Receive Process Stopped status detected
* 0b0..Receive Process Stopped status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RPS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RPS_MASK)
#define ENET_QOS_DMA_CHX_STAT_RWT_MASK (0x200U)
#define ENET_QOS_DMA_CHX_STAT_RWT_SHIFT (9U)
/*! RWT - Receive Watchdog Timeout This bit is asserted when a packet with length greater than 2,048
* bytes (10,240 bytes when Jumbo Packet mode is enabled) is received.
* 0b1..Receive Watchdog Timeout status detected
* 0b0..Receive Watchdog Timeout status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_RWT_SHIFT)) & ENET_QOS_DMA_CHX_STAT_RWT_MASK)
#define ENET_QOS_DMA_CHX_STAT_ETI_MASK (0x400U)
#define ENET_QOS_DMA_CHX_STAT_ETI_SHIFT (10U)
/*! ETI - Early Transmit Interrupt This bit when set indicates that the TxDMA has completed the
* transfer of packet data to the MTL TXFIFO memory.
* 0b1..Early Transmit Interrupt status detected
* 0b0..Early Transmit Interrupt status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ETI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ETI_MASK)
#define ENET_QOS_DMA_CHX_STAT_ERI_MASK (0x800U)
#define ENET_QOS_DMA_CHX_STAT_ERI_SHIFT (11U)
/*! ERI - Early Receive Interrupt This bit when set indicates that the RxDMA has completed the
* transfer of packet data to the memory.
* 0b1..Early Receive Interrupt status detected
* 0b0..Early Receive Interrupt status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_ERI_SHIFT)) & ENET_QOS_DMA_CHX_STAT_ERI_MASK)
#define ENET_QOS_DMA_CHX_STAT_FBE_MASK (0x1000U)
#define ENET_QOS_DMA_CHX_STAT_FBE_SHIFT (12U)
/*! FBE - Fatal Bus Error This bit indicates that a bus error occurred (as described in the EB field).
* 0b1..Fatal Bus Error status detected
* 0b0..Fatal Bus Error status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_FBE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_FBE_MASK)
#define ENET_QOS_DMA_CHX_STAT_CDE_MASK (0x2000U)
#define ENET_QOS_DMA_CHX_STAT_CDE_SHIFT (13U)
/*! CDE - Context Descriptor Error This bit indicates that the DMA Tx/Rx engine received a
* descriptor error, which indicates invalid context in the middle of packet flow ( intermediate
* descriptor) or all one's descriptor in Tx case and on Rx side it indicates DMA has read a descriptor
* with either of the buffer address as ones which is considered to be invalid.
* 0b1..Context Descriptor Error status detected
* 0b0..Context Descriptor Error status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_CDE(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_CDE_SHIFT)) & ENET_QOS_DMA_CHX_STAT_CDE_MASK)
#define ENET_QOS_DMA_CHX_STAT_AIS_MASK (0x4000U)
#define ENET_QOS_DMA_CHX_STAT_AIS_SHIFT (14U)
/*! AIS - Abnormal Interrupt Summary Abnormal Interrupt Summary bit value is the logical OR of the
* following when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
* register: - Bit 1: Transmit Process Stopped - Bit 7: Receive Buffer Unavailable - Bit 8: Receive
* Process Stopped - Bit 10: Early Transmit Interrupt - Bit 12: Fatal Bus Error - Bit 13: Context
* Descriptor Error Only unmasked bits affect the Abnormal Interrupt Summary bit.
* 0b1..Abnormal Interrupt Summary status detected
* 0b0..Abnormal Interrupt Summary status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_AIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_AIS_MASK)
#define ENET_QOS_DMA_CHX_STAT_NIS_MASK (0x8000U)
#define ENET_QOS_DMA_CHX_STAT_NIS_SHIFT (15U)
/*! NIS - Normal Interrupt Summary Normal Interrupt Summary bit value is the logical OR of the
* following bits when the corresponding interrupt bits are enabled in the DMA_CH3_INTERRUPT_ENABLE
* register: - Bit 0: Transmit Interrupt - Bit 2: Transmit Buffer Unavailable - Bit 6: Receive
* Interrupt - Bit 11: Early Receive Interrupt Only unmasked bits (interrupts for which interrupt
* enable is set in DMA_CH3_INTERRUPT_ENABLE register) affect the Normal Interrupt Summary bit.
* 0b1..Normal Interrupt Summary status detected
* 0b0..Normal Interrupt Summary status not detected
*/
#define ENET_QOS_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_NIS_SHIFT)) & ENET_QOS_DMA_CHX_STAT_NIS_MASK)
#define ENET_QOS_DMA_CHX_STAT_TEB_MASK (0x70000U)
#define ENET_QOS_DMA_CHX_STAT_TEB_SHIFT (16U)
/*! TEB - Tx DMA Error Bits This field indicates the type of error that caused a Bus Error.
*/
#define ENET_QOS_DMA_CHX_STAT_TEB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_TEB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_TEB_MASK)
#define ENET_QOS_DMA_CHX_STAT_REB_MASK (0x380000U)
#define ENET_QOS_DMA_CHX_STAT_REB_SHIFT (19U)
/*! REB - Rx DMA Error Bits This field indicates the type of error that caused a Bus Error.
*/
#define ENET_QOS_DMA_CHX_STAT_REB(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_STAT_REB_SHIFT)) & ENET_QOS_DMA_CHX_STAT_REB_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_STAT */
#define ENET_QOS_DMA_CHX_STAT_COUNT (5U)
/*! @name DMA_CHX_MISS_FRAME_CNT - Channel 0 Missed Frame Counter..Channel 4 Missed Frame Counter */
/*! @{ */
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK (0x7FFU)
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT (0U)
/*! MFC - Dropped Packet Counters This counter indicates the number of packet counters that are
* dropped by the DMA either because of bus error or because of programming RPF field in
* DMA_CH2_RX_CONTROL register.
*/
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFC_MASK)
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK (0x8000U)
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT (15U)
/*! MFCO - Overflow status of the MFC Counter When this bit is set then the MFC counter does not get incremented further.
* 0b1..Miss Frame Counter overflow occurred
* 0b0..Miss Frame Counter overflow not occurred
*/
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_SHIFT)) & ENET_QOS_DMA_CHX_MISS_FRAME_CNT_MFCO_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_MISS_FRAME_CNT */
#define ENET_QOS_DMA_CHX_MISS_FRAME_CNT_COUNT (5U)
/*! @name DMA_CHX_RXP_ACCEPT_CNT - Channel 0 RXP Frames Accepted Counter..Channel 4 RXP Frames Accepted Counter */
/*! @{ */
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK (0x7FFFFFFFU)
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT (0U)
/*! RXPAC - Rx Parser Accept Counter This 31-bit counter is implemented whenever a Rx Parser Accept a packet due to AF =1.
*/
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPAC_MASK)
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK (0x80000000U)
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT (31U)
/*! RXPACOF - Rx Parser Accept Counter Overflow Bit When set, this bit indicates that the RXPAC
* Counter field crossed the maximum limit.
* 0b1..Rx Parser Accept Counter overflow occurred
* 0b0..Rx Parser Accept Counter overflow not occurred
*/
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_SHIFT)) & ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_RXPACOF_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT */
#define ENET_QOS_DMA_CHX_RXP_ACCEPT_CNT_COUNT (5U)
/*! @name DMA_CHX_RX_ERI_CNT - Channel 0 Receive ERI Counter..Channel 4 Receive ERI Counter */
/*! @{ */
#define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK (0xFFFU)
#define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT (0U)
/*! ECNT - ERI Counter When ERIC bit of DMA_CH4_RX_CONTROL register is set, this counter increments
* for burst transfer completed by the Rx DMA from the start of packet transfer.
*/
#define ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_SHIFT)) & ENET_QOS_DMA_CHX_RX_ERI_CNT_ECNT_MASK)
/*! @} */
/* The count of ENET_QOS_DMA_CHX_RX_ERI_CNT */
#define ENET_QOS_DMA_CHX_RX_ERI_CNT_COUNT (5U)
/*!
* @}
*/ /* end of group ENET_QOS_Register_Masks */
/* ENET_QOS - Peripheral instance base addresses */
/** Peripheral ENET_QOS base address */
#define ENET_QOS_BASE (0x4043C000u)
/** Peripheral ENET_QOS base pointer */
#define ENET_QOS ((ENET_QOS_Type *)ENET_QOS_BASE)
/** Array initializer of ENET_QOS peripheral base addresses */
#define ENET_QOS_BASE_ADDRS { ENET_QOS_BASE }
/** Array initializer of ENET_QOS peripheral base pointers */
#define ENET_QOS_BASE_PTRS { ENET_QOS }
/** Interrupt vectors for the ENET_QOS peripheral type */
#define ENET_QOS_IRQS { ENET_QOS_IRQn }
#define ENET_QOS_PMT_IRQS { ENET_QOS_PMT_IRQn }
/*!
* @}
*/ /* end of group ENET_QOS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- ETHERNET_PLL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup ETHERNET_PLL_Peripheral_Access_Layer ETHERNET_PLL Peripheral Access Layer
* @{
*/
/** ETHERNET_PLL - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0 */
__IO uint32_t RW; /**< Fractional PLL Control Register, offset: 0x0 */
__IO uint32_t SET; /**< Fractional PLL Control Register, offset: 0x4 */
__IO uint32_t CLR; /**< Fractional PLL Control Register, offset: 0x8 */
__IO uint32_t TOG; /**< Fractional PLL Control Register, offset: 0xC */
} CTRL0;
struct { /* offset: 0x10 */
__IO uint32_t RW; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
__IO uint32_t SET; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
__IO uint32_t CLR; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
__IO uint32_t TOG; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
} SPREAD_SPECTRUM;
struct { /* offset: 0x20 */
__IO uint32_t RW; /**< Fractional PLL Numerator Control Register, offset: 0x20 */
__IO uint32_t SET; /**< Fractional PLL Numerator Control Register, offset: 0x24 */
__IO uint32_t CLR; /**< Fractional PLL Numerator Control Register, offset: 0x28 */
__IO uint32_t TOG; /**< Fractional PLL Numerator Control Register, offset: 0x2C */
} NUMERATOR;
struct { /* offset: 0x30 */
__IO uint32_t RW; /**< Fractional PLL Denominator Control Register, offset: 0x30 */
__IO uint32_t SET; /**< Fractional PLL Denominator Control Register, offset: 0x34 */
__IO uint32_t CLR; /**< Fractional PLL Denominator Control Register, offset: 0x38 */
__IO uint32_t TOG; /**< Fractional PLL Denominator Control Register, offset: 0x3C */
} DENOMINATOR;
} ETHERNET_PLL_Type;
/* ----------------------------------------------------------------------------
-- ETHERNET_PLL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup ETHERNET_PLL_Register_Masks ETHERNET_PLL Register Masks
* @{
*/
/*! @name CTRL0 - Fractional PLL Control Register */
/*! @{ */
#define ETHERNET_PLL_CTRL0_DIV_SELECT_MASK (0x7FU)
#define ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT (0U)
/*! DIV_SELECT - DIV_SELECT
*/
#define ETHERNET_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DIV_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_DIV_SELECT_MASK)
#define ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK (0x100U)
#define ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT (8U)
/*! ENABLE_ALT - ENABLE_ALT
* 0b0..Disable the alternate clock output
* 0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
*/
#define ETHERNET_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_ALT_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_ALT_MASK)
#define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U)
#define ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U)
/*! HOLD_RING_OFF - PLL Start up initialization
* 0b0..Normal operation
* 0b1..Initialize PLL start up
*/
#define ETHERNET_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & ETHERNET_PLL_CTRL0_HOLD_RING_OFF_MASK)
#define ETHERNET_PLL_CTRL0_POWERUP_MASK (0x4000U)
#define ETHERNET_PLL_CTRL0_POWERUP_SHIFT (14U)
/*! POWERUP - POWERUP
* 0b1..Power Up the PLL
* 0b0..Power down the PLL
*/
#define ETHERNET_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POWERUP_SHIFT)) & ETHERNET_PLL_CTRL0_POWERUP_MASK)
#define ETHERNET_PLL_CTRL0_ENABLE_MASK (0x8000U)
#define ETHERNET_PLL_CTRL0_ENABLE_SHIFT (15U)
/*! ENABLE - ENABLE
* 0b1..Enable the clock output
* 0b0..Disable the clock output
*/
#define ETHERNET_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_ENABLE_SHIFT)) & ETHERNET_PLL_CTRL0_ENABLE_MASK)
#define ETHERNET_PLL_CTRL0_BYPASS_MASK (0x10000U)
#define ETHERNET_PLL_CTRL0_BYPASS_SHIFT (16U)
/*! BYPASS - BYPASS
* 0b1..Bypass the PLL
* 0b0..No Bypass
*/
#define ETHERNET_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BYPASS_SHIFT)) & ETHERNET_PLL_CTRL0_BYPASS_MASK)
#define ETHERNET_PLL_CTRL0_DITHER_EN_MASK (0x20000U)
#define ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT (17U)
/*! DITHER_EN - DITHER_EN
* 0b0..Disable Dither
* 0b1..Enable Dither
*/
#define ETHERNET_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_DITHER_EN_SHIFT)) & ETHERNET_PLL_CTRL0_DITHER_EN_MASK)
#define ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U)
#define ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT (19U)
/*! BIAS_TRIM - BIAS_TRIM
*/
#define ETHERNET_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_TRIM_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_TRIM_MASK)
#define ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U)
#define ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT (22U)
/*! PLL_REG_EN - PLL_REG_EN
*/
#define ETHERNET_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_PLL_REG_EN_SHIFT)) & ETHERNET_PLL_CTRL0_PLL_REG_EN_MASK)
#define ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U)
#define ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U)
/*! POST_DIV_SEL - Post Divide Select
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 4
* 0b011..Divide by 8
* 0b100..Divide by 16
* 0b101..Divide by 32
*/
#define ETHERNET_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & ETHERNET_PLL_CTRL0_POST_DIV_SEL_MASK)
#define ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U)
#define ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT (29U)
/*! BIAS_SELECT - BIAS_SELECT
* 0b0..Used in SoCs with a bias current of 10uA
* 0b1..Used in SoCs with a bias current of 2uA
*/
#define ETHERNET_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_CTRL0_BIAS_SELECT_SHIFT)) & ETHERNET_PLL_CTRL0_BIAS_SELECT_MASK)
/*! @} */
/*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
/*! @{ */
#define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU)
#define ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U)
/*! STEP - Step
*/
#define ETHERNET_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STEP_MASK)
#define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U)
#define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U)
/*! ENABLE - Enable
*/
#define ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
#define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U)
#define ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U)
/*! STOP - Stop
*/
#define ETHERNET_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & ETHERNET_PLL_SPREAD_SPECTRUM_STOP_MASK)
/*! @} */
/*! @name NUMERATOR - Fractional PLL Numerator Control Register */
/*! @{ */
#define ETHERNET_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define ETHERNET_PLL_NUMERATOR_NUM_SHIFT (0U)
/*! NUM - Numerator
*/
#define ETHERNET_PLL_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_NUMERATOR_NUM_SHIFT)) & ETHERNET_PLL_NUMERATOR_NUM_MASK)
/*! @} */
/*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
/*! @{ */
#define ETHERNET_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT (0U)
/*! DENOM - Denominator
*/
#define ETHERNET_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << ETHERNET_PLL_DENOMINATOR_DENOM_SHIFT)) & ETHERNET_PLL_DENOMINATOR_DENOM_MASK)
/*! @} */
/*!
* @}
*/ /* end of group ETHERNET_PLL_Register_Masks */
/* ETHERNET_PLL - Peripheral instance base addresses */
/** Peripheral ETHERNET_PLL base address */
#define ETHERNET_PLL_BASE (0u)
/** Peripheral ETHERNET_PLL base pointer */
#define ETHERNET_PLL ((ETHERNET_PLL_Type *)ETHERNET_PLL_BASE)
/** Array initializer of ETHERNET_PLL peripheral base addresses */
#define ETHERNET_PLL_BASE_ADDRS { ETHERNET_PLL_BASE }
/** Array initializer of ETHERNET_PLL peripheral base pointers */
#define ETHERNET_PLL_BASE_PTRS { ETHERNET_PLL }
/*!
* @}
*/ /* end of group ETHERNET_PLL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- EWM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
* @{
*/
/** EWM - Register Layout Typedef */
typedef struct {
__IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
__O uint8_t SERV; /**< Service Register, offset: 0x1 */
__IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
__IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
__IO uint8_t CLKCTRL; /**< Clock Control Register, offset: 0x4 */
__IO uint8_t CLKPRESCALER; /**< Clock Prescaler Register, offset: 0x5 */
} EWM_Type;
/* ----------------------------------------------------------------------------
-- EWM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup EWM_Register_Masks EWM Register Masks
* @{
*/
/*! @name CTRL - Control Register */
/*! @{ */
#define EWM_CTRL_EWMEN_MASK (0x1U)
#define EWM_CTRL_EWMEN_SHIFT (0U)
/*! EWMEN - EWM enable.
* 0b0..EWM module is disabled.
* 0b1..EWM module is enabled.
*/
#define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
#define EWM_CTRL_ASSIN_MASK (0x2U)
#define EWM_CTRL_ASSIN_SHIFT (1U)
/*! ASSIN - EWM_in's Assertion State Select.
* 0b0..Default assert state of the EWM_in signal.
* 0b1..Inverts the assert state of EWM_in signal.
*/
#define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
#define EWM_CTRL_INEN_MASK (0x4U)
#define EWM_CTRL_INEN_SHIFT (2U)
/*! INEN - Input Enable.
* 0b0..EWM_in port is disabled.
* 0b1..EWM_in port is enabled.
*/
#define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
#define EWM_CTRL_INTEN_MASK (0x8U)
#define EWM_CTRL_INTEN_SHIFT (3U)
/*! INTEN - Interrupt Enable.
* 0b1..Generates an interrupt request, when EWM_OUT_b is asserted.
* 0b0..Deasserts the interrupt request.
*/
#define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
/*! @} */
/*! @name SERV - Service Register */
/*! @{ */
#define EWM_SERV_SERVICE_MASK (0xFFU)
#define EWM_SERV_SERVICE_SHIFT (0U)
/*! SERVICE - SERVICE
*/
#define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
/*! @} */
/*! @name CMPL - Compare Low Register */
/*! @{ */
#define EWM_CMPL_COMPAREL_MASK (0xFFU)
#define EWM_CMPL_COMPAREL_SHIFT (0U)
/*! COMPAREL - COMPAREL
*/
#define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
/*! @} */
/*! @name CMPH - Compare High Register */
/*! @{ */
#define EWM_CMPH_COMPAREH_MASK (0xFFU)
#define EWM_CMPH_COMPAREH_SHIFT (0U)
/*! COMPAREH - COMPAREH
*/
#define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
/*! @} */
/*! @name CLKCTRL - Clock Control Register */
/*! @{ */
#define EWM_CLKCTRL_CLKSEL_MASK (0x3U)
#define EWM_CLKCTRL_CLKSEL_SHIFT (0U)
/*! CLKSEL - CLKSEL
*/
#define EWM_CLKCTRL_CLKSEL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKCTRL_CLKSEL_SHIFT)) & EWM_CLKCTRL_CLKSEL_MASK)
/*! @} */
/*! @name CLKPRESCALER - Clock Prescaler Register */
/*! @{ */
#define EWM_CLKPRESCALER_CLK_DIV_MASK (0xFFU)
#define EWM_CLKPRESCALER_CLK_DIV_SHIFT (0U)
/*! CLK_DIV - CLK_DIV
*/
#define EWM_CLKPRESCALER_CLK_DIV(x) (((uint8_t)(((uint8_t)(x)) << EWM_CLKPRESCALER_CLK_DIV_SHIFT)) & EWM_CLKPRESCALER_CLK_DIV_MASK)
/*! @} */
/*!
* @}
*/ /* end of group EWM_Register_Masks */
/* EWM - Peripheral instance base addresses */
/** Peripheral EWM base address */
#define EWM_BASE (0x4002C000u)
/** Peripheral EWM base pointer */
#define EWM ((EWM_Type *)EWM_BASE)
/** Array initializer of EWM peripheral base addresses */
#define EWM_BASE_ADDRS { EWM_BASE }
/** Array initializer of EWM peripheral base pointers */
#define EWM_BASE_PTRS { EWM }
/** Interrupt vectors for the EWM peripheral type */
#define EWM_IRQS { EWM_IRQn }
/*!
* @}
*/ /* end of group EWM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Peripheral_Access_Layer FLEXIO Peripheral Access Layer
* @{
*/
/** FLEXIO - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t CTRL; /**< FlexIO Control Register, offset: 0x8 */
__I uint32_t PIN; /**< Pin State Register, offset: 0xC */
__IO uint32_t SHIFTSTAT; /**< Shifter Status Register, offset: 0x10 */
__IO uint32_t SHIFTERR; /**< Shifter Error Register, offset: 0x14 */
__IO uint32_t TIMSTAT; /**< Timer Status Register, offset: 0x18 */
uint8_t RESERVED_0[4];
__IO uint32_t SHIFTSIEN; /**< Shifter Status Interrupt Enable, offset: 0x20 */
__IO uint32_t SHIFTEIEN; /**< Shifter Error Interrupt Enable, offset: 0x24 */
__IO uint32_t TIMIEN; /**< Timer Interrupt Enable Register, offset: 0x28 */
uint8_t RESERVED_1[4];
__IO uint32_t SHIFTSDEN; /**< Shifter Status DMA Enable, offset: 0x30 */
uint8_t RESERVED_2[4];
__IO uint32_t TIMERSDEN; /**< Timer Status DMA Enable, offset: 0x38 */
uint8_t RESERVED_3[4];
__IO uint32_t SHIFTSTATE; /**< Shifter State Register, offset: 0x40 */
uint8_t RESERVED_4[60];
__IO uint32_t SHIFTCTL[8]; /**< Shifter Control N Register, array offset: 0x80, array step: 0x4 */
uint8_t RESERVED_5[96];
__IO uint32_t SHIFTCFG[8]; /**< Shifter Configuration N Register, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_6[224];
__IO uint32_t SHIFTBUF[8]; /**< Shifter Buffer N Register, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_7[96];
__IO uint32_t SHIFTBUFBIS[8]; /**< Shifter Buffer N Bit Swapped Register, array offset: 0x280, array step: 0x4 */
uint8_t RESERVED_8[96];
__IO uint32_t SHIFTBUFBYS[8]; /**< Shifter Buffer N Byte Swapped Register, array offset: 0x300, array step: 0x4 */
uint8_t RESERVED_9[96];
__IO uint32_t SHIFTBUFBBS[8]; /**< Shifter Buffer N Bit Byte Swapped Register, array offset: 0x380, array step: 0x4 */
uint8_t RESERVED_10[96];
__IO uint32_t TIMCTL[8]; /**< Timer Control N Register, array offset: 0x400, array step: 0x4 */
uint8_t RESERVED_11[96];
__IO uint32_t TIMCFG[8]; /**< Timer Configuration N Register, array offset: 0x480, array step: 0x4 */
uint8_t RESERVED_12[96];
__IO uint32_t TIMCMP[8]; /**< Timer Compare N Register, array offset: 0x500, array step: 0x4 */
uint8_t RESERVED_13[352];
__IO uint32_t SHIFTBUFNBS[8]; /**< Shifter Buffer N Nibble Byte Swapped Register, array offset: 0x680, array step: 0x4 */
uint8_t RESERVED_14[96];
__IO uint32_t SHIFTBUFHWS[8]; /**< Shifter Buffer N Half Word Swapped Register, array offset: 0x700, array step: 0x4 */
uint8_t RESERVED_15[96];
__IO uint32_t SHIFTBUFNIS[8]; /**< Shifter Buffer N Nibble Swapped Register, array offset: 0x780, array step: 0x4 */
uint8_t RESERVED_16[96];
__IO uint32_t SHIFTBUFOES[8]; /**< Shifter Buffer N Odd Even Swapped Register, array offset: 0x800, array step: 0x4 */
uint8_t RESERVED_17[96];
__IO uint32_t SHIFTBUFEOS[8]; /**< Shifter Buffer N Even Odd Swapped Register, array offset: 0x880, array step: 0x4 */
} FLEXIO_Type;
/* ----------------------------------------------------------------------------
-- FLEXIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXIO_Register_Masks FLEXIO Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
/*! @{ */
#define FLEXIO_VERID_FEATURE_MASK (0xFFFFU)
#define FLEXIO_VERID_FEATURE_SHIFT (0U)
/*! FEATURE - Feature Specification Number
* 0b0000000000000000..Standard features implemented.
* 0b0000000000000001..Supports state, logic and parallel modes.
* 0b0000000000000010..Supports pin control registers.
* 0b0000000000000011..Supports state, logic and parallel modes; plus pin control registers.
*/
#define FLEXIO_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_FEATURE_SHIFT)) & FLEXIO_VERID_FEATURE_MASK)
#define FLEXIO_VERID_MINOR_MASK (0xFF0000U)
#define FLEXIO_VERID_MINOR_SHIFT (16U)
/*! MINOR - Minor Version Number
*/
#define FLEXIO_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MINOR_SHIFT)) & FLEXIO_VERID_MINOR_MASK)
#define FLEXIO_VERID_MAJOR_MASK (0xFF000000U)
#define FLEXIO_VERID_MAJOR_SHIFT (24U)
/*! MAJOR - Major Version Number
*/
#define FLEXIO_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_VERID_MAJOR_SHIFT)) & FLEXIO_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define FLEXIO_PARAM_SHIFTER_MASK (0xFFU)
#define FLEXIO_PARAM_SHIFTER_SHIFT (0U)
/*! SHIFTER - Shifter Number
*/
#define FLEXIO_PARAM_SHIFTER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_SHIFTER_SHIFT)) & FLEXIO_PARAM_SHIFTER_MASK)
#define FLEXIO_PARAM_TIMER_MASK (0xFF00U)
#define FLEXIO_PARAM_TIMER_SHIFT (8U)
/*! TIMER - Timer Number
*/
#define FLEXIO_PARAM_TIMER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TIMER_SHIFT)) & FLEXIO_PARAM_TIMER_MASK)
#define FLEXIO_PARAM_PIN_MASK (0xFF0000U)
#define FLEXIO_PARAM_PIN_SHIFT (16U)
/*! PIN - Pin Number
*/
#define FLEXIO_PARAM_PIN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_PIN_SHIFT)) & FLEXIO_PARAM_PIN_MASK)
#define FLEXIO_PARAM_TRIGGER_MASK (0xFF000000U)
#define FLEXIO_PARAM_TRIGGER_SHIFT (24U)
/*! TRIGGER - Trigger Number
*/
#define FLEXIO_PARAM_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PARAM_TRIGGER_SHIFT)) & FLEXIO_PARAM_TRIGGER_MASK)
/*! @} */
/*! @name CTRL - FlexIO Control Register */
/*! @{ */
#define FLEXIO_CTRL_FLEXEN_MASK (0x1U)
#define FLEXIO_CTRL_FLEXEN_SHIFT (0U)
/*! FLEXEN - FlexIO Enable
* 0b0..FlexIO module is disabled.
* 0b1..FlexIO module is enabled.
*/
#define FLEXIO_CTRL_FLEXEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FLEXEN_SHIFT)) & FLEXIO_CTRL_FLEXEN_MASK)
#define FLEXIO_CTRL_SWRST_MASK (0x2U)
#define FLEXIO_CTRL_SWRST_SHIFT (1U)
/*! SWRST - Software Reset
* 0b0..Software reset is disabled
* 0b1..Software reset is enabled, all FlexIO registers except the Control Register are reset.
*/
#define FLEXIO_CTRL_SWRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_SWRST_SHIFT)) & FLEXIO_CTRL_SWRST_MASK)
#define FLEXIO_CTRL_FASTACC_MASK (0x4U)
#define FLEXIO_CTRL_FASTACC_SHIFT (2U)
/*! FASTACC - Fast Access
* 0b0..Configures for normal register accesses to FlexIO
* 0b1..Configures for fast register accesses to FlexIO
*/
#define FLEXIO_CTRL_FASTACC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_FASTACC_SHIFT)) & FLEXIO_CTRL_FASTACC_MASK)
#define FLEXIO_CTRL_DBGE_MASK (0x40000000U)
#define FLEXIO_CTRL_DBGE_SHIFT (30U)
/*! DBGE - Debug Enable
* 0b0..FlexIO is disabled in debug modes.
* 0b1..FlexIO is enabled in debug modes
*/
#define FLEXIO_CTRL_DBGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DBGE_SHIFT)) & FLEXIO_CTRL_DBGE_MASK)
#define FLEXIO_CTRL_DOZEN_MASK (0x80000000U)
#define FLEXIO_CTRL_DOZEN_SHIFT (31U)
/*! DOZEN - Doze Enable
* 0b0..FlexIO enabled in Doze modes.
* 0b1..FlexIO disabled in Doze modes.
*/
#define FLEXIO_CTRL_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_CTRL_DOZEN_SHIFT)) & FLEXIO_CTRL_DOZEN_MASK)
/*! @} */
/*! @name PIN - Pin State Register */
/*! @{ */
#define FLEXIO_PIN_PDI_MASK (0xFFFFFFFFU)
#define FLEXIO_PIN_PDI_SHIFT (0U)
/*! PDI - Pin Data Input
*/
#define FLEXIO_PIN_PDI(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_PIN_PDI_SHIFT)) & FLEXIO_PIN_PDI_MASK)
/*! @} */
/*! @name SHIFTSTAT - Shifter Status Register */
/*! @{ */
#define FLEXIO_SHIFTSTAT_SSF_MASK (0xFFU)
#define FLEXIO_SHIFTSTAT_SSF_SHIFT (0U)
/*! SSF - Shifter Status Flag
*/
#define FLEXIO_SHIFTSTAT_SSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTAT_SSF_SHIFT)) & FLEXIO_SHIFTSTAT_SSF_MASK)
/*! @} */
/*! @name SHIFTERR - Shifter Error Register */
/*! @{ */
#define FLEXIO_SHIFTERR_SEF_MASK (0xFFU)
#define FLEXIO_SHIFTERR_SEF_SHIFT (0U)
/*! SEF - Shifter Error Flags
*/
#define FLEXIO_SHIFTERR_SEF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTERR_SEF_SHIFT)) & FLEXIO_SHIFTERR_SEF_MASK)
/*! @} */
/*! @name TIMSTAT - Timer Status Register */
/*! @{ */
#define FLEXIO_TIMSTAT_TSF_MASK (0xFFU)
#define FLEXIO_TIMSTAT_TSF_SHIFT (0U)
/*! TSF - Timer Status Flags
*/
#define FLEXIO_TIMSTAT_TSF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMSTAT_TSF_SHIFT)) & FLEXIO_TIMSTAT_TSF_MASK)
/*! @} */
/*! @name SHIFTSIEN - Shifter Status Interrupt Enable */
/*! @{ */
#define FLEXIO_SHIFTSIEN_SSIE_MASK (0xFFU)
#define FLEXIO_SHIFTSIEN_SSIE_SHIFT (0U)
/*! SSIE - Shifter Status Interrupt Enable
*/
#define FLEXIO_SHIFTSIEN_SSIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSIEN_SSIE_SHIFT)) & FLEXIO_SHIFTSIEN_SSIE_MASK)
/*! @} */
/*! @name SHIFTEIEN - Shifter Error Interrupt Enable */
/*! @{ */
#define FLEXIO_SHIFTEIEN_SEIE_MASK (0xFFU)
#define FLEXIO_SHIFTEIEN_SEIE_SHIFT (0U)
/*! SEIE - Shifter Error Interrupt Enable
*/
#define FLEXIO_SHIFTEIEN_SEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTEIEN_SEIE_SHIFT)) & FLEXIO_SHIFTEIEN_SEIE_MASK)
/*! @} */
/*! @name TIMIEN - Timer Interrupt Enable Register */
/*! @{ */
#define FLEXIO_TIMIEN_TEIE_MASK (0xFFU)
#define FLEXIO_TIMIEN_TEIE_SHIFT (0U)
/*! TEIE - Timer Status Interrupt Enable
*/
#define FLEXIO_TIMIEN_TEIE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMIEN_TEIE_SHIFT)) & FLEXIO_TIMIEN_TEIE_MASK)
/*! @} */
/*! @name SHIFTSDEN - Shifter Status DMA Enable */
/*! @{ */
#define FLEXIO_SHIFTSDEN_SSDE_MASK (0xFFU)
#define FLEXIO_SHIFTSDEN_SSDE_SHIFT (0U)
/*! SSDE - Shifter Status DMA Enable
*/
#define FLEXIO_SHIFTSDEN_SSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSDEN_SSDE_SHIFT)) & FLEXIO_SHIFTSDEN_SSDE_MASK)
/*! @} */
/*! @name TIMERSDEN - Timer Status DMA Enable */
/*! @{ */
#define FLEXIO_TIMERSDEN_TSDE_MASK (0xFFU)
#define FLEXIO_TIMERSDEN_TSDE_SHIFT (0U)
/*! TSDE - Timer Status DMA Enable
*/
#define FLEXIO_TIMERSDEN_TSDE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMERSDEN_TSDE_SHIFT)) & FLEXIO_TIMERSDEN_TSDE_MASK)
/*! @} */
/*! @name SHIFTSTATE - Shifter State Register */
/*! @{ */
#define FLEXIO_SHIFTSTATE_STATE_MASK (0x7U)
#define FLEXIO_SHIFTSTATE_STATE_SHIFT (0U)
/*! STATE - Current State Pointer
*/
#define FLEXIO_SHIFTSTATE_STATE(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTSTATE_STATE_SHIFT)) & FLEXIO_SHIFTSTATE_STATE_MASK)
/*! @} */
/*! @name SHIFTCTL - Shifter Control N Register */
/*! @{ */
#define FLEXIO_SHIFTCTL_SMOD_MASK (0x7U)
#define FLEXIO_SHIFTCTL_SMOD_SHIFT (0U)
/*! SMOD - Shifter Mode
* 0b000..Disabled.
* 0b001..Receive mode. Captures the current Shifter content into the SHIFTBUF on expiration of the Timer.
* 0b010..Transmit mode. Load SHIFTBUF contents into the Shifter on expiration of the Timer.
* 0b011..Reserved.
* 0b100..Match Store mode. Shifter data is compared to SHIFTBUF content on expiration of the Timer.
* 0b101..Match Continuous mode. Shifter data is continuously compared to SHIFTBUF contents.
* 0b110..State mode. SHIFTBUF contents are used for storing programmable state attributes.
* 0b111..Logic mode. SHIFTBUF contents are used for implementing programmable logic look up table.
*/
#define FLEXIO_SHIFTCTL_SMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_SMOD_SHIFT)) & FLEXIO_SHIFTCTL_SMOD_MASK)
#define FLEXIO_SHIFTCTL_PINPOL_MASK (0x80U)
#define FLEXIO_SHIFTCTL_PINPOL_SHIFT (7U)
/*! PINPOL - Shifter Pin Polarity
* 0b0..Pin is active high
* 0b1..Pin is active low
*/
#define FLEXIO_SHIFTCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINPOL_SHIFT)) & FLEXIO_SHIFTCTL_PINPOL_MASK)
#define FLEXIO_SHIFTCTL_PINSEL_MASK (0x1F00U)
#define FLEXIO_SHIFTCTL_PINSEL_SHIFT (8U)
/*! PINSEL - Shifter Pin Select
*/
#define FLEXIO_SHIFTCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINSEL_SHIFT)) & FLEXIO_SHIFTCTL_PINSEL_MASK)
#define FLEXIO_SHIFTCTL_PINCFG_MASK (0x30000U)
#define FLEXIO_SHIFTCTL_PINCFG_SHIFT (16U)
/*! PINCFG - Shifter Pin Configuration
* 0b00..Shifter pin output disabled
* 0b01..Shifter pin open drain or bidirectional output enable
* 0b10..Shifter pin bidirectional output data
* 0b11..Shifter pin output
*/
#define FLEXIO_SHIFTCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_PINCFG_SHIFT)) & FLEXIO_SHIFTCTL_PINCFG_MASK)
#define FLEXIO_SHIFTCTL_TIMPOL_MASK (0x800000U)
#define FLEXIO_SHIFTCTL_TIMPOL_SHIFT (23U)
/*! TIMPOL - Timer Polarity
* 0b0..Shift on posedge of Shift clock
* 0b1..Shift on negedge of Shift clock
*/
#define FLEXIO_SHIFTCTL_TIMPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMPOL_SHIFT)) & FLEXIO_SHIFTCTL_TIMPOL_MASK)
#define FLEXIO_SHIFTCTL_TIMSEL_MASK (0x7000000U)
#define FLEXIO_SHIFTCTL_TIMSEL_SHIFT (24U)
/*! TIMSEL - Timer Select
*/
#define FLEXIO_SHIFTCTL_TIMSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCTL_TIMSEL_SHIFT)) & FLEXIO_SHIFTCTL_TIMSEL_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTCTL */
#define FLEXIO_SHIFTCTL_COUNT (8U)
/*! @name SHIFTCFG - Shifter Configuration N Register */
/*! @{ */
#define FLEXIO_SHIFTCFG_SSTART_MASK (0x3U)
#define FLEXIO_SHIFTCFG_SSTART_SHIFT (0U)
/*! SSTART - Shifter Start bit
* 0b00..Start bit disabled for transmitter/receiver/match store, transmitter loads data on enable
* 0b01..Start bit disabled for transmitter/receiver/match store, transmitter loads data on first shift
* 0b10..Transmitter outputs start bit value 0 before loading data on first shift, receiver/match store sets error flag if start bit is not 0
* 0b11..Transmitter outputs start bit value 1 before loading data on first shift, receiver/match store sets error flag if start bit is not 1
*/
#define FLEXIO_SHIFTCFG_SSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTART_SHIFT)) & FLEXIO_SHIFTCFG_SSTART_MASK)
#define FLEXIO_SHIFTCFG_SSTOP_MASK (0x30U)
#define FLEXIO_SHIFTCFG_SSTOP_SHIFT (4U)
/*! SSTOP - Shifter Stop bit
* 0b00..Stop bit disabled for transmitter/receiver/match store
* 0b01..Reserved for transmitter/receiver/match store
* 0b10..Transmitter outputs stop bit value 0 on store, receiver/match store sets error flag if stop bit is not 0
* 0b11..Transmitter outputs stop bit value 1 on store, receiver/match store sets error flag if stop bit is not 1
*/
#define FLEXIO_SHIFTCFG_SSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_SSTOP_SHIFT)) & FLEXIO_SHIFTCFG_SSTOP_MASK)
#define FLEXIO_SHIFTCFG_INSRC_MASK (0x100U)
#define FLEXIO_SHIFTCFG_INSRC_SHIFT (8U)
/*! INSRC - Input Source
* 0b0..Pin
* 0b1..Shifter N+1 Output
*/
#define FLEXIO_SHIFTCFG_INSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_INSRC_SHIFT)) & FLEXIO_SHIFTCFG_INSRC_MASK)
#define FLEXIO_SHIFTCFG_LATST_MASK (0x200U)
#define FLEXIO_SHIFTCFG_LATST_SHIFT (9U)
/*! LATST - Late Store
* 0b0..Shift register stores the pre-shift register state.
* 0b1..Shift register stores the post-shift register state.
*/
#define FLEXIO_SHIFTCFG_LATST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_LATST_SHIFT)) & FLEXIO_SHIFTCFG_LATST_MASK)
#define FLEXIO_SHIFTCFG_PWIDTH_MASK (0x1F0000U)
#define FLEXIO_SHIFTCFG_PWIDTH_SHIFT (16U)
/*! PWIDTH - Parallel Width
*/
#define FLEXIO_SHIFTCFG_PWIDTH(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTCFG_PWIDTH_SHIFT)) & FLEXIO_SHIFTCFG_PWIDTH_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTCFG */
#define FLEXIO_SHIFTCFG_COUNT (8U)
/*! @name SHIFTBUF - Shifter Buffer N Register */
/*! @{ */
#define FLEXIO_SHIFTBUF_SHIFTBUF_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT (0U)
/*! SHIFTBUF - Shift Buffer
*/
#define FLEXIO_SHIFTBUF_SHIFTBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUF_SHIFTBUF_SHIFT)) & FLEXIO_SHIFTBUF_SHIFTBUF_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUF */
#define FLEXIO_SHIFTBUF_COUNT (8U)
/*! @name SHIFTBUFBIS - Shifter Buffer N Bit Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT (0U)
/*! SHIFTBUFBIS - Shift Buffer
*/
#define FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_SHIFT)) & FLEXIO_SHIFTBUFBIS_SHIFTBUFBIS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFBIS */
#define FLEXIO_SHIFTBUFBIS_COUNT (8U)
/*! @name SHIFTBUFBYS - Shifter Buffer N Byte Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT (0U)
/*! SHIFTBUFBYS - Shift Buffer
*/
#define FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_SHIFT)) & FLEXIO_SHIFTBUFBYS_SHIFTBUFBYS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFBYS */
#define FLEXIO_SHIFTBUFBYS_COUNT (8U)
/*! @name SHIFTBUFBBS - Shifter Buffer N Bit Byte Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT (0U)
/*! SHIFTBUFBBS - Shift Buffer
*/
#define FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_SHIFT)) & FLEXIO_SHIFTBUFBBS_SHIFTBUFBBS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFBBS */
#define FLEXIO_SHIFTBUFBBS_COUNT (8U)
/*! @name TIMCTL - Timer Control N Register */
/*! @{ */
#define FLEXIO_TIMCTL_TIMOD_MASK (0x7U)
#define FLEXIO_TIMCTL_TIMOD_SHIFT (0U)
/*! TIMOD - Timer Mode
* 0b000..Timer Disabled.
* 0b001..Dual 8-bit counters baud mode.
* 0b010..Dual 8-bit counters PWM high mode.
* 0b011..Single 16-bit counter mode.
* 0b100..Single 16-bit counter disable mode.
* 0b101..Dual 8-bit counters word mode.
* 0b110..Dual 8-bit counters PWM low mode.
* 0b111..Single 16-bit input capture mode.
*/
#define FLEXIO_TIMCTL_TIMOD(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TIMOD_SHIFT)) & FLEXIO_TIMCTL_TIMOD_MASK)
#define FLEXIO_TIMCTL_ONETIM_MASK (0x20U)
#define FLEXIO_TIMCTL_ONETIM_SHIFT (5U)
/*! ONETIM - Timer One Time Operation
* 0b0..The timer enable event is generated as normal.
* 0b1..The timer enable event is blocked unless timer status flag is clear.
*/
#define FLEXIO_TIMCTL_ONETIM(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_ONETIM_SHIFT)) & FLEXIO_TIMCTL_ONETIM_MASK)
#define FLEXIO_TIMCTL_PININS_MASK (0x40U)
#define FLEXIO_TIMCTL_PININS_SHIFT (6U)
/*! PININS - Timer Pin Input Select
* 0b0..Timer pin input and output are selected by PINSEL.
* 0b1..Timer pin input is selected by PINSEL+1, timer pin output remains selected by PINSEL.
*/
#define FLEXIO_TIMCTL_PININS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PININS_SHIFT)) & FLEXIO_TIMCTL_PININS_MASK)
#define FLEXIO_TIMCTL_PINPOL_MASK (0x80U)
#define FLEXIO_TIMCTL_PINPOL_SHIFT (7U)
/*! PINPOL - Timer Pin Polarity
* 0b0..Pin is active high
* 0b1..Pin is active low
*/
#define FLEXIO_TIMCTL_PINPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINPOL_SHIFT)) & FLEXIO_TIMCTL_PINPOL_MASK)
#define FLEXIO_TIMCTL_PINSEL_MASK (0x1F00U)
#define FLEXIO_TIMCTL_PINSEL_SHIFT (8U)
/*! PINSEL - Timer Pin Select
*/
#define FLEXIO_TIMCTL_PINSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINSEL_SHIFT)) & FLEXIO_TIMCTL_PINSEL_MASK)
#define FLEXIO_TIMCTL_PINCFG_MASK (0x30000U)
#define FLEXIO_TIMCTL_PINCFG_SHIFT (16U)
/*! PINCFG - Timer Pin Configuration
* 0b00..Timer pin output disabled
* 0b01..Timer pin open drain or bidirectional output enable
* 0b10..Timer pin bidirectional output data
* 0b11..Timer pin output
*/
#define FLEXIO_TIMCTL_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_PINCFG_SHIFT)) & FLEXIO_TIMCTL_PINCFG_MASK)
#define FLEXIO_TIMCTL_TRGSRC_MASK (0x400000U)
#define FLEXIO_TIMCTL_TRGSRC_SHIFT (22U)
/*! TRGSRC - Trigger Source
* 0b0..External trigger selected
* 0b1..Internal trigger selected
*/
#define FLEXIO_TIMCTL_TRGSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSRC_SHIFT)) & FLEXIO_TIMCTL_TRGSRC_MASK)
#define FLEXIO_TIMCTL_TRGPOL_MASK (0x800000U)
#define FLEXIO_TIMCTL_TRGPOL_SHIFT (23U)
/*! TRGPOL - Trigger Polarity
* 0b0..Trigger active high
* 0b1..Trigger active low
*/
#define FLEXIO_TIMCTL_TRGPOL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGPOL_SHIFT)) & FLEXIO_TIMCTL_TRGPOL_MASK)
#define FLEXIO_TIMCTL_TRGSEL_MASK (0x3F000000U)
#define FLEXIO_TIMCTL_TRGSEL_SHIFT (24U)
/*! TRGSEL - Trigger Select
*/
#define FLEXIO_TIMCTL_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCTL_TRGSEL_SHIFT)) & FLEXIO_TIMCTL_TRGSEL_MASK)
/*! @} */
/* The count of FLEXIO_TIMCTL */
#define FLEXIO_TIMCTL_COUNT (8U)
/*! @name TIMCFG - Timer Configuration N Register */
/*! @{ */
#define FLEXIO_TIMCFG_TSTART_MASK (0x2U)
#define FLEXIO_TIMCFG_TSTART_SHIFT (1U)
/*! TSTART - Timer Start Bit
* 0b0..Start bit disabled
* 0b1..Start bit enabled
*/
#define FLEXIO_TIMCFG_TSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTART_SHIFT)) & FLEXIO_TIMCFG_TSTART_MASK)
#define FLEXIO_TIMCFG_TSTOP_MASK (0x30U)
#define FLEXIO_TIMCFG_TSTOP_SHIFT (4U)
/*! TSTOP - Timer Stop Bit
* 0b00..Stop bit disabled
* 0b01..Stop bit is enabled on timer compare
* 0b10..Stop bit is enabled on timer disable
* 0b11..Stop bit is enabled on timer compare and timer disable
*/
#define FLEXIO_TIMCFG_TSTOP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TSTOP_SHIFT)) & FLEXIO_TIMCFG_TSTOP_MASK)
#define FLEXIO_TIMCFG_TIMENA_MASK (0x700U)
#define FLEXIO_TIMCFG_TIMENA_SHIFT (8U)
/*! TIMENA - Timer Enable
* 0b000..Timer always enabled
* 0b001..Timer enabled on Timer N-1 enable
* 0b010..Timer enabled on Trigger high
* 0b011..Timer enabled on Trigger high and Pin high
* 0b100..Timer enabled on Pin rising edge
* 0b101..Timer enabled on Pin rising edge and Trigger high
* 0b110..Timer enabled on Trigger rising edge
* 0b111..Timer enabled on Trigger rising or falling edge
*/
#define FLEXIO_TIMCFG_TIMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMENA_SHIFT)) & FLEXIO_TIMCFG_TIMENA_MASK)
#define FLEXIO_TIMCFG_TIMDIS_MASK (0x7000U)
#define FLEXIO_TIMCFG_TIMDIS_SHIFT (12U)
/*! TIMDIS - Timer Disable
* 0b000..Timer never disabled
* 0b001..Timer disabled on Timer N-1 disable
* 0b010..Timer disabled on Timer compare (upper 8-bits match and decrement)
* 0b011..Timer disabled on Timer compare (upper 8-bits match and decrement) and Trigger Low
* 0b100..Timer disabled on Pin rising or falling edge
* 0b101..Timer disabled on Pin rising or falling edge provided Trigger is high
* 0b110..Timer disabled on Trigger falling edge
* 0b111..Reserved
*/
#define FLEXIO_TIMCFG_TIMDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDIS_SHIFT)) & FLEXIO_TIMCFG_TIMDIS_MASK)
#define FLEXIO_TIMCFG_TIMRST_MASK (0x70000U)
#define FLEXIO_TIMCFG_TIMRST_SHIFT (16U)
/*! TIMRST - Timer Reset
* 0b000..Timer never reset
* 0b001..Timer reset on Timer Output high.
* 0b010..Timer reset on Timer Pin equal to Timer Output
* 0b011..Timer reset on Timer Trigger equal to Timer Output
* 0b100..Timer reset on Timer Pin rising edge
* 0b101..Reserved
* 0b110..Timer reset on Trigger rising edge
* 0b111..Timer reset on Trigger rising or falling edge
*/
#define FLEXIO_TIMCFG_TIMRST(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMRST_SHIFT)) & FLEXIO_TIMCFG_TIMRST_MASK)
#define FLEXIO_TIMCFG_TIMDEC_MASK (0x700000U)
#define FLEXIO_TIMCFG_TIMDEC_SHIFT (20U)
/*! TIMDEC - Timer Decrement
* 0b000..Decrement counter on FlexIO clock, Shift clock equals Timer output.
* 0b001..Decrement counter on Trigger input (both edges), Shift clock equals Timer output.
* 0b010..Decrement counter on Pin input (both edges), Shift clock equals Pin input.
* 0b011..Decrement counter on Trigger input (both edges), Shift clock equals Trigger input.
* 0b100..Decrement counter on FlexIO clock divided by 16, Shift clock equals Timer output.
* 0b101..Decrement counter on FlexIO clock divided by 256, Shift clock equals Timer output.
* 0b110..Decrement counter on Pin input (rising edge), Shift clock equals Pin input.
* 0b111..Decrement counter on Trigger input (rising edge), Shift clock equals Trigger input.
*/
#define FLEXIO_TIMCFG_TIMDEC(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMDEC_SHIFT)) & FLEXIO_TIMCFG_TIMDEC_MASK)
#define FLEXIO_TIMCFG_TIMOUT_MASK (0x3000000U)
#define FLEXIO_TIMCFG_TIMOUT_SHIFT (24U)
/*! TIMOUT - Timer Output
* 0b00..Timer output is logic one when enabled and is not affected by timer reset
* 0b01..Timer output is logic zero when enabled and is not affected by timer reset
* 0b10..Timer output is logic one when enabled and on timer reset
* 0b11..Timer output is logic zero when enabled and on timer reset
*/
#define FLEXIO_TIMCFG_TIMOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCFG_TIMOUT_SHIFT)) & FLEXIO_TIMCFG_TIMOUT_MASK)
/*! @} */
/* The count of FLEXIO_TIMCFG */
#define FLEXIO_TIMCFG_COUNT (8U)
/*! @name TIMCMP - Timer Compare N Register */
/*! @{ */
#define FLEXIO_TIMCMP_CMP_MASK (0xFFFFU)
#define FLEXIO_TIMCMP_CMP_SHIFT (0U)
/*! CMP - Timer Compare Value
*/
#define FLEXIO_TIMCMP_CMP(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_TIMCMP_CMP_SHIFT)) & FLEXIO_TIMCMP_CMP_MASK)
/*! @} */
/* The count of FLEXIO_TIMCMP */
#define FLEXIO_TIMCMP_COUNT (8U)
/*! @name SHIFTBUFNBS - Shifter Buffer N Nibble Byte Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT (0U)
/*! SHIFTBUFNBS - Shift Buffer
*/
#define FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_SHIFT)) & FLEXIO_SHIFTBUFNBS_SHIFTBUFNBS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFNBS */
#define FLEXIO_SHIFTBUFNBS_COUNT (8U)
/*! @name SHIFTBUFHWS - Shifter Buffer N Half Word Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT (0U)
/*! SHIFTBUFHWS - Shift Buffer
*/
#define FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_SHIFT)) & FLEXIO_SHIFTBUFHWS_SHIFTBUFHWS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFHWS */
#define FLEXIO_SHIFTBUFHWS_COUNT (8U)
/*! @name SHIFTBUFNIS - Shifter Buffer N Nibble Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT (0U)
/*! SHIFTBUFNIS - Shift Buffer
*/
#define FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_SHIFT)) & FLEXIO_SHIFTBUFNIS_SHIFTBUFNIS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFNIS */
#define FLEXIO_SHIFTBUFNIS_COUNT (8U)
/*! @name SHIFTBUFOES - Shifter Buffer N Odd Even Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT (0U)
/*! SHIFTBUFOES - Shift Buffer
*/
#define FLEXIO_SHIFTBUFOES_SHIFTBUFOES(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFOES_SHIFTBUFOES_SHIFT)) & FLEXIO_SHIFTBUFOES_SHIFTBUFOES_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFOES */
#define FLEXIO_SHIFTBUFOES_COUNT (8U)
/*! @name SHIFTBUFEOS - Shifter Buffer N Even Odd Swapped Register */
/*! @{ */
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK (0xFFFFFFFFU)
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT (0U)
/*! SHIFTBUFEOS - Shift Buffer
*/
#define FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS(x) (((uint32_t)(((uint32_t)(x)) << FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_SHIFT)) & FLEXIO_SHIFTBUFEOS_SHIFTBUFEOS_MASK)
/*! @} */
/* The count of FLEXIO_SHIFTBUFEOS */
#define FLEXIO_SHIFTBUFEOS_COUNT (8U)
/*!
* @}
*/ /* end of group FLEXIO_Register_Masks */
/* FLEXIO - Peripheral instance base addresses */
/** Peripheral FLEXIO1 base address */
#define FLEXIO1_BASE (0x400AC000u)
/** Peripheral FLEXIO1 base pointer */
#define FLEXIO1 ((FLEXIO_Type *)FLEXIO1_BASE)
/** Peripheral FLEXIO2 base address */
#define FLEXIO2_BASE (0x400B0000u)
/** Peripheral FLEXIO2 base pointer */
#define FLEXIO2 ((FLEXIO_Type *)FLEXIO2_BASE)
/** Array initializer of FLEXIO peripheral base addresses */
#define FLEXIO_BASE_ADDRS { 0u, FLEXIO1_BASE, FLEXIO2_BASE }
/** Array initializer of FLEXIO peripheral base pointers */
#define FLEXIO_BASE_PTRS { (FLEXIO_Type *)0u, FLEXIO1, FLEXIO2 }
/** Interrupt vectors for the FLEXIO peripheral type */
#define FLEXIO_IRQS { NotAvail_IRQn, FLEXIO1_IRQn, FLEXIO2_IRQn }
/*!
* @}
*/ /* end of group FLEXIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXRAM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXRAM_Peripheral_Access_Layer FLEXRAM Peripheral Access Layer
* @{
*/
/** FLEXRAM - Register Layout Typedef */
typedef struct {
__IO uint32_t TCM_CTRL; /**< TCM CRTL Register, offset: 0x0 */
__IO uint32_t OCRAM_MAGIC_ADDR; /**< OCRAM Magic Address Register, offset: 0x4 */
__IO uint32_t DTCM_MAGIC_ADDR; /**< DTCM Magic Address Register, offset: 0x8 */
__IO uint32_t ITCM_MAGIC_ADDR; /**< ITCM Magic Address Register, offset: 0xC */
__IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x10 */
__IO uint32_t INT_STAT_EN; /**< Interrupt Status Enable Register, offset: 0x14 */
__IO uint32_t INT_SIG_EN; /**< Interrupt Enable Register, offset: 0x18 */
__I uint32_t OCRAM_ECC_SINGLE_ERROR_INFO; /**< OCRAM single-bit ECC Error Information Register, offset: 0x1C */
__I uint32_t OCRAM_ECC_SINGLE_ERROR_ADDR; /**< OCRAM single-bit ECC Error Address Register, offset: 0x20 */
__I uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_LSB; /**< OCRAM single-bit ECC Error Data Register, offset: 0x24 */
__I uint32_t OCRAM_ECC_SINGLE_ERROR_DATA_MSB; /**< OCRAM single-bit ECC Error Data Register, offset: 0x28 */
__I uint32_t OCRAM_ECC_MULTI_ERROR_INFO; /**< OCRAM multi-bit ECC Error Information Register, offset: 0x2C */
__I uint32_t OCRAM_ECC_MULTI_ERROR_ADDR; /**< OCRAM multi-bit ECC Error Address Register, offset: 0x30 */
__I uint32_t OCRAM_ECC_MULTI_ERROR_DATA_LSB; /**< OCRAM multi-bit ECC Error Data Register, offset: 0x34 */
__I uint32_t OCRAM_ECC_MULTI_ERROR_DATA_MSB; /**< OCRAM multi-bit ECC Error Data Register, offset: 0x38 */
__I uint32_t ITCM_ECC_SINGLE_ERROR_INFO; /**< ITCM single-bit ECC Error Information Register, offset: 0x3C */
__I uint32_t ITCM_ECC_SINGLE_ERROR_ADDR; /**< ITCM single-bit ECC Error Address Register, offset: 0x40 */
__I uint32_t ITCM_ECC_SINGLE_ERROR_DATA_LSB; /**< ITCM single-bit ECC Error Data Register, offset: 0x44 */
__I uint32_t ITCM_ECC_SINGLE_ERROR_DATA_MSB; /**< ITCM single-bit ECC Error Data Register, offset: 0x48 */
__I uint32_t ITCM_ECC_MULTI_ERROR_INFO; /**< ITCM multi-bit ECC Error Information Register, offset: 0x4C */
__I uint32_t ITCM_ECC_MULTI_ERROR_ADDR; /**< ITCM multi-bit ECC Error Address Register, offset: 0x50 */
__I uint32_t ITCM_ECC_MULTI_ERROR_DATA_LSB; /**< ITCM multi-bit ECC Error Data Register, offset: 0x54 */
__I uint32_t ITCM_ECC_MULTI_ERROR_DATA_MSB; /**< ITCM multi-bit ECC Error Data Register, offset: 0x58 */
__I uint32_t D0TCM_ECC_SINGLE_ERROR_INFO; /**< D0TCM single-bit ECC Error Information Register, offset: 0x5C */
__I uint32_t D0TCM_ECC_SINGLE_ERROR_ADDR; /**< D0TCM single-bit ECC Error Address Register, offset: 0x60 */
__I uint32_t D0TCM_ECC_SINGLE_ERROR_DATA; /**< D0TCM single-bit ECC Error Data Register, offset: 0x64 */
__I uint32_t D0TCM_ECC_MULTI_ERROR_INFO; /**< D0TCM multi-bit ECC Error Information Register, offset: 0x68 */
__I uint32_t D0TCM_ECC_MULTI_ERROR_ADDR; /**< D0TCM multi-bit ECC Error Address Register, offset: 0x6C */
__I uint32_t D0TCM_ECC_MULTI_ERROR_DATA; /**< D0TCM multi-bit ECC Error Data Register, offset: 0x70 */
__I uint32_t D1TCM_ECC_SINGLE_ERROR_INFO; /**< D1TCM single-bit ECC Error Information Register, offset: 0x74 */
__I uint32_t D1TCM_ECC_SINGLE_ERROR_ADDR; /**< D1TCM single-bit ECC Error Address Register, offset: 0x78 */
__I uint32_t D1TCM_ECC_SINGLE_ERROR_DATA; /**< D1TCM single-bit ECC Error Data Register, offset: 0x7C */
__I uint32_t D1TCM_ECC_MULTI_ERROR_INFO; /**< D1TCM multi-bit ECC Error Information Register, offset: 0x80 */
__I uint32_t D1TCM_ECC_MULTI_ERROR_ADDR; /**< D1TCM multi-bit ECC Error Address Register, offset: 0x84 */
__I uint32_t D1TCM_ECC_MULTI_ERROR_DATA; /**< D1TCM multi-bit ECC Error Data Register, offset: 0x88 */
uint8_t RESERVED_0[124];
__IO uint32_t FLEXRAM_CTRL; /**< FlexRAM feature Control register, offset: 0x108 */
__I uint32_t OCRAM_PIPELINE_STATUS; /**< OCRAM Pipeline Status register, offset: 0x10C */
} FLEXRAM_Type;
/* ----------------------------------------------------------------------------
-- FLEXRAM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXRAM_Register_Masks FLEXRAM Register Masks
* @{
*/
/*! @name TCM_CTRL - TCM CRTL Register */
/*! @{ */
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK (0x1U)
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT (0U)
/*! TCM_WWAIT_EN - TCM Write Wait Mode Enable
* 0b0..TCM write fast mode: Write RAM accesses are expected to be finished in 1-cycle.
* 0b1..TCM write wait mode: Write RAM accesses are expected to be finished in 2-cycles.
*/
#define FLEXRAM_TCM_CTRL_TCM_WWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_WWAIT_EN_MASK)
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK (0x2U)
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT (1U)
/*! TCM_RWAIT_EN - TCM Read Wait Mode Enable
* 0b0..TCM read fast mode: Read RAM accesses are expected to be finished in 1-cycle.
* 0b1..TCM read wait mode: Read RAM accesses are expected to be finished in 2-cycles.
*/
#define FLEXRAM_TCM_CTRL_TCM_RWAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_SHIFT)) & FLEXRAM_TCM_CTRL_TCM_RWAIT_EN_MASK)
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK (0x4U)
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT (2U)
/*! FORCE_CLK_ON - Force RAM Clock Always On
*/
#define FLEXRAM_TCM_CTRL_FORCE_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_FORCE_CLK_ON_SHIFT)) & FLEXRAM_TCM_CTRL_FORCE_CLK_ON_MASK)
#define FLEXRAM_TCM_CTRL_Reserved_MASK (0xFFFFFFF8U)
#define FLEXRAM_TCM_CTRL_Reserved_SHIFT (3U)
/*! Reserved - Reserved
*/
#define FLEXRAM_TCM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_TCM_CTRL_Reserved_SHIFT)) & FLEXRAM_TCM_CTRL_Reserved_MASK)
/*! @} */
/*! @name OCRAM_MAGIC_ADDR - OCRAM Magic Address Register */
/*! @{ */
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK (0x1U)
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT (0U)
/*! OCRAM_WR_RD_SEL - OCRAM Write Read Select
* 0b0..When OCRAM read access hits magic address, it will generate interrupt.
* 0b1..When OCRAM write access hits magic address, it will generate interrupt.
*/
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_WR_RD_SEL_MASK)
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK (0x3FFFEU)
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT (1U)
/*! OCRAM_MAGIC_ADDR - OCRAM Magic Address
*/
#define FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_OCRAM_MAGIC_ADDR_MASK)
#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK (0xFFFC0000U)
#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT (18U)
/*! Reserved - Reserved
*/
#define FLEXRAM_OCRAM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_OCRAM_MAGIC_ADDR_Reserved_MASK)
/*! @} */
/*! @name DTCM_MAGIC_ADDR - DTCM Magic Address Register */
/*! @{ */
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK (0x1U)
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT (0U)
/*! DTCM_WR_RD_SEL - DTCM Write Read Select
* 0b0..When DTCM read access hits magic address, it will generate interrupt.
* 0b1..When DTCM write access hits magic address, it will generate interrupt.
*/
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_WR_RD_SEL_MASK)
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK (0x1FFFEU)
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT (1U)
/*! DTCM_MAGIC_ADDR - DTCM Magic Address
*/
#define FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_DTCM_MAGIC_ADDR_MASK)
#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)
#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT (17U)
/*! Reserved - Reserved
*/
#define FLEXRAM_DTCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_DTCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_DTCM_MAGIC_ADDR_Reserved_MASK)
/*! @} */
/*! @name ITCM_MAGIC_ADDR - ITCM Magic Address Register */
/*! @{ */
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK (0x1U)
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT (0U)
/*! ITCM_WR_RD_SEL - ITCM Write Read Select
* 0b0..When ITCM read access hits magic address, it will generate interrupt.
* 0b1..When ITCM write access hits magic address, it will generate interrupt.
*/
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_WR_RD_SEL_MASK)
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK (0x1FFFEU)
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT (1U)
/*! ITCM_MAGIC_ADDR - ITCM Magic Address
*/
#define FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_ITCM_MAGIC_ADDR_MASK)
#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK (0xFFFE0000U)
#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT (17U)
/*! Reserved - Reserved
*/
#define FLEXRAM_ITCM_MAGIC_ADDR_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_MAGIC_ADDR_Reserved_SHIFT)) & FLEXRAM_ITCM_MAGIC_ADDR_Reserved_MASK)
/*! @} */
/*! @name INT_STATUS - Interrupt Status Register */
/*! @{ */
#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK (0x1U)
#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT (0U)
/*! ITCM_MAM_STATUS - ITCM Magic Address Match Status
* 0b0..ITCM did not access magic address.
* 0b1..ITCM accessed magic address.
*/
#define FLEXRAM_INT_STATUS_ITCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_MAM_STATUS_MASK)
#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK (0x2U)
#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT (1U)
/*! DTCM_MAM_STATUS - DTCM Magic Address Match Status
* 0b0..DTCM did not access magic address.
* 0b1..DTCM accessed magic address.
*/
#define FLEXRAM_INT_STATUS_DTCM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_MAM_STATUS_MASK)
#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK (0x4U)
#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT (2U)
/*! OCRAM_MAM_STATUS - OCRAM Magic Address Match Status
* 0b0..OCRAM did not access magic address.
* 0b1..OCRAM accessed magic address.
*/
#define FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_MAM_STATUS_MASK)
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK (0x8U)
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT (3U)
/*! ITCM_ERR_STATUS - ITCM Access Error Status
* 0b0..ITCM access error does not happen
* 0b1..ITCM access error happens.
*/
#define FLEXRAM_INT_STATUS_ITCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ERR_STATUS_MASK)
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK (0x10U)
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT (4U)
/*! DTCM_ERR_STATUS - DTCM Access Error Status
* 0b0..DTCM access error does not happen
* 0b1..DTCM access error happens.
*/
#define FLEXRAM_INT_STATUS_DTCM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_DTCM_ERR_STATUS_MASK)
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK (0x20U)
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT (5U)
/*! OCRAM_ERR_STATUS - OCRAM Access Error Status
* 0b0..OCRAM access error does not happen
* 0b1..OCRAM access error happens.
*/
#define FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ERR_STATUS_MASK)
#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK (0x40U)
#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT (6U)
/*! OCRAM_ECC_ERRM_INT - OCRAM access multi-bit ECC Error Interrupt Status
* 0b0..OCRAM multi-bit ECC error does not happen
* 0b1..OCRAM multi-bit ECC error happens.
*/
#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRM_INT_MASK)
#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK (0x80U)
#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT (7U)
/*! OCRAM_ECC_ERRS_INT - OCRAM access single-bit ECC Error Interrupt Status
* 0b0..OCRAM single-bit ECC error does not happen
* 0b1..OCRAM single-bit ECC error happens.
*/
#define FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_ECC_ERRS_INT_MASK)
#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK (0x100U)
#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT (8U)
/*! ITCM_ECC_ERRM_INT - ITCM Access multi-bit ECC Error Interrupt Status
* 0b0..ITCM multi-bit ECC error does not happen
* 0b1..ITCM multi-bit ECC error happens.
*/
#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRM_INT_MASK)
#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK (0x200U)
#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT (9U)
/*! ITCM_ECC_ERRS_INT - ITCM access single-bit ECC Error Interrupt Status
* 0b0..ITCM single-bit ECC error does not happen
* 0b1..ITCM single-bit ECC error happens.
*/
#define FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_ECC_ERRS_INT_MASK)
#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK (0x400U)
#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT (10U)
/*! D0TCM_ECC_ERRM_INT - D0TCM access multi-bit ECC Error Interrupt Status
* 0b0..D0TCM multi-bit ECC error does not happen
* 0b1..D0TCM multi-bit ECC error happens.
*/
#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRM_INT_MASK)
#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK (0x800U)
#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT (11U)
/*! D0TCM_ECC_ERRS_INT - D0TCM access single-bit ECC Error Interrupt Status
* 0b0..D0TCM single-bit ECC error does not happen
* 0b1..D0TCM single-bit ECC error happens.
*/
#define FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_ECC_ERRS_INT_MASK)
#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK (0x1000U)
#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT (12U)
/*! D1TCM_ECC_ERRM_INT - D1TCM access multi-bit ECC Error Interrupt Status
* 0b0..D1TCM multi-bit ECC error does not happen
* 0b1..D1TCM multi-bit ECC error happens.
*/
#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRM_INT_MASK)
#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK (0x2000U)
#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT (13U)
/*! D1TCM_ECC_ERRS_INT - D1TCM access single-bit ECC Error Interrupt Status
* 0b0..D1TCM single-bit ECC error does not happen
* 0b1..D1TCM single-bit ECC error happens.
*/
#define FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_ECC_ERRS_INT_MASK)
#define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK (0x4000U)
#define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT (14U)
/*! ITCM_PARTIAL_WR_INT_S - ITCM Partial Write Interrupt Status
* 0b0..ITCM Partial Write does not happen
* 0b1..ITCM Partial Write happens.
*/
#define FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_ITCM_PARTIAL_WR_INT_S_MASK)
#define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK (0x8000U)
#define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT (15U)
/*! D0TCM_PARTIAL_WR_INT_S - D0TCM Partial Write Interrupt Status
* 0b0..D0TCM Partial Write does not happen
* 0b1..D0TCM Partial Write happens.
*/
#define FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D0TCM_PARTIAL_WR_INT_S_MASK)
#define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK (0x10000U)
#define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT (16U)
/*! D1TCM_PARTIAL_WR_INT_S - D1TCM Partial Write Interrupt Status
* 0b0..D1TCM Partial Write does not happen
* 0b1..D1TCM Partial Write happens.
*/
#define FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_D1TCM_PARTIAL_WR_INT_S_MASK)
#define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK (0x20000U)
#define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT (17U)
/*! OCRAM_PARTIAL_WR_INT_S - OCRAM Partial Write Interrupt Status
* 0b0..OCRAM Partial Write does not happen
* 0b1..OCRAM Partial Write happens.
*/
#define FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_SHIFT)) & FLEXRAM_INT_STATUS_OCRAM_PARTIAL_WR_INT_S_MASK)
#define FLEXRAM_INT_STATUS_Reserved_MASK (0xFFFC0000U)
#define FLEXRAM_INT_STATUS_Reserved_SHIFT (18U)
/*! Reserved - Reserved
*/
#define FLEXRAM_INT_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STATUS_Reserved_SHIFT)) & FLEXRAM_INT_STATUS_Reserved_MASK)
/*! @} */
/*! @name INT_STAT_EN - Interrupt Status Enable Register */
/*! @{ */
#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK (0x1U)
#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT (0U)
/*! ITCM_MAM_STAT_EN - ITCM Magic Address Match Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_MAM_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK (0x2U)
#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT (1U)
/*! DTCM_MAM_STAT_EN - DTCM Magic Address Match Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_MAM_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK (0x4U)
#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT (2U)
/*! OCRAM_MAM_STAT_EN - OCRAM Magic Address Match Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_MAM_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK (0x8U)
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT (3U)
/*! ITCM_ERR_STAT_EN - ITCM Access Error Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERR_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK (0x10U)
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT (4U)
/*! DTCM_ERR_STAT_EN - DTCM Access Error Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_DTCM_ERR_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK (0x20U)
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT (5U)
/*! OCRAM_ERR_STAT_EN - OCRAM Access Error Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERR_STAT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK (0x40U)
#define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT (6U)
/*! OCRAM_ERRM_INT_EN - OCRAM Access multi-bit ECC Error Interrupt Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRM_INT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK (0x80U)
#define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT (7U)
/*! OCRAM_ERRS_INT_EN - OCRAM Access single-bit ECC Error Interrupt Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_ERRS_INT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK (0x100U)
#define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT (8U)
/*! ITCM_ERRM_INT_EN - ITCM Access multi-bit ECC Error Interrupt Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRM_INT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK (0x200U)
#define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT (9U)
/*! ITCM_ERRS_INT_EN - ITCM Access single-bit ECC Error Interrupt Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_ERRS_INT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK (0x400U)
#define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT (10U)
/*! D0TCM_ERRM_INT_EN - D0TCM Access multi-bit ECC Error Interrupt Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRM_INT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK (0x800U)
#define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT (11U)
/*! D0TCM_ERRS_INT_EN - D0TCM Access single-bit ECC Error Interrupt Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_ERRS_INT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK (0x1000U)
#define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT (12U)
/*! D1TCM_ERRM_INT_EN - D1TCM Access multi-bit ECC Error Interrupt Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRM_INT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK (0x2000U)
#define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT (13U)
/*! D1TCM_ERRS_INT_EN - D1TCM Access single-bit ECC Error Interrupt Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_ERRS_INT_EN_MASK)
#define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK (0x4000U)
#define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT (14U)
/*! ITCM_PARTIAL_WR_INT_S_EN - ITCM Partial Write Interrupt Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_ITCM_PARTIAL_WR_INT_S_EN_MASK)
#define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK (0x8000U)
#define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT (15U)
/*! D0TCM_PARTIAL_WR_INT_S_EN - D0TCM Partial Write Interrupt Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D0TCM_PARTIAL_WR_INT_S_EN_MASK)
#define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK (0x10000U)
#define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT (16U)
/*! D1TCM_PARTIAL_WR_INT_S_EN - D1TCM Partial Write Interrupt Status EN
* 0b0..Masked
* 0b1..Enbaled
*/
#define FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_D1TCM_PARTIAL_WR_INT_S_EN_MASK)
#define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK (0x20000U)
#define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT (17U)
/*! OCRAM_PARTIAL_WR_INT_S_EN - OCRAM Partial Write Interrupt Status
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_SHIFT)) & FLEXRAM_INT_STAT_EN_OCRAM_PARTIAL_WR_INT_S_EN_MASK)
#define FLEXRAM_INT_STAT_EN_Reserved_MASK (0xFFFC0000U)
#define FLEXRAM_INT_STAT_EN_Reserved_SHIFT (18U)
/*! Reserved - Reserved
*/
#define FLEXRAM_INT_STAT_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_STAT_EN_Reserved_SHIFT)) & FLEXRAM_INT_STAT_EN_Reserved_MASK)
/*! @} */
/*! @name INT_SIG_EN - Interrupt Enable Register */
/*! @{ */
#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK (0x1U)
#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT (0U)
/*! ITCM_MAM_SIG_EN - ITCM Magic Address Match Interrupt Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_MAM_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK (0x2U)
#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT (1U)
/*! DTCM_MAM_SIG_EN - DTCM Magic Address Match Interrupt Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_MAM_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK (0x4U)
#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT (2U)
/*! OCRAM_MAM_SIG_EN - OCRAM Magic Address Match Interrupt Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_MAM_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK (0x8U)
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT (3U)
/*! ITCM_ERR_SIG_EN - ITCM Access Error Interrupt Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERR_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK (0x10U)
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT (4U)
/*! DTCM_ERR_SIG_EN - DTCM Access Error Interrupt Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_DTCM_ERR_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK (0x20U)
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT (5U)
/*! OCRAM_ERR_SIG_EN - OCRAM Access Error Interrupt Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERR_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK (0x40U)
#define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT (6U)
/*! OCRAM_ERRM_INT_SIG_EN - OCRAM Access multi-bit ECC Error Interrupt Signal Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRM_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK (0x80U)
#define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT (7U)
/*! OCRAM_ERRS_INT_SIG_EN - OCRAM Access single-bit ECC Error Interrupt Signal Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_ERRS_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK (0x100U)
#define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT (8U)
/*! ITCM_ERRM_INT_SIG_EN - ITCM Access multi-bit ECC Error Interrupt Signal Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRM_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK (0x200U)
#define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT (9U)
/*! ITCM_ERRS_INT_SIG_EN - ITCM Access single-bit ECC Error Interrupt Signal Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_ERRS_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK (0x400U)
#define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT (10U)
/*! D0TCM_ERRM_INT_SIG_EN - D0TCM Access multi-bit ECC Error Interrupt Signal Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRM_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK (0x800U)
#define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT (11U)
/*! D0TCM_ERRS_INT_SIG_EN - D0TCM Access single-bit ECC Error Interrupt Signal Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_ERRS_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK (0x1000U)
#define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT (12U)
/*! D1TCM_ERRM_INT_SIG_EN - D1TCM Access multi-bit ECC Error Interrupt Signal Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRM_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK (0x2000U)
#define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT (13U)
/*! D1TCM_ERRS_INT_SIG_EN - D1TCM Access single-bit ECC Error Interrupt Signal Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_ERRS_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK (0x4000U)
#define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT (14U)
/*! ITCM_PARTIAL_WR_INT_SIG_EN - ITCM Partial Write Interrupt Signal Enable Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_ITCM_PARTIAL_WR_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x8000U)
#define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (15U)
/*! D0TCM_PARTIAL_WR_INT_SIG_EN - D0TCM Partial Write Interrupt Signal Enable Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D0TCM_PARTIAL_WR_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK (0x10000U)
#define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT (16U)
/*! D1TCM_PARTIAL_WR_INT_SIG_EN - D1TCM Partial Write Interrupt Signal Enable EN
* 0b0..Masked
* 0b1..Enbaled
*/
#define FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_D1TCM_PARTIAL_WR_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK (0x20000U)
#define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT (17U)
/*! OCRAM_PARTIAL_WR_INT_SIG_EN - OCRAM Partial Write Interrupt Signal Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_SHIFT)) & FLEXRAM_INT_SIG_EN_OCRAM_PARTIAL_WR_INT_SIG_EN_MASK)
#define FLEXRAM_INT_SIG_EN_Reserved_MASK (0xFFFC0000U)
#define FLEXRAM_INT_SIG_EN_Reserved_SHIFT (18U)
/*! Reserved - Reserved
*/
#define FLEXRAM_INT_SIG_EN_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_INT_SIG_EN_Reserved_SHIFT)) & FLEXRAM_INT_SIG_EN_Reserved_MASK)
/*! @} */
/*! @name OCRAM_ECC_SINGLE_ERROR_INFO - OCRAM single-bit ECC Error Information Register */
/*! @{ */
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK (0xFFU)
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT (0U)
/*! OCRAM_ECCS_ERRED_ECC - corresponding ECC cipher of OCRAM single-bit ECC error
*/
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_ECC_MASK)
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK (0xFF00U)
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT (8U)
/*! OCRAM_ECCS_ERRED_SYN - corresponding ECC syndrome of OCRAM single-bit ECC error
*/
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_OCRAM_ECCS_ERRED_SYN_MASK)
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFFF0000U)
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (16U)
/*! Reserved - Reserved
*/
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
/*! @} */
/*! @name OCRAM_ECC_SINGLE_ERROR_ADDR - OCRAM single-bit ECC Error Address Register */
/*! @{ */
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT (0U)
/*! OCRAM_ECCS_ERRED_ADDR - OCRAM single-bit ECC error address
*/
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_ADDR_OCRAM_ECCS_ERRED_ADDR_MASK)
/*! @} */
/*! @name OCRAM_ECC_SINGLE_ERROR_DATA_LSB - OCRAM single-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT (0U)
/*! OCRAM_ECCS_ERRED_DATA_LSB - OCRAM single-bit ECC error data [31:0]
*/
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_LSB_OCRAM_ECCS_ERRED_DATA_LSB_MASK)
/*! @} */
/*! @name OCRAM_ECC_SINGLE_ERROR_DATA_MSB - OCRAM single-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT (0U)
/*! OCRAM_ECCS_ERRED_DATA_MSB - OCRAM single-bit ECC error data [63:32]
*/
#define FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_SINGLE_ERROR_DATA_MSB_OCRAM_ECCS_ERRED_DATA_MSB_MASK)
/*! @} */
/*! @name OCRAM_ECC_MULTI_ERROR_INFO - OCRAM multi-bit ECC Error Information Register */
/*! @{ */
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK (0xFFU)
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT (0U)
/*! OCRAM_ECCM_ERRED_ECC - OCRAM multi-bit ECC error corresponding ECC value
*/
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_OCRAM_ECCM_ERRED_ECC_MASK)
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFFFFF00U)
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (8U)
/*! Reserved - Reserved
*/
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
/*! @} */
/*! @name OCRAM_ECC_MULTI_ERROR_ADDR - OCRAM multi-bit ECC Error Address Register */
/*! @{ */
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT (0U)
/*! OCRAM_ECCM_ERRED_ADDR - OCRAM multi-bit ECC error address
*/
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_ADDR_OCRAM_ECCM_ERRED_ADDR_MASK)
/*! @} */
/*! @name OCRAM_ECC_MULTI_ERROR_DATA_LSB - OCRAM multi-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT (0U)
/*! OCRAM_ECCM_ERRED_DATA_LSB - OCRAM multi-bit ECC error data [31:0]
*/
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_LSB_OCRAM_ECCM_ERRED_DATA_LSB_MASK)
/*! @} */
/*! @name OCRAM_ECC_MULTI_ERROR_DATA_MSB - OCRAM multi-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT (0U)
/*! OCRAM_ECCM_ERRED_DATA_MSB - OCRAM multi-bit ECC error data [63:32]
*/
#define FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_OCRAM_ECC_MULTI_ERROR_DATA_MSB_OCRAM_ECCM_ERRED_DATA_MSB_MASK)
/*! @} */
/*! @name ITCM_ECC_SINGLE_ERROR_INFO - ITCM single-bit ECC Error Information Register */
/*! @{ */
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK (0x1U)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT (0U)
/*! ITCM_ECCS_EFW - ITCM single-bit ECC error corresponding TCM_WR value.
*/
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFW_MASK)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK (0xEU)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT (1U)
/*! ITCM_ECCS_EFSIZ - ITCM single-bit ECC error corresponding TCM size
*/
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSIZ_MASK)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK (0xF0U)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT (4U)
/*! ITCM_ECCS_EFMST - ITCM single-bit ECC error corresponding TCM_MASTER.
*/
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFMST_MASK)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK (0xF00U)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT (8U)
/*! ITCM_ECCS_EFPRT - ITCM single-bit ECC error corresponding TCM_PRIV.
*/
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFPRT_MASK)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK (0xFF000U)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT (12U)
/*! ITCM_ECCS_EFSYN - ITCM single-bit ECC error corresponding syndrome
*/
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_ITCM_ECCS_EFSYN_MASK)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF00000U)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (20U)
/*! Reserved - Reserved
*/
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
/*! @} */
/*! @name ITCM_ECC_SINGLE_ERROR_ADDR - ITCM single-bit ECC Error Address Register */
/*! @{ */
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT (0U)
/*! ITCM_ECCS_ERRED_ADDR - ITCM single-bit ECC error address
*/
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_ADDR_ITCM_ECCS_ERRED_ADDR_MASK)
/*! @} */
/*! @name ITCM_ECC_SINGLE_ERROR_DATA_LSB - ITCM single-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT (0U)
/*! ITCM_ECCS_ERRED_DATA_LSB - ITCM single-bit ECC error data [31:0]
*/
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_LSB_ITCM_ECCS_ERRED_DATA_LSB_MASK)
/*! @} */
/*! @name ITCM_ECC_SINGLE_ERROR_DATA_MSB - ITCM single-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT (0U)
/*! ITCM_ECCS_ERRED_DATA_MSB - ITCM single-bit ECC error data [63:32]
*/
#define FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_SINGLE_ERROR_DATA_MSB_ITCM_ECCS_ERRED_DATA_MSB_MASK)
/*! @} */
/*! @name ITCM_ECC_MULTI_ERROR_INFO - ITCM multi-bit ECC Error Information Register */
/*! @{ */
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK (0x1U)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT (0U)
/*! ITCM_ECCM_EFW - ITCM multi-bit ECC error corresponding TCM_WR value
*/
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFW_MASK)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK (0xEU)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT (1U)
/*! ITCM_ECCM_EFSIZ - ITCM multi-bit ECC error corresponding tcm access size
*/
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSIZ_MASK)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK (0xF0U)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT (4U)
/*! ITCM_ECCM_EFMST - ITCM multi-bit ECC error corresponding TCM_MASTER
*/
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFMST_MASK)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK (0xF00U)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT (8U)
/*! ITCM_ECCM_EFPRT - ITCM multi-bit ECC error corresponding TCM_PRIV
*/
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFPRT_MASK)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK (0xFF000U)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT (12U)
/*! ITCM_ECCM_EFSYN - ITCM multi-bit ECC error corresponding syndrome
*/
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_ITCM_ECCM_EFSYN_MASK)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF00000U)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (20U)
/*! Reserved - Reserved
*/
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
/*! @} */
/*! @name ITCM_ECC_MULTI_ERROR_ADDR - ITCM multi-bit ECC Error Address Register */
/*! @{ */
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT (0U)
/*! ITCM_ECCM_ERRED_ADDR - ITCM multi-bit ECC error address
*/
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_ADDR_ITCM_ECCM_ERRED_ADDR_MASK)
/*! @} */
/*! @name ITCM_ECC_MULTI_ERROR_DATA_LSB - ITCM multi-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK (0xFFFFFFFFU)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT (0U)
/*! ITCM_ECCM_ERRED_DATA_LSB - ITCM multi-bit ECC error data [31:0]
*/
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_LSB_ITCM_ECCM_ERRED_DATA_LSB_MASK)
/*! @} */
/*! @name ITCM_ECC_MULTI_ERROR_DATA_MSB - ITCM multi-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK (0xFFFFFFFFU)
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT (0U)
/*! ITCM_ECCM_ERRED_DATA_MSB - ITCM multi-bit ECC error data [63:32]
*/
#define FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_SHIFT)) & FLEXRAM_ITCM_ECC_MULTI_ERROR_DATA_MSB_ITCM_ECCM_ERRED_DATA_MSB_MASK)
/*! @} */
/*! @name D0TCM_ECC_SINGLE_ERROR_INFO - D0TCM single-bit ECC Error Information Register */
/*! @{ */
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK (0x1U)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT (0U)
/*! D0TCM_ECCS_EFW - D0TCM single-bit ECC error corresponding TCM_WR value
*/
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFW_MASK)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK (0xEU)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT (1U)
/*! D0TCM_ECCS_EFSIZ - D0TCM single-bit ECC error corresponding tcm access size
*/
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSIZ_MASK)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK (0xF0U)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT (4U)
/*! D0TCM_ECCS_EFMST - D0TCM single-bit ECC error corresponding TCM_MASTER
*/
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFMST_MASK)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK (0xF00U)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT (8U)
/*! D0TCM_ECCS_EFPRT - D0TCM single-bit ECC error corresponding TCM_PRIV
*/
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFPRT_MASK)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK (0x7F000U)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT (12U)
/*! D0TCM_ECCS_EFSYN - D0TCM single-bit ECC error corresponding syndrome
*/
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_D0TCM_ECCS_EFSYN_MASK)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U)
/*! Reserved - Reserved
*/
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
/*! @} */
/*! @name D0TCM_ECC_SINGLE_ERROR_ADDR - D0TCM single-bit ECC Error Address Register */
/*! @{ */
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT (0U)
/*! D0TCM_ECCS_ERRED_ADDR - D0TCM single-bit ECC error address
*/
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_ADDR_D0TCM_ECCS_ERRED_ADDR_MASK)
/*! @} */
/*! @name D0TCM_ECC_SINGLE_ERROR_DATA - D0TCM single-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU)
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT (0U)
/*! D0TCM_ECCS_ERRED_DATA - D0TCM single-bit ECC error data
*/
#define FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_SINGLE_ERROR_DATA_D0TCM_ECCS_ERRED_DATA_MASK)
/*! @} */
/*! @name D0TCM_ECC_MULTI_ERROR_INFO - D0TCM multi-bit ECC Error Information Register */
/*! @{ */
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK (0x1U)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT (0U)
/*! D0TCM_ECCM_EFW - D0TCM multi-bit ECC error corresponding TCM_WR value
*/
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFW_MASK)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK (0xEU)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT (1U)
/*! D0TCM_ECCM_EFSIZ - D0TCM multi-bit ECC error corresponding tcm access size
*/
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSIZ_MASK)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK (0xF0U)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT (4U)
/*! D0TCM_ECCM_EFMST - D0TCM multi-bit ECC error corresponding TCM_MASTER
*/
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFMST_MASK)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK (0xF00U)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT (8U)
/*! D0TCM_ECCM_EFPRT - D0TCM multi-bit ECC error corresponding TCM_PRIV
*/
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFPRT_MASK)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK (0x7F000U)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT (12U)
/*! D0TCM_ECCM_EFSYN - D0TCM multi-bit ECC error corresponding syndrome
*/
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_D0TCM_ECCM_EFSYN_MASK)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U)
/*! Reserved - Reserved
*/
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
/*! @} */
/*! @name D0TCM_ECC_MULTI_ERROR_ADDR - D0TCM multi-bit ECC Error Address Register */
/*! @{ */
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT (0U)
/*! D0TCM_ECCM_ERRED_ADDR - D0TCM multi-bit ECC error address
*/
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_ADDR_D0TCM_ECCM_ERRED_ADDR_MASK)
/*! @} */
/*! @name D0TCM_ECC_MULTI_ERROR_DATA - D0TCM multi-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT (0U)
/*! D0TCM_ECCM_ERRED_DATA - D0TCM multi-bit ECC error data
*/
#define FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D0TCM_ECC_MULTI_ERROR_DATA_D0TCM_ECCM_ERRED_DATA_MASK)
/*! @} */
/*! @name D1TCM_ECC_SINGLE_ERROR_INFO - D1TCM single-bit ECC Error Information Register */
/*! @{ */
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK (0x1U)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT (0U)
/*! D1TCM_ECCS_EFW - D1TCM single-bit ECC error corresponding TCM_WR value
*/
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFW_MASK)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK (0xEU)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT (1U)
/*! D1TCM_ECCS_EFSIZ - D1TCM single-bit ECC error corresponding tcm access size
*/
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSIZ_MASK)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK (0xF0U)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT (4U)
/*! D1TCM_ECCS_EFMST - D1TCM single-bit ECC error corresponding TCM_MASTER
*/
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFMST_MASK)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK (0xF00U)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT (8U)
/*! D1TCM_ECCS_EFPRT - D1TCM single-bit ECC error corresponding TCM_PRIV
*/
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFPRT_MASK)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK (0x7F000U)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT (12U)
/*! D1TCM_ECCS_EFSYN - D1TCM single-bit ECC error corresponding syndrome
*/
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_D1TCM_ECCS_EFSYN_MASK)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK (0xFFF80000U)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT (19U)
/*! Reserved - Reserved
*/
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_INFO_Reserved_MASK)
/*! @} */
/*! @name D1TCM_ECC_SINGLE_ERROR_ADDR - D1TCM single-bit ECC Error Address Register */
/*! @{ */
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK (0xFFFFFFFFU)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT (0U)
/*! D1TCM_ECCS_ERRED_ADDR - D1TCM single-bit ECC error address
*/
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_ADDR_D1TCM_ECCS_ERRED_ADDR_MASK)
/*! @} */
/*! @name D1TCM_ECC_SINGLE_ERROR_DATA - D1TCM single-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK (0xFFFFFFFFU)
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT (0U)
/*! D1TCM_ECCS_ERRED_DATA - D1TCM single-bit ECC error data
*/
#define FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_SINGLE_ERROR_DATA_D1TCM_ECCS_ERRED_DATA_MASK)
/*! @} */
/*! @name D1TCM_ECC_MULTI_ERROR_INFO - D1TCM multi-bit ECC Error Information Register */
/*! @{ */
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK (0x1U)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT (0U)
/*! D1TCM_ECCM_EFW - D1TCM multi-bit ECC error corresponding TCM_WR value
*/
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFW_MASK)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK (0xEU)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT (1U)
/*! D1TCM_ECCM_EFSIZ - D1TCM multi-bit ECC error corresponding tcm access size
*/
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSIZ_MASK)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK (0xF0U)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT (4U)
/*! D1TCM_ECCM_EFMST - D1TCM multi-bit ECC error corresponding TCM_MASTER
*/
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFMST_MASK)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK (0xF00U)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT (8U)
/*! D1TCM_ECCM_EFPRT - D1TCM multi-bit ECC error corresponding TCM_PRIV
*/
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFPRT_MASK)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK (0x7F000U)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT (12U)
/*! D1TCM_ECCM_EFSYN - D1TCM multi-bit ECC error corresponding syndrome
*/
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_D1TCM_ECCM_EFSYN_MASK)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK (0xFFF80000U)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT (19U)
/*! Reserved - Reserved
*/
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_INFO_Reserved_MASK)
/*! @} */
/*! @name D1TCM_ECC_MULTI_ERROR_ADDR - D1TCM multi-bit ECC Error Address Register */
/*! @{ */
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK (0xFFFFFFFFU)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT (0U)
/*! D1TCM_ECCM_ERRED_ADDR - D1TCM multi-bit ECC error address
*/
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_ADDR_D1TCM_ECCM_ERRED_ADDR_MASK)
/*! @} */
/*! @name D1TCM_ECC_MULTI_ERROR_DATA - D1TCM multi-bit ECC Error Data Register */
/*! @{ */
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK (0xFFFFFFFFU)
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT (0U)
/*! D1TCM_ECCM_ERRED_DATA - D1TCM multi-bit ECC error data
*/
#define FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_SHIFT)) & FLEXRAM_D1TCM_ECC_MULTI_ERROR_DATA_D1TCM_ECCM_ERRED_DATA_MASK)
/*! @} */
/*! @name FLEXRAM_CTRL - FlexRAM feature Control register */
/*! @{ */
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK (0x1U)
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT (0U)
/*! OCRAM_RDATA_WAIT_EN - Read Data Wait Enable
*/
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RDATA_WAIT_EN_MASK)
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK (0x2U)
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT (1U)
/*! OCRAM_RADDR_PIPELINE_EN - Read Address Pipeline Enable
*/
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_RADDR_PIPELINE_EN_MASK)
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK (0x4U)
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT (2U)
/*! OCRAM_WRDATA_PIPELINE_EN - Write Data Pipeline Enable
*/
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRDATA_PIPELINE_EN_MASK)
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK (0x8U)
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT (3U)
/*! OCRAM_WRADDR_PIPELINE_EN - Write Address Pipeline Enable
*/
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_WRADDR_PIPELINE_EN_MASK)
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK (0x10U)
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT (4U)
/*! OCRAM_ECC_EN - OCRAM ECC enable
*/
#define FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_OCRAM_ECC_EN_MASK)
#define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK (0x20U)
#define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT (5U)
/*! TCM_ECC_EN - TCM ECC enable
*/
#define FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_TCM_ECC_EN_MASK)
#define FLEXRAM_FLEXRAM_CTRL_Reserved_MASK (0xFFFFFFC0U)
#define FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT (6U)
/*! Reserved - Reserved
*/
#define FLEXRAM_FLEXRAM_CTRL_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_FLEXRAM_CTRL_Reserved_SHIFT)) & FLEXRAM_FLEXRAM_CTRL_Reserved_MASK)
/*! @} */
/*! @name OCRAM_PIPELINE_STATUS - OCRAM Pipeline Status register */
/*! @{ */
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK (0x1U)
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT (0U)
/*! OCRAM_RDATA_WAIT_EN_UPDATA_PENDING - Read Data Wait Enable Pending
*/
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RDATA_WAIT_EN_UPDATA_PENDING_MASK)
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x2U)
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (1U)
/*! OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING - Read Address Pipeline Enable Pending
*/
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_RADDR_PIPELINE_EN_UPDATA_PENDING_MASK)
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK (0x4U)
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT (2U)
/*! OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING - Write Data Pipeline Enable Pending
*/
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRDATA_PIPELINE_EN_UPDATA_PENDING_MASK)
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK (0x8U)
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT (3U)
/*! OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING - Write Address Pipeline Enable Pending
*/
#define FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_OCRAM_WRADDR_PIPELINE_EN_UPDATA_PENDING_MASK)
#define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK (0xFFFFFFF0U)
#define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT (4U)
/*! Reserved - Reserved
*/
#define FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved(x) (((uint32_t)(((uint32_t)(x)) << FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_SHIFT)) & FLEXRAM_OCRAM_PIPELINE_STATUS_Reserved_MASK)
/*! @} */
/*!
* @}
*/ /* end of group FLEXRAM_Register_Masks */
/* FLEXRAM - Peripheral instance base addresses */
/** Peripheral FLEXRAM base address */
#define FLEXRAM_BASE (0x40028000u)
/** Peripheral FLEXRAM base pointer */
#define FLEXRAM ((FLEXRAM_Type *)FLEXRAM_BASE)
/** Array initializer of FLEXRAM peripheral base addresses */
#define FLEXRAM_BASE_ADDRS { FLEXRAM_BASE }
/** Array initializer of FLEXRAM peripheral base pointers */
#define FLEXRAM_BASE_PTRS { FLEXRAM }
/** Interrupt vectors for the FLEXRAM peripheral type */
#define FLEXRAM_IRQS { FLEXRAM_IRQn }
#define FLEXRAM_ECC_IRQS { FLEXRAM_ECC_IRQn }
/*!
* @}
*/ /* end of group FLEXRAM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- FLEXSPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXSPI_Peripheral_Access_Layer FLEXSPI Peripheral Access Layer
* @{
*/
/** FLEXSPI - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR0; /**< Module Control Register 0, offset: 0x0 */
__IO uint32_t MCR1; /**< Module Control Register 1, offset: 0x4 */
__IO uint32_t MCR2; /**< Module Control Register 2, offset: 0x8 */
__IO uint32_t AHBCR; /**< AHB Bus Control Register, offset: 0xC */
__IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x10 */
__IO uint32_t INTR; /**< Interrupt Register, offset: 0x14 */
__IO uint32_t LUTKEY; /**< LUT Key Register, offset: 0x18 */
__IO uint32_t LUTCR; /**< LUT Control Register, offset: 0x1C */
__IO uint32_t AHBRXBUFCR0[8]; /**< AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0, array offset: 0x20, array step: 0x4 */
uint8_t RESERVED_0[32];
__IO uint32_t FLSHCR0[4]; /**< Flash Control Register 0, array offset: 0x60, array step: 0x4 */
__IO uint32_t FLSHCR1[4]; /**< Flash Control Register 1, array offset: 0x70, array step: 0x4 */
__IO uint32_t FLSHCR2[4]; /**< Flash Control Register 2, array offset: 0x80, array step: 0x4 */
uint8_t RESERVED_1[4];
__IO uint32_t FLSHCR4; /**< Flash Control Register 4, offset: 0x94 */
uint8_t RESERVED_2[8];
__IO uint32_t IPCR0; /**< IP Control Register 0, offset: 0xA0 */
__IO uint32_t IPCR1; /**< IP Control Register 1, offset: 0xA4 */
uint8_t RESERVED_3[8];
__IO uint32_t IPCMD; /**< IP Command Register, offset: 0xB0 */
uint8_t RESERVED_4[4];
__IO uint32_t IPRXFCR; /**< IP RX FIFO Control Register, offset: 0xB8 */
__IO uint32_t IPTXFCR; /**< IP TX FIFO Control Register, offset: 0xBC */
__IO uint32_t DLLCR[2]; /**< DLL Control Register 0, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_5[8];
__I uint32_t MISCCR4; /**< Misc Control Register 4, offset: 0xD0 */
__I uint32_t MISCCR5; /**< Misc Control Register 5, offset: 0xD4 */
__I uint32_t MISCCR6; /**< Misc Control Register 6, offset: 0xD8 */
__I uint32_t MISCCR7; /**< Misc Control Register 7, offset: 0xDC */
__I uint32_t STS0; /**< Status Register 0, offset: 0xE0 */
__I uint32_t STS1; /**< Status Register 1, offset: 0xE4 */
__I uint32_t STS2; /**< Status Register 2, offset: 0xE8 */
__I uint32_t AHBSPNDSTS; /**< AHB Suspend Status Register, offset: 0xEC */
__I uint32_t IPRXFSTS; /**< IP RX FIFO Status Register, offset: 0xF0 */
__I uint32_t IPTXFSTS; /**< IP TX FIFO Status Register, offset: 0xF4 */
uint8_t RESERVED_6[8];
__I uint32_t RFDR[32]; /**< IP RX FIFO Data Register 0..IP RX FIFO Data Register 31, array offset: 0x100, array step: 0x4 */
__O uint32_t TFDR[32]; /**< IP TX FIFO Data Register 0..IP TX FIFO Data Register 31, array offset: 0x180, array step: 0x4 */
__IO uint32_t LUT[64]; /**< LUT 0..LUT 63, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_7[256];
__IO uint32_t HMSTRCR[8]; /**< AHB Master ID 0 Control Register..AHB Master ID 7 Control Register, array offset: 0x400, array step: 0x4 */
__IO uint32_t HADDRSTART; /**< HADDR REMAP START ADDR, offset: 0x420 */
__IO uint32_t HADDREND; /**< HADDR REMAP END ADDR, offset: 0x424 */
__IO uint32_t HADDROFFSET; /**< HADDR REMAP OFFSET, offset: 0x428 */
uint8_t RESERVED_8[4];
__IO uint32_t IPSNSZSTART0; /**< IPS nonsecure region Start address of region 0, offset: 0x430 */
__IO uint32_t IPSNSZEND0; /**< IPS nonsecure region End address of region 0, offset: 0x434 */
__IO uint32_t IPSNSZSTART1; /**< IPS nonsecure region Start address of region 1, offset: 0x438 */
__IO uint32_t IPSNSZEND1; /**< IPS nonsecure region End address of region 1, offset: 0x43C */
__IO uint32_t AHBBUFREGIONSTART0; /**< RX BUF Start address of region 0, offset: 0x440 */
__IO uint32_t AHBBUFREGIONEND0; /**< RX BUF region End address of region 0, offset: 0x444 */
__IO uint32_t AHBBUFREGIONSTART1; /**< RX BUF Start address of region 1, offset: 0x448 */
__IO uint32_t AHBBUFREGIONEND1; /**< RX BUF region End address of region 1, offset: 0x44C */
__IO uint32_t AHBBUFREGIONSTART2; /**< RX BUF Start address of region 2, offset: 0x450 */
__IO uint32_t AHBBUFREGIONEND2; /**< RX BUF region End address of region 2, offset: 0x454 */
__IO uint32_t AHBBUFREGIONSTART3; /**< RX BUF Start address of region 3, offset: 0x458 */
__IO uint32_t AHBBUFREGIONEND3; /**< RX BUF region End address of region 3, offset: 0x45C */
} FLEXSPI_Type;
/* ----------------------------------------------------------------------------
-- FLEXSPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup FLEXSPI_Register_Masks FLEXSPI Register Masks
* @{
*/
/*! @name MCR0 - Module Control Register 0 */
/*! @{ */
#define FLEXSPI_MCR0_SWRESET_MASK (0x1U)
#define FLEXSPI_MCR0_SWRESET_SHIFT (0U)
/*! SWRESET - Software Reset
*/
#define FLEXSPI_MCR0_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SWRESET_SHIFT)) & FLEXSPI_MCR0_SWRESET_MASK)
#define FLEXSPI_MCR0_MDIS_MASK (0x2U)
#define FLEXSPI_MCR0_MDIS_SHIFT (1U)
/*! MDIS - Module Disable
*/
#define FLEXSPI_MCR0_MDIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_MDIS_SHIFT)) & FLEXSPI_MCR0_MDIS_MASK)
#define FLEXSPI_MCR0_RXCLKSRC_MASK (0x30U)
#define FLEXSPI_MCR0_RXCLKSRC_SHIFT (4U)
/*! RXCLKSRC - Sample Clock source selection for Flash Reading
* 0b00..Dummy Read strobe generated by FlexSPI Controller and loopback internally.
* 0b01..Dummy Read strobe generated by FlexSPI Controller and loopback from DQS pad.
* 0b10..Reserved
* 0b11..Flash provided Read strobe and input from DQS pad
*/
#define FLEXSPI_MCR0_RXCLKSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_RXCLKSRC_SHIFT)) & FLEXSPI_MCR0_RXCLKSRC_MASK)
#define FLEXSPI_MCR0_ARDFEN_MASK (0x40U)
#define FLEXSPI_MCR0_ARDFEN_SHIFT (6U)
/*! ARDFEN - Enable AHB bus Read Access to IP RX FIFO.
* 0b0..IP RX FIFO should be read by IP Bus. AHB Bus read access to IP RX FIFO memory space will get bus error response.
* 0b1..IP RX FIFO should be read by AHB Bus. IP Bus read access to IP RX FIFO memory space will always return data zero but no bus error response.
*/
#define FLEXSPI_MCR0_ARDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ARDFEN_SHIFT)) & FLEXSPI_MCR0_ARDFEN_MASK)
#define FLEXSPI_MCR0_ATDFEN_MASK (0x80U)
#define FLEXSPI_MCR0_ATDFEN_SHIFT (7U)
/*! ATDFEN - Enable AHB bus Write Access to IP TX FIFO.
* 0b0..IP TX FIFO should be written by IP Bus. AHB Bus write access to IP TX FIFO memory space will get bus error response.
* 0b1..IP TX FIFO should be written by AHB Bus. IP Bus write access to IP TX FIFO memory space will be ignored but no bus error response.
*/
#define FLEXSPI_MCR0_ATDFEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_ATDFEN_SHIFT)) & FLEXSPI_MCR0_ATDFEN_MASK)
#define FLEXSPI_MCR0_SERCLKDIV_MASK (0x700U)
#define FLEXSPI_MCR0_SERCLKDIV_SHIFT (8U)
/*! SERCLKDIV - The serial root clock could be divided inside FlexSPI . Refer Clocks chapter for more details on clocking.
* 0b000..Divided by 1
* 0b001..Divided by 2
* 0b010..Divided by 3
* 0b011..Divided by 4
* 0b100..Divided by 5
* 0b101..Divided by 6
* 0b110..Divided by 7
* 0b111..Divided by 8
*/
#define FLEXSPI_MCR0_SERCLKDIV(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SERCLKDIV_SHIFT)) & FLEXSPI_MCR0_SERCLKDIV_MASK)
#define FLEXSPI_MCR0_HSEN_MASK (0x800U)
#define FLEXSPI_MCR0_HSEN_SHIFT (11U)
/*! HSEN - Half Speed Serial Flash access Enable.
* 0b0..Disable divide by 2 of serial flash clock for half speed commands.
* 0b1..Enable divide by 2 of serial flash clock for half speed commands.
*/
#define FLEXSPI_MCR0_HSEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_HSEN_SHIFT)) & FLEXSPI_MCR0_HSEN_MASK)
#define FLEXSPI_MCR0_DOZEEN_MASK (0x1000U)
#define FLEXSPI_MCR0_DOZEEN_SHIFT (12U)
/*! DOZEEN - Doze mode enable bit
* 0b0..Doze mode support disabled. AHB clock and serial clock will not be gated off when there is doze mode request from system.
* 0b1..Doze mode support enabled. AHB clock and serial clock will be gated off when there is doze mode request from system.
*/
#define FLEXSPI_MCR0_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_DOZEEN_SHIFT)) & FLEXSPI_MCR0_DOZEEN_MASK)
#define FLEXSPI_MCR0_COMBINATIONEN_MASK (0x2000U)
#define FLEXSPI_MCR0_COMBINATIONEN_SHIFT (13U)
/*! COMBINATIONEN - This bit is to support Flash Octal mode access by combining Port A and B Data
* pins (A_DATA[3:0] and B_DATA[3:0]), when Port A and Port B are of 4 bit data width.
* 0b0..Disable.
* 0b1..Enable.
*/
#define FLEXSPI_MCR0_COMBINATIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_COMBINATIONEN_SHIFT)) & FLEXSPI_MCR0_COMBINATIONEN_MASK)
#define FLEXSPI_MCR0_SCKFREERUNEN_MASK (0x4000U)
#define FLEXSPI_MCR0_SCKFREERUNEN_SHIFT (14U)
/*! SCKFREERUNEN - This bit is used to force SCLK output free-running. For FPGA applications,
* external device may use SCLK as reference clock to its internal PLL. If SCLK free-running is
* enabled, data sampling with loopback clock from SCLK pad is not supported (MCR0[RXCLKSRC]=2).
* 0b0..Disable.
* 0b1..Enable.
*/
#define FLEXSPI_MCR0_SCKFREERUNEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_SCKFREERUNEN_SHIFT)) & FLEXSPI_MCR0_SCKFREERUNEN_MASK)
#define FLEXSPI_MCR0_IPGRANTWAIT_MASK (0xFF0000U)
#define FLEXSPI_MCR0_IPGRANTWAIT_SHIFT (16U)
/*! IPGRANTWAIT - Time out wait cycle for IP command grant.
*/
#define FLEXSPI_MCR0_IPGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_IPGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_IPGRANTWAIT_MASK)
#define FLEXSPI_MCR0_AHBGRANTWAIT_MASK (0xFF000000U)
#define FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT (24U)
/*! AHBGRANTWAIT - Timeout wait cycle for AHB command grant.
*/
#define FLEXSPI_MCR0_AHBGRANTWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR0_AHBGRANTWAIT_SHIFT)) & FLEXSPI_MCR0_AHBGRANTWAIT_MASK)
/*! @} */
/*! @name MCR1 - Module Control Register 1 */
/*! @{ */
#define FLEXSPI_MCR1_AHBBUSWAIT_MASK (0xFFFFU)
#define FLEXSPI_MCR1_AHBBUSWAIT_SHIFT (0U)
#define FLEXSPI_MCR1_AHBBUSWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_AHBBUSWAIT_SHIFT)) & FLEXSPI_MCR1_AHBBUSWAIT_MASK)
#define FLEXSPI_MCR1_SEQWAIT_MASK (0xFFFF0000U)
#define FLEXSPI_MCR1_SEQWAIT_SHIFT (16U)
#define FLEXSPI_MCR1_SEQWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR1_SEQWAIT_SHIFT)) & FLEXSPI_MCR1_SEQWAIT_MASK)
/*! @} */
/*! @name MCR2 - Module Control Register 2 */
/*! @{ */
#define FLEXSPI_MCR2_CLRAHBBUFOPT_MASK (0x800U)
#define FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT (11U)
/*! CLRAHBBUFOPT - This bit determines whether AHB RX Buffer and AHB TX Buffer will be cleaned
* automatically when FlexSPI returns STOP mode ACK. Software should set this bit if AHB RX Buffer or
* AHB TX Buffer will be powered off in STOP mode. Otherwise AHB read access after exiting STOP
* mode may hit AHB RX Buffer or AHB TX Buffer but their data entries are invalid.
* 0b0..AHB RX/TX Buffer will not be cleaned automatically when FlexSPI return Stop mode ACK.
* 0b1..AHB RX/TX Buffer will be cleaned automatically when FlexSPI return Stop mode ACK.
*/
#define FLEXSPI_MCR2_CLRAHBBUFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_CLRAHBBUFOPT_SHIFT)) & FLEXSPI_MCR2_CLRAHBBUFOPT_MASK)
#define FLEXSPI_MCR2_SAMEDEVICEEN_MASK (0x8000U)
#define FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT (15U)
/*! SAMEDEVICEEN - All external devices are same devices (both in types and size) for A1/A2/B1/B2.
* 0b0..In Individual mode, FLSHA1CRx/FLSHA2CRx/FLSHB1CRx/FLSHB2CRx register setting will be applied to Flash
* A1/A2/B1/B2 separately. In Parallel mode, FLSHA1CRx register setting will be applied to Flash A1 and B1,
* FLSHA2CRx register setting will be applied to Flash A2 and B2. FLSHB1CRx/FLSHB2CRx register settings will be
* ignored.
* 0b1..FLSHA1CR0/FLSHA1CR1/FLSHA1CR2 register settings will be applied to Flash A1/A2/B1/B2. FLSHA2CRx/FLSHB1CRx/FLSHB2CRx will be ignored.
*/
#define FLEXSPI_MCR2_SAMEDEVICEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SAMEDEVICEEN_SHIFT)) & FLEXSPI_MCR2_SAMEDEVICEEN_MASK)
#define FLEXSPI_MCR2_SCKBDIFFOPT_MASK (0x80000U)
#define FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT (19U)
/*! SCKBDIFFOPT - B_SCLK pad can be used as A_SCLK differential clock output (inverted clock to
* A_SCLK). In this case, port B flash access is not available. After changing the value of this
* field, MCR0[SWRESET] should be set.
* 0b1..B_SCLK pad is used as port A SCLK inverted clock output (Differential clock to A_SCLK). Port B flash access is not available.
* 0b0..B_SCLK pad is used as port B SCLK clock output. Port B flash access is available.
*/
#define FLEXSPI_MCR2_SCKBDIFFOPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_SCKBDIFFOPT_SHIFT)) & FLEXSPI_MCR2_SCKBDIFFOPT_MASK)
#define FLEXSPI_MCR2_RESUMEWAIT_MASK (0xFF000000U)
#define FLEXSPI_MCR2_RESUMEWAIT_SHIFT (24U)
/*! RESUMEWAIT - Wait cycle (in AHB clock cycle) for idle state before suspended command sequence resumed.
*/
#define FLEXSPI_MCR2_RESUMEWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MCR2_RESUMEWAIT_SHIFT)) & FLEXSPI_MCR2_RESUMEWAIT_MASK)
/*! @} */
/*! @name AHBCR - AHB Bus Control Register */
/*! @{ */
#define FLEXSPI_AHBCR_APAREN_MASK (0x1U)
#define FLEXSPI_AHBCR_APAREN_SHIFT (0U)
/*! APAREN - Parallel mode enabled for AHB triggered Command (both read and write) .
* 0b0..Flash will be accessed in Individual mode.
* 0b1..Flash will be accessed in Parallel mode.
*/
#define FLEXSPI_AHBCR_APAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_APAREN_SHIFT)) & FLEXSPI_AHBCR_APAREN_MASK)
#define FLEXSPI_AHBCR_CLRAHBRXBUF_MASK (0x2U)
#define FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT (1U)
/*! CLRAHBRXBUF - Clear the status/pointers of AHB RX Buffer. Auto-cleared.
*/
#define FLEXSPI_AHBCR_CLRAHBRXBUF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CLRAHBRXBUF_SHIFT)) & FLEXSPI_AHBCR_CLRAHBRXBUF_MASK)
#define FLEXSPI_AHBCR_CACHABLEEN_MASK (0x8U)
#define FLEXSPI_AHBCR_CACHABLEEN_SHIFT (3U)
/*! CACHABLEEN - Enable AHB bus cachable read access support.
* 0b0..Disabled. When there is AHB bus cachable read access, FlexSPI will not check whether it hit AHB TX Buffer.
* 0b1..Enabled. When there is AHB bus cachable read access, FlexSPI will check whether it hit AHB TX Buffer first.
*/
#define FLEXSPI_AHBCR_CACHABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_CACHABLEEN_SHIFT)) & FLEXSPI_AHBCR_CACHABLEEN_MASK)
#define FLEXSPI_AHBCR_BUFFERABLEEN_MASK (0x10U)
#define FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT (4U)
/*! BUFFERABLEEN - Enable AHB bus bufferable write access support. This field affects the last beat
* of AHB write access, refer for more details about AHB bufferable write.
* 0b0..Disabled. For all AHB write access (no matter bufferable or non-bufferable ), FlexSPI will return AHB Bus
* ready after all data is transmitted to External device and AHB command finished.
* 0b1..Enabled. For AHB bufferable write access, FlexSPI will return AHB Bus ready when the AHB command is
* granted by arbitrator and will not wait for AHB command finished.
*/
#define FLEXSPI_AHBCR_BUFFERABLEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_BUFFERABLEEN_SHIFT)) & FLEXSPI_AHBCR_BUFFERABLEEN_MASK)
#define FLEXSPI_AHBCR_PREFETCHEN_MASK (0x20U)
#define FLEXSPI_AHBCR_PREFETCHEN_SHIFT (5U)
/*! PREFETCHEN - AHB Read Prefetch Enable.
*/
#define FLEXSPI_AHBCR_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_PREFETCHEN_SHIFT)) & FLEXSPI_AHBCR_PREFETCHEN_MASK)
#define FLEXSPI_AHBCR_READADDROPT_MASK (0x40U)
#define FLEXSPI_AHBCR_READADDROPT_SHIFT (6U)
/*! READADDROPT - AHB Read Address option bit. This option bit is intend to remove AHB burst start address alignment limitation.
* 0b0..There is AHB read burst start address alignment limitation when flash is accessed in parallel mode or flash is word-addressable.
* 0b1..There is no AHB read burst start address alignment limitation. FlexSPI will fetch more data than AHB
* burst required to meet the alignment requirement.
*/
#define FLEXSPI_AHBCR_READADDROPT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READADDROPT_SHIFT)) & FLEXSPI_AHBCR_READADDROPT_MASK)
#define FLEXSPI_AHBCR_READSZALIGN_MASK (0x400U)
#define FLEXSPI_AHBCR_READSZALIGN_SHIFT (10U)
/*! READSZALIGN - AHB Read Size Alignment
* 0b0..AHB read size will be decided by other register setting like PREFETCH_EN,OTFAD_EN...
* 0b1..AHB read size to up size to 8 bytes aligned, no prefetching
*/
#define FLEXSPI_AHBCR_READSZALIGN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_READSZALIGN_SHIFT)) & FLEXSPI_AHBCR_READSZALIGN_MASK)
#define FLEXSPI_AHBCR_ECCEN_MASK (0x800U)
#define FLEXSPI_AHBCR_ECCEN_SHIFT (11U)
/*! ECCEN - AHB Read ECC Enable
* 0b0..AHB read ECC check disabled
* 0b1..AHB read ECC check enabled
*/
#define FLEXSPI_AHBCR_ECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCEN_SHIFT)) & FLEXSPI_AHBCR_ECCEN_MASK)
#define FLEXSPI_AHBCR_SPLITEN_MASK (0x1000U)
#define FLEXSPI_AHBCR_SPLITEN_SHIFT (12U)
/*! SPLITEN - AHB transaction SPLIT
* 0b0..AHB Split disabled
* 0b1..AHB Split enabled
*/
#define FLEXSPI_AHBCR_SPLITEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLITEN_SHIFT)) & FLEXSPI_AHBCR_SPLITEN_MASK)
#define FLEXSPI_AHBCR_SPLIT_LIMIT_MASK (0x6000U)
#define FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT (13U)
/*! SPLIT_LIMIT - AHB SPLIT SIZE
* 0b00..AHB Split Size=8bytes
* 0b01..AHB Split Size=16bytes
* 0b10..AHB Split Size=32bytes
* 0b11..AHB Split Size=64bytes
*/
#define FLEXSPI_AHBCR_SPLIT_LIMIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_SPLIT_LIMIT_SHIFT)) & FLEXSPI_AHBCR_SPLIT_LIMIT_MASK)
#define FLEXSPI_AHBCR_KEYECCEN_MASK (0x8000U)
#define FLEXSPI_AHBCR_KEYECCEN_SHIFT (15U)
/*! KEYECCEN - OTFAD KEY BLOC ECC Enable
* 0b0..AHB KEY ECC check disabled
* 0b1..AHB KEY ECC check enabled
*/
#define FLEXSPI_AHBCR_KEYECCEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_KEYECCEN_SHIFT)) & FLEXSPI_AHBCR_KEYECCEN_MASK)
#define FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK (0x10000U)
#define FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT (16U)
/*! ECCSINGLEERRCLR - AHB ECC Single bit ERR CLR
*/
#define FLEXSPI_AHBCR_ECCSINGLEERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSINGLEERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCSINGLEERRCLR_MASK)
#define FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK (0x20000U)
#define FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT (17U)
/*! ECCMULTIERRCLR - AHB ECC Multi bits ERR CLR
*/
#define FLEXSPI_AHBCR_ECCMULTIERRCLR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCMULTIERRCLR_SHIFT)) & FLEXSPI_AHBCR_ECCMULTIERRCLR_MASK)
#define FLEXSPI_AHBCR_HMSTRIDREMAP_MASK (0x40000U)
#define FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT (18U)
/*! HMSTRIDREMAP - AHB Master ID Remapping enable
*/
#define FLEXSPI_AHBCR_HMSTRIDREMAP(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_HMSTRIDREMAP_SHIFT)) & FLEXSPI_AHBCR_HMSTRIDREMAP_MASK)
#define FLEXSPI_AHBCR_ECCSWAPEN_MASK (0x80000U)
#define FLEXSPI_AHBCR_ECCSWAPEN_SHIFT (19U)
/*! ECCSWAPEN - ECC Read data swap function
* 0b0..rdata send to ecc check without swap.
* 0b1..rdata send to ecc ehck with swap.
*/
#define FLEXSPI_AHBCR_ECCSWAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ECCSWAPEN_SHIFT)) & FLEXSPI_AHBCR_ECCSWAPEN_MASK)
#define FLEXSPI_AHBCR_ALIGNMENT_MASK (0x300000U)
#define FLEXSPI_AHBCR_ALIGNMENT_SHIFT (20U)
/*! ALIGNMENT - Decides all AHB read/write boundary. All access cross the boundary will be divided into smaller sub accesses.
* 0b00..No limit
* 0b01..1 KBytes
* 0b10..512 Bytes
* 0b11..256 Bytes
*/
#define FLEXSPI_AHBCR_ALIGNMENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBCR_ALIGNMENT_SHIFT)) & FLEXSPI_AHBCR_ALIGNMENT_MASK)
/*! @} */
/*! @name INTEN - Interrupt Enable Register */
/*! @{ */
#define FLEXSPI_INTEN_IPCMDDONEEN_MASK (0x1U)
#define FLEXSPI_INTEN_IPCMDDONEEN_SHIFT (0U)
/*! IPCMDDONEEN - IP triggered Command Sequences Execution finished interrupt enable.
*/
#define FLEXSPI_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDDONEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDDONEEN_MASK)
#define FLEXSPI_INTEN_IPCMDGEEN_MASK (0x2U)
#define FLEXSPI_INTEN_IPCMDGEEN_SHIFT (1U)
/*! IPCMDGEEN - IP triggered Command Sequences Grant Timeout interrupt enable.
*/
#define FLEXSPI_INTEN_IPCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDGEEN_SHIFT)) & FLEXSPI_INTEN_IPCMDGEEN_MASK)
#define FLEXSPI_INTEN_AHBCMDGEEN_MASK (0x4U)
#define FLEXSPI_INTEN_AHBCMDGEEN_SHIFT (2U)
/*! AHBCMDGEEN - AHB triggered Command Sequences Grant Timeout interrupt enable.
*/
#define FLEXSPI_INTEN_AHBCMDGEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDGEEN_SHIFT)) & FLEXSPI_INTEN_AHBCMDGEEN_MASK)
#define FLEXSPI_INTEN_IPCMDERREN_MASK (0x8U)
#define FLEXSPI_INTEN_IPCMDERREN_SHIFT (3U)
/*! IPCMDERREN - IP triggered Command Sequences Error Detected interrupt enable.
*/
#define FLEXSPI_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDERREN_SHIFT)) & FLEXSPI_INTEN_IPCMDERREN_MASK)
#define FLEXSPI_INTEN_AHBCMDERREN_MASK (0x10U)
#define FLEXSPI_INTEN_AHBCMDERREN_SHIFT (4U)
/*! AHBCMDERREN - AHB triggered Command Sequences Error Detected interrupt enable.
*/
#define FLEXSPI_INTEN_AHBCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBCMDERREN_SHIFT)) & FLEXSPI_INTEN_AHBCMDERREN_MASK)
#define FLEXSPI_INTEN_IPRXWAEN_MASK (0x20U)
#define FLEXSPI_INTEN_IPRXWAEN_SHIFT (5U)
/*! IPRXWAEN - IP RX FIFO WaterMark available interrupt enable.
*/
#define FLEXSPI_INTEN_IPRXWAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPRXWAEN_SHIFT)) & FLEXSPI_INTEN_IPRXWAEN_MASK)
#define FLEXSPI_INTEN_IPTXWEEN_MASK (0x40U)
#define FLEXSPI_INTEN_IPTXWEEN_SHIFT (6U)
/*! IPTXWEEN - IP TX FIFO WaterMark empty interrupt enable.
*/
#define FLEXSPI_INTEN_IPTXWEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPTXWEEN_SHIFT)) & FLEXSPI_INTEN_IPTXWEEN_MASK)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK (0x100U)
#define FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT (8U)
/*! SCKSTOPBYRDEN - SCLK is stopped during command sequence because Async RX FIFO full interrupt enable.
*/
#define FLEXSPI_INTEN_SCKSTOPBYRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYRDEN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYRDEN_MASK)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_MASK (0x200U)
#define FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT (9U)
/*! SCKSTOPBYWREN - SCLK is stopped during command sequence because Async TX FIFO empty interrupt enable.
*/
#define FLEXSPI_INTEN_SCKSTOPBYWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SCKSTOPBYWREN_SHIFT)) & FLEXSPI_INTEN_SCKSTOPBYWREN_MASK)
#define FLEXSPI_INTEN_AHBBUSERROREN_MASK (0x400U)
#define FLEXSPI_INTEN_AHBBUSERROREN_SHIFT (10U)
/*! AHBBUSERROREN - AHB Bus error interrupt enable.Refer Interrupts chapter for more details.
*/
#define FLEXSPI_INTEN_AHBBUSERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_AHBBUSERROREN_SHIFT)) & FLEXSPI_INTEN_AHBBUSERROREN_MASK)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_MASK (0x800U)
#define FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT (11U)
/*! SEQTIMEOUTEN - Sequence execution timeout interrupt enable.Refer Interrupts chapter for more details.
*/
#define FLEXSPI_INTEN_SEQTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_SEQTIMEOUTEN_SHIFT)) & FLEXSPI_INTEN_SEQTIMEOUTEN_MASK)
#define FLEXSPI_INTEN_KEYDONEEN_MASK (0x1000U)
#define FLEXSPI_INTEN_KEYDONEEN_SHIFT (12U)
/*! KEYDONEEN - OTFAD key blob processing done interrupt enable.Refer Interrupts chapter for more details.
*/
#define FLEXSPI_INTEN_KEYDONEEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYDONEEN_SHIFT)) & FLEXSPI_INTEN_KEYDONEEN_MASK)
#define FLEXSPI_INTEN_KEYERROREN_MASK (0x2000U)
#define FLEXSPI_INTEN_KEYERROREN_SHIFT (13U)
/*! KEYERROREN - OTFAD key blob processing error interrupt enable.Refer Interrupts chapter for more details.
*/
#define FLEXSPI_INTEN_KEYERROREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_KEYERROREN_SHIFT)) & FLEXSPI_INTEN_KEYERROREN_MASK)
#define FLEXSPI_INTEN_ECCMULTIERREN_MASK (0x4000U)
#define FLEXSPI_INTEN_ECCMULTIERREN_SHIFT (14U)
/*! ECCMULTIERREN - ECC multi bits error interrupt enable.Refer Interrupts chapter for more details.
*/
#define FLEXSPI_INTEN_ECCMULTIERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCMULTIERREN_SHIFT)) & FLEXSPI_INTEN_ECCMULTIERREN_MASK)
#define FLEXSPI_INTEN_ECCSINGLEERREN_MASK (0x8000U)
#define FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT (15U)
/*! ECCSINGLEERREN - ECC single bit error interrupt enable.Refer Interrupts chapter for more details.
*/
#define FLEXSPI_INTEN_ECCSINGLEERREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_ECCSINGLEERREN_SHIFT)) & FLEXSPI_INTEN_ECCSINGLEERREN_MASK)
#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK (0x10000U)
#define FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT (16U)
/*! IPCMDSECUREVIOEN - IP command security violation interrupt enable.
*/
#define FLEXSPI_INTEN_IPCMDSECUREVIOEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTEN_IPCMDSECUREVIOEN_SHIFT)) & FLEXSPI_INTEN_IPCMDSECUREVIOEN_MASK)
/*! @} */
/*! @name INTR - Interrupt Register */
/*! @{ */
#define FLEXSPI_INTR_IPCMDDONE_MASK (0x1U)
#define FLEXSPI_INTR_IPCMDDONE_SHIFT (0U)
/*! IPCMDDONE - IP triggered Command Sequences Execution finished interrupt. This interrupt is also
* generated when there is IPCMDGE or IPCMDERR interrupt generated.
*/
#define FLEXSPI_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDDONE_SHIFT)) & FLEXSPI_INTR_IPCMDDONE_MASK)
#define FLEXSPI_INTR_IPCMDGE_MASK (0x2U)
#define FLEXSPI_INTR_IPCMDGE_SHIFT (1U)
/*! IPCMDGE - IP triggered Command Sequences Grant Timeout interrupt.
*/
#define FLEXSPI_INTR_IPCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDGE_SHIFT)) & FLEXSPI_INTR_IPCMDGE_MASK)
#define FLEXSPI_INTR_AHBCMDGE_MASK (0x4U)
#define FLEXSPI_INTR_AHBCMDGE_SHIFT (2U)
/*! AHBCMDGE - AHB triggered Command Sequences Grant Timeout interrupt.
*/
#define FLEXSPI_INTR_AHBCMDGE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDGE_SHIFT)) & FLEXSPI_INTR_AHBCMDGE_MASK)
#define FLEXSPI_INTR_IPCMDERR_MASK (0x8U)
#define FLEXSPI_INTR_IPCMDERR_SHIFT (3U)
/*! IPCMDERR - IP triggered Command Sequences Error Detected interrupt. When an error detected for
* IP command, this command will be ignored and not executed at all.
*/
#define FLEXSPI_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDERR_SHIFT)) & FLEXSPI_INTR_IPCMDERR_MASK)
#define FLEXSPI_INTR_AHBCMDERR_MASK (0x10U)
#define FLEXSPI_INTR_AHBCMDERR_SHIFT (4U)
/*! AHBCMDERR - AHB triggered Command Sequences Error Detected interrupt. When an error detected for
* AHB command, this command will be ignored and not executed at all.
*/
#define FLEXSPI_INTR_AHBCMDERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBCMDERR_SHIFT)) & FLEXSPI_INTR_AHBCMDERR_MASK)
#define FLEXSPI_INTR_IPRXWA_MASK (0x20U)
#define FLEXSPI_INTR_IPRXWA_SHIFT (5U)
/*! IPRXWA - IP RX FIFO watermark available interrupt.
*/
#define FLEXSPI_INTR_IPRXWA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPRXWA_SHIFT)) & FLEXSPI_INTR_IPRXWA_MASK)
#define FLEXSPI_INTR_IPTXWE_MASK (0x40U)
#define FLEXSPI_INTR_IPTXWE_SHIFT (6U)
/*! IPTXWE - IP TX FIFO watermark empty interrupt.
*/
#define FLEXSPI_INTR_IPTXWE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPTXWE_SHIFT)) & FLEXSPI_INTR_IPTXWE_MASK)
#define FLEXSPI_INTR_SCKSTOPBYRD_MASK (0x100U)
#define FLEXSPI_INTR_SCKSTOPBYRD_SHIFT (8U)
/*! SCKSTOPBYRD - SCLK is stopped during command sequence because Async RX FIFO full interrupt.
*/
#define FLEXSPI_INTR_SCKSTOPBYRD(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYRD_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYRD_MASK)
#define FLEXSPI_INTR_SCKSTOPBYWR_MASK (0x200U)
#define FLEXSPI_INTR_SCKSTOPBYWR_SHIFT (9U)
/*! SCKSTOPBYWR - SCLK is stopped during command sequence because Async TX FIFO empty interrupt.
*/
#define FLEXSPI_INTR_SCKSTOPBYWR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SCKSTOPBYWR_SHIFT)) & FLEXSPI_INTR_SCKSTOPBYWR_MASK)
#define FLEXSPI_INTR_AHBBUSERROR_MASK (0x400U)
#define FLEXSPI_INTR_AHBBUSERROR_SHIFT (10U)
/*! AHBBUSERROR - AHB Bus timeout or AHB bus illegal access Flash during OTFAD key blob processing interrupt.
*/
#define FLEXSPI_INTR_AHBBUSERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_AHBBUSERROR_SHIFT)) & FLEXSPI_INTR_AHBBUSERROR_MASK)
#define FLEXSPI_INTR_SEQTIMEOUT_MASK (0x800U)
#define FLEXSPI_INTR_SEQTIMEOUT_SHIFT (11U)
/*! SEQTIMEOUT - Sequence execution timeout interrupt.
*/
#define FLEXSPI_INTR_SEQTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_SEQTIMEOUT_SHIFT)) & FLEXSPI_INTR_SEQTIMEOUT_MASK)
#define FLEXSPI_INTR_KEYDONE_MASK (0x1000U)
#define FLEXSPI_INTR_KEYDONE_SHIFT (12U)
/*! KEYDONE - OTFAD key blob processing done interrupt.
*/
#define FLEXSPI_INTR_KEYDONE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYDONE_SHIFT)) & FLEXSPI_INTR_KEYDONE_MASK)
#define FLEXSPI_INTR_KEYERROR_MASK (0x2000U)
#define FLEXSPI_INTR_KEYERROR_SHIFT (13U)
/*! KEYERROR - OTFAD key blob processing error interrupt.
*/
#define FLEXSPI_INTR_KEYERROR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_KEYERROR_SHIFT)) & FLEXSPI_INTR_KEYERROR_MASK)
#define FLEXSPI_INTR_ECCMULTIERR_MASK (0x4000U)
#define FLEXSPI_INTR_ECCMULTIERR_SHIFT (14U)
/*! ECCMULTIERR - ECC multi bits error interrupt.
*/
#define FLEXSPI_INTR_ECCMULTIERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCMULTIERR_SHIFT)) & FLEXSPI_INTR_ECCMULTIERR_MASK)
#define FLEXSPI_INTR_ECCSINGLEERR_MASK (0x8000U)
#define FLEXSPI_INTR_ECCSINGLEERR_SHIFT (15U)
/*! ECCSINGLEERR - ECC single bit error interrupt.
*/
#define FLEXSPI_INTR_ECCSINGLEERR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_ECCSINGLEERR_SHIFT)) & FLEXSPI_INTR_ECCSINGLEERR_MASK)
#define FLEXSPI_INTR_IPCMDSECUREVIO_MASK (0x10000U)
#define FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT (16U)
/*! IPCMDSECUREVIO - IP command security violation interrupt.
*/
#define FLEXSPI_INTR_IPCMDSECUREVIO(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_INTR_IPCMDSECUREVIO_SHIFT)) & FLEXSPI_INTR_IPCMDSECUREVIO_MASK)
/*! @} */
/*! @name LUTKEY - LUT Key Register */
/*! @{ */
#define FLEXSPI_LUTKEY_KEY_MASK (0xFFFFFFFFU)
#define FLEXSPI_LUTKEY_KEY_SHIFT (0U)
/*! KEY - The Key to lock or unlock LUT.
*/
#define FLEXSPI_LUTKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTKEY_KEY_SHIFT)) & FLEXSPI_LUTKEY_KEY_MASK)
/*! @} */
/*! @name LUTCR - LUT Control Register */
/*! @{ */
#define FLEXSPI_LUTCR_LOCK_MASK (0x1U)
#define FLEXSPI_LUTCR_LOCK_SHIFT (0U)
/*! LOCK - Lock LUT
*/
#define FLEXSPI_LUTCR_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_LOCK_SHIFT)) & FLEXSPI_LUTCR_LOCK_MASK)
#define FLEXSPI_LUTCR_UNLOCK_MASK (0x2U)
#define FLEXSPI_LUTCR_UNLOCK_SHIFT (1U)
/*! UNLOCK - Unlock LUT
*/
#define FLEXSPI_LUTCR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_UNLOCK_SHIFT)) & FLEXSPI_LUTCR_UNLOCK_MASK)
#define FLEXSPI_LUTCR_PROTECT_MASK (0x4U)
#define FLEXSPI_LUTCR_PROTECT_SHIFT (2U)
/*! PROTECT - LUT protection
*/
#define FLEXSPI_LUTCR_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUTCR_PROTECT_SHIFT)) & FLEXSPI_LUTCR_PROTECT_MASK)
/*! @} */
/*! @name AHBRXBUFCR0 - AHB RX Buffer 0 Control Register 0..AHB RX Buffer 7 Control Register 0 */
/*! @{ */
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK (0x3FFU)
#define FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT (0U)
/*! BUFSZ - AHB RX Buffer Size in 64 bits.
*/
#define FLEXSPI_AHBRXBUFCR0_BUFSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_BUFSZ_SHIFT)) & FLEXSPI_AHBRXBUFCR0_BUFSZ_MASK)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_MASK (0xF0000U)
#define FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT (16U)
/*! MSTRID - This AHB RX Buffer is assigned according to AHB Master with ID (MSTR_ID).
*/
#define FLEXSPI_AHBRXBUFCR0_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_MSTRID_SHIFT)) & FLEXSPI_AHBRXBUFCR0_MSTRID_MASK)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK (0x7000000U)
#define FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT (24U)
/*! PRIORITY - This priority for AHB Master Read which this AHB RX Buffer is assigned. 7 is the highest priority, 0 the lowest.
*/
#define FLEXSPI_AHBRXBUFCR0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PRIORITY_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PRIORITY_MASK)
#define FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK (0x40000000U)
#define FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT (30U)
/*! REGIONEN - AHB RX Buffer address region funciton enable
*/
#define FLEXSPI_AHBRXBUFCR0_REGIONEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_REGIONEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_REGIONEN_MASK)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK (0x80000000U)
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT (31U)
/*! PREFETCHEN - AHB Read Prefetch Enable for current AHB RX Buffer corresponding Master.
*/
#define FLEXSPI_AHBRXBUFCR0_PREFETCHEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBRXBUFCR0_PREFETCHEN_SHIFT)) & FLEXSPI_AHBRXBUFCR0_PREFETCHEN_MASK)
/*! @} */
/* The count of FLEXSPI_AHBRXBUFCR0 */
#define FLEXSPI_AHBRXBUFCR0_COUNT (8U)
/*! @name FLSHCR0 - Flash Control Register 0 */
/*! @{ */
#define FLEXSPI_FLSHCR0_FLSHSZ_MASK (0x7FFFFFU)
#define FLEXSPI_FLSHCR0_FLSHSZ_SHIFT (0U)
/*! FLSHSZ - Flash Size in KByte.
*/
#define FLEXSPI_FLSHCR0_FLSHSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_FLSHSZ_SHIFT)) & FLEXSPI_FLSHCR0_FLSHSZ_MASK)
#define FLEXSPI_FLSHCR0_SPLITWREN_MASK (0x40000000U)
#define FLEXSPI_FLSHCR0_SPLITWREN_SHIFT (30U)
/*! SPLITWREN - AHB write access split function control.
*/
#define FLEXSPI_FLSHCR0_SPLITWREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITWREN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITWREN_MASK)
#define FLEXSPI_FLSHCR0_SPLITRDEN_MASK (0x80000000U)
#define FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT (31U)
/*! SPLITRDEN - AHB read access split function control.
*/
#define FLEXSPI_FLSHCR0_SPLITRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR0_SPLITRDEN_SHIFT)) & FLEXSPI_FLSHCR0_SPLITRDEN_MASK)
/*! @} */
/* The count of FLEXSPI_FLSHCR0 */
#define FLEXSPI_FLSHCR0_COUNT (4U)
/*! @name FLSHCR1 - Flash Control Register 1 */
/*! @{ */
#define FLEXSPI_FLSHCR1_TCSS_MASK (0x1FU)
#define FLEXSPI_FLSHCR1_TCSS_SHIFT (0U)
/*! TCSS - Serial Flash CS setup time.
*/
#define FLEXSPI_FLSHCR1_TCSS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSS_SHIFT)) & FLEXSPI_FLSHCR1_TCSS_MASK)
#define FLEXSPI_FLSHCR1_TCSH_MASK (0x3E0U)
#define FLEXSPI_FLSHCR1_TCSH_SHIFT (5U)
/*! TCSH - Serial Flash CS Hold time.
*/
#define FLEXSPI_FLSHCR1_TCSH(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_TCSH_SHIFT)) & FLEXSPI_FLSHCR1_TCSH_MASK)
#define FLEXSPI_FLSHCR1_WA_MASK (0x400U)
#define FLEXSPI_FLSHCR1_WA_SHIFT (10U)
/*! WA - Word Addressable.
*/
#define FLEXSPI_FLSHCR1_WA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_WA_SHIFT)) & FLEXSPI_FLSHCR1_WA_MASK)
#define FLEXSPI_FLSHCR1_CAS_MASK (0x7800U)
#define FLEXSPI_FLSHCR1_CAS_SHIFT (11U)
/*! CAS - Column Address Size.
*/
#define FLEXSPI_FLSHCR1_CAS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CAS_SHIFT)) & FLEXSPI_FLSHCR1_CAS_MASK)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK (0x8000U)
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT (15U)
/*! CSINTERVALUNIT - CS interval unit
* 0b0..The CS interval unit is 1 serial clock cycle
* 0b1..The CS interval unit is 256 serial clock cycle
*/
#define FLEXSPI_FLSHCR1_CSINTERVALUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVALUNIT_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVALUNIT_MASK)
#define FLEXSPI_FLSHCR1_CSINTERVAL_MASK (0xFFFF0000U)
#define FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT (16U)
/*! CSINTERVAL - This field is used to set the minimum interval between flash device Chip selection
* deassertion and flash device Chip selection assertion. If external flash has a limitation on
* the interval between command sequences, this field should be set accordingly. If there is no
* limitation, set this field with value 0x0.
*/
#define FLEXSPI_FLSHCR1_CSINTERVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR1_CSINTERVAL_SHIFT)) & FLEXSPI_FLSHCR1_CSINTERVAL_MASK)
/*! @} */
/* The count of FLEXSPI_FLSHCR1 */
#define FLEXSPI_FLSHCR1_COUNT (4U)
/*! @name FLSHCR2 - Flash Control Register 2 */
/*! @{ */
#define FLEXSPI_FLSHCR2_ARDSEQID_MASK (0xFU)
#define FLEXSPI_FLSHCR2_ARDSEQID_SHIFT (0U)
/*! ARDSEQID - Sequence Index for AHB Read triggered Command in LUT.
*/
#define FLEXSPI_FLSHCR2_ARDSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQID_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQID_MASK)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_MASK (0xE0U)
#define FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT (5U)
/*! ARDSEQNUM - Sequence Number for AHB Read triggered Command in LUT.
*/
#define FLEXSPI_FLSHCR2_ARDSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_ARDSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_ARDSEQNUM_MASK)
#define FLEXSPI_FLSHCR2_AWRSEQID_MASK (0xF00U)
#define FLEXSPI_FLSHCR2_AWRSEQID_SHIFT (8U)
/*! AWRSEQID - Sequence Index for AHB Write triggered Command.
*/
#define FLEXSPI_FLSHCR2_AWRSEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQID_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQID_MASK)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_MASK (0xE000U)
#define FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT (13U)
/*! AWRSEQNUM - Sequence Number for AHB Write triggered Command.
*/
#define FLEXSPI_FLSHCR2_AWRSEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRSEQNUM_SHIFT)) & FLEXSPI_FLSHCR2_AWRSEQNUM_MASK)
#define FLEXSPI_FLSHCR2_AWRWAIT_MASK (0xFFF0000U)
#define FLEXSPI_FLSHCR2_AWRWAIT_SHIFT (16U)
#define FLEXSPI_FLSHCR2_AWRWAIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAIT_MASK)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK (0x70000000U)
#define FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT (28U)
/*! AWRWAITUNIT - AWRWAIT unit
* 0b000..The AWRWAIT unit is 2 ahb clock cycle
* 0b001..The AWRWAIT unit is 8 ahb clock cycle
* 0b010..The AWRWAIT unit is 32 ahb clock cycle
* 0b011..The AWRWAIT unit is 128 ahb clock cycle
* 0b100..The AWRWAIT unit is 512 ahb clock cycle
* 0b101..The AWRWAIT unit is 2048 ahb clock cycle
* 0b110..The AWRWAIT unit is 8192 ahb clock cycle
* 0b111..The AWRWAIT unit is 32768 ahb clock cycle
*/
#define FLEXSPI_FLSHCR2_AWRWAITUNIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_AWRWAITUNIT_SHIFT)) & FLEXSPI_FLSHCR2_AWRWAITUNIT_MASK)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK (0x80000000U)
#define FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT (31U)
/*! CLRINSTRPTR - Clear the instruction pointer which is internally saved pointer by JMP_ON_CS.
* Refer Programmable Sequence Engine for details.
*/
#define FLEXSPI_FLSHCR2_CLRINSTRPTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR2_CLRINSTRPTR_SHIFT)) & FLEXSPI_FLSHCR2_CLRINSTRPTR_MASK)
/*! @} */
/* The count of FLEXSPI_FLSHCR2 */
#define FLEXSPI_FLSHCR2_COUNT (4U)
/*! @name FLSHCR4 - Flash Control Register 4 */
/*! @{ */
#define FLEXSPI_FLSHCR4_WMOPT1_MASK (0x1U)
#define FLEXSPI_FLSHCR4_WMOPT1_SHIFT (0U)
/*! WMOPT1 - Write mask option bit 1. This option bit could be used to remove AHB write burst start address alignment limitation.
* 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
* burst start address alignment when flash is accessed in individual mode.
* 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
* burst start address alignment when flash is accessed in individual mode.
*/
#define FLEXSPI_FLSHCR4_WMOPT1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT1_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT1_MASK)
#define FLEXSPI_FLSHCR4_WMOPT2_MASK (0x2U)
#define FLEXSPI_FLSHCR4_WMOPT2_SHIFT (1U)
/*! WMOPT2 - Write mask option bit 2. When using AP memory, This option bit could be used to remove
* AHB write burst minimal length limitation. When using this bit, WMOPT1 should also be set.
* 0b0..DQS pin will be used as Write Mask when writing to external device. There is no limitation on AHB write
* burst length when flash is accessed in individual mode.
* 0b1..DQS pin will not be used as Write Mask when writing to external device. There is limitation on AHB write
* burst length when flash is accessed in individual mode, the minimal write burst length should be 4.
*/
#define FLEXSPI_FLSHCR4_WMOPT2(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMOPT2_SHIFT)) & FLEXSPI_FLSHCR4_WMOPT2_MASK)
#define FLEXSPI_FLSHCR4_WMENA_MASK (0x4U)
#define FLEXSPI_FLSHCR4_WMENA_SHIFT (2U)
/*! WMENA - Write mask enable bit for flash device on port A. When write mask function is needed for
* memory device on port A, this bit must be set.
* 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
* 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
*/
#define FLEXSPI_FLSHCR4_WMENA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENA_SHIFT)) & FLEXSPI_FLSHCR4_WMENA_MASK)
#define FLEXSPI_FLSHCR4_WMENB_MASK (0x8U)
#define FLEXSPI_FLSHCR4_WMENB_SHIFT (3U)
/*! WMENB - Write mask enable bit for flash device on port B. When write mask function is needed for
* memory device on port B, this bit must be set.
* 0b0..Write mask is disabled, DQS(RWDS) pin will be un-driven when writing to external device.
* 0b1..Write mask is enabled, DQS(RWDS) pin will be driven by FlexSPI as write mask output when writing to external device.
*/
#define FLEXSPI_FLSHCR4_WMENB(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_WMENB_SHIFT)) & FLEXSPI_FLSHCR4_WMENB_MASK)
#define FLEXSPI_FLSHCR4_PAR_WM_MASK (0x600U)
#define FLEXSPI_FLSHCR4_PAR_WM_SHIFT (9U)
/*! PAR_WM - Enable APMEM 16 bit write mask function, bit 9 for A1-B1 pair, bit 10 for A2-B2 pair.
*/
#define FLEXSPI_FLSHCR4_PAR_WM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_WM_SHIFT)) & FLEXSPI_FLSHCR4_PAR_WM_MASK)
#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK (0x800U)
#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT (11U)
/*! PAR_ADDR_ADJ_DIS - Disable the address shift logic for lower density of 16 bit PSRAM.
*/
#define FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_SHIFT)) & FLEXSPI_FLSHCR4_PAR_ADDR_ADJ_DIS_MASK)
/*! @} */
/*! @name IPCR0 - IP Control Register 0 */
/*! @{ */
#define FLEXSPI_IPCR0_SFAR_MASK (0xFFFFFFFFU)
#define FLEXSPI_IPCR0_SFAR_SHIFT (0U)
/*! SFAR - Serial Flash Address for IP command.
*/
#define FLEXSPI_IPCR0_SFAR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR0_SFAR_SHIFT)) & FLEXSPI_IPCR0_SFAR_MASK)
/*! @} */
/*! @name IPCR1 - IP Control Register 1 */
/*! @{ */
#define FLEXSPI_IPCR1_IDATSZ_MASK (0xFFFFU)
#define FLEXSPI_IPCR1_IDATSZ_SHIFT (0U)
/*! IDATSZ - Flash Read/Program Data Size (in Bytes) for IP command.
*/
#define FLEXSPI_IPCR1_IDATSZ(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IDATSZ_SHIFT)) & FLEXSPI_IPCR1_IDATSZ_MASK)
#define FLEXSPI_IPCR1_ISEQID_MASK (0xF0000U)
#define FLEXSPI_IPCR1_ISEQID_SHIFT (16U)
/*! ISEQID - Sequence Index in LUT for IP command.
*/
#define FLEXSPI_IPCR1_ISEQID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQID_SHIFT)) & FLEXSPI_IPCR1_ISEQID_MASK)
#define FLEXSPI_IPCR1_ISEQNUM_MASK (0x7000000U)
#define FLEXSPI_IPCR1_ISEQNUM_SHIFT (24U)
/*! ISEQNUM - Sequence Number for IP command: ISEQNUM+1.
*/
#define FLEXSPI_IPCR1_ISEQNUM(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_ISEQNUM_SHIFT)) & FLEXSPI_IPCR1_ISEQNUM_MASK)
#define FLEXSPI_IPCR1_IPAREN_MASK (0x80000000U)
#define FLEXSPI_IPCR1_IPAREN_SHIFT (31U)
/*! IPAREN - Parallel mode Enabled for IP command.
* 0b0..Flash will be accessed in Individual mode.
* 0b1..Flash will be accessed in Parallel mode.
*/
#define FLEXSPI_IPCR1_IPAREN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCR1_IPAREN_SHIFT)) & FLEXSPI_IPCR1_IPAREN_MASK)
/*! @} */
/*! @name IPCMD - IP Command Register */
/*! @{ */
#define FLEXSPI_IPCMD_TRG_MASK (0x1U)
#define FLEXSPI_IPCMD_TRG_SHIFT (0U)
/*! TRG - Setting this bit will trigger an IP Command.
*/
#define FLEXSPI_IPCMD_TRG(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPCMD_TRG_SHIFT)) & FLEXSPI_IPCMD_TRG_MASK)
/*! @} */
/*! @name IPRXFCR - IP RX FIFO Control Register */
/*! @{ */
#define FLEXSPI_IPRXFCR_CLRIPRXF_MASK (0x1U)
#define FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT (0U)
/*! CLRIPRXF - Clear all valid data entries in IP RX FIFO.
*/
#define FLEXSPI_IPRXFCR_CLRIPRXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_CLRIPRXF_SHIFT)) & FLEXSPI_IPRXFCR_CLRIPRXF_MASK)
#define FLEXSPI_IPRXFCR_RXDMAEN_MASK (0x2U)
#define FLEXSPI_IPRXFCR_RXDMAEN_SHIFT (1U)
/*! RXDMAEN - IP RX FIFO reading by DMA enabled.
* 0b0..IP RX FIFO would be read by processor.
* 0b1..IP RX FIFO would be read by DMA.
*/
#define FLEXSPI_IPRXFCR_RXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXDMAEN_SHIFT)) & FLEXSPI_IPRXFCR_RXDMAEN_MASK)
#define FLEXSPI_IPRXFCR_RXWMRK_MASK (0x7CU)
#define FLEXSPI_IPRXFCR_RXWMRK_SHIFT (2U)
/*! RXWMRK - Watermark level is (RXWMRK+1)*64 Bits.
*/
#define FLEXSPI_IPRXFCR_RXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFCR_RXWMRK_SHIFT)) & FLEXSPI_IPRXFCR_RXWMRK_MASK)
/*! @} */
/*! @name IPTXFCR - IP TX FIFO Control Register */
/*! @{ */
#define FLEXSPI_IPTXFCR_CLRIPTXF_MASK (0x1U)
#define FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT (0U)
/*! CLRIPTXF - Clear all valid data entries in IP TX FIFO.
*/
#define FLEXSPI_IPTXFCR_CLRIPTXF(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_CLRIPTXF_SHIFT)) & FLEXSPI_IPTXFCR_CLRIPTXF_MASK)
#define FLEXSPI_IPTXFCR_TXDMAEN_MASK (0x2U)
#define FLEXSPI_IPTXFCR_TXDMAEN_SHIFT (1U)
/*! TXDMAEN - IP TX FIFO filling by DMA enabled.
* 0b0..IP TX FIFO would be filled by processor.
* 0b1..IP TX FIFO would be filled by DMA.
*/
#define FLEXSPI_IPTXFCR_TXDMAEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXDMAEN_SHIFT)) & FLEXSPI_IPTXFCR_TXDMAEN_MASK)
#define FLEXSPI_IPTXFCR_TXWMRK_MASK (0x7CU)
#define FLEXSPI_IPTXFCR_TXWMRK_SHIFT (2U)
/*! TXWMRK - Watermark level is (TXWMRK+1)*64 Bits.
*/
#define FLEXSPI_IPTXFCR_TXWMRK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFCR_TXWMRK_SHIFT)) & FLEXSPI_IPTXFCR_TXWMRK_MASK)
/*! @} */
/*! @name DLLCR - DLL Control Register 0 */
/*! @{ */
#define FLEXSPI_DLLCR_DLLEN_MASK (0x1U)
#define FLEXSPI_DLLCR_DLLEN_SHIFT (0U)
/*! DLLEN - DLL calibration enable.
*/
#define FLEXSPI_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLEN_SHIFT)) & FLEXSPI_DLLCR_DLLEN_MASK)
#define FLEXSPI_DLLCR_DLLRESET_MASK (0x2U)
#define FLEXSPI_DLLCR_DLLRESET_SHIFT (1U)
/*! DLLRESET - Software could force a reset on DLL by setting this field to 0x1. This will cause the
* DLL to lose lock and re-calibrate to detect an ref_clock half period phase shift. The reset
* action is edge triggered, so software need to clear this bit after set this bit (no delay
* limitation).
*/
#define FLEXSPI_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_DLLRESET_SHIFT)) & FLEXSPI_DLLCR_DLLRESET_MASK)
#define FLEXSPI_DLLCR_SLVDLYTARGET_MASK (0x78U)
#define FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT (3U)
/*! SLVDLYTARGET - The delay target for slave delay line is: ((SLVDLYTARGET+1) * 1/32 * clock cycle
* of reference clock (serial root clock). If serial root clock is >= 100 MHz, DLLEN set to 0x1,
* OVRDEN set to =0x0, then SLVDLYTARGET setting of 0xF is recommended.
*/
#define FLEXSPI_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_SLVDLYTARGET_SHIFT)) & FLEXSPI_DLLCR_SLVDLYTARGET_MASK)
#define FLEXSPI_DLLCR_OVRDEN_MASK (0x100U)
#define FLEXSPI_DLLCR_OVRDEN_SHIFT (8U)
/*! OVRDEN - Slave clock delay line delay cell number selection override enable.
*/
#define FLEXSPI_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDEN_SHIFT)) & FLEXSPI_DLLCR_OVRDEN_MASK)
#define FLEXSPI_DLLCR_OVRDVAL_MASK (0x7E00U)
#define FLEXSPI_DLLCR_OVRDVAL_SHIFT (9U)
/*! OVRDVAL - Slave clock delay line delay cell number selection override value.
*/
#define FLEXSPI_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_DLLCR_OVRDVAL_SHIFT)) & FLEXSPI_DLLCR_OVRDVAL_MASK)
/*! @} */
/* The count of FLEXSPI_DLLCR */
#define FLEXSPI_DLLCR_COUNT (2U)
/*! @name MISCCR4 - Misc Control Register 4 */
/*! @{ */
#define FLEXSPI_MISCCR4_AHBADDRESS_MASK (0xFFFFFFFFU)
#define FLEXSPI_MISCCR4_AHBADDRESS_SHIFT (0U)
/*! AHBADDRESS - AHB bus address that trigger the current ECC multi bits error interrupt.
*/
#define FLEXSPI_MISCCR4_AHBADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR4_AHBADDRESS_SHIFT)) & FLEXSPI_MISCCR4_AHBADDRESS_MASK)
/*! @} */
/*! @name MISCCR5 - Misc Control Register 5 */
/*! @{ */
#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK (0xFFFFFFFFU)
#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT (0U)
/*! ECCSINGLEERRORCORR - ECC single bit error correction indication.
*/
#define FLEXSPI_MISCCR5_ECCSINGLEERRORCORR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_SHIFT)) & FLEXSPI_MISCCR5_ECCSINGLEERRORCORR_MASK)
/*! @} */
/*! @name MISCCR6 - Misc Control Register 6 */
/*! @{ */
#define FLEXSPI_MISCCR6_VALID_MASK (0x1U)
#define FLEXSPI_MISCCR6_VALID_SHIFT (0U)
/*! VALID - ECC single error information Valid
*/
#define FLEXSPI_MISCCR6_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_VALID_SHIFT)) & FLEXSPI_MISCCR6_VALID_MASK)
#define FLEXSPI_MISCCR6_HIT_MASK (0x2U)
#define FLEXSPI_MISCCR6_HIT_SHIFT (1U)
/*! HIT - ECC single error information Hit
*/
#define FLEXSPI_MISCCR6_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_HIT_SHIFT)) & FLEXSPI_MISCCR6_HIT_MASK)
#define FLEXSPI_MISCCR6_ADDRESS_MASK (0xFFFFFFFCU)
#define FLEXSPI_MISCCR6_ADDRESS_SHIFT (2U)
/*! ADDRESS - ECC single error address
*/
#define FLEXSPI_MISCCR6_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR6_ADDRESS_SHIFT)) & FLEXSPI_MISCCR6_ADDRESS_MASK)
/*! @} */
/*! @name MISCCR7 - Misc Control Register 7 */
/*! @{ */
#define FLEXSPI_MISCCR7_VALID_MASK (0x1U)
#define FLEXSPI_MISCCR7_VALID_SHIFT (0U)
/*! VALID - ECC multi error information Valid
*/
#define FLEXSPI_MISCCR7_VALID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_VALID_SHIFT)) & FLEXSPI_MISCCR7_VALID_MASK)
#define FLEXSPI_MISCCR7_HIT_MASK (0x2U)
#define FLEXSPI_MISCCR7_HIT_SHIFT (1U)
/*! HIT - ECC multi error information Hit
*/
#define FLEXSPI_MISCCR7_HIT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_HIT_SHIFT)) & FLEXSPI_MISCCR7_HIT_MASK)
#define FLEXSPI_MISCCR7_ADDRESS_MASK (0xFFFFFFFCU)
#define FLEXSPI_MISCCR7_ADDRESS_SHIFT (2U)
/*! ADDRESS - ECC multi error address
*/
#define FLEXSPI_MISCCR7_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_MISCCR7_ADDRESS_SHIFT)) & FLEXSPI_MISCCR7_ADDRESS_MASK)
/*! @} */
/*! @name STS0 - Status Register 0 */
/*! @{ */
#define FLEXSPI_STS0_SEQIDLE_MASK (0x1U)
#define FLEXSPI_STS0_SEQIDLE_SHIFT (0U)
/*! SEQIDLE - This status bit indicates the state machine in SEQ_CTL is idle and there is command
* sequence executing on FlexSPI interface.
*/
#define FLEXSPI_STS0_SEQIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_SEQIDLE_SHIFT)) & FLEXSPI_STS0_SEQIDLE_MASK)
#define FLEXSPI_STS0_ARBIDLE_MASK (0x2U)
#define FLEXSPI_STS0_ARBIDLE_SHIFT (1U)
/*! ARBIDLE - This status bit indicates the state machine in ARB_CTL is busy and there is command
* sequence granted by arbitrator and not finished yet on FlexSPI interface. When ARB_CTL state
* (ARBIDLE=0x1) is idle, there will be no transaction on FlexSPI interface also (SEQIDLE=0x1). So
* this bit should be polled to wait for FlexSPI controller become idle instead of SEQIDLE.
*/
#define FLEXSPI_STS0_ARBIDLE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBIDLE_SHIFT)) & FLEXSPI_STS0_ARBIDLE_MASK)
#define FLEXSPI_STS0_ARBCMDSRC_MASK (0xCU)
#define FLEXSPI_STS0_ARBCMDSRC_SHIFT (2U)
/*! ARBCMDSRC - This status field indicates the trigger source of current command sequence granted
* by arbitrator. This field value is meaningless when ARB_CTL is not busy (STS0[ARBIDLE]=0x1).
* 0b00..Triggered by AHB read command (triggered by AHB read).
* 0b01..Triggered by AHB write command (triggered by AHB Write).
* 0b10..Triggered by IP command (triggered by setting register bit IPCMD.TRG).
* 0b11..Triggered by suspended command (resumed).
*/
#define FLEXSPI_STS0_ARBCMDSRC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS0_ARBCMDSRC_SHIFT)) & FLEXSPI_STS0_ARBCMDSRC_MASK)
/*! @} */
/*! @name STS1 - Status Register 1 */
/*! @{ */
#define FLEXSPI_STS1_AHBCMDERRID_MASK (0xFU)
#define FLEXSPI_STS1_AHBCMDERRID_SHIFT (0U)
/*! AHBCMDERRID - Indicates the sequence index when an AHB command error is detected. This field
* will be cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
*/
#define FLEXSPI_STS1_AHBCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRID_SHIFT)) & FLEXSPI_STS1_AHBCMDERRID_MASK)
#define FLEXSPI_STS1_AHBCMDERRCODE_MASK (0xF00U)
#define FLEXSPI_STS1_AHBCMDERRCODE_SHIFT (8U)
/*! AHBCMDERRCODE - Indicates the Error Code when AHB command Error detected. This field will be
* cleared when INTR[AHBCMDERR] is write-1-clear(w1c).
* 0b0000..No error.
* 0b0010..AHB Write command with JMP_ON_CS instruction used in the sequence.
* 0b0011..There is unknown instruction opcode in the sequence.
* 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
* 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
* 0b1110..Sequence execution timeout.
*/
#define FLEXSPI_STS1_AHBCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_AHBCMDERRCODE_SHIFT)) & FLEXSPI_STS1_AHBCMDERRCODE_MASK)
#define FLEXSPI_STS1_IPCMDERRID_MASK (0xF0000U)
#define FLEXSPI_STS1_IPCMDERRID_SHIFT (16U)
/*! IPCMDERRID - Indicates the sequence Index when IP command error detected. This field will be
* cleared when INTR[IPCMDERR] is write-1-clear(w1c).
*/
#define FLEXSPI_STS1_IPCMDERRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRID_SHIFT)) & FLEXSPI_STS1_IPCMDERRID_MASK)
#define FLEXSPI_STS1_IPCMDERRCODE_MASK (0xF000000U)
#define FLEXSPI_STS1_IPCMDERRCODE_SHIFT (24U)
/*! IPCMDERRCODE - Indicates the Error Code when IP command Error detected. This field will be
* cleared when INTR[IPCMDERR] is write-1-clear(w1c).
* 0b0000..No error.
* 0b0010..IP command with JMP_ON_CS instruction used in the sequence.
* 0b0011..There is unknown instruction opcode in the sequence.
* 0b0100..Instruction DUMMY_SDR/DUMMY_RWDS_SDR used in DDR sequence.
* 0b0101..Instruction DUMMY_DDR/DUMMY_RWDS_DDR used in SDR sequence.
* 0b0110..Flash access start address exceed the whole flash address range (A1/A2/B1/B2).
* 0b1110..Sequence execution timeout.
* 0b1111..Flash boundary crossed.
*/
#define FLEXSPI_STS1_IPCMDERRCODE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS1_IPCMDERRCODE_SHIFT)) & FLEXSPI_STS1_IPCMDERRCODE_MASK)
/*! @} */
/*! @name STS2 - Status Register 2 */
/*! @{ */
#define FLEXSPI_STS2_ASLVLOCK_MASK (0x1U)
#define FLEXSPI_STS2_ASLVLOCK_SHIFT (0U)
/*! ASLVLOCK - Flash A sample clock slave delay line locked.
*/
#define FLEXSPI_STS2_ASLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVLOCK_SHIFT)) & FLEXSPI_STS2_ASLVLOCK_MASK)
#define FLEXSPI_STS2_AREFLOCK_MASK (0x2U)
#define FLEXSPI_STS2_AREFLOCK_SHIFT (1U)
/*! AREFLOCK - Flash A sample clock reference delay line locked.
*/
#define FLEXSPI_STS2_AREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFLOCK_SHIFT)) & FLEXSPI_STS2_AREFLOCK_MASK)
#define FLEXSPI_STS2_ASLVSEL_MASK (0xFCU)
#define FLEXSPI_STS2_ASLVSEL_SHIFT (2U)
/*! ASLVSEL - Flash A sample clock slave delay line delay cell number selection .
*/
#define FLEXSPI_STS2_ASLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_ASLVSEL_SHIFT)) & FLEXSPI_STS2_ASLVSEL_MASK)
#define FLEXSPI_STS2_AREFSEL_MASK (0x3F00U)
#define FLEXSPI_STS2_AREFSEL_SHIFT (8U)
/*! AREFSEL - Flash A sample clock reference delay line delay cell number selection.
*/
#define FLEXSPI_STS2_AREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_AREFSEL_SHIFT)) & FLEXSPI_STS2_AREFSEL_MASK)
#define FLEXSPI_STS2_BSLVLOCK_MASK (0x10000U)
#define FLEXSPI_STS2_BSLVLOCK_SHIFT (16U)
/*! BSLVLOCK - Flash B sample clock slave delay line locked.
*/
#define FLEXSPI_STS2_BSLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVLOCK_SHIFT)) & FLEXSPI_STS2_BSLVLOCK_MASK)
#define FLEXSPI_STS2_BREFLOCK_MASK (0x20000U)
#define FLEXSPI_STS2_BREFLOCK_SHIFT (17U)
/*! BREFLOCK - Flash B sample clock reference delay line locked.
*/
#define FLEXSPI_STS2_BREFLOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFLOCK_SHIFT)) & FLEXSPI_STS2_BREFLOCK_MASK)
#define FLEXSPI_STS2_BSLVSEL_MASK (0xFC0000U)
#define FLEXSPI_STS2_BSLVSEL_SHIFT (18U)
/*! BSLVSEL - Flash B sample clock slave delay line delay cell number selection.
*/
#define FLEXSPI_STS2_BSLVSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BSLVSEL_SHIFT)) & FLEXSPI_STS2_BSLVSEL_MASK)
#define FLEXSPI_STS2_BREFSEL_MASK (0x3F000000U)
#define FLEXSPI_STS2_BREFSEL_SHIFT (24U)
/*! BREFSEL - Flash B sample clock reference delay line delay cell number selection.
*/
#define FLEXSPI_STS2_BREFSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_STS2_BREFSEL_SHIFT)) & FLEXSPI_STS2_BREFSEL_MASK)
/*! @} */
/*! @name AHBSPNDSTS - AHB Suspend Status Register */
/*! @{ */
#define FLEXSPI_AHBSPNDSTS_ACTIVE_MASK (0x1U)
#define FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT (0U)
/*! ACTIVE - Indicates if an AHB read prefetch command sequence has been suspended.
*/
#define FLEXSPI_AHBSPNDSTS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_ACTIVE_SHIFT)) & FLEXSPI_AHBSPNDSTS_ACTIVE_MASK)
#define FLEXSPI_AHBSPNDSTS_BUFID_MASK (0xEU)
#define FLEXSPI_AHBSPNDSTS_BUFID_SHIFT (1U)
/*! BUFID - AHB RX BUF ID for suspended command sequence.
*/
#define FLEXSPI_AHBSPNDSTS_BUFID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_BUFID_SHIFT)) & FLEXSPI_AHBSPNDSTS_BUFID_MASK)
#define FLEXSPI_AHBSPNDSTS_DATLFT_MASK (0xFFFF0000U)
#define FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT (16U)
/*! DATLFT - Left Data size for suspended command sequence (in byte).
*/
#define FLEXSPI_AHBSPNDSTS_DATLFT(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBSPNDSTS_DATLFT_SHIFT)) & FLEXSPI_AHBSPNDSTS_DATLFT_MASK)
/*! @} */
/*! @name IPRXFSTS - IP RX FIFO Status Register */
/*! @{ */
#define FLEXSPI_IPRXFSTS_FILL_MASK (0xFFU)
#define FLEXSPI_IPRXFSTS_FILL_SHIFT (0U)
/*! FILL - Fill level of IP RX FIFO.
*/
#define FLEXSPI_IPRXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_FILL_SHIFT)) & FLEXSPI_IPRXFSTS_FILL_MASK)
#define FLEXSPI_IPRXFSTS_RDCNTR_MASK (0xFFFF0000U)
#define FLEXSPI_IPRXFSTS_RDCNTR_SHIFT (16U)
/*! RDCNTR - Total Read Data Counter: RDCNTR * 64 Bits.
*/
#define FLEXSPI_IPRXFSTS_RDCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPRXFSTS_RDCNTR_SHIFT)) & FLEXSPI_IPRXFSTS_RDCNTR_MASK)
/*! @} */
/*! @name IPTXFSTS - IP TX FIFO Status Register */
/*! @{ */
#define FLEXSPI_IPTXFSTS_FILL_MASK (0xFFU)
#define FLEXSPI_IPTXFSTS_FILL_SHIFT (0U)
/*! FILL - Fill level of IP TX FIFO.
*/
#define FLEXSPI_IPTXFSTS_FILL(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_FILL_SHIFT)) & FLEXSPI_IPTXFSTS_FILL_MASK)
#define FLEXSPI_IPTXFSTS_WRCNTR_MASK (0xFFFF0000U)
#define FLEXSPI_IPTXFSTS_WRCNTR_SHIFT (16U)
/*! WRCNTR - Total Write Data Counter: WRCNTR * 64 Bits.
*/
#define FLEXSPI_IPTXFSTS_WRCNTR(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPTXFSTS_WRCNTR_SHIFT)) & FLEXSPI_IPTXFSTS_WRCNTR_MASK)
/*! @} */
/*! @name RFDR - IP RX FIFO Data Register 0..IP RX FIFO Data Register 31 */
/*! @{ */
#define FLEXSPI_RFDR_RXDATA_MASK (0xFFFFFFFFU)
#define FLEXSPI_RFDR_RXDATA_SHIFT (0U)
/*! RXDATA - RX Data
*/
#define FLEXSPI_RFDR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_RFDR_RXDATA_SHIFT)) & FLEXSPI_RFDR_RXDATA_MASK)
/*! @} */
/* The count of FLEXSPI_RFDR */
#define FLEXSPI_RFDR_COUNT (32U)
/*! @name TFDR - IP TX FIFO Data Register 0..IP TX FIFO Data Register 31 */
/*! @{ */
#define FLEXSPI_TFDR_TXDATA_MASK (0xFFFFFFFFU)
#define FLEXSPI_TFDR_TXDATA_SHIFT (0U)
/*! TXDATA - TX Data
*/
#define FLEXSPI_TFDR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_TFDR_TXDATA_SHIFT)) & FLEXSPI_TFDR_TXDATA_MASK)
/*! @} */
/* The count of FLEXSPI_TFDR */
#define FLEXSPI_TFDR_COUNT (32U)
/*! @name LUT - LUT 0..LUT 63 */
/*! @{ */
#define FLEXSPI_LUT_OPERAND0_MASK (0xFFU)
#define FLEXSPI_LUT_OPERAND0_SHIFT (0U)
/*! OPERAND0 - OPERAND0
*/
#define FLEXSPI_LUT_OPERAND0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND0_SHIFT)) & FLEXSPI_LUT_OPERAND0_MASK)
#define FLEXSPI_LUT_NUM_PADS0_MASK (0x300U)
#define FLEXSPI_LUT_NUM_PADS0_SHIFT (8U)
/*! NUM_PADS0 - NUM_PADS0
*/
#define FLEXSPI_LUT_NUM_PADS0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS0_SHIFT)) & FLEXSPI_LUT_NUM_PADS0_MASK)
#define FLEXSPI_LUT_OPCODE0_MASK (0xFC00U)
#define FLEXSPI_LUT_OPCODE0_SHIFT (10U)
/*! OPCODE0 - OPCODE
*/
#define FLEXSPI_LUT_OPCODE0(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE0_SHIFT)) & FLEXSPI_LUT_OPCODE0_MASK)
#define FLEXSPI_LUT_OPERAND1_MASK (0xFF0000U)
#define FLEXSPI_LUT_OPERAND1_SHIFT (16U)
/*! OPERAND1 - OPERAND1
*/
#define FLEXSPI_LUT_OPERAND1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPERAND1_SHIFT)) & FLEXSPI_LUT_OPERAND1_MASK)
#define FLEXSPI_LUT_NUM_PADS1_MASK (0x3000000U)
#define FLEXSPI_LUT_NUM_PADS1_SHIFT (24U)
/*! NUM_PADS1 - NUM_PADS1
*/
#define FLEXSPI_LUT_NUM_PADS1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_NUM_PADS1_SHIFT)) & FLEXSPI_LUT_NUM_PADS1_MASK)
#define FLEXSPI_LUT_OPCODE1_MASK (0xFC000000U)
#define FLEXSPI_LUT_OPCODE1_SHIFT (26U)
/*! OPCODE1 - OPCODE1
*/
#define FLEXSPI_LUT_OPCODE1(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_LUT_OPCODE1_SHIFT)) & FLEXSPI_LUT_OPCODE1_MASK)
/*! @} */
/* The count of FLEXSPI_LUT */
#define FLEXSPI_LUT_COUNT (64U)
/*! @name HMSTRCR - AHB Master ID 0 Control Register..AHB Master ID 7 Control Register */
/*! @{ */
#define FLEXSPI_HMSTRCR_MASK_MASK (0xFFFFU)
#define FLEXSPI_HMSTRCR_MASK_SHIFT (0U)
/*! MASK - Mask bits for AHB master ID.
* 0b0000000000000000..Mask
* 0b0000000000000001..Unmask
*/
#define FLEXSPI_HMSTRCR_MASK(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MASK_SHIFT)) & FLEXSPI_HMSTRCR_MASK_MASK)
#define FLEXSPI_HMSTRCR_MSTRID_MASK (0xFFFF0000U)
#define FLEXSPI_HMSTRCR_MSTRID_SHIFT (16U)
/*! MSTRID - This is expected Master ID.
*/
#define FLEXSPI_HMSTRCR_MSTRID(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HMSTRCR_MSTRID_SHIFT)) & FLEXSPI_HMSTRCR_MSTRID_MASK)
/*! @} */
/* The count of FLEXSPI_HMSTRCR */
#define FLEXSPI_HMSTRCR_COUNT (8U)
/*! @name HADDRSTART - HADDR REMAP START ADDR */
/*! @{ */
#define FLEXSPI_HADDRSTART_REMAPEN_MASK (0x1U)
#define FLEXSPI_HADDRSTART_REMAPEN_SHIFT (0U)
/*! REMAPEN
* 0b0..HADDR REMAP Disabled
* 0b1..HADDR REMAP Enabled
*/
#define FLEXSPI_HADDRSTART_REMAPEN(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_REMAPEN_SHIFT)) & FLEXSPI_HADDRSTART_REMAPEN_MASK)
#define FLEXSPI_HADDRSTART_KBINECC_MASK (0x2U)
#define FLEXSPI_HADDRSTART_KBINECC_SHIFT (1U)
/*! KBINECC
* 0b0..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset
* 0b1..If key blob is in remap region, FlexSPI will fetch keyblob at base address + offset*2
*/
#define FLEXSPI_HADDRSTART_KBINECC(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_KBINECC_SHIFT)) & FLEXSPI_HADDRSTART_KBINECC_MASK)
#define FLEXSPI_HADDRSTART_ADDRSTART_MASK (0xFFFFF000U)
#define FLEXSPI_HADDRSTART_ADDRSTART_SHIFT (12U)
#define FLEXSPI_HADDRSTART_ADDRSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDRSTART_ADDRSTART_SHIFT)) & FLEXSPI_HADDRSTART_ADDRSTART_MASK)
/*! @} */
/*! @name HADDREND - HADDR REMAP END ADDR */
/*! @{ */
#define FLEXSPI_HADDREND_ENDSTART_MASK (0xFFFFF000U)
#define FLEXSPI_HADDREND_ENDSTART_SHIFT (12U)
#define FLEXSPI_HADDREND_ENDSTART(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDREND_ENDSTART_SHIFT)) & FLEXSPI_HADDREND_ENDSTART_MASK)
/*! @} */
/*! @name HADDROFFSET - HADDR REMAP OFFSET */
/*! @{ */
#define FLEXSPI_HADDROFFSET_ADDROFFSET_MASK (0xFFFFF000U)
#define FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT (12U)
#define FLEXSPI_HADDROFFSET_ADDROFFSET(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_HADDROFFSET_ADDROFFSET_SHIFT)) & FLEXSPI_HADDROFFSET_ADDROFFSET_MASK)
/*! @} */
/*! @name IPSNSZSTART0 - IPS nonsecure region Start address of region 0 */
/*! @{ */
#define FLEXSPI_IPSNSZSTART0_start_address_MASK (0xFFFFF000U)
#define FLEXSPI_IPSNSZSTART0_start_address_SHIFT (12U)
/*! start_address - Start address of region 0. Minimal 4K Bytes aligned. It is flash address.
*/
#define FLEXSPI_IPSNSZSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART0_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART0_start_address_MASK)
/*! @} */
/*! @name IPSNSZEND0 - IPS nonsecure region End address of region 0 */
/*! @{ */
#define FLEXSPI_IPSNSZEND0_end_address_MASK (0xFFFFF000U)
#define FLEXSPI_IPSNSZEND0_end_address_SHIFT (12U)
/*! end_address - End address of region 0. Minimal 4K Bytes aligned. It is flash address.
*/
#define FLEXSPI_IPSNSZEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND0_end_address_SHIFT)) & FLEXSPI_IPSNSZEND0_end_address_MASK)
/*! @} */
/*! @name IPSNSZSTART1 - IPS nonsecure region Start address of region 1 */
/*! @{ */
#define FLEXSPI_IPSNSZSTART1_start_address_MASK (0xFFFFF000U)
#define FLEXSPI_IPSNSZSTART1_start_address_SHIFT (12U)
/*! start_address - Start address of region 1. Minimal 4K Bytes aligned. It is flash address.
*/
#define FLEXSPI_IPSNSZSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZSTART1_start_address_SHIFT)) & FLEXSPI_IPSNSZSTART1_start_address_MASK)
/*! @} */
/*! @name IPSNSZEND1 - IPS nonsecure region End address of region 1 */
/*! @{ */
#define FLEXSPI_IPSNSZEND1_end_address_MASK (0xFFFFF000U)
#define FLEXSPI_IPSNSZEND1_end_address_SHIFT (12U)
/*! end_address - End address of region 1. Minimal 4K Bytes aligned. It is flash address.
*/
#define FLEXSPI_IPSNSZEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_IPSNSZEND1_end_address_SHIFT)) & FLEXSPI_IPSNSZEND1_end_address_MASK)
/*! @} */
/*! @name AHBBUFREGIONSTART0 - RX BUF Start address of region 0 */
/*! @{ */
#define FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK (0xFFFFF000U)
#define FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT (12U)
/*! start_address - Start address of region 0. Minimal 4K Bytes aligned. It is system address.
*/
#define FLEXSPI_AHBBUFREGIONSTART0_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART0_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART0_start_address_MASK)
/*! @} */
/*! @name AHBBUFREGIONEND0 - RX BUF region End address of region 0 */
/*! @{ */
#define FLEXSPI_AHBBUFREGIONEND0_end_address_MASK (0xFFFFF000U)
#define FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT (12U)
/*! end_address - End address of region 0. Minimal 4K Bytes aligned. It is system address.
*/
#define FLEXSPI_AHBBUFREGIONEND0_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND0_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND0_end_address_MASK)
/*! @} */
/*! @name AHBBUFREGIONSTART1 - RX BUF Start address of region 1 */
/*! @{ */
#define FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK (0xFFFFF000U)
#define FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT (12U)
/*! start_address - Start address of region 1. Minimal 4K Bytes aligned. It is system address.
*/
#define FLEXSPI_AHBBUFREGIONSTART1_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART1_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART1_start_address_MASK)
/*! @} */
/*! @name AHBBUFREGIONEND1 - RX BUF region End address of region 1 */
/*! @{ */
#define FLEXSPI_AHBBUFREGIONEND1_end_address_MASK (0xFFFFF000U)
#define FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT (12U)
/*! end_address - End address of region 1. Minimal 4K Bytes aligned. It is system address.
*/
#define FLEXSPI_AHBBUFREGIONEND1_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND1_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND1_end_address_MASK)
/*! @} */
/*! @name AHBBUFREGIONSTART2 - RX BUF Start address of region 2 */
/*! @{ */
#define FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK (0xFFFFF000U)
#define FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT (12U)
/*! start_address - Start address of region 2. Minimal 4K Bytes aligned. It is system address.
*/
#define FLEXSPI_AHBBUFREGIONSTART2_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART2_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART2_start_address_MASK)
/*! @} */
/*! @name AHBBUFREGIONEND2 - RX BUF region End address of region 2 */
/*! @{ */
#define FLEXSPI_AHBBUFREGIONEND2_end_address_MASK (0xFFFFF000U)
#define FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT (12U)
/*! end_address - End address of region 2. Minimal 4K Bytes aligned. It is system address.
*/
#define FLEXSPI_AHBBUFREGIONEND2_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND2_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND2_end_address_MASK)
/*! @} */
/*! @name AHBBUFREGIONSTART3 - RX BUF Start address of region 3 */
/*! @{ */
#define FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK (0xFFFFF000U)
#define FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT (12U)
/*! start_address - Start address of region 3. Minimal 4K Bytes aligned. It is system address.
*/
#define FLEXSPI_AHBBUFREGIONSTART3_start_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONSTART3_start_address_SHIFT)) & FLEXSPI_AHBBUFREGIONSTART3_start_address_MASK)
/*! @} */
/*! @name AHBBUFREGIONEND3 - RX BUF region End address of region 3 */
/*! @{ */
#define FLEXSPI_AHBBUFREGIONEND3_end_address_MASK (0xFFFFF000U)
#define FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT (12U)
/*! end_address - End address of region 3. Minimal 4K Bytes aligned. It is system address.
*/
#define FLEXSPI_AHBBUFREGIONEND3_end_address(x) (((uint32_t)(((uint32_t)(x)) << FLEXSPI_AHBBUFREGIONEND3_end_address_SHIFT)) & FLEXSPI_AHBBUFREGIONEND3_end_address_MASK)
/*! @} */
/*!
* @}
*/ /* end of group FLEXSPI_Register_Masks */
/* FLEXSPI - Peripheral instance base addresses */
/** Peripheral FLEXSPI1 base address */
#define FLEXSPI1_BASE (0x400CC000u)
/** Peripheral FLEXSPI1 base pointer */
#define FLEXSPI1 ((FLEXSPI_Type *)FLEXSPI1_BASE)
/** Peripheral FLEXSPI2 base address */
#define FLEXSPI2_BASE (0x400D0000u)
/** Peripheral FLEXSPI2 base pointer */
#define FLEXSPI2 ((FLEXSPI_Type *)FLEXSPI2_BASE)
/** Array initializer of FLEXSPI peripheral base addresses */
#define FLEXSPI_BASE_ADDRS { 0u, FLEXSPI1_BASE, FLEXSPI2_BASE }
/** Array initializer of FLEXSPI peripheral base pointers */
#define FLEXSPI_BASE_PTRS { (FLEXSPI_Type *)0u, FLEXSPI1, FLEXSPI2 }
/** Interrupt vectors for the FLEXSPI peripheral type */
#define FLEXSPI_IRQS { NotAvail_IRQn, FLEXSPI1_IRQn, FLEXSPI2_IRQn }
/* FlexSPI1 AMBA address. */
#define FlexSPI1_AMBA_BASE (0x30000000U)
/* FlexSPI1 ASFM address. */
#define FlexSPI1_ASFM_BASE (0x30000000U)
/* Base Address of AHB address space mapped to IP RX FIFO. */
#define FlexSPI1_ARDF_BASE (0x2FC00000U)
/* Base Address of AHB address space mapped to IP TX FIFO. */
#define FlexSPI1_ATDF_BASE (0x2F800000U)
/* FlexSPI1 alias base address. */
#define FlexSPI1_ALIAS_BASE (0x8000000U)
/* FlexSPI2 AMBA address. */
#define FlexSPI2_AMBA_BASE (0x60000000U)
/* FlexSPI ASFM address. */
#define FlexSPI2_ASFM_BASE (0x60000000U)
/* Base Address of AHB address space mapped to IP RX FIFO. */
#define FlexSPI2_ARDF_BASE (0x7FC00000U)
/* Base Address of AHB address space mapped to IP TX FIFO. */
#define FlexSPI2_ATDF_BASE (0x7F800000U)
/*!
* @}
*/ /* end of group FLEXSPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPC_CPU_MODE_CTRL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_CPU_MODE_CTRL_Peripheral_Access_Layer GPC_CPU_MODE_CTRL Peripheral Access Layer
* @{
*/
/** GPC_CPU_MODE_CTRL - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t CM_AUTHEN_CTRL; /**< CM Authentication Control, offset: 0x4 */
__IO uint32_t CM_INT_CTRL; /**< CM Interrupt Control, offset: 0x8 */
__IO uint32_t CM_MISC; /**< Miscellaneous, offset: 0xC */
__IO uint32_t CM_MODE_CTRL; /**< CPU mode control, offset: 0x10 */
__I uint32_t CM_MODE_STAT; /**< CM CPU mode Status, offset: 0x14 */
uint8_t RESERVED_1[232];
__IO uint32_t CM_IRQ_WAKEUP_MASK[8]; /**< CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_2[32];
__IO uint32_t CM_NON_IRQ_WAKEUP_MASK; /**< CM non-irq wakeup mask, offset: 0x140 */
uint8_t RESERVED_3[12];
__I uint32_t CM_IRQ_WAKEUP_STAT[8]; /**< CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status, array offset: 0x150, array step: 0x4 */
uint8_t RESERVED_4[32];
__I uint32_t CM_NON_IRQ_WAKEUP_STAT; /**< CM non-irq wakeup status, offset: 0x190 */
uint8_t RESERVED_5[108];
__IO uint32_t CM_SLEEP_SSAR_CTRL; /**< CM sleep SSAR control, offset: 0x200 */
uint8_t RESERVED_6[4];
__IO uint32_t CM_SLEEP_LPCG_CTRL; /**< CM sleep LPCG control, offset: 0x208 */
uint8_t RESERVED_7[4];
__IO uint32_t CM_SLEEP_PLL_CTRL; /**< CM sleep PLL control, offset: 0x210 */
uint8_t RESERVED_8[4];
__IO uint32_t CM_SLEEP_ISO_CTRL; /**< CM sleep isolation control, offset: 0x218 */
uint8_t RESERVED_9[4];
__IO uint32_t CM_SLEEP_RESET_CTRL; /**< CM sleep reset control, offset: 0x220 */
uint8_t RESERVED_10[4];
__IO uint32_t CM_SLEEP_POWER_CTRL; /**< CM sleep power control, offset: 0x228 */
uint8_t RESERVED_11[100];
__IO uint32_t CM_WAKEUP_POWER_CTRL; /**< CM wakeup power control, offset: 0x290 */
uint8_t RESERVED_12[4];
__IO uint32_t CM_WAKEUP_RESET_CTRL; /**< CM wakeup reset control, offset: 0x298 */
uint8_t RESERVED_13[4];
__IO uint32_t CM_WAKEUP_ISO_CTRL; /**< CM wakeup isolation control, offset: 0x2A0 */
uint8_t RESERVED_14[4];
__IO uint32_t CM_WAKEUP_PLL_CTRL; /**< CM wakeup PLL control, offset: 0x2A8 */
uint8_t RESERVED_15[4];
__IO uint32_t CM_WAKEUP_LPCG_CTRL; /**< CM wakeup LPCG control, offset: 0x2B0 */
uint8_t RESERVED_16[4];
__IO uint32_t CM_WAKEUP_SSAR_CTRL; /**< CM wakeup SSAR control, offset: 0x2B8 */
uint8_t RESERVED_17[68];
__IO uint32_t CM_SP_CTRL; /**< CM Setpoint Control, offset: 0x300 */
__I uint32_t CM_SP_STAT; /**< CM Setpoint Status, offset: 0x304 */
uint8_t RESERVED_18[8];
__IO uint32_t CM_RUN_MODE_MAPPING; /**< CM Run Mode Setpoint Allowed, offset: 0x310 */
__IO uint32_t CM_WAIT_MODE_MAPPING; /**< CM Wait Mode Setpoint Allowed, offset: 0x314 */
__IO uint32_t CM_STOP_MODE_MAPPING; /**< CM Stop Mode Setpoint Allowed, offset: 0x318 */
__IO uint32_t CM_SUSPEND_MODE_MAPPING; /**< CM Suspend Mode Setpoint Allowed, offset: 0x31C */
__IO uint32_t CM_SP_MAPPING[16]; /**< CM Setpoint 0 Mapping..CM Setpoint 15 Mapping, array offset: 0x320, array step: 0x4 */
uint8_t RESERVED_19[32];
__IO uint32_t CM_STBY_CTRL; /**< CM standby control, offset: 0x380 */
} GPC_CPU_MODE_CTRL_Type;
/* ----------------------------------------------------------------------------
-- GPC_CPU_MODE_CTRL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_CPU_MODE_CTRL_Register_Masks GPC_CPU_MODE_CTRL Register Masks
* @{
*/
/*! @name CM_AUTHEN_CTRL - CM Authentication Control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK (0x1U)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT (0U)
/*! USER - Allow user mode access
* 0b0..Allow only privilege mode to access CPU mode control registers
* 0b1..Allow both privilege and user mode to access CPU mode control registers
*/
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_USER_MASK)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
/*! NONSECURE - Allow non-secure mode access
* 0b0..Allow only secure mode to access CPU mode control registers
* 0b1..Allow both secure and non-secure mode to access CPU mode control registers
*/
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_NONSECURE_MASK)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_SETTING_MASK)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Domain ID white list
*/
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_WHITE_LIST_MASK)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - White list lock
*/
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_LIST_MASK)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
/*! LOCK_CFG - Configuration lock
*/
#define GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_CPU_MODE_CTRL_CM_AUTHEN_CTRL_LOCK_CFG_MASK)
/*! @} */
/*! @name CM_INT_CTRL - CM Interrupt Control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK (0x1U)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT (0U)
/*! SP_REQ_NOT_ALLOWED_SLEEP_INT_EN - sp_req_not_allowed_for_sleep interrupt enable
* 0b0..Interrupt disable
* 0b1..Interrupt enable
*/
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_EN_MASK)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK (0x2U)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT (1U)
/*! SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN - sp_req_not_allowed_for_wakeup interrupt enable
* 0b0..Interrupt disable
* 0b1..Interrupt enable
*/
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_EN_MASK)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK (0x4U)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT (2U)
/*! SP_REQ_NOT_ALLOWED_SOFT_INT_EN - sp_req_not_allowed_for_soft interrupt enable
* 0b0..Interrupt disable
* 0b1..Interrupt enable
*/
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_EN_MASK)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK (0x10000U)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT (16U)
/*! SP_REQ_NOT_ALLOWED_SLEEP_INT - sp_req_not_allowed_for_sleep interrupt status and clear register
*/
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SLEEP_INT_MASK)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK (0x20000U)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT (17U)
/*! SP_REQ_NOT_ALLOWED_WAKEUP_INT - sp_req_not_allowed_for_wakeup interrupt status and clear register
*/
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_WAKEUP_INT_MASK)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK (0x40000U)
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT (18U)
/*! SP_REQ_NOT_ALLOWED_SOFT_INT - sp_req_not_allowed_for_soft interrupt status and clear register
*/
#define GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_INT_CTRL_SP_REQ_NOT_ALLOWED_SOFT_INT_MASK)
/*! @} */
/*! @name CM_MISC - Miscellaneous */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK (0x1U)
#define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT (0U)
/*! NMI_STAT - Non-masked interrupt status
* 0b0..NMI is not asserting
* 0b1..NMI is asserting
*/
#define GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_NMI_STAT_MASK)
#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK (0x2U)
#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT (1U)
/*! SLEEP_HOLD_EN - Allow cpu_sleep_hold_req assert during CPU low power status
* 0b0..Disable cpu_sleep_hold_req
* 0b1..Allow cpu_sleep_hold_req assert during CPU low power status
*/
#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_EN_MASK)
#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK (0x4U)
#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT (2U)
/*! SLEEP_HOLD_STAT - Status of cpu_sleep_hold_ack_b
*/
#define GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_SLEEP_HOLD_STAT_MASK)
#define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK (0x10U)
#define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT (4U)
/*! MASTER_CPU - Master CPU
*/
#define GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MISC_MASTER_CPU_MASK)
/*! @} */
/*! @name CM_MODE_CTRL - CPU mode control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK (0x3U)
#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT (0U)
/*! CPU_MODE_TARGET - The CPU mode the CPU platform should transit to on next sleep event
* 0b00..Stay in RUN mode
* 0b01..Transit to WAIT mode
* 0b10..Transit to STOP mode
* 0b11..Transit to SUSPEND mode
*/
#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_CPU_MODE_TARGET_MASK)
#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK (0x10U)
#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT (4U)
/*! WFE_EN - WFE assertion can be sleep event
* 0b0..WFE assertion can not trigger low power
* 0b1..WFE assertion can trigger low power
*/
#define GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_CTRL_WFE_EN_MASK)
/*! @} */
/*! @name CM_MODE_STAT - CM CPU mode Status */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK (0x3U)
#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT (0U)
/*! CPU_MODE_CURRENT - Current CPU mode
* 0b00..CPU is currently in RUN mode
* 0b01..CPU is currently in WAIT mode
* 0b10..CPU is currently in STOP mode
* 0b11..CPU is currently in SUSPEND mode
*/
#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_CURRENT_MASK)
#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK (0xCU)
#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT (2U)
/*! CPU_MODE_PREVIOUS - Previous CPU mode
* 0b00..CPU was previously in RUN mode
* 0b01..CPU was previously in WAIT mode
* 0b10..CPU was previously in STOP mode
* 0b11..CPU was previously in SUSPEND mode
*/
#define GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_MODE_STAT_CPU_MODE_PREVIOUS_MASK)
/*! @} */
/*! @name CM_IRQ_WAKEUP_MASK - CM IRQ0~31 wakeup mask..CM IRQ224~255 wakeup mask */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT (0U)
/*! IRQ_WAKEUP_MASK_0_31 - "1" means the IRQ cannot wakeup CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_0_31_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT (0U)
/*! IRQ_WAKEUP_MASK_32_63 - "1" means the IRQ cannot wakeup CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_32_63_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT (0U)
/*! IRQ_WAKEUP_MASK_64_95 - "1" means the IRQ cannot wakeup CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_64_95_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT (0U)
/*! IRQ_WAKEUP_MASK_96_127 - "1" means the IRQ cannot wakeup CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_96_127_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT (0U)
/*! IRQ_WAKEUP_MASK_128_159 - "1" means the IRQ cannot wakeup CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_128_159_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT (0U)
/*! IRQ_WAKEUP_MASK_160_191 - "1" means the IRQ cannot wakeup CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_160_191_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT (0U)
/*! IRQ_WAKEUP_MASK_192_223 - "1" means the IRQ cannot wakeup CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_192_223_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT (0U)
/*! IRQ_WAKEUP_MASK_224_255 - "1" means the IRQ cannot wakeup CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_IRQ_WAKEUP_MASK_224_255_MASK)
/*! @} */
/* The count of GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK */
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_MASK_COUNT (8U)
/*! @name CM_NON_IRQ_WAKEUP_MASK - CM non-irq wakeup mask */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK (0x1U)
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT (0U)
/*! EVENT_WAKEUP_MASK - There are 256 interrupts and 1 event as a wakeup source for GPC. This field masks the 1 event wakeup source.
* 0b1..The event cannot wakeup CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_EVENT_WAKEUP_MASK_MASK)
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK (0x2U)
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT (1U)
/*! DEBUG_WAKEUP_MASK - "1" means the debug_wakeup_request cannot wakeup CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_MASK_DEBUG_WAKEUP_MASK_MASK)
/*! @} */
/*! @name CM_IRQ_WAKEUP_STAT - CM IRQ0~31 wakeup status..CM IRQ224~255 wakeup status */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT (0U)
/*! IRQ_WAKEUP_MASK_224_255 - IRQ status
* 0b00000000000000000000000000000000..None
* 0b00000000000000000000000000000001..Valid
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_MASK_224_255_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT (0U)
/*! IRQ_WAKEUP_STAT_0_31 - IRQ status
* 0b00000000000000000000000000000000..None
* 0b00000000000000000000000000000001..Valid
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_0_31_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT (0U)
/*! IRQ_WAKEUP_STAT_32_63 - IRQ status
* 0b00000000000000000000000000000000..None
* 0b00000000000000000000000000000001..Valid
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_32_63_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT (0U)
/*! IRQ_WAKEUP_STAT_64_95 - IRQ status
* 0b00000000000000000000000000000000..None
* 0b00000000000000000000000000000001..Valid
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_64_95_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT (0U)
/*! IRQ_WAKEUP_STAT_96_127 - IRQ status
* 0b00000000000000000000000000000000..None
* 0b00000000000000000000000000000001..Valid
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_96_127_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT (0U)
/*! IRQ_WAKEUP_STAT_128_159 - IRQ status
* 0b00000000000000000000000000000000..None
* 0b00000000000000000000000000000001..Valid
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_128_159_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT (0U)
/*! IRQ_WAKEUP_STAT_160_191 - IRQ status
* 0b00000000000000000000000000000000..None
* 0b00000000000000000000000000000001..Valid
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_160_191_MASK)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK (0xFFFFFFFFU)
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT (0U)
/*! IRQ_WAKEUP_STAT_192_223 - IRQ status
* 0b00000000000000000000000000000000..None
* 0b00000000000000000000000000000001..Valid
*/
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_SHIFT)) & GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_IRQ_WAKEUP_STAT_192_223_MASK)
/*! @} */
/* The count of GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT */
#define GPC_CPU_MODE_CTRL_CM_IRQ_WAKEUP_STAT_COUNT (8U)
/*! @name CM_NON_IRQ_WAKEUP_STAT - CM non-irq wakeup status */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK (0x1U)
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT (0U)
/*! EVENT_WAKEUP_STAT - Event wakeup status
* 0b1..Interrupt is asserting (pending)
*/
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_EVENT_WAKEUP_STAT_MASK)
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK (0x2U)
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT (1U)
/*! DEBUG_WAKEUP_STAT - Debug wakeup status
*/
#define GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_NON_IRQ_WAKEUP_STAT_DEBUG_WAKEUP_STAT_MASK)
/*! @} */
/*! @name CM_SLEEP_SSAR_CTRL - CM sleep SSAR control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE.
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_SSAR_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_SLEEP_LPCG_CTRL - CM sleep LPCG control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_LPCG_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_SLEEP_PLL_CTRL - CM sleep PLL control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_PLL_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_SLEEP_ISO_CTRL - CM sleep isolation control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_ISO_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_SLEEP_RESET_CTRL - CM sleep reset control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_RESET_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_SLEEP_POWER_CTRL - CM sleep power control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SLEEP_POWER_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_WAKEUP_POWER_CTRL - CM wakeup power control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_POWER_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_WAKEUP_RESET_CTRL - CM wakeup reset control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_RESET_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_WAKEUP_ISO_CTRL - CM wakeup isolation control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_ISO_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_WAKEUP_PLL_CTRL - CM wakeup PLL control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_PLL_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_WAKEUP_LPCG_CTRL - CM wakeup LPCG control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_LPCG_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_WAKEUP_SSAR_CTRL - CM wakeup SSAR control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_STEP_CNT_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_CNT_MODE_MASK)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAKEUP_SSAR_CTRL_DISABLE_MASK)
/*! @} */
/*! @name CM_SP_CTRL - CM Setpoint Control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK (0x1U)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT (0U)
/*! CPU_SP_RUN_EN - Request a Setpoint transition when this bit is set
*/
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_EN_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK (0x1EU)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT (1U)
/*! CPU_SP_RUN - The Setpoint that CPU want the system to transit to when CPU_SP_RUN_EN is set
*/
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_RUN_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK (0x20U)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT (5U)
/*! CPU_SP_SLEEP_EN - 1 means enable Setpoint transition on next CPU platform sleep sequence
*/
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_EN_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK (0x3C0U)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT (6U)
/*! CPU_SP_SLEEP - The Setpoint that CPU want the system to transit to on next CPU platform sleep sequence
*/
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_SLEEP_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK (0x400U)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT (10U)
/*! CPU_SP_WAKEUP_EN - 1 means enable Setpoint transition on next CPU platform wakeup sequence
*/
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_EN_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK (0x7800U)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT (11U)
/*! CPU_SP_WAKEUP - The Setpoint that CPU want the system to transit to on next CPU platform wakeup sequence
*/
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK (0x8000U)
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT (15U)
/*! CPU_SP_WAKEUP_SEL - Select the Setpoint transiton on the next CPU platform wakeup sequence
* 0b0..Request SP transition to CPU_SP_WAKEUP
* 0b1..Request SP transition to the Setpoint when the sleep event happens, which is captured in CPU_SP_PREVIOUS
*/
#define GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_CTRL_CPU_SP_WAKEUP_SEL_MASK)
/*! @} */
/*! @name CM_SP_STAT - CM Setpoint Status */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK (0xFU)
#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT (0U)
/*! CPU_SP_CURRENT - The current Setpoint of the system
*/
#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_CURRENT_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK (0xF0U)
#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT (4U)
/*! CPU_SP_PREVIOUS - The previous Setpoint of the system
*/
#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_PREVIOUS_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK (0xF00U)
#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT (8U)
/*! CPU_SP_TARGET - The requested Setpoint from the CPU platform
*/
#define GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_STAT_CPU_SP_TARGET_MASK)
/*! @} */
/*! @name CM_RUN_MODE_MAPPING - CM Run Mode Setpoint Allowed */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT (0U)
/*! CPU_RUN_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters RUN mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_RUN_MODE_MAPPING_CPU_RUN_MODE_MAPPING_MASK)
/*! @} */
/*! @name CM_WAIT_MODE_MAPPING - CM Wait Mode Setpoint Allowed */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT (0U)
/*! CPU_WAIT_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters WAIT mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG
*/
#define GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_WAIT_MODE_MAPPING_CPU_WAIT_MODE_MAPPING_MASK)
/*! @} */
/*! @name CM_STOP_MODE_MAPPING - CM Stop Mode Setpoint Allowed */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT (0U)
/*! CPU_STOP_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters STOP mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG
*/
#define GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STOP_MODE_MAPPING_CPU_STOP_MODE_MAPPING_MASK)
/*! @} */
/*! @name CM_SUSPEND_MODE_MAPPING - CM Suspend Mode Setpoint Allowed */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT (0U)
/*! CPU_SUSPEND_MODE_MAPPING - Defines which Setpoint is allowed when CPU enters SUSPEND mode. Each bit stands for 1 Setpoint, locked by LOCK_CFG
*/
#define GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SUSPEND_MODE_MAPPING_CPU_SUSPEND_MODE_MAPPING_MASK)
/*! @} */
/*! @name CM_SP_MAPPING - CM Setpoint 0 Mapping..CM Setpoint 15 Mapping */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT (0U)
/*! CPU_SP0_MAPPING - Defines when SP0 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP0_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT (0U)
/*! CPU_SP1_MAPPING - Defines when SP1 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP1_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT (0U)
/*! CPU_SP2_MAPPING - Defines when SP2 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP2_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT (0U)
/*! CPU_SP3_MAPPING - Defines when SP3 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP3_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT (0U)
/*! CPU_SP4_MAPPING - Defines when SP4 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP4_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT (0U)
/*! CPU_SP5_MAPPING - Defines when SP5 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP5_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT (0U)
/*! CPU_SP6_MAPPING - Defines when SP6 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP6_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT (0U)
/*! CPU_SP7_MAPPING - Defines when SP7 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP7_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT (0U)
/*! CPU_SP8_MAPPING - Defines when SP8 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP8_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT (0U)
/*! CPU_SP9_MAPPING - Defines when SP9 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP9_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT (0U)
/*! CPU_SP10_MAPPING - Defines when SP10 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP10_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT (0U)
/*! CPU_SP11_MAPPING - Defines when SP11 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP11_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT (0U)
/*! CPU_SP12_MAPPING - Defines when SP12 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP12_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT (0U)
/*! CPU_SP13_MAPPING - Defines when SP13 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP13_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT (0U)
/*! CPU_SP14_MAPPING - Defines when SP14 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP14_MAPPING_MASK)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK (0xFFFFU)
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT (0U)
/*! CPU_SP15_MAPPING - Defines when SP15 is set as the CPU_SP_TARGET, which SP is allowed, locked by LOCK_CFG field
*/
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_SHIFT)) & GPC_CPU_MODE_CTRL_CM_SP_MAPPING_CPU_SP15_MAPPING_MASK)
/*! @} */
/* The count of GPC_CPU_MODE_CTRL_CM_SP_MAPPING */
#define GPC_CPU_MODE_CTRL_CM_SP_MAPPING_COUNT (16U)
/*! @name CM_STBY_CTRL - CM standby control */
/*! @{ */
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK (0x1U)
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT (0U)
/*! STBY_WAIT - 0x1: Request the chip into standby mode when CPU entering WAIT mode, locked by LOCK_CFG field.
*/
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAIT_MASK)
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK (0x2U)
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT (1U)
/*! STBY_STOP - 0x1: Request the chip into standby mode when CPU entering STOP mode, locked by LOCK_CFG field.
*/
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_STOP_MASK)
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK (0x4U)
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT (2U)
/*! STBY_SUSPEND - 0x1: Request the chip into standby mode when CPU entering SUSPEND mode, locked by LOCK_CFG field.
*/
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SUSPEND_MASK)
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK (0x10000U)
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT (16U)
/*! STBY_SLEEP_BUSY - Indicate the CPU is busy entering standby mode.
*/
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_SLEEP_BUSY_MASK)
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK (0x20000U)
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT (17U)
/*! STBY_WAKEUP_BUSY - Indicate the CPU is busy exiting standby mode.
*/
#define GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY(x) (((uint32_t)(((uint32_t)(x)) << GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_SHIFT)) & GPC_CPU_MODE_CTRL_CM_STBY_CTRL_STBY_WAKEUP_BUSY_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPC_CPU_MODE_CTRL_Register_Masks */
/* GPC_CPU_MODE_CTRL - Peripheral instance base addresses */
/** Peripheral GPC_CPU_MODE_CTRL_0 base address */
#define GPC_CPU_MODE_CTRL_0_BASE (0x40C00000u)
/** Peripheral GPC_CPU_MODE_CTRL_0 base pointer */
#define GPC_CPU_MODE_CTRL_0 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_0_BASE)
/** Peripheral GPC_CPU_MODE_CTRL_1 base address */
#define GPC_CPU_MODE_CTRL_1_BASE (0x40C00800u)
/** Peripheral GPC_CPU_MODE_CTRL_1 base pointer */
#define GPC_CPU_MODE_CTRL_1 ((GPC_CPU_MODE_CTRL_Type *)GPC_CPU_MODE_CTRL_1_BASE)
/** Array initializer of GPC_CPU_MODE_CTRL peripheral base addresses */
#define GPC_CPU_MODE_CTRL_BASE_ADDRS { GPC_CPU_MODE_CTRL_0_BASE, GPC_CPU_MODE_CTRL_1_BASE }
/** Array initializer of GPC_CPU_MODE_CTRL peripheral base pointers */
#define GPC_CPU_MODE_CTRL_BASE_PTRS { GPC_CPU_MODE_CTRL_0, GPC_CPU_MODE_CTRL_1 }
/*!
* @}
*/ /* end of group GPC_CPU_MODE_CTRL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPC_SET_POINT_CTRL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_SET_POINT_CTRL_Peripheral_Access_Layer GPC_SET_POINT_CTRL Peripheral Access Layer
* @{
*/
/** GPC_SET_POINT_CTRL - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t SP_AUTHEN_CTRL; /**< SP Authentication Control, offset: 0x4 */
__IO uint32_t SP_INT_CTRL; /**< SP Interrupt Control, offset: 0x8 */
uint8_t RESERVED_1[4];
__I uint32_t SP_CPU_REQ; /**< CPU SP Request, offset: 0x10 */
__I uint32_t SP_SYS_STAT; /**< SP System Status, offset: 0x14 */
uint8_t RESERVED_2[4];
__IO uint32_t SP_ROSC_CTRL; /**< SP ROSC Control, offset: 0x1C */
uint8_t RESERVED_3[32];
__IO uint32_t SP_PRIORITY_0_7; /**< SP0~7 Priority, offset: 0x40 */
__IO uint32_t SP_PRIORITY_8_15; /**< SP8~15 Priority, offset: 0x44 */
uint8_t RESERVED_4[184];
__IO uint32_t SP_SSAR_SAVE_CTRL; /**< SP SSAR save control, offset: 0x100 */
uint8_t RESERVED_5[12];
__IO uint32_t SP_LPCG_OFF_CTRL; /**< SP LPCG off control, offset: 0x110 */
uint8_t RESERVED_6[12];
__IO uint32_t SP_GROUP_DOWN_CTRL; /**< SP group down control, offset: 0x120 */
uint8_t RESERVED_7[12];
__IO uint32_t SP_ROOT_DOWN_CTRL; /**< SP root down control, offset: 0x130 */
uint8_t RESERVED_8[12];
__IO uint32_t SP_PLL_OFF_CTRL; /**< SP PLL off control, offset: 0x140 */
uint8_t RESERVED_9[12];
__IO uint32_t SP_ISO_ON_CTRL; /**< SP ISO on control, offset: 0x150 */
uint8_t RESERVED_10[12];
__IO uint32_t SP_RESET_EARLY_CTRL; /**< SP reset early control, offset: 0x160 */
uint8_t RESERVED_11[12];
__IO uint32_t SP_POWER_OFF_CTRL; /**< SP power off control, offset: 0x170 */
uint8_t RESERVED_12[12];
__IO uint32_t SP_BIAS_OFF_CTRL; /**< SP bias off control, offset: 0x180 */
uint8_t RESERVED_13[12];
__IO uint32_t SP_BG_PLDO_OFF_CTRL; /**< SP bandgap and PLL_LDO off control, offset: 0x190 */
uint8_t RESERVED_14[12];
__IO uint32_t SP_LDO_PRE_CTRL; /**< SP LDO pre control, offset: 0x1A0 */
uint8_t RESERVED_15[12];
__IO uint32_t SP_DCDC_DOWN_CTRL; /**< SP DCDC down control, offset: 0x1B0 */
uint8_t RESERVED_16[76];
__IO uint32_t SP_DCDC_UP_CTRL; /**< SP DCDC up control, offset: 0x200 */
uint8_t RESERVED_17[12];
__IO uint32_t SP_LDO_POST_CTRL; /**< SP LDO post control, offset: 0x210 */
uint8_t RESERVED_18[12];
__IO uint32_t SP_BG_PLDO_ON_CTRL; /**< SP bandgap and PLL_LDO on control, offset: 0x220 */
uint8_t RESERVED_19[12];
__IO uint32_t SP_BIAS_ON_CTRL; /**< SP bias on control, offset: 0x230 */
uint8_t RESERVED_20[12];
__IO uint32_t SP_POWER_ON_CTRL; /**< SP power on control, offset: 0x240 */
uint8_t RESERVED_21[12];
__IO uint32_t SP_RESET_LATE_CTRL; /**< SP reset late control, offset: 0x250 */
uint8_t RESERVED_22[12];
__IO uint32_t SP_ISO_OFF_CTRL; /**< SP ISO off control, offset: 0x260 */
uint8_t RESERVED_23[12];
__IO uint32_t SP_PLL_ON_CTRL; /**< SP PLL on control, offset: 0x270 */
uint8_t RESERVED_24[12];
__IO uint32_t SP_ROOT_UP_CTRL; /**< SP root up control, offset: 0x280 */
uint8_t RESERVED_25[12];
__IO uint32_t SP_GROUP_UP_CTRL; /**< SP group up control, offset: 0x290 */
uint8_t RESERVED_26[12];
__IO uint32_t SP_LPCG_ON_CTRL; /**< SP LPCG on control, offset: 0x2A0 */
uint8_t RESERVED_27[12];
__IO uint32_t SP_SSAR_RESTORE_CTRL; /**< SP SSAR restore control, offset: 0x2B0 */
} GPC_SET_POINT_CTRL_Type;
/* ----------------------------------------------------------------------------
-- GPC_SET_POINT_CTRL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_SET_POINT_CTRL_Register_Masks GPC_SET_POINT_CTRL Register Masks
* @{
*/
/*! @name SP_AUTHEN_CTRL - SP Authentication Control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK (0x1U)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT (0U)
/*! USER - Allow user mode access
* 0b0..Allow only privilege mode to access setpoint control registers
* 0b1..Allow both privilege and user mode to access setpoint control registers
*/
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_USER_MASK)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
/*! NONSECURE - Allow non-secure mode access
* 0b0..Allow only secure mode to access setpoint control registers
* 0b1..Allow both secure and non-secure mode to access setpoint control registers
*/
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_NONSECURE_MASK)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_SETTING_MASK)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Domain ID white list
*/
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_WHITE_LIST_MASK)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - White list lock
*/
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_LIST_MASK)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
/*! LOCK_CFG - Configuration lock
*/
#define GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_SET_POINT_CTRL_SP_AUTHEN_CTRL_LOCK_CFG_MASK)
/*! @} */
/*! @name SP_INT_CTRL - SP Interrupt Control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK (0x1U)
#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT (0U)
/*! NO_ALLOWED_SP_INT_EN - no_allowed_set_point interrupt enable
*/
#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_EN_MASK)
#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK (0x2U)
#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT (1U)
/*! NO_ALLOWED_SP_INT - no_allowed_set_point interrupt
*/
#define GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_SHIFT)) & GPC_SET_POINT_CTRL_SP_INT_CTRL_NO_ALLOWED_SP_INT_MASK)
/*! @} */
/*! @name SP_CPU_REQ - CPU SP Request */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK (0xFU)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT (0U)
/*! SP_REQ_CPU0 - Setpoint requested by CPU0
*/
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU0_MASK)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK (0xF0U)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT (4U)
/*! SP_REQ_CPU1 - Setpoint requested by CPU1
*/
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU1_MASK)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK (0xF00U)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT (8U)
/*! SP_REQ_CPU2 - Setpoint requested by CPU2
*/
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU2_MASK)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK (0xF000U)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT (12U)
/*! SP_REQ_CPU3 - Setpoint requested by CPU3
*/
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_REQ_CPU3_MASK)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK (0xF0000U)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT (16U)
/*! SP_ACCEPTED_CPU0 - CPU0 Setpoint accepted by SP controller
*/
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU0_MASK)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK (0xF00000U)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT (20U)
/*! SP_ACCEPTED_CPU1 - CPU1 Setpoint accepted by SP controller
*/
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU1_MASK)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK (0xF000000U)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT (24U)
/*! SP_ACCEPTED_CPU2 - CPU2 Setpoint accepted by SP controller
*/
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU2_MASK)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK (0xF0000000U)
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT (28U)
/*! SP_ACCEPTED_CPU3 - CPU3 Setpoint accepted by SP controller
*/
#define GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_SHIFT)) & GPC_SET_POINT_CTRL_SP_CPU_REQ_SP_ACCEPTED_CPU3_MASK)
/*! @} */
/*! @name SP_SYS_STAT - SP System Status */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT (0U)
/*! SYS_SP_ALLOWED - Allowed Setpoints by all current CPU Setpoint requests
*/
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_ALLOWED_MASK)
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK (0xF0000U)
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT (16U)
/*! SYS_SP_TARGET - The Setpoint chosen as the target setpoint
*/
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_TARGET_MASK)
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK (0xF00000U)
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT (20U)
/*! SYS_SP_CURRENT - Current Setpoint, only valid when not SP trans busy
*/
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_CURRENT_MASK)
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK (0xF000000U)
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT (24U)
/*! SYS_SP_PREVIOUS - Previous Setpoint, only valid when not SP trans busy
*/
#define GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_SHIFT)) & GPC_SET_POINT_CTRL_SP_SYS_STAT_SYS_SP_PREVIOUS_MASK)
/*! @} */
/*! @name SP_ROSC_CTRL - SP ROSC Control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT (0U)
/*! SP_ALLOW_ROSC_OFF - Allow shutting off the ROSC
*/
#define GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROSC_CTRL_SP_ALLOW_ROSC_OFF_MASK)
/*! @} */
/*! @name SP_PRIORITY_0_7 - SP0~7 Priority */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK (0xFU)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT (0U)
/*! SYS_SP0_PRIORITY - priority of Setpoint 0
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP0_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK (0xF0U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT (4U)
/*! SYS_SP1_PRIORITY - priority of Setpoint 1
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP1_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK (0xF00U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT (8U)
/*! SYS_SP2_PRIORITY - priority of Setpoint 2
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP2_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK (0xF000U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT (12U)
/*! SYS_SP3_PRIORITY - priority of Setpoint 3
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP3_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK (0xF0000U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT (16U)
/*! SYS_SP4_PRIORITY - priority of Setpoint 4
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP4_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK (0xF00000U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT (20U)
/*! SYS_SP5_PRIORITY - priority of Setpoint 5
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP5_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK (0xF000000U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT (24U)
/*! SYS_SP6_PRIORITY - priority of Setpoint 6
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP6_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK (0xF0000000U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT (28U)
/*! SYS_SP7_PRIORITY - priority of Setpoint 7
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_0_7_SYS_SP7_PRIORITY_MASK)
/*! @} */
/*! @name SP_PRIORITY_8_15 - SP8~15 Priority */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK (0xFU)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT (0U)
/*! SYS_SP8_PRIORITY - priority of Setpoint 8
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP8_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK (0xF0U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT (4U)
/*! SYS_SP9_PRIORITY - priority of Setpoint 9
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP9_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK (0xF00U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT (8U)
/*! SYS_SP10_PRIORITY - priority of Setpoint 10
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP10_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK (0xF000U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT (12U)
/*! SYS_SP11_PRIORITY - priority of Setpoint 11
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP11_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK (0xF0000U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT (16U)
/*! SYS_SP12_PRIORITY - priority of Setpoint 12
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP12_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK (0xF00000U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT (20U)
/*! SYS_SP13_PRIORITY - priority of Setpoint 13
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP13_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK (0xF000000U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT (24U)
/*! SYS_SP14_PRIORITY - priority of Setpoint 14
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP14_PRIORITY_MASK)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK (0xF0000000U)
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT (28U)
/*! SYS_SP15_PRIORITY - priority of Setpoint 15
*/
#define GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_SHIFT)) & GPC_SET_POINT_CTRL_SP_PRIORITY_8_15_SYS_SP15_PRIORITY_MASK)
/*! @} */
/*! @name SP_SSAR_SAVE_CTRL - SP SSAR save control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_SAVE_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_LPCG_OFF_CTRL - SP LPCG off control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_OFF_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_GROUP_DOWN_CTRL - SP group down control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_DOWN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_ROOT_DOWN_CTRL - SP root down control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_DOWN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_PLL_OFF_CTRL - SP PLL off control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_OFF_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_ISO_ON_CTRL - SP ISO on control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_ON_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_RESET_EARLY_CTRL - SP reset early control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_EARLY_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_POWER_OFF_CTRL - SP power off control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_OFF_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_BIAS_OFF_CTRL - SP bias off control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_OFF_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_BG_PLDO_OFF_CTRL - SP bandgap and PLL_LDO off control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_OFF_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_LDO_PRE_CTRL - SP LDO pre control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_PRE_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_DCDC_DOWN_CTRL - SP DCDC down control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_DOWN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_DCDC_UP_CTRL - SP DCDC up control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_DCDC_UP_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_LDO_POST_CTRL - SP LDO post control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LDO_POST_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_BG_PLDO_ON_CTRL - SP bandgap and PLL_LDO on control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BG_PLDO_ON_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_BIAS_ON_CTRL - SP bias on control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_BIAS_ON_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_POWER_ON_CTRL - SP power on control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_POWER_ON_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_RESET_LATE_CTRL - SP reset late control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_RESET_LATE_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_ISO_OFF_CTRL - SP ISO off control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ISO_OFF_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_PLL_ON_CTRL - SP PLL on control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_PLL_ON_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_ROOT_UP_CTRL - SP root up control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_ROOT_UP_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_GROUP_UP_CTRL - SP group up control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_GROUP_UP_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_LPCG_ON_CTRL - SP LPCG on control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_LPCG_ON_CTRL_DISABLE_MASK)
/*! @} */
/*! @name SP_SSAR_RESTORE_CTRL - SP SSAR restore control */
/*! @{ */
#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_STEP_CNT_MASK)
#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_CNT_MODE_MASK)
#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_SHIFT)) & GPC_SET_POINT_CTRL_SP_SSAR_RESTORE_CTRL_DISABLE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPC_SET_POINT_CTRL_Register_Masks */
/* GPC_SET_POINT_CTRL - Peripheral instance base addresses */
/** Peripheral GPC_SET_POINT_CTRL base address */
#define GPC_SET_POINT_CTRL_BASE (0x40C02000u)
/** Peripheral GPC_SET_POINT_CTRL base pointer */
#define GPC_SET_POINT_CTRL ((GPC_SET_POINT_CTRL_Type *)GPC_SET_POINT_CTRL_BASE)
/** Array initializer of GPC_SET_POINT_CTRL peripheral base addresses */
#define GPC_SET_POINT_CTRL_BASE_ADDRS { GPC_SET_POINT_CTRL_BASE }
/** Array initializer of GPC_SET_POINT_CTRL peripheral base pointers */
#define GPC_SET_POINT_CTRL_BASE_PTRS { GPC_SET_POINT_CTRL }
/*!
* @}
*/ /* end of group GPC_SET_POINT_CTRL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPC_STBY_CTRL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_STBY_CTRL_Peripheral_Access_Layer GPC_STBY_CTRL Peripheral Access Layer
* @{
*/
/** GPC_STBY_CTRL - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t STBY_AUTHEN_CTRL; /**< Standby Authentication Control, offset: 0x4 */
uint8_t RESERVED_1[4];
__IO uint32_t STBY_MISC; /**< STBY Misc, offset: 0xC */
uint8_t RESERVED_2[224];
__IO uint32_t STBY_LPCG_IN_CTRL; /**< STBY lpcg_in control, offset: 0xF0 */
uint8_t RESERVED_3[12];
__IO uint32_t STBY_PLL_IN_CTRL; /**< STBY pll_in control, offset: 0x100 */
uint8_t RESERVED_4[12];
__IO uint32_t STBY_BIAS_IN_CTRL; /**< STBY bias_in control, offset: 0x110 */
uint8_t RESERVED_5[12];
__IO uint32_t STBY_PLDO_IN_CTRL; /**< STBY pldo_in control, offset: 0x120 */
uint8_t RESERVED_6[4];
__IO uint32_t STBY_BANDGAP_IN_CTRL; /**< STBY bandgap_in control, offset: 0x128 */
uint8_t RESERVED_7[4];
__IO uint32_t STBY_LDO_IN_CTRL; /**< STBY ldo_in control, offset: 0x130 */
uint8_t RESERVED_8[12];
__IO uint32_t STBY_DCDC_IN_CTRL; /**< STBY dcdc_in control, offset: 0x140 */
uint8_t RESERVED_9[12];
__IO uint32_t STBY_PMIC_IN_CTRL; /**< STBY PMIC in control, offset: 0x150 */
uint8_t RESERVED_10[172];
__IO uint32_t STBY_PMIC_OUT_CTRL; /**< STBY PMIC out control, offset: 0x200 */
uint8_t RESERVED_11[12];
__IO uint32_t STBY_DCDC_OUT_CTRL; /**< STBY DCDC out control, offset: 0x210 */
uint8_t RESERVED_12[12];
__IO uint32_t STBY_LDO_OUT_CTRL; /**< STBY LDO out control, offset: 0x220 */
uint8_t RESERVED_13[12];
__IO uint32_t STBY_BANDGAP_OUT_CTRL; /**< STBY bandgap out control, offset: 0x230 */
uint8_t RESERVED_14[4];
__IO uint32_t STBY_PLDO_OUT_CTRL; /**< STBY pldo out control, offset: 0x238 */
uint8_t RESERVED_15[4];
__IO uint32_t STBY_BIAS_OUT_CTRL; /**< STBY bias out control, offset: 0x240 */
uint8_t RESERVED_16[12];
__IO uint32_t STBY_PLL_OUT_CTRL; /**< STBY PLL out control, offset: 0x250 */
uint8_t RESERVED_17[12];
__IO uint32_t STBY_LPCG_OUT_CTRL; /**< STBY LPCG out control, offset: 0x260 */
} GPC_STBY_CTRL_Type;
/* ----------------------------------------------------------------------------
-- GPC_STBY_CTRL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPC_STBY_CTRL_Register_Masks GPC_STBY_CTRL Register Masks
* @{
*/
/*! @name STBY_AUTHEN_CTRL - Standby Authentication Control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
#define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
/*! LOCK_CFG - Configuration lock
*/
#define GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & GPC_STBY_CTRL_STBY_AUTHEN_CTRL_LOCK_CFG_MASK)
/*! @} */
/*! @name STBY_MISC - STBY Misc */
/*! @{ */
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK (0x1U)
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT (0U)
/*! FORCE_CPU0_STBY - Force CPU0 requesting standby mode
*/
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU0_STBY_MASK)
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK (0x2U)
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT (1U)
/*! FORCE_CPU1_STBY - Force CPU0 requesting standby mode
*/
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU1_STBY_MASK)
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK (0x4U)
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT (2U)
/*! FORCE_CPU2_STBY - Force CPU2 requesting standby mode
*/
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU2_STBY_MASK)
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK (0x8U)
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT (3U)
/*! FORCE_CPU3_STBY - Force CPU3 requesting standby mode
*/
#define GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_SHIFT)) & GPC_STBY_CTRL_STBY_MISC_FORCE_CPU3_STBY_MASK)
/*! @} */
/*! @name STBY_LPCG_IN_CTRL - STBY lpcg_in control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_IN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_PLL_IN_CTRL - STBY pll_in control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_IN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_BIAS_IN_CTRL - STBY bias_in control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_IN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_PLDO_IN_CTRL - STBY pldo_in control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_IN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_BANDGAP_IN_CTRL - STBY bandgap_in control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_IN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_LDO_IN_CTRL - STBY ldo_in control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_IN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_DCDC_IN_CTRL - STBY dcdc_in control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_IN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_PMIC_IN_CTRL - STBY PMIC in control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_IN_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_PMIC_OUT_CTRL - STBY PMIC out control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PMIC_OUT_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_DCDC_OUT_CTRL - STBY DCDC out control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_DCDC_OUT_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_LDO_OUT_CTRL - STBY LDO out control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LDO_OUT_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_BANDGAP_OUT_CTRL - STBY bandgap out control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BANDGAP_OUT_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_PLDO_OUT_CTRL - STBY pldo out control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLDO_OUT_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_BIAS_OUT_CTRL - STBY bias out control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_BIAS_OUT_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_PLL_OUT_CTRL - STBY PLL out control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_PLL_OUT_CTRL_DISABLE_MASK)
/*! @} */
/*! @name STBY_LPCG_OUT_CTRL - STBY LPCG out control */
/*! @{ */
#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK (0xFFFFU)
#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT (0U)
/*! STEP_CNT - Step count, useage is depending on CNT_MODE
*/
#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_STEP_CNT_MASK)
#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK (0x30000000U)
#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT (28U)
/*! CNT_MODE - Count mode
* 0b00..Counter disable mode: not use step counter, step completes once receiving step_done
* 0b01..Counter delay mode: delay after receiving step_done, delay cycle number is STEP_CNT
* 0b10..Ignore step_done response, the counter starts to count once step begins, when counter reaches STEP_CNT value, the step completes
* 0b11..Time out mode, the counter starts to count once step begins, the step completes when either step_done received or counting to STEP_CNT value
*/
#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_CNT_MODE_MASK)
#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK (0x80000000U)
#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT (31U)
/*! DISABLE - Disable this step
*/
#define GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_SHIFT)) & GPC_STBY_CTRL_STBY_LPCG_OUT_CTRL_DISABLE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPC_STBY_CTRL_Register_Masks */
/* GPC_STBY_CTRL - Peripheral instance base addresses */
/** Peripheral GPC_STBY_CTRL base address */
#define GPC_STBY_CTRL_BASE (0x40C02800u)
/** Peripheral GPC_STBY_CTRL base pointer */
#define GPC_STBY_CTRL ((GPC_STBY_CTRL_Type *)GPC_STBY_CTRL_BASE)
/** Array initializer of GPC_STBY_CTRL peripheral base addresses */
#define GPC_STBY_CTRL_BASE_ADDRS { GPC_STBY_CTRL_BASE }
/** Array initializer of GPC_STBY_CTRL peripheral base pointers */
#define GPC_STBY_CTRL_BASE_PTRS { GPC_STBY_CTRL }
/*!
* @}
*/ /* end of group GPC_STBY_CTRL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPIO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
* @{
*/
/** GPIO - Register Layout Typedef */
typedef struct {
__IO uint32_t DR; /**< GPIO data register, offset: 0x0 */
__IO uint32_t GDIR; /**< GPIO direction register, offset: 0x4 */
__I uint32_t PSR; /**< GPIO pad status register, offset: 0x8 */
__IO uint32_t ICR1; /**< GPIO interrupt configuration register1, offset: 0xC */
__IO uint32_t ICR2; /**< GPIO interrupt configuration register2, offset: 0x10 */
__IO uint32_t IMR; /**< GPIO interrupt mask register, offset: 0x14 */
__IO uint32_t ISR; /**< GPIO interrupt status register, offset: 0x18 */
__IO uint32_t EDGE_SEL; /**< GPIO edge select register, offset: 0x1C */
uint8_t RESERVED_0[100];
__O uint32_t DR_SET; /**< GPIO data register SET, offset: 0x84 */
__O uint32_t DR_CLEAR; /**< GPIO data register CLEAR, offset: 0x88 */
__O uint32_t DR_TOGGLE; /**< GPIO data register TOGGLE, offset: 0x8C */
} GPIO_Type;
/* ----------------------------------------------------------------------------
-- GPIO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPIO_Register_Masks GPIO Register Masks
* @{
*/
/*! @name DR - GPIO data register */
/*! @{ */
#define GPIO_DR_DR_MASK (0xFFFFFFFFU)
#define GPIO_DR_DR_SHIFT (0U)
/*! DR - DR data bits
*/
#define GPIO_DR_DR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_DR_SHIFT)) & GPIO_DR_DR_MASK)
/*! @} */
/*! @name GDIR - GPIO direction register */
/*! @{ */
#define GPIO_GDIR_GDIR_MASK (0xFFFFFFFFU)
#define GPIO_GDIR_GDIR_SHIFT (0U)
/*! GDIR - GPIO direction bits
*/
#define GPIO_GDIR_GDIR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_GDIR_GDIR_SHIFT)) & GPIO_GDIR_GDIR_MASK)
/*! @} */
/*! @name PSR - GPIO pad status register */
/*! @{ */
#define GPIO_PSR_PSR_MASK (0xFFFFFFFFU)
#define GPIO_PSR_PSR_SHIFT (0U)
/*! PSR - GPIO pad status bits
*/
#define GPIO_PSR_PSR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSR_PSR_SHIFT)) & GPIO_PSR_PSR_MASK)
/*! @} */
/*! @name ICR1 - GPIO interrupt configuration register1 */
/*! @{ */
#define GPIO_ICR1_ICR0_MASK (0x3U)
#define GPIO_ICR1_ICR0_SHIFT (0U)
/*! ICR0 - Interrupt configuration field for GPIO interrupt 0
* 0b00..Interrupt 0 is low-level sensitive.
* 0b01..Interrupt 0 is high-level sensitive.
* 0b10..Interrupt 0 is rising-edge sensitive.
* 0b11..Interrupt 0 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR0(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR0_SHIFT)) & GPIO_ICR1_ICR0_MASK)
#define GPIO_ICR1_ICR1_MASK (0xCU)
#define GPIO_ICR1_ICR1_SHIFT (2U)
/*! ICR1 - Interrupt configuration field for GPIO interrupt 1
* 0b00..Interrupt 1 is low-level sensitive.
* 0b01..Interrupt 1 is high-level sensitive.
* 0b10..Interrupt 1 is rising-edge sensitive.
* 0b11..Interrupt 1 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR1(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR1_SHIFT)) & GPIO_ICR1_ICR1_MASK)
#define GPIO_ICR1_ICR2_MASK (0x30U)
#define GPIO_ICR1_ICR2_SHIFT (4U)
/*! ICR2 - Interrupt configuration field for GPIO interrupt 2
* 0b00..Interrupt 2 is low-level sensitive.
* 0b01..Interrupt 2 is high-level sensitive.
* 0b10..Interrupt 2 is rising-edge sensitive.
* 0b11..Interrupt 2 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR2(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR2_SHIFT)) & GPIO_ICR1_ICR2_MASK)
#define GPIO_ICR1_ICR3_MASK (0xC0U)
#define GPIO_ICR1_ICR3_SHIFT (6U)
/*! ICR3 - Interrupt configuration field for GPIO interrupt 3
* 0b00..Interrupt 3 is low-level sensitive.
* 0b01..Interrupt 3 is high-level sensitive.
* 0b10..Interrupt 3 is rising-edge sensitive.
* 0b11..Interrupt 3 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR3(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR3_SHIFT)) & GPIO_ICR1_ICR3_MASK)
#define GPIO_ICR1_ICR4_MASK (0x300U)
#define GPIO_ICR1_ICR4_SHIFT (8U)
/*! ICR4 - Interrupt configuration field for GPIO interrupt 4
* 0b00..Interrupt 4 is low-level sensitive.
* 0b01..Interrupt 4 is high-level sensitive.
* 0b10..Interrupt 4 is rising-edge sensitive.
* 0b11..Interrupt 4 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR4(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR4_SHIFT)) & GPIO_ICR1_ICR4_MASK)
#define GPIO_ICR1_ICR5_MASK (0xC00U)
#define GPIO_ICR1_ICR5_SHIFT (10U)
/*! ICR5 - Interrupt configuration field for GPIO interrupt 5
* 0b00..Interrupt 5 is low-level sensitive.
* 0b01..Interrupt 5 is high-level sensitive.
* 0b10..Interrupt 5 is rising-edge sensitive.
* 0b11..Interrupt 5 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR5(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR5_SHIFT)) & GPIO_ICR1_ICR5_MASK)
#define GPIO_ICR1_ICR6_MASK (0x3000U)
#define GPIO_ICR1_ICR6_SHIFT (12U)
/*! ICR6 - Interrupt configuration field for GPIO interrupt 6
* 0b00..Interrupt 6 is low-level sensitive.
* 0b01..Interrupt 6 is high-level sensitive.
* 0b10..Interrupt 6 is rising-edge sensitive.
* 0b11..Interrupt 6 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR6(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR6_SHIFT)) & GPIO_ICR1_ICR6_MASK)
#define GPIO_ICR1_ICR7_MASK (0xC000U)
#define GPIO_ICR1_ICR7_SHIFT (14U)
/*! ICR7 - Interrupt configuration field for GPIO interrupt 7
* 0b00..Interrupt 7 is low-level sensitive.
* 0b01..Interrupt 7 is high-level sensitive.
* 0b10..Interrupt 7 is rising-edge sensitive.
* 0b11..Interrupt 7 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR7(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR7_SHIFT)) & GPIO_ICR1_ICR7_MASK)
#define GPIO_ICR1_ICR8_MASK (0x30000U)
#define GPIO_ICR1_ICR8_SHIFT (16U)
/*! ICR8 - Interrupt configuration field for GPIO interrupt 8
* 0b00..Interrupt 8 is low-level sensitive.
* 0b01..Interrupt 8 is high-level sensitive.
* 0b10..Interrupt 8 is rising-edge sensitive.
* 0b11..Interrupt 8 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR8(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR8_SHIFT)) & GPIO_ICR1_ICR8_MASK)
#define GPIO_ICR1_ICR9_MASK (0xC0000U)
#define GPIO_ICR1_ICR9_SHIFT (18U)
/*! ICR9 - Interrupt configuration field for GPIO interrupt 9
* 0b00..Interrupt 9 is low-level sensitive.
* 0b01..Interrupt 9 is high-level sensitive.
* 0b10..Interrupt 9 is rising-edge sensitive.
* 0b11..Interrupt 9 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR9(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR9_SHIFT)) & GPIO_ICR1_ICR9_MASK)
#define GPIO_ICR1_ICR10_MASK (0x300000U)
#define GPIO_ICR1_ICR10_SHIFT (20U)
/*! ICR10 - Interrupt configuration field for GPIO interrupt 10
* 0b00..Interrupt 10 is low-level sensitive.
* 0b01..Interrupt 10 is high-level sensitive.
* 0b10..Interrupt 10 is rising-edge sensitive.
* 0b11..Interrupt 10 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR10(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR10_SHIFT)) & GPIO_ICR1_ICR10_MASK)
#define GPIO_ICR1_ICR11_MASK (0xC00000U)
#define GPIO_ICR1_ICR11_SHIFT (22U)
/*! ICR11 - Interrupt configuration field for GPIO interrupt 11
* 0b00..Interrupt 11 is low-level sensitive.
* 0b01..Interrupt 11 is high-level sensitive.
* 0b10..Interrupt 11 is rising-edge sensitive.
* 0b11..Interrupt 11 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR11(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR11_SHIFT)) & GPIO_ICR1_ICR11_MASK)
#define GPIO_ICR1_ICR12_MASK (0x3000000U)
#define GPIO_ICR1_ICR12_SHIFT (24U)
/*! ICR12 - Interrupt configuration field for GPIO interrupt 12
* 0b00..Interrupt 12 is low-level sensitive.
* 0b01..Interrupt 12 is high-level sensitive.
* 0b10..Interrupt 12 is rising-edge sensitive.
* 0b11..Interrupt 12 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR12(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR12_SHIFT)) & GPIO_ICR1_ICR12_MASK)
#define GPIO_ICR1_ICR13_MASK (0xC000000U)
#define GPIO_ICR1_ICR13_SHIFT (26U)
/*! ICR13 - Interrupt configuration field for GPIO interrupt 13
* 0b00..Interrupt 13 is low-level sensitive.
* 0b01..Interrupt 13 is high-level sensitive.
* 0b10..Interrupt 13 is rising-edge sensitive.
* 0b11..Interrupt 13 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR13(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR13_SHIFT)) & GPIO_ICR1_ICR13_MASK)
#define GPIO_ICR1_ICR14_MASK (0x30000000U)
#define GPIO_ICR1_ICR14_SHIFT (28U)
/*! ICR14 - Interrupt configuration field for GPIO interrupt 14
* 0b00..Interrupt 14 is low-level sensitive.
* 0b01..Interrupt 14 is high-level sensitive.
* 0b10..Interrupt 14 is rising-edge sensitive.
* 0b11..Interrupt 14 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR14(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR14_SHIFT)) & GPIO_ICR1_ICR14_MASK)
#define GPIO_ICR1_ICR15_MASK (0xC0000000U)
#define GPIO_ICR1_ICR15_SHIFT (30U)
/*! ICR15 - Interrupt configuration field for GPIO interrupt 15
* 0b00..Interrupt 15 is low-level sensitive.
* 0b01..Interrupt 15 is high-level sensitive.
* 0b10..Interrupt 15 is rising-edge sensitive.
* 0b11..Interrupt 15 is falling-edge sensitive.
*/
#define GPIO_ICR1_ICR15(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR1_ICR15_SHIFT)) & GPIO_ICR1_ICR15_MASK)
/*! @} */
/*! @name ICR2 - GPIO interrupt configuration register2 */
/*! @{ */
#define GPIO_ICR2_ICR16_MASK (0x3U)
#define GPIO_ICR2_ICR16_SHIFT (0U)
/*! ICR16 - Interrupt configuration field for GPIO interrupt 16
* 0b00..Interrupt 16 is low-level sensitive.
* 0b01..Interrupt 16 is high-level sensitive.
* 0b10..Interrupt 16 is rising-edge sensitive.
* 0b11..Interrupt 16 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR16(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR16_SHIFT)) & GPIO_ICR2_ICR16_MASK)
#define GPIO_ICR2_ICR17_MASK (0xCU)
#define GPIO_ICR2_ICR17_SHIFT (2U)
/*! ICR17 - Interrupt configuration field for GPIO interrupt 17
* 0b00..Interrupt 17 is low-level sensitive.
* 0b01..Interrupt 17 is high-level sensitive.
* 0b10..Interrupt 17 is rising-edge sensitive.
* 0b11..Interrupt 17 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR17(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR17_SHIFT)) & GPIO_ICR2_ICR17_MASK)
#define GPIO_ICR2_ICR18_MASK (0x30U)
#define GPIO_ICR2_ICR18_SHIFT (4U)
/*! ICR18 - Interrupt configuration field for GPIO interrupt 18
* 0b00..Interrupt 18 is low-level sensitive.
* 0b01..Interrupt 18 is high-level sensitive.
* 0b10..Interrupt 18 is rising-edge sensitive.
* 0b11..Interrupt 18 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR18(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR18_SHIFT)) & GPIO_ICR2_ICR18_MASK)
#define GPIO_ICR2_ICR19_MASK (0xC0U)
#define GPIO_ICR2_ICR19_SHIFT (6U)
/*! ICR19 - Interrupt configuration field for GPIO interrupt 19
* 0b00..Interrupt 19 is low-level sensitive.
* 0b01..Interrupt 19 is high-level sensitive.
* 0b10..Interrupt 19 is rising-edge sensitive.
* 0b11..Interrupt 19 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR19(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR19_SHIFT)) & GPIO_ICR2_ICR19_MASK)
#define GPIO_ICR2_ICR20_MASK (0x300U)
#define GPIO_ICR2_ICR20_SHIFT (8U)
/*! ICR20 - Interrupt configuration field for GPIO interrupt 20
* 0b00..Interrupt 20 is low-level sensitive.
* 0b01..Interrupt 20 is high-level sensitive.
* 0b10..Interrupt 20 is rising-edge sensitive.
* 0b11..Interrupt 20 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR20(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR20_SHIFT)) & GPIO_ICR2_ICR20_MASK)
#define GPIO_ICR2_ICR21_MASK (0xC00U)
#define GPIO_ICR2_ICR21_SHIFT (10U)
/*! ICR21 - Interrupt configuration field for GPIO interrupt 21
* 0b00..Interrupt 21 is low-level sensitive.
* 0b01..Interrupt 21 is high-level sensitive.
* 0b10..Interrupt 21 is rising-edge sensitive.
* 0b11..Interrupt 21 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR21(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR21_SHIFT)) & GPIO_ICR2_ICR21_MASK)
#define GPIO_ICR2_ICR22_MASK (0x3000U)
#define GPIO_ICR2_ICR22_SHIFT (12U)
/*! ICR22 - Interrupt configuration field for GPIO interrupt 22
* 0b00..Interrupt 22 is low-level sensitive.
* 0b01..Interrupt 22 is high-level sensitive.
* 0b10..Interrupt 22 is rising-edge sensitive.
* 0b11..Interrupt 22 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR22(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR22_SHIFT)) & GPIO_ICR2_ICR22_MASK)
#define GPIO_ICR2_ICR23_MASK (0xC000U)
#define GPIO_ICR2_ICR23_SHIFT (14U)
/*! ICR23 - Interrupt configuration field for GPIO interrupt 23
* 0b00..Interrupt 23 is low-level sensitive.
* 0b01..Interrupt 23 is high-level sensitive.
* 0b10..Interrupt 23 is rising-edge sensitive.
* 0b11..Interrupt 23 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR23(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR23_SHIFT)) & GPIO_ICR2_ICR23_MASK)
#define GPIO_ICR2_ICR24_MASK (0x30000U)
#define GPIO_ICR2_ICR24_SHIFT (16U)
/*! ICR24 - Interrupt configuration field for GPIO interrupt 24
* 0b00..Interrupt 24 is low-level sensitive.
* 0b01..Interrupt 24 is high-level sensitive.
* 0b10..Interrupt 24 is rising-edge sensitive.
* 0b11..Interrupt 24 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR24(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR24_SHIFT)) & GPIO_ICR2_ICR24_MASK)
#define GPIO_ICR2_ICR25_MASK (0xC0000U)
#define GPIO_ICR2_ICR25_SHIFT (18U)
/*! ICR25 - Interrupt configuration field for GPIO interrupt 25
* 0b00..Interrupt 25 is low-level sensitive.
* 0b01..Interrupt 25 is high-level sensitive.
* 0b10..Interrupt 25 is rising-edge sensitive.
* 0b11..Interrupt 25 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR25(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR25_SHIFT)) & GPIO_ICR2_ICR25_MASK)
#define GPIO_ICR2_ICR26_MASK (0x300000U)
#define GPIO_ICR2_ICR26_SHIFT (20U)
/*! ICR26 - Interrupt configuration field for GPIO interrupt 26
* 0b00..Interrupt 26 is low-level sensitive.
* 0b01..Interrupt 26 is high-level sensitive.
* 0b10..Interrupt 26 is rising-edge sensitive.
* 0b11..Interrupt 26 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR26(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR26_SHIFT)) & GPIO_ICR2_ICR26_MASK)
#define GPIO_ICR2_ICR27_MASK (0xC00000U)
#define GPIO_ICR2_ICR27_SHIFT (22U)
/*! ICR27 - Interrupt configuration field for GPIO interrupt 27
* 0b00..Interrupt 27 is low-level sensitive.
* 0b01..Interrupt 27 is high-level sensitive.
* 0b10..Interrupt 27 is rising-edge sensitive.
* 0b11..Interrupt 27 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR27(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR27_SHIFT)) & GPIO_ICR2_ICR27_MASK)
#define GPIO_ICR2_ICR28_MASK (0x3000000U)
#define GPIO_ICR2_ICR28_SHIFT (24U)
/*! ICR28 - Interrupt configuration field for GPIO interrupt 28
* 0b00..Interrupt 28 is low-level sensitive.
* 0b01..Interrupt 28 is high-level sensitive.
* 0b10..Interrupt 28 is rising-edge sensitive.
* 0b11..Interrupt 28 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR28(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR28_SHIFT)) & GPIO_ICR2_ICR28_MASK)
#define GPIO_ICR2_ICR29_MASK (0xC000000U)
#define GPIO_ICR2_ICR29_SHIFT (26U)
/*! ICR29 - Interrupt configuration field for GPIO interrupt 29
* 0b00..Interrupt 29 is low-level sensitive.
* 0b01..Interrupt 29 is high-level sensitive.
* 0b10..Interrupt 29 is rising-edge sensitive.
* 0b11..Interrupt 29 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR29(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR29_SHIFT)) & GPIO_ICR2_ICR29_MASK)
#define GPIO_ICR2_ICR30_MASK (0x30000000U)
#define GPIO_ICR2_ICR30_SHIFT (28U)
/*! ICR30 - Interrupt configuration field for GPIO interrupt 30
* 0b00..Interrupt 30 is low-level sensitive.
* 0b01..Interrupt 30 is high-level sensitive.
* 0b10..Interrupt 30 is rising-edge sensitive.
* 0b11..Interrupt 30 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR30(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR30_SHIFT)) & GPIO_ICR2_ICR30_MASK)
#define GPIO_ICR2_ICR31_MASK (0xC0000000U)
#define GPIO_ICR2_ICR31_SHIFT (30U)
/*! ICR31 - Interrupt configuration field for GPIO interrupt 31
* 0b00..Interrupt 31 is low-level sensitive.
* 0b01..Interrupt 31 is high-level sensitive.
* 0b10..Interrupt 31 is rising-edge sensitive.
* 0b11..Interrupt 31 is falling-edge sensitive.
*/
#define GPIO_ICR2_ICR31(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ICR2_ICR31_SHIFT)) & GPIO_ICR2_ICR31_MASK)
/*! @} */
/*! @name IMR - GPIO interrupt mask register */
/*! @{ */
#define GPIO_IMR_IMR_MASK (0xFFFFFFFFU)
#define GPIO_IMR_IMR_SHIFT (0U)
/*! IMR - Interrupt Mask bits
*/
#define GPIO_IMR_IMR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_IMR_IMR_SHIFT)) & GPIO_IMR_IMR_MASK)
/*! @} */
/*! @name ISR - GPIO interrupt status register */
/*! @{ */
#define GPIO_ISR_ISR_MASK (0xFFFFFFFFU)
#define GPIO_ISR_ISR_SHIFT (0U)
/*! ISR - Interrupt status bits
*/
#define GPIO_ISR_ISR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_ISR_ISR_SHIFT)) & GPIO_ISR_ISR_MASK)
/*! @} */
/*! @name EDGE_SEL - GPIO edge select register */
/*! @{ */
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK (0xFFFFFFFFU)
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT (0U)
/*! GPIO_EDGE_SEL - Edge select
*/
#define GPIO_EDGE_SEL_GPIO_EDGE_SEL(x) (((uint32_t)(((uint32_t)(x)) << GPIO_EDGE_SEL_GPIO_EDGE_SEL_SHIFT)) & GPIO_EDGE_SEL_GPIO_EDGE_SEL_MASK)
/*! @} */
/*! @name DR_SET - GPIO data register SET */
/*! @{ */
#define GPIO_DR_SET_DR_SET_MASK (0xFFFFFFFFU)
#define GPIO_DR_SET_DR_SET_SHIFT (0U)
/*! DR_SET - Set
*/
#define GPIO_DR_SET_DR_SET(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_SET_DR_SET_SHIFT)) & GPIO_DR_SET_DR_SET_MASK)
/*! @} */
/*! @name DR_CLEAR - GPIO data register CLEAR */
/*! @{ */
#define GPIO_DR_CLEAR_DR_CLEAR_MASK (0xFFFFFFFFU)
#define GPIO_DR_CLEAR_DR_CLEAR_SHIFT (0U)
/*! DR_CLEAR - Clear
*/
#define GPIO_DR_CLEAR_DR_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_CLEAR_DR_CLEAR_SHIFT)) & GPIO_DR_CLEAR_DR_CLEAR_MASK)
/*! @} */
/*! @name DR_TOGGLE - GPIO data register TOGGLE */
/*! @{ */
#define GPIO_DR_TOGGLE_DR_TOGGLE_MASK (0xFFFFFFFFU)
#define GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT (0U)
/*! DR_TOGGLE - Toggle
*/
#define GPIO_DR_TOGGLE_DR_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DR_TOGGLE_DR_TOGGLE_SHIFT)) & GPIO_DR_TOGGLE_DR_TOGGLE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPIO_Register_Masks */
/* GPIO - Peripheral instance base addresses */
/** Peripheral GPIO1 base address */
#define GPIO1_BASE (0x4012C000u)
/** Peripheral GPIO1 base pointer */
#define GPIO1 ((GPIO_Type *)GPIO1_BASE)
/** Peripheral GPIO2 base address */
#define GPIO2_BASE (0x40130000u)
/** Peripheral GPIO2 base pointer */
#define GPIO2 ((GPIO_Type *)GPIO2_BASE)
/** Peripheral GPIO3 base address */
#define GPIO3_BASE (0x40134000u)
/** Peripheral GPIO3 base pointer */
#define GPIO3 ((GPIO_Type *)GPIO3_BASE)
/** Peripheral GPIO4 base address */
#define GPIO4_BASE (0x40138000u)
/** Peripheral GPIO4 base pointer */
#define GPIO4 ((GPIO_Type *)GPIO4_BASE)
/** Peripheral GPIO5 base address */
#define GPIO5_BASE (0x4013C000u)
/** Peripheral GPIO5 base pointer */
#define GPIO5 ((GPIO_Type *)GPIO5_BASE)
/** Peripheral GPIO6 base address */
#define GPIO6_BASE (0x40140000u)
/** Peripheral GPIO6 base pointer */
#define GPIO6 ((GPIO_Type *)GPIO6_BASE)
/** Peripheral GPIO7 base address */
#define GPIO7_BASE (0x40C5C000u)
/** Peripheral GPIO7 base pointer */
#define GPIO7 ((GPIO_Type *)GPIO7_BASE)
/** Peripheral GPIO8 base address */
#define GPIO8_BASE (0x40C60000u)
/** Peripheral GPIO8 base pointer */
#define GPIO8 ((GPIO_Type *)GPIO8_BASE)
/** Peripheral GPIO9 base address */
#define GPIO9_BASE (0x40C64000u)
/** Peripheral GPIO9 base pointer */
#define GPIO9 ((GPIO_Type *)GPIO9_BASE)
/** Peripheral GPIO10 base address */
#define GPIO10_BASE (0x40C68000u)
/** Peripheral GPIO10 base pointer */
#define GPIO10 ((GPIO_Type *)GPIO10_BASE)
/** Peripheral GPIO11 base address */
#define GPIO11_BASE (0x40C6C000u)
/** Peripheral GPIO11 base pointer */
#define GPIO11 ((GPIO_Type *)GPIO11_BASE)
/** Peripheral GPIO12 base address */
#define GPIO12_BASE (0x40C70000u)
/** Peripheral GPIO12 base pointer */
#define GPIO12 ((GPIO_Type *)GPIO12_BASE)
/** Peripheral GPIO13 base address */
#define GPIO13_BASE (0x40CA0000u)
/** Peripheral GPIO13 base pointer */
#define GPIO13 ((GPIO_Type *)GPIO13_BASE)
/** Peripheral CM7_GPIO2 base address */
#define CM7_GPIO2_BASE (0x42008000u)
/** Peripheral CM7_GPIO2 base pointer */
#define CM7_GPIO2 ((GPIO_Type *)CM7_GPIO2_BASE)
/** Peripheral CM7_GPIO3 base address */
#define CM7_GPIO3_BASE (0x4200C000u)
/** Peripheral CM7_GPIO3 base pointer */
#define CM7_GPIO3 ((GPIO_Type *)CM7_GPIO3_BASE)
/** Array initializer of GPIO peripheral base addresses */
#define GPIO_BASE_ADDRS { 0u, GPIO1_BASE, GPIO2_BASE, GPIO3_BASE, GPIO4_BASE, GPIO5_BASE, GPIO6_BASE, GPIO7_BASE, GPIO8_BASE, GPIO9_BASE, GPIO10_BASE, GPIO11_BASE, GPIO12_BASE, GPIO13_BASE, CM7_GPIO2_BASE, CM7_GPIO3_BASE }
/** Array initializer of GPIO peripheral base pointers */
#define GPIO_BASE_PTRS { (GPIO_Type *)0u, GPIO1, GPIO2, GPIO3, GPIO4, GPIO5, GPIO6, GPIO7, GPIO8, GPIO9, GPIO10, GPIO11, GPIO12, GPIO13, CM7_GPIO2, CM7_GPIO3 }
/** Interrupt vectors for the GPIO peripheral type */
#define GPIO_COMBINED_LOW_IRQS { NotAvail_IRQn, GPIO1_Combined_0_15_IRQn, GPIO2_Combined_0_15_IRQn, GPIO3_Combined_0_15_IRQn, GPIO4_Combined_0_15_IRQn, GPIO5_Combined_0_15_IRQn, GPIO6_Combined_0_15_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, GPIO13_Combined_0_31_IRQn, CM7_GPIO2_3_IRQn, CM7_GPIO2_3_IRQn }
#define GPIO_COMBINED_HIGH_IRQS { NotAvail_IRQn, GPIO1_Combined_16_31_IRQn, GPIO2_Combined_16_31_IRQn, GPIO3_Combined_16_31_IRQn, GPIO4_Combined_16_31_IRQn, GPIO5_Combined_16_31_IRQn, GPIO6_Combined_16_31_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, GPIO13_Combined_0_31_IRQn, CM7_GPIO2_3_IRQn, CM7_GPIO2_3_IRQn }
/*!
* @}
*/ /* end of group GPIO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- GPT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPT_Peripheral_Access_Layer GPT Peripheral Access Layer
* @{
*/
/** GPT - Register Layout Typedef */
typedef struct {
__IO uint32_t CR; /**< GPT Control Register, offset: 0x0 */
__IO uint32_t PR; /**< GPT Prescaler Register, offset: 0x4 */
__IO uint32_t SR; /**< GPT Status Register, offset: 0x8 */
__IO uint32_t IR; /**< GPT Interrupt Register, offset: 0xC */
__IO uint32_t OCR[3]; /**< GPT Output Compare Register, array offset: 0x10, array step: 0x4 */
__I uint32_t ICR[2]; /**< GPT Input Capture Register, array offset: 0x1C, array step: 0x4 */
__I uint32_t CNT; /**< GPT Counter Register, offset: 0x24 */
} GPT_Type;
/* ----------------------------------------------------------------------------
-- GPT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup GPT_Register_Masks GPT Register Masks
* @{
*/
/*! @name CR - GPT Control Register */
/*! @{ */
#define GPT_CR_EN_MASK (0x1U)
#define GPT_CR_EN_SHIFT (0U)
/*! EN - GPT Enable
* 0b0..Disable
* 0b1..Enable
*/
#define GPT_CR_EN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_SHIFT)) & GPT_CR_EN_MASK)
#define GPT_CR_ENMOD_MASK (0x2U)
#define GPT_CR_ENMOD_SHIFT (1U)
/*! ENMOD - GPT Enable Mode
* 0b0..Restart counting from their frozen values after GPT is enabled (EN=1).
* 0b1..Reset counting from 0 after GPT is enabled (EN=1).
*/
#define GPT_CR_ENMOD(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_ENMOD_SHIFT)) & GPT_CR_ENMOD_MASK)
#define GPT_CR_DBGEN_MASK (0x4U)
#define GPT_CR_DBGEN_SHIFT (2U)
/*! DBGEN - GPT Debug Mode Enable
* 0b0..Disable in Debug mode
* 0b1..Enable in Debug mode
*/
#define GPT_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DBGEN_SHIFT)) & GPT_CR_DBGEN_MASK)
#define GPT_CR_WAITEN_MASK (0x8U)
#define GPT_CR_WAITEN_SHIFT (3U)
/*! WAITEN - GPT Wait Mode Enable
* 0b0..Disable in Wait mode
* 0b1..Enable in Wait mode
*/
#define GPT_CR_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_WAITEN_SHIFT)) & GPT_CR_WAITEN_MASK)
#define GPT_CR_DOZEEN_MASK (0x10U)
#define GPT_CR_DOZEEN_SHIFT (4U)
/*! DOZEEN - GPT Doze Mode Enable
* 0b0..Disable in Doze mode
* 0b1..Enable in Doze mode
*/
#define GPT_CR_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_DOZEEN_SHIFT)) & GPT_CR_DOZEEN_MASK)
#define GPT_CR_STOPEN_MASK (0x20U)
#define GPT_CR_STOPEN_SHIFT (5U)
/*! STOPEN - GPT Stop Mode Enable
* 0b0..Disable in Stop mode
* 0b1..Enable in Stop mode
*/
#define GPT_CR_STOPEN(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_STOPEN_SHIFT)) & GPT_CR_STOPEN_MASK)
#define GPT_CR_CLKSRC_MASK (0x1C0U)
#define GPT_CR_CLKSRC_SHIFT (6U)
/*! CLKSRC - Clock Source Select
* 0b000..No clock
* 0b001..Peripheral Clock (ipg_clk)
* 0b010..High Frequency Reference Clock (ipg_clk_highfreq)
* 0b011..External Clock
* 0b100..Low Frequency Reference Clock (ipg_clk_32k)
* 0b101..Oscillator as Reference Clock (ipg_clk_16M)
*/
#define GPT_CR_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_CLKSRC_SHIFT)) & GPT_CR_CLKSRC_MASK)
#define GPT_CR_FRR_MASK (0x200U)
#define GPT_CR_FRR_SHIFT (9U)
/*! FRR - Free-Run or Restart Mode
* 0b0..Restart mode. After a compare event, the counter resets to 0x0000_0000 and resumes counting.
* 0b1..Free-Run mode. After a compare event, the counter continues counting until 0xFFFF_FFFF and then rolls over to 0.
*/
#define GPT_CR_FRR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FRR_SHIFT)) & GPT_CR_FRR_MASK)
#define GPT_CR_EN_24M_MASK (0x400U)
#define GPT_CR_EN_24M_SHIFT (10U)
/*! EN_24M - Enable Oscillator Clock Input
* 0b0..Disable
* 0b1..Enable
*/
#define GPT_CR_EN_24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_EN_24M_SHIFT)) & GPT_CR_EN_24M_MASK)
#define GPT_CR_SWR_MASK (0x8000U)
#define GPT_CR_SWR_SHIFT (15U)
/*! SWR - Software Reset
* 0b0..GPT is not in software reset state
* 0b1..GPT is in software reset state
*/
#define GPT_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_SWR_SHIFT)) & GPT_CR_SWR_MASK)
#define GPT_CR_IM1_MASK (0x30000U)
#define GPT_CR_IM1_SHIFT (16U)
/*! IM1 - Input Capture Operating Mode for Channel 1
* 0b00..Capture disabled
* 0b01..Capture on rising edge only
* 0b10..Capture on falling edge only
* 0b11..Capture on both edges
*/
#define GPT_CR_IM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM1_SHIFT)) & GPT_CR_IM1_MASK)
#define GPT_CR_IM2_MASK (0xC0000U)
#define GPT_CR_IM2_SHIFT (18U)
/*! IM2 - Input Capture Operating Mode for Channel 2
* 0b00..Capture disabled
* 0b01..Capture on rising edge only
* 0b10..Capture on falling edge only
* 0b11..Capture on both edges
*/
#define GPT_CR_IM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_IM2_SHIFT)) & GPT_CR_IM2_MASK)
#define GPT_CR_OM1_MASK (0x700000U)
#define GPT_CR_OM1_SHIFT (20U)
/*! OM1 - Output Compare Operating Mode for Channel 1
* 0b000..Output disabled. No response on pin.
* 0b001..Toggle output pin
* 0b010..Clear output pin
* 0b011..Set output pin
* 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
* as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
* "Input clock" here refers to the clock selected by the CLKSRC field of this register.
*/
#define GPT_CR_OM1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM1_SHIFT)) & GPT_CR_OM1_MASK)
#define GPT_CR_OM2_MASK (0x3800000U)
#define GPT_CR_OM2_SHIFT (23U)
/*! OM2 - Output Compare Operating Mode for Channel 2
* 0b000..Output disabled. No response on pin.
* 0b001..Toggle output pin
* 0b010..Clear output pin
* 0b011..Set output pin
* 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
* as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
* "Input clock" here refers to the clock selected by the CLKSRC field of this register.
*/
#define GPT_CR_OM2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM2_SHIFT)) & GPT_CR_OM2_MASK)
#define GPT_CR_OM3_MASK (0x1C000000U)
#define GPT_CR_OM3_SHIFT (26U)
/*! OM3 - Output Compare Operating Mode for Channel 3
* 0b000..Output disabled. No response on pin.
* 0b001..Toggle output pin
* 0b010..Clear output pin
* 0b011..Set output pin
* 0b1xx..Generate a low pulse that is one input clock cycle wide on the output pin. When OMn is first programmed
* as 1xx, the output pin is set to one immediately on the next input clock (if it was not one already).
* "Input clock" here refers to the clock selected by the CLKSRC field of this register.
*/
#define GPT_CR_OM3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_OM3_SHIFT)) & GPT_CR_OM3_MASK)
#define GPT_CR_FO1_MASK (0x20000000U)
#define GPT_CR_FO1_SHIFT (29U)
/*! FO1 - Force Output Compare for Channel 1
* 0b0..No effect
* 0b1..Trigger the programmed response on the pin
*/
#define GPT_CR_FO1(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO1_SHIFT)) & GPT_CR_FO1_MASK)
#define GPT_CR_FO2_MASK (0x40000000U)
#define GPT_CR_FO2_SHIFT (30U)
/*! FO2 - Force Output Compare for Channel 2
* 0b0..No effect
* 0b1..Trigger the programmed response on the pin
*/
#define GPT_CR_FO2(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO2_SHIFT)) & GPT_CR_FO2_MASK)
#define GPT_CR_FO3_MASK (0x80000000U)
#define GPT_CR_FO3_SHIFT (31U)
/*! FO3 - Force Output Compare for Channel 3
* 0b0..No effect
* 0b1..Trigger the programmed response on the pin
*/
#define GPT_CR_FO3(x) (((uint32_t)(((uint32_t)(x)) << GPT_CR_FO3_SHIFT)) & GPT_CR_FO3_MASK)
/*! @} */
/*! @name PR - GPT Prescaler Register */
/*! @{ */
#define GPT_PR_PRESCALER_MASK (0xFFFU)
#define GPT_PR_PRESCALER_SHIFT (0U)
/*! PRESCALER - Prescaler divide value
* 0b000000000000..Divide by 1
* 0b000000000001..Divide by 2
* 0b111111111111..Divide by 4096
*/
#define GPT_PR_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER_SHIFT)) & GPT_PR_PRESCALER_MASK)
#define GPT_PR_PRESCALER24M_MASK (0xF000U)
#define GPT_PR_PRESCALER24M_SHIFT (12U)
/*! PRESCALER24M - Prescaler divide value for the oscillator clock
* 0b0000..Divide by 1
* 0b0001..Divide by 2
* 0b1111..Divide by 16
*/
#define GPT_PR_PRESCALER24M(x) (((uint32_t)(((uint32_t)(x)) << GPT_PR_PRESCALER24M_SHIFT)) & GPT_PR_PRESCALER24M_MASK)
/*! @} */
/*! @name SR - GPT Status Register */
/*! @{ */
#define GPT_SR_OF1_MASK (0x1U)
#define GPT_SR_OF1_SHIFT (0U)
/*! OF1 - Output Compare Flag for Channel 1
* 0b0..Compare event has not occurred.
* 0b1..Compare event has occurred.
*/
#define GPT_SR_OF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF1_SHIFT)) & GPT_SR_OF1_MASK)
#define GPT_SR_OF2_MASK (0x2U)
#define GPT_SR_OF2_SHIFT (1U)
/*! OF2 - Output Compare Flag for Channel 2
* 0b0..Compare event has not occurred.
* 0b1..Compare event has occurred.
*/
#define GPT_SR_OF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF2_SHIFT)) & GPT_SR_OF2_MASK)
#define GPT_SR_OF3_MASK (0x4U)
#define GPT_SR_OF3_SHIFT (2U)
/*! OF3 - Output Compare Flag for Channel 3
* 0b0..Compare event has not occurred.
* 0b1..Compare event has occurred.
*/
#define GPT_SR_OF3(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_OF3_SHIFT)) & GPT_SR_OF3_MASK)
#define GPT_SR_IF1_MASK (0x8U)
#define GPT_SR_IF1_SHIFT (3U)
/*! IF1 - Input Capture Flag for Channel 1
* 0b0..Capture event has not occurred.
* 0b1..Capture event has occurred.
*/
#define GPT_SR_IF1(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF1_SHIFT)) & GPT_SR_IF1_MASK)
#define GPT_SR_IF2_MASK (0x10U)
#define GPT_SR_IF2_SHIFT (4U)
/*! IF2 - Input Capture Flag for Channel 2
* 0b0..Capture event has not occurred.
* 0b1..Capture event has occurred.
*/
#define GPT_SR_IF2(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_IF2_SHIFT)) & GPT_SR_IF2_MASK)
#define GPT_SR_ROV_MASK (0x20U)
#define GPT_SR_ROV_SHIFT (5U)
/*! ROV - Rollover Flag
* 0b0..Rollover has not occurred.
* 0b1..Rollover has occurred.
*/
#define GPT_SR_ROV(x) (((uint32_t)(((uint32_t)(x)) << GPT_SR_ROV_SHIFT)) & GPT_SR_ROV_MASK)
/*! @} */
/*! @name IR - GPT Interrupt Register */
/*! @{ */
#define GPT_IR_OF1IE_MASK (0x1U)
#define GPT_IR_OF1IE_SHIFT (0U)
/*! OF1IE - Output Compare Flag for Channel 1 Interrupt Enable
* 0b0..Disable
* 0b1..Enable
*/
#define GPT_IR_OF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF1IE_SHIFT)) & GPT_IR_OF1IE_MASK)
#define GPT_IR_OF2IE_MASK (0x2U)
#define GPT_IR_OF2IE_SHIFT (1U)
/*! OF2IE - Output Compare Flag for Channel 2 Interrupt Enable
* 0b0..Disable
* 0b1..Enable
*/
#define GPT_IR_OF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF2IE_SHIFT)) & GPT_IR_OF2IE_MASK)
#define GPT_IR_OF3IE_MASK (0x4U)
#define GPT_IR_OF3IE_SHIFT (2U)
/*! OF3IE - Output Compare Flag for Channel 3 Interrupt Enable
* 0b0..Disable
* 0b1..Enable
*/
#define GPT_IR_OF3IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_OF3IE_SHIFT)) & GPT_IR_OF3IE_MASK)
#define GPT_IR_IF1IE_MASK (0x8U)
#define GPT_IR_IF1IE_SHIFT (3U)
/*! IF1IE - Input Capture Flag for Channel 1 Interrupt Enable
* 0b0..Disable
* 0b1..Enable
*/
#define GPT_IR_IF1IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF1IE_SHIFT)) & GPT_IR_IF1IE_MASK)
#define GPT_IR_IF2IE_MASK (0x10U)
#define GPT_IR_IF2IE_SHIFT (4U)
/*! IF2IE - Input Capture Flag for Channel 2 Interrupt Enable
* 0b0..Disable
* 0b1..Enable
*/
#define GPT_IR_IF2IE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_IF2IE_SHIFT)) & GPT_IR_IF2IE_MASK)
#define GPT_IR_ROVIE_MASK (0x20U)
#define GPT_IR_ROVIE_SHIFT (5U)
/*! ROVIE - Rollover Interrupt Enable
* 0b0..Disable
* 0b1..Enable
*/
#define GPT_IR_ROVIE(x) (((uint32_t)(((uint32_t)(x)) << GPT_IR_ROVIE_SHIFT)) & GPT_IR_ROVIE_MASK)
/*! @} */
/*! @name OCR - GPT Output Compare Register */
/*! @{ */
#define GPT_OCR_COMP_MASK (0xFFFFFFFFU)
#define GPT_OCR_COMP_SHIFT (0U)
/*! COMP - Compare Value
*/
#define GPT_OCR_COMP(x) (((uint32_t)(((uint32_t)(x)) << GPT_OCR_COMP_SHIFT)) & GPT_OCR_COMP_MASK)
/*! @} */
/* The count of GPT_OCR */
#define GPT_OCR_COUNT (3U)
/*! @name ICR - GPT Input Capture Register */
/*! @{ */
#define GPT_ICR_CAPT_MASK (0xFFFFFFFFU)
#define GPT_ICR_CAPT_SHIFT (0U)
/*! CAPT - Capture Value
*/
#define GPT_ICR_CAPT(x) (((uint32_t)(((uint32_t)(x)) << GPT_ICR_CAPT_SHIFT)) & GPT_ICR_CAPT_MASK)
/*! @} */
/* The count of GPT_ICR */
#define GPT_ICR_COUNT (2U)
/*! @name CNT - GPT Counter Register */
/*! @{ */
#define GPT_CNT_COUNT_MASK (0xFFFFFFFFU)
#define GPT_CNT_COUNT_SHIFT (0U)
/*! COUNT - Counter Value
*/
#define GPT_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << GPT_CNT_COUNT_SHIFT)) & GPT_CNT_COUNT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group GPT_Register_Masks */
/* GPT - Peripheral instance base addresses */
/** Peripheral GPT1 base address */
#define GPT1_BASE (0x400EC000u)
/** Peripheral GPT1 base pointer */
#define GPT1 ((GPT_Type *)GPT1_BASE)
/** Peripheral GPT2 base address */
#define GPT2_BASE (0x400F0000u)
/** Peripheral GPT2 base pointer */
#define GPT2 ((GPT_Type *)GPT2_BASE)
/** Peripheral GPT3 base address */
#define GPT3_BASE (0x400F4000u)
/** Peripheral GPT3 base pointer */
#define GPT3 ((GPT_Type *)GPT3_BASE)
/** Peripheral GPT4 base address */
#define GPT4_BASE (0x400F8000u)
/** Peripheral GPT4 base pointer */
#define GPT4 ((GPT_Type *)GPT4_BASE)
/** Peripheral GPT5 base address */
#define GPT5_BASE (0x400FC000u)
/** Peripheral GPT5 base pointer */
#define GPT5 ((GPT_Type *)GPT5_BASE)
/** Peripheral GPT6 base address */
#define GPT6_BASE (0x40100000u)
/** Peripheral GPT6 base pointer */
#define GPT6 ((GPT_Type *)GPT6_BASE)
/** Array initializer of GPT peripheral base addresses */
#define GPT_BASE_ADDRS { 0u, GPT1_BASE, GPT2_BASE, GPT3_BASE, GPT4_BASE, GPT5_BASE, GPT6_BASE }
/** Array initializer of GPT peripheral base pointers */
#define GPT_BASE_PTRS { (GPT_Type *)0u, GPT1, GPT2, GPT3, GPT4, GPT5, GPT6 }
/** Interrupt vectors for the GPT peripheral type */
#define GPT_IRQS { NotAvail_IRQn, GPT1_IRQn, GPT2_IRQn, GPT3_IRQn, GPT4_IRQn, GPT5_IRQn, GPT6_IRQn }
/*!
* @}
*/ /* end of group GPT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- I2S Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
* @{
*/
/** I2S - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter, offset: 0x4 */
__IO uint32_t TCSR; /**< Transmit Control, offset: 0x8 */
__IO uint32_t TCR1; /**< Transmit Configuration 1, offset: 0xC */
__IO uint32_t TCR2; /**< Transmit Configuration 2, offset: 0x10 */
__IO uint32_t TCR3; /**< Transmit Configuration 3, offset: 0x14 */
__IO uint32_t TCR4; /**< Transmit Configuration 4, offset: 0x18 */
__IO uint32_t TCR5; /**< Transmit Configuration 5, offset: 0x1C */
__O uint32_t TDR[4]; /**< Transmit Data, array offset: 0x20, array step: 0x4 */
uint8_t RESERVED_0[16];
__I uint32_t TFR[4]; /**< Transmit FIFO, array offset: 0x40, array step: 0x4 */
uint8_t RESERVED_1[16];
__IO uint32_t TMR; /**< Transmit Mask, offset: 0x60 */
uint8_t RESERVED_2[36];
__IO uint32_t RCSR; /**< Receive Control, offset: 0x88 */
__IO uint32_t RCR1; /**< Receive Configuration 1, offset: 0x8C */
__IO uint32_t RCR2; /**< Receive Configuration 2, offset: 0x90 */
__IO uint32_t RCR3; /**< Receive Configuration 3, offset: 0x94 */
__IO uint32_t RCR4; /**< Receive Configuration 4, offset: 0x98 */
__IO uint32_t RCR5; /**< Receive Configuration 5, offset: 0x9C */
__I uint32_t RDR[4]; /**< Receive Data, array offset: 0xA0, array step: 0x4 */
uint8_t RESERVED_3[16];
__I uint32_t RFR[4]; /**< Receive FIFO, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_4[16];
__IO uint32_t RMR; /**< Receive Mask, offset: 0xE0 */
} I2S_Type;
/* ----------------------------------------------------------------------------
-- I2S Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup I2S_Register_Masks I2S Register Masks
* @{
*/
/*! @name VERID - Version ID */
/*! @{ */
#define I2S_VERID_FEATURE_MASK (0xFFFFU)
#define I2S_VERID_FEATURE_SHIFT (0U)
/*! FEATURE - Feature Specification Number
* 0b0000000000000000..Standard feature set.
*/
#define I2S_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_FEATURE_SHIFT)) & I2S_VERID_FEATURE_MASK)
#define I2S_VERID_MINOR_MASK (0xFF0000U)
#define I2S_VERID_MINOR_SHIFT (16U)
/*! MINOR - Minor Version Number
*/
#define I2S_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MINOR_SHIFT)) & I2S_VERID_MINOR_MASK)
#define I2S_VERID_MAJOR_MASK (0xFF000000U)
#define I2S_VERID_MAJOR_SHIFT (24U)
/*! MAJOR - Major Version Number
*/
#define I2S_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << I2S_VERID_MAJOR_SHIFT)) & I2S_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter */
/*! @{ */
#define I2S_PARAM_DATALINE_MASK (0xFU)
#define I2S_PARAM_DATALINE_SHIFT (0U)
/*! DATALINE - Number of Datalines
*/
#define I2S_PARAM_DATALINE(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_DATALINE_SHIFT)) & I2S_PARAM_DATALINE_MASK)
#define I2S_PARAM_FIFO_MASK (0xF00U)
#define I2S_PARAM_FIFO_SHIFT (8U)
/*! FIFO - FIFO Size
*/
#define I2S_PARAM_FIFO(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FIFO_SHIFT)) & I2S_PARAM_FIFO_MASK)
#define I2S_PARAM_FRAME_MASK (0xF0000U)
#define I2S_PARAM_FRAME_SHIFT (16U)
/*! FRAME - Frame Size
*/
#define I2S_PARAM_FRAME(x) (((uint32_t)(((uint32_t)(x)) << I2S_PARAM_FRAME_SHIFT)) & I2S_PARAM_FRAME_MASK)
/*! @} */
/*! @name TCSR - Transmit Control */
/*! @{ */
#define I2S_TCSR_FRDE_MASK (0x1U)
#define I2S_TCSR_FRDE_SHIFT (0U)
/*! FRDE - FIFO Request DMA Enable
* 0b0..Disables the DMA request.
* 0b1..Enables the DMA request.
*/
#define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
#define I2S_TCSR_FWDE_MASK (0x2U)
#define I2S_TCSR_FWDE_SHIFT (1U)
/*! FWDE - FIFO Warning DMA Enable
* 0b0..Disables the DMA request.
* 0b1..Enables the DMA request.
*/
#define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
#define I2S_TCSR_FRIE_MASK (0x100U)
#define I2S_TCSR_FRIE_SHIFT (8U)
/*! FRIE - FIFO Request Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
#define I2S_TCSR_FWIE_MASK (0x200U)
#define I2S_TCSR_FWIE_SHIFT (9U)
/*! FWIE - FIFO Warning Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
#define I2S_TCSR_FEIE_MASK (0x400U)
#define I2S_TCSR_FEIE_SHIFT (10U)
/*! FEIE - FIFO Error Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
#define I2S_TCSR_SEIE_MASK (0x800U)
#define I2S_TCSR_SEIE_SHIFT (11U)
/*! SEIE - Sync Error Interrupt Enable
* 0b0..Disables interrupt.
* 0b1..Enables interrupt.
*/
#define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
#define I2S_TCSR_WSIE_MASK (0x1000U)
#define I2S_TCSR_WSIE_SHIFT (12U)
/*! WSIE - Word Start Interrupt Enable
* 0b0..Disables interrupt.
* 0b1..Enables interrupt.
*/
#define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
#define I2S_TCSR_FRF_MASK (0x10000U)
#define I2S_TCSR_FRF_SHIFT (16U)
/*! FRF - FIFO Request Flag
* 0b0..Transmit FIFO watermark has not been reached.
* 0b1..Transmit FIFO watermark has been reached.
*/
#define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
#define I2S_TCSR_FWF_MASK (0x20000U)
#define I2S_TCSR_FWF_SHIFT (17U)
/*! FWF - FIFO Warning Flag
* 0b0..No enabled transmit FIFO is empty.
* 0b1..Enabled transmit FIFO is empty.
*/
#define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
#define I2S_TCSR_FEF_MASK (0x40000U)
#define I2S_TCSR_FEF_SHIFT (18U)
/*! FEF - FIFO Error Flag
* 0b0..Transmit underrun not detected.
* 0b1..Transmit underrun detected.
*/
#define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
#define I2S_TCSR_SEF_MASK (0x80000U)
#define I2S_TCSR_SEF_SHIFT (19U)
/*! SEF - Sync Error Flag
* 0b0..Sync error not detected.
* 0b1..Frame sync error detected.
*/
#define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
#define I2S_TCSR_WSF_MASK (0x100000U)
#define I2S_TCSR_WSF_SHIFT (20U)
/*! WSF - Word Start Flag
* 0b0..Start of word not detected.
* 0b1..Start of word detected.
*/
#define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
#define I2S_TCSR_SR_MASK (0x1000000U)
#define I2S_TCSR_SR_SHIFT (24U)
/*! SR - Software Reset
* 0b0..No effect.
* 0b1..Software reset.
*/
#define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
#define I2S_TCSR_FR_MASK (0x2000000U)
#define I2S_TCSR_FR_SHIFT (25U)
/*! FR - FIFO Reset
* 0b0..No effect.
* 0b1..FIFO reset.
*/
#define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
#define I2S_TCSR_BCE_MASK (0x10000000U)
#define I2S_TCSR_BCE_SHIFT (28U)
/*! BCE - Bit Clock Enable
* 0b0..Transmit bit clock is disabled.
* 0b1..Transmit bit clock is enabled.
*/
#define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
#define I2S_TCSR_DBGE_MASK (0x20000000U)
#define I2S_TCSR_DBGE_SHIFT (29U)
/*! DBGE - Debug Enable
* 0b0..Transmitter is disabled in Debug mode, after completing the current frame.
* 0b1..Transmitter is enabled in Debug mode.
*/
#define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
#define I2S_TCSR_STOPE_MASK (0x40000000U)
#define I2S_TCSR_STOPE_SHIFT (30U)
/*! STOPE - Stop Enable
* 0b0..Transmitter disabled in Stop mode.
* 0b1..Transmitter enabled in Stop mode.
*/
#define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
#define I2S_TCSR_TE_MASK (0x80000000U)
#define I2S_TCSR_TE_SHIFT (31U)
/*! TE - Transmitter Enable
* 0b0..Transmitter is disabled.
* 0b1..Transmitter is enabled, or transmitter has been disabled and has not yet reached end of frame.
*/
#define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
/*! @} */
/*! @name TCR1 - Transmit Configuration 1 */
/*! @{ */
#define I2S_TCR1_TFW_MASK (0x1FU)
#define I2S_TCR1_TFW_SHIFT (0U)
/*! TFW - Transmit FIFO Watermark
*/
#define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
/*! @} */
/*! @name TCR2 - Transmit Configuration 2 */
/*! @{ */
#define I2S_TCR2_DIV_MASK (0xFFU)
#define I2S_TCR2_DIV_SHIFT (0U)
/*! DIV - Bit Clock Divide
*/
#define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
#define I2S_TCR2_BYP_MASK (0x800000U)
#define I2S_TCR2_BYP_SHIFT (23U)
/*! BYP - Bit Clock Bypass
* 0b0..Internal bit clock is generated from bit clock divider.
* 0b1..Internal bit clock is divide by one of the audio master clock.
*/
#define I2S_TCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BYP_SHIFT)) & I2S_TCR2_BYP_MASK)
#define I2S_TCR2_BCD_MASK (0x1000000U)
#define I2S_TCR2_BCD_SHIFT (24U)
/*! BCD - Bit Clock Direction
* 0b0..Bit clock is generated externally in Slave mode.
* 0b1..Bit clock is generated internally in Master mode.
*/
#define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
#define I2S_TCR2_BCP_MASK (0x2000000U)
#define I2S_TCR2_BCP_SHIFT (25U)
/*! BCP - Bit Clock Polarity
* 0b0..Bit clock is active high with drive outputs on rising edge and sample inputs on falling edge.
* 0b1..Bit clock is active low with drive outputs on falling edge and sample inputs on rising edge.
*/
#define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
#define I2S_TCR2_MSEL_MASK (0xC000000U)
#define I2S_TCR2_MSEL_SHIFT (26U)
/*! MSEL - MCLK Select
* 0b00..Bus Clock selected.
* 0b01..Master Clock (MCLK) 1 option selected.
* 0b10..Master Clock (MCLK) 2 option selected.
* 0b11..Master Clock (MCLK) 3 option selected.
*/
#define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
#define I2S_TCR2_BCI_MASK (0x10000000U)
#define I2S_TCR2_BCI_SHIFT (28U)
/*! BCI - Bit Clock Input
* 0b0..No effect.
* 0b1..Internal logic is clocked as if bit clock was externally generated.
*/
#define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
#define I2S_TCR2_BCS_MASK (0x20000000U)
#define I2S_TCR2_BCS_SHIFT (29U)
/*! BCS - Bit Clock Swap
* 0b0..Use the normal bit clock source.
* 0b1..Swap the bit clock source.
*/
#define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
#define I2S_TCR2_SYNC_MASK (0x40000000U)
#define I2S_TCR2_SYNC_SHIFT (30U)
/*! SYNC - Synchronous Mode
* 0b0..Asynchronous mode.
* 0b1..Synchronous with receiver.
*/
#define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
/*! @} */
/*! @name TCR3 - Transmit Configuration 3 */
/*! @{ */
#define I2S_TCR3_WDFL_MASK (0x1FU)
#define I2S_TCR3_WDFL_SHIFT (0U)
/*! WDFL - Word Flag Configuration
*/
#define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
#define I2S_TCR3_TCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define I2S_TCR3_TCE_SHIFT (16U)
/*! TCE - Transmit Channel Enable
*/
#define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define I2S_TCR3_CFR_MASK (0xF000000U)
#define I2S_TCR3_CFR_SHIFT (24U)
/*! CFR - Channel FIFO Reset
*/
#define I2S_TCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_CFR_SHIFT)) & I2S_TCR3_CFR_MASK)
/*! @} */
/*! @name TCR4 - Transmit Configuration 4 */
/*! @{ */
#define I2S_TCR4_FSD_MASK (0x1U)
#define I2S_TCR4_FSD_SHIFT (0U)
/*! FSD - Frame Sync Direction
* 0b0..Frame sync is generated externally in Slave mode.
* 0b1..Frame sync is generated internally in Master mode.
*/
#define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
#define I2S_TCR4_FSP_MASK (0x2U)
#define I2S_TCR4_FSP_SHIFT (1U)
/*! FSP - Frame Sync Polarity
* 0b0..Frame sync is active high.
* 0b1..Frame sync is active low.
*/
#define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
#define I2S_TCR4_ONDEM_MASK (0x4U)
#define I2S_TCR4_ONDEM_SHIFT (2U)
/*! ONDEM - On Demand Mode
* 0b0..Internal frame sync is generated continuously.
* 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
*/
#define I2S_TCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_ONDEM_SHIFT)) & I2S_TCR4_ONDEM_MASK)
#define I2S_TCR4_FSE_MASK (0x8U)
#define I2S_TCR4_FSE_SHIFT (3U)
/*! FSE - Frame Sync Early
* 0b0..Frame sync asserts with the first bit of the frame.
* 0b1..Frame sync asserts one bit before the first bit of the frame.
*/
#define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
#define I2S_TCR4_MF_MASK (0x10U)
#define I2S_TCR4_MF_SHIFT (4U)
/*! MF - MSB First
* 0b0..LSB is transmitted first.
* 0b1..MSB is transmitted first.
*/
#define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
#define I2S_TCR4_CHMOD_MASK (0x20U)
#define I2S_TCR4_CHMOD_SHIFT (5U)
/*! CHMOD - Channel Mode
* 0b0..TDM mode, transmit data pins are tri-stated when slots are masked or channels are disabled.
* 0b1..Output mode, transmit data pins are never tri-stated and will output zero when slots are masked or channels are disabled.
*/
#define I2S_TCR4_CHMOD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_CHMOD_SHIFT)) & I2S_TCR4_CHMOD_MASK)
#define I2S_TCR4_SYWD_MASK (0x1F00U)
#define I2S_TCR4_SYWD_SHIFT (8U)
/*! SYWD - Sync Width
*/
#define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
#define I2S_TCR4_FRSZ_MASK (0x1F0000U)
#define I2S_TCR4_FRSZ_SHIFT (16U)
/*! FRSZ - Frame size
*/
#define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
#define I2S_TCR4_FPACK_MASK (0x3000000U)
#define I2S_TCR4_FPACK_SHIFT (24U)
/*! FPACK - FIFO Packing Mode
* 0b00..FIFO packing is disabled.
* 0b01..Reserved
* 0b10..8-bit FIFO packing is enabled.
* 0b11..16-bit FIFO packing is enabled.
*/
#define I2S_TCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FPACK_SHIFT)) & I2S_TCR4_FPACK_MASK)
#define I2S_TCR4_FCOMB_MASK (0xC000000U)
#define I2S_TCR4_FCOMB_SHIFT (26U)
/*! FCOMB - FIFO Combine Mode
* 0b00..FIFO combine mode disabled.
* 0b01..FIFO combine mode enabled on FIFO reads (from transmit shift registers).
* 0b10..FIFO combine mode enabled on FIFO writes (by software).
* 0b11..FIFO combine mode enabled on FIFO reads (from transmit shift registers) and writes (by software).
*/
#define I2S_TCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCOMB_SHIFT)) & I2S_TCR4_FCOMB_MASK)
#define I2S_TCR4_FCONT_MASK (0x10000000U)
#define I2S_TCR4_FCONT_SHIFT (28U)
/*! FCONT - FIFO Continue on Error
* 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
* 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
*/
#define I2S_TCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FCONT_SHIFT)) & I2S_TCR4_FCONT_MASK)
/*! @} */
/*! @name TCR5 - Transmit Configuration 5 */
/*! @{ */
#define I2S_TCR5_FBT_MASK (0x1F00U)
#define I2S_TCR5_FBT_SHIFT (8U)
/*! FBT - First Bit Shifted
*/
#define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
#define I2S_TCR5_W0W_MASK (0x1F0000U)
#define I2S_TCR5_W0W_SHIFT (16U)
/*! W0W - Word 0 Width
*/
#define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
#define I2S_TCR5_WNW_MASK (0x1F000000U)
#define I2S_TCR5_WNW_SHIFT (24U)
/*! WNW - Word N Width
*/
#define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
/*! @} */
/*! @name TDR - Transmit Data */
/*! @{ */
#define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
#define I2S_TDR_TDR_SHIFT (0U)
/*! TDR - Transmit Data Register
*/
#define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
/*! @} */
/* The count of I2S_TDR */
#define I2S_TDR_COUNT (4U)
/*! @name TFR - Transmit FIFO */
/*! @{ */
#define I2S_TFR_RFP_MASK (0x3FU)
#define I2S_TFR_RFP_SHIFT (0U)
/*! RFP - Read FIFO Pointer
*/
#define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
#define I2S_TFR_WFP_MASK (0x3F0000U)
#define I2S_TFR_WFP_SHIFT (16U)
/*! WFP - Write FIFO Pointer
*/
#define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
#define I2S_TFR_WCP_MASK (0x80000000U)
#define I2S_TFR_WCP_SHIFT (31U)
/*! WCP - Write Channel Pointer
* 0b0..No effect.
* 0b1..FIFO combine is enabled for FIFO writes and this FIFO will be written on the next FIFO write.
*/
#define I2S_TFR_WCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WCP_SHIFT)) & I2S_TFR_WCP_MASK)
/*! @} */
/* The count of I2S_TFR */
#define I2S_TFR_COUNT (4U)
/*! @name TMR - Transmit Mask */
/*! @{ */
#define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
#define I2S_TMR_TWM_SHIFT (0U)
/*! TWM - Transmit Word Mask
* 0b00000000000000000000000000000000..Word N is enabled.
* 0b00000000000000000000000000000001..Word N is masked. The transmit data pins are tri-stated or drive zero when masked.
*/
#define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
/*! @} */
/*! @name RCSR - Receive Control */
/*! @{ */
#define I2S_RCSR_FRDE_MASK (0x1U)
#define I2S_RCSR_FRDE_SHIFT (0U)
/*! FRDE - FIFO Request DMA Enable
* 0b0..Disables the DMA request.
* 0b1..Enables the DMA request.
*/
#define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
#define I2S_RCSR_FWDE_MASK (0x2U)
#define I2S_RCSR_FWDE_SHIFT (1U)
/*! FWDE - FIFO Warning DMA Enable
* 0b0..Disables the DMA request.
* 0b1..Enables the DMA request.
*/
#define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
#define I2S_RCSR_FRIE_MASK (0x100U)
#define I2S_RCSR_FRIE_SHIFT (8U)
/*! FRIE - FIFO Request Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
#define I2S_RCSR_FWIE_MASK (0x200U)
#define I2S_RCSR_FWIE_SHIFT (9U)
/*! FWIE - FIFO Warning Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
#define I2S_RCSR_FEIE_MASK (0x400U)
#define I2S_RCSR_FEIE_SHIFT (10U)
/*! FEIE - FIFO Error Interrupt Enable
* 0b0..Disables the interrupt.
* 0b1..Enables the interrupt.
*/
#define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
#define I2S_RCSR_SEIE_MASK (0x800U)
#define I2S_RCSR_SEIE_SHIFT (11U)
/*! SEIE - Sync Error Interrupt Enable
* 0b0..Disables interrupt.
* 0b1..Enables interrupt.
*/
#define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
#define I2S_RCSR_WSIE_MASK (0x1000U)
#define I2S_RCSR_WSIE_SHIFT (12U)
/*! WSIE - Word Start Interrupt Enable
* 0b0..Disables interrupt.
* 0b1..Enables interrupt.
*/
#define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
#define I2S_RCSR_FRF_MASK (0x10000U)
#define I2S_RCSR_FRF_SHIFT (16U)
/*! FRF - FIFO Request Flag
* 0b0..Receive FIFO watermark not reached.
* 0b1..Receive FIFO watermark has been reached.
*/
#define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
#define I2S_RCSR_FWF_MASK (0x20000U)
#define I2S_RCSR_FWF_SHIFT (17U)
/*! FWF - FIFO Warning Flag
* 0b0..No enabled receive FIFO is full.
* 0b1..Enabled receive FIFO is full.
*/
#define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
#define I2S_RCSR_FEF_MASK (0x40000U)
#define I2S_RCSR_FEF_SHIFT (18U)
/*! FEF - FIFO Error Flag
* 0b0..Receive overflow not detected.
* 0b1..Receive overflow detected.
*/
#define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
#define I2S_RCSR_SEF_MASK (0x80000U)
#define I2S_RCSR_SEF_SHIFT (19U)
/*! SEF - Sync Error Flag
* 0b0..Sync error not detected.
* 0b1..Frame sync error detected.
*/
#define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
#define I2S_RCSR_WSF_MASK (0x100000U)
#define I2S_RCSR_WSF_SHIFT (20U)
/*! WSF - Word Start Flag
* 0b0..Start of word not detected.
* 0b1..Start of word detected.
*/
#define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
#define I2S_RCSR_SR_MASK (0x1000000U)
#define I2S_RCSR_SR_SHIFT (24U)
/*! SR - Software Reset
* 0b0..No effect.
* 0b1..Software reset.
*/
#define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
#define I2S_RCSR_FR_MASK (0x2000000U)
#define I2S_RCSR_FR_SHIFT (25U)
/*! FR - FIFO Reset
* 0b0..No effect.
* 0b1..FIFO reset.
*/
#define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
#define I2S_RCSR_BCE_MASK (0x10000000U)
#define I2S_RCSR_BCE_SHIFT (28U)
/*! BCE - Bit Clock Enable
* 0b0..Receive bit clock is disabled.
* 0b1..Receive bit clock is enabled.
*/
#define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
#define I2S_RCSR_DBGE_MASK (0x20000000U)
#define I2S_RCSR_DBGE_SHIFT (29U)
/*! DBGE - Debug Enable
* 0b0..Receiver is disabled in Debug mode, after completing the current frame.
* 0b1..Receiver is enabled in Debug mode.
*/
#define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
#define I2S_RCSR_STOPE_MASK (0x40000000U)
#define I2S_RCSR_STOPE_SHIFT (30U)
/*! STOPE - Stop Enable
* 0b0..Receiver disabled in Stop mode.
* 0b1..Receiver enabled in Stop mode.
*/
#define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
#define I2S_RCSR_RE_MASK (0x80000000U)
#define I2S_RCSR_RE_SHIFT (31U)
/*! RE - Receiver Enable
* 0b0..Receiver is disabled.
* 0b1..Receiver is enabled, or receiver has been disabled and has not yet reached end of frame.
*/
#define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
/*! @} */
/*! @name RCR1 - Receive Configuration 1 */
/*! @{ */
#define I2S_RCR1_RFW_MASK (0x1FU)
#define I2S_RCR1_RFW_SHIFT (0U)
/*! RFW - Receive FIFO Watermark
*/
#define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
/*! @} */
/*! @name RCR2 - Receive Configuration 2 */
/*! @{ */
#define I2S_RCR2_DIV_MASK (0xFFU)
#define I2S_RCR2_DIV_SHIFT (0U)
/*! DIV - Bit Clock Divide
*/
#define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
#define I2S_RCR2_BYP_MASK (0x800000U)
#define I2S_RCR2_BYP_SHIFT (23U)
/*! BYP - Bit Clock Bypass
* 0b0..Internal bit clock is generated from bit clock divider.
* 0b1..Internal bit clock is divide by one of the audio master clock.
*/
#define I2S_RCR2_BYP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BYP_SHIFT)) & I2S_RCR2_BYP_MASK)
#define I2S_RCR2_BCD_MASK (0x1000000U)
#define I2S_RCR2_BCD_SHIFT (24U)
/*! BCD - Bit Clock Direction
* 0b0..Bit clock is generated externally in Slave mode.
* 0b1..Bit clock is generated internally in Master mode.
*/
#define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
#define I2S_RCR2_BCP_MASK (0x2000000U)
#define I2S_RCR2_BCP_SHIFT (25U)
/*! BCP - Bit Clock Polarity
* 0b0..Bit Clock is active high with drive outputs on rising edge and sample inputs on falling edge.
* 0b1..Bit Clock is active low with drive outputs on falling edge and sample inputs on rising edge.
*/
#define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
#define I2S_RCR2_MSEL_MASK (0xC000000U)
#define I2S_RCR2_MSEL_SHIFT (26U)
/*! MSEL - MCLK Select
* 0b00..Bus Clock selected.
* 0b01..Master Clock (MCLK) 1 option selected.
* 0b10..Master Clock (MCLK) 2 option selected.
* 0b11..Master Clock (MCLK) 3 option selected.
*/
#define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
#define I2S_RCR2_BCI_MASK (0x10000000U)
#define I2S_RCR2_BCI_SHIFT (28U)
/*! BCI - Bit Clock Input
* 0b0..No effect.
* 0b1..Internal logic is clocked as if bit clock was externally generated.
*/
#define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
#define I2S_RCR2_BCS_MASK (0x20000000U)
#define I2S_RCR2_BCS_SHIFT (29U)
/*! BCS - Bit Clock Swap
* 0b0..Use the normal bit clock source.
* 0b1..Swap the bit clock source.
*/
#define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
#define I2S_RCR2_SYNC_MASK (0x40000000U)
#define I2S_RCR2_SYNC_SHIFT (30U)
/*! SYNC - Synchronous Mode
* 0b0..Asynchronous mode.
* 0b1..Synchronous with transmitter.
*/
#define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
/*! @} */
/*! @name RCR3 - Receive Configuration 3 */
/*! @{ */
#define I2S_RCR3_WDFL_MASK (0x1FU)
#define I2S_RCR3_WDFL_SHIFT (0U)
/*! WDFL - Word Flag Configuration
*/
#define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
#define I2S_RCR3_RCE_MASK (0xF0000U) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define I2S_RCR3_RCE_SHIFT (16U)
/*! RCE - Receive Channel Enable
*/
#define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK) /* Merged from fields with different position or width, of widths (1, 4), largest definition used */
#define I2S_RCR3_CFR_MASK (0xF000000U)
#define I2S_RCR3_CFR_SHIFT (24U)
/*! CFR - Channel FIFO Reset
*/
#define I2S_RCR3_CFR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_CFR_SHIFT)) & I2S_RCR3_CFR_MASK)
/*! @} */
/*! @name RCR4 - Receive Configuration 4 */
/*! @{ */
#define I2S_RCR4_FSD_MASK (0x1U)
#define I2S_RCR4_FSD_SHIFT (0U)
/*! FSD - Frame Sync Direction
* 0b0..Frame Sync is generated externally in Slave mode.
* 0b1..Frame Sync is generated internally in Master mode.
*/
#define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
#define I2S_RCR4_FSP_MASK (0x2U)
#define I2S_RCR4_FSP_SHIFT (1U)
/*! FSP - Frame Sync Polarity
* 0b0..Frame sync is active high.
* 0b1..Frame sync is active low.
*/
#define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
#define I2S_RCR4_ONDEM_MASK (0x4U)
#define I2S_RCR4_ONDEM_SHIFT (2U)
/*! ONDEM - On Demand Mode
* 0b0..Internal frame sync is generated continuously.
* 0b1..Internal frame sync is generated when the FIFO warning flag is clear.
*/
#define I2S_RCR4_ONDEM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_ONDEM_SHIFT)) & I2S_RCR4_ONDEM_MASK)
#define I2S_RCR4_FSE_MASK (0x8U)
#define I2S_RCR4_FSE_SHIFT (3U)
/*! FSE - Frame Sync Early
* 0b0..Frame sync asserts with the first bit of the frame.
* 0b1..Frame sync asserts one bit before the first bit of the frame.
*/
#define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
#define I2S_RCR4_MF_MASK (0x10U)
#define I2S_RCR4_MF_SHIFT (4U)
/*! MF - MSB First
* 0b0..LSB is received first.
* 0b1..MSB is received first.
*/
#define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
#define I2S_RCR4_SYWD_MASK (0x1F00U)
#define I2S_RCR4_SYWD_SHIFT (8U)
/*! SYWD - Sync Width
*/
#define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
#define I2S_RCR4_FRSZ_MASK (0x1F0000U)
#define I2S_RCR4_FRSZ_SHIFT (16U)
/*! FRSZ - Frame Size
*/
#define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
#define I2S_RCR4_FPACK_MASK (0x3000000U)
#define I2S_RCR4_FPACK_SHIFT (24U)
/*! FPACK - FIFO Packing Mode
* 0b00..FIFO packing is disabled
* 0b01..Reserved.
* 0b10..8-bit FIFO packing is enabled
* 0b11..16-bit FIFO packing is enabled
*/
#define I2S_RCR4_FPACK(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FPACK_SHIFT)) & I2S_RCR4_FPACK_MASK)
#define I2S_RCR4_FCOMB_MASK (0xC000000U)
#define I2S_RCR4_FCOMB_SHIFT (26U)
/*! FCOMB - FIFO Combine Mode
* 0b00..FIFO combine mode disabled.
* 0b01..FIFO combine mode enabled on FIFO writes (from receive shift registers).
* 0b10..FIFO combine mode enabled on FIFO reads (by software).
* 0b11..FIFO combine mode enabled on FIFO writes (from receive shift registers) and reads (by software).
*/
#define I2S_RCR4_FCOMB(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCOMB_SHIFT)) & I2S_RCR4_FCOMB_MASK)
#define I2S_RCR4_FCONT_MASK (0x10000000U)
#define I2S_RCR4_FCONT_SHIFT (28U)
/*! FCONT - FIFO Continue on Error
* 0b0..On FIFO error, the SAI will continue from the start of the next frame after the FIFO error flag has been cleared.
* 0b1..On FIFO error, the SAI will continue from the same word that caused the FIFO error to set after the FIFO warning flag has been cleared.
*/
#define I2S_RCR4_FCONT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FCONT_SHIFT)) & I2S_RCR4_FCONT_MASK)
/*! @} */
/*! @name RCR5 - Receive Configuration 5 */
/*! @{ */
#define I2S_RCR5_FBT_MASK (0x1F00U)
#define I2S_RCR5_FBT_SHIFT (8U)
/*! FBT - First Bit Shifted
*/
#define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
#define I2S_RCR5_W0W_MASK (0x1F0000U)
#define I2S_RCR5_W0W_SHIFT (16U)
/*! W0W - Word 0 Width
*/
#define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
#define I2S_RCR5_WNW_MASK (0x1F000000U)
#define I2S_RCR5_WNW_SHIFT (24U)
/*! WNW - Word N Width
*/
#define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
/*! @} */
/*! @name RDR - Receive Data */
/*! @{ */
#define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
#define I2S_RDR_RDR_SHIFT (0U)
/*! RDR - Receive Data Register
*/
#define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
/*! @} */
/* The count of I2S_RDR */
#define I2S_RDR_COUNT (4U)
/*! @name RFR - Receive FIFO */
/*! @{ */
#define I2S_RFR_RFP_MASK (0x3FU)
#define I2S_RFR_RFP_SHIFT (0U)
/*! RFP - Read FIFO Pointer
*/
#define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
#define I2S_RFR_RCP_MASK (0x8000U)
#define I2S_RFR_RCP_SHIFT (15U)
/*! RCP - Receive Channel Pointer
* 0b0..No effect.
* 0b1..FIFO combine is enabled for FIFO reads and this FIFO will be read on the next FIFO read.
*/
#define I2S_RFR_RCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RCP_SHIFT)) & I2S_RFR_RCP_MASK)
#define I2S_RFR_WFP_MASK (0x3F0000U)
#define I2S_RFR_WFP_SHIFT (16U)
/*! WFP - Write FIFO Pointer
*/
#define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
/*! @} */
/* The count of I2S_RFR */
#define I2S_RFR_COUNT (4U)
/*! @name RMR - Receive Mask */
/*! @{ */
#define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
#define I2S_RMR_RWM_SHIFT (0U)
/*! RWM - Receive Word Mask
* 0b00000000000000000000000000000000..Word N is enabled.
* 0b00000000000000000000000000000001..Word N is masked.
*/
#define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
/*! @} */
/*!
* @}
*/ /* end of group I2S_Register_Masks */
/* I2S - Peripheral instance base addresses */
/** Peripheral SAI1 base address */
#define SAI1_BASE (0x40404000u)
/** Peripheral SAI1 base pointer */
#define SAI1 ((I2S_Type *)SAI1_BASE)
/** Peripheral SAI2 base address */
#define SAI2_BASE (0x40408000u)
/** Peripheral SAI2 base pointer */
#define SAI2 ((I2S_Type *)SAI2_BASE)
/** Peripheral SAI3 base address */
#define SAI3_BASE (0x4040C000u)
/** Peripheral SAI3 base pointer */
#define SAI3 ((I2S_Type *)SAI3_BASE)
/** Peripheral SAI4 base address */
#define SAI4_BASE (0x40C40000u)
/** Peripheral SAI4 base pointer */
#define SAI4 ((I2S_Type *)SAI4_BASE)
/** Array initializer of I2S peripheral base addresses */
#define I2S_BASE_ADDRS { 0u, SAI1_BASE, SAI2_BASE, SAI3_BASE, SAI4_BASE }
/** Array initializer of I2S peripheral base pointers */
#define I2S_BASE_PTRS { (I2S_Type *)0u, SAI1, SAI2, SAI3, SAI4 }
/** Interrupt vectors for the I2S peripheral type */
#define I2S_RX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_RX_IRQn, SAI4_RX_IRQn }
#define I2S_TX_IRQS { NotAvail_IRQn, SAI1_IRQn, SAI2_IRQn, SAI3_TX_IRQn, SAI4_TX_IRQn }
/*!
* @}
*/ /* end of group I2S_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IEE Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IEE_Peripheral_Access_Layer IEE Peripheral Access Layer
* @{
*/
/** IEE - Register Layout Typedef */
typedef struct {
__IO uint32_t GCFG; /**< IEE Global Configuration, offset: 0x0 */
__I uint32_t STA; /**< IEE Status, offset: 0x4 */
__IO uint32_t TSTMD; /**< IEE Test Mode Register, offset: 0x8 */
__O uint32_t DPAMS; /**< AES Mask Generation Seed, offset: 0xC */
uint8_t RESERVED_0[16];
__IO uint32_t PC_S_LT; /**< Performance Counter, AES Slave Latency Threshold Value, offset: 0x20 */
__IO uint32_t PC_M_LT; /**< Performance Counter, AES Master Latency Threshold, offset: 0x24 */
uint8_t RESERVED_1[24];
__IO uint32_t PC_BLK_ENC; /**< Performance Counter, Number of AES Block Encryptions, offset: 0x40 */
__IO uint32_t PC_BLK_DEC; /**< Performance Counter, Number of AES Block Decryptions, offset: 0x44 */
uint8_t RESERVED_2[8];
__IO uint32_t PC_SR_TRANS; /**< Performance Counter, Number of AXI Slave Read Transactions, offset: 0x50 */
__IO uint32_t PC_SW_TRANS; /**< Performance Counter, Number of AXI Slave Write Transactions, offset: 0x54 */
__IO uint32_t PC_MR_TRANS; /**< Performance Counter, Number of AXI Master Read Transactions, offset: 0x58 */
__IO uint32_t PC_MW_TRANS; /**< Performance Counter, Number of AXI Master Write Transactions, offset: 0x5C */
uint8_t RESERVED_3[4];
__IO uint32_t PC_M_MBR; /**< Performance Counter, Number of AXI Master Merge Buffer Read Transactions, offset: 0x64 */
uint8_t RESERVED_4[8];
__IO uint32_t PC_SR_TBC_U; /**< Performance Counter, Upper Slave Read Transactions Byte Count, offset: 0x70 */
__IO uint32_t PC_SR_TBC_L; /**< Performance Counter, Lower Slave Read Transactions Byte Count, offset: 0x74 */
__IO uint32_t PC_SW_TBC_U; /**< Performance Counter, Upper Slave Write Transactions Byte Count, offset: 0x78 */
__IO uint32_t PC_SW_TBC_L; /**< Performance Counter, Lower Slave Write Transactions Byte Count, offset: 0x7C */
__IO uint32_t PC_MR_TBC_U; /**< Performance Counter, Upper Master Read Transactions Byte Count, offset: 0x80 */
__IO uint32_t PC_MR_TBC_L; /**< Performance Counter, Lower Master Read Transactions Byte Count, offset: 0x84 */
__IO uint32_t PC_MW_TBC_U; /**< Performance Counter, Upper Master Write Transactions Byte Count, offset: 0x88 */
__IO uint32_t PC_MW_TBC_L; /**< Performance Counter, Lower Master Write Transactions Byte Count, offset: 0x8C */
__IO uint32_t PC_SR_TLGTT; /**< Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold, offset: 0x90 */
__IO uint32_t PC_SW_TLGTT; /**< Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold, offset: 0x94 */
__IO uint32_t PC_MR_TLGTT; /**< Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold, offset: 0x98 */
__IO uint32_t PC_MW_TLGTT; /**< Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold, offset: 0x9C */
__IO uint32_t PC_SR_TLAT_U; /**< Performance Counter, Upper Slave Read Latency Count, offset: 0xA0 */
__IO uint32_t PC_SR_TLAT_L; /**< Performance Counter, Lower Slave Read Latency Count, offset: 0xA4 */
__IO uint32_t PC_SW_TLAT_U; /**< Performance Counter, Upper Slave Write Latency Count, offset: 0xA8 */
__IO uint32_t PC_SW_TLAT_L; /**< Performance Counter, Lower Slave Write Latency Count, offset: 0xAC */
__IO uint32_t PC_MR_TLAT_U; /**< Performance Counter, Upper Master Read Latency Count, offset: 0xB0 */
__IO uint32_t PC_MR_TLAT_L; /**< Performance Counter, Lower Master Read Latency Count, offset: 0xB4 */
__IO uint32_t PC_MW_TLAT_U; /**< Performance Counter, Upper Master Write Latency Count, offset: 0xB8 */
__IO uint32_t PC_MW_TLAT_L; /**< Performance Counter, Lower Master Write Latency Count, offset: 0xBC */
__IO uint32_t PC_SR_TNRT_U; /**< Performance Counter, Upper Slave Read Total Non-Responding Time, offset: 0xC0 */
__IO uint32_t PC_SR_TNRT_L; /**< Performance Counter, Lower Slave Read Total Non-Responding Time, offset: 0xC4 */
__IO uint32_t PC_SW_TNRT_U; /**< Performance Counter, Upper Slave Write Total Non-Responding Time, offset: 0xC8 */
__IO uint32_t PC_SW_TNRT_L; /**< Performance Counter, Lower Slave Write Total Non-Responding Time, offset: 0xCC */
uint8_t RESERVED_5[32];
__I uint32_t VIDR1; /**< IEE Version ID Register 1, offset: 0xF0 */
uint8_t RESERVED_6[4];
__I uint32_t AESVID; /**< IEE AES Version ID Register, offset: 0xF8 */
uint8_t RESERVED_7[4];
struct { /* offset: 0x100, array step: 0x100 */
__IO uint32_t REGATTR; /**< IEE Region 0 Attribute Register...IEE Region 7 Attribute Register., array offset: 0x100, array step: 0x100 */
uint8_t RESERVED_0[4];
__IO uint32_t REGPO; /**< IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register, array offset: 0x108, array step: 0x100 */
uint8_t RESERVED_1[52];
__O uint32_t REGKEY1[8]; /**< IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register, array offset: 0x140, array step: index*0x100, index2*0x4 */
uint8_t RESERVED_2[32];
__O uint32_t REGKEY2[8]; /**< IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register, array offset: 0x180, array step: index*0x100, index2*0x4 */
uint8_t RESERVED_3[96];
} REGX[8];
uint8_t RESERVED_8[1536];
__IO uint32_t AES_TST_DB[32]; /**< IEE AES Test Mode Data Buffer, array offset: 0xF00, array step: 0x4 */
} IEE_Type;
/* ----------------------------------------------------------------------------
-- IEE Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IEE_Register_Masks IEE Register Masks
* @{
*/
/*! @name GCFG - IEE Global Configuration */
/*! @{ */
#define IEE_GCFG_RL0_MASK (0x1U)
#define IEE_GCFG_RL0_SHIFT (0U)
/*! RL0
* 0b0..Unlocked.
* 0b1..Key, Offset and Attribute registers are locked.
*/
#define IEE_GCFG_RL0(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL0_SHIFT)) & IEE_GCFG_RL0_MASK)
#define IEE_GCFG_RL1_MASK (0x2U)
#define IEE_GCFG_RL1_SHIFT (1U)
/*! RL1
* 0b0..Unlocked.
* 0b1..Key, Offset and Attribute registers are locked.
*/
#define IEE_GCFG_RL1(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL1_SHIFT)) & IEE_GCFG_RL1_MASK)
#define IEE_GCFG_RL2_MASK (0x4U)
#define IEE_GCFG_RL2_SHIFT (2U)
/*! RL2
* 0b0..Unlocked.
* 0b1..Key, Offset and Attribute registers are locked.
*/
#define IEE_GCFG_RL2(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL2_SHIFT)) & IEE_GCFG_RL2_MASK)
#define IEE_GCFG_RL3_MASK (0x8U)
#define IEE_GCFG_RL3_SHIFT (3U)
/*! RL3
* 0b0..Unlocked.
* 0b1..Key, Offset and Attribute registers are locked.
*/
#define IEE_GCFG_RL3(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL3_SHIFT)) & IEE_GCFG_RL3_MASK)
#define IEE_GCFG_RL4_MASK (0x10U)
#define IEE_GCFG_RL4_SHIFT (4U)
/*! RL4
* 0b0..Unlocked.
* 0b1..Key, Offset and Attribute registers are locked.
*/
#define IEE_GCFG_RL4(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL4_SHIFT)) & IEE_GCFG_RL4_MASK)
#define IEE_GCFG_RL5_MASK (0x20U)
#define IEE_GCFG_RL5_SHIFT (5U)
/*! RL5
* 0b0..Unlocked.
* 0b1..Key, Offset and Attribute registers are locked.
*/
#define IEE_GCFG_RL5(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL5_SHIFT)) & IEE_GCFG_RL5_MASK)
#define IEE_GCFG_RL6_MASK (0x40U)
#define IEE_GCFG_RL6_SHIFT (6U)
/*! RL6
* 0b0..Unlocked.
* 0b1..Key, Offset and Attribute registers are locked.
*/
#define IEE_GCFG_RL6(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL6_SHIFT)) & IEE_GCFG_RL6_MASK)
#define IEE_GCFG_RL7_MASK (0x80U)
#define IEE_GCFG_RL7_SHIFT (7U)
/*! RL7
* 0b0..Unlocked.
* 0b1..Key, Offset and Attribute registers are locked.
*/
#define IEE_GCFG_RL7(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RL7_SHIFT)) & IEE_GCFG_RL7_MASK)
#define IEE_GCFG_TME_MASK (0x10000U)
#define IEE_GCFG_TME_SHIFT (16U)
/*! TME
* 0b0..Disabled.
* 0b1..Enabled.
*/
#define IEE_GCFG_TME(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TME_SHIFT)) & IEE_GCFG_TME_MASK)
#define IEE_GCFG_TMD_MASK (0x20000U)
#define IEE_GCFG_TMD_SHIFT (17U)
/*! TMD
* 0b0..Test mode is usable.
* 0b1..Test mode is disabled.
*/
#define IEE_GCFG_TMD(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_TMD_SHIFT)) & IEE_GCFG_TMD_MASK)
#define IEE_GCFG_KEY_RD_DIS_MASK (0x2000000U)
#define IEE_GCFG_KEY_RD_DIS_SHIFT (25U)
/*! KEY_RD_DIS
* 0b0..Key read enabled. Reading the key registers is allowed.
* 0b1..Key read disabled. Reading the key registers is disabled.
*/
#define IEE_GCFG_KEY_RD_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_KEY_RD_DIS_SHIFT)) & IEE_GCFG_KEY_RD_DIS_MASK)
#define IEE_GCFG_MON_EN_MASK (0x10000000U)
#define IEE_GCFG_MON_EN_SHIFT (28U)
/*! MON_EN
* 0b0..Performance monitoring disabled. Writing of the performance counter registers is enabled.
* 0b1..Performance monitoring enabled. Writing of the performance counter registers is disabled.
*/
#define IEE_GCFG_MON_EN(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_MON_EN_SHIFT)) & IEE_GCFG_MON_EN_MASK)
#define IEE_GCFG_CLR_MON_MASK (0x20000000U)
#define IEE_GCFG_CLR_MON_SHIFT (29U)
/*! CLR_MON
* 0b0..Do not reset.
* 0b1..Reset performance counters.
*/
#define IEE_GCFG_CLR_MON(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_CLR_MON_SHIFT)) & IEE_GCFG_CLR_MON_MASK)
#define IEE_GCFG_RST_MASK (0x80000000U)
#define IEE_GCFG_RST_SHIFT (31U)
/*! RST
* 0b0..Do Not Reset.
* 0b1..Reset IEE.
*/
#define IEE_GCFG_RST(x) (((uint32_t)(((uint32_t)(x)) << IEE_GCFG_RST_SHIFT)) & IEE_GCFG_RST_MASK)
/*! @} */
/*! @name STA - IEE Status */
/*! @{ */
#define IEE_STA_DSR_MASK (0x1U)
#define IEE_STA_DSR_SHIFT (0U)
/*! DSR
* 0b0..No seed request present
* 0b1..Seed request present
*/
#define IEE_STA_DSR(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_DSR_SHIFT)) & IEE_STA_DSR_MASK)
#define IEE_STA_AFD_MASK (0x10U)
#define IEE_STA_AFD_SHIFT (4U)
/*! AFD
* 0b0..No fault detected
* 0b1..Fault detected
*/
#define IEE_STA_AFD(x) (((uint32_t)(((uint32_t)(x)) << IEE_STA_AFD_SHIFT)) & IEE_STA_AFD_MASK)
/*! @} */
/*! @name TSTMD - IEE Test Mode Register */
/*! @{ */
#define IEE_TSTMD_TMRDY_MASK (0x1U)
#define IEE_TSTMD_TMRDY_SHIFT (0U)
/*! TMRDY
* 0b0..Not Ready.
* 0b1..Ready.
*/
#define IEE_TSTMD_TMRDY(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMRDY_SHIFT)) & IEE_TSTMD_TMRDY_MASK)
#define IEE_TSTMD_TMR_MASK (0x2U)
#define IEE_TSTMD_TMR_SHIFT (1U)
/*! TMR
* 0b0..Not running. May be written if IEE_GCFG[TME] = 1
* 0b1..Run AES Test until TMDONE is indicated.
*/
#define IEE_TSTMD_TMR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMR_SHIFT)) & IEE_TSTMD_TMR_MASK)
#define IEE_TSTMD_TMENCR_MASK (0x4U)
#define IEE_TSTMD_TMENCR_SHIFT (2U)
/*! TMENCR
* 0b0..AES Test mode will do decryption.
* 0b1..AES Test mode will do encryption.
*/
#define IEE_TSTMD_TMENCR(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMENCR_SHIFT)) & IEE_TSTMD_TMENCR_MASK)
#define IEE_TSTMD_TMCONT_MASK (0x8U)
#define IEE_TSTMD_TMCONT_SHIFT (3U)
/*! TMCONT
* 0b0..Do not continue. This is the last block of data for AES.
* 0b1..Continue. Do not initialize AES after this block.
*/
#define IEE_TSTMD_TMCONT(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMCONT_SHIFT)) & IEE_TSTMD_TMCONT_MASK)
#define IEE_TSTMD_TMDONE_MASK (0x10U)
#define IEE_TSTMD_TMDONE_SHIFT (4U)
/*! TMDONE
* 0b0..Not Done.
* 0b1..Test Done.
*/
#define IEE_TSTMD_TMDONE(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMDONE_SHIFT)) & IEE_TSTMD_TMDONE_MASK)
#define IEE_TSTMD_TMLEN_MASK (0xF00U)
#define IEE_TSTMD_TMLEN_SHIFT (8U)
#define IEE_TSTMD_TMLEN(x) (((uint32_t)(((uint32_t)(x)) << IEE_TSTMD_TMLEN_SHIFT)) & IEE_TSTMD_TMLEN_MASK)
/*! @} */
/*! @name DPAMS - AES Mask Generation Seed */
/*! @{ */
#define IEE_DPAMS_DPAMS_MASK (0xFFFFFFFFU)
#define IEE_DPAMS_DPAMS_SHIFT (0U)
#define IEE_DPAMS_DPAMS(x) (((uint32_t)(((uint32_t)(x)) << IEE_DPAMS_DPAMS_SHIFT)) & IEE_DPAMS_DPAMS_MASK)
/*! @} */
/*! @name PC_S_LT - Performance Counter, AES Slave Latency Threshold Value */
/*! @{ */
#define IEE_PC_S_LT_SW_LT_MASK (0xFFFFU)
#define IEE_PC_S_LT_SW_LT_SHIFT (0U)
#define IEE_PC_S_LT_SW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SW_LT_SHIFT)) & IEE_PC_S_LT_SW_LT_MASK)
#define IEE_PC_S_LT_SR_LT_MASK (0xFFFF0000U)
#define IEE_PC_S_LT_SR_LT_SHIFT (16U)
#define IEE_PC_S_LT_SR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_S_LT_SR_LT_SHIFT)) & IEE_PC_S_LT_SR_LT_MASK)
/*! @} */
/*! @name PC_M_LT - Performance Counter, AES Master Latency Threshold */
/*! @{ */
#define IEE_PC_M_LT_MW_LT_MASK (0xFFFU)
#define IEE_PC_M_LT_MW_LT_SHIFT (0U)
#define IEE_PC_M_LT_MW_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MW_LT_SHIFT)) & IEE_PC_M_LT_MW_LT_MASK)
#define IEE_PC_M_LT_MR_LT_MASK (0xFFF0000U)
#define IEE_PC_M_LT_MR_LT_SHIFT (16U)
#define IEE_PC_M_LT_MR_LT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_LT_MR_LT_SHIFT)) & IEE_PC_M_LT_MR_LT_MASK)
/*! @} */
/*! @name PC_BLK_ENC - Performance Counter, Number of AES Block Encryptions */
/*! @{ */
#define IEE_PC_BLK_ENC_BLK_ENC_MASK (0xFFFFFFFFU)
#define IEE_PC_BLK_ENC_BLK_ENC_SHIFT (0U)
#define IEE_PC_BLK_ENC_BLK_ENC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_ENC_BLK_ENC_SHIFT)) & IEE_PC_BLK_ENC_BLK_ENC_MASK)
/*! @} */
/*! @name PC_BLK_DEC - Performance Counter, Number of AES Block Decryptions */
/*! @{ */
#define IEE_PC_BLK_DEC_BLK_DEC_MASK (0xFFFFFFFFU)
#define IEE_PC_BLK_DEC_BLK_DEC_SHIFT (0U)
#define IEE_PC_BLK_DEC_BLK_DEC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_BLK_DEC_BLK_DEC_SHIFT)) & IEE_PC_BLK_DEC_BLK_DEC_MASK)
/*! @} */
/*! @name PC_SR_TRANS - Performance Counter, Number of AXI Slave Read Transactions */
/*! @{ */
#define IEE_PC_SR_TRANS_SR_TRANS_MASK (0xFFFFFFFFU)
#define IEE_PC_SR_TRANS_SR_TRANS_SHIFT (0U)
#define IEE_PC_SR_TRANS_SR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TRANS_SR_TRANS_SHIFT)) & IEE_PC_SR_TRANS_SR_TRANS_MASK)
/*! @} */
/*! @name PC_SW_TRANS - Performance Counter, Number of AXI Slave Write Transactions */
/*! @{ */
#define IEE_PC_SW_TRANS_SW_TRANS_MASK (0xFFFFFFFFU)
#define IEE_PC_SW_TRANS_SW_TRANS_SHIFT (0U)
#define IEE_PC_SW_TRANS_SW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TRANS_SW_TRANS_SHIFT)) & IEE_PC_SW_TRANS_SW_TRANS_MASK)
/*! @} */
/*! @name PC_MR_TRANS - Performance Counter, Number of AXI Master Read Transactions */
/*! @{ */
#define IEE_PC_MR_TRANS_MR_TRANS_MASK (0xFFFFFFFFU)
#define IEE_PC_MR_TRANS_MR_TRANS_SHIFT (0U)
#define IEE_PC_MR_TRANS_MR_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TRANS_MR_TRANS_SHIFT)) & IEE_PC_MR_TRANS_MR_TRANS_MASK)
/*! @} */
/*! @name PC_MW_TRANS - Performance Counter, Number of AXI Master Write Transactions */
/*! @{ */
#define IEE_PC_MW_TRANS_MW_TRANS_MASK (0xFFFFFFFFU)
#define IEE_PC_MW_TRANS_MW_TRANS_SHIFT (0U)
#define IEE_PC_MW_TRANS_MW_TRANS(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TRANS_MW_TRANS_SHIFT)) & IEE_PC_MW_TRANS_MW_TRANS_MASK)
/*! @} */
/*! @name PC_M_MBR - Performance Counter, Number of AXI Master Merge Buffer Read Transactions */
/*! @{ */
#define IEE_PC_M_MBR_M_MBR_MASK (0xFFFFFFFFU)
#define IEE_PC_M_MBR_M_MBR_SHIFT (0U)
#define IEE_PC_M_MBR_M_MBR(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_M_MBR_M_MBR_SHIFT)) & IEE_PC_M_MBR_M_MBR_MASK)
/*! @} */
/*! @name PC_SR_TBC_U - Performance Counter, Upper Slave Read Transactions Byte Count */
/*! @{ */
#define IEE_PC_SR_TBC_U_SR_TBC_MASK (0xFFFFU)
#define IEE_PC_SR_TBC_U_SR_TBC_SHIFT (0U)
#define IEE_PC_SR_TBC_U_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_U_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_U_SR_TBC_MASK)
/*! @} */
/*! @name PC_SR_TBC_L - Performance Counter, Lower Slave Read Transactions Byte Count */
/*! @{ */
#define IEE_PC_SR_TBC_L_SR_TBC_MASK (0xFFFFFFFFU)
#define IEE_PC_SR_TBC_L_SR_TBC_SHIFT (0U)
#define IEE_PC_SR_TBC_L_SR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TBC_L_SR_TBC_SHIFT)) & IEE_PC_SR_TBC_L_SR_TBC_MASK)
/*! @} */
/*! @name PC_SW_TBC_U - Performance Counter, Upper Slave Write Transactions Byte Count */
/*! @{ */
#define IEE_PC_SW_TBC_U_SW_TBC_MASK (0xFFFFU)
#define IEE_PC_SW_TBC_U_SW_TBC_SHIFT (0U)
#define IEE_PC_SW_TBC_U_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_U_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_U_SW_TBC_MASK)
/*! @} */
/*! @name PC_SW_TBC_L - Performance Counter, Lower Slave Write Transactions Byte Count */
/*! @{ */
#define IEE_PC_SW_TBC_L_SW_TBC_MASK (0xFFFFFFFFU)
#define IEE_PC_SW_TBC_L_SW_TBC_SHIFT (0U)
#define IEE_PC_SW_TBC_L_SW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TBC_L_SW_TBC_SHIFT)) & IEE_PC_SW_TBC_L_SW_TBC_MASK)
/*! @} */
/*! @name PC_MR_TBC_U - Performance Counter, Upper Master Read Transactions Byte Count */
/*! @{ */
#define IEE_PC_MR_TBC_U_MR_TBC_MASK (0xFFFFU)
#define IEE_PC_MR_TBC_U_MR_TBC_SHIFT (0U)
#define IEE_PC_MR_TBC_U_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_U_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_U_MR_TBC_MASK)
/*! @} */
/*! @name PC_MR_TBC_L - Performance Counter, Lower Master Read Transactions Byte Count */
/*! @{ */
#define IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK (0xFU)
#define IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT (0U)
#define IEE_PC_MR_TBC_L_MR_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_LSB_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_LSB_MASK)
#define IEE_PC_MR_TBC_L_MR_TBC_MASK (0xFFFFFFF0U)
#define IEE_PC_MR_TBC_L_MR_TBC_SHIFT (4U)
#define IEE_PC_MR_TBC_L_MR_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TBC_L_MR_TBC_SHIFT)) & IEE_PC_MR_TBC_L_MR_TBC_MASK)
/*! @} */
/*! @name PC_MW_TBC_U - Performance Counter, Upper Master Write Transactions Byte Count */
/*! @{ */
#define IEE_PC_MW_TBC_U_MW_TBC_MASK (0xFFFFU)
#define IEE_PC_MW_TBC_U_MW_TBC_SHIFT (0U)
#define IEE_PC_MW_TBC_U_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_U_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_U_MW_TBC_MASK)
/*! @} */
/*! @name PC_MW_TBC_L - Performance Counter, Lower Master Write Transactions Byte Count */
/*! @{ */
#define IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK (0xFU)
#define IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT (0U)
#define IEE_PC_MW_TBC_L_MW_TBC_LSB(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_LSB_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_LSB_MASK)
#define IEE_PC_MW_TBC_L_MW_TBC_MASK (0xFFFFFFF0U)
#define IEE_PC_MW_TBC_L_MW_TBC_SHIFT (4U)
#define IEE_PC_MW_TBC_L_MW_TBC(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TBC_L_MW_TBC_SHIFT)) & IEE_PC_MW_TBC_L_MW_TBC_MASK)
/*! @} */
/*! @name PC_SR_TLGTT - Performance Counter, Number of AXI Slave Read Transactions with Latency Greater than the Threshold */
/*! @{ */
#define IEE_PC_SR_TLGTT_SR_TLGTT_MASK (0xFFFFFFFFU)
#define IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT (0U)
#define IEE_PC_SR_TLGTT_SR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLGTT_SR_TLGTT_SHIFT)) & IEE_PC_SR_TLGTT_SR_TLGTT_MASK)
/*! @} */
/*! @name PC_SW_TLGTT - Performance Counter, Number of AXI Slave Write Transactions with Latency Greater than the Threshold */
/*! @{ */
#define IEE_PC_SW_TLGTT_SW_TLGTT_MASK (0xFFFFFFFFU)
#define IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT (0U)
#define IEE_PC_SW_TLGTT_SW_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLGTT_SW_TLGTT_SHIFT)) & IEE_PC_SW_TLGTT_SW_TLGTT_MASK)
/*! @} */
/*! @name PC_MR_TLGTT - Performance Counter, Number of AXI Master Read Transactions with Latency Greater than the Threshold */
/*! @{ */
#define IEE_PC_MR_TLGTT_MR_TLGTT_MASK (0xFFFFFFFFU)
#define IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT (0U)
#define IEE_PC_MR_TLGTT_MR_TLGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLGTT_MR_TLGTT_SHIFT)) & IEE_PC_MR_TLGTT_MR_TLGTT_MASK)
/*! @} */
/*! @name PC_MW_TLGTT - Performance Counter, Number of AXI Master Write Transactions with Latency Greater than the Threshold */
/*! @{ */
#define IEE_PC_MW_TLGTT_MW_TGTT_MASK (0xFFFFFFFFU)
#define IEE_PC_MW_TLGTT_MW_TGTT_SHIFT (0U)
#define IEE_PC_MW_TLGTT_MW_TGTT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLGTT_MW_TGTT_SHIFT)) & IEE_PC_MW_TLGTT_MW_TGTT_MASK)
/*! @} */
/*! @name PC_SR_TLAT_U - Performance Counter, Upper Slave Read Latency Count */
/*! @{ */
#define IEE_PC_SR_TLAT_U_SR_TLAT_MASK (0xFFFFU)
#define IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT (0U)
#define IEE_PC_SR_TLAT_U_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_U_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_U_SR_TLAT_MASK)
/*! @} */
/*! @name PC_SR_TLAT_L - Performance Counter, Lower Slave Read Latency Count */
/*! @{ */
#define IEE_PC_SR_TLAT_L_SR_TLAT_MASK (0xFFFFFFFFU)
#define IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT (0U)
#define IEE_PC_SR_TLAT_L_SR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TLAT_L_SR_TLAT_SHIFT)) & IEE_PC_SR_TLAT_L_SR_TLAT_MASK)
/*! @} */
/*! @name PC_SW_TLAT_U - Performance Counter, Upper Slave Write Latency Count */
/*! @{ */
#define IEE_PC_SW_TLAT_U_SW_TLAT_MASK (0xFFFFU)
#define IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT (0U)
#define IEE_PC_SW_TLAT_U_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_U_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_U_SW_TLAT_MASK)
/*! @} */
/*! @name PC_SW_TLAT_L - Performance Counter, Lower Slave Write Latency Count */
/*! @{ */
#define IEE_PC_SW_TLAT_L_SW_TLAT_MASK (0xFFFFFFFFU)
#define IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT (0U)
#define IEE_PC_SW_TLAT_L_SW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TLAT_L_SW_TLAT_SHIFT)) & IEE_PC_SW_TLAT_L_SW_TLAT_MASK)
/*! @} */
/*! @name PC_MR_TLAT_U - Performance Counter, Upper Master Read Latency Count */
/*! @{ */
#define IEE_PC_MR_TLAT_U_MR_TLAT_MASK (0xFFFFU)
#define IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT (0U)
#define IEE_PC_MR_TLAT_U_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_U_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_U_MR_TLAT_MASK)
/*! @} */
/*! @name PC_MR_TLAT_L - Performance Counter, Lower Master Read Latency Count */
/*! @{ */
#define IEE_PC_MR_TLAT_L_MR_TLAT_MASK (0xFFFFFFFFU)
#define IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT (0U)
#define IEE_PC_MR_TLAT_L_MR_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MR_TLAT_L_MR_TLAT_SHIFT)) & IEE_PC_MR_TLAT_L_MR_TLAT_MASK)
/*! @} */
/*! @name PC_MW_TLAT_U - Performance Counter, Upper Master Write Latency Count */
/*! @{ */
#define IEE_PC_MW_TLAT_U_MW_TLAT_MASK (0xFFFFU)
#define IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT (0U)
#define IEE_PC_MW_TLAT_U_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_U_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_U_MW_TLAT_MASK)
/*! @} */
/*! @name PC_MW_TLAT_L - Performance Counter, Lower Master Write Latency Count */
/*! @{ */
#define IEE_PC_MW_TLAT_L_MW_TLAT_MASK (0xFFFFFFFFU)
#define IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT (0U)
#define IEE_PC_MW_TLAT_L_MW_TLAT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_MW_TLAT_L_MW_TLAT_SHIFT)) & IEE_PC_MW_TLAT_L_MW_TLAT_MASK)
/*! @} */
/*! @name PC_SR_TNRT_U - Performance Counter, Upper Slave Read Total Non-Responding Time */
/*! @{ */
#define IEE_PC_SR_TNRT_U_SR_TNRT_MASK (0xFFFFU)
#define IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT (0U)
#define IEE_PC_SR_TNRT_U_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_U_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_U_SR_TNRT_MASK)
/*! @} */
/*! @name PC_SR_TNRT_L - Performance Counter, Lower Slave Read Total Non-Responding Time */
/*! @{ */
#define IEE_PC_SR_TNRT_L_SR_TNRT_MASK (0xFFFFFFFFU)
#define IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT (0U)
#define IEE_PC_SR_TNRT_L_SR_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SR_TNRT_L_SR_TNRT_SHIFT)) & IEE_PC_SR_TNRT_L_SR_TNRT_MASK)
/*! @} */
/*! @name PC_SW_TNRT_U - Performance Counter, Upper Slave Write Total Non-Responding Time */
/*! @{ */
#define IEE_PC_SW_TNRT_U_SW_TNRT_MASK (0xFFFFU)
#define IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT (0U)
#define IEE_PC_SW_TNRT_U_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_U_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_U_SW_TNRT_MASK)
/*! @} */
/*! @name PC_SW_TNRT_L - Performance Counter, Lower Slave Write Total Non-Responding Time */
/*! @{ */
#define IEE_PC_SW_TNRT_L_SW_TNRT_MASK (0xFFFFFFFFU)
#define IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT (0U)
#define IEE_PC_SW_TNRT_L_SW_TNRT(x) (((uint32_t)(((uint32_t)(x)) << IEE_PC_SW_TNRT_L_SW_TNRT_SHIFT)) & IEE_PC_SW_TNRT_L_SW_TNRT_MASK)
/*! @} */
/*! @name VIDR1 - IEE Version ID Register 1 */
/*! @{ */
#define IEE_VIDR1_MIN_REV_MASK (0xFFU)
#define IEE_VIDR1_MIN_REV_SHIFT (0U)
#define IEE_VIDR1_MIN_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MIN_REV_SHIFT)) & IEE_VIDR1_MIN_REV_MASK)
#define IEE_VIDR1_MAJ_REV_MASK (0xFF00U)
#define IEE_VIDR1_MAJ_REV_SHIFT (8U)
#define IEE_VIDR1_MAJ_REV(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_MAJ_REV_SHIFT)) & IEE_VIDR1_MAJ_REV_MASK)
#define IEE_VIDR1_IP_ID_MASK (0xFFFF0000U)
#define IEE_VIDR1_IP_ID_SHIFT (16U)
#define IEE_VIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << IEE_VIDR1_IP_ID_SHIFT)) & IEE_VIDR1_IP_ID_MASK)
/*! @} */
/*! @name AESVID - IEE AES Version ID Register */
/*! @{ */
#define IEE_AESVID_AESRN_MASK (0xFU)
#define IEE_AESVID_AESRN_SHIFT (0U)
#define IEE_AESVID_AESRN(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESRN_SHIFT)) & IEE_AESVID_AESRN_MASK)
#define IEE_AESVID_AESVID_MASK (0xF0U)
#define IEE_AESVID_AESVID_SHIFT (4U)
#define IEE_AESVID_AESVID(x) (((uint32_t)(((uint32_t)(x)) << IEE_AESVID_AESVID_SHIFT)) & IEE_AESVID_AESVID_MASK)
/*! @} */
/*! @name REGATTR - IEE Region 0 Attribute Register...IEE Region 7 Attribute Register. */
/*! @{ */
#define IEE_REGATTR_KS_MASK (0x1U)
#define IEE_REGATTR_KS_SHIFT (0U)
/*! KS
* 0b0..128 bits (CTR), 256 bits (XTS).
* 0b1..256 bits (CTR), 512 bits (XTS).
*/
#define IEE_REGATTR_KS(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_KS_SHIFT)) & IEE_REGATTR_KS_MASK)
#define IEE_REGATTR_MD_MASK (0x70U)
#define IEE_REGATTR_MD_SHIFT (4U)
/*! MD
* 0b000..None (AXI error if accessed)
* 0b001..XTS
* 0b010..CTR w/ address binding
* 0b011..CTR w/o address binding
* 0b100..CTR keystream only
* 0b101..Undefined, AXI error if used
* 0b110..Undefined, AXI error if used
* 0b111..Undefined, AXI error if used
*/
#define IEE_REGATTR_MD(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_MD_SHIFT)) & IEE_REGATTR_MD_MASK)
#define IEE_REGATTR_BYP_MASK (0x80U)
#define IEE_REGATTR_BYP_SHIFT (7U)
/*! BYP
* 0b0..use MD field
* 0b1..Bypass AES, no encrypt/decrypt
*/
#define IEE_REGATTR_BYP(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGATTR_BYP_SHIFT)) & IEE_REGATTR_BYP_MASK)
/*! @} */
/* The count of IEE_REGATTR */
#define IEE_REGATTR_COUNT (8U)
/*! @name REGPO - IEE Region 0 Page Offset Register..IEE Region 7 Page Offset Register */
/*! @{ */
#define IEE_REGPO_PGOFF_MASK (0xFFFFFFU)
#define IEE_REGPO_PGOFF_SHIFT (0U)
#define IEE_REGPO_PGOFF(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGPO_PGOFF_SHIFT)) & IEE_REGPO_PGOFF_MASK)
/*! @} */
/* The count of IEE_REGPO */
#define IEE_REGPO_COUNT (8U)
/*! @name REGKEY1 - IEE Region 0 Key 1 Register..IEE Region 7 Key 1 Register */
/*! @{ */
#define IEE_REGKEY1_KEY1_MASK (0xFFFFFFFFU)
#define IEE_REGKEY1_KEY1_SHIFT (0U)
#define IEE_REGKEY1_KEY1(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY1_KEY1_SHIFT)) & IEE_REGKEY1_KEY1_MASK)
/*! @} */
/* The count of IEE_REGKEY1 */
#define IEE_REGKEY1_COUNT (8U)
/* The count of IEE_REGKEY1 */
#define IEE_REGKEY1_COUNT2 (8U)
/*! @name REGKEY2 - IEE Region 0 Key 2 Register..IEE Region 7 Key 2 Register */
/*! @{ */
#define IEE_REGKEY2_KEY2_MASK (0xFFFFFFFFU)
#define IEE_REGKEY2_KEY2_SHIFT (0U)
#define IEE_REGKEY2_KEY2(x) (((uint32_t)(((uint32_t)(x)) << IEE_REGKEY2_KEY2_SHIFT)) & IEE_REGKEY2_KEY2_MASK)
/*! @} */
/* The count of IEE_REGKEY2 */
#define IEE_REGKEY2_COUNT (8U)
/* The count of IEE_REGKEY2 */
#define IEE_REGKEY2_COUNT2 (8U)
/*! @name AES_TST_DB - IEE AES Test Mode Data Buffer */
/*! @{ */
#define IEE_AES_TST_DB_AES_TST_DB0_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB0_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB0(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB0_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB0_MASK)
#define IEE_AES_TST_DB_AES_TST_DB1_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB1_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB1(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB1_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB1_MASK)
#define IEE_AES_TST_DB_AES_TST_DB2_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB2_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB2(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB2_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB2_MASK)
#define IEE_AES_TST_DB_AES_TST_DB3_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB3_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB3(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB3_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB3_MASK)
#define IEE_AES_TST_DB_AES_TST_DB4_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB4_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB4(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB4_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB4_MASK)
#define IEE_AES_TST_DB_AES_TST_DB5_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB5_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB5(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB5_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB5_MASK)
#define IEE_AES_TST_DB_AES_TST_DB6_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB6_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB6(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB6_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB6_MASK)
#define IEE_AES_TST_DB_AES_TST_DB7_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB7_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB7(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB7_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB7_MASK)
#define IEE_AES_TST_DB_AES_TST_DB8_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB8_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB8(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB8_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB8_MASK)
#define IEE_AES_TST_DB_AES_TST_DB9_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB9_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB9(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB9_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB9_MASK)
#define IEE_AES_TST_DB_AES_TST_DB10_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB10_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB10(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB10_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB10_MASK)
#define IEE_AES_TST_DB_AES_TST_DB11_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB11_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB11(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB11_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB11_MASK)
#define IEE_AES_TST_DB_AES_TST_DB12_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB12_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB12(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB12_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB12_MASK)
#define IEE_AES_TST_DB_AES_TST_DB13_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB13_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB13(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB13_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB13_MASK)
#define IEE_AES_TST_DB_AES_TST_DB14_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB14_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB14(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB14_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB14_MASK)
#define IEE_AES_TST_DB_AES_TST_DB15_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB15_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB15(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB15_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB15_MASK)
#define IEE_AES_TST_DB_AES_TST_DB16_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB16_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB16(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB16_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB16_MASK)
#define IEE_AES_TST_DB_AES_TST_DB17_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB17_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB17(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB17_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB17_MASK)
#define IEE_AES_TST_DB_AES_TST_DB18_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB18_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB18(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB18_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB18_MASK)
#define IEE_AES_TST_DB_AES_TST_DB19_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB19_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB19(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB19_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB19_MASK)
#define IEE_AES_TST_DB_AES_TST_DB20_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB20_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB20(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB20_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB20_MASK)
#define IEE_AES_TST_DB_AES_TST_DB21_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB21_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB21(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB21_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB21_MASK)
#define IEE_AES_TST_DB_AES_TST_DB22_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB22_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB22(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB22_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB22_MASK)
#define IEE_AES_TST_DB_AES_TST_DB23_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB23_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB23(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB23_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB23_MASK)
#define IEE_AES_TST_DB_AES_TST_DB24_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB24_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB24(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB24_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB24_MASK)
#define IEE_AES_TST_DB_AES_TST_DB25_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB25_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB25(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB25_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB25_MASK)
#define IEE_AES_TST_DB_AES_TST_DB26_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB26_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB26(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB26_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB26_MASK)
#define IEE_AES_TST_DB_AES_TST_DB27_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB27_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB27(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB27_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB27_MASK)
#define IEE_AES_TST_DB_AES_TST_DB28_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB28_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB28(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB28_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB28_MASK)
#define IEE_AES_TST_DB_AES_TST_DB29_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB29_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB29(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB29_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB29_MASK)
#define IEE_AES_TST_DB_AES_TST_DB30_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB30_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB30(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB30_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB30_MASK)
#define IEE_AES_TST_DB_AES_TST_DB31_MASK (0xFFFFFFFFU)
#define IEE_AES_TST_DB_AES_TST_DB31_SHIFT (0U)
#define IEE_AES_TST_DB_AES_TST_DB31(x) (((uint32_t)(((uint32_t)(x)) << IEE_AES_TST_DB_AES_TST_DB31_SHIFT)) & IEE_AES_TST_DB_AES_TST_DB31_MASK)
/*! @} */
/* The count of IEE_AES_TST_DB */
#define IEE_AES_TST_DB_COUNT (32U)
/*!
* @}
*/ /* end of group IEE_Register_Masks */
/* IEE - Peripheral instance base addresses */
/** Peripheral IEE__IEE_RT1170 base address */
#define IEE__IEE_RT1170_BASE (0x4006C000u)
/** Peripheral IEE__IEE_RT1170 base pointer */
#define IEE__IEE_RT1170 ((IEE_Type *)IEE__IEE_RT1170_BASE)
/** Array initializer of IEE peripheral base addresses */
#define IEE_BASE_ADDRS { IEE__IEE_RT1170_BASE }
/** Array initializer of IEE peripheral base pointers */
#define IEE_BASE_PTRS { IEE__IEE_RT1170 }
/*!
* @}
*/ /* end of group IEE_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IEE_APC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IEE_APC_Peripheral_Access_Layer IEE_APC Peripheral Access Layer
* @{
*/
/** IEE_APC - Register Layout Typedef */
typedef struct {
__IO uint32_t REGION0_TOP_ADDR; /**< End address of IEE region (n), offset: 0x0 */
__IO uint32_t REGION0_BOT_ADDR; /**< Start address of IEE region (n), offset: 0x4 */
__IO uint32_t REGION0_RDC_D0; /**< Region control of core domain 0 for region (n), offset: 0x8 */
__IO uint32_t REGION0_RDC_D1; /**< Region control of core domain 1 for region (n), offset: 0xC */
__IO uint32_t REGION1_TOP_ADDR; /**< End address of IEE region (n), offset: 0x10 */
__IO uint32_t REGION1_BOT_ADDR; /**< Start address of IEE region (n), offset: 0x14 */
__IO uint32_t REGION1_RDC_D0; /**< Region control of core domain 0 for region (n), offset: 0x18 */
__IO uint32_t REGION1_RDC_D1; /**< Region control of core domain 1 for region (n), offset: 0x1C */
__IO uint32_t REGION2_TOP_ADDR; /**< End address of IEE region (n), offset: 0x20 */
__IO uint32_t REGION2_BOT_ADDR; /**< Start address of IEE region (n), offset: 0x24 */
__IO uint32_t REGION2_RDC_D0; /**< Region control of core domain 0 for region (n), offset: 0x28 */
__IO uint32_t REGION2_RDC_D1; /**< Region control of core domain 1 for region (n), offset: 0x2C */
__IO uint32_t REGION3_TOP_ADDR; /**< End address of IEE region (n), offset: 0x30 */
__IO uint32_t REGION3_BOT_ADDR; /**< Start address of IEE region (n), offset: 0x34 */
__IO uint32_t REGION3_RDC_D0; /**< Region control of core domain 0 for region (n), offset: 0x38 */
__IO uint32_t REGION3_RDC_D1; /**< Region control of core domain 1 for region (n), offset: 0x3C */
__IO uint32_t REGION4_TOP_ADDR; /**< End address of IEE region (n), offset: 0x40 */
__IO uint32_t REGION4_BOT_ADDR; /**< Start address of IEE region (n), offset: 0x44 */
__IO uint32_t REGION4_RDC_D0; /**< Region control of core domain 0 for region (n), offset: 0x48 */
__IO uint32_t REGION4_RDC_D1; /**< Region control of core domain 1 for region (n), offset: 0x4C */
__IO uint32_t REGION5_TOP_ADDR; /**< End address of IEE region (n), offset: 0x50 */
__IO uint32_t REGION5_BOT_ADDR; /**< Start address of IEE region (n), offset: 0x54 */
__IO uint32_t REGION5_RDC_D0; /**< Region control of core domain 0 for region (n), offset: 0x58 */
__IO uint32_t REGION5_RDC_D1; /**< Region control of core domain 1 for region (n), offset: 0x5C */
__IO uint32_t REGION6_TOP_ADDR; /**< End address of IEE region (n), offset: 0x60 */
__IO uint32_t REGION6_BOT_ADDR; /**< Start address of IEE region (n), offset: 0x64 */
__IO uint32_t REGION6_RDC_D0; /**< Region control of core domain 0 for region (n), offset: 0x68 */
__IO uint32_t REGION6_RDC_D1; /**< Region control of core domain 1 for region (n), offset: 0x6C */
__IO uint32_t REGION7_TOP_ADDR; /**< End address of IEE region (n), offset: 0x70 */
__IO uint32_t REGION7_BOT_ADDR; /**< Start address of IEE region (n), offset: 0x74 */
__IO uint32_t REGION7_RDC_D0; /**< Region control of core domain 0 for region (n), offset: 0x78 */
__IO uint32_t REGION7_RDC_D1; /**< Region control of core domain 1 for region (n), offset: 0x7C */
} IEE_APC_Type;
/* ----------------------------------------------------------------------------
-- IEE_APC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IEE_APC_Register_Masks IEE_APC Register Masks
* @{
*/
/*! @name REGION0_TOP_ADDR - End address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT (0U)
/*! TOP_ADDR - End address of IEE region
*/
#define IEE_APC_REGION0_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION0_TOP_ADDR_TOP_ADDR_MASK)
/*! @} */
/*! @name REGION0_BOT_ADDR - Start address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT (0U)
/*! BOT_ADDR - Start address of IEE region
*/
#define IEE_APC_REGION0_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION0_BOT_ADDR_BOT_ADDR_MASK)
/*! @} */
/*! @name REGION0_RDC_D0 - Region control of core domain 0 for region (n) */
/*! @{ */
#define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
/*! RDC_D0_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_WRITE_DIS_MASK)
#define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
#define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
/*! RDC_D0_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D0_RDC_D0_LOCK_MASK)
/*! @} */
/*! @name REGION0_RDC_D1 - Region control of core domain 1 for region (n) */
/*! @{ */
#define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
/*! RDC_D1_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_WRITE_DIS_MASK)
#define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
#define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
/*! RDC_D1_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION0_RDC_D1_RDC_D1_LOCK_MASK)
/*! @} */
/*! @name REGION1_TOP_ADDR - End address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT (0U)
/*! TOP_ADDR - End address of IEE region
*/
#define IEE_APC_REGION1_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION1_TOP_ADDR_TOP_ADDR_MASK)
/*! @} */
/*! @name REGION1_BOT_ADDR - Start address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT (0U)
/*! BOT_ADDR - Start address of IEE region
*/
#define IEE_APC_REGION1_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION1_BOT_ADDR_BOT_ADDR_MASK)
/*! @} */
/*! @name REGION1_RDC_D0 - Region control of core domain 0 for region (n) */
/*! @{ */
#define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
/*! RDC_D0_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_WRITE_DIS_MASK)
#define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
#define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
/*! RDC_D0_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D0_RDC_D0_LOCK_MASK)
/*! @} */
/*! @name REGION1_RDC_D1 - Region control of core domain 1 for region (n) */
/*! @{ */
#define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
/*! RDC_D1_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_WRITE_DIS_MASK)
#define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
#define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
/*! RDC_D1_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION1_RDC_D1_RDC_D1_LOCK_MASK)
/*! @} */
/*! @name REGION2_TOP_ADDR - End address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT (0U)
/*! TOP_ADDR - End address of IEE region
*/
#define IEE_APC_REGION2_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION2_TOP_ADDR_TOP_ADDR_MASK)
/*! @} */
/*! @name REGION2_BOT_ADDR - Start address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT (0U)
/*! BOT_ADDR - Start address of IEE region
*/
#define IEE_APC_REGION2_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION2_BOT_ADDR_BOT_ADDR_MASK)
/*! @} */
/*! @name REGION2_RDC_D0 - Region control of core domain 0 for region (n) */
/*! @{ */
#define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
/*! RDC_D0_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_WRITE_DIS_MASK)
#define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
#define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
/*! RDC_D0_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D0_RDC_D0_LOCK_MASK)
/*! @} */
/*! @name REGION2_RDC_D1 - Region control of core domain 1 for region (n) */
/*! @{ */
#define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
/*! RDC_D1_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_WRITE_DIS_MASK)
#define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
#define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
/*! RDC_D1_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION2_RDC_D1_RDC_D1_LOCK_MASK)
/*! @} */
/*! @name REGION3_TOP_ADDR - End address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT (0U)
/*! TOP_ADDR - End address of IEE region
*/
#define IEE_APC_REGION3_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION3_TOP_ADDR_TOP_ADDR_MASK)
/*! @} */
/*! @name REGION3_BOT_ADDR - Start address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT (0U)
/*! BOT_ADDR - Start address of IEE region
*/
#define IEE_APC_REGION3_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION3_BOT_ADDR_BOT_ADDR_MASK)
/*! @} */
/*! @name REGION3_RDC_D0 - Region control of core domain 0 for region (n) */
/*! @{ */
#define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
/*! RDC_D0_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_WRITE_DIS_MASK)
#define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
#define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
/*! RDC_D0_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D0_RDC_D0_LOCK_MASK)
/*! @} */
/*! @name REGION3_RDC_D1 - Region control of core domain 1 for region (n) */
/*! @{ */
#define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
/*! RDC_D1_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_WRITE_DIS_MASK)
#define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
#define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
/*! RDC_D1_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION3_RDC_D1_RDC_D1_LOCK_MASK)
/*! @} */
/*! @name REGION4_TOP_ADDR - End address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT (0U)
/*! TOP_ADDR - End address of IEE region
*/
#define IEE_APC_REGION4_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION4_TOP_ADDR_TOP_ADDR_MASK)
/*! @} */
/*! @name REGION4_BOT_ADDR - Start address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT (0U)
/*! BOT_ADDR - Start address of IEE region
*/
#define IEE_APC_REGION4_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION4_BOT_ADDR_BOT_ADDR_MASK)
/*! @} */
/*! @name REGION4_RDC_D0 - Region control of core domain 0 for region (n) */
/*! @{ */
#define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
/*! RDC_D0_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_WRITE_DIS_MASK)
#define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
#define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
/*! RDC_D0_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D0_RDC_D0_LOCK_MASK)
/*! @} */
/*! @name REGION4_RDC_D1 - Region control of core domain 1 for region (n) */
/*! @{ */
#define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
/*! RDC_D1_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_WRITE_DIS_MASK)
#define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
#define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
/*! RDC_D1_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION4_RDC_D1_RDC_D1_LOCK_MASK)
/*! @} */
/*! @name REGION5_TOP_ADDR - End address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT (0U)
/*! TOP_ADDR - End address of IEE region
*/
#define IEE_APC_REGION5_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION5_TOP_ADDR_TOP_ADDR_MASK)
/*! @} */
/*! @name REGION5_BOT_ADDR - Start address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT (0U)
/*! BOT_ADDR - Start address of IEE region
*/
#define IEE_APC_REGION5_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION5_BOT_ADDR_BOT_ADDR_MASK)
/*! @} */
/*! @name REGION5_RDC_D0 - Region control of core domain 0 for region (n) */
/*! @{ */
#define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
/*! RDC_D0_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_WRITE_DIS_MASK)
#define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
#define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
/*! RDC_D0_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D0_RDC_D0_LOCK_MASK)
/*! @} */
/*! @name REGION5_RDC_D1 - Region control of core domain 1 for region (n) */
/*! @{ */
#define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
/*! RDC_D1_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_WRITE_DIS_MASK)
#define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
#define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
/*! RDC_D1_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION5_RDC_D1_RDC_D1_LOCK_MASK)
/*! @} */
/*! @name REGION6_TOP_ADDR - End address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT (0U)
/*! TOP_ADDR - End address of IEE region
*/
#define IEE_APC_REGION6_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION6_TOP_ADDR_TOP_ADDR_MASK)
/*! @} */
/*! @name REGION6_BOT_ADDR - Start address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT (0U)
/*! BOT_ADDR - Start address of IEE region
*/
#define IEE_APC_REGION6_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION6_BOT_ADDR_BOT_ADDR_MASK)
/*! @} */
/*! @name REGION6_RDC_D0 - Region control of core domain 0 for region (n) */
/*! @{ */
#define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
/*! RDC_D0_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_WRITE_DIS_MASK)
#define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
#define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
/*! RDC_D0_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D0_RDC_D0_LOCK_MASK)
/*! @} */
/*! @name REGION6_RDC_D1 - Region control of core domain 1 for region (n) */
/*! @{ */
#define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
/*! RDC_D1_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_WRITE_DIS_MASK)
#define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
#define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
/*! RDC_D1_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION6_RDC_D1_RDC_D1_LOCK_MASK)
/*! @} */
/*! @name REGION7_TOP_ADDR - End address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT (0U)
/*! TOP_ADDR - End address of IEE region
*/
#define IEE_APC_REGION7_TOP_ADDR_TOP_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_SHIFT)) & IEE_APC_REGION7_TOP_ADDR_TOP_ADDR_MASK)
/*! @} */
/*! @name REGION7_BOT_ADDR - Start address of IEE region (n) */
/*! @{ */
#define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK (0x1FFFFFFFU)
#define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT (0U)
/*! BOT_ADDR - Start address of IEE region
*/
#define IEE_APC_REGION7_BOT_ADDR_BOT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_SHIFT)) & IEE_APC_REGION7_BOT_ADDR_BOT_ADDR_MASK)
/*! @} */
/*! @name REGION7_RDC_D0 - Region control of core domain 0 for region (n) */
/*! @{ */
#define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT (0U)
/*! RDC_D0_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_WRITE_DIS_MASK)
#define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK (0x2U)
#define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT (1U)
/*! RDC_D0_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D0_RDC_D0_LOCK_MASK)
/*! @} */
/*! @name REGION7_RDC_D1 - Region control of core domain 1 for region (n) */
/*! @{ */
#define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK (0x1U)
#define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT (0U)
/*! RDC_D1_WRITE_DIS - Write disable of core domain 1
* 0b0..Write to TOP_ADDR and BOT_ADDR of this region enabled
* 0b1..Write to TOP_ADDR and BOT_ADDR of this region disabled
*/
#define IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_WRITE_DIS_MASK)
#define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK (0x2U)
#define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT (1U)
/*! RDC_D1_LOCK - Lock bit for bit 0
* 0b0..Bit 0 is unlocked
* 0b1..Bit 0 is locked
*/
#define IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_SHIFT)) & IEE_APC_REGION7_RDC_D1_RDC_D1_LOCK_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IEE_APC_Register_Masks */
/* IEE_APC - Peripheral instance base addresses */
/** Peripheral IEE_APC base address */
#define IEE_APC_BASE (0x40068000u)
/** Peripheral IEE_APC base pointer */
#define IEE_APC ((IEE_APC_Type *)IEE_APC_BASE)
/** Array initializer of IEE_APC peripheral base addresses */
#define IEE_APC_BASE_ADDRS { IEE_APC_BASE }
/** Array initializer of IEE_APC peripheral base pointers */
#define IEE_APC_BASE_PTRS { IEE_APC }
/*!
* @}
*/ /* end of group IEE_APC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_Peripheral_Access_Layer IOMUXC Peripheral Access Layer
* @{
*/
/** IOMUXC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[16];
__IO uint32_t SW_MUX_CTL_PAD[145]; /**< SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register, array offset: 0x10, array step: 0x4 */
__IO uint32_t SW_PAD_CTL_PAD[145]; /**< SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register, array offset: 0x254, array step: 0x4 */
__IO uint32_t SELECT_INPUT[160]; /**< FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register, array offset: 0x498, array step: 0x4 */
} IOMUXC_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_Register_Masks IOMUXC Register Masks
* @{
*/
/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_EMC_B1_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_DISP_B2_15 SW MUX Control Register */
/*! @{ */
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU)
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b0000..Select mux mode: ALT0 mux port: SEMC_DATA16 of instance: SEMC
* 0b0001..Select mux mode: ALT1 mux port: CCM_ENET_REF_CLK_25M of instance: CCM
* 0b0010..Select mux mode: ALT2 mux port: TMR3_TIMER1 of instance: TMR3
* 0b0011..Select mux mode: ALT3 mux port: LPUART6_CTS_B of instance: LPUART6
* 0b0100..Select mux mode: ALT4 mux port: FLEXSPI2_B_DATA06 of instance: FLEXSPI2
* 0b0101..Select mux mode: ALT5 mux port: GPIO_MUX2_IO10 of instance: GPIO_MUX2
* 0b0110..Select mux mode: ALT6 mux port: XBAR1_INOUT20 of instance: XBAR1
* 0b0111..Select mux mode: ALT7 mux port: ENET_QOS_1588_EVENT1_OUT of instance: ENET_QOS
* 0b1000..Select mux mode: ALT8 mux port: LPSPI1_SCK of instance: LPSPI1
* 0b1001..Select mux mode: ALT9 mux port: LPI2C2_SCL of instance: LPI2C2
* 0b1010..Select mux mode: ALT10 mux port: GPIO8_IO10 of instance: GPIO8
* 0b1011..Select mux mode: ALT11 mux port: FLEXPWM3_PWM0_A of instance: FLEXPWM3
*/
#define IOMUXC_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_MUX_MODE_MASK)
#define IOMUXC_SW_MUX_CTL_PAD_SION_MASK (0x10U)
#define IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_DISP_B1_00
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_SW_MUX_CTL_PAD_SION_MASK)
/*! @} */
/* The count of IOMUXC_SW_MUX_CTL_PAD */
#define IOMUXC_SW_MUX_CTL_PAD_COUNT (145U)
/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_EMC_B1_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_DISP_B2_15 SW PAD Control Register */
/*! @{ */
#define IOMUXC_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
#define IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_SRE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_MASK (0x2U)
#define IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal drive strength
* 0b1..high drive strength
*/
#define IOMUXC_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DSE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK (0x2U)
#define IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT (1U)
/*! PDRV - PDRV Field
* 0b0..high drive strength
* 0b1..normal drive strength
*/
#define IOMUXC_SW_PAD_CTL_PAD_PDRV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PDRV_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PDRV_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_PUE_MASK (0x4U)
#define IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable, Highz
* 0b1..Pull Enable
*/
#define IOMUXC_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_PULL_MASK (0xCU)
#define IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT (2U)
/*! PULL - Pull Down Pull Up Field
* 0b00..Forbidden
* 0b01..Internal pullup resistor enabled
* 0b10..Internal pulldown resistor enabled
* 0b11..No Pull
*/
#define IOMUXC_SW_PAD_CTL_PAD_PULL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PULL_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PULL_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_PUS_MASK (0x8U)
#define IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_PUS_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_ODE_MASK (0x10U)
#define IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT (4U)
/*! ODE - Open Drain Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SW_PAD_CTL_PAD_ODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_ODE_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_ODE_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_DWP_MASK (0x30000000U)
#define IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SW_PAD_CTL_PAD_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_MASK)
#define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
/*! @} */
/* The count of IOMUXC_SW_PAD_CTL_PAD */
#define IOMUXC_SW_PAD_CTL_PAD_COUNT (145U)
/*! @name SELECT_INPUT - FLEXCAN1_RX_SELECT_INPUT DAISY Register..XBAR1_IN_SELECT_INPUT_35 DAISY Register */
/*! @{ */
#define IOMUXC_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
#define IOMUXC_SELECT_INPUT_DAISY_SHIFT (0U)
/*! DAISY - Selecting Pads Involved in Daisy Chain.
* 0b00..Selecting Pad: GPIO_EMC_B2_19 for Mode: ALT3
* 0b01..Selecting Pad: GPIO_SD_B2_11 for Mode: ALT3
* 0b10..Selecting Pad: GPIO_DISP_B1_11 for Mode: ALT2
* 0b11..Selecting Pad: GPIO_DISP_B2_14 for Mode: ALT4
*/
#define IOMUXC_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
/*! @} */
/* The count of IOMUXC_SELECT_INPUT */
#define IOMUXC_SELECT_INPUT_COUNT (160U)
/*!
* @}
*/ /* end of group IOMUXC_Register_Masks */
/* IOMUXC - Peripheral instance base addresses */
/** Peripheral IOMUXC base address */
#define IOMUXC_BASE (0x400E8000u)
/** Peripheral IOMUXC base pointer */
#define IOMUXC ((IOMUXC_Type *)IOMUXC_BASE)
/** Array initializer of IOMUXC peripheral base addresses */
#define IOMUXC_BASE_ADDRS { IOMUXC_BASE }
/** Array initializer of IOMUXC peripheral base pointers */
#define IOMUXC_BASE_PTRS { IOMUXC }
/*!
* @}
*/ /* end of group IOMUXC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC_GPR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_GPR_Peripheral_Access_Layer IOMUXC_GPR Peripheral Access Layer
* @{
*/
/** IOMUXC_GPR - Register Layout Typedef */
typedef struct {
__IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */
__IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */
__IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */
__IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */
__IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */
__IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */
__IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */
__IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */
__IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */
__IO uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */
__IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */
__IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */
__IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */
__IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */
__IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */
__IO uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */
__IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */
__IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */
__IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */
uint8_t RESERVED_0[4];
__IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */
__IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */
__IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */
__IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */
__IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */
__IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */
__IO uint32_t GPR26; /**< GPR26 General Purpose Register, offset: 0x68 */
__IO uint32_t GPR27; /**< GPR27 General Purpose Register, offset: 0x6C */
__IO uint32_t GPR28; /**< GPR28 General Purpose Register, offset: 0x70 */
__IO uint32_t GPR29; /**< GPR29 General Purpose Register, offset: 0x74 */
__IO uint32_t GPR30; /**< GPR30 General Purpose Register, offset: 0x78 */
__IO uint32_t GPR31; /**< GPR31 General Purpose Register, offset: 0x7C */
__IO uint32_t GPR32; /**< GPR32 General Purpose Register, offset: 0x80 */
__IO uint32_t GPR33; /**< GPR33 General Purpose Register, offset: 0x84 */
__IO uint32_t GPR34; /**< GPR34 General Purpose Register, offset: 0x88 */
__IO uint32_t GPR35; /**< GPR35 General Purpose Register, offset: 0x8C */
__IO uint32_t GPR36; /**< GPR36 General Purpose Register, offset: 0x90 */
__IO uint32_t GPR37; /**< GPR37 General Purpose Register, offset: 0x94 */
__IO uint32_t GPR38; /**< GPR38 General Purpose Register, offset: 0x98 */
__IO uint32_t GPR39; /**< GPR39 General Purpose Register, offset: 0x9C */
__IO uint32_t GPR40; /**< GPR40 General Purpose Register, offset: 0xA0 */
__IO uint32_t GPR41; /**< GPR41 General Purpose Register, offset: 0xA4 */
__IO uint32_t GPR42; /**< GPR42 General Purpose Register, offset: 0xA8 */
__IO uint32_t GPR43; /**< GPR43 General Purpose Register, offset: 0xAC */
__IO uint32_t GPR44; /**< GPR44 General Purpose Register, offset: 0xB0 */
__IO uint32_t GPR45; /**< GPR45 General Purpose Register, offset: 0xB4 */
__IO uint32_t GPR46; /**< GPR46 General Purpose Register, offset: 0xB8 */
__IO uint32_t GPR47; /**< GPR47 General Purpose Register, offset: 0xBC */
__IO uint32_t GPR48; /**< GPR48 General Purpose Register, offset: 0xC0 */
__IO uint32_t GPR49; /**< GPR49 General Purpose Register, offset: 0xC4 */
__IO uint32_t GPR50; /**< GPR50 General Purpose Register, offset: 0xC8 */
__IO uint32_t GPR51; /**< GPR51 General Purpose Register, offset: 0xCC */
__IO uint32_t GPR52; /**< GPR52 General Purpose Register, offset: 0xD0 */
__IO uint32_t GPR53; /**< GPR53 General Purpose Register, offset: 0xD4 */
__IO uint32_t GPR54; /**< GPR54 General Purpose Register, offset: 0xD8 */
__IO uint32_t GPR55; /**< GPR55 General Purpose Register, offset: 0xDC */
uint8_t RESERVED_1[12];
__IO uint32_t GPR59; /**< GPR59 General Purpose Register, offset: 0xEC */
uint8_t RESERVED_2[8];
__IO uint32_t GPR62; /**< GPR62 General Purpose Register, offset: 0xF8 */
__I uint32_t GPR63; /**< GPR63 General Purpose Register, offset: 0xFC */
__IO uint32_t GPR64; /**< GPR64 General Purpose Register, offset: 0x100 */
__IO uint32_t GPR65; /**< GPR65 General Purpose Register, offset: 0x104 */
__IO uint32_t GPR66; /**< GPR66 General Purpose Register, offset: 0x108 */
__IO uint32_t GPR67; /**< GPR67 General Purpose Register, offset: 0x10C */
__IO uint32_t GPR68; /**< GPR68 General Purpose Register, offset: 0x110 */
__IO uint32_t GPR69; /**< GPR69 General Purpose Register, offset: 0x114 */
__IO uint32_t GPR70; /**< GPR70 General Purpose Register, offset: 0x118 */
__IO uint32_t GPR71; /**< GPR71 General Purpose Register, offset: 0x11C */
__IO uint32_t GPR72; /**< GPR72 General Purpose Register, offset: 0x120 */
__IO uint32_t GPR73; /**< GPR73 General Purpose Register, offset: 0x124 */
__IO uint32_t GPR74; /**< GPR74 General Purpose Register, offset: 0x128 */
__I uint32_t GPR75; /**< GPR75 General Purpose Register, offset: 0x12C */
__I uint32_t GPR76; /**< GPR76 General Purpose Register, offset: 0x130 */
} IOMUXC_GPR_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC_GPR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_GPR_Register_Masks IOMUXC_GPR Register Masks
* @{
*/
/*! @name GPR0 - GPR0 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK (0x7U)
#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT (0U)
/*! SAI1_MCLK1_SEL - SAI1 MCLK1 source select
*/
#define IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK1_SEL_MASK)
#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK (0x38U)
#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT (3U)
/*! SAI1_MCLK2_SEL - SAI1 MCLK2 source select
*/
#define IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK2_SEL_MASK)
#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK (0xC0U)
#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT (6U)
/*! SAI1_MCLK3_SEL - SAI1 MCLK3 source select
*/
#define IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK3_SEL_MASK)
#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK (0x100U)
#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT (8U)
/*! SAI1_MCLK_DIR - SAI1_MCLK signal direction control
*/
#define IOMUXC_GPR_GPR0_SAI1_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR0_SAI1_MCLK_DIR_MASK)
#define IOMUXC_GPR_GPR0_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR0_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR0_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_SHIFT)) & IOMUXC_GPR_GPR0_DWP_MASK)
#define IOMUXC_GPR_GPR0_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR0_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR0_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR1 - GPR1 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK (0x3U)
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT (0U)
/*! SAI2_MCLK3_SEL - SAI2 MCLK3 source select
*/
#define IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK3_SEL_MASK)
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK (0x100U)
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT (8U)
/*! SAI2_MCLK_DIR - SAI2_MCLK signal direction control
*/
#define IOMUXC_GPR_GPR1_SAI2_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR1_SAI2_MCLK_DIR_MASK)
#define IOMUXC_GPR_GPR1_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR1_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR1_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_SHIFT)) & IOMUXC_GPR_GPR1_DWP_MASK)
#define IOMUXC_GPR_GPR1_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR1_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR1_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR2 - GPR2 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK (0x3U)
#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT (0U)
/*! SAI3_MCLK3_SEL - SAI3 MCLK3 source select
*/
#define IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK3_SEL_MASK)
#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK (0x100U)
#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT (8U)
/*! SAI3_MCLK_DIR - SAI3_MCLK signal direction control
*/
#define IOMUXC_GPR_GPR2_SAI3_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI3_MCLK_DIR_MASK)
#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK (0x200U)
#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT (9U)
/*! SAI4_MCLK_DIR - SAI4_MCLK signal direction control
*/
#define IOMUXC_GPR_GPR2_SAI4_MCLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_SHIFT)) & IOMUXC_GPR_GPR2_SAI4_MCLK_DIR_MASK)
#define IOMUXC_GPR_GPR2_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR2_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR2_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_SHIFT)) & IOMUXC_GPR_GPR2_DWP_MASK)
#define IOMUXC_GPR_GPR2_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR2_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR2_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR2_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR3 - GPR3 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK (0xFFU)
#define IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT (0U)
/*! MQS_CLK_DIV - Divider ratio control for mclk from hmclk.
*/
#define IOMUXC_GPR_GPR3_MQS_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_CLK_DIV_SHIFT)) & IOMUXC_GPR_GPR3_MQS_CLK_DIV_MASK)
#define IOMUXC_GPR_GPR3_MQS_SW_RST_MASK (0x100U)
#define IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT (8U)
/*! MQS_SW_RST - MQS software reset
*/
#define IOMUXC_GPR_GPR3_MQS_SW_RST(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_SW_RST_SHIFT)) & IOMUXC_GPR_GPR3_MQS_SW_RST_MASK)
#define IOMUXC_GPR_GPR3_MQS_EN_MASK (0x200U)
#define IOMUXC_GPR_GPR3_MQS_EN_SHIFT (9U)
/*! MQS_EN - MQS enable
*/
#define IOMUXC_GPR_GPR3_MQS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_EN_SHIFT)) & IOMUXC_GPR_GPR3_MQS_EN_MASK)
#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK (0x400U)
#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT (10U)
/*! MQS_OVERSAMPLE - Medium Quality Sound (MQS) Oversample
*/
#define IOMUXC_GPR_GPR3_MQS_OVERSAMPLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_SHIFT)) & IOMUXC_GPR_GPR3_MQS_OVERSAMPLE_MASK)
#define IOMUXC_GPR_GPR3_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR3_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR3_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_SHIFT)) & IOMUXC_GPR_GPR3_DWP_MASK)
#define IOMUXC_GPR_GPR3_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR3_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR3_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR3_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR4 - GPR4 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK (0x1U)
#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT (0U)
/*! ENET_TX_CLK_SEL - ENET TX_CLK select
*/
#define IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TX_CLK_SEL_MASK)
#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK (0x2U)
#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT (1U)
/*! ENET_REF_CLK_DIR - ENET_REF_CLK direction control
*/
#define IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR4_ENET_REF_CLK_DIR_MASK)
#define IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK (0x4U)
#define IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT (2U)
/*! ENET_TIME_SEL - ENET master timer source select
*/
#define IOMUXC_GPR_GPR4_ENET_TIME_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_TIME_SEL_MASK)
#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK (0x8U)
#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT (3U)
/*! ENET_EVENT0IN_SEL - ENET ENET_1588_EVENT0_IN source select
*/
#define IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR4_ENET_EVENT0IN_SEL_MASK)
#define IOMUXC_GPR_GPR4_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR4_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR4_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_SHIFT)) & IOMUXC_GPR_GPR4_DWP_MASK)
#define IOMUXC_GPR_GPR4_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR4_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR4_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR4_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR5 - GPR5 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK (0x1U)
#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT (0U)
/*! ENET1G_TX_CLK_SEL - ENET1G TX_CLK select
*/
#define IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TX_CLK_SEL_MASK)
#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK (0x2U)
#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT (1U)
/*! ENET1G_REF_CLK_DIR - ENET1G_REF_CLK direction control
*/
#define IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_REF_CLK_DIR_MASK)
#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK (0x4U)
#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT (2U)
/*! ENET1G_RGMII_EN - ENET1G RGMII TX clock output enable
*/
#define IOMUXC_GPR_GPR5_ENET1G_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_RGMII_EN_MASK)
#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK (0x8U)
#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT (3U)
/*! ENET1G_TIME_SEL - ENET1G master timer source select
*/
#define IOMUXC_GPR_GPR5_ENET1G_TIME_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_TIME_SEL_MASK)
#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK (0x10U)
#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT (4U)
/*! ENET1G_EVENT0IN_SEL - ENET1G ENET_1588_EVENT0_IN source select
*/
#define IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR5_ENET1G_EVENT0IN_SEL_MASK)
#define IOMUXC_GPR_GPR5_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR5_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR5_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_SHIFT)) & IOMUXC_GPR_GPR5_DWP_MASK)
#define IOMUXC_GPR_GPR5_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR5_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR5_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR5_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR6 - GPR6 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK (0x1U)
#define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_SHIFT (0U)
/*! ENET_QOS_REF_CLK_DIR - ENET_QOS_REF_CLK direction control
*/
#define IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_REF_CLK_DIR_MASK)
#define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK (0x2U)
#define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_SHIFT (1U)
/*! ENET_QOS_RGMII_EN - ENET_QOS RGMII TX clock output enable
*/
#define IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_RGMII_EN_MASK)
#define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_MASK (0x4U)
#define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_SHIFT (2U)
/*! ENET_QOS_TIME_SEL - ENET_QOS master timer source select
*/
#define IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_TIME_SEL_MASK)
#define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_MASK (0x38U)
#define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_SHIFT (3U)
/*! ENET_QOS_INTF_SEL - ENET_QOS PHY Interface Select
*/
#define IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_INTF_SEL_MASK)
#define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_MASK (0x40U)
#define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_SHIFT (6U)
/*! ENET_QOS_CLKGEN_EN - ENET_QOS clock generator enable
*/
#define IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_CLKGEN_EN_MASK)
#define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_MASK (0x80U)
#define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_SHIFT (7U)
/*! ENET_QOS_EVENT0IN_SEL - ENET_QOS ENET_1588_EVENT0_IN source select
*/
#define IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_SHIFT)) & IOMUXC_GPR_GPR6_ENET_QOS_EVENT0IN_SEL_MASK)
#define IOMUXC_GPR_GPR6_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR6_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR6_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_DWP_SHIFT)) & IOMUXC_GPR_GPR6_DWP_MASK)
#define IOMUXC_GPR_GPR6_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR6_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR6_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR6_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR6_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR7 - GPR7 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR7_GINT_MASK (0x1U)
#define IOMUXC_GPR_GPR7_GINT_SHIFT (0U)
/*! GINT - Global interrupt
*/
#define IOMUXC_GPR_GPR7_GINT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_GINT_SHIFT)) & IOMUXC_GPR_GPR7_GINT_MASK)
#define IOMUXC_GPR_GPR7_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR7_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR7_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_SHIFT)) & IOMUXC_GPR_GPR7_DWP_MASK)
#define IOMUXC_GPR_GPR7_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR7_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR7_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR7_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR8 - GPR8 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR8_WDOG1_MASK_MASK (0x1U)
#define IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT (0U)
/*! WDOG1_MASK - WDOG1 timeout mask for WDOG_ANY
*/
#define IOMUXC_GPR_GPR8_WDOG1_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_WDOG1_MASK_SHIFT)) & IOMUXC_GPR_GPR8_WDOG1_MASK_MASK)
#define IOMUXC_GPR_GPR8_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR8_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR8_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_SHIFT)) & IOMUXC_GPR_GPR8_DWP_MASK)
#define IOMUXC_GPR_GPR8_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR8_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR8_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR8_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR9 - GPR9 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR9_WDOG2_MASK_MASK (0x1U)
#define IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT (0U)
/*! WDOG2_MASK - WDOG2 timeout mask for WDOG_ANY
*/
#define IOMUXC_GPR_GPR9_WDOG2_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_WDOG2_MASK_SHIFT)) & IOMUXC_GPR_GPR9_WDOG2_MASK_MASK)
#define IOMUXC_GPR_GPR9_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR9_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR9_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_SHIFT)) & IOMUXC_GPR_GPR9_DWP_MASK)
#define IOMUXC_GPR_GPR9_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR9_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR9_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR9_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR10 - GPR10 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR10_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR10_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR10_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_SHIFT)) & IOMUXC_GPR_GPR10_DWP_MASK)
#define IOMUXC_GPR_GPR10_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR10_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR10_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR10_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR11 - GPR11 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR11_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR11_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR11_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_SHIFT)) & IOMUXC_GPR_GPR11_DWP_MASK)
#define IOMUXC_GPR_GPR11_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR11_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR11_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR11_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR12 - GPR12 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK (0x1U)
#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT (0U)
/*! QTIMER1_TMR_CNTS_FREEZE - QTIMER1 timer counter freeze
*/
#define IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TMR_CNTS_FREEZE_MASK)
#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK (0x100U)
#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT (8U)
/*! QTIMER1_TRM0_INPUT_SEL - QTIMER1 TMR0 input select
*/
#define IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM0_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK (0x200U)
#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT (9U)
/*! QTIMER1_TRM1_INPUT_SEL - QTIMER1 TMR1 input select
*/
#define IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM1_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK (0x400U)
#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT (10U)
/*! QTIMER1_TRM2_INPUT_SEL - QTIMER1 TMR2 input select
*/
#define IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM2_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK (0x800U)
#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT (11U)
/*! QTIMER1_TRM3_INPUT_SEL - QTIMER1 TMR3 input select
*/
#define IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR12_QTIMER1_TRM3_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR12_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR12_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR12_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_SHIFT)) & IOMUXC_GPR_GPR12_DWP_MASK)
#define IOMUXC_GPR_GPR12_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR12_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR12_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR12_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR13 - GPR13 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK (0x1U)
#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT (0U)
/*! QTIMER2_TMR_CNTS_FREEZE - QTIMER2 timer counter freeze
*/
#define IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TMR_CNTS_FREEZE_MASK)
#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK (0x100U)
#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT (8U)
/*! QTIMER2_TRM0_INPUT_SEL - QTIMER2 TMR0 input select
*/
#define IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM0_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK (0x200U)
#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT (9U)
/*! QTIMER2_TRM1_INPUT_SEL - QTIMER2 TMR1 input select
*/
#define IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM1_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK (0x400U)
#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT (10U)
/*! QTIMER2_TRM2_INPUT_SEL - QTIMER2 TMR2 input select
*/
#define IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM2_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK (0x800U)
#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT (11U)
/*! QTIMER2_TRM3_INPUT_SEL - QTIMER2 TMR3 input select
*/
#define IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR13_QTIMER2_TRM3_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR13_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR13_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR13_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_SHIFT)) & IOMUXC_GPR_GPR13_DWP_MASK)
#define IOMUXC_GPR_GPR13_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR13_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR13_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR13_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR14 - GPR14 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK (0x1U)
#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT (0U)
/*! QTIMER3_TMR_CNTS_FREEZE - QTIMER3 timer counter freeze
*/
#define IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TMR_CNTS_FREEZE_MASK)
#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK (0x100U)
#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT (8U)
/*! QTIMER3_TRM0_INPUT_SEL - QTIMER3 TMR0 input select
*/
#define IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM0_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK (0x200U)
#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT (9U)
/*! QTIMER3_TRM1_INPUT_SEL - QTIMER3 TMR1 input select
*/
#define IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM1_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK (0x400U)
#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT (10U)
/*! QTIMER3_TRM2_INPUT_SEL - QTIMER3 TMR2 input select
*/
#define IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM2_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK (0x800U)
#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT (11U)
/*! QTIMER3_TRM3_INPUT_SEL - QTIMER3 TMR3 input select
*/
#define IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR14_QTIMER3_TRM3_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR14_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR14_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR14_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_SHIFT)) & IOMUXC_GPR_GPR14_DWP_MASK)
#define IOMUXC_GPR_GPR14_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR14_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR14_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR14_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR15 - GPR15 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK (0x1U)
#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT (0U)
/*! QTIMER4_TMR_CNTS_FREEZE - QTIMER4 timer counter freeze
*/
#define IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TMR_CNTS_FREEZE_MASK)
#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK (0x100U)
#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT (8U)
/*! QTIMER4_TRM0_INPUT_SEL - QTIMER4 TMR0 input select
*/
#define IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM0_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK (0x200U)
#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT (9U)
/*! QTIMER4_TRM1_INPUT_SEL - QTIMER4 TMR1 input select
*/
#define IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM1_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK (0x400U)
#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT (10U)
/*! QTIMER4_TRM2_INPUT_SEL - QTIMER4 TMR2 input select
*/
#define IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM2_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK (0x800U)
#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT (11U)
/*! QTIMER4_TRM3_INPUT_SEL - QTIMER4 TMR3 input select
*/
#define IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_SHIFT)) & IOMUXC_GPR_GPR15_QTIMER4_TRM3_INPUT_SEL_MASK)
#define IOMUXC_GPR_GPR15_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR15_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR15_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_SHIFT)) & IOMUXC_GPR_GPR15_DWP_MASK)
#define IOMUXC_GPR_GPR15_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR15_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR15_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR15_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR16 - GPR16 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK (0x4U)
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT (2U)
/*! FLEXRAM_BANK_CFG_SEL - FlexRAM bank config source select
*/
#define IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_SHIFT)) & IOMUXC_GPR_GPR16_FLEXRAM_BANK_CFG_SEL_MASK)
#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK (0x8U)
#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT (3U)
/*! CM7_FORCE_HCLK_EN - CM7 platform AHB clock enable
*/
#define IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_SHIFT)) & IOMUXC_GPR_GPR16_CM7_FORCE_HCLK_EN_MASK)
#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK (0x20U)
#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT (5U)
/*! M7_GPC_SLEEP_SEL - CM7 sleep request selection
*/
#define IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_GPR_GPR16_M7_GPC_SLEEP_SEL_MASK)
#define IOMUXC_GPR_GPR16_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR16_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR16_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_SHIFT)) & IOMUXC_GPR_GPR16_DWP_MASK)
#define IOMUXC_GPR_GPR16_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR16_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR16_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR16_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR17 - GPR17 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK (0xFFFFU)
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT (0U)
/*! FLEXRAM_BANK_CFG_LOW - FlexRAM bank config value
*/
#define IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_SHIFT)) & IOMUXC_GPR_GPR17_FLEXRAM_BANK_CFG_LOW_MASK)
#define IOMUXC_GPR_GPR17_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR17_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR17_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_SHIFT)) & IOMUXC_GPR_GPR17_DWP_MASK)
#define IOMUXC_GPR_GPR17_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR17_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR17_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR17_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR18 - GPR18 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK (0xFFFFU)
#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT (0U)
/*! FLEXRAM_BANK_CFG_HIGH - FlexRAM bank config value
*/
#define IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_SHIFT)) & IOMUXC_GPR_GPR18_FLEXRAM_BANK_CFG_HIGH_MASK)
#define IOMUXC_GPR_GPR18_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR18_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR18_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_SHIFT)) & IOMUXC_GPR_GPR18_DWP_MASK)
#define IOMUXC_GPR_GPR18_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR18_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR18_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR18_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR20 - GPR20 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK (0x1U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT (0U)
/*! IOMUXC_XBAR_DIR_SEL_4 - IOMUXC XBAR_INOUT4 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_4_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK (0x2U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT (1U)
/*! IOMUXC_XBAR_DIR_SEL_5 - IOMUXC XBAR_INOUT5 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_5_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK (0x4U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT (2U)
/*! IOMUXC_XBAR_DIR_SEL_6 - IOMUXC XBAR_INOUT6 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_6_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK (0x8U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT (3U)
/*! IOMUXC_XBAR_DIR_SEL_7 - IOMUXC XBAR_INOUT7 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_7_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK (0x10U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT (4U)
/*! IOMUXC_XBAR_DIR_SEL_8 - IOMUXC XBAR_INOUT8 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_8_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK (0x20U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT (5U)
/*! IOMUXC_XBAR_DIR_SEL_9 - IOMUXC XBAR_INOUT9 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_9_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK (0x40U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT (6U)
/*! IOMUXC_XBAR_DIR_SEL_10 - IOMUXC XBAR_INOUT10 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_10_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK (0x80U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT (7U)
/*! IOMUXC_XBAR_DIR_SEL_11 - IOMUXC XBAR_INOUT11 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_11_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK (0x100U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT (8U)
/*! IOMUXC_XBAR_DIR_SEL_12 - IOMUXC XBAR_INOUT12 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_12_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK (0x200U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT (9U)
/*! IOMUXC_XBAR_DIR_SEL_13 - IOMUXC XBAR_INOUT13 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_13_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK (0x400U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT (10U)
/*! IOMUXC_XBAR_DIR_SEL_14 - IOMUXC XBAR_INOUT14 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_14_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK (0x800U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT (11U)
/*! IOMUXC_XBAR_DIR_SEL_15 - IOMUXC XBAR_INOUT15 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_15_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK (0x1000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT (12U)
/*! IOMUXC_XBAR_DIR_SEL_16 - IOMUXC XBAR_INOUT16 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_16_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK (0x2000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT (13U)
/*! IOMUXC_XBAR_DIR_SEL_17 - IOMUXC XBAR_INOUT17 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_17_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK (0x4000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT (14U)
/*! IOMUXC_XBAR_DIR_SEL_18 - IOMUXC XBAR_INOUT18 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_18_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK (0x8000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT (15U)
/*! IOMUXC_XBAR_DIR_SEL_19 - IOMUXC XBAR_INOUT19 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_19_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK (0x10000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT (16U)
/*! IOMUXC_XBAR_DIR_SEL_20 - IOMUXC XBAR_INOUT20 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_20_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK (0x20000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT (17U)
/*! IOMUXC_XBAR_DIR_SEL_21 - IOMUXC XBAR_INOUT21 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_21_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK (0x40000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT (18U)
/*! IOMUXC_XBAR_DIR_SEL_22 - IOMUXC XBAR_INOUT22 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_22_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK (0x80000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT (19U)
/*! IOMUXC_XBAR_DIR_SEL_23 - IOMUXC XBAR_INOUT23 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_23_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK (0x100000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT (20U)
/*! IOMUXC_XBAR_DIR_SEL_24 - IOMUXC XBAR_INOUT24 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_24_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK (0x200000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT (21U)
/*! IOMUXC_XBAR_DIR_SEL_25 - IOMUXC XBAR_INOUT25 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_25_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK (0x400000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT (22U)
/*! IOMUXC_XBAR_DIR_SEL_26 - IOMUXC XBAR_INOUT26 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_26_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK (0x800000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT (23U)
/*! IOMUXC_XBAR_DIR_SEL_27 - IOMUXC XBAR_INOUT27 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_27_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK (0x1000000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT (24U)
/*! IOMUXC_XBAR_DIR_SEL_28 - IOMUXC XBAR_INOUT28 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_28_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK (0x2000000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT (25U)
/*! IOMUXC_XBAR_DIR_SEL_29 - IOMUXC XBAR_INOUT29 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_29_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK (0x4000000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT (26U)
/*! IOMUXC_XBAR_DIR_SEL_30 - IOMUXC XBAR_INOUT30 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_30_MASK)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK (0x8000000U)
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT (27U)
/*! IOMUXC_XBAR_DIR_SEL_31 - IOMUXC XBAR_INOUT31 function direction select
*/
#define IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_SHIFT)) & IOMUXC_GPR_GPR20_IOMUXC_XBAR_DIR_SEL_31_MASK)
#define IOMUXC_GPR_GPR20_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR20_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR20_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_SHIFT)) & IOMUXC_GPR_GPR20_DWP_MASK)
#define IOMUXC_GPR_GPR20_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR20_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR20_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR20_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR21 - GPR21 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK (0x1U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT (0U)
/*! IOMUXC_XBAR_DIR_SEL_32 - IOMUXC XBAR_INOUT32 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_32_MASK)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK (0x2U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT (1U)
/*! IOMUXC_XBAR_DIR_SEL_33 - IOMUXC XBAR_INOUT33 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_33_MASK)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK (0x4U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT (2U)
/*! IOMUXC_XBAR_DIR_SEL_34 - IOMUXC XBAR_INOUT34 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_34_MASK)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK (0x8U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT (3U)
/*! IOMUXC_XBAR_DIR_SEL_35 - IOMUXC XBAR_INOUT35 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_35_MASK)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK (0x10U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT (4U)
/*! IOMUXC_XBAR_DIR_SEL_36 - IOMUXC XBAR_INOUT36 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_36_MASK)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK (0x20U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT (5U)
/*! IOMUXC_XBAR_DIR_SEL_37 - IOMUXC XBAR_INOUT37 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_37_MASK)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK (0x40U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT (6U)
/*! IOMUXC_XBAR_DIR_SEL_38 - IOMUXC XBAR_INOUT38 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_38_MASK)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK (0x80U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT (7U)
/*! IOMUXC_XBAR_DIR_SEL_39 - IOMUXC XBAR_INOUT39 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_39_MASK)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK (0x100U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT (8U)
/*! IOMUXC_XBAR_DIR_SEL_40 - IOMUXC XBAR_INOUT40 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_40_MASK)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK (0x200U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT (9U)
/*! IOMUXC_XBAR_DIR_SEL_41 - IOMUXC XBAR_INOUT41 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_41_MASK)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK (0x400U)
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT (10U)
/*! IOMUXC_XBAR_DIR_SEL_42 - IOMUXC XBAR_INOUT42 function direction select
*/
#define IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_SHIFT)) & IOMUXC_GPR_GPR21_IOMUXC_XBAR_DIR_SEL_42_MASK)
#define IOMUXC_GPR_GPR21_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR21_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR21_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_SHIFT)) & IOMUXC_GPR_GPR21_DWP_MASK)
#define IOMUXC_GPR_GPR21_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR21_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR21_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR21_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR22 - GPR22 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK (0x1U)
#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT (0U)
/*! REF_1M_CLK_GPT1 - GPT1 1 MHz clock source select
*/
#define IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_SHIFT)) & IOMUXC_GPR_GPR22_REF_1M_CLK_GPT1_MASK)
#define IOMUXC_GPR_GPR22_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR22_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR22_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_SHIFT)) & IOMUXC_GPR_GPR22_DWP_MASK)
#define IOMUXC_GPR_GPR22_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR22_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR22_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR22_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR23 - GPR23 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK (0x1U)
#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT (0U)
/*! REF_1M_CLK_GPT2 - GPT2 1 MHz clock source select
*/
#define IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_SHIFT)) & IOMUXC_GPR_GPR23_REF_1M_CLK_GPT2_MASK)
#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK (0x2U)
#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT (1U)
/*! GPT2_CAPIN1_SEL - GPT2 input capture channel 1 source select
*/
#define IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN1_SEL_MASK)
#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK (0x4U)
#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT (2U)
/*! GPT2_CAPIN2_SEL - GPT2 input capture channel 2 source select
*/
#define IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_SHIFT)) & IOMUXC_GPR_GPR23_GPT2_CAPIN2_SEL_MASK)
#define IOMUXC_GPR_GPR23_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR23_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR23_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_SHIFT)) & IOMUXC_GPR_GPR23_DWP_MASK)
#define IOMUXC_GPR_GPR23_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR23_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR23_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR23_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR24 - GPR24 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK (0x1U)
#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT (0U)
/*! REF_1M_CLK_GPT3 - GPT3 1 MHz clock source select
*/
#define IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_SHIFT)) & IOMUXC_GPR_GPR24_REF_1M_CLK_GPT3_MASK)
#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK (0x2U)
#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT (1U)
/*! GPT3_CAPIN1_SEL - GPT3 input capture channel 1 source select
*/
#define IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_SHIFT)) & IOMUXC_GPR_GPR24_GPT3_CAPIN1_SEL_MASK)
#define IOMUXC_GPR_GPR24_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR24_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR24_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_SHIFT)) & IOMUXC_GPR_GPR24_DWP_MASK)
#define IOMUXC_GPR_GPR24_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR24_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR24_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR24_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR25 - GPR25 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK (0x1U)
#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT (0U)
/*! REF_1M_CLK_GPT4 - GPT4 1 MHz clock source select
*/
#define IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_SHIFT)) & IOMUXC_GPR_GPR25_REF_1M_CLK_GPT4_MASK)
#define IOMUXC_GPR_GPR25_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR25_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR25_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_SHIFT)) & IOMUXC_GPR_GPR25_DWP_MASK)
#define IOMUXC_GPR_GPR25_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR25_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR25_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR25_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR26 - GPR26 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK (0x1U)
#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT (0U)
/*! REF_1M_CLK_GPT5 - GPT5 1 MHz clock source select
*/
#define IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_SHIFT)) & IOMUXC_GPR_GPR26_REF_1M_CLK_GPT5_MASK)
#define IOMUXC_GPR_GPR26_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR26_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR26_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_SHIFT)) & IOMUXC_GPR_GPR26_DWP_MASK)
#define IOMUXC_GPR_GPR26_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR26_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR26_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR27 - GPR27 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK (0x1U)
#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT (0U)
/*! REF_1M_CLK_GPT6 - GPT6 1 MHz clock source select
*/
#define IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_SHIFT)) & IOMUXC_GPR_GPR27_REF_1M_CLK_GPT6_MASK)
#define IOMUXC_GPR_GPR27_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR27_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR27_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_SHIFT)) & IOMUXC_GPR_GPR27_DWP_MASK)
#define IOMUXC_GPR_GPR27_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR27_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR27_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR27_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR28 - GPR28 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK (0x1U)
#define IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT (0U)
/*! ARCACHE_USDHC - uSDHC block cacheable attribute value of AXI read transactions
*/
#define IOMUXC_GPR_GPR28_ARCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_ARCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_ARCACHE_USDHC_MASK)
#define IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK (0x2U)
#define IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT (1U)
/*! AWCACHE_USDHC - uSDHC block cacheable attribute value of AXI write transactions
*/
#define IOMUXC_GPR_GPR28_AWCACHE_USDHC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_AWCACHE_USDHC_SHIFT)) & IOMUXC_GPR_GPR28_AWCACHE_USDHC_MASK)
#define IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK (0x20U)
#define IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT (5U)
#define IOMUXC_GPR_GPR28_CACHE_ENET1G(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET1G_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET1G_MASK)
#define IOMUXC_GPR_GPR28_CACHE_ENET_MASK (0x80U)
#define IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT (7U)
/*! CACHE_ENET - ENET block cacheable attribute value of AXI transactions
*/
#define IOMUXC_GPR_GPR28_CACHE_ENET(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_ENET_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_ENET_MASK)
#define IOMUXC_GPR_GPR28_CACHE_USB_MASK (0x2000U)
#define IOMUXC_GPR_GPR28_CACHE_USB_SHIFT (13U)
/*! CACHE_USB - USB block cacheable attribute value of AXI transactions
*/
#define IOMUXC_GPR_GPR28_CACHE_USB(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_CACHE_USB_SHIFT)) & IOMUXC_GPR_GPR28_CACHE_USB_MASK)
#define IOMUXC_GPR_GPR28_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR28_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR28_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_SHIFT)) & IOMUXC_GPR_GPR28_DWP_MASK)
#define IOMUXC_GPR_GPR28_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR28_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR28_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR28_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR29 - GPR29 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK (0x1U)
#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT (0U)
/*! USBPHY1_IPG_CLK_ACTIVE - USBPHY1 register access clock enable
*/
#define IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR29_USBPHY1_IPG_CLK_ACTIVE_MASK)
#define IOMUXC_GPR_GPR29_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR29_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR29_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_SHIFT)) & IOMUXC_GPR_GPR29_DWP_MASK)
#define IOMUXC_GPR_GPR29_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR29_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR29_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR29_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR30 - GPR30 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK (0x1U)
#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT (0U)
/*! USBPHY2_IPG_CLK_ACTIVE - USBPHY2 register access clock enable
*/
#define IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR30_USBPHY2_IPG_CLK_ACTIVE_MASK)
#define IOMUXC_GPR_GPR30_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR30_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR30_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_SHIFT)) & IOMUXC_GPR_GPR30_DWP_MASK)
#define IOMUXC_GPR_GPR30_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR30_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR30_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR30_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR31 - GPR31 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK (0x1U)
#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT (0U)
/*! RMW2_WAIT_BVALID_CPL - OCRAM M7 RMW wait enable
*/
#define IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR31_RMW2_WAIT_BVALID_CPL_MASK)
#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK (0x4U)
#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT (2U)
/*! OCRAM_M7_CLK_GATING - OCRAM M7 clock gating enable
*/
#define IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_SHIFT)) & IOMUXC_GPR_GPR31_OCRAM_M7_CLK_GATING_MASK)
#define IOMUXC_GPR_GPR31_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR31_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR31_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_SHIFT)) & IOMUXC_GPR_GPR31_DWP_MASK)
#define IOMUXC_GPR_GPR31_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR31_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR31_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR31_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR32 - GPR32 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK (0x1U)
#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT (0U)
/*! RMW1_WAIT_BVALID_CPL - OCRAM1 RMW wait enable
*/
#define IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR32_RMW1_WAIT_BVALID_CPL_MASK)
#define IOMUXC_GPR_GPR32_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR32_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR32_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_SHIFT)) & IOMUXC_GPR_GPR32_DWP_MASK)
#define IOMUXC_GPR_GPR32_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR32_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR32_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR32_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR33 - GPR33 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK (0x1U)
#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT (0U)
/*! RMW2_WAIT_BVALID_CPL - OCRAM2 RMW wait enable
*/
#define IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR33_RMW2_WAIT_BVALID_CPL_MASK)
#define IOMUXC_GPR_GPR33_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR33_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR33_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_SHIFT)) & IOMUXC_GPR_GPR33_DWP_MASK)
#define IOMUXC_GPR_GPR33_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR33_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR33_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR34 - GPR34 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK (0x1U)
#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT (0U)
/*! XECC_FLEXSPI1_WAIT_BVALID_CPL - XECC_FLEXSPI1 RMW wait enable
*/
#define IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR34_XECC_FLEXSPI1_WAIT_BVALID_CPL_MASK)
#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK (0x2U)
#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT (1U)
/*! FLEXSPI1_OTFAD_EN - FlexSPI1 OTFAD enable
*/
#define IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR34_FLEXSPI1_OTFAD_EN_MASK)
#define IOMUXC_GPR_GPR34_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR34_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR34_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_SHIFT)) & IOMUXC_GPR_GPR34_DWP_MASK)
#define IOMUXC_GPR_GPR34_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR34_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR34_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR35 - GPR35 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK (0x1U)
#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT (0U)
/*! XECC_FLEXSPI2_WAIT_BVALID_CPL - XECC_FLEXSPI2 RMW wait enable
*/
#define IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR35_XECC_FLEXSPI2_WAIT_BVALID_CPL_MASK)
#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK (0x2U)
#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT (1U)
/*! FLEXSPI2_OTFAD_EN - FlexSPI2 OTFAD enable
*/
#define IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_SHIFT)) & IOMUXC_GPR_GPR35_FLEXSPI2_OTFAD_EN_MASK)
#define IOMUXC_GPR_GPR35_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR35_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR35_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_SHIFT)) & IOMUXC_GPR_GPR35_DWP_MASK)
#define IOMUXC_GPR_GPR35_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR35_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR35_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR36 - GPR36 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK (0x1U)
#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT (0U)
/*! XECC_SEMC_WAIT_BVALID_CPL - XECC_SEMC RMW wait enable
*/
#define IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_SHIFT)) & IOMUXC_GPR_GPR36_XECC_SEMC_WAIT_BVALID_CPL_MASK)
#define IOMUXC_GPR_GPR36_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR36_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR36_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_SHIFT)) & IOMUXC_GPR_GPR36_DWP_MASK)
#define IOMUXC_GPR_GPR36_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR36_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR36_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR37 - GPR37 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR37_NIDEN_MASK (0x1U)
#define IOMUXC_GPR_GPR37_NIDEN_SHIFT (0U)
/*! NIDEN - ARM non-secure (non-invasive) debug enable
*/
#define IOMUXC_GPR_GPR37_NIDEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_NIDEN_SHIFT)) & IOMUXC_GPR_GPR37_NIDEN_MASK)
#define IOMUXC_GPR_GPR37_DBG_EN_MASK (0x2U)
#define IOMUXC_GPR_GPR37_DBG_EN_SHIFT (1U)
/*! DBG_EN - ARM invasive debug enable
*/
#define IOMUXC_GPR_GPR37_DBG_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DBG_EN_SHIFT)) & IOMUXC_GPR_GPR37_DBG_EN_MASK)
#define IOMUXC_GPR_GPR37_EXC_MON_MASK (0x8U)
#define IOMUXC_GPR_GPR37_EXC_MON_SHIFT (3U)
/*! EXC_MON - Exclusive monitor response select of illegal command
*/
#define IOMUXC_GPR_GPR37_EXC_MON(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_EXC_MON_SHIFT)) & IOMUXC_GPR_GPR37_EXC_MON_MASK)
#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK (0x20U)
#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT (5U)
/*! M7_DBG_ACK_MASK - CM7 debug halt mask
*/
#define IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M7_DBG_ACK_MASK_MASK)
#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK (0x40U)
#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT (6U)
/*! M4_DBG_ACK_MASK - CM4 debug halt mask
*/
#define IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_SHIFT)) & IOMUXC_GPR_GPR37_M4_DBG_ACK_MASK_MASK)
#define IOMUXC_GPR_GPR37_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR37_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR37_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_SHIFT)) & IOMUXC_GPR_GPR37_DWP_MASK)
#define IOMUXC_GPR_GPR37_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR37_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR37_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR38 - GPR38 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR38_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR38_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR38_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_SHIFT)) & IOMUXC_GPR_GPR38_DWP_MASK)
#define IOMUXC_GPR_GPR38_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR38_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR38_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR39 - GPR39 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR39_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR39_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR39_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_SHIFT)) & IOMUXC_GPR_GPR39_DWP_MASK)
#define IOMUXC_GPR_GPR39_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR39_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR39_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR40 - GPR40 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK (0xFFFFU)
#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT (0U)
/*! GPIO_MUX2_GPIO_SEL_LOW - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.
*/
#define IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR40_GPIO_MUX2_GPIO_SEL_LOW_MASK)
#define IOMUXC_GPR_GPR40_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR40_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR40_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_SHIFT)) & IOMUXC_GPR_GPR40_DWP_MASK)
#define IOMUXC_GPR_GPR40_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR40_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR40_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR40_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR41 - GPR41 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK (0xFFFFU)
#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT (0U)
/*! GPIO_MUX2_GPIO_SEL_HIGH - GPIO2 and CM7_GPIO2 share same IO MUX function, GPIO_MUX2 selects one GPIO function.
*/
#define IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR41_GPIO_MUX2_GPIO_SEL_HIGH_MASK)
#define IOMUXC_GPR_GPR41_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR41_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR41_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_SHIFT)) & IOMUXC_GPR_GPR41_DWP_MASK)
#define IOMUXC_GPR_GPR41_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR41_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR41_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR41_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR42 - GPR42 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK (0xFFFFU)
#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT (0U)
/*! GPIO_MUX3_GPIO_SEL_LOW - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.
*/
#define IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_SHIFT)) & IOMUXC_GPR_GPR42_GPIO_MUX3_GPIO_SEL_LOW_MASK)
#define IOMUXC_GPR_GPR42_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR42_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR42_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_SHIFT)) & IOMUXC_GPR_GPR42_DWP_MASK)
#define IOMUXC_GPR_GPR42_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR42_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR42_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR42_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR43 - GPR43 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK (0xFFFFU)
#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT (0U)
/*! GPIO_MUX3_GPIO_SEL_HIGH - GPIO3 and CM7_GPIO3 share same IO MUX function, GPIO_MUX3 selects one GPIO function.
*/
#define IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_SHIFT)) & IOMUXC_GPR_GPR43_GPIO_MUX3_GPIO_SEL_HIGH_MASK)
#define IOMUXC_GPR_GPR43_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR43_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR43_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_SHIFT)) & IOMUXC_GPR_GPR43_DWP_MASK)
#define IOMUXC_GPR_GPR43_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR43_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR43_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR43_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR44 - GPR44 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR44_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR44_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR44_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_SHIFT)) & IOMUXC_GPR_GPR44_DWP_MASK)
#define IOMUXC_GPR_GPR44_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR44_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR44_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR44_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR45 - GPR45 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR45_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR45_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR45_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_SHIFT)) & IOMUXC_GPR_GPR45_DWP_MASK)
#define IOMUXC_GPR_GPR45_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR45_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR45_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR45_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR46 - GPR46 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR46_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR46_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR46_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_SHIFT)) & IOMUXC_GPR_GPR46_DWP_MASK)
#define IOMUXC_GPR_GPR46_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR46_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR46_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR46_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR47 - GPR47 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR47_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR47_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR47_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_SHIFT)) & IOMUXC_GPR_GPR47_DWP_MASK)
#define IOMUXC_GPR_GPR47_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR47_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR47_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR47_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR48 - GPR48 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR48_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR48_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR48_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_SHIFT)) & IOMUXC_GPR_GPR48_DWP_MASK)
#define IOMUXC_GPR_GPR48_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR48_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR48_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR48_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR49 - GPR49 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR49_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR49_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR49_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_SHIFT)) & IOMUXC_GPR_GPR49_DWP_MASK)
#define IOMUXC_GPR_GPR49_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR49_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR49_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR49_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR50 - GPR50 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK (0x1FU)
#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT (0U)
/*! CAAM_IPS_MGR - CAAM manager processor identifier
*/
#define IOMUXC_GPR_GPR50_CAAM_IPS_MGR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_CAAM_IPS_MGR_SHIFT)) & IOMUXC_GPR_GPR50_CAAM_IPS_MGR_MASK)
#define IOMUXC_GPR_GPR50_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR50_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR50_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_SHIFT)) & IOMUXC_GPR_GPR50_DWP_MASK)
#define IOMUXC_GPR_GPR50_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR50_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR50_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR50_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR51 - GPR51 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK (0x1U)
#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT (0U)
/*! M7_NMI_CLEAR - Clear CM7 NMI holding register
*/
#define IOMUXC_GPR_GPR51_M7_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_M7_NMI_CLEAR_SHIFT)) & IOMUXC_GPR_GPR51_M7_NMI_CLEAR_MASK)
#define IOMUXC_GPR_GPR51_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR51_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR51_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_SHIFT)) & IOMUXC_GPR_GPR51_DWP_MASK)
#define IOMUXC_GPR_GPR51_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR51_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR51_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR51_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR52 - GPR52 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR52_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR52_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR52_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_SHIFT)) & IOMUXC_GPR_GPR52_DWP_MASK)
#define IOMUXC_GPR_GPR52_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR52_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR52_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR52_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR53 - GPR53 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR53_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR53_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR53_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_SHIFT)) & IOMUXC_GPR_GPR53_DWP_MASK)
#define IOMUXC_GPR_GPR53_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR53_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR53_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR53_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR54 - GPR54 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR54_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR54_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR54_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_SHIFT)) & IOMUXC_GPR_GPR54_DWP_MASK)
#define IOMUXC_GPR_GPR54_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR54_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR54_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR54_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR55 - GPR55 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR55_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR55_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR55_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_SHIFT)) & IOMUXC_GPR_GPR55_DWP_MASK)
#define IOMUXC_GPR_GPR55_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR55_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR55_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR55_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR59 - GPR59 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK (0x1U)
#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT (0U)
/*! MIPI_CSI_AUTO_PD_EN - Powers down inactive lanes reported by CSI2X_CFG_NUM_LANES.
*/
#define IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_AUTO_PD_EN_MASK)
#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK (0x2U)
#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT (1U)
/*! MIPI_CSI_SOFT_RST_N - MIPI CSI APB clock domain and User interface clock domain software reset bit
* 0b0..Assert reset
* 0b1..De-assert reset
*/
#define IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_SOFT_RST_N_MASK)
#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK (0x4U)
#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT (2U)
/*! MIPI_CSI_CONT_CLK_MODE - Enables the slave clock lane feature to maintain HS reception state
* during continuous clock mode operation, despite line glitches.
*/
#define IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_CONT_CLK_MODE_MASK)
#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK (0x8U)
#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT (3U)
/*! MIPI_CSI_DDRCLK_EN - When high, enables received DDR clock on CLK_DRXHS
*/
#define IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_DDRCLK_EN_MASK)
#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK (0x10U)
#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT (4U)
/*! MIPI_CSI_PD_RX - Power Down input for MIPI CSI PHY.
*/
#define IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_PD_RX_MASK)
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK (0x20U)
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT (5U)
/*! MIPI_CSI_RX_ENABLE - Assert to enable MIPI CSI Receive Enable
*/
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_ENABLE_MASK)
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK (0xC0U)
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT (6U)
/*! MIPI_CSI_RX_RCAL - MIPI CSI PHY on-chip termination control bits
*/
#define IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RX_RCAL_MASK)
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK (0x300U)
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT (8U)
/*! MIPI_CSI_RXCDRP - Programming bits that adjust the threshold voltage of LP-CD, default setting 2'b01
* 0b00..344mV
* 0b01..325mV (Default)
* 0b10..307mV
* 0b11..Invalid
*/
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXCDRP_MASK)
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK (0xC00U)
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT (10U)
/*! MIPI_CSI_RXLPRP - Programming bits that adjust the threshold voltage of LP-RX, default setting 2'b01
*/
#define IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_RXLPRP_MASK)
#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK (0x3F000U)
#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT (12U)
/*! MIPI_CSI_S_PRG_RXHS_SETTLE - Bits used to program T_HS_SETTLE.
*/
#define IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_SHIFT)) & IOMUXC_GPR_GPR59_MIPI_CSI_S_PRG_RXHS_SETTLE_MASK)
#define IOMUXC_GPR_GPR59_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR59_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR59_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_SHIFT)) & IOMUXC_GPR_GPR59_DWP_MASK)
#define IOMUXC_GPR_GPR59_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR59_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR59_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR59_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR62 - GPR62 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK (0x7U)
#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT (0U)
/*! MIPI_DSI_CLK_TM - MIPI DSI Clock Lane triming bits
*/
#define IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_CLK_TM_MASK)
#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK (0x38U)
#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT (3U)
/*! MIPI_DSI_D0_TM - MIPI DSI Data Lane 0 triming bits
*/
#define IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D0_TM_MASK)
#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK (0x1C0U)
#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT (6U)
/*! MIPI_DSI_D1_TM - MIPI DSI Data Lane 1 triming bits
*/
#define IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_D1_TM_MASK)
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK (0x600U)
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT (9U)
/*! MIPI_DSI_TX_RCAL - MIPI DSI PHY on-chip termination control bits
*/
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_RCAL_MASK)
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK (0x3800U)
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT (11U)
/*! MIPI_DSI_TX_ULPS_ENABLE - DSI transmit ULPS mode enable
*/
#define IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_TX_ULPS_ENABLE_MASK)
#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK (0x10000U)
#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT (16U)
/*! MIPI_DSI_PCLK_SOFT_RESET_N - MIPI DSI APB clock domain software reset bit
* 0b0..Assert reset
* 0b1..De-assert reset
*/
#define IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_PCLK_SOFT_RESET_N_MASK)
#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK (0x20000U)
#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT (17U)
/*! MIPI_DSI_BYTE_SOFT_RESET_N - MIPI DSI Byte clock domain software reset bit
* 0b0..Assert reset
* 0b1..De-assert reset
*/
#define IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_BYTE_SOFT_RESET_N_MASK)
#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK (0x40000U)
#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT (18U)
/*! MIPI_DSI_DPI_SOFT_RESET_N - MIPI DSI Pixel clock domain software reset bit
* 0b0..Assert reset
* 0b1..De-assert reset
*/
#define IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_DPI_SOFT_RESET_N_MASK)
#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK (0x80000U)
#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT (19U)
/*! MIPI_DSI_ESC_SOFT_RESET_N - MIPI DSI Escape clock domain software reset bit
* 0b0..Assert reset
* 0b1..De-assert reset
*/
#define IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_SHIFT)) & IOMUXC_GPR_GPR62_MIPI_DSI_ESC_SOFT_RESET_N_MASK)
#define IOMUXC_GPR_GPR62_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR62_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR62_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_SHIFT)) & IOMUXC_GPR_GPR62_DWP_MASK)
#define IOMUXC_GPR_GPR62_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR62_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR62_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR62_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR63 - GPR63 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK (0x7U)
#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT (0U)
/*! MIPI_DSI_TX_ULPS_ACTIVE - DSI transmit ULPS mode active flag
*/
#define IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_SHIFT)) & IOMUXC_GPR_GPR63_MIPI_DSI_TX_ULPS_ACTIVE_MASK)
/*! @} */
/*! @name GPR64 - GPR64 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK (0x1U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT (0U)
/*! GPIO_DISP1_FREEZE - Compensation code freeze
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FREEZE_MASK)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK (0x2U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT (1U)
/*! GPIO_DISP1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPTQ_MASK)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK (0x4U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT (2U)
/*! GPIO_DISP1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPEN_MASK)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK (0x8U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT (3U)
/*! GPIO_DISP1_FASTFRZ_EN - Compensation code fast freeze
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_FASTFRZ_EN_MASK)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK (0xF0U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT (4U)
/*! GPIO_DISP1_RASRCP - GPIO_DISP_B1 IO bank's 4-bit PMOS compensation codes from core
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCP_MASK)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK (0xF00U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT (8U)
/*! GPIO_DISP1_RASRCN - GPIO_DISP_B1 IO bank's 4-bit NMOS compensation codes from core
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_RASRCN_MASK)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK (0x1000U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT (12U)
/*! GPIO_DISP1_SELECT_NASRC - GPIO_DISP1_NASRC selection
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SELECT_NASRC_MASK)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK (0x2000U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT (13U)
/*! GPIO_DISP1_REFGEN_SLEEP - GPIO_DISP_B1 IO bank reference voltage generator cell sleep enable
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_REFGEN_SLEEP_MASK)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK (0x4000U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT (14U)
/*! GPIO_DISP1_SUPLYDET_LATCH - GPIO_DISP_B1 IO bank power supply mode latch enable
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_SUPLYDET_LATCH_MASK)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK (0x100000U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT (20U)
/*! GPIO_DISP1_COMPOK - GPIO_DISP_B1 IO bank compensation OK flag
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_COMPOK_MASK)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK (0x1E00000U)
#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT (21U)
/*! GPIO_DISP1_NASRC - GPIO_DISP_B1 IO bank compensation codes
*/
#define IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_SHIFT)) & IOMUXC_GPR_GPR64_GPIO_DISP1_NASRC_MASK)
#define IOMUXC_GPR_GPR64_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR64_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR64_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_SHIFT)) & IOMUXC_GPR_GPR64_DWP_MASK)
#define IOMUXC_GPR_GPR64_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR64_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR64_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR64_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR65 - GPR65 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK (0x1U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT (0U)
/*! GPIO_EMC1_FREEZE - Compensation code freeze
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FREEZE_MASK)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK (0x2U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT (1U)
/*! GPIO_EMC1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPTQ_MASK)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK (0x4U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT (2U)
/*! GPIO_EMC1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPEN_MASK)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK (0x8U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT (3U)
/*! GPIO_EMC1_FASTFRZ_EN - Compensation code fast freeze
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_FASTFRZ_EN_MASK)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK (0xF0U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT (4U)
/*! GPIO_EMC1_RASRCP - GPIO_EMC_B1 IO bank's 4-bit PMOS compensation codes from core
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCP_MASK)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK (0xF00U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT (8U)
/*! GPIO_EMC1_RASRCN - GPIO_EMC_B1 IO bank's 4-bit NMOS compensation codes from core
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_RASRCN_MASK)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK (0x1000U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT (12U)
/*! GPIO_EMC1_SELECT_NASRC - GPIO_EMC1_NASRC selection
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SELECT_NASRC_MASK)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK (0x2000U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT (13U)
/*! GPIO_EMC1_REFGEN_SLEEP - GPIO_EMC_B1 IO bank reference voltage generator cell sleep enable
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_REFGEN_SLEEP_MASK)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK (0x4000U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT (14U)
/*! GPIO_EMC1_SUPLYDET_LATCH - GPIO_EMC_B1 IO bank power supply mode latch enable
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_SUPLYDET_LATCH_MASK)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK (0x100000U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT (20U)
/*! GPIO_EMC1_COMPOK - GPIO_EMC_B1 IO bank compensation OK flag
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_COMPOK_MASK)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK (0x1E00000U)
#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT (21U)
/*! GPIO_EMC1_NASRC - GPIO_EMC_B1 IO bank compensation codes
*/
#define IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_SHIFT)) & IOMUXC_GPR_GPR65_GPIO_EMC1_NASRC_MASK)
#define IOMUXC_GPR_GPR65_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR65_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR65_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_SHIFT)) & IOMUXC_GPR_GPR65_DWP_MASK)
#define IOMUXC_GPR_GPR65_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR65_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR65_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR65_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR66 - GPR66 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK (0x1U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT (0U)
/*! GPIO_EMC2_FREEZE - Compensation code freeze
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FREEZE_MASK)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK (0x2U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT (1U)
/*! GPIO_EMC2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPTQ_MASK)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK (0x4U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT (2U)
/*! GPIO_EMC2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPEN_MASK)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK (0x8U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT (3U)
/*! GPIO_EMC2_FASTFRZ_EN - Compensation code fast freeze
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_FASTFRZ_EN_MASK)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK (0xF0U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT (4U)
/*! GPIO_EMC2_RASRCP - GPIO_EMC_B2 IO bank's 4-bit PMOS compensation codes from core
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCP_MASK)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK (0xF00U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT (8U)
/*! GPIO_EMC2_RASRCN - GPIO_EMC_B2 IO bank's 4-bit NMOS compensation codes from core
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_RASRCN_MASK)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK (0x1000U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT (12U)
/*! GPIO_EMC2_SELECT_NASRC - GPIO_EMC2_NASRC selection
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SELECT_NASRC_MASK)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK (0x2000U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT (13U)
/*! GPIO_EMC2_REFGEN_SLEEP - GPIO_EMC_B2 IO bank reference voltage generator cell sleep enable
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_REFGEN_SLEEP_MASK)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK (0x4000U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT (14U)
/*! GPIO_EMC2_SUPLYDET_LATCH - GPIO_EMC_B2 IO bank power supply mode latch enable
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_SUPLYDET_LATCH_MASK)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK (0x100000U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT (20U)
/*! GPIO_EMC2_COMPOK - GPIO_EMC_B2 IO bank compensation OK flag
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_COMPOK_MASK)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK (0x1E00000U)
#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT (21U)
/*! GPIO_EMC2_NASRC - GPIO_EMC_B2 IO bank compensation codes
*/
#define IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_SHIFT)) & IOMUXC_GPR_GPR66_GPIO_EMC2_NASRC_MASK)
#define IOMUXC_GPR_GPR66_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR66_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR66_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_SHIFT)) & IOMUXC_GPR_GPR66_DWP_MASK)
#define IOMUXC_GPR_GPR66_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR66_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR66_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR66_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR67 - GPR67 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK (0x1U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT (0U)
/*! GPIO_SD1_FREEZE - Compensation code freeze
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FREEZE_MASK)
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK (0x2U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT (1U)
/*! GPIO_SD1_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPTQ_MASK)
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK (0x4U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT (2U)
/*! GPIO_SD1_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPEN_MASK)
#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK (0x8U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT (3U)
/*! GPIO_SD1_FASTFRZ_EN - Compensation code fast freeze
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_FASTFRZ_EN_MASK)
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK (0xF0U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT (4U)
/*! GPIO_SD1_RASRCP - GPIO_SD_B1 IO bank's 4-bit PMOS compensation codes from core
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCP_MASK)
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK (0xF00U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT (8U)
/*! GPIO_SD1_RASRCN - GPIO_SD_B1 IO bank's 4-bit NMOS compensation codes from core
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_RASRCN_MASK)
#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK (0x1000U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT (12U)
/*! GPIO_SD1_SELECT_NASRC - GPIO_SD1_NASRC selection
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SELECT_NASRC_MASK)
#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK (0x2000U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT (13U)
/*! GPIO_SD1_REFGEN_SLEEP - GPIO_SD_B1 IO bank reference voltage generator cell sleep enable
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_REFGEN_SLEEP_MASK)
#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK (0x4000U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT (14U)
/*! GPIO_SD1_SUPLYDET_LATCH - GPIO_SD_B1 IO bank power supply mode latch enable
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_SUPLYDET_LATCH_MASK)
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK (0x100000U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT (20U)
/*! GPIO_SD1_COMPOK - GPIO_SD_B1 IO bank compensation OK flag
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_COMPOK_MASK)
#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK (0x1E00000U)
#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT (21U)
/*! GPIO_SD1_NASRC - GPIO_SD_B1 IO bank compensation codes
*/
#define IOMUXC_GPR_GPR67_GPIO_SD1_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_SHIFT)) & IOMUXC_GPR_GPR67_GPIO_SD1_NASRC_MASK)
#define IOMUXC_GPR_GPR67_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR67_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR67_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_SHIFT)) & IOMUXC_GPR_GPR67_DWP_MASK)
#define IOMUXC_GPR_GPR67_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR67_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR67_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR67_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR68 - GPR68 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK (0x1U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT (0U)
/*! GPIO_SD2_FREEZE - Compensation code freeze
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FREEZE_MASK)
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK (0x2U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT (1U)
/*! GPIO_SD2_COMPTQ - COMPEN and COMPTQ control the operating modes of the compensation cell
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPTQ_MASK)
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK (0x4U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT (2U)
/*! GPIO_SD2_COMPEN - COMPEN and COMPTQ control the operating modes of the compensation cell
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPEN_MASK)
#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK (0x8U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT (3U)
/*! GPIO_SD2_FASTFRZ_EN - Compensation code fast freeze
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_FASTFRZ_EN_MASK)
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK (0xF0U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT (4U)
/*! GPIO_SD2_RASRCP - GPIO_SD_B2 IO bank's 4-bit PMOS compensation codes from core
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCP_MASK)
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK (0xF00U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT (8U)
/*! GPIO_SD2_RASRCN - GPIO_SD_B2 IO bank's 4-bit NMOS compensation codes from core
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_RASRCN_MASK)
#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK (0x1000U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT (12U)
/*! GPIO_SD2_SELECT_NASRC - GPIO_SD2_NASRC selection
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SELECT_NASRC_MASK)
#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK (0x2000U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT (13U)
/*! GPIO_SD2_REFGEN_SLEEP - GPIO_SD_B2 IO bank reference voltage generator cell sleep enable
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_REFGEN_SLEEP_MASK)
#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK (0x4000U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT (14U)
/*! GPIO_SD2_SUPLYDET_LATCH - GPIO_SD_B2 IO bank power supply mode latch enable
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_SUPLYDET_LATCH_MASK)
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK (0x100000U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT (20U)
/*! GPIO_SD2_COMPOK - GPIO_SD_B2 IO bank compensation OK flag
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_COMPOK_MASK)
#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK (0x1E00000U)
#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT (21U)
/*! GPIO_SD2_NASRC - GPIO_SD_B2 IO bank compensation codes
*/
#define IOMUXC_GPR_GPR68_GPIO_SD2_NASRC(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_SHIFT)) & IOMUXC_GPR_GPR68_GPIO_SD2_NASRC_MASK)
#define IOMUXC_GPR_GPR68_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR68_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR68_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_SHIFT)) & IOMUXC_GPR_GPR68_DWP_MASK)
#define IOMUXC_GPR_GPR68_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR68_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR68_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR68_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR69 - GPR69 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK (0x2U)
#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT (1U)
/*! GPIO_DISP2_HIGH_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection
*/
#define IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_HIGH_RANGE_MASK)
#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK (0x4U)
#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT (2U)
/*! GPIO_DISP2_LOW_RANGE - GPIO_DISP_B2 IO bank supply voltage range selection
*/
#define IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_DISP2_LOW_RANGE_MASK)
#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK (0x10U)
#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT (4U)
/*! GPIO_AD0_HIGH_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17
*/
#define IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_HIGH_RANGE_MASK)
#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK (0x20U)
#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT (5U)
/*! GPIO_AD0_LOW_RANGE - GPIO_AD IO bank supply voltage range selection for GPIO_AD_00 to GPIO_AD_17
*/
#define IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD0_LOW_RANGE_MASK)
#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK (0x80U)
#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT (7U)
/*! GPIO_AD1_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35
*/
#define IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_HIGH_RANGE_MASK)
#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK (0x100U)
#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT (8U)
/*! GPIO_AD1_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection for GPIO_AD_18 to GPIO_AD_35
*/
#define IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_SHIFT)) & IOMUXC_GPR_GPR69_GPIO_AD1_LOW_RANGE_MASK)
#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK (0x200U)
#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT (9U)
/*! SUPLYDET_DISP1_SLEEP - GPIO_DISP_B1 IO bank supply voltage detector sleep mode enable
*/
#define IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_DISP1_SLEEP_MASK)
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK (0x400U)
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT (10U)
/*! SUPLYDET_EMC1_SLEEP - GPIO_EMC_B1 IO bank supply voltage detector sleep mode enable
*/
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC1_SLEEP_MASK)
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK (0x800U)
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT (11U)
/*! SUPLYDET_EMC2_SLEEP - GPIO_EMC_B2 IO bank supply voltage detector sleep mode enable
*/
#define IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_EMC2_SLEEP_MASK)
#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK (0x1000U)
#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT (12U)
/*! SUPLYDET_SD1_SLEEP - GPIO_SD_B1 IO bank supply voltage detector sleep mode enable
*/
#define IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD1_SLEEP_MASK)
#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK (0x2000U)
#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT (13U)
/*! SUPLYDET_SD2_SLEEP - GPIO_SD_B2 IO bank supply voltage detector sleep mode enable
*/
#define IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_SHIFT)) & IOMUXC_GPR_GPR69_SUPLYDET_SD2_SLEEP_MASK)
#define IOMUXC_GPR_GPR69_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR69_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR69_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_SHIFT)) & IOMUXC_GPR_GPR69_DWP_MASK)
#define IOMUXC_GPR_GPR69_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR69_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR69_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR69_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR70 - GPR70 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK (0x1U)
#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT (0U)
/*! ADC1_IPG_DOZE - ADC1 doze mode
*/
#define IOMUXC_GPR_GPR70_ADC1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK (0x2U)
#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT (1U)
/*! ADC1_STOP_REQ - ADC1 stop request
*/
#define IOMUXC_GPR_GPR70_ADC1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK (0x4U)
#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT (2U)
/*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection, cannot change when ADC1_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC1_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK (0x8U)
#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT (3U)
/*! ADC2_IPG_DOZE - ADC2 doze mode
*/
#define IOMUXC_GPR_GPR70_ADC2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK (0x10U)
#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT (4U)
/*! ADC2_STOP_REQ - ADC2 stop request
*/
#define IOMUXC_GPR_GPR70_ADC2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK (0x20U)
#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT (5U)
/*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection, cannot change when ADC2_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR70_ADC2_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK (0x40U)
#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT (6U)
/*! CAAM_IPG_DOZE - CAN3 doze mode
*/
#define IOMUXC_GPR_GPR70_CAAM_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK (0x80U)
#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT (7U)
/*! CAAM_STOP_REQ - CAAM stop request
*/
#define IOMUXC_GPR_GPR70_CAAM_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAAM_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAAM_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK (0x100U)
#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT (8U)
/*! CAN1_IPG_DOZE - CAN1 doze mode
*/
#define IOMUXC_GPR_GPR70_CAN1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK (0x200U)
#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT (9U)
/*! CAN1_STOP_REQ - CAN1 stop request
*/
#define IOMUXC_GPR_GPR70_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK (0x400U)
#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT (10U)
/*! CAN2_IPG_DOZE - CAN2 doze mode
*/
#define IOMUXC_GPR_GPR70_CAN2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK (0x800U)
#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT (11U)
/*! CAN2_STOP_REQ - CAN2 stop request
*/
#define IOMUXC_GPR_GPR70_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK (0x1000U)
#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT (12U)
/*! CAN3_IPG_DOZE - CAN3 doze mode
*/
#define IOMUXC_GPR_GPR70_CAN3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK (0x2000U)
#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT (13U)
/*! CAN3_STOP_REQ - CAN3 stop request
*/
#define IOMUXC_GPR_GPR70_CAN3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_CAN3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_CAN3_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK (0x8000U)
#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT (15U)
/*! EDMA_STOP_REQ - EDMA stop request
*/
#define IOMUXC_GPR_GPR70_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK (0x10000U)
#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT (16U)
/*! EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request
*/
#define IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_EDMA_LPSR_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK (0x20000U)
#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT (17U)
/*! ENET_IPG_DOZE - ENET doze mode
*/
#define IOMUXC_GPR_GPR70_ENET_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK (0x40000U)
#define IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT (18U)
/*! ENET_STOP_REQ - ENET stop request
*/
#define IOMUXC_GPR_GPR70_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK (0x80000U)
#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT (19U)
/*! ENET1G_IPG_DOZE - ENET1G doze mode
*/
#define IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK (0x100000U)
#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT (20U)
/*! ENET1G_STOP_REQ - ENET1G stop request
*/
#define IOMUXC_GPR_GPR70_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_ENET1G_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK (0x200000U)
#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT (21U)
/*! FLEXIO1_IPG_DOZE - FLEXIO2 doze mode
*/
#define IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK (0x400000U)
#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT (22U)
/*! FLEXIO2_IPG_DOZE - FLEXIO2 doze mode
*/
#define IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXIO2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK (0x800000U)
#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT (23U)
/*! FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode
*/
#define IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK (0x1000000U)
#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT (24U)
/*! FLEXSPI1_STOP_REQ - FLEXSPI1 stop request
*/
#define IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK (0x2000000U)
#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT (25U)
/*! FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode
*/
#define IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK (0x4000000U)
#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT (26U)
/*! FLEXSPI2_STOP_REQ - FLEXSPI2 stop request
*/
#define IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR70_FLEXSPI2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR70_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR70_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR70_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_SHIFT)) & IOMUXC_GPR_GPR70_DWP_MASK)
#define IOMUXC_GPR_GPR70_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR70_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR70_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR70_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR71 - GPR71 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK (0x1U)
#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT (0U)
/*! GPT1_IPG_DOZE - GPT1 doze mode
*/
#define IOMUXC_GPR_GPR71_GPT1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK (0x2U)
#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT (1U)
/*! GPT2_IPG_DOZE - GPT2 doze mode
*/
#define IOMUXC_GPR_GPR71_GPT2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK (0x4U)
#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT (2U)
/*! GPT3_IPG_DOZE - GPT3 doze mode
*/
#define IOMUXC_GPR_GPR71_GPT3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT3_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK (0x8U)
#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT (3U)
/*! GPT4_IPG_DOZE - GPT4 doze mode
*/
#define IOMUXC_GPR_GPR71_GPT4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT4_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK (0x10U)
#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT (4U)
/*! GPT5_IPG_DOZE - GPT5 doze mode
*/
#define IOMUXC_GPR_GPR71_GPT5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT5_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK (0x20U)
#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT (5U)
/*! GPT6_IPG_DOZE - GPT6 doze mode
*/
#define IOMUXC_GPR_GPR71_GPT6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_GPT6_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK (0x40U)
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT (6U)
/*! LPI2C1_IPG_DOZE - LPI2C1 doze mode
*/
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK (0x80U)
#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT (7U)
/*! LPI2C1_STOP_REQ - LPI2C1 stop request
*/
#define IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK (0x100U)
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT (8U)
/*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection, cannot change when LPI2C1_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C1_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK (0x200U)
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT (9U)
/*! LPI2C2_IPG_DOZE - LPI2C2 doze mode
*/
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK (0x400U)
#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT (10U)
/*! LPI2C2_STOP_REQ - LPI2C2 stop request
*/
#define IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK (0x800U)
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT (11U)
/*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection, cannot change when LPI2C2_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C2_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK (0x1000U)
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT (12U)
/*! LPI2C3_IPG_DOZE - LPI2C3 doze mode
*/
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK (0x2000U)
#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT (13U)
/*! LPI2C3_STOP_REQ - LPI2C3 stop request
*/
#define IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK (0x4000U)
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT (14U)
/*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection, cannot change when LPI2C3_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C3_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK (0x8000U)
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT (15U)
/*! LPI2C4_IPG_DOZE - LPI2C4 doze mode
*/
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK (0x10000U)
#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT (16U)
/*! LPI2C4_STOP_REQ - LPI2C4 stop request
*/
#define IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK (0x20000U)
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT (17U)
/*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection, cannot change when LPI2C4_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C4_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK (0x40000U)
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT (18U)
/*! LPI2C5_IPG_DOZE - LPI2C5 doze mode
*/
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK (0x80000U)
#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT (19U)
/*! LPI2C5_STOP_REQ - LPI2C5 stop request
*/
#define IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK (0x100000U)
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT (20U)
/*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection, cannot change when LPI2C5_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C5_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK (0x200000U)
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT (21U)
/*! LPI2C6_IPG_DOZE - LPI2C6 doze mode
*/
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK (0x400000U)
#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT (22U)
/*! LPI2C6_STOP_REQ - LPI2C6 stop request
*/
#define IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK (0x800000U)
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT (23U)
/*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection, cannot change when LPI2C6_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPI2C6_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK (0x1000000U)
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT (24U)
/*! LPSPI1_IPG_DOZE - LPSPI1 doze mode
*/
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK (0x2000000U)
#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT (25U)
/*! LPSPI1_STOP_REQ - LPSPI1 stop request
*/
#define IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U)
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT (26U)
/*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection, cannot change when LPSPI1_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR71_LPSPI1_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR71_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR71_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR71_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_SHIFT)) & IOMUXC_GPR_GPR71_DWP_MASK)
#define IOMUXC_GPR_GPR71_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR71_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR71_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR71_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR72 - GPR72 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK (0x1U)
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT (0U)
/*! LPSPI2_IPG_DOZE - LPSPI2 doze mode
*/
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK (0x2U)
#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT (1U)
/*! LPSPI2_STOP_REQ - LPSPI2 stop request
*/
#define IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK (0x4U)
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT (2U)
/*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection, cannot change when LPSPI2_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI2_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK (0x8U)
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT (3U)
/*! LPSPI3_IPG_DOZE - LPSPI3 doze mode
*/
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK (0x10U)
#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT (4U)
/*! LPSPI3_STOP_REQ - LPSPI3 stop request
*/
#define IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK (0x20U)
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT (5U)
/*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection, cannot change when LPSPI3_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI3_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK (0x40U)
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT (6U)
/*! LPSPI4_IPG_DOZE - LPSPI4 doze mode
*/
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK (0x80U)
#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT (7U)
/*! LPSPI4_STOP_REQ - LPSPI4 stop request
*/
#define IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK (0x100U)
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT (8U)
/*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection, cannot change when LPSPI4_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI4_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK (0x200U)
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT (9U)
/*! LPSPI5_IPG_DOZE - LPSPI5 doze mode
*/
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK (0x400U)
#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT (10U)
/*! LPSPI5_STOP_REQ - LPSPI5 stop request
*/
#define IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK (0x800U)
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT (11U)
/*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection, cannot change when LPSPI5_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI5_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK (0x1000U)
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT (12U)
/*! LPSPI6_IPG_DOZE - LPSPI6 doze mode
*/
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK (0x2000U)
#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT (13U)
/*! LPSPI6_STOP_REQ - LPSPI6 stop request
*/
#define IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK (0x4000U)
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT (14U)
/*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection, cannot change when LPSPI6_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPSPI6_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK (0x8000U)
#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT (15U)
/*! LPUART1_IPG_DOZE - LPUART1 doze mode
*/
#define IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK (0x10000U)
#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT (16U)
/*! LPUART1_STOP_REQ - LPUART1 stop request
*/
#define IOMUXC_GPR_GPR72_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK (0x20000U)
#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT (17U)
/*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection, cannot change when LPUART1_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART1_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK (0x40000U)
#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT (18U)
/*! LPUART2_IPG_DOZE - LPUART2 doze mode
*/
#define IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK (0x80000U)
#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT (19U)
/*! LPUART2_STOP_REQ - LPUART2 stop request
*/
#define IOMUXC_GPR_GPR72_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK (0x100000U)
#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT (20U)
/*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection, cannot change when LPUART2_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART2_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK (0x200000U)
#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT (21U)
/*! LPUART3_IPG_DOZE - LPUART3 doze mode
*/
#define IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK (0x400000U)
#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT (22U)
/*! LPUART3_STOP_REQ - LPUART3 stop request
*/
#define IOMUXC_GPR_GPR72_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK (0x800000U)
#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT (23U)
/*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection, cannot change when LPUART3_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART3_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK (0x1000000U)
#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT (24U)
/*! LPUART4_IPG_DOZE - LPUART4 doze mode
*/
#define IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK (0x2000000U)
#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT (25U)
/*! LPUART4_STOP_REQ - LPUART4 stop request
*/
#define IOMUXC_GPR_GPR72_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK (0x4000000U)
#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT (26U)
/*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection, cannot change when LPUART4_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR72_LPUART4_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR72_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR72_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR72_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_SHIFT)) & IOMUXC_GPR_GPR72_DWP_MASK)
#define IOMUXC_GPR_GPR72_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR72_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR72_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR72_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR73 - GPR73 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK (0x1U)
#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT (0U)
/*! LPUART5_IPG_DOZE - LPUART5 doze mode
*/
#define IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK (0x2U)
#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT (1U)
/*! LPUART5_STOP_REQ - LPUART5 stop request
*/
#define IOMUXC_GPR_GPR73_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK (0x4U)
#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT (2U)
/*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection, cannot change when LPUART5_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART5_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK (0x8U)
#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT (3U)
/*! LPUART6_IPG_DOZE - LPUART6 doze mode
*/
#define IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK (0x10U)
#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT (4U)
/*! LPUART6_STOP_REQ - LPUART6 stop request
*/
#define IOMUXC_GPR_GPR73_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK (0x20U)
#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT (5U)
/*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection, cannot change when LPUART6_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART6_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK (0x40U)
#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT (6U)
/*! LPUART7_IPG_DOZE - LPUART7 doze mode
*/
#define IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK (0x80U)
#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT (7U)
/*! LPUART7_STOP_REQ - LPUART7 stop request
*/
#define IOMUXC_GPR_GPR73_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK (0x100U)
#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT (8U)
/*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection, cannot change when LPUART7_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART7_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK (0x200U)
#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT (9U)
/*! LPUART8_IPG_DOZE - LPUART8 doze mode
*/
#define IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK (0x400U)
#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT (10U)
/*! LPUART8_STOP_REQ - LPUART8 stop request
*/
#define IOMUXC_GPR_GPR73_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK (0x800U)
#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT (11U)
/*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection, cannot change when LPUART8_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART8_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK (0x1000U)
#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT (12U)
/*! LPUART9_IPG_DOZE - LPUART9 doze mode
*/
#define IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK (0x2000U)
#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT (13U)
/*! LPUART9_STOP_REQ - LPUART9 stop request
*/
#define IOMUXC_GPR_GPR73_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK (0x4000U)
#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT (14U)
/*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection, cannot change when LPUART9_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART9_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK (0x8000U)
#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT (15U)
/*! LPUART10_IPG_DOZE - LPUART10 doze mode
*/
#define IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK (0x10000U)
#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT (16U)
/*! LPUART10_STOP_REQ - LPUART10 stop request
*/
#define IOMUXC_GPR_GPR73_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK (0x20000U)
#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT (17U)
/*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection, cannot change when LPUART10_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART10_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK (0x40000U)
#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT (18U)
/*! LPUART11_IPG_DOZE - LPUART11 doze mode
*/
#define IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK (0x80000U)
#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT (19U)
/*! LPUART11_STOP_REQ - LPUART11 stop request
*/
#define IOMUXC_GPR_GPR73_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK (0x100000U)
#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT (20U)
/*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection, cannot change when LPUART11_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART11_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK (0x200000U)
#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT (21U)
/*! LPUART12_IPG_DOZE - LPUART12 doze mode
*/
#define IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK (0x400000U)
#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT (22U)
/*! LPUART12_STOP_REQ - LPUART12 stop request
*/
#define IOMUXC_GPR_GPR73_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK (0x800000U)
#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT (23U)
/*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection, cannot change when LPUART12_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_LPUART12_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK (0x1000000U)
#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT (24U)
/*! MIC_IPG_DOZE - MIC doze mode
*/
#define IOMUXC_GPR_GPR73_MIC_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK (0x2000000U)
#define IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT (25U)
/*! MIC_STOP_REQ - MIC stop request
*/
#define IOMUXC_GPR_GPR73_MIC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR73_MIC_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK (0x4000000U)
#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT (26U)
/*! MIC_IPG_STOP_MODE - MIC stop mode selection, cannot change when MIC_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_GPR_GPR73_MIC_IPG_STOP_MODE_MASK)
#define IOMUXC_GPR_GPR73_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR73_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR73_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_SHIFT)) & IOMUXC_GPR_GPR73_DWP_MASK)
#define IOMUXC_GPR_GPR73_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR73_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR73_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR73_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR74 - GPR74 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK (0x2U)
#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT (1U)
/*! PIT1_STOP_REQ - PIT1 stop request
*/
#define IOMUXC_GPR_GPR74_PIT1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK (0x4U)
#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT (2U)
/*! PIT2_STOP_REQ - PIT2 stop request
*/
#define IOMUXC_GPR_GPR74_PIT2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_PIT2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_PIT2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK (0x8U)
#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT (3U)
/*! SEMC_STOP_REQ - SEMC stop request
*/
#define IOMUXC_GPR_GPR74_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SEMC_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SEMC_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK (0x10U)
#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT (4U)
/*! SIM1_IPG_DOZE - SIM1 doze mode
*/
#define IOMUXC_GPR_GPR74_SIM1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK (0x20U)
#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT (5U)
/*! SIM2_IPG_DOZE - SIM2 doze mode
*/
#define IOMUXC_GPR_GPR74_SIM2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SIM2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK (0x40U)
#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT (6U)
/*! SNVS_HP_IPG_DOZE - SNVS_HP doze mode
*/
#define IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK (0x80U)
#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT (7U)
/*! SNVS_HP_STOP_REQ - SNVS_HP stop request
*/
#define IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SNVS_HP_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK (0x100U)
#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT (8U)
/*! WDOG1_IPG_DOZE - WDOG1 doze mode
*/
#define IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG1_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK (0x200U)
#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT (9U)
/*! WDOG2_IPG_DOZE - WDOG2 doze mode
*/
#define IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_GPR_GPR74_WDOG2_IPG_DOZE_MASK)
#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK (0x400U)
#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT (10U)
/*! SAI1_STOP_REQ - SAI1 stop request
*/
#define IOMUXC_GPR_GPR74_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI1_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI1_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK (0x800U)
#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT (11U)
/*! SAI2_STOP_REQ - SAI2 stop request
*/
#define IOMUXC_GPR_GPR74_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI2_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI2_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK (0x1000U)
#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT (12U)
/*! SAI3_STOP_REQ - SAI3 stop request
*/
#define IOMUXC_GPR_GPR74_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI3_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI3_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK (0x2000U)
#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT (13U)
/*! SAI4_STOP_REQ - SAI4 stop request
*/
#define IOMUXC_GPR_GPR74_SAI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_SAI4_STOP_REQ_SHIFT)) & IOMUXC_GPR_GPR74_SAI4_STOP_REQ_MASK)
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U)
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT (14U)
/*! FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request
*/
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_BUS_MASK)
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK (0x8000U)
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT (15U)
/*! FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request
*/
#define IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO1_STOP_REQ_PER_MASK)
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U)
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT (16U)
/*! FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request
*/
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_BUS_MASK)
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK (0x20000U)
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT (17U)
/*! FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request
*/
#define IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_GPR_GPR74_FLEXIO2_STOP_REQ_PER_MASK)
#define IOMUXC_GPR_GPR74_DWP_MASK (0x30000000U)
#define IOMUXC_GPR_GPR74_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_GPR_GPR74_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_SHIFT)) & IOMUXC_GPR_GPR74_DWP_MASK)
#define IOMUXC_GPR_GPR74_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_GPR_GPR74_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR74_DWP_LOCK_SHIFT)) & IOMUXC_GPR_GPR74_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR75 - GPR75 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK (0x1U)
#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT (0U)
/*! ADC1_STOP_ACK - ADC1 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_ADC1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK (0x2U)
#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT (1U)
/*! ADC2_STOP_ACK - ADC2 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_ADC2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ADC2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ADC2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK (0x4U)
#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT (2U)
/*! CAAM_STOP_ACK - CAAM stop acknowledge
*/
#define IOMUXC_GPR_GPR75_CAAM_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAAM_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAAM_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK (0x8U)
#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT (3U)
/*! CAN1_STOP_ACK - CAN1 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK (0x10U)
#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT (4U)
/*! CAN2_STOP_ACK - CAN2 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK (0x20U)
#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT (5U)
/*! CAN3_STOP_ACK - CAN3 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_CAN3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_CAN3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_CAN3_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK (0x40U)
#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT (6U)
/*! EDMA_STOP_ACK - EDMA stop acknowledge
*/
#define IOMUXC_GPR_GPR75_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK (0x80U)
#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT (7U)
/*! EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge
*/
#define IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_EDMA_LPSR_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK (0x100U)
#define IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT (8U)
/*! ENET_STOP_ACK - ENET stop acknowledge
*/
#define IOMUXC_GPR_GPR75_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK (0x200U)
#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT (9U)
/*! ENET1G_STOP_ACK - ENET1G stop acknowledge
*/
#define IOMUXC_GPR_GPR75_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_ENET1G_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK (0x400U)
#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT (10U)
/*! FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK (0x800U)
#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT (11U)
/*! FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_FLEXSPI2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK (0x1000U)
#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT (12U)
/*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK (0x2000U)
#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT (13U)
/*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK (0x4000U)
#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT (14U)
/*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C3_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK (0x8000U)
#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT (15U)
/*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C4_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK (0x10000U)
#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT (16U)
/*! LPI2C5_STOP_ACK - LPI2C5 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C5_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK (0x20000U)
#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT (17U)
/*! LPI2C6_STOP_ACK - LPI2C6 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPI2C6_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK (0x40000U)
#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT (18U)
/*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK (0x80000U)
#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT (19U)
/*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK (0x100000U)
#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT (20U)
/*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI3_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK (0x200000U)
#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT (21U)
/*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI4_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK (0x400000U)
#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT (22U)
/*! LPSPI5_STOP_ACK - LPSPI5 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI5_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK (0x800000U)
#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT (23U)
/*! LPSPI6_STOP_ACK - LPSPI6 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPSPI6_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK (0x1000000U)
#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT (24U)
/*! LPUART1_STOP_ACK - LPUART1 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK (0x2000000U)
#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT (25U)
/*! LPUART2_STOP_ACK - LPUART2 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK (0x4000000U)
#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT (26U)
/*! LPUART3_STOP_ACK - LPUART3 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART3_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK (0x8000000U)
#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT (27U)
/*! LPUART4_STOP_ACK - LPUART4 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART4_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK (0x10000000U)
#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT (28U)
/*! LPUART5_STOP_ACK - LPUART5 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART5_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK (0x20000000U)
#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT (29U)
/*! LPUART6_STOP_ACK - LPUART6 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART6_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK (0x40000000U)
#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT (30U)
/*! LPUART7_STOP_ACK - LPUART7 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART7_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK (0x80000000U)
#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT (31U)
/*! LPUART8_STOP_ACK - LPUART8 stop acknowledge
*/
#define IOMUXC_GPR_GPR75_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR75_LPUART8_STOP_ACK_MASK)
/*! @} */
/*! @name GPR76 - GPR76 General Purpose Register */
/*! @{ */
#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK (0x1U)
#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT (0U)
/*! LPUART9_STOP_ACK - LPUART9 stop acknowledge
*/
#define IOMUXC_GPR_GPR76_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART9_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK (0x2U)
#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT (1U)
/*! LPUART10_STOP_ACK - LPUART10 stop acknowledge
*/
#define IOMUXC_GPR_GPR76_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART10_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK (0x4U)
#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT (2U)
/*! LPUART11_STOP_ACK - LPUART11 stop acknowledge
*/
#define IOMUXC_GPR_GPR76_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART11_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK (0x8U)
#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT (3U)
/*! LPUART12_STOP_ACK - LPUART12 stop acknowledge
*/
#define IOMUXC_GPR_GPR76_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_LPUART12_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK (0x10U)
#define IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT (4U)
/*! MIC_STOP_ACK - MIC stop acknowledge
*/
#define IOMUXC_GPR_GPR76_MIC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_MIC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_MIC_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK (0x20U)
#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT (5U)
/*! PIT1_STOP_ACK - PIT1 stop acknowledge
*/
#define IOMUXC_GPR_GPR76_PIT1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK (0x40U)
#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT (6U)
/*! PIT2_STOP_ACK - PIT2 stop acknowledge
*/
#define IOMUXC_GPR_GPR76_PIT2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_PIT2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_PIT2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK (0x80U)
#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT (7U)
/*! SEMC_STOP_ACK - SEMC stop acknowledge
*/
#define IOMUXC_GPR_GPR76_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SEMC_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SEMC_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK (0x100U)
#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT (8U)
/*! SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge
*/
#define IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SNVS_HP_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK (0x200U)
#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT (9U)
/*! SAI1_STOP_ACK - SAI1 stop acknowledge
*/
#define IOMUXC_GPR_GPR76_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI1_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI1_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK (0x400U)
#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT (10U)
/*! SAI2_STOP_ACK - SAI2 stop acknowledge
*/
#define IOMUXC_GPR_GPR76_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI2_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI2_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK (0x800U)
#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT (11U)
/*! SAI3_STOP_ACK - SAI3 stop acknowledge
*/
#define IOMUXC_GPR_GPR76_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI3_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI3_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK (0x1000U)
#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT (12U)
/*! SAI4_STOP_ACK - SAI4 stop acknowledge
*/
#define IOMUXC_GPR_GPR76_SAI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_SAI4_STOP_ACK_SHIFT)) & IOMUXC_GPR_GPR76_SAI4_STOP_ACK_MASK)
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U)
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT (13U)
/*! FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain
*/
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_BUS_MASK)
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK (0x4000U)
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT (14U)
/*! FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain
*/
#define IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO1_STOP_ACK_PER_MASK)
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U)
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT (15U)
/*! FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain
*/
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_BUS_MASK)
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK (0x10000U)
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT (16U)
/*! FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain
*/
#define IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_GPR_GPR76_FLEXIO2_STOP_ACK_PER_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IOMUXC_GPR_Register_Masks */
/* IOMUXC_GPR - Peripheral instance base addresses */
/** Peripheral IOMUXC_GPR base address */
#define IOMUXC_GPR_BASE (0x400E4000u)
/** Peripheral IOMUXC_GPR base pointer */
#define IOMUXC_GPR ((IOMUXC_GPR_Type *)IOMUXC_GPR_BASE)
/** Array initializer of IOMUXC_GPR peripheral base addresses */
#define IOMUXC_GPR_BASE_ADDRS { IOMUXC_GPR_BASE }
/** Array initializer of IOMUXC_GPR peripheral base pointers */
#define IOMUXC_GPR_BASE_PTRS { IOMUXC_GPR }
/*!
* @}
*/ /* end of group IOMUXC_GPR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC_LPSR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_LPSR_Peripheral_Access_Layer IOMUXC_LPSR Peripheral Access Layer
* @{
*/
/** IOMUXC_LPSR - Register Layout Typedef */
typedef struct {
__IO uint32_t SW_MUX_CTL_PAD[16]; /**< SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register, array offset: 0x0, array step: 0x4 */
__IO uint32_t SW_PAD_CTL_PAD[16]; /**< SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register, array offset: 0x40, array step: 0x4 */
__IO uint32_t SELECT_INPUT[24]; /**< CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register, array offset: 0x80, array step: 0x4 */
} IOMUXC_LPSR_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC_LPSR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_LPSR_Register_Masks IOMUXC_LPSR Register Masks
* @{
*/
/*! @name SW_MUX_CTL_PAD - SW_MUX_CTL_PAD_GPIO_LPSR_00 SW MUX Control Register..SW_MUX_CTL_PAD_GPIO_LPSR_15 SW MUX Control Register */
/*! @{ */
#define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK (0xFU)
#define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b1010..Select mux mode: ALT10 mux port: GPIO12_IO10 of instance: GPIO12
* 0b0000..Select mux mode: ALT0 mux port: JTAG_MUX_TRSTB of instance: JTAG_MUX
* 0b0001..Select mux mode: ALT1 mux port: LPUART11_CTS_B of instance: LPUART11
* 0b0010..Select mux mode: ALT2 mux port: LPI2C6_SDA of instance: LPI2C6
* 0b0011..Select mux mode: ALT3 mux port: MIC_BITSTREAM1 of instance: MIC
* 0b0100..Select mux mode: ALT4 mux port: LPSPI6_SCK of instance: LPSPI6
* 0b0101..Select mux mode: ALT5 mux port: GPIO_MUX6_IO10 of instance: GPIO_MUX6
* 0b0110..Select mux mode: ALT6 mux port: LPI2C5_SCLS of instance: LPI2C5
* 0b0111..Select mux mode: ALT7 mux port: SAI4_TX_SYNC of instance: SAI4
* 0b1000..Select mux mode: ALT8 mux port: LPUART12_TXD of instance: LPUART12
*/
#define IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_MUX_MODE_MASK)
#define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK (0x10U)
#define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_LPSR_00
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_LPSR_SW_MUX_CTL_PAD_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_SHIFT)) & IOMUXC_LPSR_SW_MUX_CTL_PAD_SION_MASK)
/*! @} */
/* The count of IOMUXC_LPSR_SW_MUX_CTL_PAD */
#define IOMUXC_LPSR_SW_MUX_CTL_PAD_COUNT (16U)
/*! @name SW_PAD_CTL_PAD - SW_PAD_CTL_PAD_GPIO_LPSR_00 SW PAD Control Register..SW_PAD_CTL_PAD_GPIO_LPSR_15 SW PAD Control Register */
/*! @{ */
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK (0x1U)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_SRE_MASK)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK (0x2U)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DSE_MASK)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK (0x4U)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUE_MASK)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK (0x8U)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_PUS_MASK)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK (0x20U)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT (5U)
/*! ODE_LPSR - Open Drain LPSR Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_ODE_LPSR_MASK)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_MASK)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_SW_PAD_CTL_PAD_DWP_LOCK_MASK)
/*! @} */
/* The count of IOMUXC_LPSR_SW_PAD_CTL_PAD */
#define IOMUXC_LPSR_SW_PAD_CTL_PAD_COUNT (16U)
/*! @name SELECT_INPUT - CAN3_IPP_IND_CANRX_SELECT_INPUT DAISY Register..SAI4_IPP_IND_SAI_TXSYNC_SELECT_INPUT DAISY Register */
/*! @{ */
#define IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK (0x3U) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
#define IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT (0U)
/*! DAISY - Selecting Pads Involved in Daisy Chain.
* 0b00..Selecting Pad: GPIO_LPSR_00 for Mode: ALT6
* 0b01..Selecting Pad: GPIO_LPSR_06 for Mode: ALT3
* 0b10..Selecting Pad: GPIO_LPSR_10 for Mode: ALT8
*/
#define IOMUXC_LPSR_SELECT_INPUT_DAISY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_SELECT_INPUT_DAISY_SHIFT)) & IOMUXC_LPSR_SELECT_INPUT_DAISY_MASK) /* Merged from fields with different position or width, of widths (1, 2), largest definition used */
/*! @} */
/* The count of IOMUXC_LPSR_SELECT_INPUT */
#define IOMUXC_LPSR_SELECT_INPUT_COUNT (24U)
/*!
* @}
*/ /* end of group IOMUXC_LPSR_Register_Masks */
/* IOMUXC_LPSR - Peripheral instance base addresses */
/** Peripheral IOMUXC_LPSR base address */
#define IOMUXC_LPSR_BASE (0x40C08000u)
/** Peripheral IOMUXC_LPSR base pointer */
#define IOMUXC_LPSR ((IOMUXC_LPSR_Type *)IOMUXC_LPSR_BASE)
/** Array initializer of IOMUXC_LPSR peripheral base addresses */
#define IOMUXC_LPSR_BASE_ADDRS { IOMUXC_LPSR_BASE }
/** Array initializer of IOMUXC_LPSR peripheral base pointers */
#define IOMUXC_LPSR_BASE_PTRS { IOMUXC_LPSR }
/*!
* @}
*/ /* end of group IOMUXC_LPSR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC_LPSR_GPR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_LPSR_GPR_Peripheral_Access_Layer IOMUXC_LPSR_GPR Peripheral Access Layer
* @{
*/
/** IOMUXC_LPSR_GPR - Register Layout Typedef */
typedef struct {
__IO uint32_t GPR0; /**< GPR0 General Purpose Register, offset: 0x0 */
__IO uint32_t GPR1; /**< GPR1 General Purpose Register, offset: 0x4 */
__IO uint32_t GPR2; /**< GPR2 General Purpose Register, offset: 0x8 */
__IO uint32_t GPR3; /**< GPR3 General Purpose Register, offset: 0xC */
__IO uint32_t GPR4; /**< GPR4 General Purpose Register, offset: 0x10 */
__IO uint32_t GPR5; /**< GPR5 General Purpose Register, offset: 0x14 */
__IO uint32_t GPR6; /**< GPR6 General Purpose Register, offset: 0x18 */
__IO uint32_t GPR7; /**< GPR7 General Purpose Register, offset: 0x1C */
__IO uint32_t GPR8; /**< GPR8 General Purpose Register, offset: 0x20 */
__IO uint32_t GPR9; /**< GPR9 General Purpose Register, offset: 0x24 */
__IO uint32_t GPR10; /**< GPR10 General Purpose Register, offset: 0x28 */
__IO uint32_t GPR11; /**< GPR11 General Purpose Register, offset: 0x2C */
__IO uint32_t GPR12; /**< GPR12 General Purpose Register, offset: 0x30 */
__IO uint32_t GPR13; /**< GPR13 General Purpose Register, offset: 0x34 */
__IO uint32_t GPR14; /**< GPR14 General Purpose Register, offset: 0x38 */
__IO uint32_t GPR15; /**< GPR15 General Purpose Register, offset: 0x3C */
__IO uint32_t GPR16; /**< GPR16 General Purpose Register, offset: 0x40 */
__IO uint32_t GPR17; /**< GPR17 General Purpose Register, offset: 0x44 */
__IO uint32_t GPR18; /**< GPR18 General Purpose Register, offset: 0x48 */
__IO uint32_t GPR19; /**< GPR19 General Purpose Register, offset: 0x4C */
__IO uint32_t GPR20; /**< GPR20 General Purpose Register, offset: 0x50 */
__IO uint32_t GPR21; /**< GPR21 General Purpose Register, offset: 0x54 */
__IO uint32_t GPR22; /**< GPR22 General Purpose Register, offset: 0x58 */
__IO uint32_t GPR23; /**< GPR23 General Purpose Register, offset: 0x5C */
__IO uint32_t GPR24; /**< GPR24 General Purpose Register, offset: 0x60 */
__IO uint32_t GPR25; /**< GPR25 General Purpose Register, offset: 0x64 */
__IO uint32_t GPR26; /**< GPR26 General Purpose Register, offset: 0x68 */
uint8_t RESERVED_0[24];
__IO uint32_t GPR33; /**< GPR33 General Purpose Register, offset: 0x84 */
__IO uint32_t GPR34; /**< GPR34 General Purpose Register, offset: 0x88 */
__IO uint32_t GPR35; /**< GPR35 General Purpose Register, offset: 0x8C */
__IO uint32_t GPR36; /**< GPR36 General Purpose Register, offset: 0x90 */
__IO uint32_t GPR37; /**< GPR37 General Purpose Register, offset: 0x94 */
__IO uint32_t GPR38; /**< GPR38 General Purpose Register, offset: 0x98 */
__IO uint32_t GPR39; /**< GPR39 General Purpose Register, offset: 0x9C */
__I uint32_t GPR40; /**< GPR40 General Purpose Register, offset: 0xA0 */
__I uint32_t GPR41; /**< GPR41 General Purpose Register, offset: 0xA4 */
} IOMUXC_LPSR_GPR_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC_LPSR_GPR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_LPSR_GPR_Register_Masks IOMUXC_LPSR_GPR Register Masks
* @{
*/
/*! @name GPR0 - GPR0 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK (0xFFF8U)
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT (3U)
/*! CM4_INIT_VTOR_LOW - CM4 Vector table offset value lower bits out of reset
*/
#define IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_CM4_INIT_VTOR_LOW_MASK)
#define IOMUXC_LPSR_GPR_GPR0_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_GPR_GPR0_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_MASK)
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_GPR_GPR0_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR0_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR1 - GPR1 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK (0xFFFFU)
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT (0U)
/*! CM4_INIT_VTOR_HIGH - CM4 Vector table offset value higher bits out of reset
*/
#define IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_CM4_INIT_VTOR_HIGH_MASK)
#define IOMUXC_LPSR_GPR_GPR1_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_GPR_GPR1_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_MASK)
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_GPR_GPR1_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR1_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR2 - GPR2 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR2_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR2_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT (3U)
/*! APC_AC_R0_BOT - APC start address of memory region-0
*/
#define IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR2_APC_AC_R0_BOT_MASK)
/*! @} */
/*! @name GPR3 - GPR3 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR3_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR3_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT (3U)
/*! APC_AC_R0_TOP - APC end address of memory region-0
*/
#define IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR3_APC_AC_R0_TOP_MASK)
/*! @} */
/*! @name GPR4 - GPR4 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR4_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR4_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT (3U)
/*! APC_AC_R1_BOT - APC start address of memory region-1
*/
#define IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR4_APC_AC_R1_BOT_MASK)
/*! @} */
/*! @name GPR5 - GPR5 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR5_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR5_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT (3U)
/*! APC_AC_R1_TOP - APC end address of memory region-1
*/
#define IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR5_APC_AC_R1_TOP_MASK)
/*! @} */
/*! @name GPR6 - GPR6 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR6_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR6_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT (3U)
/*! APC_AC_R2_BOT - APC start address of memory region-2
*/
#define IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR6_APC_AC_R2_BOT_MASK)
/*! @} */
/*! @name GPR7 - GPR7 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR7_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR7_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT (3U)
/*! APC_AC_R2_TOP - APC end address of memory region-2
*/
#define IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR7_APC_AC_R2_TOP_MASK)
/*! @} */
/*! @name GPR8 - GPR8 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR8_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR8_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT (3U)
/*! APC_AC_R3_BOT - APC start address of memory region-3
*/
#define IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR8_APC_AC_R3_BOT_MASK)
/*! @} */
/*! @name GPR9 - GPR9 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR9_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR9_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT (3U)
/*! APC_AC_R3_TOP - APC end address of memory region-3
*/
#define IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR9_APC_AC_R3_TOP_MASK)
/*! @} */
/*! @name GPR10 - GPR10 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR10_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR10_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT (3U)
/*! APC_AC_R4_BOT - APC start address of memory region-4
*/
#define IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR10_APC_AC_R4_BOT_MASK)
/*! @} */
/*! @name GPR11 - GPR11 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR11_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR11_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT (3U)
/*! APC_AC_R4_TOP - APC end address of memory region-4
*/
#define IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR11_APC_AC_R4_TOP_MASK)
/*! @} */
/*! @name GPR12 - GPR12 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR12_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR12_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT (3U)
/*! APC_AC_R5_BOT - APC start address of memory region-5
*/
#define IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR12_APC_AC_R5_BOT_MASK)
/*! @} */
/*! @name GPR13 - GPR13 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR13_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR13_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT (3U)
/*! APC_AC_R5_TOP - APC end address of memory region-5
*/
#define IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR13_APC_AC_R5_TOP_MASK)
/*! @} */
/*! @name GPR14 - GPR14 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR14_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR14_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT (3U)
/*! APC_AC_R6_BOT - APC start address of memory region-6
*/
#define IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR14_APC_AC_R6_BOT_MASK)
/*! @} */
/*! @name GPR15 - GPR15 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR15_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR15_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT (3U)
/*! APC_AC_R6_TOP - APC end address of memory region-6
*/
#define IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR15_APC_AC_R6_TOP_MASK)
/*! @} */
/*! @name GPR16 - GPR16 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR16_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR16_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT (3U)
/*! APC_AC_R7_BOT - APC start address of memory region-7
*/
#define IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_SHIFT)) & IOMUXC_LPSR_GPR_GPR16_APC_AC_R7_BOT_MASK)
/*! @} */
/*! @name GPR17 - GPR17 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR17_LOCK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b1..Write access to bit 31:1 is blocked
* 0b0..Write access to bit 31:1 is not blocked
*/
#define IOMUXC_LPSR_GPR_GPR17_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_LOCK_MASK)
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK (0xFFFFFFF8U)
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT (3U)
/*! APC_AC_R7_TOP - APC end address of memory region-7
*/
#define IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_SHIFT)) & IOMUXC_LPSR_GPR_GPR17_APC_AC_R7_TOP_MASK)
/*! @} */
/*! @name GPR18 - GPR18 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT (4U)
/*! APC_R0_ENCRYPT_ENABLE - APC memory region-0 encryption enable
* 0b1..Encryption enabled
* 0b0..No effect
*/
#define IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_APC_R0_ENCRYPT_ENABLE_MASK)
#define IOMUXC_LPSR_GPR_GPR18_LOCK_MASK (0xFFFF0000U)
#define IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT (16U)
/*! LOCK - Lock the write to bit 15:0
*/
#define IOMUXC_LPSR_GPR_GPR18_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR18_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR18_LOCK_MASK)
/*! @} */
/*! @name GPR19 - GPR19 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT (4U)
/*! APC_R1_ENCRYPT_ENABLE - APC memory region-1 encryption enable
* 0b1..Encryption enabled
* 0b0..No effect
*/
#define IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_APC_R1_ENCRYPT_ENABLE_MASK)
#define IOMUXC_LPSR_GPR_GPR19_LOCK_MASK (0xFFFF0000U)
#define IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT (16U)
/*! LOCK - Lock the write to bit 15:0
*/
#define IOMUXC_LPSR_GPR_GPR19_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR19_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR19_LOCK_MASK)
/*! @} */
/*! @name GPR20 - GPR20 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT (4U)
/*! APC_R2_ENCRYPT_ENABLE - APC memory region-2 encryption enable
* 0b1..Encryption enabled
* 0b0..No effect
*/
#define IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_APC_R2_ENCRYPT_ENABLE_MASK)
#define IOMUXC_LPSR_GPR_GPR20_LOCK_MASK (0xFFFF0000U)
#define IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT (16U)
/*! LOCK - Lock the write to bit 15:0
*/
#define IOMUXC_LPSR_GPR_GPR20_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR20_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR20_LOCK_MASK)
/*! @} */
/*! @name GPR21 - GPR21 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT (4U)
/*! APC_R3_ENCRYPT_ENABLE - APC memory region-3 encryption enable
* 0b1..Encryption enabled
* 0b0..No effect
*/
#define IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_APC_R3_ENCRYPT_ENABLE_MASK)
#define IOMUXC_LPSR_GPR_GPR21_LOCK_MASK (0xFFFF0000U)
#define IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT (16U)
/*! LOCK - Lock the write to bit 15:0
*/
#define IOMUXC_LPSR_GPR_GPR21_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR21_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR21_LOCK_MASK)
/*! @} */
/*! @name GPR22 - GPR22 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT (4U)
/*! APC_R4_ENCRYPT_ENABLE - APC memory region-4 encryption enable
* 0b1..Encryption enabled
* 0b0..No effect
*/
#define IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_APC_R4_ENCRYPT_ENABLE_MASK)
#define IOMUXC_LPSR_GPR_GPR22_LOCK_MASK (0xFFFF0000U)
#define IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT (16U)
/*! LOCK - Lock the write to bit 15:0
*/
#define IOMUXC_LPSR_GPR_GPR22_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR22_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR22_LOCK_MASK)
/*! @} */
/*! @name GPR23 - GPR23 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT (4U)
/*! APC_R5_ENCRYPT_ENABLE - APC memory region-5 encryption enable
* 0b1..Encryption enabled
* 0b0..No effect
*/
#define IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_APC_R5_ENCRYPT_ENABLE_MASK)
#define IOMUXC_LPSR_GPR_GPR23_LOCK_MASK (0xFFFF0000U)
#define IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT (16U)
/*! LOCK - Lock the write to bit 15:0
*/
#define IOMUXC_LPSR_GPR_GPR23_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR23_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR23_LOCK_MASK)
/*! @} */
/*! @name GPR24 - GPR24 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT (4U)
/*! APC_R6_ENCRYPT_ENABLE - APC memory region-6 encryption enable
* 0b1..Encryption enabled
* 0b0..No effect
*/
#define IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_APC_R6_ENCRYPT_ENABLE_MASK)
#define IOMUXC_LPSR_GPR_GPR24_LOCK_MASK (0xFFFF0000U)
#define IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT (16U)
/*! LOCK - Lock the write to bit 15:0
*/
#define IOMUXC_LPSR_GPR_GPR24_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR24_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR24_LOCK_MASK)
/*! @} */
/*! @name GPR25 - GPR25 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT (4U)
/*! APC_R7_ENCRYPT_ENABLE - APC memory region-7 encryption enable
* 0b1..Encryption enabled
* 0b0..No effect
*/
#define IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_R7_ENCRYPT_ENABLE_MASK)
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK (0x20U)
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT (5U)
/*! APC_VALID - APC global enable bit
* 0b1..Enable encryption for GPRx[APC_x_ENCRYPT_ENABLE] (valid for GPR2-GPR25)
* 0b0..No effect
*/
#define IOMUXC_LPSR_GPR_GPR25_APC_VALID(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_APC_VALID_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_APC_VALID_MASK)
#define IOMUXC_LPSR_GPR_GPR25_LOCK_MASK (0xFFFF0000U)
#define IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT (16U)
/*! LOCK - Lock the write to bit 15:0
*/
#define IOMUXC_LPSR_GPR_GPR25_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR25_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR25_LOCK_MASK)
/*! @} */
/*! @name GPR26 - GPR26 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK (0x1FFFFFFU)
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT (0U)
/*! CM7_INIT_VTOR - Vector table offset register out of reset. See the ARM v7-M Architecture
* Reference Manual for more information about the vector table offset register (VTOR).
*/
#define IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_CM7_INIT_VTOR_MASK)
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK (0xE000000U)
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT (25U)
/*! FIELD_0 - General purpose bits
*/
#define IOMUXC_LPSR_GPR_GPR26_FIELD_0(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_FIELD_0_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_FIELD_0_MASK)
#define IOMUXC_LPSR_GPR_GPR26_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_GPR_GPR26_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_MASK)
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_GPR_GPR26_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR26_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR33 - GPR33 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT (0U)
/*! M4_NMI_CLEAR - Clear CM4 NMI holding register
*/
#define IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_M4_NMI_CLEAR_MASK)
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK (0x100U)
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT (8U)
/*! USBPHY1_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register
*/
#define IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY1_WAKEUP_IRQ_CLEAR_MASK)
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK (0x200U)
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT (9U)
/*! USBPHY2_WAKEUP_IRQ_CLEAR - Clear USBPHY1 wakeup interrupt holding register
*/
#define IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_USBPHY2_WAKEUP_IRQ_CLEAR_MASK)
#define IOMUXC_LPSR_GPR_GPR33_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_GPR_GPR33_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_MASK)
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_GPR_GPR33_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR33_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR34 - GPR34 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK (0x2U)
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT (1U)
/*! GPIO_LPSR_HIGH_RANGE - GPIO_LPSR IO bank supply voltage range selection
*/
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_HIGH_RANGE_MASK)
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK (0x4U)
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT (2U)
/*! GPIO_LPSR_LOW_RANGE - GPIO_LPSR IO bank supply voltage range selection
*/
#define IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_GPIO_LPSR_LOW_RANGE_MASK)
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK (0x8U)
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT (3U)
/*! M7_NMI_MASK - Mask CM7 NMI pin input
* 0b0..NMI input from IO to CM7 is not blocked
* 0b1..NMI input from IO to CM7 is blocked
*/
#define IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M7_NMI_MASK_MASK)
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT (4U)
/*! M4_NMI_MASK - Mask CM4 NMI pin input
* 0b0..NMI input from IO to CM4 is not blocked
* 0b1..NMI input from IO to CM4 is blocked
*/
#define IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_NMI_MASK_MASK)
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK (0x20U)
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT (5U)
/*! M4_GPC_SLEEP_SEL - CM4 sleep request selection
* 0b0..CM4 SLEEPDEEP is sent to GPC
* 0b1..CM4 SLEEPING is sent to GPC
*/
#define IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_M4_GPC_SLEEP_SEL_MASK)
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK (0x800U)
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT (11U)
/*! SEC_ERR_RESP - Security error response enable
* 0b0..OKEY response
* 0b1..SLVError (default)
*/
#define IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_SEC_ERR_RESP_MASK)
#define IOMUXC_LPSR_GPR_GPR34_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_GPR_GPR34_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_MASK)
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_GPR_GPR34_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR34_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR35 - GPR35 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT (0U)
/*! ADC1_IPG_DOZE - ADC1 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK (0x2U)
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT (1U)
/*! ADC1_STOP_REQ - ADC1 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK (0x4U)
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT (2U)
/*! ADC1_IPG_STOP_MODE - ADC1 stop mode selection. This bitfield cannot change when ADC1_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC1_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK (0x8U)
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT (3U)
/*! ADC2_IPG_DOZE - ADC2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT (4U)
/*! ADC2_STOP_REQ - ADC2 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK (0x20U)
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT (5U)
/*! ADC2_IPG_STOP_MODE - ADC2 stop mode selection. This bitfield cannot change when ADC2_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ADC2_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK (0x40U)
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT (6U)
/*! CAAM_IPG_DOZE - CAN3 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK (0x80U)
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT (7U)
/*! CAAM_STOP_REQ - CAAM stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAAM_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK (0x100U)
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT (8U)
/*! CAN1_IPG_DOZE - CAN1 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK (0x200U)
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT (9U)
/*! CAN1_STOP_REQ - CAN1 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN1_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK (0x400U)
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT (10U)
/*! CAN2_IPG_DOZE - CAN2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK (0x800U)
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT (11U)
/*! CAN2_STOP_REQ - CAN2 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN2_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK (0x1000U)
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT (12U)
/*! CAN3_IPG_DOZE - CAN3 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK (0x2000U)
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT (13U)
/*! CAN3_STOP_REQ - CAN3 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_CAN3_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK (0x8000U)
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT (15U)
/*! EDMA_STOP_REQ - EDMA stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK (0x10000U)
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT (16U)
/*! EDMA_LPSR_STOP_REQ - EDMA_LPSR stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_EDMA_LPSR_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK (0x20000U)
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT (17U)
/*! ENET_IPG_DOZE - ENET doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK (0x40000U)
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT (18U)
/*! ENET_STOP_REQ - ENET stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK (0x80000U)
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT (19U)
/*! ENET1G_IPG_DOZE - ENET1G doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK (0x100000U)
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT (20U)
/*! ENET1G_STOP_REQ - ENET1G stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_ENET1G_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK (0x200000U)
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT (21U)
/*! FLEXIO1_IPG_DOZE - FLEXIO2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO1_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK (0x400000U)
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT (22U)
/*! FLEXIO2_IPG_DOZE - FLEXIO2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXIO2_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK (0x800000U)
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT (23U)
/*! FLEXSPI1_IPG_DOZE - FLEXSPI1 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK (0x1000000U)
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT (24U)
/*! FLEXSPI1_STOP_REQ - FLEXSPI1 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI1_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK (0x2000000U)
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT (25U)
/*! FLEXSPI2_IPG_DOZE - FLEXSPI2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK (0x4000000U)
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT (26U)
/*! FLEXSPI2_STOP_REQ - FLEXSPI2 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_FLEXSPI2_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR35_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_GPR_GPR35_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_MASK)
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_GPR_GPR35_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR35_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR36 - GPR36 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT (0U)
/*! GPT1_IPG_DOZE - GPT1 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT1_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK (0x2U)
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT (1U)
/*! GPT2_IPG_DOZE - GPT2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT2_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK (0x4U)
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT (2U)
/*! GPT3_IPG_DOZE - GPT3 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT3_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK (0x8U)
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT (3U)
/*! GPT4_IPG_DOZE - GPT4 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT4_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT (4U)
/*! GPT5_IPG_DOZE - GPT5 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT5_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK (0x20U)
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT (5U)
/*! GPT6_IPG_DOZE - GPT6 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_GPT6_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK (0x40U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT (6U)
/*! LPI2C1_IPG_DOZE - LPI2C1 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK (0x80U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT (7U)
/*! LPI2C1_STOP_REQ - LPI2C1 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK (0x100U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT (8U)
/*! LPI2C1_IPG_STOP_MODE - LPI2C1 stop mode selection. This bitfield cannot change when LPI2C1_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C1_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK (0x200U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT (9U)
/*! LPI2C2_IPG_DOZE - LPI2C2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK (0x400U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT (10U)
/*! LPI2C2_STOP_REQ - LPI2C2 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK (0x800U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT (11U)
/*! LPI2C2_IPG_STOP_MODE - LPI2C2 stop mode selection. This bitfield cannot change when LPI2C2_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C2_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK (0x1000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT (12U)
/*! LPI2C3_IPG_DOZE - LPI2C3 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK (0x2000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT (13U)
/*! LPI2C3_STOP_REQ - LPI2C3 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK (0x4000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT (14U)
/*! LPI2C3_IPG_STOP_MODE - LPI2C3 stop mode selection. This bitfield cannot change when LPI2C3_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C3_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK (0x8000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT (15U)
/*! LPI2C4_IPG_DOZE - LPI2C4 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK (0x10000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT (16U)
/*! LPI2C4_STOP_REQ - LPI2C4 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK (0x20000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT (17U)
/*! LPI2C4_IPG_STOP_MODE - LPI2C4 stop mode selection. This bitfield cannot change when LPI2C4_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C4_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK (0x40000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT (18U)
/*! LPI2C5_IPG_DOZE - LPI2C5 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK (0x80000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT (19U)
/*! LPI2C5_STOP_REQ - LPI2C5 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK (0x100000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT (20U)
/*! LPI2C5_IPG_STOP_MODE - LPI2C5 stop mode selection. This bitfield cannot change when LPI2C5_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C5_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK (0x200000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT (21U)
/*! LPI2C6_IPG_DOZE - LPI2C6 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK (0x400000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT (22U)
/*! LPI2C6_STOP_REQ - LPI2C6 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK (0x800000U)
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT (23U)
/*! LPI2C6_IPG_STOP_MODE - LPI2C6 stop mode selection. This bitfield cannot change when LPI2C6_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPI2C6_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK (0x1000000U)
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT (24U)
/*! LPSPI1_IPG_DOZE - LPSPI1 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK (0x2000000U)
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT (25U)
/*! LPSPI1_STOP_REQ - LPSPI1 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK (0x4000000U)
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT (26U)
/*! LPSPI1_IPG_STOP_MODE - LPSPI1 stop mode selection. This bitfield cannot change when LPSPI1_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_LPSPI1_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR36_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_GPR_GPR36_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_MASK)
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_GPR_GPR36_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR36_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR37 - GPR37 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT (0U)
/*! LPSPI2_IPG_DOZE - LPSPI2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK (0x2U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT (1U)
/*! LPSPI2_STOP_REQ - LPSPI2 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK (0x4U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT (2U)
/*! LPSPI2_IPG_STOP_MODE - LPSPI2 stop mode selection. This bitfield cannot change when LPSPI2_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI2_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK (0x8U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT (3U)
/*! LPSPI3_IPG_DOZE - LPSPI3 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT (4U)
/*! LPSPI3_STOP_REQ - LPSPI3 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK (0x20U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT (5U)
/*! LPSPI3_IPG_STOP_MODE - LPSPI3 stop mode selection. This bitfield cannot change when LPSPI3_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI3_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK (0x40U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT (6U)
/*! LPSPI4_IPG_DOZE - LPSPI4 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK (0x80U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT (7U)
/*! LPSPI4_STOP_REQ - LPSPI4 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK (0x100U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT (8U)
/*! LPSPI4_IPG_STOP_MODE - LPSPI4 stop mode selection. This bitfield cannot change when LPSPI4_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI4_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK (0x200U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT (9U)
/*! LPSPI5_IPG_DOZE - LPSPI5 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK (0x400U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT (10U)
/*! LPSPI5_STOP_REQ - LPSPI5 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK (0x800U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT (11U)
/*! LPSPI5_IPG_STOP_MODE - LPSPI5 stop mode selection. This bitfield cannot change when LPSPI5_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI5_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK (0x1000U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT (12U)
/*! LPSPI6_IPG_DOZE - LPSPI6 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK (0x2000U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT (13U)
/*! LPSPI6_STOP_REQ - LPSPI6 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK (0x4000U)
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT (14U)
/*! LPSPI6_IPG_STOP_MODE - LPSPI6 stop mode selection. This bitfield cannot change when LPSPI6_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPSPI6_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK (0x8000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT (15U)
/*! LPUART1_IPG_DOZE - LPUART1 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK (0x10000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT (16U)
/*! LPUART1_STOP_REQ - LPUART1 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK (0x20000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT (17U)
/*! LPUART1_IPG_STOP_MODE - LPUART1 stop mode selection. This bitfield cannot change when LPUART1_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART1_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK (0x40000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT (18U)
/*! LPUART2_IPG_DOZE - LPUART2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK (0x80000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT (19U)
/*! LPUART2_STOP_REQ - LPUART2 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK (0x100000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT (20U)
/*! LPUART2_IPG_STOP_MODE - LPUART2 stop mode selection. This bitfield cannot change when LPUART2_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART2_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK (0x200000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT (21U)
/*! LPUART3_IPG_DOZE - LPUART3 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK (0x400000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT (22U)
/*! LPUART3_STOP_REQ - LPUART3 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK (0x800000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT (23U)
/*! LPUART3_IPG_STOP_MODE - LPUART3 stop mode selection. This bitfield cannot change when LPUART3_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART3_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK (0x1000000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT (24U)
/*! LPUART4_IPG_DOZE - LPUART4 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK (0x2000000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT (25U)
/*! LPUART4_STOP_REQ - LPUART4 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK (0x4000000U)
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT (26U)
/*! LPUART4_IPG_STOP_MODE - LPUART4 stop mode selection. This bitfield cannot change when LPUART4_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_LPUART4_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR37_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_GPR_GPR37_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_MASK)
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_GPR_GPR37_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR37_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR38 - GPR38 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT (0U)
/*! LPUART5_IPG_DOZE - LPUART5 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK (0x2U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT (1U)
/*! LPUART5_STOP_REQ - LPUART5 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK (0x4U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT (2U)
/*! LPUART5_IPG_STOP_MODE - LPUART5 stop mode selection. This bitfield cannot change when LPUART5_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART5_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK (0x8U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT (3U)
/*! LPUART6_IPG_DOZE - LPUART6 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT (4U)
/*! LPUART6_STOP_REQ - LPUART6 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK (0x20U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT (5U)
/*! LPUART6_IPG_STOP_MODE - LPUART6 stop mode selection. This bitfield cannot change when LPUART6_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART6_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK (0x40U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT (6U)
/*! LPUART7_IPG_DOZE - LPUART7 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK (0x80U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT (7U)
/*! LPUART7_STOP_REQ - LPUART7 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK (0x100U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT (8U)
/*! LPUART7_IPG_STOP_MODE - LPUART7 stop mode selection. This bitfield cannot change when LPUART7_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART7_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK (0x200U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT (9U)
/*! LPUART8_IPG_DOZE - LPUART8 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK (0x400U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT (10U)
/*! LPUART8_STOP_REQ - LPUART8 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK (0x800U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT (11U)
/*! LPUART8_IPG_STOP_MODE - LPUART8 stop mode selection. This bitfield cannot change when LPUART8_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART8_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK (0x1000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT (12U)
/*! LPUART9_IPG_DOZE - LPUART9 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK (0x2000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT (13U)
/*! LPUART9_STOP_REQ - LPUART9 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK (0x4000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT (14U)
/*! LPUART9_IPG_STOP_MODE - LPUART9 stop mode selection. This bitfield cannot change when LPUART9_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART9_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK (0x8000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT (15U)
/*! LPUART10_IPG_DOZE - LPUART10 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK (0x10000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT (16U)
/*! LPUART10_STOP_REQ - LPUART10 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK (0x20000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT (17U)
/*! LPUART10_IPG_STOP_MODE - LPUART10 stop mode selection. This bitfield cannot change when LPUART10_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART10_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK (0x40000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT (18U)
/*! LPUART11_IPG_DOZE - LPUART11 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK (0x80000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT (19U)
/*! LPUART11_STOP_REQ - LPUART11 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK (0x100000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT (20U)
/*! LPUART11_IPG_STOP_MODE - LPUART11 stop mode selection. This bitfield cannot change when LPUART11_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART11_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK (0x200000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT (21U)
/*! LPUART12_IPG_DOZE - LPUART12 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK (0x400000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT (22U)
/*! LPUART12_STOP_REQ - LPUART12 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK (0x800000U)
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT (23U)
/*! LPUART12_IPG_STOP_MODE - LPUART12 stop mode selection. This bitfield cannot change when LPUART12_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_LPUART12_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK (0x1000000U)
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT (24U)
/*! MIC_IPG_DOZE - MIC doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK (0x2000000U)
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT (25U)
/*! MIC_STOP_REQ - MIC stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK (0x4000000U)
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT (26U)
/*! MIC_IPG_STOP_MODE - MIC stop mode selection. This bitfield cannot change when MIC_STOP_REQ is asserted.
* 0b0..This module is functional in Stop Mode
* 0b1..This module is not functional in Stop Mode and the corresponding x_STOP_REQ field is set to '1'.
*/
#define IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_MIC_IPG_STOP_MODE_MASK)
#define IOMUXC_LPSR_GPR_GPR38_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_GPR_GPR38_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_MASK)
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_GPR_GPR38_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR38_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR39 - GPR39 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK (0x2U)
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT (1U)
/*! PIT1_STOP_REQ - PIT1 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT1_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK (0x4U)
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT (2U)
/*! PIT2_STOP_REQ - PIT2 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_PIT2_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK (0x8U)
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT (3U)
/*! SEMC_STOP_REQ - SEMC stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SEMC_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT (4U)
/*! SIM1_IPG_DOZE - SIM1 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM1_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK (0x20U)
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT (5U)
/*! SIM2_IPG_DOZE - SIM2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SIM2_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK (0x40U)
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT (6U)
/*! SNVS_HP_IPG_DOZE - SNVS_HP doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK (0x80U)
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT (7U)
/*! SNVS_HP_STOP_REQ - SNVS_HP stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SNVS_HP_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK (0x100U)
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT (8U)
/*! WDOG1_IPG_DOZE - WDOG1 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG1_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK (0x200U)
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT (9U)
/*! WDOG2_IPG_DOZE - WDOG2 doze mode
* 0b0..Not in doze mode
* 0b1..In doze mode
*/
#define IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_WDOG2_IPG_DOZE_MASK)
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK (0x400U)
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT (10U)
/*! SAI1_STOP_REQ - SAI1 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI1_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK (0x800U)
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT (11U)
/*! SAI2_STOP_REQ - SAI2 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI2_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK (0x1000U)
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT (12U)
/*! SAI3_STOP_REQ - SAI3 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI3_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK (0x2000U)
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT (13U)
/*! SAI4_STOP_REQ - SAI4 stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_SAI4_STOP_REQ_MASK)
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK (0x4000U)
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT (14U)
/*! FLEXIO1_STOP_REQ_BUS - FLEXIO1 bus clock domain stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_BUS_MASK)
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK (0x8000U)
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT (15U)
/*! FLEXIO1_STOP_REQ_PER - FLEXIO1 peripheral clock domain stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO1_STOP_REQ_PER_MASK)
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK (0x10000U)
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT (16U)
/*! FLEXIO2_STOP_REQ_BUS - FLEXIO2 bus clock domain stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_BUS_MASK)
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK (0x20000U)
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT (17U)
/*! FLEXIO2_STOP_REQ_PER - FLEXIO2 peripheral clock domain stop request
* 0b0..Stop request off
* 0b1..Stop request on
*/
#define IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_FLEXIO2_STOP_REQ_PER_MASK)
#define IOMUXC_LPSR_GPR_GPR39_DWP_MASK (0x30000000U)
#define IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_LPSR_GPR_GPR39_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_MASK)
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_LPSR_GPR_GPR39_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_SHIFT)) & IOMUXC_LPSR_GPR_GPR39_DWP_LOCK_MASK)
/*! @} */
/*! @name GPR40 - GPR40 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT (0U)
/*! ADC1_STOP_ACK - ADC1 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC1_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK (0x2U)
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT (1U)
/*! ADC2_STOP_ACK - ADC2 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ADC2_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK (0x4U)
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT (2U)
/*! CAAM_STOP_ACK - CAAM stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAAM_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK (0x8U)
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT (3U)
/*! CAN1_STOP_ACK - CAN1 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN1_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT (4U)
/*! CAN2_STOP_ACK - CAN2 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN2_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK (0x20U)
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT (5U)
/*! CAN3_STOP_ACK - CAN3 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_CAN3_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK (0x40U)
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT (6U)
/*! EDMA_STOP_ACK - EDMA stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK (0x80U)
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT (7U)
/*! EDMA_LPSR_STOP_ACK - EDMA_LPSR stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_EDMA_LPSR_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK (0x100U)
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT (8U)
/*! ENET_STOP_ACK - ENET stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK (0x200U)
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT (9U)
/*! ENET1G_STOP_ACK - ENET1G stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_ENET1G_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK (0x400U)
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT (10U)
/*! FLEXSPI1_STOP_ACK - FLEXSPI1 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI1_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK (0x800U)
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT (11U)
/*! FLEXSPI2_STOP_ACK - FLEXSPI2 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_FLEXSPI2_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK (0x1000U)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT (12U)
/*! LPI2C1_STOP_ACK - LPI2C1 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C1_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK (0x2000U)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT (13U)
/*! LPI2C2_STOP_ACK - LPI2C2 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C2_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK (0x4000U)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT (14U)
/*! LPI2C3_STOP_ACK - LPI2C3 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C3_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK (0x8000U)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT (15U)
/*! LPI2C4_STOP_ACK - LPI2C4 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C4_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK (0x10000U)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT (16U)
/*! LPI2C5_STOP_ACK - LPI2C5 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C5_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK (0x20000U)
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT (17U)
/*! LPI2C6_STOP_ACK - LPI2C6 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPI2C6_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK (0x40000U)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT (18U)
/*! LPSPI1_STOP_ACK - LPSPI1 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI1_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK (0x80000U)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT (19U)
/*! LPSPI2_STOP_ACK - LPSPI2 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI2_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK (0x100000U)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT (20U)
/*! LPSPI3_STOP_ACK - LPSPI3 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI3_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK (0x200000U)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT (21U)
/*! LPSPI4_STOP_ACK - LPSPI4 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI4_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK (0x400000U)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT (22U)
/*! LPSPI5_STOP_ACK - LPSPI5 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI5_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK (0x800000U)
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT (23U)
/*! LPSPI6_STOP_ACK - LPSPI6 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPSPI6_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK (0x1000000U)
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT (24U)
/*! LPUART1_STOP_ACK - LPUART1 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART1_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK (0x2000000U)
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT (25U)
/*! LPUART2_STOP_ACK - LPUART2 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART2_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK (0x4000000U)
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT (26U)
/*! LPUART3_STOP_ACK - LPUART3 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART3_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK (0x8000000U)
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT (27U)
/*! LPUART4_STOP_ACK - LPUART4 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART4_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK (0x10000000U)
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT (28U)
/*! LPUART5_STOP_ACK - LPUART5 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART5_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK (0x20000000U)
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT (29U)
/*! LPUART6_STOP_ACK - LPUART6 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART6_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK (0x40000000U)
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT (30U)
/*! LPUART7_STOP_ACK - LPUART7 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART7_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK (0x80000000U)
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT (31U)
/*! LPUART8_STOP_ACK - LPUART8 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR40_LPUART8_STOP_ACK_MASK)
/*! @} */
/*! @name GPR41 - GPR41 General Purpose Register */
/*! @{ */
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK (0x1U)
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT (0U)
/*! LPUART9_STOP_ACK - LPUART9 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART9_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK (0x2U)
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT (1U)
/*! LPUART10_STOP_ACK - LPUART10 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART10_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK (0x4U)
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT (2U)
/*! LPUART11_STOP_ACK - LPUART11 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART11_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK (0x8U)
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT (3U)
/*! LPUART12_STOP_ACK - LPUART12 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_LPUART12_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK (0x10U)
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT (4U)
/*! MIC_STOP_ACK - MIC stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_MIC_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK (0x20U)
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT (5U)
/*! PIT1_STOP_ACK - PIT1 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT1_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK (0x40U)
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT (6U)
/*! PIT2_STOP_ACK - PIT2 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_PIT2_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK (0x80U)
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT (7U)
/*! SEMC_STOP_ACK - SEMC stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SEMC_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK (0x100U)
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT (8U)
/*! SNVS_HP_STOP_ACK - SNVS_HP stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SNVS_HP_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK (0x200U)
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT (9U)
/*! SAI1_STOP_ACK - SAI1 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI1_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK (0x400U)
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT (10U)
/*! SAI2_STOP_ACK - SAI2 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI2_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK (0x800U)
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT (11U)
/*! SAI3_STOP_ACK - SAI3 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI3_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK (0x1000U)
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT (12U)
/*! SAI4_STOP_ACK - SAI4 stop acknowledge
*/
#define IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_SAI4_STOP_ACK_MASK)
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK (0x2000U)
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT (13U)
/*! FLEXIO1_STOP_ACK_BUS - FLEXIO1 stop acknowledge of bus clock domain
*/
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_BUS_MASK)
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK (0x4000U)
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT (14U)
/*! FLEXIO1_STOP_ACK_PER - FLEXIO1 stop acknowledge of peripheral clock domain
*/
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO1_STOP_ACK_PER_MASK)
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK (0x8000U)
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT (15U)
/*! FLEXIO2_STOP_ACK_BUS - FLEXIO2 stop acknowledge of bus clock domain
*/
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_BUS_MASK)
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK (0x10000U)
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT (16U)
/*! FLEXIO2_STOP_ACK_PER - FLEXIO2 stop acknowledge of peripheral clock domain
*/
#define IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_FLEXIO2_STOP_ACK_PER_MASK)
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK (0x1000000U)
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT (24U)
/*! ROM_READ_LOCKED - ROM read lock status bit
*/
#define IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_SHIFT)) & IOMUXC_LPSR_GPR_GPR41_ROM_READ_LOCKED_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IOMUXC_LPSR_GPR_Register_Masks */
/* IOMUXC_LPSR_GPR - Peripheral instance base addresses */
/** Peripheral IOMUXC_LPSR_GPR base address */
#define IOMUXC_LPSR_GPR_BASE (0x40C0C000u)
/** Peripheral IOMUXC_LPSR_GPR base pointer */
#define IOMUXC_LPSR_GPR ((IOMUXC_LPSR_GPR_Type *)IOMUXC_LPSR_GPR_BASE)
/** Array initializer of IOMUXC_LPSR_GPR peripheral base addresses */
#define IOMUXC_LPSR_GPR_BASE_ADDRS { IOMUXC_LPSR_GPR_BASE }
/** Array initializer of IOMUXC_LPSR_GPR peripheral base pointers */
#define IOMUXC_LPSR_GPR_BASE_PTRS { IOMUXC_LPSR_GPR }
/*!
* @}
*/ /* end of group IOMUXC_LPSR_GPR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC_SNVS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_SNVS_Peripheral_Access_Layer IOMUXC_SNVS Peripheral Access Layer
* @{
*/
/** IOMUXC_SNVS - Register Layout Typedef */
typedef struct {
__IO uint32_t SW_MUX_CTL_PAD_WAKEUP_DIG; /**< SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register, offset: 0x0 */
__IO uint32_t SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG; /**< SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register, offset: 0x4 */
__IO uint32_t SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG; /**< SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register, offset: 0x8 */
__IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG; /**< SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register, offset: 0xC */
__IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG; /**< SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register, offset: 0x10 */
__IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG; /**< SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register, offset: 0x14 */
__IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG; /**< SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register, offset: 0x18 */
__IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG; /**< SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register, offset: 0x1C */
__IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG; /**< SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register, offset: 0x20 */
__IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG; /**< SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register, offset: 0x24 */
__IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG; /**< SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register, offset: 0x28 */
__IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG; /**< SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register, offset: 0x2C */
__IO uint32_t SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG; /**< SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register, offset: 0x30 */
__IO uint32_t SW_PAD_CTL_PAD_TEST_MODE_DIG; /**< SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register, offset: 0x34 */
__IO uint32_t SW_PAD_CTL_PAD_POR_B_DIG; /**< SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register, offset: 0x38 */
__IO uint32_t SW_PAD_CTL_PAD_ONOFF_DIG; /**< SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register, offset: 0x3C */
__IO uint32_t SW_PAD_CTL_PAD_WAKEUP_DIG; /**< SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register, offset: 0x40 */
__IO uint32_t SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG; /**< SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register, offset: 0x44 */
__IO uint32_t SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG; /**< SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register, offset: 0x48 */
__IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG; /**< SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register, offset: 0x4C */
__IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG; /**< SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register, offset: 0x50 */
__IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG; /**< SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register, offset: 0x54 */
__IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG; /**< SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register, offset: 0x58 */
__IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG; /**< SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register, offset: 0x5C */
__IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG; /**< SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register, offset: 0x60 */
__IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG; /**< SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register, offset: 0x64 */
__IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG; /**< SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register, offset: 0x68 */
__IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG; /**< SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register, offset: 0x6C */
__IO uint32_t SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG; /**< SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register, offset: 0x70 */
} IOMUXC_SNVS_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC_SNVS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_SNVS_Register_Masks IOMUXC_SNVS Register Masks
* @{
*/
/*! @name SW_MUX_CTL_PAD_WAKEUP_DIG - SW_MUX_CTL_PAD_WAKEUP_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO00 of instance: GPIO13
* 0b111..Select mux mode: ALT7 mux port: NMI_GLUE_NMI of instance: NMI_GLUE
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad WAKEUP_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_WAKEUP_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG - SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_LP_PMIC_ON_REQ of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO01 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad PMIC_ON_REQ_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_ON_REQ_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG - SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: CCM_PMIC_VSTBY_REQ of instance: CCM
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO02 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad PMIC_STBY_REQ_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_PMIC_STBY_REQ_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER0 of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO03 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_SNVS_00_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_00_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER1 of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO04 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_SNVS_01_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_01_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER2 of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO05 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_SNVS_02_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_02_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER3 of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO06 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_SNVS_03_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_03_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER4 of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO07 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_SNVS_04_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_04_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER5 of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO08 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_SNVS_05_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_05_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER6 of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO09 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_SNVS_06_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_06_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER7 of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO10 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_SNVS_07_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_07_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER8 of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO11 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_SNVS_08_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_08_DIG_SION_MASK)
/*! @} */
/*! @name SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG - SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG SW MUX Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK (0x7U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT (0U)
/*! MUX_MODE - MUX Mode Select Field.
* 0b000..Select mux mode: ALT0 mux port: SNVS_TAMPER9 of instance: SNVS_LP
* 0b101..Select mux mode: ALT5 mux port: GPIO13_IO12 of instance: GPIO13
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_MUX_MODE_MASK)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK (0x10U)
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT (4U)
/*! SION - Software Input On Field.
* 0b1..Force input path of pad GPIO_SNVS_09_DIG
* 0b0..Input Path is determined by functionality
*/
#define IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_SHIFT)) & IOMUXC_SNVS_SW_MUX_CTL_PAD_GPIO_SNVS_09_DIG_SION_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_TEST_MODE_DIG - SW_PAD_CTL_PAD_TEST_MODE_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_TEST_MODE_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_POR_B_DIG - SW_PAD_CTL_PAD_POR_B_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_POR_B_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_ONOFF_DIG - SW_PAD_CTL_PAD_ONOFF_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_ONOFF_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_WAKEUP_DIG - SW_PAD_CTL_PAD_WAKEUP_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_WAKEUP_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG - SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_ON_REQ_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG - SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_PMIC_STBY_REQ_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_00_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_01_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_02_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_03_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_04_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_05_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_06_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_07_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_08_DIG_DWP_LOCK_MASK)
/*! @} */
/*! @name SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG - SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG SW PAD Control Register */
/*! @{ */
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK (0x1U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT (0U)
/*! SRE - Slew Rate Field
* 0b0..Slow Slew Rate
* 0b1..Fast Slew Rate
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_SRE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK (0x2U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT (1U)
/*! DSE - Drive Strength Field
* 0b0..normal driver
* 0b1..high driver
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DSE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK (0x4U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT (2U)
/*! PUE - Pull / Keep Select Field
* 0b0..Pull Disable
* 0b1..Pull Enable
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUE_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK (0x8U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT (3U)
/*! PUS - Pull Up / Down Config. Field
* 0b0..Weak pull down
* 0b1..Weak pull up
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_PUS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK (0x40U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT (6U)
/*! ODE_SNVS - Open Drain SNVS Field
* 0b0..Disabled
* 0b1..Enabled
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_ODE_SNVS_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK (0x30000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT (28U)
/*! DWP - Domain write protection
* 0b00..Both cores are allowed
* 0b01..CM7 is forbidden
* 0b10..CM4 is forbidden
* 0b11..Both cores are forbidden
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_MASK)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK (0xC0000000U)
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT (30U)
/*! DWP_LOCK - Domain write protection lock
* 0b00..Neither of DWP bits is locked
* 0b01..The lower DWP bit is locked
* 0b10..The higher DWP bit is locked
* 0b11..Both DWP bits are locked
*/
#define IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_SHIFT)) & IOMUXC_SNVS_SW_PAD_CTL_PAD_GPIO_SNVS_09_DIG_DWP_LOCK_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IOMUXC_SNVS_Register_Masks */
/* IOMUXC_SNVS - Peripheral instance base addresses */
/** Peripheral IOMUXC_SNVS base address */
#define IOMUXC_SNVS_BASE (0x40C94000u)
/** Peripheral IOMUXC_SNVS base pointer */
#define IOMUXC_SNVS ((IOMUXC_SNVS_Type *)IOMUXC_SNVS_BASE)
/** Array initializer of IOMUXC_SNVS peripheral base addresses */
#define IOMUXC_SNVS_BASE_ADDRS { IOMUXC_SNVS_BASE }
/** Array initializer of IOMUXC_SNVS peripheral base pointers */
#define IOMUXC_SNVS_BASE_PTRS { IOMUXC_SNVS }
/*!
* @}
*/ /* end of group IOMUXC_SNVS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IOMUXC_SNVS_GPR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_SNVS_GPR_Peripheral_Access_Layer IOMUXC_SNVS_GPR Peripheral Access Layer
* @{
*/
/** IOMUXC_SNVS_GPR - Register Layout Typedef */
typedef struct {
__IO uint32_t GPR[32]; /**< GPR0 General Purpose Register, array offset: 0x0, array step: 0x4 */
__IO uint32_t GPR32; /**< GPR32 General Purpose Register, offset: 0x80 */
__IO uint32_t GPR33; /**< GPR33 General Purpose Register, offset: 0x84 */
__IO uint32_t GPR34; /**< GPR34 General Purpose Register, offset: 0x88 */
__IO uint32_t GPR35; /**< GPR35 General Purpose Register, offset: 0x8C */
__IO uint32_t GPR36; /**< GPR36 General Purpose Register, offset: 0x90 */
__IO uint32_t GPR37; /**< GPR37 General Purpose Register, offset: 0x94 */
} IOMUXC_SNVS_GPR_Type;
/* ----------------------------------------------------------------------------
-- IOMUXC_SNVS_GPR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IOMUXC_SNVS_GPR_Register_Masks IOMUXC_SNVS_GPR Register Masks
* @{
*/
/*! @name GPR - GPR0 General Purpose Register */
/*! @{ */
#define IOMUXC_SNVS_GPR_GPR_GPR_MASK (0xFFFFFFFFU)
#define IOMUXC_SNVS_GPR_GPR_GPR_SHIFT (0U)
/*! GPR - General purpose bits
*/
#define IOMUXC_SNVS_GPR_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR_GPR_MASK)
/*! @} */
/* The count of IOMUXC_SNVS_GPR_GPR */
#define IOMUXC_SNVS_GPR_GPR_COUNT (32U)
/*! @name GPR32 - GPR32 General Purpose Register */
/*! @{ */
#define IOMUXC_SNVS_GPR_GPR32_GPR_MASK (0xFFFEU)
#define IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT (1U)
/*! GPR - General purpose bits
*/
#define IOMUXC_SNVS_GPR_GPR32_GPR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_GPR_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_GPR_MASK)
#define IOMUXC_SNVS_GPR_GPR32_LOCK_MASK (0xFFFF0000U)
#define IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT (16U)
/*! LOCK - Lock the write to bit 15:0
*/
#define IOMUXC_SNVS_GPR_GPR32_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR32_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR32_LOCK_MASK)
/*! @} */
/*! @name GPR33 - GPR33 General Purpose Register */
/*! @{ */
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK (0x2U)
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT (1U)
/*! DCDC_STATUS_CAPT_CLR - DCDC captured status clear
* 0b0..No change
* 0b1..Clear the 3 bits of DCDC captured status: DCDC_OVER_VOL, DCDC_OVER_CUR, and DCDC_IN_LOW_VOL
*/
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STATUS_CAPT_CLR_MASK)
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK (0x4U)
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT (2U)
/*! SNVS_BYPASS_EN - SNVS LDO_SNVS_ANA bypass enable
* 0b1..Enable bypass
* 0b0..Disable bypass
*/
#define IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_BYPASS_EN_MASK)
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK (0x10000U)
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT (16U)
/*! DCDC_IN_LOW_VOL - DCDC_IN low voltage detect
* 0b1..Voltage on DCDC_IN is lower than 2.6V
* 0b0..Voltage on DCDC_IN is higher than 2.6V
*/
#define IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_IN_LOW_VOL_MASK)
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK (0x20000U)
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT (17U)
/*! DCDC_OVER_CUR - DCDC output over current alert
* 0b1..Overcurrent on DCDC output
* 0b0..No Overcurrent on DCDC output
*/
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_CUR_MASK)
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK (0x40000U)
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT (18U)
/*! DCDC_OVER_VOL - DCDC output over voltage alert
* 0b1..Overvoltage on DCDC VDDLP0 or VDDLP8 output
* 0b0..No Overvoltage on DCDC VDDLP0 or VDDLP8 output
*/
#define IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_OVER_VOL_MASK)
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK (0x80000U)
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT (19U)
/*! DCDC_STS_DC_OK - DCDC status OK
* 0b0..DCDC is settling
* 0b1..DCDC already settled
*/
#define IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_DCDC_STS_DC_OK_MASK)
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK (0x100000U)
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT (20U)
/*! SNVS_XTAL_CLK_OK - 32K OSC ok flag
* 0b1..32K oscillator is stable into normal operation
* 0b0..32K oscillator is NOT stable into normal operation
*/
#define IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_SHIFT)) & IOMUXC_SNVS_GPR_GPR33_SNVS_XTAL_CLK_OK_MASK)
/*! @} */
/*! @name GPR34 - GPR34 General Purpose Register */
/*! @{ */
#define IOMUXC_SNVS_GPR_GPR34_LOCK_MASK (0x1U)
#define IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b0..Write access is not blocked
* 0b1..Write access is blocked
*/
#define IOMUXC_SNVS_GPR_GPR34_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_LOCK_MASK)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK (0x2U)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT (1U)
/*! SNVS_CORE_VOLT_DET_TRIM_SEL - SNVS core voltage detect trim select
* 0b0..The trimming codes are selected from eFuse
* 0b1..The trimming codes of core voltage detectors used to change the voltage falling trip point are selected from SNVS_CORE_VOLT_DET_TRIM
*/
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SEL_MASK)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK (0xCU)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT (2U)
/*! SNVS_CORE_VOLT_DET_TRIM - SNVS core voltage detect trim
*/
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CORE_VOLT_DET_TRIM_MASK)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK (0x80U)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT (7U)
/*! SNVS_CLK_DET_TRIM_SEL - SNVS clock detect trim select
* 0b0..The trimming codes are selected from eFuse
* 0b1..The trimming codes of clock detector used to change the boundary frequencies are selected from SNVS_CLK_DET_TRIM
*/
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SEL_MASK)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK (0xFF00U)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT (8U)
/*! SNVS_CLK_DET_TRIM - SNVS clock detect trim bits
*/
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_TRIM_MASK)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK (0x30000U)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT (16U)
/*! SNVS_CLK_DET_OFFSET_HIGH - SNVS clock detect offset of high boundary frequency
* 0b00..No change (Default)
* 0b01..Add +5 to the Trim
* 0b10..Add +10 to the trim
* 0b11..Add -5 to the Trim
*/
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_HIGH_MASK)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK (0xC0000U)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT (18U)
/*! SNVS_CLK_DET_OFFSET_LOW - SNVS clock detect offset of low boundary frequency
* 0b00..No change (Default)
* 0b01..Add +5 to the Trim
* 0b10..Add +10 to the trim
* 0b11..Add -5 to the Trim
*/
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CLK_DET_OFFSET_LOW_MASK)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK (0x800000U)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT (23U)
/*! SNVS_CAP_TRIM_SEL - SNVS OSC load capacitor trim select
* 0b0..The trimming codes are selected from eFuse
* 0b1..The trimming codes are used from SNVS_OSC_CAP_TRIM (osc32k's load capacitor)
*/
#define IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_CAP_TRIM_SEL_MASK)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK (0xF000000U)
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT (24U)
/*! SNVS_OSC_CAP_TRIM - SNVS OSC load capacitor trim
*/
#define IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR34_SNVS_OSC_CAP_TRIM_MASK)
/*! @} */
/*! @name GPR35 - GPR35 General Purpose Register */
/*! @{ */
#define IOMUXC_SNVS_GPR_GPR35_LOCK_MASK (0x1U)
#define IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b0..Write access is not blocked
* 0b1..Write access is blocked
*/
#define IOMUXC_SNVS_GPR_GPR35_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_LOCK_MASK)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK (0x8U)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT (3U)
/*! SNVS_VOLT_DET_TRIM_SEL - SNVS voltage detect trim select
* 0b0..The trimming codes are selected from eFuse
* 0b1..The trimming codes of voltage detectors to change the voltage boundaries in battery voltage detecting are selected from SNVS_VOLT_DET_TRIM
*/
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SEL_MASK)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK (0xFF0U)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT (4U)
/*! SNVS_VOLT_DET_TRIM - SNVS voltage detect trim
*/
#define IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_VOLT_DET_TRIM_MASK)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK (0x8000U)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT (15U)
/*! SNVS_TEMP_DET_TRIM_SEL - SNVS temperature detect trim select
* 0b0..The trimming codes are selected from eFuse
* 0b1..The trimming codes to define the temperature boundaries of temperature detector are selected from SNVS_TEMP_DET_TRIM
*/
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SEL_MASK)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK (0xFFF0000U)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT (16U)
/*! SNVS_TEMP_DET_TRIM - SNVS temperature detect trim
*/
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_TRIM_MASK)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK (0x30000000U)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT (28U)
/*! SNVS_TEMP_DET_OFFSET_HIGH - SNVS temperature detect offset of high temperature boundary
* 0b00..No change (Default)
* 0b01..Add +5 to the Trim
* 0b10..Add +10 to the trim
* 0b11..Add -5 to the Trim
*/
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_HIGH_MASK)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK (0xC0000000U)
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT (30U)
/*! SNVS_TEMP_DET_OFFSET_LOW - SNVS temperature detect offset of low temperature boundary
* 0b00..No change (Default)
* 0b01..Add +5 to the Trim
* 0b10..Add +10 to the trim
* 0b11..Add -5 to the Trim
*/
#define IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_SHIFT)) & IOMUXC_SNVS_GPR_GPR35_SNVS_TEMP_DET_OFFSET_LOW_MASK)
/*! @} */
/*! @name GPR36 - GPR36 General Purpose Register */
/*! @{ */
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK (0x800000U)
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT (23U)
/*! SNVSDIG_SNVS1P8_ISO_EN - SNVS RAM isolation enable bit
* 0b1..Enable the isolation to avoid extra leakage power before SNVS SRAM peripheral power or LDO_SNVS_DIG is switched off
* 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG and SNVS SRAM peripheral power is back)
*/
#define IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVSDIG_SNVS1P8_ISO_EN_MASK)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK (0x4000000U)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT (26U)
/*! SNVS_SRAM_SLEEP - SNVS SRAM power-down enable bit
* 0b0..Enable SRAM access (It should be cleared after LDO_SNVS_DIG is enabled)
* 0b1..SNVS SRAM can go in Shutdown/ Periphery Off Array On/ Periphery On Array Off mode. In addition, this bit
* ensures power-up without stuck-at /high DC current states and hence must be held to 1 during wake-up, so
* this bit is default high.
*/
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_SLEEP_MASK)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK (0x8000000U)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT (27U)
/*! SNVS_SRAM_STDBY - SNVS SRAM standby enable bit
* 0b1..SNVS SRAM enters low leakage state and large drivers are switched OFF
* 0b0..SNVS SRAM does not enter low leakage state
*/
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_STDBY_MASK)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK (0x10000000U)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT (28U)
/*! SNVS_SRAM_PSWLARGEMP_FORCE - SNVS SRAM large switch control bit for peripheral
* 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained)
* 0b0..Switch on SNVS SRAM power for peripheral
*/
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGEMP_FORCE_MASK)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK (0x20000000U)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT (29U)
/*! SNVS_SRAM_PSWLARGE - SNVS SRAM large switch control bit
* 0b1..Switch off SNVS SRAM power for peripheral and array
* 0b0..Switch on SNVS SRAM power for peripheral and array
*/
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWLARGE_MASK)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK (0x40000000U)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT (30U)
/*! SNVS_SRAM_PSWSMALLMP_FORCE - SNVS SRAM small switch control bit for peripheral
* 0b1..Switch off SNVS SRAM power for peripheral (SRAM array power is not impacted, and data can be retained)
* 0b0..Switch on SNVS SRAM power for peripheral
*/
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALLMP_FORCE_MASK)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK (0x80000000U)
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT (31U)
/*! SNVS_SRAM_PSWSMALL - SNVS SRAM small switch control bit
* 0b1..Switch off SNVS SRAM power for peripheral and array
* 0b0..Switch on SNVS SRAM power for peripheral and array
*/
#define IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_SHIFT)) & IOMUXC_SNVS_GPR_GPR36_SNVS_SRAM_PSWSMALL_MASK)
/*! @} */
/*! @name GPR37 - GPR37 General Purpose Register */
/*! @{ */
#define IOMUXC_SNVS_GPR_GPR37_LOCK_MASK (0x1U)
#define IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT (0U)
/*! LOCK - Lock the write to bit 31:1
* 0b0..Write access is not blocked
* 0b1..Write access is blocked
*/
#define IOMUXC_SNVS_GPR_GPR37_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_LOCK_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_LOCK_MASK)
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK (0x7FEU)
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT (1U)
/*! SNVS_TAMPER_PUE - SNVS tamper detect pin pull enable bit
*/
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUE_MASK)
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK (0x1FF800U)
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT (11U)
/*! SNVS_TAMPER_PUS - SNVS tamper detect pin pull selection bit
*/
#define IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS(x) (((uint32_t)(((uint32_t)(x)) << IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_SHIFT)) & IOMUXC_SNVS_GPR_GPR37_SNVS_TAMPER_PUS_MASK)
/*! @} */
/*!
* @}
*/ /* end of group IOMUXC_SNVS_GPR_Register_Masks */
/* IOMUXC_SNVS_GPR - Peripheral instance base addresses */
/** Peripheral IOMUXC_SNVS_GPR base address */
#define IOMUXC_SNVS_GPR_BASE (0x40C98000u)
/** Peripheral IOMUXC_SNVS_GPR base pointer */
#define IOMUXC_SNVS_GPR ((IOMUXC_SNVS_GPR_Type *)IOMUXC_SNVS_GPR_BASE)
/** Array initializer of IOMUXC_SNVS_GPR peripheral base addresses */
#define IOMUXC_SNVS_GPR_BASE_ADDRS { IOMUXC_SNVS_GPR_BASE }
/** Array initializer of IOMUXC_SNVS_GPR peripheral base pointers */
#define IOMUXC_SNVS_GPR_BASE_PTRS { IOMUXC_SNVS_GPR }
/*!
* @}
*/ /* end of group IOMUXC_SNVS_GPR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- IPS_DOMAIN Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup IPS_DOMAIN_Peripheral_Access_Layer IPS_DOMAIN Peripheral Access Layer
* @{
*/
/** IPS_DOMAIN - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x10 */
__IO uint32_t SLOT_CTRL; /**< Slot Control Register, array offset: 0x0, array step: 0x10 */
uint8_t RESERVED_0[12];
} SLOT_CTRL[38];
} IPS_DOMAIN_Type;
/* ----------------------------------------------------------------------------
-- IPS_DOMAIN Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup IPS_DOMAIN_Register_Masks IPS_DOMAIN Register Masks
* @{
*/
/*! @name SLOT_CTRL - Slot Control Register */
/*! @{ */
#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK (0xFU)
#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT (0U)
/*! LOCKED_DOMAIN_ID - Domain ID of the slot to be locked
*/
#define IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCKED_DOMAIN_ID_MASK)
#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK (0x8000U)
#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT (15U)
/*! DOMAIN_LOCK - Lock domain ID of this slot
* 0b0..Do not lock the domain ID
* 0b1..Lock the domain ID
*/
#define IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_DOMAIN_LOCK_MASK)
#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK (0x10000U)
#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT (16U)
/*! ALLOW_NONSECURE - Allow non-secure write access to this domain control register or domain register
* 0b0..Do not allow non-secure write access
* 0b1..Allow non-secure write access
*/
#define IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_NONSECURE_MASK)
#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK (0x20000U)
#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT (17U)
/*! ALLOW_USER - Allow user write access to this domain control register or domain register
* 0b0..Do not allow user write access
* 0b1..Allow user write access
*/
#define IPS_DOMAIN_SLOT_CTRL_ALLOW_USER(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_ALLOW_USER_MASK)
#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK (0x80000000U)
#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT (31U)
/*! LOCK_CONTROL - Lock control of this slot
* 0b0..Do not lock the control register of this slot
* 0b1..Lock the control register of this slot
*/
#define IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_SHIFT)) & IPS_DOMAIN_SLOT_CTRL_LOCK_CONTROL_MASK)
/*! @} */
/* The count of IPS_DOMAIN_SLOT_CTRL */
#define IPS_DOMAIN_SLOT_CTRL_COUNT (38U)
/*!
* @}
*/ /* end of group IPS_DOMAIN_Register_Masks */
/* IPS_DOMAIN - Peripheral instance base addresses */
/** Peripheral IPS_DOMAIN base address */
#define IPS_DOMAIN_BASE (0x40C87C00u)
/** Peripheral IPS_DOMAIN base pointer */
#define IPS_DOMAIN ((IPS_DOMAIN_Type *)IPS_DOMAIN_BASE)
/** Array initializer of IPS_DOMAIN peripheral base addresses */
#define IPS_DOMAIN_BASE_ADDRS { IPS_DOMAIN_BASE }
/** Array initializer of IPS_DOMAIN peripheral base pointers */
#define IPS_DOMAIN_BASE_PTRS { IPS_DOMAIN }
/*!
* @}
*/ /* end of group IPS_DOMAIN_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- KEY_MANAGER Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup KEY_MANAGER_Peripheral_Access_Layer KEY_MANAGER Peripheral Access Layer
* @{
*/
/** KEY_MANAGER - Register Layout Typedef */
typedef struct {
__IO uint32_t MASTER_KEY_CTRL; /**< CSR Master Key Control Register, offset: 0x0 */
uint8_t RESERVED_0[12];
__IO uint32_t OTFAD1_KEY_CTRL; /**< CSR OTFAD-1 Key Control, offset: 0x10 */
uint8_t RESERVED_1[4];
__IO uint32_t OTFAD2_KEY_CTRL; /**< CSR OTFAD-2 Key Control, offset: 0x18 */
uint8_t RESERVED_2[4];
__IO uint32_t IEE_KEY_CTRL; /**< CSR IEE Key Control, offset: 0x20 */
uint8_t RESERVED_3[12];
__IO uint32_t PUF_KEY_CTRL; /**< CSR PUF Key Control, offset: 0x30 */
uint8_t RESERVED_4[972];
__IO uint32_t SLOT0_CTRL; /**< Slot 0 Control, offset: 0x400 */
__IO uint32_t SLOT1_CTRL; /**< Slot1 Control, offset: 0x404 */
__IO uint32_t SLOT2_CTRL; /**< Slot2 Control, offset: 0x408 */
__IO uint32_t SLOT3_CTRL; /**< Slot3 Control, offset: 0x40C */
__IO uint32_t SLOT4_CTRL; /**< Slot 4 Control, offset: 0x410 */
} KEY_MANAGER_Type;
/* ----------------------------------------------------------------------------
-- KEY_MANAGER Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup KEY_MANAGER_Register_Masks KEY_MANAGER Register Masks
* @{
*/
/*! @name MASTER_KEY_CTRL - CSR Master Key Control Register */
/*! @{ */
#define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK (0x1U)
#define KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT (0U)
/*! SELECT - Key select for SNVS OTPMK. Default value comes from FUSE_MASTER_KEY_SEL.
* 0b0..select key from UDF
* 0b1..If LOCK = 1, select key from PUF, otherwise select key from fuse (bypass the fuse OTPMK to SNVS)
*/
#define KEY_MANAGER_MASTER_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_SELECT_MASK)
#define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK (0x10000U)
#define KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT (16U)
/*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_MASTER_KEY_SEL_LOCK.
* 0b0..not locked
* 0b1..locked
*/
#define KEY_MANAGER_MASTER_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_MASTER_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_MASTER_KEY_CTRL_LOCK_MASK)
/*! @} */
/*! @name OTFAD1_KEY_CTRL - CSR OTFAD-1 Key Control */
/*! @{ */
#define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK (0x1U)
#define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT (0U)
/*! SELECT - key select for OTFAD-1. Default value comes from FUSE_OTFAD1_KEY_SEL.
* 0b0..Select key from OCOTP USER_KEY5
* 0b1..If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5
*/
#define KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_SELECT_MASK)
#define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK (0x10000U)
#define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT (16U)
/*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_OTFAD1_KEY_SEL_LOCK.
* 0b0..not locked
* 0b1..locked
*/
#define KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD1_KEY_CTRL_LOCK_MASK)
/*! @} */
/*! @name OTFAD2_KEY_CTRL - CSR OTFAD-2 Key Control */
/*! @{ */
#define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK (0x1U)
#define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT (0U)
/*! SELECT - key select for OTFAD-2. Default value comes from FUSE_OTFAD1_KEY_SEL.
* 0b0..select key from OCOTP USER_KEY5
* 0b1..If PUF_KEY_CTRL[LOCK] is 1, select key from PUF, otherwise select key from OCOTP USER_KEY5
*/
#define KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_SELECT_MASK)
#define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK (0x10000U)
#define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT (16U)
/*! LOCK - lock this register, prevent from writing. Default value comes from FUSE_OTFAD2_KEY_SEL_LOCK.
* 0b0..not locked
* 0b1..locked
*/
#define KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_OTFAD2_KEY_CTRL_LOCK_MASK)
/*! @} */
/*! @name IEE_KEY_CTRL - CSR IEE Key Control */
/*! @{ */
#define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK (0x1U)
#define KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT (0U)
/*! RELOAD - Restart load key signal for IEE
* 0b0..Do nothing
* 0b1..Restart IEE key load flow
*/
#define KEY_MANAGER_IEE_KEY_CTRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_IEE_KEY_CTRL_RELOAD_SHIFT)) & KEY_MANAGER_IEE_KEY_CTRL_RELOAD_MASK)
/*! @} */
/*! @name PUF_KEY_CTRL - CSR PUF Key Control */
/*! @{ */
#define KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK (0x1U)
#define KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT (0U)
/*! LOCK - Lock signal for key select
* 0b0..Do not lock the key select
* 0b1..Lock the key select to select key from PUF, otherwise bypass key from OCOPT and do not lock. Once it has
* been set to 1, it cannot be reset manually. It will be set to 0 when the IEE key reload operation is done.
*/
#define KEY_MANAGER_PUF_KEY_CTRL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_PUF_KEY_CTRL_LOCK_SHIFT)) & KEY_MANAGER_PUF_KEY_CTRL_LOCK_MASK)
/*! @} */
/*! @name SLOT0_CTRL - Slot 0 Control */
/*! @{ */
#define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK (0xFU)
#define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT (0U)
/*! WHITE_LIST - Whitelist
*/
#define KEY_MANAGER_SLOT0_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_WHITE_LIST_MASK)
#define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK (0x8000U)
#define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT (15U)
/*! LOCK_LIST - Lock whitelist
* 0b0..Whitelist is not locked
* 0b1..Whitelist is locked
*/
#define KEY_MANAGER_SLOT0_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_LIST_MASK)
#define KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK (0x10000U)
#define KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT (16U)
/*! TZ_NS - Allow non-secure write access to this register and the slot it controls
* 0b0..Do not allow non-secure write access
* 0b1..Allow non-secure write access
*/
#define KEY_MANAGER_SLOT0_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_NS_MASK)
#define KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK (0x20000U)
#define KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT (17U)
/*! TZ_USER - Allow user write access to this register and the slot it controls
* 0b0..Do not allow user write access
* 0b1..Allow user write access
*/
#define KEY_MANAGER_SLOT0_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_TZ_USER_MASK)
#define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK (0x80000000U)
#define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT (31U)
/*! LOCK_CONTROL - Lock control of this slot
* 0b0..Do not lock the control register of this slot
* 0b1..Lock the control register of this slot
*/
#define KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT0_CTRL_LOCK_CONTROL_MASK)
/*! @} */
/*! @name SLOT1_CTRL - Slot1 Control */
/*! @{ */
#define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK (0xFU)
#define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT (0U)
/*! WHITE_LIST - Whitelist
*/
#define KEY_MANAGER_SLOT1_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_WHITE_LIST_MASK)
#define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK (0x8000U)
#define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT (15U)
/*! LOCK_LIST - Lock whitelist
* 0b0..Whitelist is not locked
* 0b1..Whitelist is locked
*/
#define KEY_MANAGER_SLOT1_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_LIST_MASK)
#define KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK (0x10000U)
#define KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT (16U)
/*! TZ_NS - Allow non-secure write access to this register and the slot it controls
* 0b0..Do not allow non-secure write access
* 0b1..Allow non-secure write access
*/
#define KEY_MANAGER_SLOT1_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_NS_MASK)
#define KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK (0x20000U)
#define KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT (17U)
/*! TZ_USER - Allow user write access to this register and the slot it controls
* 0b0..Do not allow user write access
* 0b1..Allow user write access
*/
#define KEY_MANAGER_SLOT1_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_TZ_USER_MASK)
#define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK (0x80000000U)
#define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT (31U)
/*! LOCK_CONTROL - Lock control of this slot
* 0b0..Do not lock the control register of this slot
* 0b1..Lock the control register of this slot
*/
#define KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT1_CTRL_LOCK_CONTROL_MASK)
/*! @} */
/*! @name SLOT2_CTRL - Slot2 Control */
/*! @{ */
#define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK (0xFU)
#define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT (0U)
/*! WHITE_LIST - Whitelist
*/
#define KEY_MANAGER_SLOT2_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_WHITE_LIST_MASK)
#define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK (0x8000U)
#define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT (15U)
/*! LOCK_LIST - Lock whitelist
* 0b0..Whitelist is not locked
* 0b1..Whitelist is locked
*/
#define KEY_MANAGER_SLOT2_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_LIST_MASK)
#define KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK (0x10000U)
#define KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT (16U)
/*! TZ_NS - Allow non-secure write access to this register and the slot it controls
* 0b0..Do not allow non-secure write access
* 0b1..Allow non-secure write access
*/
#define KEY_MANAGER_SLOT2_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_NS_MASK)
#define KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK (0x20000U)
#define KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT (17U)
/*! TZ_USER - Allow user write access to this register and the slot it controls
* 0b0..Do not allow user write access
* 0b1..Allow user write access
*/
#define KEY_MANAGER_SLOT2_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_TZ_USER_MASK)
#define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK (0x80000000U)
#define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT (31U)
/*! LOCK_CONTROL - Lock control of this slot
* 0b0..Do not lock the control register of this slot
* 0b1..Lock the control register of this slot
*/
#define KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT2_CTRL_LOCK_CONTROL_MASK)
/*! @} */
/*! @name SLOT3_CTRL - Slot3 Control */
/*! @{ */
#define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK (0xFU)
#define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT (0U)
/*! WHITE_LIST - Whitelist
*/
#define KEY_MANAGER_SLOT3_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_WHITE_LIST_MASK)
#define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK (0x8000U)
#define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT (15U)
/*! LOCK_LIST - Lock whitelist
* 0b0..Whitelist is not locked
* 0b1..Whitelist is locked
*/
#define KEY_MANAGER_SLOT3_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_LIST_MASK)
#define KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK (0x10000U)
#define KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT (16U)
/*! TZ_NS - Allow non-secure write access to this register and the slot it controls
* 0b0..Do not allow non-secure write access
* 0b1..Allow non-secure write access
*/
#define KEY_MANAGER_SLOT3_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_NS_MASK)
#define KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK (0x20000U)
#define KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT (17U)
/*! TZ_USER - Allow user write access to this register and the slot it controls
* 0b0..Do not allow user write access
* 0b1..Allow user write access
*/
#define KEY_MANAGER_SLOT3_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_TZ_USER_MASK)
#define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK (0x80000000U)
#define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT (31U)
/*! LOCK_CONTROL - Lock control of this slot
* 0b0..Do not lock the control register of this slot
* 0b1..Lock the control register of this slot
*/
#define KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT3_CTRL_LOCK_CONTROL_MASK)
/*! @} */
/*! @name SLOT4_CTRL - Slot 4 Control */
/*! @{ */
#define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK (0xFU)
#define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT (0U)
/*! WHITE_LIST - Whitelist
*/
#define KEY_MANAGER_SLOT4_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_WHITE_LIST_MASK)
#define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK (0x8000U)
#define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT (15U)
/*! LOCK_LIST - Lock whitelist
* 0b0..Whitelist is not locked
* 0b1..Whitelist is locked
*/
#define KEY_MANAGER_SLOT4_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_LIST_MASK)
#define KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK (0x10000U)
#define KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT (16U)
/*! TZ_NS - Allow non-secure write access to this register and the slot it controls
* 0b0..Do not allow non-secure write access
* 0b1..Allow non-secure write access
*/
#define KEY_MANAGER_SLOT4_CTRL_TZ_NS(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_NS_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_NS_MASK)
#define KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK (0x20000U)
#define KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT (17U)
/*! TZ_USER - Allow user write access to this register and the slot it controls
* 0b0..Do not allow user write access
* 0b1..Allow user write access
*/
#define KEY_MANAGER_SLOT4_CTRL_TZ_USER(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_TZ_USER_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_TZ_USER_MASK)
#define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK (0x80000000U)
#define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT (31U)
/*! LOCK_CONTROL - Lock control of this slot
* 0b0..Do not lock the control register of this slot
* 0b1..Lock the control register of this slot
*/
#define KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL(x) (((uint32_t)(((uint32_t)(x)) << KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_SHIFT)) & KEY_MANAGER_SLOT4_CTRL_LOCK_CONTROL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group KEY_MANAGER_Register_Masks */
/* KEY_MANAGER - Peripheral instance base addresses */
/** Peripheral KEY_MANAGER base address */
#define KEY_MANAGER_BASE (0x40C80000u)
/** Peripheral KEY_MANAGER base pointer */
#define KEY_MANAGER ((KEY_MANAGER_Type *)KEY_MANAGER_BASE)
/** Array initializer of KEY_MANAGER peripheral base addresses */
#define KEY_MANAGER_BASE_ADDRS { KEY_MANAGER_BASE }
/** Array initializer of KEY_MANAGER peripheral base pointers */
#define KEY_MANAGER_BASE_PTRS { KEY_MANAGER }
/*!
* @}
*/ /* end of group KEY_MANAGER_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- KPP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup KPP_Peripheral_Access_Layer KPP Peripheral Access Layer
* @{
*/
/** KPP - Register Layout Typedef */
typedef struct {
__IO uint16_t KPCR; /**< Keypad Control Register, offset: 0x0 */
__IO uint16_t KPSR; /**< Keypad Status Register, offset: 0x2 */
__IO uint16_t KDDR; /**< Keypad Data Direction Register, offset: 0x4 */
__IO uint16_t KPDR; /**< Keypad Data Register, offset: 0x6 */
} KPP_Type;
/* ----------------------------------------------------------------------------
-- KPP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup KPP_Register_Masks KPP Register Masks
* @{
*/
/*! @name KPCR - Keypad Control Register */
/*! @{ */
#define KPP_KPCR_KRE_MASK (0xFFU)
#define KPP_KPCR_KRE_SHIFT (0U)
/*! KRE - KRE
* 0b00000000..Row is not included in the keypad key press detect.
* 0b00000001..Row is included in the keypad key press detect.
*/
#define KPP_KPCR_KRE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KRE_SHIFT)) & KPP_KPCR_KRE_MASK)
#define KPP_KPCR_KCO_MASK (0xFF00U)
#define KPP_KPCR_KCO_SHIFT (8U)
/*! KCO - KCO
* 0b00000000..Column strobe output is totem pole drive.
* 0b00000001..Column strobe output is open drain.
*/
#define KPP_KPCR_KCO(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPCR_KCO_SHIFT)) & KPP_KPCR_KCO_MASK)
/*! @} */
/*! @name KPSR - Keypad Status Register */
/*! @{ */
#define KPP_KPSR_KPKD_MASK (0x1U)
#define KPP_KPSR_KPKD_SHIFT (0U)
/*! KPKD - KPKD
* 0b0..No key presses detected
* 0b1..A key has been depressed
*/
#define KPP_KPSR_KPKD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKD_SHIFT)) & KPP_KPSR_KPKD_MASK)
#define KPP_KPSR_KPKR_MASK (0x2U)
#define KPP_KPSR_KPKR_SHIFT (1U)
/*! KPKR - KPKR
* 0b0..No key release detected
* 0b1..All keys have been released
*/
#define KPP_KPSR_KPKR(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KPKR_SHIFT)) & KPP_KPSR_KPKR_MASK)
#define KPP_KPSR_KDSC_MASK (0x4U)
#define KPP_KPSR_KDSC_SHIFT (2U)
/*! KDSC - KDSC
* 0b0..No effect
* 0b1..Set bits that clear the keypad depress synchronizer chain
*/
#define KPP_KPSR_KDSC(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDSC_SHIFT)) & KPP_KPSR_KDSC_MASK)
#define KPP_KPSR_KRSS_MASK (0x8U)
#define KPP_KPSR_KRSS_SHIFT (3U)
/*! KRSS - KRSS
* 0b0..No effect
* 0b1..Set bits which sets keypad release synchronizer chain
*/
#define KPP_KPSR_KRSS(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRSS_SHIFT)) & KPP_KPSR_KRSS_MASK)
#define KPP_KPSR_KDIE_MASK (0x100U)
#define KPP_KPSR_KDIE_SHIFT (8U)
/*! KDIE - KDIE
* 0b0..No interrupt request is generated when KPKD is set.
* 0b1..An interrupt request is generated when KPKD is set.
*/
#define KPP_KPSR_KDIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KDIE_SHIFT)) & KPP_KPSR_KDIE_MASK)
#define KPP_KPSR_KRIE_MASK (0x200U)
#define KPP_KPSR_KRIE_SHIFT (9U)
/*! KRIE - KRIE
* 0b0..No interrupt request is generated when KPKR is set.
* 0b1..An interrupt request is generated when KPKR is set.
*/
#define KPP_KPSR_KRIE(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPSR_KRIE_SHIFT)) & KPP_KPSR_KRIE_MASK)
/*! @} */
/*! @name KDDR - Keypad Data Direction Register */
/*! @{ */
#define KPP_KDDR_KRDD_MASK (0xFFU)
#define KPP_KDDR_KRDD_SHIFT (0U)
/*! KRDD - KRDD
* 0b00000000..ROWn pin configured as an input.
* 0b00000001..ROWn pin configured as an output.
*/
#define KPP_KDDR_KRDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KRDD_SHIFT)) & KPP_KDDR_KRDD_MASK)
#define KPP_KDDR_KCDD_MASK (0xFF00U)
#define KPP_KDDR_KCDD_SHIFT (8U)
/*! KCDD - KCDD
* 0b00000000..COLn pin is configured as an input.
* 0b00000001..COLn pin is configured as an output.
*/
#define KPP_KDDR_KCDD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KDDR_KCDD_SHIFT)) & KPP_KDDR_KCDD_MASK)
/*! @} */
/*! @name KPDR - Keypad Data Register */
/*! @{ */
#define KPP_KPDR_KRD_MASK (0xFFU)
#define KPP_KPDR_KRD_SHIFT (0U)
/*! KRD - KRD
*/
#define KPP_KPDR_KRD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KRD_SHIFT)) & KPP_KPDR_KRD_MASK)
#define KPP_KPDR_KCD_MASK (0xFF00U)
#define KPP_KPDR_KCD_SHIFT (8U)
/*! KCD - KCD
*/
#define KPP_KPDR_KCD(x) (((uint16_t)(((uint16_t)(x)) << KPP_KPDR_KCD_SHIFT)) & KPP_KPDR_KCD_MASK)
/*! @} */
/*!
* @}
*/ /* end of group KPP_Register_Masks */
/* KPP - Peripheral instance base addresses */
/** Peripheral KPP base address */
#define KPP_BASE (0x400E0000u)
/** Peripheral KPP base pointer */
#define KPP ((KPP_Type *)KPP_BASE)
/** Array initializer of KPP peripheral base addresses */
#define KPP_BASE_ADDRS { KPP_BASE }
/** Array initializer of KPP peripheral base pointers */
#define KPP_BASE_PTRS { KPP }
/** Interrupt vectors for the KPP peripheral type */
#define KPP_IRQS { KPP_IRQn }
/*!
* @}
*/ /* end of group KPP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LCDIF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LCDIF_Peripheral_Access_Layer LCDIF Peripheral Access Layer
* @{
*/
/** LCDIF - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< LCDIF General Control Register, offset: 0x0 */
__IO uint32_t CTRL_SET; /**< LCDIF General Control Register, offset: 0x4 */
__IO uint32_t CTRL_CLR; /**< LCDIF General Control Register, offset: 0x8 */
__IO uint32_t CTRL_TOG; /**< LCDIF General Control Register, offset: 0xC */
__IO uint32_t CTRL1; /**< LCDIF General Control1 Register, offset: 0x10 */
__IO uint32_t CTRL1_SET; /**< LCDIF General Control1 Register, offset: 0x14 */
__IO uint32_t CTRL1_CLR; /**< LCDIF General Control1 Register, offset: 0x18 */
__IO uint32_t CTRL1_TOG; /**< LCDIF General Control1 Register, offset: 0x1C */
__IO uint32_t CTRL2; /**< LCDIF General Control2 Register, offset: 0x20 */
__IO uint32_t CTRL2_SET; /**< LCDIF General Control2 Register, offset: 0x24 */
__IO uint32_t CTRL2_CLR; /**< LCDIF General Control2 Register, offset: 0x28 */
__IO uint32_t CTRL2_TOG; /**< LCDIF General Control2 Register, offset: 0x2C */
__IO uint32_t TRANSFER_COUNT; /**< LCDIF Horizontal and Vertical Valid Data Count Register, offset: 0x30 */
uint8_t RESERVED_0[12];
__IO uint32_t CUR_BUF; /**< LCD Interface Current Buffer Address Register, offset: 0x40 */
uint8_t RESERVED_1[12];
__IO uint32_t NEXT_BUF; /**< LCD Interface Next Buffer Address Register, offset: 0x50 */
uint8_t RESERVED_2[28];
__IO uint32_t VDCTRL0; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x70 */
__IO uint32_t VDCTRL0_SET; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x74 */
__IO uint32_t VDCTRL0_CLR; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x78 */
__IO uint32_t VDCTRL0_TOG; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register0, offset: 0x7C */
__IO uint32_t VDCTRL1; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register1, offset: 0x80 */
uint8_t RESERVED_3[12];
__IO uint32_t VDCTRL2; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register2, offset: 0x90 */
uint8_t RESERVED_4[12];
__IO uint32_t VDCTRL3; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register3, offset: 0xA0 */
uint8_t RESERVED_5[12];
__IO uint32_t VDCTRL4; /**< LCDIF VSYNC Mode and Dotclk Mode Control Register4, offset: 0xB0 */
uint8_t RESERVED_6[220];
__IO uint32_t BM_ERROR_STAT; /**< Bus Master Error Status Register, offset: 0x190 */
uint8_t RESERVED_7[12];
__IO uint32_t CRC_STAT; /**< CRC Status Register, offset: 0x1A0 */
uint8_t RESERVED_8[12];
__I uint32_t STAT; /**< LCD Interface Status Register, offset: 0x1B0 */
uint8_t RESERVED_9[76];
__IO uint32_t THRES; /**< LCDIF Threshold Register, offset: 0x200 */
uint8_t RESERVED_10[380];
__IO uint32_t PIGEONCTRL0; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x380 */
__IO uint32_t PIGEONCTRL0_SET; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x384 */
__IO uint32_t PIGEONCTRL0_CLR; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x388 */
__IO uint32_t PIGEONCTRL0_TOG; /**< LCDIF Pigeon Mode Control0 Register, offset: 0x38C */
__IO uint32_t PIGEONCTRL1; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x390 */
__IO uint32_t PIGEONCTRL1_SET; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x394 */
__IO uint32_t PIGEONCTRL1_CLR; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x398 */
__IO uint32_t PIGEONCTRL1_TOG; /**< LCDIF Pigeon Mode Control1 Register, offset: 0x39C */
__IO uint32_t PIGEONCTRL2; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A0 */
__IO uint32_t PIGEONCTRL2_SET; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A4 */
__IO uint32_t PIGEONCTRL2_CLR; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3A8 */
__IO uint32_t PIGEONCTRL2_TOG; /**< LCDIF Pigeon Mode Control2 Register, offset: 0x3AC */
uint8_t RESERVED_11[1104];
struct { /* offset: 0x800, array step: 0x40 */
__IO uint32_t PIGEON_0; /**< Panel Interface Signal Generator Register, array offset: 0x800, array step: 0x40 */
uint8_t RESERVED_0[12];
__IO uint32_t PIGEON_1; /**< Panel Interface Signal Generator Register, array offset: 0x810, array step: 0x40 */
uint8_t RESERVED_1[12];
__IO uint32_t PIGEON_2; /**< Panel Interface Signal Generator Register, array offset: 0x820, array step: 0x40 */
uint8_t RESERVED_2[28];
} PIGEON[12];
__IO uint32_t LUT_CTRL; /**< Look Up Table Control Register, offset: 0xB00 */
uint8_t RESERVED_12[12];
__IO uint32_t LUT0_ADDR; /**< Lookup Table 0 Index Register, offset: 0xB10 */
uint8_t RESERVED_13[12];
__IO uint32_t LUT0_DATA; /**< Lookup Table 0 Data Register, offset: 0xB20 */
uint8_t RESERVED_14[12];
__IO uint32_t LUT1_ADDR; /**< Lookup Table 1 Index Register, offset: 0xB30 */
uint8_t RESERVED_15[12];
__IO uint32_t LUT1_DATA; /**< Lookup Table 1 Data Register, offset: 0xB40 */
} LCDIF_Type;
/* ----------------------------------------------------------------------------
-- LCDIF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LCDIF_Register_Masks LCDIF Register Masks
* @{
*/
/*! @name CTRL - LCDIF General Control Register */
/*! @{ */
#define LCDIF_CTRL_RUN_MASK (0x1U)
#define LCDIF_CTRL_RUN_SHIFT (0U)
#define LCDIF_CTRL_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RUN_SHIFT)) & LCDIF_CTRL_RUN_MASK)
#define LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK (0x2U)
#define LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT (1U)
/*! DATA_FORMAT_24_BIT
* 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
* 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
* each byte do not contain any useful data, and should be dropped.
*/
#define LCDIF_CTRL_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_24_BIT_MASK)
#define LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK (0x4U)
#define LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT (2U)
/*! DATA_FORMAT_18_BIT
* 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
* 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
*/
#define LCDIF_CTRL_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_18_BIT_MASK)
#define LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK (0x8U)
#define LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT (3U)
#define LCDIF_CTRL_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_DATA_FORMAT_16_BIT_MASK)
#define LCDIF_CTRL_RSRVD0_MASK (0x10U)
#define LCDIF_CTRL_RSRVD0_SHIFT (4U)
#define LCDIF_CTRL_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_RSRVD0_SHIFT)) & LCDIF_CTRL_RSRVD0_MASK)
#define LCDIF_CTRL_MASTER_MASK (0x20U)
#define LCDIF_CTRL_MASTER_SHIFT (5U)
#define LCDIF_CTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_MASTER_SHIFT)) & LCDIF_CTRL_MASTER_MASK)
#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define LCDIF_CTRL_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_ENABLE_PXP_HANDSHAKE_MASK)
#define LCDIF_CTRL_WORD_LENGTH_MASK (0x300U)
#define LCDIF_CTRL_WORD_LENGTH_SHIFT (8U)
/*! WORD_LENGTH
* 0b00..Input data is 16 bits per pixel.
* 0b01..Input data is 8 bits wide.
* 0b10..Input data is 18 bits per pixel.
* 0b11..Input data is 24 bits per pixel.
*/
#define LCDIF_CTRL_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_WORD_LENGTH_MASK)
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT (10U)
/*! LCD_DATABUS_WIDTH
* 0b00..16-bit data bus mode.
* 0b01..8-bit data bus mode.
* 0b10..18-bit data bus mode.
* 0b11..24-bit data bus mode.
*/
#define LCDIF_CTRL_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_LCD_DATABUS_WIDTH_MASK)
#define LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT (12U)
/*! CSC_DATA_SWIZZLE
* 0b00..No byte swapping.(Little endian)
* 0b00..Little Endian byte ordering (same as NO_SWAP).
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
* 0b10..Swap half-words.
* 0b11..Swap bytes within each half-word.
*/
#define LCDIF_CTRL_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CSC_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT (14U)
/*! INPUT_DATA_SWIZZLE
* 0b00..No byte swapping.(Little endian)
* 0b00..Little Endian byte ordering (same as NO_SWAP).
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
* 0b10..Swap half-words.
* 0b11..Swap bytes within each half-word.
*/
#define LCDIF_CTRL_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_INPUT_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_DOTCLK_MODE_MASK (0x20000U)
#define LCDIF_CTRL_DOTCLK_MODE_SHIFT (17U)
#define LCDIF_CTRL_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_DOTCLK_MODE_MASK)
#define LCDIF_CTRL_BYPASS_COUNT_MASK (0x80000U)
#define LCDIF_CTRL_BYPASS_COUNT_SHIFT (19U)
#define LCDIF_CTRL_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_BYPASS_COUNT_MASK)
#define LCDIF_CTRL_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT (21U)
#define LCDIF_CTRL_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SHIFT_NUM_BITS_MASK)
#define LCDIF_CTRL_DATA_SHIFT_DIR_MASK (0x4000000U)
#define LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT (26U)
/*! DATA_SHIFT_DIR
* 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
* 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
*/
#define LCDIF_CTRL_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_DATA_SHIFT_DIR_MASK)
#define LCDIF_CTRL_CLKGATE_MASK (0x40000000U)
#define LCDIF_CTRL_CLKGATE_SHIFT (30U)
#define LCDIF_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLKGATE_SHIFT)) & LCDIF_CTRL_CLKGATE_MASK)
#define LCDIF_CTRL_SFTRST_MASK (0x80000000U)
#define LCDIF_CTRL_SFTRST_SHIFT (31U)
#define LCDIF_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SFTRST_SHIFT)) & LCDIF_CTRL_SFTRST_MASK)
/*! @} */
/*! @name CTRL_SET - LCDIF General Control Register */
/*! @{ */
#define LCDIF_CTRL_SET_RUN_MASK (0x1U)
#define LCDIF_CTRL_SET_RUN_SHIFT (0U)
#define LCDIF_CTRL_SET_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RUN_SHIFT)) & LCDIF_CTRL_SET_RUN_MASK)
#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK (0x2U)
#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT (1U)
/*! DATA_FORMAT_24_BIT
* 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
* 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
* each byte do not contain any useful data, and should be dropped.
*/
#define LCDIF_CTRL_SET_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_24_BIT_MASK)
#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK (0x4U)
#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT (2U)
/*! DATA_FORMAT_18_BIT
* 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
* 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
*/
#define LCDIF_CTRL_SET_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_18_BIT_MASK)
#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK (0x8U)
#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT (3U)
#define LCDIF_CTRL_SET_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_SET_DATA_FORMAT_16_BIT_MASK)
#define LCDIF_CTRL_SET_RSRVD0_MASK (0x10U)
#define LCDIF_CTRL_SET_RSRVD0_SHIFT (4U)
#define LCDIF_CTRL_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_RSRVD0_SHIFT)) & LCDIF_CTRL_SET_RSRVD0_MASK)
#define LCDIF_CTRL_SET_MASTER_MASK (0x20U)
#define LCDIF_CTRL_SET_MASTER_SHIFT (5U)
#define LCDIF_CTRL_SET_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_MASTER_SHIFT)) & LCDIF_CTRL_SET_MASTER_MASK)
#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_SET_ENABLE_PXP_HANDSHAKE_MASK)
#define LCDIF_CTRL_SET_WORD_LENGTH_MASK (0x300U)
#define LCDIF_CTRL_SET_WORD_LENGTH_SHIFT (8U)
/*! WORD_LENGTH
* 0b00..Input data is 16 bits per pixel.
* 0b01..Input data is 8 bits wide.
* 0b10..Input data is 18 bits per pixel.
* 0b11..Input data is 24 bits per pixel.
*/
#define LCDIF_CTRL_SET_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_SET_WORD_LENGTH_MASK)
#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT (10U)
/*! LCD_DATABUS_WIDTH
* 0b00..16-bit data bus mode.
* 0b01..8-bit data bus mode.
* 0b10..18-bit data bus mode.
* 0b11..24-bit data bus mode.
*/
#define LCDIF_CTRL_SET_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_SET_LCD_DATABUS_WIDTH_MASK)
#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT (12U)
/*! CSC_DATA_SWIZZLE
* 0b00..No byte swapping.(Little endian)
* 0b00..Little Endian byte ordering (same as NO_SWAP).
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
* 0b10..Swap half-words.
* 0b11..Swap bytes within each half-word.
*/
#define LCDIF_CTRL_SET_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_CSC_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT (14U)
/*! INPUT_DATA_SWIZZLE
* 0b00..No byte swapping.(Little endian)
* 0b00..Little Endian byte ordering (same as NO_SWAP).
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
* 0b10..Swap half-words.
* 0b11..Swap bytes within each half-word.
*/
#define LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_SET_INPUT_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_SET_DOTCLK_MODE_MASK (0x20000U)
#define LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT (17U)
#define LCDIF_CTRL_SET_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_SET_DOTCLK_MODE_MASK)
#define LCDIF_CTRL_SET_BYPASS_COUNT_MASK (0x80000U)
#define LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT (19U)
#define LCDIF_CTRL_SET_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_SET_BYPASS_COUNT_MASK)
#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT (21U)
#define LCDIF_CTRL_SET_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_SET_SHIFT_NUM_BITS_MASK)
#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK (0x4000000U)
#define LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT (26U)
/*! DATA_SHIFT_DIR
* 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
* 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
*/
#define LCDIF_CTRL_SET_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_SET_DATA_SHIFT_DIR_MASK)
#define LCDIF_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define LCDIF_CTRL_SET_CLKGATE_SHIFT (30U)
#define LCDIF_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_CLKGATE_SHIFT)) & LCDIF_CTRL_SET_CLKGATE_MASK)
#define LCDIF_CTRL_SET_SFTRST_MASK (0x80000000U)
#define LCDIF_CTRL_SET_SFTRST_SHIFT (31U)
#define LCDIF_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_SET_SFTRST_SHIFT)) & LCDIF_CTRL_SET_SFTRST_MASK)
/*! @} */
/*! @name CTRL_CLR - LCDIF General Control Register */
/*! @{ */
#define LCDIF_CTRL_CLR_RUN_MASK (0x1U)
#define LCDIF_CTRL_CLR_RUN_SHIFT (0U)
#define LCDIF_CTRL_CLR_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RUN_SHIFT)) & LCDIF_CTRL_CLR_RUN_MASK)
#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK (0x2U)
#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT (1U)
/*! DATA_FORMAT_24_BIT
* 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
* 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
* each byte do not contain any useful data, and should be dropped.
*/
#define LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_24_BIT_MASK)
#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK (0x4U)
#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT (2U)
/*! DATA_FORMAT_18_BIT
* 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
* 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
*/
#define LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_18_BIT_MASK)
#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK (0x8U)
#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT (3U)
#define LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_CLR_DATA_FORMAT_16_BIT_MASK)
#define LCDIF_CTRL_CLR_RSRVD0_MASK (0x10U)
#define LCDIF_CTRL_CLR_RSRVD0_SHIFT (4U)
#define LCDIF_CTRL_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL_CLR_RSRVD0_MASK)
#define LCDIF_CTRL_CLR_MASTER_MASK (0x20U)
#define LCDIF_CTRL_CLR_MASTER_SHIFT (5U)
#define LCDIF_CTRL_CLR_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_MASTER_SHIFT)) & LCDIF_CTRL_CLR_MASTER_MASK)
#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_CLR_ENABLE_PXP_HANDSHAKE_MASK)
#define LCDIF_CTRL_CLR_WORD_LENGTH_MASK (0x300U)
#define LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT (8U)
/*! WORD_LENGTH
* 0b00..Input data is 16 bits per pixel.
* 0b01..Input data is 8 bits wide.
* 0b10..Input data is 18 bits per pixel.
* 0b11..Input data is 24 bits per pixel.
*/
#define LCDIF_CTRL_CLR_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_CLR_WORD_LENGTH_MASK)
#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT (10U)
/*! LCD_DATABUS_WIDTH
* 0b00..16-bit data bus mode.
* 0b01..8-bit data bus mode.
* 0b10..18-bit data bus mode.
* 0b11..24-bit data bus mode.
*/
#define LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_CLR_LCD_DATABUS_WIDTH_MASK)
#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT (12U)
/*! CSC_DATA_SWIZZLE
* 0b00..No byte swapping.(Little endian)
* 0b00..Little Endian byte ordering (same as NO_SWAP).
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
* 0b10..Swap half-words.
* 0b11..Swap bytes within each half-word.
*/
#define LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_CSC_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT (14U)
/*! INPUT_DATA_SWIZZLE
* 0b00..No byte swapping.(Little endian)
* 0b00..Little Endian byte ordering (same as NO_SWAP).
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
* 0b10..Swap half-words.
* 0b11..Swap bytes within each half-word.
*/
#define LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_CLR_INPUT_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_CLR_DOTCLK_MODE_MASK (0x20000U)
#define LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT (17U)
#define LCDIF_CTRL_CLR_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_CLR_DOTCLK_MODE_MASK)
#define LCDIF_CTRL_CLR_BYPASS_COUNT_MASK (0x80000U)
#define LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT (19U)
#define LCDIF_CTRL_CLR_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_CLR_BYPASS_COUNT_MASK)
#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT (21U)
#define LCDIF_CTRL_CLR_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_CLR_SHIFT_NUM_BITS_MASK)
#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK (0x4000000U)
#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT (26U)
/*! DATA_SHIFT_DIR
* 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
* 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
*/
#define LCDIF_CTRL_CLR_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_CLR_DATA_SHIFT_DIR_MASK)
#define LCDIF_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define LCDIF_CTRL_CLR_CLKGATE_SHIFT (30U)
#define LCDIF_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_CLKGATE_SHIFT)) & LCDIF_CTRL_CLR_CLKGATE_MASK)
#define LCDIF_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define LCDIF_CTRL_CLR_SFTRST_SHIFT (31U)
#define LCDIF_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_CLR_SFTRST_SHIFT)) & LCDIF_CTRL_CLR_SFTRST_MASK)
/*! @} */
/*! @name CTRL_TOG - LCDIF General Control Register */
/*! @{ */
#define LCDIF_CTRL_TOG_RUN_MASK (0x1U)
#define LCDIF_CTRL_TOG_RUN_SHIFT (0U)
#define LCDIF_CTRL_TOG_RUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RUN_SHIFT)) & LCDIF_CTRL_TOG_RUN_MASK)
#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK (0x2U)
#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT (1U)
/*! DATA_FORMAT_24_BIT
* 0b0..Data input to the block is in 24 bpp format, such that all RGB 888 data is contained in 24 bits.
* 0b1..Data input to the block is actually RGB 18 bpp, but there is 1 color per byte, hence the upper 2 bits in
* each byte do not contain any useful data, and should be dropped.
*/
#define LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_24_BIT_MASK)
#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK (0x4U)
#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT (2U)
/*! DATA_FORMAT_18_BIT
* 0b0..Data input to the block is in 18 bpp format, such that lower 18 bits contain RGB 666 and upper 14 bits do not contain any useful data.
* 0b1..Data input to the block is in 18 bpp format, such that upper 18 bits contain RGB 666 and lower 14 bits do not contain any useful data.
*/
#define LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_18_BIT_MASK)
#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK (0x8U)
#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT (3U)
#define LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_SHIFT)) & LCDIF_CTRL_TOG_DATA_FORMAT_16_BIT_MASK)
#define LCDIF_CTRL_TOG_RSRVD0_MASK (0x10U)
#define LCDIF_CTRL_TOG_RSRVD0_SHIFT (4U)
#define LCDIF_CTRL_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL_TOG_RSRVD0_MASK)
#define LCDIF_CTRL_TOG_MASTER_MASK (0x20U)
#define LCDIF_CTRL_TOG_MASTER_SHIFT (5U)
#define LCDIF_CTRL_TOG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_MASTER_SHIFT)) & LCDIF_CTRL_TOG_MASTER_MASK)
#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK (0x40U)
#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT (6U)
#define LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_SHIFT)) & LCDIF_CTRL_TOG_ENABLE_PXP_HANDSHAKE_MASK)
#define LCDIF_CTRL_TOG_WORD_LENGTH_MASK (0x300U)
#define LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT (8U)
/*! WORD_LENGTH
* 0b00..Input data is 16 bits per pixel.
* 0b01..Input data is 8 bits wide.
* 0b10..Input data is 18 bits per pixel.
* 0b11..Input data is 24 bits per pixel.
*/
#define LCDIF_CTRL_TOG_WORD_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_WORD_LENGTH_SHIFT)) & LCDIF_CTRL_TOG_WORD_LENGTH_MASK)
#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK (0xC00U)
#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT (10U)
/*! LCD_DATABUS_WIDTH
* 0b00..16-bit data bus mode.
* 0b01..8-bit data bus mode.
* 0b10..18-bit data bus mode.
* 0b11..24-bit data bus mode.
*/
#define LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_SHIFT)) & LCDIF_CTRL_TOG_LCD_DATABUS_WIDTH_MASK)
#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK (0x3000U)
#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT (12U)
/*! CSC_DATA_SWIZZLE
* 0b00..No byte swapping.(Little endian)
* 0b00..Little Endian byte ordering (same as NO_SWAP).
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
* 0b10..Swap half-words.
* 0b11..Swap bytes within each half-word.
*/
#define LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_CSC_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK (0xC000U)
#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT (14U)
/*! INPUT_DATA_SWIZZLE
* 0b00..No byte swapping.(Little endian)
* 0b00..Little Endian byte ordering (same as NO_SWAP).
* 0b01..Big Endian swap (swap bytes 0,3 and 1,2).
* 0b01..Swizzle all bytes, swap bytes 0,3 and 1,2 (aka Big Endian).
* 0b10..Swap half-words.
* 0b11..Swap bytes within each half-word.
*/
#define LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_SHIFT)) & LCDIF_CTRL_TOG_INPUT_DATA_SWIZZLE_MASK)
#define LCDIF_CTRL_TOG_DOTCLK_MODE_MASK (0x20000U)
#define LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT (17U)
#define LCDIF_CTRL_TOG_DOTCLK_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DOTCLK_MODE_SHIFT)) & LCDIF_CTRL_TOG_DOTCLK_MODE_MASK)
#define LCDIF_CTRL_TOG_BYPASS_COUNT_MASK (0x80000U)
#define LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT (19U)
#define LCDIF_CTRL_TOG_BYPASS_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_BYPASS_COUNT_SHIFT)) & LCDIF_CTRL_TOG_BYPASS_COUNT_MASK)
#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK (0x3E00000U)
#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT (21U)
#define LCDIF_CTRL_TOG_SHIFT_NUM_BITS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SHIFT_NUM_BITS_SHIFT)) & LCDIF_CTRL_TOG_SHIFT_NUM_BITS_MASK)
#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK (0x4000000U)
#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT (26U)
/*! DATA_SHIFT_DIR
* 0b0..Data to be transmitted is shifted LEFT by SHIFT_NUM_BITS bits.
* 0b1..Data to be transmitted is shifted RIGHT by SHIFT_NUM_BITS bits.
*/
#define LCDIF_CTRL_TOG_DATA_SHIFT_DIR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_DATA_SHIFT_DIR_SHIFT)) & LCDIF_CTRL_TOG_DATA_SHIFT_DIR_MASK)
#define LCDIF_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define LCDIF_CTRL_TOG_CLKGATE_SHIFT (30U)
#define LCDIF_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_CLKGATE_SHIFT)) & LCDIF_CTRL_TOG_CLKGATE_MASK)
#define LCDIF_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define LCDIF_CTRL_TOG_SFTRST_SHIFT (31U)
#define LCDIF_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL_TOG_SFTRST_SHIFT)) & LCDIF_CTRL_TOG_SFTRST_MASK)
/*! @} */
/*! @name CTRL1 - LCDIF General Control1 Register */
/*! @{ */
#define LCDIF_CTRL1_RSRVD0_MASK (0xF8U)
#define LCDIF_CTRL1_RSRVD0_SHIFT (3U)
#define LCDIF_CTRL1_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RSRVD0_SHIFT)) & LCDIF_CTRL1_RSRVD0_MASK)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK (0x100U)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT (8U)
/*! VSYNC_EDGE_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_MASK)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT (9U)
/*! CUR_FRAME_DONE_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_MASK)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_MASK (0x400U)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT (10U)
/*! UNDERFLOW_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_OVERFLOW_IRQ_MASK (0x800U)
#define LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT (11U)
/*! OVERFLOW_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_VSYNC_EDGE_IRQ_EN_MASK)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CUR_FRAME_DONE_IRQ_EN_MASK)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define LCDIF_CTRL1_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_UNDERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT (15U)
#define LCDIF_CTRL1_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_OVERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT (16U)
#define LCDIF_CTRL1_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_BYTE_PACKING_FORMAT_MASK)
#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define LCDIF_CTRL1_FIFO_CLEAR_MASK (0x200000U)
#define LCDIF_CTRL1_FIFO_CLEAR_SHIFT (21U)
#define LCDIF_CTRL1_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_FIFO_CLEAR_MASK)
#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define LCDIF_CTRL1_INTERLACE_FIELDS_MASK (0x800000U)
#define LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT (23U)
#define LCDIF_CTRL1_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_INTERLACE_FIELDS_MASK)
#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define LCDIF_CTRL1_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_RECOVER_ON_UNDERFLOW_MASK)
#define LCDIF_CTRL1_BM_ERROR_IRQ_MASK (0x2000000U)
#define LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT (25U)
/*! BM_ERROR_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_MASK)
#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT (26U)
#define LCDIF_CTRL1_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_BM_ERROR_IRQ_EN_MASK)
#define LCDIF_CTRL1_CS_OUT_SELECT_MASK (0x40000000U)
#define LCDIF_CTRL1_CS_OUT_SELECT_SHIFT (30U)
#define LCDIF_CTRL1_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CS_OUT_SELECT_MASK)
#define LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT (31U)
#define LCDIF_CTRL1_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_IMAGE_DATA_SELECT_MASK)
/*! @} */
/*! @name CTRL1_SET - LCDIF General Control1 Register */
/*! @{ */
#define LCDIF_CTRL1_SET_RSRVD0_MASK (0xF8U)
#define LCDIF_CTRL1_SET_RSRVD0_SHIFT (3U)
#define LCDIF_CTRL1_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RSRVD0_SHIFT)) & LCDIF_CTRL1_SET_RSRVD0_MASK)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK (0x100U)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT (8U)
/*! VSYNC_EDGE_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_MASK)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT (9U)
/*! CUR_FRAME_DONE_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_MASK)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK (0x400U)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT (10U)
/*! UNDERFLOW_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK (0x800U)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT (11U)
/*! OVERFLOW_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_VSYNC_EDGE_IRQ_EN_MASK)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_CUR_FRAME_DONE_IRQ_EN_MASK)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_UNDERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT (15U)
#define LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_OVERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT (16U)
#define LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_SET_BYTE_PACKING_FORMAT_MASK)
#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define LCDIF_CTRL1_SET_FIFO_CLEAR_MASK (0x200000U)
#define LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT (21U)
#define LCDIF_CTRL1_SET_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_SET_FIFO_CLEAR_MASK)
#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_SET_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK (0x800000U)
#define LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT (23U)
#define LCDIF_CTRL1_SET_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_SET_INTERLACE_FIELDS_MASK)
#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_SET_RECOVER_ON_UNDERFLOW_MASK)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK (0x2000000U)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT (25U)
/*! BM_ERROR_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_MASK)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT (26U)
#define LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_SET_BM_ERROR_IRQ_EN_MASK)
#define LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK (0x40000000U)
#define LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT (30U)
#define LCDIF_CTRL1_SET_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_SET_CS_OUT_SELECT_MASK)
#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT (31U)
#define LCDIF_CTRL1_SET_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_SET_IMAGE_DATA_SELECT_MASK)
/*! @} */
/*! @name CTRL1_CLR - LCDIF General Control1 Register */
/*! @{ */
#define LCDIF_CTRL1_CLR_RSRVD0_MASK (0xF8U)
#define LCDIF_CTRL1_CLR_RSRVD0_SHIFT (3U)
#define LCDIF_CTRL1_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL1_CLR_RSRVD0_MASK)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK (0x100U)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT (8U)
/*! VSYNC_EDGE_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_MASK)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT (9U)
/*! CUR_FRAME_DONE_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_MASK)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK (0x400U)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT (10U)
/*! UNDERFLOW_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK (0x800U)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT (11U)
/*! OVERFLOW_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_VSYNC_EDGE_IRQ_EN_MASK)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_CUR_FRAME_DONE_IRQ_EN_MASK)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_UNDERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT (15U)
#define LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_OVERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT (16U)
#define LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_CLR_BYTE_PACKING_FORMAT_MASK)
#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK (0x200000U)
#define LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT (21U)
#define LCDIF_CTRL1_CLR_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_CLR_FIFO_CLEAR_MASK)
#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_CLR_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK (0x800000U)
#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT (23U)
#define LCDIF_CTRL1_CLR_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_CLR_INTERLACE_FIELDS_MASK)
#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_CLR_RECOVER_ON_UNDERFLOW_MASK)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK (0x2000000U)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT (25U)
/*! BM_ERROR_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_MASK)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT (26U)
#define LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_CLR_BM_ERROR_IRQ_EN_MASK)
#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK (0x40000000U)
#define LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT (30U)
#define LCDIF_CTRL1_CLR_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_CS_OUT_SELECT_MASK)
#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT (31U)
#define LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_CLR_IMAGE_DATA_SELECT_MASK)
/*! @} */
/*! @name CTRL1_TOG - LCDIF General Control1 Register */
/*! @{ */
#define LCDIF_CTRL1_TOG_RSRVD0_MASK (0xF8U)
#define LCDIF_CTRL1_TOG_RSRVD0_SHIFT (3U)
#define LCDIF_CTRL1_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL1_TOG_RSRVD0_MASK)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK (0x100U)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT (8U)
/*! VSYNC_EDGE_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_MASK)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK (0x200U)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT (9U)
/*! CUR_FRAME_DONE_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_MASK)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK (0x400U)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT (10U)
/*! UNDERFLOW_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK (0x800U)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT (11U)
/*! OVERFLOW_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_MASK)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK (0x1000U)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT (12U)
#define LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_VSYNC_EDGE_IRQ_EN_MASK)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK (0x2000U)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT (13U)
#define LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_CUR_FRAME_DONE_IRQ_EN_MASK)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK (0x4000U)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT (14U)
#define LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_UNDERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK (0x8000U)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT (15U)
#define LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_OVERFLOW_IRQ_EN_MASK)
#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK (0xF0000U)
#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT (16U)
#define LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_SHIFT)) & LCDIF_CTRL1_TOG_BYTE_PACKING_FORMAT_MASK)
#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK (0x100000U)
#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT (20U)
#define LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_IRQ_ON_ALTERNATE_FIELDS_MASK)
#define LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK (0x200000U)
#define LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT (21U)
#define LCDIF_CTRL1_TOG_FIFO_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_FIFO_CLEAR_SHIFT)) & LCDIF_CTRL1_TOG_FIFO_CLEAR_MASK)
#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK (0x400000U)
#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT (22U)
#define LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_SHIFT)) & LCDIF_CTRL1_TOG_START_INTERLACE_FROM_SECOND_FIELD_MASK)
#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK (0x800000U)
#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT (23U)
#define LCDIF_CTRL1_TOG_INTERLACE_FIELDS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_INTERLACE_FIELDS_SHIFT)) & LCDIF_CTRL1_TOG_INTERLACE_FIELDS_MASK)
#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK (0x1000000U)
#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT (24U)
#define LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_SHIFT)) & LCDIF_CTRL1_TOG_RECOVER_ON_UNDERFLOW_MASK)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK (0x2000000U)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT (25U)
/*! BM_ERROR_IRQ
* 0b0..No Interrupt Request Pending.
* 0b1..Interrupt Request Pending.
*/
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_MASK)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK (0x4000000U)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT (26U)
#define LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_SHIFT)) & LCDIF_CTRL1_TOG_BM_ERROR_IRQ_EN_MASK)
#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK (0x40000000U)
#define LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT (30U)
#define LCDIF_CTRL1_TOG_CS_OUT_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_CS_OUT_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_CS_OUT_SELECT_MASK)
#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK (0x80000000U)
#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT (31U)
#define LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_SHIFT)) & LCDIF_CTRL1_TOG_IMAGE_DATA_SELECT_MASK)
/*! @} */
/*! @name CTRL2 - LCDIF General Control2 Register */
/*! @{ */
#define LCDIF_CTRL2_RSRVD0_MASK (0xFFFU)
#define LCDIF_CTRL2_RSRVD0_SHIFT (0U)
#define LCDIF_CTRL2_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD0_SHIFT)) & LCDIF_CTRL2_RSRVD0_MASK)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK (0x7000U)
#define LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT (12U)
/*! EVEN_LINE_PATTERN
* 0b000..RGB
* 0b001..RBG
* 0b010..GBR
* 0b011..GRB
* 0b100..BRG
* 0b101..BGR
*/
#define LCDIF_CTRL2_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_EVEN_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_RSRVD3_MASK (0x8000U)
#define LCDIF_CTRL2_RSRVD3_SHIFT (15U)
#define LCDIF_CTRL2_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD3_SHIFT)) & LCDIF_CTRL2_RSRVD3_MASK)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_MASK (0x70000U)
#define LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT (16U)
/*! ODD_LINE_PATTERN
* 0b000..RGB
* 0b001..RBG
* 0b010..GBR
* 0b011..GRB
* 0b100..BRG
* 0b101..BGR
*/
#define LCDIF_CTRL2_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_ODD_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_RSRVD4_MASK (0x80000U)
#define LCDIF_CTRL2_RSRVD4_SHIFT (19U)
#define LCDIF_CTRL2_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD4_SHIFT)) & LCDIF_CTRL2_RSRVD4_MASK)
#define LCDIF_CTRL2_BURST_LEN_8_MASK (0x100000U)
#define LCDIF_CTRL2_BURST_LEN_8_SHIFT (20U)
#define LCDIF_CTRL2_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_BURST_LEN_8_MASK)
#define LCDIF_CTRL2_OUTSTANDING_REQS_MASK (0xE00000U)
#define LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT (21U)
/*! OUTSTANDING_REQS
* 0b000..REQ_1
* 0b001..REQ_2
* 0b010..REQ_4
* 0b011..REQ_8
* 0b100..REQ_16
*/
#define LCDIF_CTRL2_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_OUTSTANDING_REQS_MASK)
#define LCDIF_CTRL2_RSRVD5_MASK (0xFF000000U)
#define LCDIF_CTRL2_RSRVD5_SHIFT (24U)
#define LCDIF_CTRL2_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_RSRVD5_SHIFT)) & LCDIF_CTRL2_RSRVD5_MASK)
/*! @} */
/*! @name CTRL2_SET - LCDIF General Control2 Register */
/*! @{ */
#define LCDIF_CTRL2_SET_RSRVD0_MASK (0xFFFU)
#define LCDIF_CTRL2_SET_RSRVD0_SHIFT (0U)
#define LCDIF_CTRL2_SET_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD0_SHIFT)) & LCDIF_CTRL2_SET_RSRVD0_MASK)
#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK (0x7000U)
#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT (12U)
/*! EVEN_LINE_PATTERN
* 0b000..RGB
* 0b001..RBG
* 0b010..GBR
* 0b011..GRB
* 0b100..BRG
* 0b101..BGR
*/
#define LCDIF_CTRL2_SET_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_EVEN_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_SET_RSRVD3_MASK (0x8000U)
#define LCDIF_CTRL2_SET_RSRVD3_SHIFT (15U)
#define LCDIF_CTRL2_SET_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD3_SHIFT)) & LCDIF_CTRL2_SET_RSRVD3_MASK)
#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK (0x70000U)
#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT (16U)
/*! ODD_LINE_PATTERN
* 0b000..RGB
* 0b001..RBG
* 0b010..GBR
* 0b011..GRB
* 0b100..BRG
* 0b101..BGR
*/
#define LCDIF_CTRL2_SET_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_SET_ODD_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_SET_RSRVD4_MASK (0x80000U)
#define LCDIF_CTRL2_SET_RSRVD4_SHIFT (19U)
#define LCDIF_CTRL2_SET_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD4_SHIFT)) & LCDIF_CTRL2_SET_RSRVD4_MASK)
#define LCDIF_CTRL2_SET_BURST_LEN_8_MASK (0x100000U)
#define LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT (20U)
#define LCDIF_CTRL2_SET_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_SET_BURST_LEN_8_MASK)
#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK (0xE00000U)
#define LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT (21U)
/*! OUTSTANDING_REQS
* 0b000..REQ_1
* 0b001..REQ_2
* 0b010..REQ_4
* 0b011..REQ_8
* 0b100..REQ_16
*/
#define LCDIF_CTRL2_SET_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_SET_OUTSTANDING_REQS_MASK)
#define LCDIF_CTRL2_SET_RSRVD5_MASK (0xFF000000U)
#define LCDIF_CTRL2_SET_RSRVD5_SHIFT (24U)
#define LCDIF_CTRL2_SET_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_SET_RSRVD5_SHIFT)) & LCDIF_CTRL2_SET_RSRVD5_MASK)
/*! @} */
/*! @name CTRL2_CLR - LCDIF General Control2 Register */
/*! @{ */
#define LCDIF_CTRL2_CLR_RSRVD0_MASK (0xFFFU)
#define LCDIF_CTRL2_CLR_RSRVD0_SHIFT (0U)
#define LCDIF_CTRL2_CLR_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD0_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD0_MASK)
#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK (0x7000U)
#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT (12U)
/*! EVEN_LINE_PATTERN
* 0b000..RGB
* 0b001..RBG
* 0b010..GBR
* 0b011..GRB
* 0b100..BRG
* 0b101..BGR
*/
#define LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_EVEN_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_CLR_RSRVD3_MASK (0x8000U)
#define LCDIF_CTRL2_CLR_RSRVD3_SHIFT (15U)
#define LCDIF_CTRL2_CLR_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD3_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD3_MASK)
#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK (0x70000U)
#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT (16U)
/*! ODD_LINE_PATTERN
* 0b000..RGB
* 0b001..RBG
* 0b010..GBR
* 0b011..GRB
* 0b100..BRG
* 0b101..BGR
*/
#define LCDIF_CTRL2_CLR_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_CLR_ODD_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_CLR_RSRVD4_MASK (0x80000U)
#define LCDIF_CTRL2_CLR_RSRVD4_SHIFT (19U)
#define LCDIF_CTRL2_CLR_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD4_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD4_MASK)
#define LCDIF_CTRL2_CLR_BURST_LEN_8_MASK (0x100000U)
#define LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT (20U)
#define LCDIF_CTRL2_CLR_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_CLR_BURST_LEN_8_MASK)
#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK (0xE00000U)
#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT (21U)
/*! OUTSTANDING_REQS
* 0b000..REQ_1
* 0b001..REQ_2
* 0b010..REQ_4
* 0b011..REQ_8
* 0b100..REQ_16
*/
#define LCDIF_CTRL2_CLR_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_CLR_OUTSTANDING_REQS_MASK)
#define LCDIF_CTRL2_CLR_RSRVD5_MASK (0xFF000000U)
#define LCDIF_CTRL2_CLR_RSRVD5_SHIFT (24U)
#define LCDIF_CTRL2_CLR_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_CLR_RSRVD5_SHIFT)) & LCDIF_CTRL2_CLR_RSRVD5_MASK)
/*! @} */
/*! @name CTRL2_TOG - LCDIF General Control2 Register */
/*! @{ */
#define LCDIF_CTRL2_TOG_RSRVD0_MASK (0xFFFU)
#define LCDIF_CTRL2_TOG_RSRVD0_SHIFT (0U)
#define LCDIF_CTRL2_TOG_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD0_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD0_MASK)
#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK (0x7000U)
#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT (12U)
/*! EVEN_LINE_PATTERN
* 0b000..RGB
* 0b001..RBG
* 0b010..GBR
* 0b011..GRB
* 0b100..BRG
* 0b101..BGR
*/
#define LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_EVEN_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_TOG_RSRVD3_MASK (0x8000U)
#define LCDIF_CTRL2_TOG_RSRVD3_SHIFT (15U)
#define LCDIF_CTRL2_TOG_RSRVD3(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD3_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD3_MASK)
#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK (0x70000U)
#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT (16U)
/*! ODD_LINE_PATTERN
* 0b000..RGB
* 0b001..RBG
* 0b010..GBR
* 0b011..GRB
* 0b100..BRG
* 0b101..BGR
*/
#define LCDIF_CTRL2_TOG_ODD_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_SHIFT)) & LCDIF_CTRL2_TOG_ODD_LINE_PATTERN_MASK)
#define LCDIF_CTRL2_TOG_RSRVD4_MASK (0x80000U)
#define LCDIF_CTRL2_TOG_RSRVD4_SHIFT (19U)
#define LCDIF_CTRL2_TOG_RSRVD4(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD4_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD4_MASK)
#define LCDIF_CTRL2_TOG_BURST_LEN_8_MASK (0x100000U)
#define LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT (20U)
#define LCDIF_CTRL2_TOG_BURST_LEN_8(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_BURST_LEN_8_SHIFT)) & LCDIF_CTRL2_TOG_BURST_LEN_8_MASK)
#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK (0xE00000U)
#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT (21U)
/*! OUTSTANDING_REQS
* 0b000..REQ_1
* 0b001..REQ_2
* 0b010..REQ_4
* 0b011..REQ_8
* 0b100..REQ_16
*/
#define LCDIF_CTRL2_TOG_OUTSTANDING_REQS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_OUTSTANDING_REQS_SHIFT)) & LCDIF_CTRL2_TOG_OUTSTANDING_REQS_MASK)
#define LCDIF_CTRL2_TOG_RSRVD5_MASK (0xFF000000U)
#define LCDIF_CTRL2_TOG_RSRVD5_SHIFT (24U)
#define LCDIF_CTRL2_TOG_RSRVD5(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CTRL2_TOG_RSRVD5_SHIFT)) & LCDIF_CTRL2_TOG_RSRVD5_MASK)
/*! @} */
/*! @name TRANSFER_COUNT - LCDIF Horizontal and Vertical Valid Data Count Register */
/*! @{ */
#define LCDIF_TRANSFER_COUNT_H_COUNT_MASK (0xFFFFU)
#define LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT (0U)
#define LCDIF_TRANSFER_COUNT_H_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_H_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_H_COUNT_MASK)
#define LCDIF_TRANSFER_COUNT_V_COUNT_MASK (0xFFFF0000U)
#define LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT (16U)
#define LCDIF_TRANSFER_COUNT_V_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_TRANSFER_COUNT_V_COUNT_SHIFT)) & LCDIF_TRANSFER_COUNT_V_COUNT_MASK)
/*! @} */
/*! @name CUR_BUF - LCD Interface Current Buffer Address Register */
/*! @{ */
#define LCDIF_CUR_BUF_ADDR_MASK (0xFFFFFFFFU)
#define LCDIF_CUR_BUF_ADDR_SHIFT (0U)
#define LCDIF_CUR_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CUR_BUF_ADDR_SHIFT)) & LCDIF_CUR_BUF_ADDR_MASK)
/*! @} */
/*! @name NEXT_BUF - LCD Interface Next Buffer Address Register */
/*! @{ */
#define LCDIF_NEXT_BUF_ADDR_MASK (0xFFFFFFFFU)
#define LCDIF_NEXT_BUF_ADDR_SHIFT (0U)
#define LCDIF_NEXT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_NEXT_BUF_ADDR_SHIFT)) & LCDIF_NEXT_BUF_ADDR_MASK)
/*! @} */
/*! @name VDCTRL0 - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
/*! @{ */
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_MASK)
#define LCDIF_VDCTRL0_HALF_LINE_MODE_MASK (0x40000U)
#define LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT (18U)
#define LCDIF_VDCTRL0_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MODE_MASK)
#define LCDIF_VDCTRL0_HALF_LINE_MASK (0x80000U)
#define LCDIF_VDCTRL0_HALF_LINE_SHIFT (19U)
#define LCDIF_VDCTRL0_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_HALF_LINE_MASK)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_VSYNC_PERIOD_UNIT_MASK)
#define LCDIF_VDCTRL0_RSRVD1_MASK (0xC00000U)
#define LCDIF_VDCTRL0_RSRVD1_SHIFT (22U)
#define LCDIF_VDCTRL0_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_RSRVD1_MASK)
#define LCDIF_VDCTRL0_ENABLE_POL_MASK (0x1000000U)
#define LCDIF_VDCTRL0_ENABLE_POL_SHIFT (24U)
#define LCDIF_VDCTRL0_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_ENABLE_POL_MASK)
#define LCDIF_VDCTRL0_DOTCLK_POL_MASK (0x2000000U)
#define LCDIF_VDCTRL0_DOTCLK_POL_SHIFT (25U)
#define LCDIF_VDCTRL0_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_DOTCLK_POL_MASK)
#define LCDIF_VDCTRL0_HSYNC_POL_MASK (0x4000000U)
#define LCDIF_VDCTRL0_HSYNC_POL_SHIFT (26U)
#define LCDIF_VDCTRL0_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_HSYNC_POL_MASK)
#define LCDIF_VDCTRL0_VSYNC_POL_MASK (0x8000000U)
#define LCDIF_VDCTRL0_VSYNC_POL_SHIFT (27U)
#define LCDIF_VDCTRL0_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_VSYNC_POL_MASK)
#define LCDIF_VDCTRL0_ENABLE_PRESENT_MASK (0x10000000U)
#define LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT (28U)
#define LCDIF_VDCTRL0_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_ENABLE_PRESENT_MASK)
#define LCDIF_VDCTRL0_VSYNC_OEB_MASK (0x20000000U)
#define LCDIF_VDCTRL0_VSYNC_OEB_SHIFT (29U)
/*! VSYNC_OEB
* 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
* 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
*/
#define LCDIF_VDCTRL0_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_VSYNC_OEB_MASK)
#define LCDIF_VDCTRL0_RSRVD2_MASK (0xC0000000U)
#define LCDIF_VDCTRL0_RSRVD2_SHIFT (30U)
#define LCDIF_VDCTRL0_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_RSRVD2_MASK)
/*! @} */
/*! @name VDCTRL0_SET - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
/*! @{ */
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_MASK)
#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK (0x40000U)
#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT (18U)
#define LCDIF_VDCTRL0_SET_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MODE_MASK)
#define LCDIF_VDCTRL0_SET_HALF_LINE_MASK (0x80000U)
#define LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT (19U)
#define LCDIF_VDCTRL0_SET_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_SET_HALF_LINE_MASK)
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_PERIOD_UNIT_MASK)
#define LCDIF_VDCTRL0_SET_RSRVD1_MASK (0xC00000U)
#define LCDIF_VDCTRL0_SET_RSRVD1_SHIFT (22U)
#define LCDIF_VDCTRL0_SET_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD1_MASK)
#define LCDIF_VDCTRL0_SET_ENABLE_POL_MASK (0x1000000U)
#define LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT (24U)
#define LCDIF_VDCTRL0_SET_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_POL_MASK)
#define LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK (0x2000000U)
#define LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT (25U)
#define LCDIF_VDCTRL0_SET_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_SET_DOTCLK_POL_MASK)
#define LCDIF_VDCTRL0_SET_HSYNC_POL_MASK (0x4000000U)
#define LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT (26U)
#define LCDIF_VDCTRL0_SET_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_HSYNC_POL_MASK)
#define LCDIF_VDCTRL0_SET_VSYNC_POL_MASK (0x8000000U)
#define LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT (27U)
#define LCDIF_VDCTRL0_SET_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_POL_MASK)
#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK (0x10000000U)
#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT (28U)
#define LCDIF_VDCTRL0_SET_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_SET_ENABLE_PRESENT_MASK)
#define LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK (0x20000000U)
#define LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT (29U)
/*! VSYNC_OEB
* 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
* 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
*/
#define LCDIF_VDCTRL0_SET_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_SET_VSYNC_OEB_MASK)
#define LCDIF_VDCTRL0_SET_RSRVD2_MASK (0xC0000000U)
#define LCDIF_VDCTRL0_SET_RSRVD2_SHIFT (30U)
#define LCDIF_VDCTRL0_SET_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_SET_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_SET_RSRVD2_MASK)
/*! @} */
/*! @name VDCTRL0_CLR - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
/*! @{ */
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_MASK)
#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK (0x40000U)
#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT (18U)
#define LCDIF_VDCTRL0_CLR_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MODE_MASK)
#define LCDIF_VDCTRL0_CLR_HALF_LINE_MASK (0x80000U)
#define LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT (19U)
#define LCDIF_VDCTRL0_CLR_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_CLR_HALF_LINE_MASK)
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_PERIOD_UNIT_MASK)
#define LCDIF_VDCTRL0_CLR_RSRVD1_MASK (0xC00000U)
#define LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT (22U)
#define LCDIF_VDCTRL0_CLR_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD1_MASK)
#define LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK (0x1000000U)
#define LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT (24U)
#define LCDIF_VDCTRL0_CLR_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_POL_MASK)
#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK (0x2000000U)
#define LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT (25U)
#define LCDIF_VDCTRL0_CLR_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_DOTCLK_POL_MASK)
#define LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK (0x4000000U)
#define LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT (26U)
#define LCDIF_VDCTRL0_CLR_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_HSYNC_POL_MASK)
#define LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK (0x8000000U)
#define LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT (27U)
#define LCDIF_VDCTRL0_CLR_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_POL_MASK)
#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK (0x10000000U)
#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT (28U)
#define LCDIF_VDCTRL0_CLR_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_CLR_ENABLE_PRESENT_MASK)
#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK (0x20000000U)
#define LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT (29U)
/*! VSYNC_OEB
* 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
* 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
*/
#define LCDIF_VDCTRL0_CLR_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_CLR_VSYNC_OEB_MASK)
#define LCDIF_VDCTRL0_CLR_RSRVD2_MASK (0xC0000000U)
#define LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT (30U)
#define LCDIF_VDCTRL0_CLR_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_CLR_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_CLR_RSRVD2_MASK)
/*! @} */
/*! @name VDCTRL0_TOG - LCDIF VSYNC Mode and Dotclk Mode Control Register0 */
/*! @{ */
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK (0x3FFFFU)
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT (0U)
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_MASK)
#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK (0x40000U)
#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT (18U)
#define LCDIF_VDCTRL0_TOG_HALF_LINE_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MODE_MASK)
#define LCDIF_VDCTRL0_TOG_HALF_LINE_MASK (0x80000U)
#define LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT (19U)
#define LCDIF_VDCTRL0_TOG_HALF_LINE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HALF_LINE_SHIFT)) & LCDIF_VDCTRL0_TOG_HALF_LINE_MASK)
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK (0x100000U)
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT (20U)
#define LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PULSE_WIDTH_UNIT_MASK)
#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK (0x200000U)
#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT (21U)
#define LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_PERIOD_UNIT_MASK)
#define LCDIF_VDCTRL0_TOG_RSRVD1_MASK (0xC00000U)
#define LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT (22U)
#define LCDIF_VDCTRL0_TOG_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD1_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD1_MASK)
#define LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK (0x1000000U)
#define LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT (24U)
#define LCDIF_VDCTRL0_TOG_ENABLE_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_POL_MASK)
#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK (0x2000000U)
#define LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT (25U)
#define LCDIF_VDCTRL0_TOG_DOTCLK_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_DOTCLK_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_DOTCLK_POL_MASK)
#define LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK (0x4000000U)
#define LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT (26U)
#define LCDIF_VDCTRL0_TOG_HSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_HSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_HSYNC_POL_MASK)
#define LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK (0x8000000U)
#define LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT (27U)
#define LCDIF_VDCTRL0_TOG_VSYNC_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_POL_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_POL_MASK)
#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK (0x10000000U)
#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT (28U)
#define LCDIF_VDCTRL0_TOG_ENABLE_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_SHIFT)) & LCDIF_VDCTRL0_TOG_ENABLE_PRESENT_MASK)
#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK (0x20000000U)
#define LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT (29U)
/*! VSYNC_OEB
* 0b0..The VSYNC pin is in the output mode and the VSYNC signal has to be generated by the LCDIF block.
* 0b1..The VSYNC pin is in the input mode and the LCD controller sends the VSYNC signal to the block.
*/
#define LCDIF_VDCTRL0_TOG_VSYNC_OEB(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_VSYNC_OEB_SHIFT)) & LCDIF_VDCTRL0_TOG_VSYNC_OEB_MASK)
#define LCDIF_VDCTRL0_TOG_RSRVD2_MASK (0xC0000000U)
#define LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT (30U)
#define LCDIF_VDCTRL0_TOG_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL0_TOG_RSRVD2_SHIFT)) & LCDIF_VDCTRL0_TOG_RSRVD2_MASK)
/*! @} */
/*! @name VDCTRL1 - LCDIF VSYNC Mode and Dotclk Mode Control Register1 */
/*! @{ */
#define LCDIF_VDCTRL1_VSYNC_PERIOD_MASK (0xFFFFFFFFU)
#define LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT (0U)
#define LCDIF_VDCTRL1_VSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL1_VSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL1_VSYNC_PERIOD_MASK)
/*! @} */
/*! @name VDCTRL2 - LCDIF VSYNC Mode and Dotclk Mode Control Register2 */
/*! @{ */
#define LCDIF_VDCTRL2_HSYNC_PERIOD_MASK (0x3FFFFU)
#define LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT (0U)
#define LCDIF_VDCTRL2_HSYNC_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PERIOD_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PERIOD_MASK)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK (0xFFFC0000U)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT (18U)
#define LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_SHIFT)) & LCDIF_VDCTRL2_HSYNC_PULSE_WIDTH_MASK)
/*! @} */
/*! @name VDCTRL3 - LCDIF VSYNC Mode and Dotclk Mode Control Register3 */
/*! @{ */
#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK (0xFFFFU)
#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT (0U)
#define LCDIF_VDCTRL3_VERTICAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_VERTICAL_WAIT_CNT_MASK)
#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK (0xFFF0000U)
#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT (16U)
#define LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_SHIFT)) & LCDIF_VDCTRL3_HORIZONTAL_WAIT_CNT_MASK)
#define LCDIF_VDCTRL3_VSYNC_ONLY_MASK (0x10000000U)
#define LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT (28U)
#define LCDIF_VDCTRL3_VSYNC_ONLY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_VSYNC_ONLY_SHIFT)) & LCDIF_VDCTRL3_VSYNC_ONLY_MASK)
#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK (0x20000000U)
#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT (29U)
#define LCDIF_VDCTRL3_MUX_SYNC_SIGNALS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_SHIFT)) & LCDIF_VDCTRL3_MUX_SYNC_SIGNALS_MASK)
#define LCDIF_VDCTRL3_RSRVD0_MASK (0xC0000000U)
#define LCDIF_VDCTRL3_RSRVD0_SHIFT (30U)
#define LCDIF_VDCTRL3_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL3_RSRVD0_SHIFT)) & LCDIF_VDCTRL3_RSRVD0_MASK)
/*! @} */
/*! @name VDCTRL4 - LCDIF VSYNC Mode and Dotclk Mode Control Register4 */
/*! @{ */
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK (0x3FFFFU)
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT (0U)
#define LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_H_VALID_DATA_CNT_MASK)
#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK (0x40000U)
#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT (18U)
#define LCDIF_VDCTRL4_SYNC_SIGNALS_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_SYNC_SIGNALS_ON_SHIFT)) & LCDIF_VDCTRL4_SYNC_SIGNALS_ON_MASK)
#define LCDIF_VDCTRL4_RSRVD0_MASK (0x1FF80000U)
#define LCDIF_VDCTRL4_RSRVD0_SHIFT (19U)
#define LCDIF_VDCTRL4_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_RSRVD0_SHIFT)) & LCDIF_VDCTRL4_RSRVD0_MASK)
#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK (0xE0000000U)
#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT (29U)
#define LCDIF_VDCTRL4_DOTCLK_DLY_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_VDCTRL4_DOTCLK_DLY_SEL_SHIFT)) & LCDIF_VDCTRL4_DOTCLK_DLY_SEL_MASK)
/*! @} */
/*! @name BM_ERROR_STAT - Bus Master Error Status Register */
/*! @{ */
#define LCDIF_BM_ERROR_STAT_ADDR_MASK (0xFFFFFFFFU)
#define LCDIF_BM_ERROR_STAT_ADDR_SHIFT (0U)
#define LCDIF_BM_ERROR_STAT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_BM_ERROR_STAT_ADDR_SHIFT)) & LCDIF_BM_ERROR_STAT_ADDR_MASK)
/*! @} */
/*! @name CRC_STAT - CRC Status Register */
/*! @{ */
#define LCDIF_CRC_STAT_CRC_VALUE_MASK (0xFFFFFFFFU)
#define LCDIF_CRC_STAT_CRC_VALUE_SHIFT (0U)
#define LCDIF_CRC_STAT_CRC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_CRC_STAT_CRC_VALUE_SHIFT)) & LCDIF_CRC_STAT_CRC_VALUE_MASK)
/*! @} */
/*! @name STAT - LCD Interface Status Register */
/*! @{ */
#define LCDIF_STAT_LFIFO_COUNT_MASK (0x1FFU)
#define LCDIF_STAT_LFIFO_COUNT_SHIFT (0U)
#define LCDIF_STAT_LFIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_COUNT_SHIFT)) & LCDIF_STAT_LFIFO_COUNT_MASK)
#define LCDIF_STAT_RSRVD0_MASK (0x1FFFE00U)
#define LCDIF_STAT_RSRVD0_SHIFT (9U)
#define LCDIF_STAT_RSRVD0(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_RSRVD0_SHIFT)) & LCDIF_STAT_RSRVD0_MASK)
#define LCDIF_STAT_TXFIFO_EMPTY_MASK (0x4000000U)
#define LCDIF_STAT_TXFIFO_EMPTY_SHIFT (26U)
#define LCDIF_STAT_TXFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_EMPTY_SHIFT)) & LCDIF_STAT_TXFIFO_EMPTY_MASK)
#define LCDIF_STAT_TXFIFO_FULL_MASK (0x8000000U)
#define LCDIF_STAT_TXFIFO_FULL_SHIFT (27U)
#define LCDIF_STAT_TXFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_TXFIFO_FULL_SHIFT)) & LCDIF_STAT_TXFIFO_FULL_MASK)
#define LCDIF_STAT_LFIFO_EMPTY_MASK (0x10000000U)
#define LCDIF_STAT_LFIFO_EMPTY_SHIFT (28U)
#define LCDIF_STAT_LFIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_EMPTY_SHIFT)) & LCDIF_STAT_LFIFO_EMPTY_MASK)
#define LCDIF_STAT_LFIFO_FULL_MASK (0x20000000U)
#define LCDIF_STAT_LFIFO_FULL_SHIFT (29U)
#define LCDIF_STAT_LFIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_LFIFO_FULL_SHIFT)) & LCDIF_STAT_LFIFO_FULL_MASK)
#define LCDIF_STAT_DMA_REQ_MASK (0x40000000U)
#define LCDIF_STAT_DMA_REQ_SHIFT (30U)
#define LCDIF_STAT_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_DMA_REQ_SHIFT)) & LCDIF_STAT_DMA_REQ_MASK)
#define LCDIF_STAT_PRESENT_MASK (0x80000000U)
#define LCDIF_STAT_PRESENT_SHIFT (31U)
#define LCDIF_STAT_PRESENT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_STAT_PRESENT_SHIFT)) & LCDIF_STAT_PRESENT_MASK)
/*! @} */
/*! @name THRES - LCDIF Threshold Register */
/*! @{ */
#define LCDIF_THRES_RSRVD_MASK (0x1FFU)
#define LCDIF_THRES_RSRVD_SHIFT (0U)
#define LCDIF_THRES_RSRVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD_SHIFT)) & LCDIF_THRES_RSRVD_MASK)
#define LCDIF_THRES_RSRVD1_MASK (0xFE00U)
#define LCDIF_THRES_RSRVD1_SHIFT (9U)
#define LCDIF_THRES_RSRVD1(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD1_SHIFT)) & LCDIF_THRES_RSRVD1_MASK)
#define LCDIF_THRES_FASTCLOCK_MASK (0x1FF0000U)
#define LCDIF_THRES_FASTCLOCK_SHIFT (16U)
#define LCDIF_THRES_FASTCLOCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_FASTCLOCK_SHIFT)) & LCDIF_THRES_FASTCLOCK_MASK)
#define LCDIF_THRES_RSRVD2_MASK (0xFE000000U)
#define LCDIF_THRES_RSRVD2_SHIFT (25U)
#define LCDIF_THRES_RSRVD2(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_THRES_RSRVD2_SHIFT)) & LCDIF_THRES_RSRVD2_MASK)
/*! @} */
/*! @name PIGEONCTRL0 - LCDIF Pigeon Mode Control0 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL0_FD_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL0_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_FD_PERIOD_MASK)
#define LCDIF_PIGEONCTRL0_LD_PERIOD_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT (16U)
#define LCDIF_PIGEONCTRL0_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_LD_PERIOD_MASK)
/*! @} */
/*! @name PIGEONCTRL0_SET - LCDIF Pigeon Mode Control0 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL0_SET_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_FD_PERIOD_MASK)
#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT (16U)
#define LCDIF_PIGEONCTRL0_SET_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_SET_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_SET_LD_PERIOD_MASK)
/*! @} */
/*! @name PIGEONCTRL0_CLR - LCDIF Pigeon Mode Control0 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL0_CLR_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_FD_PERIOD_MASK)
#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT (16U)
#define LCDIF_PIGEONCTRL0_CLR_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_CLR_LD_PERIOD_MASK)
/*! @} */
/*! @name PIGEONCTRL0_TOG - LCDIF Pigeon Mode Control0 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL0_TOG_FD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_FD_PERIOD_MASK)
#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT (16U)
#define LCDIF_PIGEONCTRL0_TOG_LD_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL0_TOG_LD_PERIOD_MASK)
/*! @} */
/*! @name PIGEONCTRL1 - LCDIF Pigeon Mode Control1 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_PERIOD_MASK)
#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT (16U)
#define LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_FRAME_CNT_CYCLES_MASK)
/*! @} */
/*! @name PIGEONCTRL1_SET - LCDIF Pigeon Mode Control1 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_PERIOD_MASK)
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT (16U)
#define LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_SET_FRAME_CNT_CYCLES_MASK)
/*! @} */
/*! @name PIGEONCTRL1_CLR - LCDIF Pigeon Mode Control1 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_PERIOD_MASK)
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT (16U)
#define LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_CLR_FRAME_CNT_CYCLES_MASK)
/*! @} */
/*! @name PIGEONCTRL1_TOG - LCDIF Pigeon Mode Control1 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK (0xFFFU)
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT (0U)
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_PERIOD_MASK)
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK (0xFFF0000U)
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT (16U)
#define LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_SHIFT)) & LCDIF_PIGEONCTRL1_TOG_FRAME_CNT_CYCLES_MASK)
/*! @} */
/*! @name PIGEONCTRL2 - LCDIF Pigeon Mode Control2 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK (0x1U)
#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT (0U)
#define LCDIF_PIGEONCTRL2_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_DATA_EN_MASK)
#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK (0x2U)
#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT (1U)
#define LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_PIGEON_CLK_GATE_MASK)
/*! @} */
/*! @name PIGEONCTRL2_SET - LCDIF Pigeon Mode Control2 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK (0x1U)
#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT (0U)
#define LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_DATA_EN_MASK)
#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK (0x2U)
#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT (1U)
#define LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_SET_PIGEON_CLK_GATE_MASK)
/*! @} */
/*! @name PIGEONCTRL2_CLR - LCDIF Pigeon Mode Control2 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK (0x1U)
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT (0U)
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_DATA_EN_MASK)
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK (0x2U)
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT (1U)
#define LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_CLR_PIGEON_CLK_GATE_MASK)
/*! @} */
/*! @name PIGEONCTRL2_TOG - LCDIF Pigeon Mode Control2 Register */
/*! @{ */
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK (0x1U)
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT (0U)
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_DATA_EN_MASK)
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK (0x2U)
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT (1U)
#define LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_SHIFT)) & LCDIF_PIGEONCTRL2_TOG_PIGEON_CLK_GATE_MASK)
/*! @} */
/*! @name PIGEON_0 - Panel Interface Signal Generator Register */
/*! @{ */
#define LCDIF_PIGEON_0_EN_MASK (0x1U)
#define LCDIF_PIGEON_0_EN_SHIFT (0U)
#define LCDIF_PIGEON_0_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_EN_SHIFT)) & LCDIF_PIGEON_0_EN_MASK)
#define LCDIF_PIGEON_0_POL_MASK (0x2U)
#define LCDIF_PIGEON_0_POL_SHIFT (1U)
/*! POL
* 0b0..Normal Signal (Active high)
* 0b1..Inverted signal (Active low)
*/
#define LCDIF_PIGEON_0_POL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_POL_SHIFT)) & LCDIF_PIGEON_0_POL_MASK)
#define LCDIF_PIGEON_0_INC_SEL_MASK (0xCU)
#define LCDIF_PIGEON_0_INC_SEL_SHIFT (2U)
/*! INC_SEL
* 0b00..pclk
* 0b01..Line start pulse
* 0b10..Frame start pulse
* 0b11..Use another signal as tick event
*/
#define LCDIF_PIGEON_0_INC_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_INC_SEL_SHIFT)) & LCDIF_PIGEON_0_INC_SEL_MASK)
#define LCDIF_PIGEON_0_OFFSET_MASK (0xF0U)
#define LCDIF_PIGEON_0_OFFSET_SHIFT (4U)
#define LCDIF_PIGEON_0_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_OFFSET_SHIFT)) & LCDIF_PIGEON_0_OFFSET_MASK)
#define LCDIF_PIGEON_0_MASK_CNT_SEL_MASK (0xF00U)
#define LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT (8U)
/*! MASK_CNT_SEL
* 0b0000..pclk counter within one hscan state
* 0b0001..pclk cycle within one hscan state
* 0b0010..line counter within one vscan state
* 0b0011..line cycle within one vscan state
* 0b0100..frame counter
* 0b0101..frame cycle
* 0b0110..horizontal counter (pclk counter within one line )
* 0b0111..vertical counter (line counter within one frame)
*/
#define LCDIF_PIGEON_0_MASK_CNT_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SEL_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_SEL_MASK)
#define LCDIF_PIGEON_0_MASK_CNT_MASK (0xFFF000U)
#define LCDIF_PIGEON_0_MASK_CNT_SHIFT (12U)
#define LCDIF_PIGEON_0_MASK_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_MASK_CNT_SHIFT)) & LCDIF_PIGEON_0_MASK_CNT_MASK)
#define LCDIF_PIGEON_0_STATE_MASK_MASK (0xFF000000U)
#define LCDIF_PIGEON_0_STATE_MASK_SHIFT (24U)
/*! STATE_MASK
* 0b00000001..FRAME SYNC
* 0b00000010..FRAME BEGIN
* 0b00000100..FRAME DATA
* 0b00001000..FRAME END
* 0b00010000..LINE SYNC
* 0b00100000..LINE BEGIN
* 0b01000000..LINE DATA
* 0b10000000..LINE END
*/
#define LCDIF_PIGEON_0_STATE_MASK(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_0_STATE_MASK_SHIFT)) & LCDIF_PIGEON_0_STATE_MASK_MASK)
/*! @} */
/* The count of LCDIF_PIGEON_0 */
#define LCDIF_PIGEON_0_COUNT (12U)
/*! @name PIGEON_1 - Panel Interface Signal Generator Register */
/*! @{ */
#define LCDIF_PIGEON_1_SET_CNT_MASK (0xFFFFU)
#define LCDIF_PIGEON_1_SET_CNT_SHIFT (0U)
/*! SET_CNT
* 0b0000000000000000..Start as active
*/
#define LCDIF_PIGEON_1_SET_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_SET_CNT_SHIFT)) & LCDIF_PIGEON_1_SET_CNT_MASK)
#define LCDIF_PIGEON_1_CLR_CNT_MASK (0xFFFF0000U)
#define LCDIF_PIGEON_1_CLR_CNT_SHIFT (16U)
/*! CLR_CNT
* 0b0000000000000000..Keep active until mask off
*/
#define LCDIF_PIGEON_1_CLR_CNT(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_1_CLR_CNT_SHIFT)) & LCDIF_PIGEON_1_CLR_CNT_MASK)
/*! @} */
/* The count of LCDIF_PIGEON_1 */
#define LCDIF_PIGEON_1_COUNT (12U)
/*! @name PIGEON_2 - Panel Interface Signal Generator Register */
/*! @{ */
#define LCDIF_PIGEON_2_SIG_LOGIC_MASK (0xFU)
#define LCDIF_PIGEON_2_SIG_LOGIC_SHIFT (0U)
/*! SIG_LOGIC
* 0b0000..No logic operation
* 0b0001..sigout = sig_another AND this_sig
* 0b0010..sigout = sig_another OR this_sig
* 0b0011..mask = sig_another AND other_masks
*/
#define LCDIF_PIGEON_2_SIG_LOGIC(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_LOGIC_SHIFT)) & LCDIF_PIGEON_2_SIG_LOGIC_MASK)
#define LCDIF_PIGEON_2_SIG_ANOTHER_MASK (0x1F0U)
#define LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT (4U)
/*! SIG_ANOTHER
* 0b00000..Keep active until mask off
*/
#define LCDIF_PIGEON_2_SIG_ANOTHER(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_SIG_ANOTHER_SHIFT)) & LCDIF_PIGEON_2_SIG_ANOTHER_MASK)
#define LCDIF_PIGEON_2_RSVD_MASK (0xFFFFFE00U)
#define LCDIF_PIGEON_2_RSVD_SHIFT (9U)
#define LCDIF_PIGEON_2_RSVD(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_PIGEON_2_RSVD_SHIFT)) & LCDIF_PIGEON_2_RSVD_MASK)
/*! @} */
/* The count of LCDIF_PIGEON_2 */
#define LCDIF_PIGEON_2_COUNT (12U)
/*! @name LUT_CTRL - Look Up Table Control Register */
/*! @{ */
#define LCDIF_LUT_CTRL_LUT_BYPASS_MASK (0x1U)
#define LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT (0U)
#define LCDIF_LUT_CTRL_LUT_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT_CTRL_LUT_BYPASS_SHIFT)) & LCDIF_LUT_CTRL_LUT_BYPASS_MASK)
/*! @} */
/*! @name LUT0_ADDR - Lookup Table 0 Index Register */
/*! @{ */
#define LCDIF_LUT0_ADDR_ADDR_MASK (0xFFU)
#define LCDIF_LUT0_ADDR_ADDR_SHIFT (0U)
#define LCDIF_LUT0_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_ADDR_ADDR_SHIFT)) & LCDIF_LUT0_ADDR_ADDR_MASK)
/*! @} */
/*! @name LUT0_DATA - Lookup Table 0 Data Register */
/*! @{ */
#define LCDIF_LUT0_DATA_DATA_MASK (0xFFFFFFFFU)
#define LCDIF_LUT0_DATA_DATA_SHIFT (0U)
#define LCDIF_LUT0_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT0_DATA_DATA_SHIFT)) & LCDIF_LUT0_DATA_DATA_MASK)
/*! @} */
/*! @name LUT1_ADDR - Lookup Table 1 Index Register */
/*! @{ */
#define LCDIF_LUT1_ADDR_ADDR_MASK (0xFFU)
#define LCDIF_LUT1_ADDR_ADDR_SHIFT (0U)
#define LCDIF_LUT1_ADDR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_ADDR_ADDR_SHIFT)) & LCDIF_LUT1_ADDR_ADDR_MASK)
/*! @} */
/*! @name LUT1_DATA - Lookup Table 1 Data Register */
/*! @{ */
#define LCDIF_LUT1_DATA_DATA_MASK (0xFFFFFFFFU)
#define LCDIF_LUT1_DATA_DATA_SHIFT (0U)
#define LCDIF_LUT1_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << LCDIF_LUT1_DATA_DATA_SHIFT)) & LCDIF_LUT1_DATA_DATA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group LCDIF_Register_Masks */
/* LCDIF - Peripheral instance base addresses */
/** Peripheral LCDIF base address */
#define LCDIF_BASE (0x40804000u)
/** Peripheral LCDIF base pointer */
#define LCDIF ((LCDIF_Type *)LCDIF_BASE)
/** Array initializer of LCDIF peripheral base addresses */
#define LCDIF_BASE_ADDRS { LCDIF_BASE }
/** Array initializer of LCDIF peripheral base pointers */
#define LCDIF_BASE_PTRS { LCDIF }
/** Interrupt vectors for the LCDIF peripheral type */
#define LCDIF_IRQ0_IRQS { eLCDIF_IRQn }
/*!
* @}
*/ /* end of group LCDIF_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LCDIFV2 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LCDIFV2_Peripheral_Access_Layer LCDIFV2 Peripheral Access Layer
* @{
*/
/** LCDIFV2 - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< LCDIFv2 display control Register, offset: 0x0 */
__IO uint32_t CTRL_SET; /**< LCDIFv2 display control Register, offset: 0x4 */
__IO uint32_t CTRL_CLR; /**< LCDIFv2 display control Register, offset: 0x8 */
__IO uint32_t CTRL_TOG; /**< LCDIFv2 display control Register, offset: 0xC */
__IO uint32_t DISP_PARA; /**< Display Parameter Register, offset: 0x10 */
__IO uint32_t DISP_SIZE; /**< Display Size Register, offset: 0x14 */
__IO uint32_t HSYN_PARA; /**< Horizontal Sync Parameter Register, offset: 0x18 */
__IO uint32_t VSYN_PARA; /**< Vertical Sync Parameter Register, offset: 0x1C */
struct { /* offset: 0x20, array step: 0x10 */
__IO uint32_t INT_STATUS; /**< Interrupt Status Register for domain 0..Interrupt Status Register for domain 1, array offset: 0x20, array step: 0x10 */
__IO uint32_t INT_ENABLE; /**< Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1, array offset: 0x24, array step: 0x10 */
uint8_t RESERVED_0[8];
} INT[2];
__IO uint32_t PDI_PARA; /**< Parallel Data Interface Parameter Register, offset: 0x40 */
uint8_t RESERVED_0[444];
struct { /* offset: 0x200, array step: 0x40 */
__IO uint32_t CTRLDESCL1; /**< Control Descriptor Layer 1 Register, array offset: 0x200, array step: 0x40 */
__IO uint32_t CTRLDESCL2; /**< Control Descriptor Layer 2 Register, array offset: 0x204, array step: 0x40 */
__IO uint32_t CTRLDESCL3; /**< Control Descriptor Layer 3 Register, array offset: 0x208, array step: 0x40 */
__IO uint32_t CTRLDESCL4; /**< Control Descriptor Layer 4 Register, array offset: 0x20C, array step: 0x40 */
__IO uint32_t CTRLDESCL5; /**< Control Descriptor Layer 5 Register, array offset: 0x210, array step: 0x40 */
__IO uint32_t CTRLDESCL6; /**< Control Descriptor Layer 6 Register, array offset: 0x214, array step: 0x40 */
__IO uint32_t CSC_COEF0; /**< Color Space Conversion Coefficient Register 0, array offset: 0x218, array step: 0x40, this item is not available for all array instances */
__IO uint32_t CSC_COEF1; /**< Color Space Conversion Coefficient Register 1, array offset: 0x21C, array step: 0x40, this item is not available for all array instances */
__IO uint32_t CSC_COEF2; /**< Color Space Conversion Coefficient Register 2, array offset: 0x220, array step: 0x40, this item is not available for all array instances */
uint8_t RESERVED_0[28];
} LAYER[8];
__IO uint32_t CLUT_LOAD; /**< LCDIFv2 CLUT load Register, offset: 0x400 */
} LCDIFV2_Type;
/* ----------------------------------------------------------------------------
-- LCDIFV2 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LCDIFV2_Register_Masks LCDIFV2 Register Masks
* @{
*/
/*! @name CTRL - LCDIFv2 display control Register */
/*! @{ */
#define LCDIFV2_CTRL_INV_HS_MASK (0x1U)
#define LCDIFV2_CTRL_INV_HS_SHIFT (0U)
/*! INV_HS - Invert Horizontal synchronization signal
* 0b0..HSYNC signal not inverted (active HIGH)
* 0b1..Invert HSYNC signal (active LOW)
*/
#define LCDIFV2_CTRL_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_HS_SHIFT)) & LCDIFV2_CTRL_INV_HS_MASK)
#define LCDIFV2_CTRL_INV_VS_MASK (0x2U)
#define LCDIFV2_CTRL_INV_VS_SHIFT (1U)
/*! INV_VS - Invert Vertical synchronization signal
* 0b0..VSYNC signal not inverted (active HIGH)
* 0b1..Invert VSYNC signal (active LOW)
*/
#define LCDIFV2_CTRL_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_VS_SHIFT)) & LCDIFV2_CTRL_INV_VS_MASK)
#define LCDIFV2_CTRL_INV_DE_MASK (0x4U)
#define LCDIFV2_CTRL_INV_DE_SHIFT (2U)
/*! INV_DE - Invert Data Enable polarity
* 0b0..Data enable is active high
* 0b1..Data enable is active low
*/
#define LCDIFV2_CTRL_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_DE_SHIFT)) & LCDIFV2_CTRL_INV_DE_MASK)
#define LCDIFV2_CTRL_INV_PXCK_MASK (0x8U)
#define LCDIFV2_CTRL_INV_PXCK_SHIFT (3U)
/*! INV_PXCK - Polarity change of Pixel Clock
* 0b0..Display samples data on the falling edge
* 0b1..Display samples data on the rising edge
*/
#define LCDIFV2_CTRL_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_INV_PXCK_MASK)
#define LCDIFV2_CTRL_NEG_MASK (0x10U)
#define LCDIFV2_CTRL_NEG_SHIFT (4U)
/*! NEG - Indicates if value at the output (pixel data output) needs to be negated
* 0b0..Output is to remain same
* 0b1..Output to be negated
*/
#define LCDIFV2_CTRL_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_NEG_SHIFT)) & LCDIFV2_CTRL_NEG_MASK)
#define LCDIFV2_CTRL_SW_RESET_MASK (0x80000000U)
#define LCDIFV2_CTRL_SW_RESET_SHIFT (31U)
/*! SW_RESET - Software Reset
* 0b0..No action
* 0b1..All LCDIFv2 internal registers are forced into their reset state. User registers are not affected
*/
#define LCDIFV2_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SW_RESET_MASK)
/*! @} */
/*! @name CTRL_SET - LCDIFv2 display control Register */
/*! @{ */
#define LCDIFV2_CTRL_SET_INV_HS_MASK (0x1U)
#define LCDIFV2_CTRL_SET_INV_HS_SHIFT (0U)
/*! INV_HS - Invert Horizontal synchronization signal
*/
#define LCDIFV2_CTRL_SET_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_HS_SHIFT)) & LCDIFV2_CTRL_SET_INV_HS_MASK)
#define LCDIFV2_CTRL_SET_INV_VS_MASK (0x2U)
#define LCDIFV2_CTRL_SET_INV_VS_SHIFT (1U)
/*! INV_VS - Invert Vertical synchronization signal
*/
#define LCDIFV2_CTRL_SET_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_VS_SHIFT)) & LCDIFV2_CTRL_SET_INV_VS_MASK)
#define LCDIFV2_CTRL_SET_INV_DE_MASK (0x4U)
#define LCDIFV2_CTRL_SET_INV_DE_SHIFT (2U)
/*! INV_DE - Invert Data Enable polarity
*/
#define LCDIFV2_CTRL_SET_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_DE_SHIFT)) & LCDIFV2_CTRL_SET_INV_DE_MASK)
#define LCDIFV2_CTRL_SET_INV_PXCK_MASK (0x8U)
#define LCDIFV2_CTRL_SET_INV_PXCK_SHIFT (3U)
/*! INV_PXCK - Polarity change of Pixel Clock
*/
#define LCDIFV2_CTRL_SET_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_SET_INV_PXCK_MASK)
#define LCDIFV2_CTRL_SET_NEG_MASK (0x10U)
#define LCDIFV2_CTRL_SET_NEG_SHIFT (4U)
/*! NEG - Indicates if value at the output (pixel data output) needs to be negated
*/
#define LCDIFV2_CTRL_SET_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_NEG_SHIFT)) & LCDIFV2_CTRL_SET_NEG_MASK)
#define LCDIFV2_CTRL_SET_SW_RESET_MASK (0x80000000U)
#define LCDIFV2_CTRL_SET_SW_RESET_SHIFT (31U)
/*! SW_RESET - Software Reset
*/
#define LCDIFV2_CTRL_SET_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_SET_SW_RESET_SHIFT)) & LCDIFV2_CTRL_SET_SW_RESET_MASK)
/*! @} */
/*! @name CTRL_CLR - LCDIFv2 display control Register */
/*! @{ */
#define LCDIFV2_CTRL_CLR_INV_HS_MASK (0x1U)
#define LCDIFV2_CTRL_CLR_INV_HS_SHIFT (0U)
/*! INV_HS - Invert Horizontal synchronization signal
*/
#define LCDIFV2_CTRL_CLR_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_HS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_HS_MASK)
#define LCDIFV2_CTRL_CLR_INV_VS_MASK (0x2U)
#define LCDIFV2_CTRL_CLR_INV_VS_SHIFT (1U)
/*! INV_VS - Invert Vertical synchronization signal
*/
#define LCDIFV2_CTRL_CLR_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_VS_SHIFT)) & LCDIFV2_CTRL_CLR_INV_VS_MASK)
#define LCDIFV2_CTRL_CLR_INV_DE_MASK (0x4U)
#define LCDIFV2_CTRL_CLR_INV_DE_SHIFT (2U)
/*! INV_DE - Invert Data Enable polarity
*/
#define LCDIFV2_CTRL_CLR_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_DE_SHIFT)) & LCDIFV2_CTRL_CLR_INV_DE_MASK)
#define LCDIFV2_CTRL_CLR_INV_PXCK_MASK (0x8U)
#define LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT (3U)
/*! INV_PXCK - Polarity change of Pixel Clock
*/
#define LCDIFV2_CTRL_CLR_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_CLR_INV_PXCK_MASK)
#define LCDIFV2_CTRL_CLR_NEG_MASK (0x10U)
#define LCDIFV2_CTRL_CLR_NEG_SHIFT (4U)
/*! NEG - Indicates if value at the output (pixel data output) needs to be negated
*/
#define LCDIFV2_CTRL_CLR_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_NEG_SHIFT)) & LCDIFV2_CTRL_CLR_NEG_MASK)
#define LCDIFV2_CTRL_CLR_SW_RESET_MASK (0x80000000U)
#define LCDIFV2_CTRL_CLR_SW_RESET_SHIFT (31U)
/*! SW_RESET - Software Reset
*/
#define LCDIFV2_CTRL_CLR_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_CLR_SW_RESET_SHIFT)) & LCDIFV2_CTRL_CLR_SW_RESET_MASK)
/*! @} */
/*! @name CTRL_TOG - LCDIFv2 display control Register */
/*! @{ */
#define LCDIFV2_CTRL_TOG_INV_HS_MASK (0x1U)
#define LCDIFV2_CTRL_TOG_INV_HS_SHIFT (0U)
/*! INV_HS - Invert Horizontal synchronization signal
*/
#define LCDIFV2_CTRL_TOG_INV_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_HS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_HS_MASK)
#define LCDIFV2_CTRL_TOG_INV_VS_MASK (0x2U)
#define LCDIFV2_CTRL_TOG_INV_VS_SHIFT (1U)
/*! INV_VS - Invert Vertical synchronization signal
*/
#define LCDIFV2_CTRL_TOG_INV_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_VS_SHIFT)) & LCDIFV2_CTRL_TOG_INV_VS_MASK)
#define LCDIFV2_CTRL_TOG_INV_DE_MASK (0x4U)
#define LCDIFV2_CTRL_TOG_INV_DE_SHIFT (2U)
/*! INV_DE - Invert Data Enable polarity
*/
#define LCDIFV2_CTRL_TOG_INV_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_DE_SHIFT)) & LCDIFV2_CTRL_TOG_INV_DE_MASK)
#define LCDIFV2_CTRL_TOG_INV_PXCK_MASK (0x8U)
#define LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT (3U)
/*! INV_PXCK - Polarity change of Pixel Clock
*/
#define LCDIFV2_CTRL_TOG_INV_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_INV_PXCK_SHIFT)) & LCDIFV2_CTRL_TOG_INV_PXCK_MASK)
#define LCDIFV2_CTRL_TOG_NEG_MASK (0x10U)
#define LCDIFV2_CTRL_TOG_NEG_SHIFT (4U)
/*! NEG - Indicates if value at the output (pixel data output) needs to be negated
*/
#define LCDIFV2_CTRL_TOG_NEG(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_NEG_SHIFT)) & LCDIFV2_CTRL_TOG_NEG_MASK)
#define LCDIFV2_CTRL_TOG_SW_RESET_MASK (0x80000000U)
#define LCDIFV2_CTRL_TOG_SW_RESET_SHIFT (31U)
/*! SW_RESET - Software Reset
*/
#define LCDIFV2_CTRL_TOG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRL_TOG_SW_RESET_SHIFT)) & LCDIFV2_CTRL_TOG_SW_RESET_MASK)
/*! @} */
/*! @name DISP_PARA - Display Parameter Register */
/*! @{ */
#define LCDIFV2_DISP_PARA_BGND_B_MASK (0xFFU)
#define LCDIFV2_DISP_PARA_BGND_B_SHIFT (0U)
/*! BGND_B - Blue component of the default color displayed in the sectors where no layer is active
*/
#define LCDIFV2_DISP_PARA_BGND_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_B_SHIFT)) & LCDIFV2_DISP_PARA_BGND_B_MASK)
#define LCDIFV2_DISP_PARA_BGND_G_MASK (0xFF00U)
#define LCDIFV2_DISP_PARA_BGND_G_SHIFT (8U)
/*! BGND_G - Green component of the default color displayed in the sectors where no layer is active
*/
#define LCDIFV2_DISP_PARA_BGND_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_G_SHIFT)) & LCDIFV2_DISP_PARA_BGND_G_MASK)
#define LCDIFV2_DISP_PARA_BGND_R_MASK (0xFF0000U)
#define LCDIFV2_DISP_PARA_BGND_R_SHIFT (16U)
/*! BGND_R - Red component of the default color displayed in the sectors where no layer is active
*/
#define LCDIFV2_DISP_PARA_BGND_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_BGND_R_SHIFT)) & LCDIFV2_DISP_PARA_BGND_R_MASK)
#define LCDIFV2_DISP_PARA_DISP_MODE_MASK (0x3000000U)
#define LCDIFV2_DISP_PARA_DISP_MODE_SHIFT (24U)
/*! DISP_MODE - LCDIFv2 operating mode
* 0b00..Normal mode. Panel content controlled by layer configuration
* 0b01..Test Mode1(BGND Color Display)
* 0b10..Test Mode2(Column Color Bar)
* 0b11..Test Mode3(Row Color Bar)
*/
#define LCDIFV2_DISP_PARA_DISP_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_MODE_SHIFT)) & LCDIFV2_DISP_PARA_DISP_MODE_MASK)
#define LCDIFV2_DISP_PARA_LINE_PATTERN_MASK (0x1C000000U)
#define LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT (26U)
/*! LINE_PATTERN - LCDIFv2 line output order
* 0b000..RGB
* 0b001..RBG
* 0b010..GBR
* 0b011..GRB
* 0b100..BRG
* 0b101..BGR
*/
#define LCDIFV2_DISP_PARA_LINE_PATTERN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_LINE_PATTERN_SHIFT)) & LCDIFV2_DISP_PARA_LINE_PATTERN_MASK)
#define LCDIFV2_DISP_PARA_DISP_ON_MASK (0x80000000U)
#define LCDIFV2_DISP_PARA_DISP_ON_SHIFT (31U)
/*! DISP_ON - Display panel On/Off mode
* 0b0..Display Off
* 0b1..Display On
*/
#define LCDIFV2_DISP_PARA_DISP_ON(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_PARA_DISP_ON_SHIFT)) & LCDIFV2_DISP_PARA_DISP_ON_MASK)
/*! @} */
/*! @name DISP_SIZE - Display Size Register */
/*! @{ */
#define LCDIFV2_DISP_SIZE_DELTA_X_MASK (0xFFFU)
#define LCDIFV2_DISP_SIZE_DELTA_X_SHIFT (0U)
/*! DELTA_X - Sets the display size horizontal resolution in pixels
*/
#define LCDIFV2_DISP_SIZE_DELTA_X(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_X_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_X_MASK)
#define LCDIFV2_DISP_SIZE_DELTA_Y_MASK (0xFFF0000U)
#define LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT (16U)
/*! DELTA_Y - Sets the display size vertical resolution in pixels
*/
#define LCDIFV2_DISP_SIZE_DELTA_Y(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_DISP_SIZE_DELTA_Y_SHIFT)) & LCDIFV2_DISP_SIZE_DELTA_Y_MASK)
/*! @} */
/*! @name HSYN_PARA - Horizontal Sync Parameter Register */
/*! @{ */
#define LCDIFV2_HSYN_PARA_FP_H_MASK (0x1FFU)
#define LCDIFV2_HSYN_PARA_FP_H_SHIFT (0U)
/*! FP_H - HSYNC front-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1
*/
#define LCDIFV2_HSYN_PARA_FP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_FP_H_SHIFT)) & LCDIFV2_HSYN_PARA_FP_H_MASK)
#define LCDIFV2_HSYN_PARA_PW_H_MASK (0xFF800U)
#define LCDIFV2_HSYN_PARA_PW_H_SHIFT (11U)
/*! PW_H - HSYNC active pulse width (in pixel clock cycles). Pulse width has a minimum value of 1
*/
#define LCDIFV2_HSYN_PARA_PW_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_PW_H_SHIFT)) & LCDIFV2_HSYN_PARA_PW_H_MASK)
#define LCDIFV2_HSYN_PARA_BP_H_MASK (0x7FC00000U)
#define LCDIFV2_HSYN_PARA_BP_H_SHIFT (22U)
/*! BP_H - HSYNC back-porch pulse width (in pixel clock cycles). Pulse width has a minimum value of 1
*/
#define LCDIFV2_HSYN_PARA_BP_H(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_HSYN_PARA_BP_H_SHIFT)) & LCDIFV2_HSYN_PARA_BP_H_MASK)
/*! @} */
/*! @name VSYN_PARA - Vertical Sync Parameter Register */
/*! @{ */
#define LCDIFV2_VSYN_PARA_FP_V_MASK (0x1FFU)
#define LCDIFV2_VSYN_PARA_FP_V_SHIFT (0U)
/*! FP_V - VSYNC front-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1
*/
#define LCDIFV2_VSYN_PARA_FP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_FP_V_SHIFT)) & LCDIFV2_VSYN_PARA_FP_V_MASK)
#define LCDIFV2_VSYN_PARA_PW_V_MASK (0xFF800U)
#define LCDIFV2_VSYN_PARA_PW_V_SHIFT (11U)
/*! PW_V - VSYNC active pulse width (in horizontal line cycles). Pulse width has a minimum value of 1
*/
#define LCDIFV2_VSYN_PARA_PW_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_PW_V_SHIFT)) & LCDIFV2_VSYN_PARA_PW_V_MASK)
#define LCDIFV2_VSYN_PARA_BP_V_MASK (0x7FC00000U)
#define LCDIFV2_VSYN_PARA_BP_V_SHIFT (22U)
/*! BP_V - VSYNC back-porch pulse width (in horizontal line cycles). Pulse width has a minimum value of 1
*/
#define LCDIFV2_VSYN_PARA_BP_V(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_VSYN_PARA_BP_V_SHIFT)) & LCDIFV2_VSYN_PARA_BP_V_MASK)
/*! @} */
/*! @name INT_STATUS - Interrupt Status Register for domain 0..Interrupt Status Register for domain 1 */
/*! @{ */
#define LCDIFV2_INT_STATUS_VSYNC_MASK (0x1U)
#define LCDIFV2_INT_STATUS_VSYNC_SHIFT (0U)
/*! VSYNC - Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame)
* 0b0..VSYNC has not started
* 0b1..VSYNC has started
*/
#define LCDIFV2_INT_STATUS_VSYNC(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VSYNC_SHIFT)) & LCDIFV2_INT_STATUS_VSYNC_MASK)
#define LCDIFV2_INT_STATUS_UNDERRUN_MASK (0x2U)
#define LCDIFV2_INT_STATUS_UNDERRUN_SHIFT (1U)
/*! UNDERRUN - Interrupt flag to indicate the output buffer underrun condition
* 0b0..Output buffer not underrun
* 0b1..Output buffer underrun
*/
#define LCDIFV2_INT_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_UNDERRUN_SHIFT)) & LCDIFV2_INT_STATUS_UNDERRUN_MASK)
#define LCDIFV2_INT_STATUS_VS_BLANK_MASK (0x4U)
#define LCDIFV2_INT_STATUS_VS_BLANK_SHIFT (2U)
/*! VS_BLANK - Interrupt flag to indicate vertical blanking period
* 0b0..Vertical blanking period has not started
* 0b1..Vertical blanking period has started
*/
#define LCDIFV2_INT_STATUS_VS_BLANK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_VS_BLANK_SHIFT)) & LCDIFV2_INT_STATUS_VS_BLANK_MASK)
#define LCDIFV2_INT_STATUS_DMA_ERR_MASK (0xFF00U)
#define LCDIFV2_INT_STATUS_DMA_ERR_SHIFT (8U)
/*! DMA_ERR - Interrupt flag to indicate that which PLANE has Read Error on the AXI interface
*/
#define LCDIFV2_INT_STATUS_DMA_ERR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_ERR_SHIFT)) & LCDIFV2_INT_STATUS_DMA_ERR_MASK)
#define LCDIFV2_INT_STATUS_DMA_DONE_MASK (0xFF0000U)
#define LCDIFV2_INT_STATUS_DMA_DONE_SHIFT (16U)
/*! DMA_DONE - Interrupt flag to indicate that which PLANE has fetched the last pixel from memory
*/
#define LCDIFV2_INT_STATUS_DMA_DONE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_DMA_DONE_SHIFT)) & LCDIFV2_INT_STATUS_DMA_DONE_MASK)
#define LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK (0xFF000000U)
#define LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT (24U)
/*! FIFO_EMPTY - Interrupt flag to indicate that which FIFO in the pixel blending underflowed
*/
#define LCDIFV2_INT_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_STATUS_FIFO_EMPTY_SHIFT)) & LCDIFV2_INT_STATUS_FIFO_EMPTY_MASK)
/*! @} */
/* The count of LCDIFV2_INT_STATUS */
#define LCDIFV2_INT_STATUS_COUNT (2U)
/*! @name INT_ENABLE - Interrupt Enable Register for domain 0..Interrupt Enable Register for domain 1 */
/*! @{ */
#define LCDIFV2_INT_ENABLE_VSYNC_EN_MASK (0x1U)
#define LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT (0U)
/*! VSYNC_EN - Enable Interrupt flag to indicate that the vertical synchronization phase(The beginning of a frame)
* 0b0..VSYNC interrupt disable
* 0b1..VSYNC interrupt enable
*/
#define LCDIFV2_INT_ENABLE_VSYNC_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VSYNC_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VSYNC_EN_MASK)
#define LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK (0x2U)
#define LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT (1U)
/*! UNDERRUN_EN - Enable Interrupt flag to indicate the output buffer underrun condition
* 0b0..Output buffer underrun disable
* 0b1..Output buffer underrun enable
*/
#define LCDIFV2_INT_ENABLE_UNDERRUN_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_UNDERRUN_EN_SHIFT)) & LCDIFV2_INT_ENABLE_UNDERRUN_EN_MASK)
#define LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK (0x4U)
#define LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT (2U)
/*! VS_BLANK_EN - Enable Interrupt flag to indicate vertical blanking period
* 0b0..Vertical blanking start interrupt disable
* 0b1..Vertical blanking start interrupt enable
*/
#define LCDIFV2_INT_ENABLE_VS_BLANK_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_VS_BLANK_EN_SHIFT)) & LCDIFV2_INT_ENABLE_VS_BLANK_EN_MASK)
#define LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK (0xFF00U)
#define LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT (8U)
/*! DMA_ERR_EN - Enable Interrupt flag to indicate that which PLANE has Read Error on the AXI interface
*/
#define LCDIFV2_INT_ENABLE_DMA_ERR_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_ERR_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_ERR_EN_MASK)
#define LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK (0xFF0000U)
#define LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT (16U)
/*! DMA_DONE_EN - Enable Interrupt flag to indicate that which PLANE has fetched the last pixel from memory
*/
#define LCDIFV2_INT_ENABLE_DMA_DONE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_DMA_DONE_EN_SHIFT)) & LCDIFV2_INT_ENABLE_DMA_DONE_EN_MASK)
#define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK (0xFF000000U)
#define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT (24U)
/*! FIFO_EMPTY_EN - Enable Interrupt flag to indicate that which FIFO in the pixel blending underflowed
*/
#define LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_SHIFT)) & LCDIFV2_INT_ENABLE_FIFO_EMPTY_EN_MASK)
/*! @} */
/* The count of LCDIFV2_INT_ENABLE */
#define LCDIFV2_INT_ENABLE_COUNT (2U)
/*! @name PDI_PARA - Parallel Data Interface Parameter Register */
/*! @{ */
#define LCDIFV2_PDI_PARA_INV_PDI_HS_MASK (0x1U)
#define LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT (0U)
/*! INV_PDI_HS - Polarity of PDI input HSYNC
* 0b0..HSYNC is active HIGH
* 0b1..HSYNC is active LOW
*/
#define LCDIFV2_PDI_PARA_INV_PDI_HS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_HS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_HS_MASK)
#define LCDIFV2_PDI_PARA_INV_PDI_VS_MASK (0x2U)
#define LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT (1U)
/*! INV_PDI_VS - Polarity of PDI input VSYNC
* 0b0..VSYNC is active HIGH
* 0b1..VSYNC is active LOW
*/
#define LCDIFV2_PDI_PARA_INV_PDI_VS(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_VS_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_VS_MASK)
#define LCDIFV2_PDI_PARA_INV_PDI_DE_MASK (0x4U)
#define LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT (2U)
/*! INV_PDI_DE - Polarity of PDI input Data Enable
* 0b0..Data enable is active HIGH
* 0b1..Data enable is active LOW
*/
#define LCDIFV2_PDI_PARA_INV_PDI_DE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_DE_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_DE_MASK)
#define LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK (0x8U)
#define LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT (3U)
/*! INV_PDI_PXCK - Polarity of PDI input Pixel Clock
* 0b0..Samples data on the falling edge
* 0b1..Samples data on the rising edge
*/
#define LCDIFV2_PDI_PARA_INV_PDI_PXCK(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_INV_PDI_PXCK_SHIFT)) & LCDIFV2_PDI_PARA_INV_PDI_PXCK_MASK)
#define LCDIFV2_PDI_PARA_MODE_MASK (0xF0U)
#define LCDIFV2_PDI_PARA_MODE_SHIFT (4U)
/*! MODE - The PDI mode for input data format
* 0b0000..32 bpp (ARGB8888)
* 0b0001..24 bpp (RGB888)
* 0b0010..24 bpp (RGB666)
* 0b0011..16 bpp (RGB565)
* 0b0100..16 bpp (RGB444)
* 0b0101..16 bpp (RGB555)
* 0b0110..16 bpp (YCbCr422)
*/
#define LCDIFV2_PDI_PARA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_MODE_SHIFT)) & LCDIFV2_PDI_PARA_MODE_MASK)
#define LCDIFV2_PDI_PARA_PDI_SEL_MASK (0x40000000U)
#define LCDIFV2_PDI_PARA_PDI_SEL_SHIFT (30U)
/*! PDI_SEL - PDI selected on LCDIFv2 plane number
* 0b0..PDI selected on LCDIFv2 plane 0
* 0b1..PDI selected on LCDIFv2 plane 1
*/
#define LCDIFV2_PDI_PARA_PDI_SEL(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_SEL_SHIFT)) & LCDIFV2_PDI_PARA_PDI_SEL_MASK)
#define LCDIFV2_PDI_PARA_PDI_EN_MASK (0x80000000U)
#define LCDIFV2_PDI_PARA_PDI_EN_SHIFT (31U)
/*! PDI_EN - Enable PDI input data to LCDIFv2 display
* 0b0..Disable PDI input data
* 0b1..Enable PDI input data
*/
#define LCDIFV2_PDI_PARA_PDI_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_PDI_PARA_PDI_EN_SHIFT)) & LCDIFV2_PDI_PARA_PDI_EN_MASK)
/*! @} */
/*! @name CTRLDESCL1 - Control Descriptor Layer 1 Register */
/*! @{ */
#define LCDIFV2_CTRLDESCL1_WIDTH_MASK (0xFFFU)
#define LCDIFV2_CTRLDESCL1_WIDTH_SHIFT (0U)
/*! WIDTH - Width of the layer in pixels
*/
#define LCDIFV2_CTRLDESCL1_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_WIDTH_SHIFT)) & LCDIFV2_CTRLDESCL1_WIDTH_MASK)
#define LCDIFV2_CTRLDESCL1_HEIGHT_MASK (0xFFF0000U)
#define LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT (16U)
/*! HEIGHT - Height of the layer in pixels
*/
#define LCDIFV2_CTRLDESCL1_HEIGHT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL1_HEIGHT_SHIFT)) & LCDIFV2_CTRLDESCL1_HEIGHT_MASK)
/*! @} */
/* The count of LCDIFV2_CTRLDESCL1 */
#define LCDIFV2_CTRLDESCL1_COUNT (8U)
/*! @name CTRLDESCL2 - Control Descriptor Layer 2 Register */
/*! @{ */
#define LCDIFV2_CTRLDESCL2_POSX_MASK (0xFFFU)
#define LCDIFV2_CTRLDESCL2_POSX_SHIFT (0U)
/*! POSX - The horizontal position of left-hand column of the layer, where 0 is the left-hand column
* of the panel, only positive values are to the right the left-hand column of the panel
*/
#define LCDIFV2_CTRLDESCL2_POSX(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSX_SHIFT)) & LCDIFV2_CTRLDESCL2_POSX_MASK)
#define LCDIFV2_CTRLDESCL2_POSY_MASK (0xFFF0000U)
#define LCDIFV2_CTRLDESCL2_POSY_SHIFT (16U)
/*! POSY - The vertical position of top row of the layer, where 0 is the top row of the panel, only
* positive values are below the top row of the panel
*/
#define LCDIFV2_CTRLDESCL2_POSY(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL2_POSY_SHIFT)) & LCDIFV2_CTRLDESCL2_POSY_MASK)
/*! @} */
/* The count of LCDIFV2_CTRLDESCL2 */
#define LCDIFV2_CTRLDESCL2_COUNT (8U)
/*! @name CTRLDESCL3 - Control Descriptor Layer 3 Register */
/*! @{ */
#define LCDIFV2_CTRLDESCL3_PITCH_MASK (0xFFFFU)
#define LCDIFV2_CTRLDESCL3_PITCH_SHIFT (0U)
/*! PITCH - Number of bytes between 2 vertically adjacent pixels in system memory. Byte granularity
* is supported, but SW should align to 64B boundry
*/
#define LCDIFV2_CTRLDESCL3_PITCH(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL3_PITCH_SHIFT)) & LCDIFV2_CTRLDESCL3_PITCH_MASK)
/*! @} */
/* The count of LCDIFV2_CTRLDESCL3 */
#define LCDIFV2_CTRLDESCL3_COUNT (8U)
/*! @name CTRLDESCL4 - Control Descriptor Layer 4 Register */
/*! @{ */
#define LCDIFV2_CTRLDESCL4_ADDR_MASK (0xFFFFFFFFU)
#define LCDIFV2_CTRLDESCL4_ADDR_SHIFT (0U)
/*! ADDR - Address of layer data in the memory. The address programmed should be 64-bit aligned
*/
#define LCDIFV2_CTRLDESCL4_ADDR(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL4_ADDR_SHIFT)) & LCDIFV2_CTRLDESCL4_ADDR_MASK)
/*! @} */
/* The count of LCDIFV2_CTRLDESCL4 */
#define LCDIFV2_CTRLDESCL4_COUNT (8U)
/*! @name CTRLDESCL5 - Control Descriptor Layer 5 Register */
/*! @{ */
#define LCDIFV2_CTRLDESCL5_AB_MODE_MASK (0x3U)
#define LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT (0U)
/*! AB_MODE - Alpha Blending Mode
* 0b00..No alpha Blending (The SAFETY_EN bit need set to 1)
* 0b01..Blend with global ALPHA
* 0b10..Blend with embedded ALPHA
* 0b11..Blend with PoterDuff enable
*/
#define LCDIFV2_CTRLDESCL5_AB_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_AB_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_AB_MODE_MASK)
#define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK (0x30U)
#define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT (4U)
/*! PD_FACTOR_MODE - PoterDuff factor mode
* 0b00..Using 1
* 0b01..Using 0
* 0b10..Using straight alpha
* 0b11..Using inverse alpha
*/
#define LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_FACTOR_MODE_MASK)
#define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK (0xC0U)
#define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT (6U)
/*! PD_GLOBAL_ALPHA_MODE - PoterDuff global alpha mode
* 0b00..Using global alpha
* 0b01..Using local alpha
* 0b10..Using scaled alpha
* 0b11..Using scaled alpha
*/
#define LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_GLOBAL_ALPHA_MODE_MASK)
#define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK (0x100U)
#define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT (8U)
/*! PD_ALPHA_MODE - PoterDuff alpha mode
* 0b0..Straight mode for Porter Duff alpha
* 0b1..Inversed mode for Porter Duff alpha
*/
#define LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_ALPHA_MODE_MASK)
#define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK (0x200U)
#define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT (9U)
/*! PD_COLOR_MODE - PoterDuff alpha mode
* 0b0..Straight mode for Porter Duff color
* 0b1..Inversed mode for Porter Duff color
*/
#define LCDIFV2_CTRLDESCL5_PD_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_SHIFT)) & LCDIFV2_CTRLDESCL5_PD_COLOR_MODE_MASK)
#define LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK (0xC000U)
#define LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT (14U)
/*! YUV_FORMAT - The YUV422 input format selection
* 0b00..The YVYU422 8bit sequence is U1,Y1,V1,Y2
* 0b01..The YVYU422 8bit sequence is V1,Y1,U1,Y2
* 0b10..The YVYU422 8bit sequence is Y1,U1,Y2,V1
* 0b11..The YVYU422 8bit sequence is Y1,V1,Y2,U1
*/
#define LCDIFV2_CTRLDESCL5_YUV_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_YUV_FORMAT_SHIFT)) & LCDIFV2_CTRLDESCL5_YUV_FORMAT_MASK)
#define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK (0xFF0000U)
#define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT (16U)
/*! GLOBAL_ALPHA - Global Alpha
*/
#define LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_SHIFT)) & LCDIFV2_CTRLDESCL5_GLOBAL_ALPHA_MASK)
#define LCDIFV2_CTRLDESCL5_BPP_MASK (0xF000000U)
#define LCDIFV2_CTRLDESCL5_BPP_SHIFT (24U)
/*! BPP - Layer encoding format (bit per pixel)
* 0b0000..1 bpp
* 0b0001..2 bpp
* 0b0010..4 bpp
* 0b0011..8 bpp
* 0b0100..16 bpp (RGB565)
* 0b0101..16 bpp (ARGB1555)
* 0b0110..16 bpp (ARGB4444)
* 0b0111..YCbCr422 (Only layer 0/1 can support this format)
* 0b1000..24 bpp (RGB888)
* 0b1001..32 bpp (ARGB8888)
* 0b1010..32 bpp (ABGR8888)
*/
#define LCDIFV2_CTRLDESCL5_BPP(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_BPP_SHIFT)) & LCDIFV2_CTRLDESCL5_BPP_MASK)
#define LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK (0x10000000U)
#define LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT (28U)
/*! SAFETY_EN - Safety Mode Enable Bit
* 0b0..Safety Mode is disabled
* 0b1..Safety Mode is enabled for this layer
*/
#define LCDIFV2_CTRLDESCL5_SAFETY_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SAFETY_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SAFETY_EN_MASK)
#define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK (0x40000000U)
#define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT (30U)
/*! SHADOW_LOAD_EN - Shadow Load Enable
*/
#define LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_SHADOW_LOAD_EN_MASK)
#define LCDIFV2_CTRLDESCL5_EN_MASK (0x80000000U)
#define LCDIFV2_CTRLDESCL5_EN_SHIFT (31U)
/*! EN - Enable the layer for DMA
* 0b0..OFF
* 0b1..ON
*/
#define LCDIFV2_CTRLDESCL5_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL5_EN_SHIFT)) & LCDIFV2_CTRLDESCL5_EN_MASK)
/*! @} */
/* The count of LCDIFV2_CTRLDESCL5 */
#define LCDIFV2_CTRLDESCL5_COUNT (8U)
/*! @name CTRLDESCL6 - Control Descriptor Layer 6 Register */
/*! @{ */
#define LCDIFV2_CTRLDESCL6_BCLR_B_MASK (0xFFU)
#define LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT (0U)
/*! BCLR_B - Background B component value
*/
#define LCDIFV2_CTRLDESCL6_BCLR_B(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_B_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_B_MASK)
#define LCDIFV2_CTRLDESCL6_BCLR_G_MASK (0xFF00U)
#define LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT (8U)
/*! BCLR_G - Background G component value
*/
#define LCDIFV2_CTRLDESCL6_BCLR_G(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_G_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_G_MASK)
#define LCDIFV2_CTRLDESCL6_BCLR_R_MASK (0xFF0000U)
#define LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT (16U)
/*! BCLR_R - Background R component value
*/
#define LCDIFV2_CTRLDESCL6_BCLR_R(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CTRLDESCL6_BCLR_R_SHIFT)) & LCDIFV2_CTRLDESCL6_BCLR_R_MASK)
/*! @} */
/* The count of LCDIFV2_CTRLDESCL6 */
#define LCDIFV2_CTRLDESCL6_COUNT (8U)
/*! @name CSC_COEF0 - Color Space Conversion Coefficient Register 0 */
/*! @{ */
#define LCDIFV2_CSC_COEF0_Y_OFFSET_MASK (0x1FFU)
#define LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT (0U)
/*! Y_OFFSET - Two's compliment amplitude offset implicit in the Y data. For YUV, this is typically
* 0 and for YCbCr, this is typically -16 (0x1F0)
*/
#define LCDIFV2_CSC_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_Y_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_Y_OFFSET_MASK)
#define LCDIFV2_CSC_COEF0_UV_OFFSET_MASK (0x3FE00U)
#define LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT (9U)
/*! UV_OFFSET - Two's compliment phase offset implicit for CbCr data. Generally used for YCbCr to
* RGB conversion. YCbCr=0x180, YUV=0x000 (typically -128 or 0x180 to indicate normalized -0.5 to
* 0.5 range)
*/
#define LCDIFV2_CSC_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_UV_OFFSET_SHIFT)) & LCDIFV2_CSC_COEF0_UV_OFFSET_MASK)
#define LCDIFV2_CSC_COEF0_C0_MASK (0x1FFC0000U)
#define LCDIFV2_CSC_COEF0_C0_SHIFT (18U)
/*! C0 - Two's compliment Y multiplier coefficient. YUV=0x100 (1.000) YCbCr=0x12A (1.164)
*/
#define LCDIFV2_CSC_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_C0_SHIFT)) & LCDIFV2_CSC_COEF0_C0_MASK)
#define LCDIFV2_CSC_COEF0_ENABLE_MASK (0x40000000U)
#define LCDIFV2_CSC_COEF0_ENABLE_SHIFT (30U)
/*! ENABLE - Enable the CSC unit in the LCDIFv2 plane data path
* 0b0..The CSC is bypassed and the input pixels are RGB data already
* 0b1..The CSC is enabled and the pixels will be converted to RGB data
*/
#define LCDIFV2_CSC_COEF0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_ENABLE_SHIFT)) & LCDIFV2_CSC_COEF0_ENABLE_MASK)
#define LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK (0x80000000U)
#define LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT (31U)
/*! YCBCR_MODE - This bit changes the behavior when performing U/V converting
* 0b0..Converting YUV to RGB data
* 0b1..Converting YCbCr to RGB data
*/
#define LCDIFV2_CSC_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF0_YCBCR_MODE_SHIFT)) & LCDIFV2_CSC_COEF0_YCBCR_MODE_MASK)
/*! @} */
/* The count of LCDIFV2_CSC_COEF0 */
#define LCDIFV2_CSC_COEF0_COUNT (8U)
/*! @name CSC_COEF1 - Color Space Conversion Coefficient Register 1 */
/*! @{ */
#define LCDIFV2_CSC_COEF1_C4_MASK (0x7FFU)
#define LCDIFV2_CSC_COEF1_C4_SHIFT (0U)
/*! C4 - Two's compliment Blue U/Cb multiplier coefficient. YUV=0x208 (2.032) YCbCr=0x204 (2.017)
*/
#define LCDIFV2_CSC_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C4_SHIFT)) & LCDIFV2_CSC_COEF1_C4_MASK)
#define LCDIFV2_CSC_COEF1_C1_MASK (0x7FF0000U)
#define LCDIFV2_CSC_COEF1_C1_SHIFT (16U)
/*! C1 - Two's compliment Red V/Cr multiplier coefficient. YUV=0x123 (1.140) YCbCr=0x198 (1.596)
*/
#define LCDIFV2_CSC_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF1_C1_SHIFT)) & LCDIFV2_CSC_COEF1_C1_MASK)
/*! @} */
/* The count of LCDIFV2_CSC_COEF1 */
#define LCDIFV2_CSC_COEF1_COUNT (8U)
/*! @name CSC_COEF2 - Color Space Conversion Coefficient Register 2 */
/*! @{ */
#define LCDIFV2_CSC_COEF2_C3_MASK (0x7FFU)
#define LCDIFV2_CSC_COEF2_C3_SHIFT (0U)
/*! C3 - Two's compliment Green U/Cb multiplier coefficient. YUV=0x79C (-0.394) YCbCr=0x79C (-0.392)
*/
#define LCDIFV2_CSC_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C3_SHIFT)) & LCDIFV2_CSC_COEF2_C3_MASK)
#define LCDIFV2_CSC_COEF2_C2_MASK (0x7FF0000U)
#define LCDIFV2_CSC_COEF2_C2_SHIFT (16U)
/*! C2 - Two's compliment Green V/Cr multiplier coefficient. YUV=0x76B (-0.581) YCbCr=0x730 (-0.813)
*/
#define LCDIFV2_CSC_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CSC_COEF2_C2_SHIFT)) & LCDIFV2_CSC_COEF2_C2_MASK)
/*! @} */
/* The count of LCDIFV2_CSC_COEF2 */
#define LCDIFV2_CSC_COEF2_COUNT (8U)
/*! @name CLUT_LOAD - LCDIFv2 CLUT load Register */
/*! @{ */
#define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK (0x1U)
#define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT (0U)
/*! CLUT_UPDATE_EN - CLUT Update Enable
*/
#define LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_SHIFT)) & LCDIFV2_CLUT_LOAD_CLUT_UPDATE_EN_MASK)
#define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK (0x70U)
#define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT (4U)
/*! SEL_CLUT_NUM - Selected CLUT Number
*/
#define LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM(x) (((uint32_t)(((uint32_t)(x)) << LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_SHIFT)) & LCDIFV2_CLUT_LOAD_SEL_CLUT_NUM_MASK)
/*! @} */
/*!
* @}
*/ /* end of group LCDIFV2_Register_Masks */
/* LCDIFV2 - Peripheral instance base addresses */
/** Peripheral LCDIFV2 base address */
#define LCDIFV2_BASE (0x40808000u)
/** Peripheral LCDIFV2 base pointer */
#define LCDIFV2 ((LCDIFV2_Type *)LCDIFV2_BASE)
/** Array initializer of LCDIFV2 peripheral base addresses */
#define LCDIFV2_BASE_ADDRS { LCDIFV2_BASE }
/** Array initializer of LCDIFV2 peripheral base pointers */
#define LCDIFV2_BASE_PTRS { LCDIFV2 }
/*!
* @}
*/ /* end of group LCDIFV2_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPI2C Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Peripheral_Access_Layer LPI2C Peripheral Access Layer
* @{
*/
/** LPI2C - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t MCR; /**< Master Control, offset: 0x10 */
__IO uint32_t MSR; /**< Master Status, offset: 0x14 */
__IO uint32_t MIER; /**< Master Interrupt Enable, offset: 0x18 */
__IO uint32_t MDER; /**< Master DMA Enable, offset: 0x1C */
__IO uint32_t MCFGR0; /**< Master Configuration 0, offset: 0x20 */
__IO uint32_t MCFGR1; /**< Master Configuration 1, offset: 0x24 */
__IO uint32_t MCFGR2; /**< Master Configuration 2, offset: 0x28 */
__IO uint32_t MCFGR3; /**< Master Configuration 3, offset: 0x2C */
uint8_t RESERVED_1[16];
__IO uint32_t MDMR; /**< Master Data Match, offset: 0x40 */
uint8_t RESERVED_2[4];
__IO uint32_t MCCR0; /**< Master Clock Configuration 0, offset: 0x48 */
uint8_t RESERVED_3[4];
__IO uint32_t MCCR1; /**< Master Clock Configuration 1, offset: 0x50 */
uint8_t RESERVED_4[4];
__IO uint32_t MFCR; /**< Master FIFO Control, offset: 0x58 */
__I uint32_t MFSR; /**< Master FIFO Status, offset: 0x5C */
__O uint32_t MTDR; /**< Master Transmit Data, offset: 0x60 */
uint8_t RESERVED_5[12];
__I uint32_t MRDR; /**< Master Receive Data, offset: 0x70 */
uint8_t RESERVED_6[156];
__IO uint32_t SCR; /**< Slave Control, offset: 0x110 */
__IO uint32_t SSR; /**< Slave Status, offset: 0x114 */
__IO uint32_t SIER; /**< Slave Interrupt Enable, offset: 0x118 */
__IO uint32_t SDER; /**< Slave DMA Enable, offset: 0x11C */
uint8_t RESERVED_7[4];
__IO uint32_t SCFGR1; /**< Slave Configuration 1, offset: 0x124 */
__IO uint32_t SCFGR2; /**< Slave Configuration 2, offset: 0x128 */
uint8_t RESERVED_8[20];
__IO uint32_t SAMR; /**< Slave Address Match, offset: 0x140 */
uint8_t RESERVED_9[12];
__I uint32_t SASR; /**< Slave Address Status, offset: 0x150 */
__IO uint32_t STAR; /**< Slave Transmit ACK, offset: 0x154 */
uint8_t RESERVED_10[8];
__O uint32_t STDR; /**< Slave Transmit Data, offset: 0x160 */
uint8_t RESERVED_11[12];
__I uint32_t SRDR; /**< Slave Receive Data, offset: 0x170 */
} LPI2C_Type;
/* ----------------------------------------------------------------------------
-- LPI2C Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPI2C_Register_Masks LPI2C Register Masks
* @{
*/
/*! @name VERID - Version ID */
/*! @{ */
#define LPI2C_VERID_FEATURE_MASK (0xFFFFU)
#define LPI2C_VERID_FEATURE_SHIFT (0U)
/*! FEATURE - Feature Specification Number
* 0b0000000000000010..Master only, with standard feature set
* 0b0000000000000011..Master and slave, with standard feature set
*/
#define LPI2C_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_FEATURE_SHIFT)) & LPI2C_VERID_FEATURE_MASK)
#define LPI2C_VERID_MINOR_MASK (0xFF0000U)
#define LPI2C_VERID_MINOR_SHIFT (16U)
/*! MINOR - Minor Version Number
*/
#define LPI2C_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MINOR_SHIFT)) & LPI2C_VERID_MINOR_MASK)
#define LPI2C_VERID_MAJOR_MASK (0xFF000000U)
#define LPI2C_VERID_MAJOR_SHIFT (24U)
/*! MAJOR - Major Version Number
*/
#define LPI2C_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_VERID_MAJOR_SHIFT)) & LPI2C_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter */
/*! @{ */
#define LPI2C_PARAM_MTXFIFO_MASK (0xFU)
#define LPI2C_PARAM_MTXFIFO_SHIFT (0U)
/*! MTXFIFO - Master Transmit FIFO Size
*/
#define LPI2C_PARAM_MTXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MTXFIFO_SHIFT)) & LPI2C_PARAM_MTXFIFO_MASK)
#define LPI2C_PARAM_MRXFIFO_MASK (0xF00U)
#define LPI2C_PARAM_MRXFIFO_SHIFT (8U)
/*! MRXFIFO - Master Receive FIFO Size
*/
#define LPI2C_PARAM_MRXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_PARAM_MRXFIFO_SHIFT)) & LPI2C_PARAM_MRXFIFO_MASK)
/*! @} */
/*! @name MCR - Master Control */
/*! @{ */
#define LPI2C_MCR_MEN_MASK (0x1U)
#define LPI2C_MCR_MEN_SHIFT (0U)
/*! MEN - Master Enable
* 0b0..Master logic is disabled
* 0b1..Master logic is enabled
*/
#define LPI2C_MCR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_MEN_SHIFT)) & LPI2C_MCR_MEN_MASK)
#define LPI2C_MCR_RST_MASK (0x2U)
#define LPI2C_MCR_RST_SHIFT (1U)
/*! RST - Software Reset
* 0b0..Master logic is not reset
* 0b1..Master logic is reset
*/
#define LPI2C_MCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RST_SHIFT)) & LPI2C_MCR_RST_MASK)
#define LPI2C_MCR_DOZEN_MASK (0x4U)
#define LPI2C_MCR_DOZEN_SHIFT (2U)
/*! DOZEN - Doze mode enable
* 0b0..Master is enabled in Doze mode
* 0b1..Master is disabled in Doze mode
*/
#define LPI2C_MCR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DOZEN_SHIFT)) & LPI2C_MCR_DOZEN_MASK)
#define LPI2C_MCR_DBGEN_MASK (0x8U)
#define LPI2C_MCR_DBGEN_SHIFT (3U)
/*! DBGEN - Debug Enable
* 0b0..Master is disabled in debug mode
* 0b1..Master is enabled in debug mode
*/
#define LPI2C_MCR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_DBGEN_SHIFT)) & LPI2C_MCR_DBGEN_MASK)
#define LPI2C_MCR_RTF_MASK (0x100U)
#define LPI2C_MCR_RTF_SHIFT (8U)
/*! RTF - Reset Transmit FIFO
* 0b0..No effect
* 0b1..Transmit FIFO is reset
*/
#define LPI2C_MCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RTF_SHIFT)) & LPI2C_MCR_RTF_MASK)
#define LPI2C_MCR_RRF_MASK (0x200U)
#define LPI2C_MCR_RRF_SHIFT (9U)
/*! RRF - Reset Receive FIFO
* 0b0..No effect
* 0b1..Receive FIFO is reset
*/
#define LPI2C_MCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCR_RRF_SHIFT)) & LPI2C_MCR_RRF_MASK)
/*! @} */
/*! @name MSR - Master Status */
/*! @{ */
#define LPI2C_MSR_TDF_MASK (0x1U)
#define LPI2C_MSR_TDF_SHIFT (0U)
/*! TDF - Transmit Data Flag
* 0b0..Transmit data is not requested
* 0b1..Transmit data is requested
*/
#define LPI2C_MSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_TDF_SHIFT)) & LPI2C_MSR_TDF_MASK)
#define LPI2C_MSR_RDF_MASK (0x2U)
#define LPI2C_MSR_RDF_SHIFT (1U)
/*! RDF - Receive Data Flag
* 0b0..Receive Data is not ready
* 0b1..Receive data is ready
*/
#define LPI2C_MSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_RDF_SHIFT)) & LPI2C_MSR_RDF_MASK)
#define LPI2C_MSR_EPF_MASK (0x100U)
#define LPI2C_MSR_EPF_SHIFT (8U)
/*! EPF - End Packet Flag
* 0b0..Master has not generated a STOP or Repeated START condition
* 0b1..Master has generated a STOP or Repeated START condition
*/
#define LPI2C_MSR_EPF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_EPF_SHIFT)) & LPI2C_MSR_EPF_MASK)
#define LPI2C_MSR_SDF_MASK (0x200U)
#define LPI2C_MSR_SDF_SHIFT (9U)
/*! SDF - STOP Detect Flag
* 0b0..Master has not generated a STOP condition
* 0b1..Master has generated a STOP condition
*/
#define LPI2C_MSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_SDF_SHIFT)) & LPI2C_MSR_SDF_MASK)
#define LPI2C_MSR_NDF_MASK (0x400U)
#define LPI2C_MSR_NDF_SHIFT (10U)
/*! NDF - NACK Detect Flag
* 0b0..Unexpected NACK was not detected
* 0b1..Unexpected NACK was detected
*/
#define LPI2C_MSR_NDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_NDF_SHIFT)) & LPI2C_MSR_NDF_MASK)
#define LPI2C_MSR_ALF_MASK (0x800U)
#define LPI2C_MSR_ALF_SHIFT (11U)
/*! ALF - Arbitration Lost Flag
* 0b0..Master has not lost arbitration
* 0b1..Master has lost arbitration
*/
#define LPI2C_MSR_ALF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_ALF_SHIFT)) & LPI2C_MSR_ALF_MASK)
#define LPI2C_MSR_FEF_MASK (0x1000U)
#define LPI2C_MSR_FEF_SHIFT (12U)
/*! FEF - FIFO Error Flag
* 0b0..No error
* 0b1..Master sending or receiving data without a START condition
*/
#define LPI2C_MSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_FEF_SHIFT)) & LPI2C_MSR_FEF_MASK)
#define LPI2C_MSR_PLTF_MASK (0x2000U)
#define LPI2C_MSR_PLTF_SHIFT (13U)
/*! PLTF - Pin Low Timeout Flag
* 0b0..Pin low timeout has not occurred or is disabled
* 0b1..Pin low timeout has occurred
*/
#define LPI2C_MSR_PLTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_PLTF_SHIFT)) & LPI2C_MSR_PLTF_MASK)
#define LPI2C_MSR_DMF_MASK (0x4000U)
#define LPI2C_MSR_DMF_SHIFT (14U)
/*! DMF - Data Match Flag
* 0b0..Have not received matching data
* 0b1..Have received matching data
*/
#define LPI2C_MSR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_DMF_SHIFT)) & LPI2C_MSR_DMF_MASK)
#define LPI2C_MSR_MBF_MASK (0x1000000U)
#define LPI2C_MSR_MBF_SHIFT (24U)
/*! MBF - Master Busy Flag
* 0b0..I2C Master is idle
* 0b1..I2C Master is busy
*/
#define LPI2C_MSR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_MBF_SHIFT)) & LPI2C_MSR_MBF_MASK)
#define LPI2C_MSR_BBF_MASK (0x2000000U)
#define LPI2C_MSR_BBF_SHIFT (25U)
/*! BBF - Bus Busy Flag
* 0b0..I2C Bus is idle
* 0b1..I2C Bus is busy
*/
#define LPI2C_MSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MSR_BBF_SHIFT)) & LPI2C_MSR_BBF_MASK)
/*! @} */
/*! @name MIER - Master Interrupt Enable */
/*! @{ */
#define LPI2C_MIER_TDIE_MASK (0x1U)
#define LPI2C_MIER_TDIE_SHIFT (0U)
/*! TDIE - Transmit Data Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_MIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_TDIE_SHIFT)) & LPI2C_MIER_TDIE_MASK)
#define LPI2C_MIER_RDIE_MASK (0x2U)
#define LPI2C_MIER_RDIE_SHIFT (1U)
/*! RDIE - Receive Data Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_MIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_RDIE_SHIFT)) & LPI2C_MIER_RDIE_MASK)
#define LPI2C_MIER_EPIE_MASK (0x100U)
#define LPI2C_MIER_EPIE_SHIFT (8U)
/*! EPIE - End Packet Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_MIER_EPIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_EPIE_SHIFT)) & LPI2C_MIER_EPIE_MASK)
#define LPI2C_MIER_SDIE_MASK (0x200U)
#define LPI2C_MIER_SDIE_SHIFT (9U)
/*! SDIE - STOP Detect Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_MIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_SDIE_SHIFT)) & LPI2C_MIER_SDIE_MASK)
#define LPI2C_MIER_NDIE_MASK (0x400U)
#define LPI2C_MIER_NDIE_SHIFT (10U)
/*! NDIE - NACK Detect Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_MIER_NDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_NDIE_SHIFT)) & LPI2C_MIER_NDIE_MASK)
#define LPI2C_MIER_ALIE_MASK (0x800U)
#define LPI2C_MIER_ALIE_SHIFT (11U)
/*! ALIE - Arbitration Lost Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_MIER_ALIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_ALIE_SHIFT)) & LPI2C_MIER_ALIE_MASK)
#define LPI2C_MIER_FEIE_MASK (0x1000U)
#define LPI2C_MIER_FEIE_SHIFT (12U)
/*! FEIE - FIFO Error Interrupt Enable
* 0b0..Enabled
* 0b1..Disabled
*/
#define LPI2C_MIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_FEIE_SHIFT)) & LPI2C_MIER_FEIE_MASK)
#define LPI2C_MIER_PLTIE_MASK (0x2000U)
#define LPI2C_MIER_PLTIE_SHIFT (13U)
/*! PLTIE - Pin Low Timeout Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_MIER_PLTIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_PLTIE_SHIFT)) & LPI2C_MIER_PLTIE_MASK)
#define LPI2C_MIER_DMIE_MASK (0x4000U)
#define LPI2C_MIER_DMIE_SHIFT (14U)
/*! DMIE - Data Match Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_MIER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MIER_DMIE_SHIFT)) & LPI2C_MIER_DMIE_MASK)
/*! @} */
/*! @name MDER - Master DMA Enable */
/*! @{ */
#define LPI2C_MDER_TDDE_MASK (0x1U)
#define LPI2C_MDER_TDDE_SHIFT (0U)
/*! TDDE - Transmit Data DMA Enable
* 0b0..DMA request is disabled
* 0b1..DMA request is enabled
*/
#define LPI2C_MDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_TDDE_SHIFT)) & LPI2C_MDER_TDDE_MASK)
#define LPI2C_MDER_RDDE_MASK (0x2U)
#define LPI2C_MDER_RDDE_SHIFT (1U)
/*! RDDE - Receive Data DMA Enable
* 0b0..DMA request is disabled
* 0b1..DMA request is enabled
*/
#define LPI2C_MDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDER_RDDE_SHIFT)) & LPI2C_MDER_RDDE_MASK)
/*! @} */
/*! @name MCFGR0 - Master Configuration 0 */
/*! @{ */
#define LPI2C_MCFGR0_HREN_MASK (0x1U)
#define LPI2C_MCFGR0_HREN_SHIFT (0U)
/*! HREN - Host Request Enable
* 0b0..Host request input is disabled
* 0b1..Host request input is enabled
*/
#define LPI2C_MCFGR0_HREN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HREN_SHIFT)) & LPI2C_MCFGR0_HREN_MASK)
#define LPI2C_MCFGR0_HRPOL_MASK (0x2U)
#define LPI2C_MCFGR0_HRPOL_SHIFT (1U)
/*! HRPOL - Host Request Polarity
* 0b0..Active low
* 0b1..Active high
*/
#define LPI2C_MCFGR0_HRPOL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRPOL_SHIFT)) & LPI2C_MCFGR0_HRPOL_MASK)
#define LPI2C_MCFGR0_HRSEL_MASK (0x4U)
#define LPI2C_MCFGR0_HRSEL_SHIFT (2U)
/*! HRSEL - Host Request Select
* 0b0..Host request input is pin HREQ
* 0b1..Host request input is input trigger
*/
#define LPI2C_MCFGR0_HRSEL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_HRSEL_SHIFT)) & LPI2C_MCFGR0_HRSEL_MASK)
#define LPI2C_MCFGR0_CIRFIFO_MASK (0x100U)
#define LPI2C_MCFGR0_CIRFIFO_SHIFT (8U)
/*! CIRFIFO - Circular FIFO Enable
* 0b0..Circular FIFO is disabled
* 0b1..Circular FIFO is enabled
*/
#define LPI2C_MCFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_CIRFIFO_SHIFT)) & LPI2C_MCFGR0_CIRFIFO_MASK)
#define LPI2C_MCFGR0_RDMO_MASK (0x200U)
#define LPI2C_MCFGR0_RDMO_SHIFT (9U)
/*! RDMO - Receive Data Match Only
* 0b0..Received data is stored in the receive FIFO
* 0b1..Received data is discarded unless the the Data Match Flag (MSR[DMF]) is set
*/
#define LPI2C_MCFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR0_RDMO_SHIFT)) & LPI2C_MCFGR0_RDMO_MASK)
/*! @} */
/*! @name MCFGR1 - Master Configuration 1 */
/*! @{ */
#define LPI2C_MCFGR1_PRESCALE_MASK (0x7U)
#define LPI2C_MCFGR1_PRESCALE_SHIFT (0U)
/*! PRESCALE - Prescaler
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 4
* 0b011..Divide by 8
* 0b100..Divide by 16
* 0b101..Divide by 32
* 0b110..Divide by 64
* 0b111..Divide by 128
*/
#define LPI2C_MCFGR1_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PRESCALE_SHIFT)) & LPI2C_MCFGR1_PRESCALE_MASK)
#define LPI2C_MCFGR1_AUTOSTOP_MASK (0x100U)
#define LPI2C_MCFGR1_AUTOSTOP_SHIFT (8U)
/*! AUTOSTOP - Automatic STOP Generation
* 0b0..No effect
* 0b1..STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy
*/
#define LPI2C_MCFGR1_AUTOSTOP(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_AUTOSTOP_SHIFT)) & LPI2C_MCFGR1_AUTOSTOP_MASK)
#define LPI2C_MCFGR1_IGNACK_MASK (0x200U)
#define LPI2C_MCFGR1_IGNACK_SHIFT (9U)
/*! IGNACK - IGNACK
* 0b0..LPI2C Master receives ACK and NACK normally
* 0b1..LPI2C Master treats a received NACK as if it (NACK) was an ACK
*/
#define LPI2C_MCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_IGNACK_SHIFT)) & LPI2C_MCFGR1_IGNACK_MASK)
#define LPI2C_MCFGR1_TIMECFG_MASK (0x400U)
#define LPI2C_MCFGR1_TIMECFG_SHIFT (10U)
/*! TIMECFG - Timeout Configuration
* 0b0..MSR[PLTF] sets if SCL is low for longer than the configured timeout
* 0b1..MSR[PLTF] sets if either SCL or SDA is low for longer than the configured timeout
*/
#define LPI2C_MCFGR1_TIMECFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_TIMECFG_SHIFT)) & LPI2C_MCFGR1_TIMECFG_MASK)
#define LPI2C_MCFGR1_MATCFG_MASK (0x70000U)
#define LPI2C_MCFGR1_MATCFG_SHIFT (16U)
/*! MATCFG - Match Configuration
* 0b000..Match is disabled
* 0b001..Reserved
* 0b010..Match is enabled (1st data word equals MDMR[MATCH0] OR MDMR[MATCH1])
* 0b011..Match is enabled (any data word equals MDMR[MATCH0] OR MDMR[MATCH1])
* 0b100..Match is enabled (1st data word equals MDMR[MATCH0] AND 2nd data word equals MDMR[MATCH1)
* 0b101..Match is enabled (any data word equals MDMR[MATCH0] AND next data word equals MDMR[MATCH1)
* 0b110..Match is enabled (1st data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
* 0b111..Match is enabled (any data word AND MDMR[MATCH1] equals MDMR[MATCH0] AND MDMR[MATCH1])
*/
#define LPI2C_MCFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_MATCFG_SHIFT)) & LPI2C_MCFGR1_MATCFG_MASK)
#define LPI2C_MCFGR1_PINCFG_MASK (0x7000000U)
#define LPI2C_MCFGR1_PINCFG_SHIFT (24U)
/*! PINCFG - Pin Configuration
* 0b000..2-pin open drain mode
* 0b001..2-pin output only mode (ultra-fast mode)
* 0b010..2-pin push-pull mode
* 0b011..4-pin push-pull mode
* 0b100..2-pin open drain mode with separate LPI2C slave
* 0b101..2-pin output only mode (ultra-fast mode) with separate LPI2C slave
* 0b110..2-pin push-pull mode with separate LPI2C slave
* 0b111..4-pin push-pull mode (inverted outputs)
*/
#define LPI2C_MCFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR1_PINCFG_SHIFT)) & LPI2C_MCFGR1_PINCFG_MASK)
/*! @} */
/*! @name MCFGR2 - Master Configuration 2 */
/*! @{ */
#define LPI2C_MCFGR2_BUSIDLE_MASK (0xFFFU)
#define LPI2C_MCFGR2_BUSIDLE_SHIFT (0U)
/*! BUSIDLE - Bus Idle Timeout
*/
#define LPI2C_MCFGR2_BUSIDLE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_BUSIDLE_SHIFT)) & LPI2C_MCFGR2_BUSIDLE_MASK)
#define LPI2C_MCFGR2_FILTSCL_MASK (0xF0000U)
#define LPI2C_MCFGR2_FILTSCL_SHIFT (16U)
/*! FILTSCL - Glitch Filter SCL
*/
#define LPI2C_MCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSCL_SHIFT)) & LPI2C_MCFGR2_FILTSCL_MASK)
#define LPI2C_MCFGR2_FILTSDA_MASK (0xF000000U)
#define LPI2C_MCFGR2_FILTSDA_SHIFT (24U)
/*! FILTSDA - Glitch Filter SDA
*/
#define LPI2C_MCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR2_FILTSDA_SHIFT)) & LPI2C_MCFGR2_FILTSDA_MASK)
/*! @} */
/*! @name MCFGR3 - Master Configuration 3 */
/*! @{ */
#define LPI2C_MCFGR3_PINLOW_MASK (0xFFF00U)
#define LPI2C_MCFGR3_PINLOW_SHIFT (8U)
/*! PINLOW - Pin Low Timeout
*/
#define LPI2C_MCFGR3_PINLOW(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCFGR3_PINLOW_SHIFT)) & LPI2C_MCFGR3_PINLOW_MASK)
/*! @} */
/*! @name MDMR - Master Data Match */
/*! @{ */
#define LPI2C_MDMR_MATCH0_MASK (0xFFU)
#define LPI2C_MDMR_MATCH0_SHIFT (0U)
/*! MATCH0 - Match 0 Value
*/
#define LPI2C_MDMR_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH0_SHIFT)) & LPI2C_MDMR_MATCH0_MASK)
#define LPI2C_MDMR_MATCH1_MASK (0xFF0000U)
#define LPI2C_MDMR_MATCH1_SHIFT (16U)
/*! MATCH1 - Match 1 Value
*/
#define LPI2C_MDMR_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MDMR_MATCH1_SHIFT)) & LPI2C_MDMR_MATCH1_MASK)
/*! @} */
/*! @name MCCR0 - Master Clock Configuration 0 */
/*! @{ */
#define LPI2C_MCCR0_CLKLO_MASK (0x3FU)
#define LPI2C_MCCR0_CLKLO_SHIFT (0U)
/*! CLKLO - Clock Low Period
*/
#define LPI2C_MCCR0_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKLO_SHIFT)) & LPI2C_MCCR0_CLKLO_MASK)
#define LPI2C_MCCR0_CLKHI_MASK (0x3F00U)
#define LPI2C_MCCR0_CLKHI_SHIFT (8U)
/*! CLKHI - Clock High Period
*/
#define LPI2C_MCCR0_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_CLKHI_SHIFT)) & LPI2C_MCCR0_CLKHI_MASK)
#define LPI2C_MCCR0_SETHOLD_MASK (0x3F0000U)
#define LPI2C_MCCR0_SETHOLD_SHIFT (16U)
/*! SETHOLD - Setup Hold Delay
*/
#define LPI2C_MCCR0_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_SETHOLD_SHIFT)) & LPI2C_MCCR0_SETHOLD_MASK)
#define LPI2C_MCCR0_DATAVD_MASK (0x3F000000U)
#define LPI2C_MCCR0_DATAVD_SHIFT (24U)
/*! DATAVD - Data Valid Delay
*/
#define LPI2C_MCCR0_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR0_DATAVD_SHIFT)) & LPI2C_MCCR0_DATAVD_MASK)
/*! @} */
/*! @name MCCR1 - Master Clock Configuration 1 */
/*! @{ */
#define LPI2C_MCCR1_CLKLO_MASK (0x3FU)
#define LPI2C_MCCR1_CLKLO_SHIFT (0U)
/*! CLKLO - Clock Low Period
*/
#define LPI2C_MCCR1_CLKLO(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKLO_SHIFT)) & LPI2C_MCCR1_CLKLO_MASK)
#define LPI2C_MCCR1_CLKHI_MASK (0x3F00U)
#define LPI2C_MCCR1_CLKHI_SHIFT (8U)
/*! CLKHI - Clock High Period
*/
#define LPI2C_MCCR1_CLKHI(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_CLKHI_SHIFT)) & LPI2C_MCCR1_CLKHI_MASK)
#define LPI2C_MCCR1_SETHOLD_MASK (0x3F0000U)
#define LPI2C_MCCR1_SETHOLD_SHIFT (16U)
/*! SETHOLD - Setup Hold Delay
*/
#define LPI2C_MCCR1_SETHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_SETHOLD_SHIFT)) & LPI2C_MCCR1_SETHOLD_MASK)
#define LPI2C_MCCR1_DATAVD_MASK (0x3F000000U)
#define LPI2C_MCCR1_DATAVD_SHIFT (24U)
/*! DATAVD - Data Valid Delay
*/
#define LPI2C_MCCR1_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MCCR1_DATAVD_SHIFT)) & LPI2C_MCCR1_DATAVD_MASK)
/*! @} */
/*! @name MFCR - Master FIFO Control */
/*! @{ */
#define LPI2C_MFCR_TXWATER_MASK (0x3U)
#define LPI2C_MFCR_TXWATER_SHIFT (0U)
/*! TXWATER - Transmit FIFO Watermark
*/
#define LPI2C_MFCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_TXWATER_SHIFT)) & LPI2C_MFCR_TXWATER_MASK)
#define LPI2C_MFCR_RXWATER_MASK (0x30000U)
#define LPI2C_MFCR_RXWATER_SHIFT (16U)
/*! RXWATER - Receive FIFO Watermark
*/
#define LPI2C_MFCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFCR_RXWATER_SHIFT)) & LPI2C_MFCR_RXWATER_MASK)
/*! @} */
/*! @name MFSR - Master FIFO Status */
/*! @{ */
#define LPI2C_MFSR_TXCOUNT_MASK (0x7U)
#define LPI2C_MFSR_TXCOUNT_SHIFT (0U)
/*! TXCOUNT - Transmit FIFO Count
*/
#define LPI2C_MFSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_TXCOUNT_SHIFT)) & LPI2C_MFSR_TXCOUNT_MASK)
#define LPI2C_MFSR_RXCOUNT_MASK (0x70000U)
#define LPI2C_MFSR_RXCOUNT_SHIFT (16U)
/*! RXCOUNT - Receive FIFO Count
*/
#define LPI2C_MFSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MFSR_RXCOUNT_SHIFT)) & LPI2C_MFSR_RXCOUNT_MASK)
/*! @} */
/*! @name MTDR - Master Transmit Data */
/*! @{ */
#define LPI2C_MTDR_DATA_MASK (0xFFU)
#define LPI2C_MTDR_DATA_SHIFT (0U)
/*! DATA - Transmit Data
*/
#define LPI2C_MTDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_DATA_SHIFT)) & LPI2C_MTDR_DATA_MASK)
#define LPI2C_MTDR_CMD_MASK (0x700U)
#define LPI2C_MTDR_CMD_SHIFT (8U)
/*! CMD - Command Data
* 0b000..Transmit DATA[7:0]
* 0b001..Receive (DATA[7:0] + 1) bytes
* 0b010..Generate STOP condition
* 0b011..Receive and discard (DATA[7:0] + 1) bytes
* 0b100..Generate (repeated) START and transmit address in DATA[7:0]
* 0b101..Generate (repeated) START and transmit address in DATA[7:0]. This transfer expects a NACK to be returned.
* 0b110..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode
* 0b111..Generate (repeated) START and transmit address in DATA[7:0] using high speed mode. This transfer expects a NACK to be returned.
*/
#define LPI2C_MTDR_CMD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MTDR_CMD_SHIFT)) & LPI2C_MTDR_CMD_MASK)
/*! @} */
/*! @name MRDR - Master Receive Data */
/*! @{ */
#define LPI2C_MRDR_DATA_MASK (0xFFU)
#define LPI2C_MRDR_DATA_SHIFT (0U)
/*! DATA - Receive Data
*/
#define LPI2C_MRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_DATA_SHIFT)) & LPI2C_MRDR_DATA_MASK)
#define LPI2C_MRDR_RXEMPTY_MASK (0x4000U)
#define LPI2C_MRDR_RXEMPTY_SHIFT (14U)
/*! RXEMPTY - RX Empty
* 0b0..Receive FIFO is not empty
* 0b1..Receive FIFO is empty
*/
#define LPI2C_MRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_MRDR_RXEMPTY_SHIFT)) & LPI2C_MRDR_RXEMPTY_MASK)
/*! @} */
/*! @name SCR - Slave Control */
/*! @{ */
#define LPI2C_SCR_SEN_MASK (0x1U)
#define LPI2C_SCR_SEN_SHIFT (0U)
/*! SEN - Slave Enable
* 0b0..I2C Slave mode is disabled
* 0b1..I2C Slave mode is enabled
*/
#define LPI2C_SCR_SEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_SEN_SHIFT)) & LPI2C_SCR_SEN_MASK)
#define LPI2C_SCR_RST_MASK (0x2U)
#define LPI2C_SCR_RST_SHIFT (1U)
/*! RST - Software Reset
* 0b0..Slave mode logic is not reset
* 0b1..Slave mode logic is reset
*/
#define LPI2C_SCR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RST_SHIFT)) & LPI2C_SCR_RST_MASK)
#define LPI2C_SCR_FILTEN_MASK (0x10U)
#define LPI2C_SCR_FILTEN_SHIFT (4U)
/*! FILTEN - Filter Enable
* 0b0..Disable digital filter and output delay counter for slave mode
* 0b1..Enable digital filter and output delay counter for slave mode
*/
#define LPI2C_SCR_FILTEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTEN_SHIFT)) & LPI2C_SCR_FILTEN_MASK)
#define LPI2C_SCR_FILTDZ_MASK (0x20U)
#define LPI2C_SCR_FILTDZ_SHIFT (5U)
/*! FILTDZ - Filter Doze Enable
* 0b0..Filter remains enabled in Doze mode
* 0b1..Filter is disabled in Doze mode
*/
#define LPI2C_SCR_FILTDZ(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_FILTDZ_SHIFT)) & LPI2C_SCR_FILTDZ_MASK)
#define LPI2C_SCR_RTF_MASK (0x100U)
#define LPI2C_SCR_RTF_SHIFT (8U)
/*! RTF - Reset Transmit FIFO
* 0b0..No effect
* 0b1..Transmit Data Register is now empty
*/
#define LPI2C_SCR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RTF_SHIFT)) & LPI2C_SCR_RTF_MASK)
#define LPI2C_SCR_RRF_MASK (0x200U)
#define LPI2C_SCR_RRF_SHIFT (9U)
/*! RRF - Reset Receive FIFO
* 0b0..No effect
* 0b1..Receive Data Register is now empty
*/
#define LPI2C_SCR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCR_RRF_SHIFT)) & LPI2C_SCR_RRF_MASK)
/*! @} */
/*! @name SSR - Slave Status */
/*! @{ */
#define LPI2C_SSR_TDF_MASK (0x1U)
#define LPI2C_SSR_TDF_SHIFT (0U)
/*! TDF - Transmit Data Flag
* 0b0..Transmit data not requested
* 0b1..Transmit data is requested
*/
#define LPI2C_SSR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TDF_SHIFT)) & LPI2C_SSR_TDF_MASK)
#define LPI2C_SSR_RDF_MASK (0x2U)
#define LPI2C_SSR_RDF_SHIFT (1U)
/*! RDF - Receive Data Flag
* 0b0..Receive data is not ready
* 0b1..Receive data is ready
*/
#define LPI2C_SSR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RDF_SHIFT)) & LPI2C_SSR_RDF_MASK)
#define LPI2C_SSR_AVF_MASK (0x4U)
#define LPI2C_SSR_AVF_SHIFT (2U)
/*! AVF - Address Valid Flag
* 0b0..Address Status Register is not valid
* 0b1..Address Status Register is valid
*/
#define LPI2C_SSR_AVF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AVF_SHIFT)) & LPI2C_SSR_AVF_MASK)
#define LPI2C_SSR_TAF_MASK (0x8U)
#define LPI2C_SSR_TAF_SHIFT (3U)
/*! TAF - Transmit ACK Flag
* 0b0..Transmit ACK/NACK is not required
* 0b1..Transmit ACK/NACK is required
*/
#define LPI2C_SSR_TAF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_TAF_SHIFT)) & LPI2C_SSR_TAF_MASK)
#define LPI2C_SSR_RSF_MASK (0x100U)
#define LPI2C_SSR_RSF_SHIFT (8U)
/*! RSF - Repeated Start Flag
* 0b0..Slave has not detected a Repeated START condition
* 0b1..Slave has detected a Repeated START condition
*/
#define LPI2C_SSR_RSF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_RSF_SHIFT)) & LPI2C_SSR_RSF_MASK)
#define LPI2C_SSR_SDF_MASK (0x200U)
#define LPI2C_SSR_SDF_SHIFT (9U)
/*! SDF - STOP Detect Flag
* 0b0..Slave has not detected a STOP condition
* 0b1..Slave has detected a STOP condition
*/
#define LPI2C_SSR_SDF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SDF_SHIFT)) & LPI2C_SSR_SDF_MASK)
#define LPI2C_SSR_BEF_MASK (0x400U)
#define LPI2C_SSR_BEF_SHIFT (10U)
/*! BEF - Bit Error Flag
* 0b0..Slave has not detected a bit error
* 0b1..Slave has detected a bit error
*/
#define LPI2C_SSR_BEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BEF_SHIFT)) & LPI2C_SSR_BEF_MASK)
#define LPI2C_SSR_FEF_MASK (0x800U)
#define LPI2C_SSR_FEF_SHIFT (11U)
/*! FEF - FIFO Error Flag
* 0b0..FIFO underflow or overflow was not detected
* 0b1..FIFO underflow or overflow was detected
*/
#define LPI2C_SSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_FEF_SHIFT)) & LPI2C_SSR_FEF_MASK)
#define LPI2C_SSR_AM0F_MASK (0x1000U)
#define LPI2C_SSR_AM0F_SHIFT (12U)
/*! AM0F - Address Match 0 Flag
* 0b0..Have not received an ADDR0 matching address
* 0b1..Have received an ADDR0 matching address
*/
#define LPI2C_SSR_AM0F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM0F_SHIFT)) & LPI2C_SSR_AM0F_MASK)
#define LPI2C_SSR_AM1F_MASK (0x2000U)
#define LPI2C_SSR_AM1F_SHIFT (13U)
/*! AM1F - Address Match 1 Flag
* 0b0..Have not received an ADDR1 or ADDR0/ADDR1 range matching address
* 0b1..Have received an ADDR1 or ADDR0/ADDR1 range matching address
*/
#define LPI2C_SSR_AM1F(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_AM1F_SHIFT)) & LPI2C_SSR_AM1F_MASK)
#define LPI2C_SSR_GCF_MASK (0x4000U)
#define LPI2C_SSR_GCF_SHIFT (14U)
/*! GCF - General Call Flag
* 0b0..Slave has not detected the General Call Address or the General Call Address is disabled
* 0b1..Slave has detected the General Call Address
*/
#define LPI2C_SSR_GCF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_GCF_SHIFT)) & LPI2C_SSR_GCF_MASK)
#define LPI2C_SSR_SARF_MASK (0x8000U)
#define LPI2C_SSR_SARF_SHIFT (15U)
/*! SARF - SMBus Alert Response Flag
* 0b0..SMBus Alert Response is disabled or not detected
* 0b1..SMBus Alert Response is enabled and detected
*/
#define LPI2C_SSR_SARF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SARF_SHIFT)) & LPI2C_SSR_SARF_MASK)
#define LPI2C_SSR_SBF_MASK (0x1000000U)
#define LPI2C_SSR_SBF_SHIFT (24U)
/*! SBF - Slave Busy Flag
* 0b0..I2C Slave is idle
* 0b1..I2C Slave is busy
*/
#define LPI2C_SSR_SBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_SBF_SHIFT)) & LPI2C_SSR_SBF_MASK)
#define LPI2C_SSR_BBF_MASK (0x2000000U)
#define LPI2C_SSR_BBF_SHIFT (25U)
/*! BBF - Bus Busy Flag
* 0b0..I2C Bus is idle
* 0b1..I2C Bus is busy
*/
#define LPI2C_SSR_BBF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SSR_BBF_SHIFT)) & LPI2C_SSR_BBF_MASK)
/*! @} */
/*! @name SIER - Slave Interrupt Enable */
/*! @{ */
#define LPI2C_SIER_TDIE_MASK (0x1U)
#define LPI2C_SIER_TDIE_SHIFT (0U)
/*! TDIE - Transmit Data Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TDIE_SHIFT)) & LPI2C_SIER_TDIE_MASK)
#define LPI2C_SIER_RDIE_MASK (0x2U)
#define LPI2C_SIER_RDIE_SHIFT (1U)
/*! RDIE - Receive Data Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RDIE_SHIFT)) & LPI2C_SIER_RDIE_MASK)
#define LPI2C_SIER_AVIE_MASK (0x4U)
#define LPI2C_SIER_AVIE_SHIFT (2U)
/*! AVIE - Address Valid Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_AVIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AVIE_SHIFT)) & LPI2C_SIER_AVIE_MASK)
#define LPI2C_SIER_TAIE_MASK (0x8U)
#define LPI2C_SIER_TAIE_SHIFT (3U)
/*! TAIE - Transmit ACK Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_TAIE_SHIFT)) & LPI2C_SIER_TAIE_MASK)
#define LPI2C_SIER_RSIE_MASK (0x100U)
#define LPI2C_SIER_RSIE_SHIFT (8U)
/*! RSIE - Repeated Start Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_RSIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_RSIE_SHIFT)) & LPI2C_SIER_RSIE_MASK)
#define LPI2C_SIER_SDIE_MASK (0x200U)
#define LPI2C_SIER_SDIE_SHIFT (9U)
/*! SDIE - STOP Detect Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_SDIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SDIE_SHIFT)) & LPI2C_SIER_SDIE_MASK)
#define LPI2C_SIER_BEIE_MASK (0x400U)
#define LPI2C_SIER_BEIE_SHIFT (10U)
/*! BEIE - Bit Error Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_BEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_BEIE_SHIFT)) & LPI2C_SIER_BEIE_MASK)
#define LPI2C_SIER_FEIE_MASK (0x800U)
#define LPI2C_SIER_FEIE_SHIFT (11U)
/*! FEIE - FIFO Error Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_FEIE_SHIFT)) & LPI2C_SIER_FEIE_MASK)
#define LPI2C_SIER_AM0IE_MASK (0x1000U)
#define LPI2C_SIER_AM0IE_SHIFT (12U)
/*! AM0IE - Address Match 0 Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_AM0IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM0IE_SHIFT)) & LPI2C_SIER_AM0IE_MASK)
#define LPI2C_SIER_AM1IE_MASK (0x2000U)
#define LPI2C_SIER_AM1IE_SHIFT (13U)
/*! AM1IE - Address Match 1 Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_AM1IE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_AM1IE_SHIFT)) & LPI2C_SIER_AM1IE_MASK)
#define LPI2C_SIER_GCIE_MASK (0x4000U)
#define LPI2C_SIER_GCIE_SHIFT (14U)
/*! GCIE - General Call Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_GCIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_GCIE_SHIFT)) & LPI2C_SIER_GCIE_MASK)
#define LPI2C_SIER_SARIE_MASK (0x8000U)
#define LPI2C_SIER_SARIE_SHIFT (15U)
/*! SARIE - SMBus Alert Response Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPI2C_SIER_SARIE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SIER_SARIE_SHIFT)) & LPI2C_SIER_SARIE_MASK)
/*! @} */
/*! @name SDER - Slave DMA Enable */
/*! @{ */
#define LPI2C_SDER_TDDE_MASK (0x1U)
#define LPI2C_SDER_TDDE_SHIFT (0U)
/*! TDDE - Transmit Data DMA Enable
* 0b0..DMA request is disabled
* 0b1..DMA request is enabled
*/
#define LPI2C_SDER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_TDDE_SHIFT)) & LPI2C_SDER_TDDE_MASK)
#define LPI2C_SDER_RDDE_MASK (0x2U)
#define LPI2C_SDER_RDDE_SHIFT (1U)
/*! RDDE - Receive Data DMA Enable
* 0b0..DMA request is disabled
* 0b1..DMA request is enabled
*/
#define LPI2C_SDER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_RDDE_SHIFT)) & LPI2C_SDER_RDDE_MASK)
#define LPI2C_SDER_AVDE_MASK (0x4U)
#define LPI2C_SDER_AVDE_SHIFT (2U)
/*! AVDE - Address Valid DMA Enable
* 0b0..DMA request is disabled
* 0b1..DMA request is enabled
*/
#define LPI2C_SDER_AVDE(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SDER_AVDE_SHIFT)) & LPI2C_SDER_AVDE_MASK)
/*! @} */
/*! @name SCFGR1 - Slave Configuration 1 */
/*! @{ */
#define LPI2C_SCFGR1_ADRSTALL_MASK (0x1U)
#define LPI2C_SCFGR1_ADRSTALL_SHIFT (0U)
/*! ADRSTALL - Address SCL Stall
* 0b0..Clock stretching is disabled
* 0b1..Clock stretching is enabled
*/
#define LPI2C_SCFGR1_ADRSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADRSTALL_SHIFT)) & LPI2C_SCFGR1_ADRSTALL_MASK)
#define LPI2C_SCFGR1_RXSTALL_MASK (0x2U)
#define LPI2C_SCFGR1_RXSTALL_SHIFT (1U)
/*! RXSTALL - RX SCL Stall
* 0b0..Clock stretching is disabled
* 0b1..Clock stretching is enabled
*/
#define LPI2C_SCFGR1_RXSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXSTALL_SHIFT)) & LPI2C_SCFGR1_RXSTALL_MASK)
#define LPI2C_SCFGR1_TXDSTALL_MASK (0x4U)
#define LPI2C_SCFGR1_TXDSTALL_SHIFT (2U)
/*! TXDSTALL - TX Data SCL Stall
* 0b0..Clock stretching is disabled
* 0b1..Clock stretching is enabled
*/
#define LPI2C_SCFGR1_TXDSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXDSTALL_SHIFT)) & LPI2C_SCFGR1_TXDSTALL_MASK)
#define LPI2C_SCFGR1_ACKSTALL_MASK (0x8U)
#define LPI2C_SCFGR1_ACKSTALL_SHIFT (3U)
/*! ACKSTALL - ACK SCL Stall
* 0b0..Clock stretching is disabled
* 0b1..Clock stretching is enabled
*/
#define LPI2C_SCFGR1_ACKSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ACKSTALL_SHIFT)) & LPI2C_SCFGR1_ACKSTALL_MASK)
#define LPI2C_SCFGR1_GCEN_MASK (0x100U)
#define LPI2C_SCFGR1_GCEN_SHIFT (8U)
/*! GCEN - General Call Enable
* 0b0..General Call address is disabled
* 0b1..General Call address is enabled
*/
#define LPI2C_SCFGR1_GCEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_GCEN_SHIFT)) & LPI2C_SCFGR1_GCEN_MASK)
#define LPI2C_SCFGR1_SAEN_MASK (0x200U)
#define LPI2C_SCFGR1_SAEN_SHIFT (9U)
/*! SAEN - SMBus Alert Enable
* 0b0..Disables match on SMBus Alert
* 0b1..Enables match on SMBus Alert
*/
#define LPI2C_SCFGR1_SAEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_SAEN_SHIFT)) & LPI2C_SCFGR1_SAEN_MASK)
#define LPI2C_SCFGR1_TXCFG_MASK (0x400U)
#define LPI2C_SCFGR1_TXCFG_SHIFT (10U)
/*! TXCFG - Transmit Flag Configuration
* 0b0..Transmit Data Flag only asserts during a slave-transmit transfer when the Transmit Data register is empty
* 0b1..Transmit Data Flag asserts whenever the Transmit Data register is empty
*/
#define LPI2C_SCFGR1_TXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_TXCFG_SHIFT)) & LPI2C_SCFGR1_TXCFG_MASK)
#define LPI2C_SCFGR1_RXCFG_MASK (0x800U)
#define LPI2C_SCFGR1_RXCFG_SHIFT (11U)
/*! RXCFG - Receive Data Configuration
* 0b0..Reading the Receive Data register returns received data and clears the Receive Data flag (MSR[RDF]).
* 0b1..Reading the Receive Data register when the Address Valid flag (SSR[AVF])is set, returns the Address
* Status register and clear the Address Valid flag. Reading the Receive Data register when the Address Valid flag
* is clear, returns received data and clears the Receive Data flag (MSR[RDF]).
*/
#define LPI2C_SCFGR1_RXCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_RXCFG_SHIFT)) & LPI2C_SCFGR1_RXCFG_MASK)
#define LPI2C_SCFGR1_IGNACK_MASK (0x1000U)
#define LPI2C_SCFGR1_IGNACK_SHIFT (12U)
/*! IGNACK - Ignore NACK
* 0b0..Slave ends transfer when NACK is detected
* 0b1..Slave does not end transfer when NACK detected
*/
#define LPI2C_SCFGR1_IGNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_IGNACK_SHIFT)) & LPI2C_SCFGR1_IGNACK_MASK)
#define LPI2C_SCFGR1_HSMEN_MASK (0x2000U)
#define LPI2C_SCFGR1_HSMEN_SHIFT (13U)
/*! HSMEN - High Speed Mode Enable
* 0b0..Disables detection of HS-mode master code
* 0b1..Enables detection of HS-mode master code
*/
#define LPI2C_SCFGR1_HSMEN(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_HSMEN_SHIFT)) & LPI2C_SCFGR1_HSMEN_MASK)
#define LPI2C_SCFGR1_ADDRCFG_MASK (0x70000U)
#define LPI2C_SCFGR1_ADDRCFG_SHIFT (16U)
/*! ADDRCFG - Address Configuration
* 0b000..Address match 0 (7-bit)
* 0b001..Address match 0 (10-bit)
* 0b010..Address match 0 (7-bit) or Address match 1 (7-bit)
* 0b011..Address match 0 (10-bit) or Address match 1 (10-bit)
* 0b100..Address match 0 (7-bit) or Address match 1 (10-bit)
* 0b101..Address match 0 (10-bit) or Address match 1 (7-bit)
* 0b110..From Address match 0 (7-bit) to Address match 1 (7-bit)
* 0b111..From Address match 0 (10-bit) to Address match 1 (10-bit)
*/
#define LPI2C_SCFGR1_ADDRCFG(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR1_ADDRCFG_SHIFT)) & LPI2C_SCFGR1_ADDRCFG_MASK)
/*! @} */
/*! @name SCFGR2 - Slave Configuration 2 */
/*! @{ */
#define LPI2C_SCFGR2_CLKHOLD_MASK (0xFU)
#define LPI2C_SCFGR2_CLKHOLD_SHIFT (0U)
/*! CLKHOLD - Clock Hold Time
*/
#define LPI2C_SCFGR2_CLKHOLD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_CLKHOLD_SHIFT)) & LPI2C_SCFGR2_CLKHOLD_MASK)
#define LPI2C_SCFGR2_DATAVD_MASK (0x3F00U)
#define LPI2C_SCFGR2_DATAVD_SHIFT (8U)
/*! DATAVD - Data Valid Delay
*/
#define LPI2C_SCFGR2_DATAVD(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_DATAVD_SHIFT)) & LPI2C_SCFGR2_DATAVD_MASK)
#define LPI2C_SCFGR2_FILTSCL_MASK (0xF0000U)
#define LPI2C_SCFGR2_FILTSCL_SHIFT (16U)
/*! FILTSCL - Glitch Filter SCL
*/
#define LPI2C_SCFGR2_FILTSCL(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSCL_SHIFT)) & LPI2C_SCFGR2_FILTSCL_MASK)
#define LPI2C_SCFGR2_FILTSDA_MASK (0xF000000U)
#define LPI2C_SCFGR2_FILTSDA_SHIFT (24U)
/*! FILTSDA - Glitch Filter SDA
*/
#define LPI2C_SCFGR2_FILTSDA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SCFGR2_FILTSDA_SHIFT)) & LPI2C_SCFGR2_FILTSDA_MASK)
/*! @} */
/*! @name SAMR - Slave Address Match */
/*! @{ */
#define LPI2C_SAMR_ADDR0_MASK (0x7FEU)
#define LPI2C_SAMR_ADDR0_SHIFT (1U)
/*! ADDR0 - Address 0 Value
*/
#define LPI2C_SAMR_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR0_SHIFT)) & LPI2C_SAMR_ADDR0_MASK)
#define LPI2C_SAMR_ADDR1_MASK (0x7FE0000U)
#define LPI2C_SAMR_ADDR1_SHIFT (17U)
/*! ADDR1 - Address 1 Value
*/
#define LPI2C_SAMR_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SAMR_ADDR1_SHIFT)) & LPI2C_SAMR_ADDR1_MASK)
/*! @} */
/*! @name SASR - Slave Address Status */
/*! @{ */
#define LPI2C_SASR_RADDR_MASK (0x7FFU)
#define LPI2C_SASR_RADDR_SHIFT (0U)
/*! RADDR - Received Address
*/
#define LPI2C_SASR_RADDR(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_RADDR_SHIFT)) & LPI2C_SASR_RADDR_MASK)
#define LPI2C_SASR_ANV_MASK (0x4000U)
#define LPI2C_SASR_ANV_SHIFT (14U)
/*! ANV - Address Not Valid
* 0b0..Received Address (RADDR) is valid
* 0b1..Received Address (RADDR) is not valid
*/
#define LPI2C_SASR_ANV(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SASR_ANV_SHIFT)) & LPI2C_SASR_ANV_MASK)
/*! @} */
/*! @name STAR - Slave Transmit ACK */
/*! @{ */
#define LPI2C_STAR_TXNACK_MASK (0x1U)
#define LPI2C_STAR_TXNACK_SHIFT (0U)
/*! TXNACK - Transmit NACK
* 0b0..Write a Transmit ACK for each received word
* 0b1..Write a Transmit NACK for each received word
*/
#define LPI2C_STAR_TXNACK(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STAR_TXNACK_SHIFT)) & LPI2C_STAR_TXNACK_MASK)
/*! @} */
/*! @name STDR - Slave Transmit Data */
/*! @{ */
#define LPI2C_STDR_DATA_MASK (0xFFU)
#define LPI2C_STDR_DATA_SHIFT (0U)
/*! DATA - Transmit Data
*/
#define LPI2C_STDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_STDR_DATA_SHIFT)) & LPI2C_STDR_DATA_MASK)
/*! @} */
/*! @name SRDR - Slave Receive Data */
/*! @{ */
#define LPI2C_SRDR_DATA_MASK (0xFFU)
#define LPI2C_SRDR_DATA_SHIFT (0U)
/*! DATA - Receive Data
*/
#define LPI2C_SRDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_DATA_SHIFT)) & LPI2C_SRDR_DATA_MASK)
#define LPI2C_SRDR_RXEMPTY_MASK (0x4000U)
#define LPI2C_SRDR_RXEMPTY_SHIFT (14U)
/*! RXEMPTY - RX Empty
* 0b0..The Receive Data Register is not empty
* 0b1..The Receive Data Register is empty
*/
#define LPI2C_SRDR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_RXEMPTY_SHIFT)) & LPI2C_SRDR_RXEMPTY_MASK)
#define LPI2C_SRDR_SOF_MASK (0x8000U)
#define LPI2C_SRDR_SOF_SHIFT (15U)
/*! SOF - Start Of Frame
* 0b0..Indicates this is not the first data word since a (repeated) START or STOP condition
* 0b1..Indicates this is the first data word since a (repeated) START or STOP condition
*/
#define LPI2C_SRDR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPI2C_SRDR_SOF_SHIFT)) & LPI2C_SRDR_SOF_MASK)
/*! @} */
/*!
* @}
*/ /* end of group LPI2C_Register_Masks */
/* LPI2C - Peripheral instance base addresses */
/** Peripheral LPI2C1 base address */
#define LPI2C1_BASE (0x40104000u)
/** Peripheral LPI2C1 base pointer */
#define LPI2C1 ((LPI2C_Type *)LPI2C1_BASE)
/** Peripheral LPI2C2 base address */
#define LPI2C2_BASE (0x40108000u)
/** Peripheral LPI2C2 base pointer */
#define LPI2C2 ((LPI2C_Type *)LPI2C2_BASE)
/** Peripheral LPI2C3 base address */
#define LPI2C3_BASE (0x4010C000u)
/** Peripheral LPI2C3 base pointer */
#define LPI2C3 ((LPI2C_Type *)LPI2C3_BASE)
/** Peripheral LPI2C4 base address */
#define LPI2C4_BASE (0x40110000u)
/** Peripheral LPI2C4 base pointer */
#define LPI2C4 ((LPI2C_Type *)LPI2C4_BASE)
/** Peripheral LPI2C5 base address */
#define LPI2C5_BASE (0x40C34000u)
/** Peripheral LPI2C5 base pointer */
#define LPI2C5 ((LPI2C_Type *)LPI2C5_BASE)
/** Peripheral LPI2C6 base address */
#define LPI2C6_BASE (0x40C38000u)
/** Peripheral LPI2C6 base pointer */
#define LPI2C6 ((LPI2C_Type *)LPI2C6_BASE)
/** Array initializer of LPI2C peripheral base addresses */
#define LPI2C_BASE_ADDRS { 0u, LPI2C1_BASE, LPI2C2_BASE, LPI2C3_BASE, LPI2C4_BASE, LPI2C5_BASE, LPI2C6_BASE }
/** Array initializer of LPI2C peripheral base pointers */
#define LPI2C_BASE_PTRS { (LPI2C_Type *)0u, LPI2C1, LPI2C2, LPI2C3, LPI2C4, LPI2C5, LPI2C6 }
/** Interrupt vectors for the LPI2C peripheral type */
#define LPI2C_IRQS { NotAvail_IRQn, LPI2C1_IRQn, LPI2C2_IRQn, LPI2C3_IRQn, LPI2C4_IRQn, LPI2C5_IRQn, LPI2C6_IRQn }
/*!
* @}
*/ /* end of group LPI2C_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPSPI Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPSPI_Peripheral_Access_Layer LPSPI Peripheral Access Layer
* @{
*/
/** LPSPI - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t CR; /**< Control, offset: 0x10 */
__IO uint32_t SR; /**< Status, offset: 0x14 */
__IO uint32_t IER; /**< Interrupt Enable, offset: 0x18 */
__IO uint32_t DER; /**< DMA Enable, offset: 0x1C */
__IO uint32_t CFGR0; /**< Configuration 0, offset: 0x20 */
__IO uint32_t CFGR1; /**< Configuration 1, offset: 0x24 */
uint8_t RESERVED_1[8];
__IO uint32_t DMR0; /**< Data Match 0, offset: 0x30 */
__IO uint32_t DMR1; /**< Data Match 1, offset: 0x34 */
uint8_t RESERVED_2[8];
__IO uint32_t CCR; /**< Clock Configuration, offset: 0x40 */
uint8_t RESERVED_3[20];
__IO uint32_t FCR; /**< FIFO Control, offset: 0x58 */
__I uint32_t FSR; /**< FIFO Status, offset: 0x5C */
__IO uint32_t TCR; /**< Transmit Command, offset: 0x60 */
__O uint32_t TDR; /**< Transmit Data, offset: 0x64 */
uint8_t RESERVED_4[8];
__I uint32_t RSR; /**< Receive Status, offset: 0x70 */
__I uint32_t RDR; /**< Receive Data, offset: 0x74 */
} LPSPI_Type;
/* ----------------------------------------------------------------------------
-- LPSPI Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPSPI_Register_Masks LPSPI Register Masks
* @{
*/
/*! @name VERID - Version ID */
/*! @{ */
#define LPSPI_VERID_FEATURE_MASK (0xFFFFU)
#define LPSPI_VERID_FEATURE_SHIFT (0U)
/*! FEATURE - Module Identification Number
* 0b0000000000000100..Standard feature set supporting a 32-bit shift register.
*/
#define LPSPI_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_FEATURE_SHIFT)) & LPSPI_VERID_FEATURE_MASK)
#define LPSPI_VERID_MINOR_MASK (0xFF0000U)
#define LPSPI_VERID_MINOR_SHIFT (16U)
/*! MINOR - Minor Version Number
*/
#define LPSPI_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MINOR_SHIFT)) & LPSPI_VERID_MINOR_MASK)
#define LPSPI_VERID_MAJOR_MASK (0xFF000000U)
#define LPSPI_VERID_MAJOR_SHIFT (24U)
/*! MAJOR - Major Version Number
*/
#define LPSPI_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_VERID_MAJOR_SHIFT)) & LPSPI_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter */
/*! @{ */
#define LPSPI_PARAM_TXFIFO_MASK (0xFFU)
#define LPSPI_PARAM_TXFIFO_SHIFT (0U)
/*! TXFIFO - Transmit FIFO Size
*/
#define LPSPI_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_TXFIFO_SHIFT)) & LPSPI_PARAM_TXFIFO_MASK)
#define LPSPI_PARAM_RXFIFO_MASK (0xFF00U)
#define LPSPI_PARAM_RXFIFO_SHIFT (8U)
/*! RXFIFO - Receive FIFO Size
*/
#define LPSPI_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_RXFIFO_SHIFT)) & LPSPI_PARAM_RXFIFO_MASK)
#define LPSPI_PARAM_PCSNUM_MASK (0xFF0000U)
#define LPSPI_PARAM_PCSNUM_SHIFT (16U)
/*! PCSNUM - PCS Number
*/
#define LPSPI_PARAM_PCSNUM(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_PARAM_PCSNUM_SHIFT)) & LPSPI_PARAM_PCSNUM_MASK)
/*! @} */
/*! @name CR - Control */
/*! @{ */
#define LPSPI_CR_MEN_MASK (0x1U)
#define LPSPI_CR_MEN_SHIFT (0U)
/*! MEN - Module Enable
* 0b0..Module is disabled
* 0b1..Module is enabled
*/
#define LPSPI_CR_MEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_MEN_SHIFT)) & LPSPI_CR_MEN_MASK)
#define LPSPI_CR_RST_MASK (0x2U)
#define LPSPI_CR_RST_SHIFT (1U)
/*! RST - Software Reset
* 0b0..Module is not reset
* 0b1..Module is reset
*/
#define LPSPI_CR_RST(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RST_SHIFT)) & LPSPI_CR_RST_MASK)
#define LPSPI_CR_DOZEN_MASK (0x4U)
#define LPSPI_CR_DOZEN_SHIFT (2U)
/*! DOZEN - Doze Mode Enable
* 0b0..LPSPI module is enabled in Doze mode
* 0b1..LPSPI module is disabled in Doze mode
*/
#define LPSPI_CR_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DOZEN_SHIFT)) & LPSPI_CR_DOZEN_MASK)
#define LPSPI_CR_DBGEN_MASK (0x8U)
#define LPSPI_CR_DBGEN_SHIFT (3U)
/*! DBGEN - Debug Enable
* 0b0..LPSPI module is disabled in debug mode
* 0b1..LPSPI module is enabled in debug mode
*/
#define LPSPI_CR_DBGEN(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_DBGEN_SHIFT)) & LPSPI_CR_DBGEN_MASK)
#define LPSPI_CR_RTF_MASK (0x100U)
#define LPSPI_CR_RTF_SHIFT (8U)
/*! RTF - Reset Transmit FIFO
* 0b0..No effect
* 0b1..Reset the Transmit FIFO. The register bit always reads zero.
*/
#define LPSPI_CR_RTF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RTF_SHIFT)) & LPSPI_CR_RTF_MASK)
#define LPSPI_CR_RRF_MASK (0x200U)
#define LPSPI_CR_RRF_SHIFT (9U)
/*! RRF - Reset Receive FIFO
* 0b0..No effect
* 0b1..Reset the Receive FIFO. The register bit always reads zero.
*/
#define LPSPI_CR_RRF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CR_RRF_SHIFT)) & LPSPI_CR_RRF_MASK)
/*! @} */
/*! @name SR - Status */
/*! @{ */
#define LPSPI_SR_TDF_MASK (0x1U)
#define LPSPI_SR_TDF_SHIFT (0U)
/*! TDF - Transmit Data Flag
* 0b0..Transmit data not requested
* 0b1..Transmit data is requested
*/
#define LPSPI_SR_TDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TDF_SHIFT)) & LPSPI_SR_TDF_MASK)
#define LPSPI_SR_RDF_MASK (0x2U)
#define LPSPI_SR_RDF_SHIFT (1U)
/*! RDF - Receive Data Flag
* 0b0..Receive Data is not ready
* 0b1..Receive data is ready
*/
#define LPSPI_SR_RDF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_RDF_SHIFT)) & LPSPI_SR_RDF_MASK)
#define LPSPI_SR_WCF_MASK (0x100U)
#define LPSPI_SR_WCF_SHIFT (8U)
/*! WCF - Word Complete Flag
* 0b0..Transfer of a received word has not yet completed
* 0b1..Transfer of a received word has completed
*/
#define LPSPI_SR_WCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_WCF_SHIFT)) & LPSPI_SR_WCF_MASK)
#define LPSPI_SR_FCF_MASK (0x200U)
#define LPSPI_SR_FCF_SHIFT (9U)
/*! FCF - Frame Complete Flag
* 0b0..Frame transfer has not completed
* 0b1..Frame transfer has completed
*/
#define LPSPI_SR_FCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_FCF_SHIFT)) & LPSPI_SR_FCF_MASK)
#define LPSPI_SR_TCF_MASK (0x400U)
#define LPSPI_SR_TCF_SHIFT (10U)
/*! TCF - Transfer Complete Flag
* 0b0..All transfers have not completed
* 0b1..All transfers have completed
*/
#define LPSPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TCF_SHIFT)) & LPSPI_SR_TCF_MASK)
#define LPSPI_SR_TEF_MASK (0x800U)
#define LPSPI_SR_TEF_SHIFT (11U)
/*! TEF - Transmit Error Flag
* 0b0..Transmit FIFO underrun has not occurred
* 0b1..Transmit FIFO underrun has occurred
*/
#define LPSPI_SR_TEF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_TEF_SHIFT)) & LPSPI_SR_TEF_MASK)
#define LPSPI_SR_REF_MASK (0x1000U)
#define LPSPI_SR_REF_SHIFT (12U)
/*! REF - Receive Error Flag
* 0b0..Receive FIFO has not overflowed
* 0b1..Receive FIFO has overflowed
*/
#define LPSPI_SR_REF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_REF_SHIFT)) & LPSPI_SR_REF_MASK)
#define LPSPI_SR_DMF_MASK (0x2000U)
#define LPSPI_SR_DMF_SHIFT (13U)
/*! DMF - Data Match Flag
* 0b0..Have not received matching data
* 0b1..Have received matching data
*/
#define LPSPI_SR_DMF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_DMF_SHIFT)) & LPSPI_SR_DMF_MASK)
#define LPSPI_SR_MBF_MASK (0x1000000U)
#define LPSPI_SR_MBF_SHIFT (24U)
/*! MBF - Module Busy Flag
* 0b0..LPSPI is idle
* 0b1..LPSPI is busy
*/
#define LPSPI_SR_MBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_SR_MBF_SHIFT)) & LPSPI_SR_MBF_MASK)
/*! @} */
/*! @name IER - Interrupt Enable */
/*! @{ */
#define LPSPI_IER_TDIE_MASK (0x1U)
#define LPSPI_IER_TDIE_SHIFT (0U)
/*! TDIE - Transmit Data Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPSPI_IER_TDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TDIE_SHIFT)) & LPSPI_IER_TDIE_MASK)
#define LPSPI_IER_RDIE_MASK (0x2U)
#define LPSPI_IER_RDIE_SHIFT (1U)
/*! RDIE - Receive Data Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPSPI_IER_RDIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_RDIE_SHIFT)) & LPSPI_IER_RDIE_MASK)
#define LPSPI_IER_WCIE_MASK (0x100U)
#define LPSPI_IER_WCIE_SHIFT (8U)
/*! WCIE - Word Complete Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPSPI_IER_WCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_WCIE_SHIFT)) & LPSPI_IER_WCIE_MASK)
#define LPSPI_IER_FCIE_MASK (0x200U)
#define LPSPI_IER_FCIE_SHIFT (9U)
/*! FCIE - Frame Complete Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPSPI_IER_FCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_FCIE_SHIFT)) & LPSPI_IER_FCIE_MASK)
#define LPSPI_IER_TCIE_MASK (0x400U)
#define LPSPI_IER_TCIE_SHIFT (10U)
/*! TCIE - Transfer Complete Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPSPI_IER_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TCIE_SHIFT)) & LPSPI_IER_TCIE_MASK)
#define LPSPI_IER_TEIE_MASK (0x800U)
#define LPSPI_IER_TEIE_SHIFT (11U)
/*! TEIE - Transmit Error Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPSPI_IER_TEIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_TEIE_SHIFT)) & LPSPI_IER_TEIE_MASK)
#define LPSPI_IER_REIE_MASK (0x1000U)
#define LPSPI_IER_REIE_SHIFT (12U)
/*! REIE - Receive Error Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPSPI_IER_REIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_REIE_SHIFT)) & LPSPI_IER_REIE_MASK)
#define LPSPI_IER_DMIE_MASK (0x2000U)
#define LPSPI_IER_DMIE_SHIFT (13U)
/*! DMIE - Data Match Interrupt Enable
* 0b0..Disabled
* 0b1..Enabled
*/
#define LPSPI_IER_DMIE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_IER_DMIE_SHIFT)) & LPSPI_IER_DMIE_MASK)
/*! @} */
/*! @name DER - DMA Enable */
/*! @{ */
#define LPSPI_DER_TDDE_MASK (0x1U)
#define LPSPI_DER_TDDE_SHIFT (0U)
/*! TDDE - Transmit Data DMA Enable
* 0b0..DMA request is disabled
* 0b1..DMA request is enabled
*/
#define LPSPI_DER_TDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_TDDE_SHIFT)) & LPSPI_DER_TDDE_MASK)
#define LPSPI_DER_RDDE_MASK (0x2U)
#define LPSPI_DER_RDDE_SHIFT (1U)
/*! RDDE - Receive Data DMA Enable
* 0b0..DMA request is disabled
* 0b1..DMA request is enabled
*/
#define LPSPI_DER_RDDE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DER_RDDE_SHIFT)) & LPSPI_DER_RDDE_MASK)
/*! @} */
/*! @name CFGR0 - Configuration 0 */
/*! @{ */
#define LPSPI_CFGR0_CIRFIFO_MASK (0x100U)
#define LPSPI_CFGR0_CIRFIFO_SHIFT (8U)
/*! CIRFIFO - Circular FIFO Enable
* 0b0..Circular FIFO is disabled
* 0b1..Circular FIFO is enabled
*/
#define LPSPI_CFGR0_CIRFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_CIRFIFO_SHIFT)) & LPSPI_CFGR0_CIRFIFO_MASK)
#define LPSPI_CFGR0_RDMO_MASK (0x200U)
#define LPSPI_CFGR0_RDMO_SHIFT (9U)
/*! RDMO - Receive Data Match Only
* 0b0..Received data is stored in the receive FIFO as in normal operations
* 0b1..Received data is discarded unless the SR[DMF] = 1
*/
#define LPSPI_CFGR0_RDMO(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR0_RDMO_SHIFT)) & LPSPI_CFGR0_RDMO_MASK)
/*! @} */
/*! @name CFGR1 - Configuration 1 */
/*! @{ */
#define LPSPI_CFGR1_MASTER_MASK (0x1U)
#define LPSPI_CFGR1_MASTER_SHIFT (0U)
/*! MASTER - Master Mode
* 0b0..Slave mode
* 0b1..Master mode
*/
#define LPSPI_CFGR1_MASTER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MASTER_SHIFT)) & LPSPI_CFGR1_MASTER_MASK)
#define LPSPI_CFGR1_SAMPLE_MASK (0x2U)
#define LPSPI_CFGR1_SAMPLE_SHIFT (1U)
/*! SAMPLE - Sample Point
* 0b0..Input data is sampled on SCK edge
* 0b1..Input data is sampled on delayed SCK edge
*/
#define LPSPI_CFGR1_SAMPLE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_SAMPLE_SHIFT)) & LPSPI_CFGR1_SAMPLE_MASK)
#define LPSPI_CFGR1_AUTOPCS_MASK (0x4U)
#define LPSPI_CFGR1_AUTOPCS_SHIFT (2U)
/*! AUTOPCS - Automatic PCS
* 0b0..Automatic PCS generation is disabled
* 0b1..Automatic PCS generation is enabled
*/
#define LPSPI_CFGR1_AUTOPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_AUTOPCS_SHIFT)) & LPSPI_CFGR1_AUTOPCS_MASK)
#define LPSPI_CFGR1_NOSTALL_MASK (0x8U)
#define LPSPI_CFGR1_NOSTALL_SHIFT (3U)
/*! NOSTALL - No Stall
* 0b0..Transfers stall when the transmit FIFO is empty
* 0b1..Transfers do not stall, allowing transmit FIFO underruns to occur
*/
#define LPSPI_CFGR1_NOSTALL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_NOSTALL_SHIFT)) & LPSPI_CFGR1_NOSTALL_MASK)
#define LPSPI_CFGR1_PCSPOL_MASK (0xF00U)
#define LPSPI_CFGR1_PCSPOL_SHIFT (8U)
/*! PCSPOL - Peripheral Chip Select Polarity
*/
#define LPSPI_CFGR1_PCSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSPOL_SHIFT)) & LPSPI_CFGR1_PCSPOL_MASK)
#define LPSPI_CFGR1_MATCFG_MASK (0x70000U)
#define LPSPI_CFGR1_MATCFG_SHIFT (16U)
/*! MATCFG - Match Configuration
* 0b000..Match is disabled
* 0b001..Reserved
* 0b010..Match is enabled is 1st data word is MATCH0 or MATCH1
* 0b011..Match is enabled on any data word equal MATCH0 or MATCH1
* 0b100..Match is enabled on data match sequence
* 0b101..Match is enabled on data match sequence
* 0b110..Match is enabled
* 0b111..Match is enabled
*/
#define LPSPI_CFGR1_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_MATCFG_SHIFT)) & LPSPI_CFGR1_MATCFG_MASK)
#define LPSPI_CFGR1_PINCFG_MASK (0x3000000U)
#define LPSPI_CFGR1_PINCFG_SHIFT (24U)
/*! PINCFG - Pin Configuration
* 0b00..SIN is used for input data and SOUT is used for output data
* 0b01..SIN is used for both input and output data, only half-duplex serial transfers are supported
* 0b10..SOUT is used for both input and output data, only half-duplex serial transfers are supported
* 0b11..SOUT is used for input data and SIN is used for output data
*/
#define LPSPI_CFGR1_PINCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PINCFG_SHIFT)) & LPSPI_CFGR1_PINCFG_MASK)
#define LPSPI_CFGR1_OUTCFG_MASK (0x4000000U)
#define LPSPI_CFGR1_OUTCFG_SHIFT (26U)
/*! OUTCFG - Output Configuration
* 0b0..Output data retains last value when chip select is negated
* 0b1..Output data is tristated when chip select is negated
*/
#define LPSPI_CFGR1_OUTCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_OUTCFG_SHIFT)) & LPSPI_CFGR1_OUTCFG_MASK)
#define LPSPI_CFGR1_PCSCFG_MASK (0x8000000U)
#define LPSPI_CFGR1_PCSCFG_SHIFT (27U)
/*! PCSCFG - Peripheral Chip Select Configuration
* 0b0..PCS[3:2] are configured for chip select function
* 0b1..PCS[3:2] are configured for half-duplex 4-bit transfers (PCS[3:2] = DATA[3:2])
*/
#define LPSPI_CFGR1_PCSCFG(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CFGR1_PCSCFG_SHIFT)) & LPSPI_CFGR1_PCSCFG_MASK)
/*! @} */
/*! @name DMR0 - Data Match 0 */
/*! @{ */
#define LPSPI_DMR0_MATCH0_MASK (0xFFFFFFFFU)
#define LPSPI_DMR0_MATCH0_SHIFT (0U)
/*! MATCH0 - Match 0 Value
*/
#define LPSPI_DMR0_MATCH0(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR0_MATCH0_SHIFT)) & LPSPI_DMR0_MATCH0_MASK)
/*! @} */
/*! @name DMR1 - Data Match 1 */
/*! @{ */
#define LPSPI_DMR1_MATCH1_MASK (0xFFFFFFFFU)
#define LPSPI_DMR1_MATCH1_SHIFT (0U)
/*! MATCH1 - Match 1 Value
*/
#define LPSPI_DMR1_MATCH1(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_DMR1_MATCH1_SHIFT)) & LPSPI_DMR1_MATCH1_MASK)
/*! @} */
/*! @name CCR - Clock Configuration */
/*! @{ */
#define LPSPI_CCR_SCKDIV_MASK (0xFFU)
#define LPSPI_CCR_SCKDIV_SHIFT (0U)
/*! SCKDIV - SCK Divider
*/
#define LPSPI_CCR_SCKDIV(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKDIV_SHIFT)) & LPSPI_CCR_SCKDIV_MASK)
#define LPSPI_CCR_DBT_MASK (0xFF00U)
#define LPSPI_CCR_DBT_SHIFT (8U)
/*! DBT - Delay Between Transfers
*/
#define LPSPI_CCR_DBT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_DBT_SHIFT)) & LPSPI_CCR_DBT_MASK)
#define LPSPI_CCR_PCSSCK_MASK (0xFF0000U)
#define LPSPI_CCR_PCSSCK_SHIFT (16U)
/*! PCSSCK - PCS-to-SCK Delay
*/
#define LPSPI_CCR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_PCSSCK_SHIFT)) & LPSPI_CCR_PCSSCK_MASK)
#define LPSPI_CCR_SCKPCS_MASK (0xFF000000U)
#define LPSPI_CCR_SCKPCS_SHIFT (24U)
/*! SCKPCS - SCK-to-PCS Delay
*/
#define LPSPI_CCR_SCKPCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_CCR_SCKPCS_SHIFT)) & LPSPI_CCR_SCKPCS_MASK)
/*! @} */
/*! @name FCR - FIFO Control */
/*! @{ */
#define LPSPI_FCR_TXWATER_MASK (0xFU)
#define LPSPI_FCR_TXWATER_SHIFT (0U)
/*! TXWATER - Transmit FIFO Watermark
*/
#define LPSPI_FCR_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_TXWATER_SHIFT)) & LPSPI_FCR_TXWATER_MASK)
#define LPSPI_FCR_RXWATER_MASK (0xF0000U)
#define LPSPI_FCR_RXWATER_SHIFT (16U)
/*! RXWATER - Receive FIFO Watermark
*/
#define LPSPI_FCR_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FCR_RXWATER_SHIFT)) & LPSPI_FCR_RXWATER_MASK)
/*! @} */
/*! @name FSR - FIFO Status */
/*! @{ */
#define LPSPI_FSR_TXCOUNT_MASK (0x1FU)
#define LPSPI_FSR_TXCOUNT_SHIFT (0U)
/*! TXCOUNT - Transmit FIFO Count
*/
#define LPSPI_FSR_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_TXCOUNT_SHIFT)) & LPSPI_FSR_TXCOUNT_MASK)
#define LPSPI_FSR_RXCOUNT_MASK (0x1F0000U)
#define LPSPI_FSR_RXCOUNT_SHIFT (16U)
/*! RXCOUNT - Receive FIFO Count
*/
#define LPSPI_FSR_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_FSR_RXCOUNT_SHIFT)) & LPSPI_FSR_RXCOUNT_MASK)
/*! @} */
/*! @name TCR - Transmit Command */
/*! @{ */
#define LPSPI_TCR_FRAMESZ_MASK (0xFFFU)
#define LPSPI_TCR_FRAMESZ_SHIFT (0U)
/*! FRAMESZ - Frame Size
*/
#define LPSPI_TCR_FRAMESZ(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_FRAMESZ_SHIFT)) & LPSPI_TCR_FRAMESZ_MASK)
#define LPSPI_TCR_WIDTH_MASK (0x30000U)
#define LPSPI_TCR_WIDTH_SHIFT (16U)
/*! WIDTH - Transfer Width
* 0b00..1 bit transfer
* 0b01..2 bit transfer
* 0b10..4 bit transfer
* 0b11..Reserved
*/
#define LPSPI_TCR_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_WIDTH_SHIFT)) & LPSPI_TCR_WIDTH_MASK)
#define LPSPI_TCR_TXMSK_MASK (0x40000U)
#define LPSPI_TCR_TXMSK_SHIFT (18U)
/*! TXMSK - Transmit Data Mask
* 0b0..Normal transfer
* 0b1..Mask transmit data
*/
#define LPSPI_TCR_TXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_TXMSK_SHIFT)) & LPSPI_TCR_TXMSK_MASK)
#define LPSPI_TCR_RXMSK_MASK (0x80000U)
#define LPSPI_TCR_RXMSK_SHIFT (19U)
/*! RXMSK - Receive Data Mask
* 0b0..Normal transfer
* 0b1..Receive data is masked
*/
#define LPSPI_TCR_RXMSK(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_RXMSK_SHIFT)) & LPSPI_TCR_RXMSK_MASK)
#define LPSPI_TCR_CONTC_MASK (0x100000U)
#define LPSPI_TCR_CONTC_SHIFT (20U)
/*! CONTC - Continuing Command
* 0b0..Command word for start of new transfer
* 0b1..Command word for continuing transfer
*/
#define LPSPI_TCR_CONTC(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONTC_SHIFT)) & LPSPI_TCR_CONTC_MASK)
#define LPSPI_TCR_CONT_MASK (0x200000U)
#define LPSPI_TCR_CONT_SHIFT (21U)
/*! CONT - Continuous Transfer
* 0b0..Continuous transfer is disabled
* 0b1..Continuous transfer is enabled
*/
#define LPSPI_TCR_CONT(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CONT_SHIFT)) & LPSPI_TCR_CONT_MASK)
#define LPSPI_TCR_BYSW_MASK (0x400000U)
#define LPSPI_TCR_BYSW_SHIFT (22U)
/*! BYSW - Byte Swap
* 0b0..Byte swap is disabled
* 0b1..Byte swap is enabled
*/
#define LPSPI_TCR_BYSW(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_BYSW_SHIFT)) & LPSPI_TCR_BYSW_MASK)
#define LPSPI_TCR_LSBF_MASK (0x800000U)
#define LPSPI_TCR_LSBF_SHIFT (23U)
/*! LSBF - LSB First
* 0b0..Data is transferred MSB first
* 0b1..Data is transferred LSB first
*/
#define LPSPI_TCR_LSBF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_LSBF_SHIFT)) & LPSPI_TCR_LSBF_MASK)
#define LPSPI_TCR_PCS_MASK (0x3000000U)
#define LPSPI_TCR_PCS_SHIFT (24U)
/*! PCS - Peripheral Chip Select
* 0b00..Transfer using PCS[0]
* 0b01..Transfer using PCS[1]
* 0b10..Transfer using PCS[2]
* 0b11..Transfer using PCS[3]
*/
#define LPSPI_TCR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PCS_SHIFT)) & LPSPI_TCR_PCS_MASK)
#define LPSPI_TCR_PRESCALE_MASK (0x38000000U)
#define LPSPI_TCR_PRESCALE_SHIFT (27U)
/*! PRESCALE - Prescaler Value
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 4
* 0b011..Divide by 8
* 0b100..Divide by 16
* 0b101..Divide by 32
* 0b110..Divide by 64
* 0b111..Divide by 128
*/
#define LPSPI_TCR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_PRESCALE_SHIFT)) & LPSPI_TCR_PRESCALE_MASK)
#define LPSPI_TCR_CPHA_MASK (0x40000000U)
#define LPSPI_TCR_CPHA_SHIFT (30U)
/*! CPHA - Clock Phase
* 0b0..Captured
* 0b1..Changed
*/
#define LPSPI_TCR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPHA_SHIFT)) & LPSPI_TCR_CPHA_MASK)
#define LPSPI_TCR_CPOL_MASK (0x80000000U)
#define LPSPI_TCR_CPOL_SHIFT (31U)
/*! CPOL - Clock Polarity
* 0b0..The inactive state value of SCK is low
* 0b1..The inactive state value of SCK is high
*/
#define LPSPI_TCR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TCR_CPOL_SHIFT)) & LPSPI_TCR_CPOL_MASK)
/*! @} */
/*! @name TDR - Transmit Data */
/*! @{ */
#define LPSPI_TDR_DATA_MASK (0xFFFFFFFFU)
#define LPSPI_TDR_DATA_SHIFT (0U)
/*! DATA - Transmit Data
*/
#define LPSPI_TDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_TDR_DATA_SHIFT)) & LPSPI_TDR_DATA_MASK)
/*! @} */
/*! @name RSR - Receive Status */
/*! @{ */
#define LPSPI_RSR_SOF_MASK (0x1U)
#define LPSPI_RSR_SOF_SHIFT (0U)
/*! SOF - Start Of Frame
* 0b0..Subsequent data word received after PCS assertion
* 0b1..First data word received after PCS assertion
*/
#define LPSPI_RSR_SOF(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_SOF_SHIFT)) & LPSPI_RSR_SOF_MASK)
#define LPSPI_RSR_RXEMPTY_MASK (0x2U)
#define LPSPI_RSR_RXEMPTY_SHIFT (1U)
/*! RXEMPTY - RX FIFO Empty
* 0b0..RX FIFO is not empty
* 0b1..RX FIFO is empty
*/
#define LPSPI_RSR_RXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RSR_RXEMPTY_SHIFT)) & LPSPI_RSR_RXEMPTY_MASK)
/*! @} */
/*! @name RDR - Receive Data */
/*! @{ */
#define LPSPI_RDR_DATA_MASK (0xFFFFFFFFU)
#define LPSPI_RDR_DATA_SHIFT (0U)
/*! DATA - Receive Data
*/
#define LPSPI_RDR_DATA(x) (((uint32_t)(((uint32_t)(x)) << LPSPI_RDR_DATA_SHIFT)) & LPSPI_RDR_DATA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group LPSPI_Register_Masks */
/* LPSPI - Peripheral instance base addresses */
/** Peripheral LPSPI1 base address */
#define LPSPI1_BASE (0x40114000u)
/** Peripheral LPSPI1 base pointer */
#define LPSPI1 ((LPSPI_Type *)LPSPI1_BASE)
/** Peripheral LPSPI2 base address */
#define LPSPI2_BASE (0x40118000u)
/** Peripheral LPSPI2 base pointer */
#define LPSPI2 ((LPSPI_Type *)LPSPI2_BASE)
/** Peripheral LPSPI3 base address */
#define LPSPI3_BASE (0x4011C000u)
/** Peripheral LPSPI3 base pointer */
#define LPSPI3 ((LPSPI_Type *)LPSPI3_BASE)
/** Peripheral LPSPI4 base address */
#define LPSPI4_BASE (0x40120000u)
/** Peripheral LPSPI4 base pointer */
#define LPSPI4 ((LPSPI_Type *)LPSPI4_BASE)
/** Peripheral LPSPI5 base address */
#define LPSPI5_BASE (0x40C2C000u)
/** Peripheral LPSPI5 base pointer */
#define LPSPI5 ((LPSPI_Type *)LPSPI5_BASE)
/** Peripheral LPSPI6 base address */
#define LPSPI6_BASE (0x40C30000u)
/** Peripheral LPSPI6 base pointer */
#define LPSPI6 ((LPSPI_Type *)LPSPI6_BASE)
/** Array initializer of LPSPI peripheral base addresses */
#define LPSPI_BASE_ADDRS { 0u, LPSPI1_BASE, LPSPI2_BASE, LPSPI3_BASE, LPSPI4_BASE, LPSPI5_BASE, LPSPI6_BASE }
/** Array initializer of LPSPI peripheral base pointers */
#define LPSPI_BASE_PTRS { (LPSPI_Type *)0u, LPSPI1, LPSPI2, LPSPI3, LPSPI4, LPSPI5, LPSPI6 }
/** Interrupt vectors for the LPSPI peripheral type */
#define LPSPI_IRQS { NotAvail_IRQn, LPSPI1_IRQn, LPSPI2_IRQn, LPSPI3_IRQn, LPSPI4_IRQn, LPSPI5_IRQn, LPSPI6_IRQn }
/*!
* @}
*/ /* end of group LPSPI_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- LPUART Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Peripheral_Access_Layer LPUART Peripheral Access Layer
* @{
*/
/** LPUART - Register Layout Typedef */
typedef struct {
__I uint32_t VERID; /**< Version ID Register, offset: 0x0 */
__I uint32_t PARAM; /**< Parameter Register, offset: 0x4 */
__IO uint32_t GLOBAL; /**< LPUART Global Register, offset: 0x8 */
__IO uint32_t PINCFG; /**< LPUART Pin Configuration Register, offset: 0xC */
__IO uint32_t BAUD; /**< LPUART Baud Rate Register, offset: 0x10 */
__IO uint32_t STAT; /**< LPUART Status Register, offset: 0x14 */
__IO uint32_t CTRL; /**< LPUART Control Register, offset: 0x18 */
__IO uint32_t DATA; /**< LPUART Data Register, offset: 0x1C */
__IO uint32_t MATCH; /**< LPUART Match Address Register, offset: 0x20 */
__IO uint32_t MODIR; /**< LPUART Modem IrDA Register, offset: 0x24 */
__IO uint32_t FIFO; /**< LPUART FIFO Register, offset: 0x28 */
__IO uint32_t WATER; /**< LPUART Watermark Register, offset: 0x2C */
} LPUART_Type;
/* ----------------------------------------------------------------------------
-- LPUART Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup LPUART_Register_Masks LPUART Register Masks
* @{
*/
/*! @name VERID - Version ID Register */
/*! @{ */
#define LPUART_VERID_FEATURE_MASK (0xFFFFU)
#define LPUART_VERID_FEATURE_SHIFT (0U)
/*! FEATURE - Feature Identification Number
* 0b0000000000000001..Standard feature set.
* 0b0000000000000011..Standard feature set with MODEM/IrDA support.
*/
#define LPUART_VERID_FEATURE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_FEATURE_SHIFT)) & LPUART_VERID_FEATURE_MASK)
#define LPUART_VERID_MINOR_MASK (0xFF0000U)
#define LPUART_VERID_MINOR_SHIFT (16U)
/*! MINOR - Minor Version Number
*/
#define LPUART_VERID_MINOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MINOR_SHIFT)) & LPUART_VERID_MINOR_MASK)
#define LPUART_VERID_MAJOR_MASK (0xFF000000U)
#define LPUART_VERID_MAJOR_SHIFT (24U)
/*! MAJOR - Major Version Number
*/
#define LPUART_VERID_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_VERID_MAJOR_SHIFT)) & LPUART_VERID_MAJOR_MASK)
/*! @} */
/*! @name PARAM - Parameter Register */
/*! @{ */
#define LPUART_PARAM_TXFIFO_MASK (0xFFU)
#define LPUART_PARAM_TXFIFO_SHIFT (0U)
/*! TXFIFO - Transmit FIFO Size
*/
#define LPUART_PARAM_TXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_TXFIFO_SHIFT)) & LPUART_PARAM_TXFIFO_MASK)
#define LPUART_PARAM_RXFIFO_MASK (0xFF00U)
#define LPUART_PARAM_RXFIFO_SHIFT (8U)
/*! RXFIFO - Receive FIFO Size
*/
#define LPUART_PARAM_RXFIFO(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PARAM_RXFIFO_SHIFT)) & LPUART_PARAM_RXFIFO_MASK)
/*! @} */
/*! @name GLOBAL - LPUART Global Register */
/*! @{ */
#define LPUART_GLOBAL_RST_MASK (0x2U)
#define LPUART_GLOBAL_RST_SHIFT (1U)
/*! RST - Software Reset
* 0b0..Module is not reset.
* 0b1..Module is reset.
*/
#define LPUART_GLOBAL_RST(x) (((uint32_t)(((uint32_t)(x)) << LPUART_GLOBAL_RST_SHIFT)) & LPUART_GLOBAL_RST_MASK)
/*! @} */
/*! @name PINCFG - LPUART Pin Configuration Register */
/*! @{ */
#define LPUART_PINCFG_TRGSEL_MASK (0x3U)
#define LPUART_PINCFG_TRGSEL_SHIFT (0U)
/*! TRGSEL - Trigger Select
* 0b00..Input trigger is disabled.
* 0b01..Input trigger is used instead of RXD pin input.
* 0b10..Input trigger is used instead of CTS_B pin input.
* 0b11..Input trigger is used to modulate the TXD pin output. The TXD pin output (after TXINV configuration) is
* internally ANDed with the input trigger.
*/
#define LPUART_PINCFG_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_PINCFG_TRGSEL_SHIFT)) & LPUART_PINCFG_TRGSEL_MASK)
/*! @} */
/*! @name BAUD - LPUART Baud Rate Register */
/*! @{ */
#define LPUART_BAUD_SBR_MASK (0x1FFFU)
#define LPUART_BAUD_SBR_SHIFT (0U)
/*! SBR - Baud Rate Modulo Divisor.
*/
#define LPUART_BAUD_SBR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBR_SHIFT)) & LPUART_BAUD_SBR_MASK)
#define LPUART_BAUD_SBNS_MASK (0x2000U)
#define LPUART_BAUD_SBNS_SHIFT (13U)
/*! SBNS - Stop Bit Number Select
* 0b0..One stop bit.
* 0b1..Two stop bits.
*/
#define LPUART_BAUD_SBNS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_SBNS_SHIFT)) & LPUART_BAUD_SBNS_MASK)
#define LPUART_BAUD_RXEDGIE_MASK (0x4000U)
#define LPUART_BAUD_RXEDGIE_SHIFT (14U)
/*! RXEDGIE - RX Input Active Edge Interrupt Enable
* 0b0..Hardware interrupts from STAT[RXEDGIF] are disabled.
* 0b1..Hardware interrupt is requested when STAT[RXEDGIF] flag is 1.
*/
#define LPUART_BAUD_RXEDGIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RXEDGIE_SHIFT)) & LPUART_BAUD_RXEDGIE_MASK)
#define LPUART_BAUD_LBKDIE_MASK (0x8000U)
#define LPUART_BAUD_LBKDIE_SHIFT (15U)
/*! LBKDIE - LIN Break Detect Interrupt Enable
* 0b0..Hardware interrupts from STAT[LBKDIF] flag are disabled (use polling).
* 0b1..Hardware interrupt is requested when STAT[LBKDIF] flag is 1.
*/
#define LPUART_BAUD_LBKDIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_LBKDIE_SHIFT)) & LPUART_BAUD_LBKDIE_MASK)
#define LPUART_BAUD_RESYNCDIS_MASK (0x10000U)
#define LPUART_BAUD_RESYNCDIS_SHIFT (16U)
/*! RESYNCDIS - Resynchronization Disable
* 0b0..Resynchronization during received data word is supported.
* 0b1..Resynchronization during received data word is disabled.
*/
#define LPUART_BAUD_RESYNCDIS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RESYNCDIS_SHIFT)) & LPUART_BAUD_RESYNCDIS_MASK)
#define LPUART_BAUD_BOTHEDGE_MASK (0x20000U)
#define LPUART_BAUD_BOTHEDGE_SHIFT (17U)
/*! BOTHEDGE - Both Edge Sampling
* 0b0..Receiver samples input data using the rising edge of the baud rate clock.
* 0b1..Receiver samples input data using the rising and falling edge of the baud rate clock.
*/
#define LPUART_BAUD_BOTHEDGE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_BOTHEDGE_SHIFT)) & LPUART_BAUD_BOTHEDGE_MASK)
#define LPUART_BAUD_MATCFG_MASK (0xC0000U)
#define LPUART_BAUD_MATCFG_SHIFT (18U)
/*! MATCFG - Match Configuration
* 0b00..Address Match Wakeup
* 0b01..Idle Match Wakeup
* 0b10..Match On and Match Off
* 0b11..Enables RWU on Data Match and Match On/Off for transmitter CTS input
*/
#define LPUART_BAUD_MATCFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MATCFG_SHIFT)) & LPUART_BAUD_MATCFG_MASK)
#define LPUART_BAUD_RDMAE_MASK (0x200000U)
#define LPUART_BAUD_RDMAE_SHIFT (21U)
/*! RDMAE - Receiver Full DMA Enable
* 0b0..DMA request disabled.
* 0b1..DMA request enabled.
*/
#define LPUART_BAUD_RDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_RDMAE_SHIFT)) & LPUART_BAUD_RDMAE_MASK)
#define LPUART_BAUD_TDMAE_MASK (0x800000U)
#define LPUART_BAUD_TDMAE_SHIFT (23U)
/*! TDMAE - Transmitter DMA Enable
* 0b0..DMA request disabled.
* 0b1..DMA request enabled.
*/
#define LPUART_BAUD_TDMAE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_TDMAE_SHIFT)) & LPUART_BAUD_TDMAE_MASK)
#define LPUART_BAUD_OSR_MASK (0x1F000000U)
#define LPUART_BAUD_OSR_SHIFT (24U)
/*! OSR - Oversampling Ratio
* 0b00000..Writing 0 to this field results in an oversampling ratio of 16
* 0b00001..Reserved
* 0b00010..Reserved
* 0b00011..Oversampling ratio of 4, requires BOTHEDGE to be set.
* 0b00100..Oversampling ratio of 5, requires BOTHEDGE to be set.
* 0b00101..Oversampling ratio of 6, requires BOTHEDGE to be set.
* 0b00110..Oversampling ratio of 7, requires BOTHEDGE to be set.
* 0b00111..Oversampling ratio of 8.
* 0b01000..Oversampling ratio of 9.
* 0b01001..Oversampling ratio of 10.
* 0b01010..Oversampling ratio of 11.
* 0b01011..Oversampling ratio of 12.
* 0b01100..Oversampling ratio of 13.
* 0b01101..Oversampling ratio of 14.
* 0b01110..Oversampling ratio of 15.
* 0b01111..Oversampling ratio of 16.
* 0b10000..Oversampling ratio of 17.
* 0b10001..Oversampling ratio of 18.
* 0b10010..Oversampling ratio of 19.
* 0b10011..Oversampling ratio of 20.
* 0b10100..Oversampling ratio of 21.
* 0b10101..Oversampling ratio of 22.
* 0b10110..Oversampling ratio of 23.
* 0b10111..Oversampling ratio of 24.
* 0b11000..Oversampling ratio of 25.
* 0b11001..Oversampling ratio of 26.
* 0b11010..Oversampling ratio of 27.
* 0b11011..Oversampling ratio of 28.
* 0b11100..Oversampling ratio of 29.
* 0b11101..Oversampling ratio of 30.
* 0b11110..Oversampling ratio of 31.
* 0b11111..Oversampling ratio of 32.
*/
#define LPUART_BAUD_OSR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_OSR_SHIFT)) & LPUART_BAUD_OSR_MASK)
#define LPUART_BAUD_M10_MASK (0x20000000U)
#define LPUART_BAUD_M10_SHIFT (29U)
/*! M10 - 10-bit Mode select
* 0b0..Receiver and transmitter use 7-bit to 9-bit data characters.
* 0b1..Receiver and transmitter use 10-bit data characters.
*/
#define LPUART_BAUD_M10(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_M10_SHIFT)) & LPUART_BAUD_M10_MASK)
#define LPUART_BAUD_MAEN2_MASK (0x40000000U)
#define LPUART_BAUD_MAEN2_SHIFT (30U)
/*! MAEN2 - Match Address Mode Enable 2
* 0b0..Normal operation.
* 0b1..Enables automatic address matching or data matching mode for MATCH[MA2].
*/
#define LPUART_BAUD_MAEN2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN2_SHIFT)) & LPUART_BAUD_MAEN2_MASK)
#define LPUART_BAUD_MAEN1_MASK (0x80000000U)
#define LPUART_BAUD_MAEN1_SHIFT (31U)
/*! MAEN1 - Match Address Mode Enable 1
* 0b0..Normal operation.
* 0b1..Enables automatic address matching or data matching mode for MATCH[MA1].
*/
#define LPUART_BAUD_MAEN1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_BAUD_MAEN1_SHIFT)) & LPUART_BAUD_MAEN1_MASK)
/*! @} */
/*! @name STAT - LPUART Status Register */
/*! @{ */
#define LPUART_STAT_MA2F_MASK (0x4000U)
#define LPUART_STAT_MA2F_SHIFT (14U)
/*! MA2F - Match 2 Flag
* 0b0..Received data is not equal to MA2
* 0b1..Received data is equal to MA2
*/
#define LPUART_STAT_MA2F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA2F_SHIFT)) & LPUART_STAT_MA2F_MASK)
#define LPUART_STAT_MA1F_MASK (0x8000U)
#define LPUART_STAT_MA1F_SHIFT (15U)
/*! MA1F - Match 1 Flag
* 0b0..Received data is not equal to MA1
* 0b1..Received data is equal to MA1
*/
#define LPUART_STAT_MA1F(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MA1F_SHIFT)) & LPUART_STAT_MA1F_MASK)
#define LPUART_STAT_PF_MASK (0x10000U)
#define LPUART_STAT_PF_SHIFT (16U)
/*! PF - Parity Error Flag
* 0b0..No parity error.
* 0b1..Parity error.
*/
#define LPUART_STAT_PF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_PF_SHIFT)) & LPUART_STAT_PF_MASK)
#define LPUART_STAT_FE_MASK (0x20000U)
#define LPUART_STAT_FE_SHIFT (17U)
/*! FE - Framing Error Flag
* 0b0..No framing error detected. This does not guarantee the framing is correct.
* 0b1..Framing error.
*/
#define LPUART_STAT_FE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_FE_SHIFT)) & LPUART_STAT_FE_MASK)
#define LPUART_STAT_NF_MASK (0x40000U)
#define LPUART_STAT_NF_SHIFT (18U)
/*! NF - Noise Flag
* 0b0..No noise detected.
* 0b1..Noise detected in the received character in the DATA register.
*/
#define LPUART_STAT_NF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_NF_SHIFT)) & LPUART_STAT_NF_MASK)
#define LPUART_STAT_OR_MASK (0x80000U)
#define LPUART_STAT_OR_SHIFT (19U)
/*! OR - Receiver Overrun Flag
* 0b0..No overrun.
* 0b1..Receive overrun (new LPUART data lost).
*/
#define LPUART_STAT_OR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_OR_SHIFT)) & LPUART_STAT_OR_MASK)
#define LPUART_STAT_IDLE_MASK (0x100000U)
#define LPUART_STAT_IDLE_SHIFT (20U)
/*! IDLE - Idle Line Flag
* 0b0..No idle line detected.
* 0b1..Idle line is detected.
*/
#define LPUART_STAT_IDLE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_IDLE_SHIFT)) & LPUART_STAT_IDLE_MASK)
#define LPUART_STAT_RDRF_MASK (0x200000U)
#define LPUART_STAT_RDRF_SHIFT (21U)
/*! RDRF - Receive Data Register Full Flag
* 0b0..Receive FIFO level is less than watermark.
* 0b1..Receive FIFO level is equal or greater than watermark.
*/
#define LPUART_STAT_RDRF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RDRF_SHIFT)) & LPUART_STAT_RDRF_MASK)
#define LPUART_STAT_TC_MASK (0x400000U)
#define LPUART_STAT_TC_SHIFT (22U)
/*! TC - Transmission Complete Flag
* 0b0..Transmitter active (sending data, a preamble, or a break).
* 0b1..Transmitter idle (transmission activity complete).
*/
#define LPUART_STAT_TC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TC_SHIFT)) & LPUART_STAT_TC_MASK)
#define LPUART_STAT_TDRE_MASK (0x800000U)
#define LPUART_STAT_TDRE_SHIFT (23U)
/*! TDRE - Transmit Data Register Empty Flag
* 0b0..Transmit FIFO level is greater than watermark.
* 0b1..Transmit FIFO level is equal or less than watermark.
*/
#define LPUART_STAT_TDRE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_TDRE_SHIFT)) & LPUART_STAT_TDRE_MASK)
#define LPUART_STAT_RAF_MASK (0x1000000U)
#define LPUART_STAT_RAF_SHIFT (24U)
/*! RAF - Receiver Active Flag
* 0b0..LPUART receiver idle waiting for a start bit.
* 0b1..LPUART receiver active (RXD input not idle).
*/
#define LPUART_STAT_RAF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RAF_SHIFT)) & LPUART_STAT_RAF_MASK)
#define LPUART_STAT_LBKDE_MASK (0x2000000U)
#define LPUART_STAT_LBKDE_SHIFT (25U)
/*! LBKDE - LIN Break Detection Enable
* 0b0..LIN break detect is disabled, normal break character can be detected.
* 0b1..LIN break detect is enabled. LIN break character is detected at length of 11 bit times (if M = 0) or 12 (if M = 1) or 13 (M10 = 1).
*/
#define LPUART_STAT_LBKDE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDE_SHIFT)) & LPUART_STAT_LBKDE_MASK)
#define LPUART_STAT_BRK13_MASK (0x4000000U)
#define LPUART_STAT_BRK13_SHIFT (26U)
/*! BRK13 - Break Character Generation Length
* 0b0..Break character is transmitted with length of 9 to 13 bit times.
* 0b1..Break character is transmitted with length of 12 to 15 bit times.
*/
#define LPUART_STAT_BRK13(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_BRK13_SHIFT)) & LPUART_STAT_BRK13_MASK)
#define LPUART_STAT_RWUID_MASK (0x8000000U)
#define LPUART_STAT_RWUID_SHIFT (27U)
/*! RWUID - Receive Wake Up Idle Detect
* 0b0..During receive standby state (RWU = 1), the IDLE bit does not get set upon detection of an idle
* character. During address match wakeup, the IDLE bit does not set when an address does not match.
* 0b1..During receive standby state (RWU = 1), the IDLE bit gets set upon detection of an idle character. During
* address match wakeup, the IDLE bit does set when an address does not match.
*/
#define LPUART_STAT_RWUID(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RWUID_SHIFT)) & LPUART_STAT_RWUID_MASK)
#define LPUART_STAT_RXINV_MASK (0x10000000U)
#define LPUART_STAT_RXINV_SHIFT (28U)
/*! RXINV - Receive Data Inversion
* 0b0..Receive data not inverted.
* 0b1..Receive data inverted.
*/
#define LPUART_STAT_RXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXINV_SHIFT)) & LPUART_STAT_RXINV_MASK)
#define LPUART_STAT_MSBF_MASK (0x20000000U)
#define LPUART_STAT_MSBF_SHIFT (29U)
/*! MSBF - MSB First
* 0b0..LSB (bit0) is the first bit that is transmitted following the start bit. Further, the first bit received
* after the start bit is identified as bit0.
* 0b1..MSB (identified as bit9, bit8, bit7 or bit6) is the first bit that is transmitted following the start bit
* depending on the setting of CTRL[M], CTRL[PE] and BAUD[M10]. .
*/
#define LPUART_STAT_MSBF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_MSBF_SHIFT)) & LPUART_STAT_MSBF_MASK)
#define LPUART_STAT_RXEDGIF_MASK (0x40000000U)
#define LPUART_STAT_RXEDGIF_SHIFT (30U)
/*! RXEDGIF - RXD Pin Active Edge Interrupt Flag
* 0b0..No active edge on the receive pin has occurred.
* 0b1..An active edge on the receive pin has occurred.
*/
#define LPUART_STAT_RXEDGIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_RXEDGIF_SHIFT)) & LPUART_STAT_RXEDGIF_MASK)
#define LPUART_STAT_LBKDIF_MASK (0x80000000U)
#define LPUART_STAT_LBKDIF_SHIFT (31U)
/*! LBKDIF - LIN Break Detect Interrupt Flag
* 0b0..No LIN break character has been detected.
* 0b1..LIN break character has been detected.
*/
#define LPUART_STAT_LBKDIF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_STAT_LBKDIF_SHIFT)) & LPUART_STAT_LBKDIF_MASK)
/*! @} */
/*! @name CTRL - LPUART Control Register */
/*! @{ */
#define LPUART_CTRL_PT_MASK (0x1U)
#define LPUART_CTRL_PT_SHIFT (0U)
/*! PT - Parity Type
* 0b0..Even parity.
* 0b1..Odd parity.
*/
#define LPUART_CTRL_PT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PT_SHIFT)) & LPUART_CTRL_PT_MASK)
#define LPUART_CTRL_PE_MASK (0x2U)
#define LPUART_CTRL_PE_SHIFT (1U)
/*! PE - Parity Enable
* 0b0..No hardware parity generation or checking.
* 0b1..Parity enabled.
*/
#define LPUART_CTRL_PE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PE_SHIFT)) & LPUART_CTRL_PE_MASK)
#define LPUART_CTRL_ILT_MASK (0x4U)
#define LPUART_CTRL_ILT_SHIFT (2U)
/*! ILT - Idle Line Type Select
* 0b0..Idle character bit count starts after start bit.
* 0b1..Idle character bit count starts after stop bit.
*/
#define LPUART_CTRL_ILT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILT_SHIFT)) & LPUART_CTRL_ILT_MASK)
#define LPUART_CTRL_WAKE_MASK (0x8U)
#define LPUART_CTRL_WAKE_SHIFT (3U)
/*! WAKE - Receiver Wakeup Method Select
* 0b0..Configures RWU for idle-line wakeup.
* 0b1..Configures RWU with address-mark wakeup.
*/
#define LPUART_CTRL_WAKE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_WAKE_SHIFT)) & LPUART_CTRL_WAKE_MASK)
#define LPUART_CTRL_M_MASK (0x10U)
#define LPUART_CTRL_M_SHIFT (4U)
/*! M - 9-Bit or 8-Bit Mode Select
* 0b0..Receiver and transmitter use 8-bit data characters.
* 0b1..Receiver and transmitter use 9-bit data characters.
*/
#define LPUART_CTRL_M(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M_SHIFT)) & LPUART_CTRL_M_MASK)
#define LPUART_CTRL_RSRC_MASK (0x20U)
#define LPUART_CTRL_RSRC_SHIFT (5U)
/*! RSRC - Receiver Source Select
* 0b0..Provided LOOPS is set, RSRC is cleared, selects internal loop back mode and the LPUART does not use the RXD pin.
* 0b1..Single-wire LPUART mode where the TXD pin is connected to the transmitter output and receiver input.
*/
#define LPUART_CTRL_RSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RSRC_SHIFT)) & LPUART_CTRL_RSRC_MASK)
#define LPUART_CTRL_DOZEEN_MASK (0x40U)
#define LPUART_CTRL_DOZEEN_SHIFT (6U)
/*! DOZEEN - Doze Enable
* 0b0..LPUART is enabled in Doze mode.
* 0b1..LPUART is disabled in Doze mode .
*/
#define LPUART_CTRL_DOZEEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_DOZEEN_SHIFT)) & LPUART_CTRL_DOZEEN_MASK)
#define LPUART_CTRL_LOOPS_MASK (0x80U)
#define LPUART_CTRL_LOOPS_SHIFT (7U)
/*! LOOPS - Loop Mode Select
* 0b0..Normal operation - RXD and TXD use separate pins.
* 0b1..Loop mode or single-wire mode where transmitter outputs are internally connected to receiver input (see RSRC bit).
*/
#define LPUART_CTRL_LOOPS(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_LOOPS_SHIFT)) & LPUART_CTRL_LOOPS_MASK)
#define LPUART_CTRL_IDLECFG_MASK (0x700U)
#define LPUART_CTRL_IDLECFG_SHIFT (8U)
/*! IDLECFG - Idle Configuration
* 0b000..1 idle character
* 0b001..2 idle characters
* 0b010..4 idle characters
* 0b011..8 idle characters
* 0b100..16 idle characters
* 0b101..32 idle characters
* 0b110..64 idle characters
* 0b111..128 idle characters
*/
#define LPUART_CTRL_IDLECFG(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_IDLECFG_SHIFT)) & LPUART_CTRL_IDLECFG_MASK)
#define LPUART_CTRL_M7_MASK (0x800U)
#define LPUART_CTRL_M7_SHIFT (11U)
/*! M7 - 7-Bit Mode Select
* 0b0..Receiver and transmitter use 8-bit to 10-bit data characters.
* 0b1..Receiver and transmitter use 7-bit data characters.
*/
#define LPUART_CTRL_M7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_M7_SHIFT)) & LPUART_CTRL_M7_MASK)
#define LPUART_CTRL_MA2IE_MASK (0x4000U)
#define LPUART_CTRL_MA2IE_SHIFT (14U)
/*! MA2IE - Match 2 Interrupt Enable
* 0b0..MA2F interrupt disabled
* 0b1..MA2F interrupt enabled
*/
#define LPUART_CTRL_MA2IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA2IE_SHIFT)) & LPUART_CTRL_MA2IE_MASK)
#define LPUART_CTRL_MA1IE_MASK (0x8000U)
#define LPUART_CTRL_MA1IE_SHIFT (15U)
/*! MA1IE - Match 1 Interrupt Enable
* 0b0..MA1F interrupt disabled
* 0b1..MA1F interrupt enabled
*/
#define LPUART_CTRL_MA1IE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_MA1IE_SHIFT)) & LPUART_CTRL_MA1IE_MASK)
#define LPUART_CTRL_SBK_MASK (0x10000U)
#define LPUART_CTRL_SBK_SHIFT (16U)
/*! SBK - Send Break
* 0b0..Normal transmitter operation.
* 0b1..Queue break character(s) to be sent.
*/
#define LPUART_CTRL_SBK(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_SBK_SHIFT)) & LPUART_CTRL_SBK_MASK)
#define LPUART_CTRL_RWU_MASK (0x20000U)
#define LPUART_CTRL_RWU_SHIFT (17U)
/*! RWU - Receiver Wakeup Control
* 0b0..Normal receiver operation.
* 0b1..LPUART receiver in standby waiting for wakeup condition.
*/
#define LPUART_CTRL_RWU(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RWU_SHIFT)) & LPUART_CTRL_RWU_MASK)
#define LPUART_CTRL_RE_MASK (0x40000U)
#define LPUART_CTRL_RE_SHIFT (18U)
/*! RE - Receiver Enable
* 0b0..Receiver disabled.
* 0b1..Receiver enabled.
*/
#define LPUART_CTRL_RE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RE_SHIFT)) & LPUART_CTRL_RE_MASK)
#define LPUART_CTRL_TE_MASK (0x80000U)
#define LPUART_CTRL_TE_SHIFT (19U)
/*! TE - Transmitter Enable
* 0b0..Transmitter disabled.
* 0b1..Transmitter enabled.
*/
#define LPUART_CTRL_TE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TE_SHIFT)) & LPUART_CTRL_TE_MASK)
#define LPUART_CTRL_ILIE_MASK (0x100000U)
#define LPUART_CTRL_ILIE_SHIFT (20U)
/*! ILIE - Idle Line Interrupt Enable
* 0b0..Hardware interrupts from IDLE disabled; use polling.
* 0b1..Hardware interrupt is requested when IDLE flag is 1.
*/
#define LPUART_CTRL_ILIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ILIE_SHIFT)) & LPUART_CTRL_ILIE_MASK)
#define LPUART_CTRL_RIE_MASK (0x200000U)
#define LPUART_CTRL_RIE_SHIFT (21U)
/*! RIE - Receiver Interrupt Enable
* 0b0..Hardware interrupts from RDRF disabled.
* 0b1..Hardware interrupt is requested when RDRF flag is 1.
*/
#define LPUART_CTRL_RIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_RIE_SHIFT)) & LPUART_CTRL_RIE_MASK)
#define LPUART_CTRL_TCIE_MASK (0x400000U)
#define LPUART_CTRL_TCIE_SHIFT (22U)
/*! TCIE - Transmission Complete Interrupt Enable for
* 0b0..Hardware interrupts from TC disabled.
* 0b1..Hardware interrupt is requested when TC flag is 1.
*/
#define LPUART_CTRL_TCIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TCIE_SHIFT)) & LPUART_CTRL_TCIE_MASK)
#define LPUART_CTRL_TIE_MASK (0x800000U)
#define LPUART_CTRL_TIE_SHIFT (23U)
/*! TIE - Transmit Interrupt Enable
* 0b0..Hardware interrupts from TDRE disabled.
* 0b1..Hardware interrupt is requested when TDRE flag is 1.
*/
#define LPUART_CTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TIE_SHIFT)) & LPUART_CTRL_TIE_MASK)
#define LPUART_CTRL_PEIE_MASK (0x1000000U)
#define LPUART_CTRL_PEIE_SHIFT (24U)
/*! PEIE - Parity Error Interrupt Enable
* 0b0..PF interrupts disabled; use polling).
* 0b1..Hardware interrupt is requested when PF is set.
*/
#define LPUART_CTRL_PEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_PEIE_SHIFT)) & LPUART_CTRL_PEIE_MASK)
#define LPUART_CTRL_FEIE_MASK (0x2000000U)
#define LPUART_CTRL_FEIE_SHIFT (25U)
/*! FEIE - Framing Error Interrupt Enable
* 0b0..FE interrupts disabled; use polling.
* 0b1..Hardware interrupt is requested when FE is set.
*/
#define LPUART_CTRL_FEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_FEIE_SHIFT)) & LPUART_CTRL_FEIE_MASK)
#define LPUART_CTRL_NEIE_MASK (0x4000000U)
#define LPUART_CTRL_NEIE_SHIFT (26U)
/*! NEIE - Noise Error Interrupt Enable
* 0b0..NF interrupts disabled; use polling.
* 0b1..Hardware interrupt is requested when NF is set.
*/
#define LPUART_CTRL_NEIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_NEIE_SHIFT)) & LPUART_CTRL_NEIE_MASK)
#define LPUART_CTRL_ORIE_MASK (0x8000000U)
#define LPUART_CTRL_ORIE_SHIFT (27U)
/*! ORIE - Overrun Interrupt Enable
* 0b0..OR interrupts disabled; use polling.
* 0b1..Hardware interrupt is requested when OR is set.
*/
#define LPUART_CTRL_ORIE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_ORIE_SHIFT)) & LPUART_CTRL_ORIE_MASK)
#define LPUART_CTRL_TXINV_MASK (0x10000000U)
#define LPUART_CTRL_TXINV_SHIFT (28U)
/*! TXINV - Transmit Data Inversion
* 0b0..Transmit data not inverted.
* 0b1..Transmit data inverted.
*/
#define LPUART_CTRL_TXINV(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXINV_SHIFT)) & LPUART_CTRL_TXINV_MASK)
#define LPUART_CTRL_TXDIR_MASK (0x20000000U)
#define LPUART_CTRL_TXDIR_SHIFT (29U)
/*! TXDIR - TXD Pin Direction in Single-Wire Mode
* 0b0..TXD pin is an input in single-wire mode.
* 0b1..TXD pin is an output in single-wire mode.
*/
#define LPUART_CTRL_TXDIR(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_TXDIR_SHIFT)) & LPUART_CTRL_TXDIR_MASK)
#define LPUART_CTRL_R9T8_MASK (0x40000000U)
#define LPUART_CTRL_R9T8_SHIFT (30U)
/*! R9T8 - Receive Bit 9 / Transmit Bit 8
*/
#define LPUART_CTRL_R9T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R9T8_SHIFT)) & LPUART_CTRL_R9T8_MASK)
#define LPUART_CTRL_R8T9_MASK (0x80000000U)
#define LPUART_CTRL_R8T9_SHIFT (31U)
/*! R8T9 - Receive Bit 8 / Transmit Bit 9
*/
#define LPUART_CTRL_R8T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_CTRL_R8T9_SHIFT)) & LPUART_CTRL_R8T9_MASK)
/*! @} */
/*! @name DATA - LPUART Data Register */
/*! @{ */
#define LPUART_DATA_R0T0_MASK (0x1U)
#define LPUART_DATA_R0T0_SHIFT (0U)
/*! R0T0 - R0T0
*/
#define LPUART_DATA_R0T0(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R0T0_SHIFT)) & LPUART_DATA_R0T0_MASK)
#define LPUART_DATA_R1T1_MASK (0x2U)
#define LPUART_DATA_R1T1_SHIFT (1U)
/*! R1T1 - R1T1
*/
#define LPUART_DATA_R1T1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R1T1_SHIFT)) & LPUART_DATA_R1T1_MASK)
#define LPUART_DATA_R2T2_MASK (0x4U)
#define LPUART_DATA_R2T2_SHIFT (2U)
/*! R2T2 - R2T2
*/
#define LPUART_DATA_R2T2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R2T2_SHIFT)) & LPUART_DATA_R2T2_MASK)
#define LPUART_DATA_R3T3_MASK (0x8U)
#define LPUART_DATA_R3T3_SHIFT (3U)
/*! R3T3 - R3T3
*/
#define LPUART_DATA_R3T3(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R3T3_SHIFT)) & LPUART_DATA_R3T3_MASK)
#define LPUART_DATA_R4T4_MASK (0x10U)
#define LPUART_DATA_R4T4_SHIFT (4U)
/*! R4T4 - R4T4
*/
#define LPUART_DATA_R4T4(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R4T4_SHIFT)) & LPUART_DATA_R4T4_MASK)
#define LPUART_DATA_R5T5_MASK (0x20U)
#define LPUART_DATA_R5T5_SHIFT (5U)
/*! R5T5 - R5T5
*/
#define LPUART_DATA_R5T5(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R5T5_SHIFT)) & LPUART_DATA_R5T5_MASK)
#define LPUART_DATA_R6T6_MASK (0x40U)
#define LPUART_DATA_R6T6_SHIFT (6U)
/*! R6T6 - R6T6
*/
#define LPUART_DATA_R6T6(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R6T6_SHIFT)) & LPUART_DATA_R6T6_MASK)
#define LPUART_DATA_R7T7_MASK (0x80U)
#define LPUART_DATA_R7T7_SHIFT (7U)
/*! R7T7 - R7T7
*/
#define LPUART_DATA_R7T7(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R7T7_SHIFT)) & LPUART_DATA_R7T7_MASK)
#define LPUART_DATA_R8T8_MASK (0x100U)
#define LPUART_DATA_R8T8_SHIFT (8U)
/*! R8T8 - R8T8
*/
#define LPUART_DATA_R8T8(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R8T8_SHIFT)) & LPUART_DATA_R8T8_MASK)
#define LPUART_DATA_R9T9_MASK (0x200U)
#define LPUART_DATA_R9T9_SHIFT (9U)
/*! R9T9 - R9T9
*/
#define LPUART_DATA_R9T9(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_R9T9_SHIFT)) & LPUART_DATA_R9T9_MASK)
#define LPUART_DATA_IDLINE_MASK (0x800U)
#define LPUART_DATA_IDLINE_SHIFT (11U)
/*! IDLINE - Idle Line
* 0b0..Receiver was not idle before receiving this character.
* 0b1..Receiver was idle before receiving this character.
*/
#define LPUART_DATA_IDLINE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_IDLINE_SHIFT)) & LPUART_DATA_IDLINE_MASK)
#define LPUART_DATA_RXEMPT_MASK (0x1000U)
#define LPUART_DATA_RXEMPT_SHIFT (12U)
/*! RXEMPT - Receive Buffer Empty
* 0b0..Receive buffer contains valid data.
* 0b1..Receive buffer is empty, data returned on read is not valid.
*/
#define LPUART_DATA_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_RXEMPT_SHIFT)) & LPUART_DATA_RXEMPT_MASK)
#define LPUART_DATA_FRETSC_MASK (0x2000U)
#define LPUART_DATA_FRETSC_SHIFT (13U)
/*! FRETSC - Frame Error / Transmit Special Character
* 0b0..The dataword is received without a frame error on read, or transmit a normal character on write.
* 0b1..The dataword is received with a frame error, or transmit an idle or break character on transmit.
*/
#define LPUART_DATA_FRETSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_FRETSC_SHIFT)) & LPUART_DATA_FRETSC_MASK)
#define LPUART_DATA_PARITYE_MASK (0x4000U)
#define LPUART_DATA_PARITYE_SHIFT (14U)
/*! PARITYE - Parity Error
* 0b0..The dataword is received without a parity error.
* 0b1..The dataword is received with a parity error.
*/
#define LPUART_DATA_PARITYE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_PARITYE_SHIFT)) & LPUART_DATA_PARITYE_MASK)
#define LPUART_DATA_NOISY_MASK (0x8000U)
#define LPUART_DATA_NOISY_SHIFT (15U)
/*! NOISY - Noisy Data Received
* 0b0..The dataword is received without noise.
* 0b1..The data is received with noise.
*/
#define LPUART_DATA_NOISY(x) (((uint32_t)(((uint32_t)(x)) << LPUART_DATA_NOISY_SHIFT)) & LPUART_DATA_NOISY_MASK)
/*! @} */
/*! @name MATCH - LPUART Match Address Register */
/*! @{ */
#define LPUART_MATCH_MA1_MASK (0x3FFU)
#define LPUART_MATCH_MA1_SHIFT (0U)
/*! MA1 - Match Address 1
*/
#define LPUART_MATCH_MA1(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA1_SHIFT)) & LPUART_MATCH_MA1_MASK)
#define LPUART_MATCH_MA2_MASK (0x3FF0000U)
#define LPUART_MATCH_MA2_SHIFT (16U)
/*! MA2 - Match Address 2
*/
#define LPUART_MATCH_MA2(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MATCH_MA2_SHIFT)) & LPUART_MATCH_MA2_MASK)
/*! @} */
/*! @name MODIR - LPUART Modem IrDA Register */
/*! @{ */
#define LPUART_MODIR_TXCTSE_MASK (0x1U)
#define LPUART_MODIR_TXCTSE_SHIFT (0U)
/*! TXCTSE - Transmitter clear-to-send enable
* 0b0..CTS has no effect on the transmitter.
* 0b1..Enables clear-to-send operation. The transmitter checks the state of CTS each time it is ready to send a
* character. If CTS is asserted, the character is sent. If CTS is deasserted, the signal TXD remains in the
* mark state and transmission is delayed until CTS is asserted. Changes in CTS as a character is being sent
* do not affect its transmission.
*/
#define LPUART_MODIR_TXCTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSE_SHIFT)) & LPUART_MODIR_TXCTSE_MASK)
#define LPUART_MODIR_TXRTSE_MASK (0x2U)
#define LPUART_MODIR_TXRTSE_SHIFT (1U)
/*! TXRTSE - Transmitter request-to-send enable
* 0b0..The transmitter has no effect on RTS.
* 0b1..When a character is placed into an empty transmit shift register, RTS asserts one bit time before the
* start bit is transmitted. RTS deasserts one bit time after all characters in the transmitter FIFO and shift
* register are completely sent, including the last stop bit.
*/
#define LPUART_MODIR_TXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSE_SHIFT)) & LPUART_MODIR_TXRTSE_MASK)
#define LPUART_MODIR_TXRTSPOL_MASK (0x4U)
#define LPUART_MODIR_TXRTSPOL_SHIFT (2U)
/*! TXRTSPOL - Transmitter request-to-send polarity
* 0b0..Transmitter RTS is active low.
* 0b1..Transmitter RTS is active high.
*/
#define LPUART_MODIR_TXRTSPOL(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXRTSPOL_SHIFT)) & LPUART_MODIR_TXRTSPOL_MASK)
#define LPUART_MODIR_RXRTSE_MASK (0x8U)
#define LPUART_MODIR_RXRTSE_SHIFT (3U)
/*! RXRTSE - Receiver request-to-send enable
* 0b0..The receiver has no effect on RTS.
* 0b1..RTS is deasserted if the receiver data register is full or a start bit has been detected that would cause
* the receiver data register to become full. RTS is asserted if the receiver data register is not full and
* has not detected a start bit that would cause the receiver data register to become full.
*/
#define LPUART_MODIR_RXRTSE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RXRTSE_SHIFT)) & LPUART_MODIR_RXRTSE_MASK)
#define LPUART_MODIR_TXCTSC_MASK (0x10U)
#define LPUART_MODIR_TXCTSC_SHIFT (4U)
/*! TXCTSC - Transmit CTS Configuration
* 0b0..CTS input is sampled at the start of each character.
* 0b1..CTS input is sampled when the transmitter is idle.
*/
#define LPUART_MODIR_TXCTSC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSC_SHIFT)) & LPUART_MODIR_TXCTSC_MASK)
#define LPUART_MODIR_TXCTSSRC_MASK (0x20U)
#define LPUART_MODIR_TXCTSSRC_SHIFT (5U)
/*! TXCTSSRC - Transmit CTS Source
* 0b0..CTS input is the CTS_B pin.
* 0b1..CTS input is an internal connection to the receiver address match result.
*/
#define LPUART_MODIR_TXCTSSRC(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TXCTSSRC_SHIFT)) & LPUART_MODIR_TXCTSSRC_MASK)
#define LPUART_MODIR_RTSWATER_MASK (0x300U)
#define LPUART_MODIR_RTSWATER_SHIFT (8U)
/*! RTSWATER - Receive RTS Configuration
*/
#define LPUART_MODIR_RTSWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_RTSWATER_SHIFT)) & LPUART_MODIR_RTSWATER_MASK)
#define LPUART_MODIR_TNP_MASK (0x30000U)
#define LPUART_MODIR_TNP_SHIFT (16U)
/*! TNP - Transmitter narrow pulse
* 0b00..1/OSR.
* 0b01..2/OSR.
* 0b10..3/OSR.
* 0b11..4/OSR.
*/
#define LPUART_MODIR_TNP(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_TNP_SHIFT)) & LPUART_MODIR_TNP_MASK)
#define LPUART_MODIR_IREN_MASK (0x40000U)
#define LPUART_MODIR_IREN_SHIFT (18U)
/*! IREN - Infrared enable
* 0b0..IR disabled.
* 0b1..IR enabled.
*/
#define LPUART_MODIR_IREN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_MODIR_IREN_SHIFT)) & LPUART_MODIR_IREN_MASK)
/*! @} */
/*! @name FIFO - LPUART FIFO Register */
/*! @{ */
#define LPUART_FIFO_RXFIFOSIZE_MASK (0x7U)
#define LPUART_FIFO_RXFIFOSIZE_SHIFT (0U)
/*! RXFIFOSIZE - Receive FIFO Buffer Depth
* 0b000..Receive FIFO/Buffer depth = 1 dataword.
* 0b001..Receive FIFO/Buffer depth = 4 datawords.
* 0b010..Receive FIFO/Buffer depth = 8 datawords.
* 0b011..Receive FIFO/Buffer depth = 16 datawords.
* 0b100..Receive FIFO/Buffer depth = 32 datawords.
* 0b101..Receive FIFO/Buffer depth = 64 datawords.
* 0b110..Receive FIFO/Buffer depth = 128 datawords.
* 0b111..Receive FIFO/Buffer depth = 256 datawords.
*/
#define LPUART_FIFO_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFIFOSIZE_SHIFT)) & LPUART_FIFO_RXFIFOSIZE_MASK)
#define LPUART_FIFO_RXFE_MASK (0x8U)
#define LPUART_FIFO_RXFE_SHIFT (3U)
/*! RXFE - Receive FIFO Enable
* 0b0..Receive FIFO is not enabled. Buffer depth is 1.
* 0b1..Receive FIFO is enabled. Buffer depth is indicted by RXFIFOSIZE.
*/
#define LPUART_FIFO_RXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFE_SHIFT)) & LPUART_FIFO_RXFE_MASK)
#define LPUART_FIFO_TXFIFOSIZE_MASK (0x70U)
#define LPUART_FIFO_TXFIFOSIZE_SHIFT (4U)
/*! TXFIFOSIZE - Transmit FIFO Buffer Depth
* 0b000..Transmit FIFO/Buffer depth = 1 dataword.
* 0b001..Transmit FIFO/Buffer depth = 4 datawords.
* 0b010..Transmit FIFO/Buffer depth = 8 datawords.
* 0b011..Transmit FIFO/Buffer depth = 16 datawords.
* 0b100..Transmit FIFO/Buffer depth = 32 datawords.
* 0b101..Transmit FIFO/Buffer depth = 64 datawords.
* 0b110..Transmit FIFO/Buffer depth = 128 datawords.
* 0b111..Transmit FIFO/Buffer depth = 256 datawords
*/
#define LPUART_FIFO_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFIFOSIZE_SHIFT)) & LPUART_FIFO_TXFIFOSIZE_MASK)
#define LPUART_FIFO_TXFE_MASK (0x80U)
#define LPUART_FIFO_TXFE_SHIFT (7U)
/*! TXFE - Transmit FIFO Enable
* 0b0..Transmit FIFO is not enabled. Buffer depth is 1.
* 0b1..Transmit FIFO is enabled. Buffer depth is indicated by TXFIFOSIZE.
*/
#define LPUART_FIFO_TXFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFE_SHIFT)) & LPUART_FIFO_TXFE_MASK)
#define LPUART_FIFO_RXUFE_MASK (0x100U)
#define LPUART_FIFO_RXUFE_SHIFT (8U)
/*! RXUFE - Receive FIFO Underflow Interrupt Enable
* 0b0..RXUF flag does not generate an interrupt to the host.
* 0b1..RXUF flag generates an interrupt to the host.
*/
#define LPUART_FIFO_RXUFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUFE_SHIFT)) & LPUART_FIFO_RXUFE_MASK)
#define LPUART_FIFO_TXOFE_MASK (0x200U)
#define LPUART_FIFO_TXOFE_SHIFT (9U)
/*! TXOFE - Transmit FIFO Overflow Interrupt Enable
* 0b0..TXOF flag does not generate an interrupt to the host.
* 0b1..TXOF flag generates an interrupt to the host.
*/
#define LPUART_FIFO_TXOFE(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOFE_SHIFT)) & LPUART_FIFO_TXOFE_MASK)
#define LPUART_FIFO_RXIDEN_MASK (0x1C00U)
#define LPUART_FIFO_RXIDEN_SHIFT (10U)
/*! RXIDEN - Receiver Idle Empty Enable
* 0b000..Disable RDRF assertion due to partially filled FIFO when receiver is idle.
* 0b001..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 1 character.
* 0b010..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 2 characters.
* 0b011..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 4 characters.
* 0b100..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 8 characters.
* 0b101..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 16 characters.
* 0b110..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 32 characters.
* 0b111..Enable RDRF assertion due to partially filled FIFO when receiver is idle for 64 characters.
*/
#define LPUART_FIFO_RXIDEN(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXIDEN_SHIFT)) & LPUART_FIFO_RXIDEN_MASK)
#define LPUART_FIFO_RXFLUSH_MASK (0x4000U)
#define LPUART_FIFO_RXFLUSH_SHIFT (14U)
/*! RXFLUSH - Receive FIFO Flush
* 0b0..No flush operation occurs.
* 0b1..All data in the receive FIFO/buffer is cleared out.
*/
#define LPUART_FIFO_RXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXFLUSH_SHIFT)) & LPUART_FIFO_RXFLUSH_MASK)
#define LPUART_FIFO_TXFLUSH_MASK (0x8000U)
#define LPUART_FIFO_TXFLUSH_SHIFT (15U)
/*! TXFLUSH - Transmit FIFO Flush
* 0b0..No flush operation occurs.
* 0b1..All data in the transmit FIFO is cleared out.
*/
#define LPUART_FIFO_TXFLUSH(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXFLUSH_SHIFT)) & LPUART_FIFO_TXFLUSH_MASK)
#define LPUART_FIFO_RXUF_MASK (0x10000U)
#define LPUART_FIFO_RXUF_SHIFT (16U)
/*! RXUF - Receiver FIFO Underflow Flag
* 0b0..No receive FIFO underflow has occurred since the last time the flag was cleared.
* 0b1..At least one receive FIFO underflow has occurred since the last time the flag was cleared.
*/
#define LPUART_FIFO_RXUF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXUF_SHIFT)) & LPUART_FIFO_RXUF_MASK)
#define LPUART_FIFO_TXOF_MASK (0x20000U)
#define LPUART_FIFO_TXOF_SHIFT (17U)
/*! TXOF - Transmitter FIFO Overflow Flag
* 0b0..No transmit FIFO overflow has occurred since the last time the flag was cleared.
* 0b1..At least one transmit FIFO overflow has occurred since the last time the flag was cleared.
*/
#define LPUART_FIFO_TXOF(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXOF_SHIFT)) & LPUART_FIFO_TXOF_MASK)
#define LPUART_FIFO_RXEMPT_MASK (0x400000U)
#define LPUART_FIFO_RXEMPT_SHIFT (22U)
/*! RXEMPT - Receive FIFO/Buffer Empty
* 0b0..Receive buffer is not empty.
* 0b1..Receive buffer is empty.
*/
#define LPUART_FIFO_RXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_RXEMPT_SHIFT)) & LPUART_FIFO_RXEMPT_MASK)
#define LPUART_FIFO_TXEMPT_MASK (0x800000U)
#define LPUART_FIFO_TXEMPT_SHIFT (23U)
/*! TXEMPT - Transmit FIFO/Buffer Empty
* 0b0..Transmit buffer is not empty.
* 0b1..Transmit buffer is empty.
*/
#define LPUART_FIFO_TXEMPT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_FIFO_TXEMPT_SHIFT)) & LPUART_FIFO_TXEMPT_MASK)
/*! @} */
/*! @name WATER - LPUART Watermark Register */
/*! @{ */
#define LPUART_WATER_TXWATER_MASK (0x3U)
#define LPUART_WATER_TXWATER_SHIFT (0U)
/*! TXWATER - Transmit Watermark
*/
#define LPUART_WATER_TXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXWATER_SHIFT)) & LPUART_WATER_TXWATER_MASK)
#define LPUART_WATER_TXCOUNT_MASK (0x700U)
#define LPUART_WATER_TXCOUNT_SHIFT (8U)
/*! TXCOUNT - Transmit Counter
*/
#define LPUART_WATER_TXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_TXCOUNT_SHIFT)) & LPUART_WATER_TXCOUNT_MASK)
#define LPUART_WATER_RXWATER_MASK (0x30000U)
#define LPUART_WATER_RXWATER_SHIFT (16U)
/*! RXWATER - Receive Watermark
*/
#define LPUART_WATER_RXWATER(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXWATER_SHIFT)) & LPUART_WATER_RXWATER_MASK)
#define LPUART_WATER_RXCOUNT_MASK (0x7000000U)
#define LPUART_WATER_RXCOUNT_SHIFT (24U)
/*! RXCOUNT - Receive Counter
*/
#define LPUART_WATER_RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << LPUART_WATER_RXCOUNT_SHIFT)) & LPUART_WATER_RXCOUNT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group LPUART_Register_Masks */
/* LPUART - Peripheral instance base addresses */
/** Peripheral LPUART1 base address */
#define LPUART1_BASE (0x4007C000u)
/** Peripheral LPUART1 base pointer */
#define LPUART1 ((LPUART_Type *)LPUART1_BASE)
/** Peripheral LPUART2 base address */
#define LPUART2_BASE (0x40080000u)
/** Peripheral LPUART2 base pointer */
#define LPUART2 ((LPUART_Type *)LPUART2_BASE)
/** Peripheral LPUART3 base address */
#define LPUART3_BASE (0x40084000u)
/** Peripheral LPUART3 base pointer */
#define LPUART3 ((LPUART_Type *)LPUART3_BASE)
/** Peripheral LPUART4 base address */
#define LPUART4_BASE (0x40088000u)
/** Peripheral LPUART4 base pointer */
#define LPUART4 ((LPUART_Type *)LPUART4_BASE)
/** Peripheral LPUART5 base address */
#define LPUART5_BASE (0x4008C000u)
/** Peripheral LPUART5 base pointer */
#define LPUART5 ((LPUART_Type *)LPUART5_BASE)
/** Peripheral LPUART6 base address */
#define LPUART6_BASE (0x40090000u)
/** Peripheral LPUART6 base pointer */
#define LPUART6 ((LPUART_Type *)LPUART6_BASE)
/** Peripheral LPUART7 base address */
#define LPUART7_BASE (0x40094000u)
/** Peripheral LPUART7 base pointer */
#define LPUART7 ((LPUART_Type *)LPUART7_BASE)
/** Peripheral LPUART8 base address */
#define LPUART8_BASE (0x40098000u)
/** Peripheral LPUART8 base pointer */
#define LPUART8 ((LPUART_Type *)LPUART8_BASE)
/** Peripheral LPUART9 base address */
#define LPUART9_BASE (0x4009C000u)
/** Peripheral LPUART9 base pointer */
#define LPUART9 ((LPUART_Type *)LPUART9_BASE)
/** Peripheral LPUART10 base address */
#define LPUART10_BASE (0x400A0000u)
/** Peripheral LPUART10 base pointer */
#define LPUART10 ((LPUART_Type *)LPUART10_BASE)
/** Peripheral LPUART11 base address */
#define LPUART11_BASE (0x40C24000u)
/** Peripheral LPUART11 base pointer */
#define LPUART11 ((LPUART_Type *)LPUART11_BASE)
/** Peripheral LPUART12 base address */
#define LPUART12_BASE (0x40C28000u)
/** Peripheral LPUART12 base pointer */
#define LPUART12 ((LPUART_Type *)LPUART12_BASE)
/** Array initializer of LPUART peripheral base addresses */
#define LPUART_BASE_ADDRS { 0u, LPUART1_BASE, LPUART2_BASE, LPUART3_BASE, LPUART4_BASE, LPUART5_BASE, LPUART6_BASE, LPUART7_BASE, LPUART8_BASE, LPUART9_BASE, LPUART10_BASE, LPUART11_BASE, LPUART12_BASE }
/** Array initializer of LPUART peripheral base pointers */
#define LPUART_BASE_PTRS { (LPUART_Type *)0u, LPUART1, LPUART2, LPUART3, LPUART4, LPUART5, LPUART6, LPUART7, LPUART8, LPUART9, LPUART10, LPUART11, LPUART12 }
/** Interrupt vectors for the LPUART peripheral type */
#define LPUART_RX_TX_IRQS { NotAvail_IRQn, LPUART1_IRQn, LPUART2_IRQn, LPUART3_IRQn, LPUART4_IRQn, LPUART5_IRQn, LPUART6_IRQn, LPUART7_IRQn, LPUART8_IRQn, LPUART9_IRQn, LPUART10_IRQn, LPUART11_IRQn, LPUART12_IRQn }
/*!
* @}
*/ /* end of group LPUART_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MCM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
* @{
*/
/** MCM - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[16];
__IO uint32_t ISCR; /**< Interrupt Status and Control Register, offset: 0x10 */
} MCM_Type;
/* ----------------------------------------------------------------------------
-- MCM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MCM_Register_Masks MCM Register Masks
* @{
*/
/*! @name ISCR - Interrupt Status and Control Register */
/*! @{ */
#define MCM_ISCR_WABS_MASK (0x20U)
#define MCM_ISCR_WABS_SHIFT (5U)
/*! WABS - Write Abort on Slave
* 0b0..No abort
* 0b1..Abort
*/
#define MCM_ISCR_WABS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABS_SHIFT)) & MCM_ISCR_WABS_MASK)
#define MCM_ISCR_WABSO_MASK (0x40U)
#define MCM_ISCR_WABSO_SHIFT (6U)
/*! WABSO - Write Abort on Slave Overrun
* 0b0..No write abort overrun
* 0b1..Write abort overrun occurred
*/
#define MCM_ISCR_WABSO(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABSO_SHIFT)) & MCM_ISCR_WABSO_MASK)
#define MCM_ISCR_FIOC_MASK (0x100U)
#define MCM_ISCR_FIOC_SHIFT (8U)
/*! FIOC - FPU Invalid Operation interrupt Status
* 0b0..No interrupt
* 0b1..Interrupt occured
*/
#define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
#define MCM_ISCR_FDZC_MASK (0x200U)
#define MCM_ISCR_FDZC_SHIFT (9U)
/*! FDZC - FPU Divide-by-Zero Interrupt Status
* 0b0..No interrupt
* 0b1..Interrupt occured
*/
#define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
#define MCM_ISCR_FOFC_MASK (0x400U)
#define MCM_ISCR_FOFC_SHIFT (10U)
/*! FOFC - FPU Overflow interrupt status
* 0b0..No interrupt
* 0b1..Interrupt occured
*/
#define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
#define MCM_ISCR_FUFC_MASK (0x800U)
#define MCM_ISCR_FUFC_SHIFT (11U)
/*! FUFC - FPU Underflow Interrupt Status
* 0b0..No interrupt
* 0b1..Interrupt occured
*/
#define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
#define MCM_ISCR_FIXC_MASK (0x1000U)
#define MCM_ISCR_FIXC_SHIFT (12U)
/*! FIXC - FPU Inexact Interrupt Status
* 0b0..No interrupt
* 0b1..Interrupt occured
*/
#define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
#define MCM_ISCR_FIDC_MASK (0x8000U)
#define MCM_ISCR_FIDC_SHIFT (15U)
/*! FIDC - FPU Input Denormal Interrupt Status
* 0b0..No interrupt
* 0b1..Interrupt occured
*/
#define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
#define MCM_ISCR_WABE_MASK (0x200000U)
#define MCM_ISCR_WABE_SHIFT (21U)
/*! WABE - TCM Write Abort Interrupt enable
* 0b0..Disable interrupt
* 0b1..Enable interrupt
*/
#define MCM_ISCR_WABE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_WABE_SHIFT)) & MCM_ISCR_WABE_MASK)
#define MCM_ISCR_FIOCE_MASK (0x1000000U)
#define MCM_ISCR_FIOCE_SHIFT (24U)
/*! FIOCE - FPU Invalid Operation Interrupt Enable
* 0b0..Disable interrupt
* 0b1..Enable interrupt
*/
#define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
#define MCM_ISCR_FDZCE_MASK (0x2000000U)
#define MCM_ISCR_FDZCE_SHIFT (25U)
/*! FDZCE - FPU Divide-by-Zero Interrupt Enable
* 0b0..Disable interrupt
* 0b1..Enable interrupt
*/
#define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
#define MCM_ISCR_FOFCE_MASK (0x4000000U)
#define MCM_ISCR_FOFCE_SHIFT (26U)
/*! FOFCE - FPU Overflow Interrupt Enable
* 0b0..Disable interrupt
* 0b1..Enable interrupt
*/
#define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
#define MCM_ISCR_FUFCE_MASK (0x8000000U)
#define MCM_ISCR_FUFCE_SHIFT (27U)
/*! FUFCE - FPU Underflow Interrupt Enable
* 0b0..Disable interrupt
* 0b1..Enable interrupt
*/
#define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
#define MCM_ISCR_FIXCE_MASK (0x10000000U)
#define MCM_ISCR_FIXCE_SHIFT (28U)
/*! FIXCE - FPU Inexact Interrupt Enable
* 0b0..Disable interrupt
* 0b1..Enable interrupt
*/
#define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
#define MCM_ISCR_FIDCE_MASK (0x80000000U)
#define MCM_ISCR_FIDCE_SHIFT (31U)
/*! FIDCE - FPU Input Denormal Interrupt Enable
* 0b0..Disable interrupt
* 0b1..Enable interrupt
*/
#define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group MCM_Register_Masks */
/* MCM - Peripheral instance base addresses */
/** Peripheral CM7_MCM base address */
#define CM7_MCM_BASE (0xE0080000u)
/** Peripheral CM7_MCM base pointer */
#define CM7_MCM ((MCM_Type *)CM7_MCM_BASE)
/** Array initializer of MCM peripheral base addresses */
#define MCM_BASE_ADDRS { CM7_MCM_BASE }
/** Array initializer of MCM peripheral base pointers */
#define MCM_BASE_PTRS { CM7_MCM }
/*!
* @}
*/ /* end of group MCM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MECC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MECC_Peripheral_Access_Layer MECC Peripheral Access Layer
* @{
*/
/** MECC - Register Layout Typedef */
typedef struct {
__IO uint32_t ERR_STATUS; /**< Error Interrupt Status Register, offset: 0x0 */
__IO uint32_t ERR_STAT_EN; /**< Error Interrupt Status Enable Register, offset: 0x4 */
__IO uint32_t ERR_SIG_EN; /**< Error Interrupt Enable Register, offset: 0x8 */
__IO uint32_t ERR_DATA_INJ_LOW0; /**< Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data, offset: 0xC */
__IO uint32_t ERR_DATA_INJ_HIGH0; /**< Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data, offset: 0x10 */
__IO uint32_t ERR_ECC_INJ0; /**< Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data, offset: 0x14 */
__IO uint32_t ERR_DATA_INJ_LOW1; /**< Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data, offset: 0x18 */
__IO uint32_t ERR_DATA_INJ_HIGH1; /**< Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data, offset: 0x1C */
__IO uint32_t ERR_ECC_INJ1; /**< Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data, offset: 0x20 */
__IO uint32_t ERR_DATA_INJ_LOW2; /**< Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data, offset: 0x24 */
__IO uint32_t ERR_DATA_INJ_HIGH2; /**< Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data, offset: 0x28 */
__IO uint32_t ERR_ECC_INJ2; /**< Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data, offset: 0x2C */
__IO uint32_t ERR_DATA_INJ_LOW3; /**< Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data, offset: 0x30 */
__IO uint32_t ERR_DATA_INJ_HIGH3; /**< Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data, offset: 0x34 */
__IO uint32_t ERR_ECC_INJ3; /**< Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data, offset: 0x38 */
__I uint32_t SINGLE_ERR_ADDR_ECC0; /**< Single Error Address And ECC code On OCRAM Bank0, offset: 0x3C */
__I uint32_t SINGLE_ERR_DATA_LOW0; /**< LOW 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x40 */
__I uint32_t SINGLE_ERR_DATA_HIGH0; /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank0, offset: 0x44 */
__I uint32_t SINGLE_ERR_POS_LOW0; /**< LOW Single Error Bit Position On OCRAM Bank0, offset: 0x48 */
__I uint32_t SINGLE_ERR_POS_HIGH0; /**< HIGH Single Error Bit Position On OCRAM Bank0, offset: 0x4C */
__I uint32_t SINGLE_ERR_ADDR_ECC1; /**< Single Error Address And ECC code On OCRAM Bank1, offset: 0x50 */
__I uint32_t SINGLE_ERR_DATA_LOW1; /**< LOW 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x54 */
__I uint32_t SINGLE_ERR_DATA_HIGH1; /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank1, offset: 0x58 */
__I uint32_t SINGLE_ERR_POS_LOW1; /**< LOW Single Error Bit Position On OCRAM Bank1, offset: 0x5C */
__I uint32_t SINGLE_ERR_POS_HIGH1; /**< HIGH Single Error Bit Position On OCRAM Bank1, offset: 0x60 */
__I uint32_t SINGLE_ERR_ADDR_ECC2; /**< Single Error Address And ECC code On OCRAM Bank2, offset: 0x64 */
__I uint32_t SINGLE_ERR_DATA_LOW2; /**< LOW 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x68 */
__I uint32_t SINGLE_ERR_DATA_HIGH2; /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank2, offset: 0x6C */
__I uint32_t SINGLE_ERR_POS_LOW2; /**< LOW Single Error Bit Position On OCRAM Bank2, offset: 0x70 */
__I uint32_t SINGLE_ERR_POS_HIGH2; /**< HIGH Single Error Bit Position On OCRAM Bank2, offset: 0x74 */
__I uint32_t SINGLE_ERR_ADDR_ECC3; /**< Single Error Address And ECC code On OCRAM Bank3, offset: 0x78 */
__I uint32_t SINGLE_ERR_DATA_LOW3; /**< LOW 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x7C */
__I uint32_t SINGLE_ERR_DATA_HIGH3; /**< HIGH 32 Bits Single Error Read Data On OCRAM Bank3, offset: 0x80 */
__I uint32_t SINGLE_ERR_POS_LOW3; /**< LOW Single Error Bit Position On OCRAM Bank3, offset: 0x84 */
__I uint32_t SINGLE_ERR_POS_HIGH3; /**< HIGH Single Error Bit Position On OCRAM Bank3, offset: 0x88 */
__I uint32_t MULTI_ERR_ADDR_ECC0; /**< Multiple Error Address And ECC code On OCRAM Bank0, offset: 0x8C */
__I uint32_t MULTI_ERR_DATA_LOW0; /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x90 */
__I uint32_t MULTI_ERR_DATA_HIGH0; /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0, offset: 0x94 */
__I uint32_t MULTI_ERR_ADDR_ECC1; /**< Multiple Error Address And ECC code On OCRAM Bank1, offset: 0x98 */
__I uint32_t MULTI_ERR_DATA_LOW1; /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0x9C */
__I uint32_t MULTI_ERR_DATA_HIGH1; /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1, offset: 0xA0 */
__I uint32_t MULTI_ERR_ADDR_ECC2; /**< Multiple Error Address And ECC code On OCRAM Bank2, offset: 0xA4 */
__I uint32_t MULTI_ERR_DATA_LOW2; /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xA8 */
__I uint32_t MULTI_ERR_DATA_HIGH2; /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2, offset: 0xAC */
__I uint32_t MULTI_ERR_ADDR_ECC3; /**< Multiple Error Address And ECC code On OCRAM Bank3, offset: 0xB0 */
__I uint32_t MULTI_ERR_DATA_LOW3; /**< LOW 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB4 */
__I uint32_t MULTI_ERR_DATA_HIGH3; /**< HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3, offset: 0xB8 */
uint8_t RESERVED_0[68];
__IO uint32_t PIPE_ECC_EN; /**< OCRAM Pipeline And ECC Enable, offset: 0x100 */
__I uint32_t PENDING_STAT; /**< Pending Status, offset: 0x104 */
} MECC_Type;
/* ----------------------------------------------------------------------------
-- MECC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MECC_Register_Masks MECC Register Masks
* @{
*/
/*! @name ERR_STATUS - Error Interrupt Status Register */
/*! @{ */
#define MECC_ERR_STATUS_SINGLE_ERR0_MASK (0x1U)
#define MECC_ERR_STATUS_SINGLE_ERR0_SHIFT (0U)
/*! SINGLE_ERR0 - Single Bit Error On OCRAM Bank0
* 0b0..Single bit error does not happen on OCRAM bank0.
* 0b1..Single bit error happens on OCRAM bank0.
*/
#define MECC_ERR_STATUS_SINGLE_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR0_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR0_MASK)
#define MECC_ERR_STATUS_SINGLE_ERR1_MASK (0x2U)
#define MECC_ERR_STATUS_SINGLE_ERR1_SHIFT (1U)
/*! SINGLE_ERR1 - Single Bit Error On OCRAM Bank1
* 0b0..Single bit error does not happen on OCRAM bank1.
* 0b1..Single bit error happens on OCRAM bank1.
*/
#define MECC_ERR_STATUS_SINGLE_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR1_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR1_MASK)
#define MECC_ERR_STATUS_SINGLE_ERR2_MASK (0x4U)
#define MECC_ERR_STATUS_SINGLE_ERR2_SHIFT (2U)
/*! SINGLE_ERR2 - Single Bit Error On OCRAM Bank2
* 0b0..Single bit error does not happen on OCRAM bank2.
* 0b1..Single bit error happens on OCRAM bank2.
*/
#define MECC_ERR_STATUS_SINGLE_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR2_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR2_MASK)
#define MECC_ERR_STATUS_SINGLE_ERR3_MASK (0x8U)
#define MECC_ERR_STATUS_SINGLE_ERR3_SHIFT (3U)
/*! SINGLE_ERR3 - Single Bit Error On OCRAM Bank3
* 0b0..Single bit error does not happen on OCRAM bank3.
* 0b1..Single bit error happens on OCRAM bank3.
*/
#define MECC_ERR_STATUS_SINGLE_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_SINGLE_ERR3_SHIFT)) & MECC_ERR_STATUS_SINGLE_ERR3_MASK)
#define MECC_ERR_STATUS_MULTI_ERR0_MASK (0x10U)
#define MECC_ERR_STATUS_MULTI_ERR0_SHIFT (4U)
/*! MULTI_ERR0 - Multiple Bits Error On OCRAM Bank0
* 0b0..Multiple bits error does not happen on OCRAM bank0.
* 0b1..Multiple bits error happens on OCRAM bank0.
*/
#define MECC_ERR_STATUS_MULTI_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR0_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR0_MASK)
#define MECC_ERR_STATUS_MULTI_ERR1_MASK (0x20U)
#define MECC_ERR_STATUS_MULTI_ERR1_SHIFT (5U)
/*! MULTI_ERR1 - Multiple Bits Error On OCRAM Bank1
* 0b0..Multiple bits error does not happen on OCRAM bank1.
* 0b1..Multiple bits error happens on OCRAM bank1.
*/
#define MECC_ERR_STATUS_MULTI_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR1_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR1_MASK)
#define MECC_ERR_STATUS_MULTI_ERR2_MASK (0x40U)
#define MECC_ERR_STATUS_MULTI_ERR2_SHIFT (6U)
/*! MULTI_ERR2 - Multiple Bits Error On OCRAM Bank2
* 0b0..Multiple bits error does not happen on OCRAM bank2.
* 0b1..Multiple bits error happens on OCRAM bank2.
*/
#define MECC_ERR_STATUS_MULTI_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR2_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR2_MASK)
#define MECC_ERR_STATUS_MULTI_ERR3_MASK (0x80U)
#define MECC_ERR_STATUS_MULTI_ERR3_SHIFT (7U)
/*! MULTI_ERR3 - Multiple Bits Error On OCRAM Bank3
* 0b0..Multiple bits error does not happen on OCRAM bank3.
* 0b1..Multiple bits error happens on OCRAM bank3.
*/
#define MECC_ERR_STATUS_MULTI_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_MULTI_ERR3_SHIFT)) & MECC_ERR_STATUS_MULTI_ERR3_MASK)
#define MECC_ERR_STATUS_STRB_ERR0_MASK (0x100U)
#define MECC_ERR_STATUS_STRB_ERR0_SHIFT (8U)
/*! STRB_ERR0 - AXI Strobe Error On OCRAM Bank0
* 0b0..AXI strobe error does not happen on OCRAM bank0.
* 0b1..AXI strobe error happens on OCRAM bank0.
*/
#define MECC_ERR_STATUS_STRB_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR0_SHIFT)) & MECC_ERR_STATUS_STRB_ERR0_MASK)
#define MECC_ERR_STATUS_STRB_ERR1_MASK (0x200U)
#define MECC_ERR_STATUS_STRB_ERR1_SHIFT (9U)
/*! STRB_ERR1 - AXI Strobe Error On OCRAM Bank1
* 0b0..AXI strobe error does not happen on OCRAM bank1.
* 0b1..AXI strobe error happens on OCRAM bank1.
*/
#define MECC_ERR_STATUS_STRB_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR1_SHIFT)) & MECC_ERR_STATUS_STRB_ERR1_MASK)
#define MECC_ERR_STATUS_STRB_ERR2_MASK (0x400U)
#define MECC_ERR_STATUS_STRB_ERR2_SHIFT (10U)
/*! STRB_ERR2 - AXI Strobe Error On OCRAM Bank2
* 0b0..AXI strobe error does not happen on OCRAM bank2.
* 0b1..AXI strobe error happens on OCRAM bank2.
*/
#define MECC_ERR_STATUS_STRB_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR2_SHIFT)) & MECC_ERR_STATUS_STRB_ERR2_MASK)
#define MECC_ERR_STATUS_STRB_ERR3_MASK (0x800U)
#define MECC_ERR_STATUS_STRB_ERR3_SHIFT (11U)
/*! STRB_ERR3 - AXI Strobe Error On OCRAM Bank3
* 0b0..AXI strobe error does not happen on OCRAM bank3.
* 0b1..AXI strobe error happens on OCRAM bank3.
*/
#define MECC_ERR_STATUS_STRB_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_STRB_ERR3_SHIFT)) & MECC_ERR_STATUS_STRB_ERR3_MASK)
#define MECC_ERR_STATUS_ADDR_ERR0_MASK (0x1000U)
#define MECC_ERR_STATUS_ADDR_ERR0_SHIFT (12U)
/*! ADDR_ERR0 - OCRAM Access Error On Bank0
* 0b0..OCRAM access error does not happen on OCRAM bank0.
* 0b1..OCRAM access error happens on OCRAM bank0.
*/
#define MECC_ERR_STATUS_ADDR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR0_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR0_MASK)
#define MECC_ERR_STATUS_ADDR_ERR1_MASK (0x2000U)
#define MECC_ERR_STATUS_ADDR_ERR1_SHIFT (13U)
/*! ADDR_ERR1 - OCRAM Access Error On Bank1
* 0b0..OCRAM access error does not happen on OCRAM bank1.
* 0b1..OCRAM access error happens on OCRAM bank1.
*/
#define MECC_ERR_STATUS_ADDR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR1_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR1_MASK)
#define MECC_ERR_STATUS_ADDR_ERR2_MASK (0x4000U)
#define MECC_ERR_STATUS_ADDR_ERR2_SHIFT (14U)
/*! ADDR_ERR2 - OCRAM Access Error On Bank2
* 0b0..OCRAM access error does not happen on OCRAM bank2.
* 0b1..OCRAM access error happens on OCRAM bank2.
*/
#define MECC_ERR_STATUS_ADDR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR2_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR2_MASK)
#define MECC_ERR_STATUS_ADDR_ERR3_MASK (0x8000U)
#define MECC_ERR_STATUS_ADDR_ERR3_SHIFT (15U)
/*! ADDR_ERR3 - OCRAM Access Error On Bank3
* 0b0..OCRAM access error does not happen on OCRAM bank3.
* 0b1..OCRAM access error happens on OCRAM bank3.
*/
#define MECC_ERR_STATUS_ADDR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STATUS_ADDR_ERR3_SHIFT)) & MECC_ERR_STATUS_ADDR_ERR3_MASK)
/*! @} */
/*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */
/*! @{ */
#define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK (0x1U)
#define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT (0U)
/*! SINGLE_ERR0_STAT_EN - Single Bit Error Status Enable On OCRAM Bank0
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR0_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK (0x2U)
#define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT (1U)
/*! SINGLE_ERR1_STAT_EN - Single Bit Error Status Enable On OCRAM Bank1
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR1_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK (0x4U)
#define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT (2U)
/*! SINGLE_ERR2_STAT_EN - Single Bit Error Status Enable On OCRAM Bank2
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR2_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK (0x8U)
#define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT (3U)
/*! SINGLE_ERR3_STAT_EN - Single Bit Error Status Enable On OCRAM Bank3
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_SINGLE_ERR3_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK (0x10U)
#define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT (4U)
/*! MULTI_ERR0_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank0
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR0_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK (0x20U)
#define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT (5U)
/*! MULTI_ERR1_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank1
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR1_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK (0x40U)
#define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT (6U)
/*! MULTI_ERR2_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank2
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR2_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK (0x80U)
#define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT (7U)
/*! MULTI_ERR3_STAT_EN - Multiple Bits Error Status Enable On OCRAM Bank3
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_MULTI_ERR3_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK (0x100U)
#define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT (8U)
/*! STRB_ERR0_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank0
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR0_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK (0x200U)
#define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT (9U)
/*! STRB_ERR1_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank1
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR1_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK (0x400U)
#define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT (10U)
/*! STRB_ERR2_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank2
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR2_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK (0x800U)
#define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT (11U)
/*! STRB_ERR3_STAT_EN - AXI Strobe Error Status Enable On OCRAM Bank3
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_STRB_ERR3_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK (0x1000U)
#define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT (12U)
/*! ADDR_ERR0_STAT_EN - OCRAM Access Error Status Enable On Bank0
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR0_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK (0x2000U)
#define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT (13U)
/*! ADDR_ERR1_STAT_EN - OCRAM Access Error Status Enable On Bank1
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR1_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK (0x4000U)
#define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT (14U)
/*! ADDR_ERR2_STAT_EN - OCRAM Access Error Status Enable On Bank2
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR2_STAT_EN_MASK)
#define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK (0x8000U)
#define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT (15U)
/*! ADDR_ERR3_STAT_EN - OCRAM Access Error Status Enable On Bank3
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_SHIFT)) & MECC_ERR_STAT_EN_ADDR_ERR3_STAT_EN_MASK)
/*! @} */
/*! @name ERR_SIG_EN - Error Interrupt Enable Register */
/*! @{ */
#define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK (0x1U)
#define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT (0U)
/*! SINGLE_ERR0_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank0
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR0_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK (0x2U)
#define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT (1U)
/*! SINGLE_ERR1_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank1
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR1_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK (0x4U)
#define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT (2U)
/*! SINGLE_ERR2_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank2
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR2_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK (0x8U)
#define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT (3U)
/*! SINGLE_ERR3_SIG_EN - Single Bit Error Interrupt Enable On OCRAM Bank3
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_SINGLE_ERR3_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK (0x10U)
#define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT (4U)
/*! MULTI_ERR0_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank0
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR0_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK (0x20U)
#define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT (5U)
/*! MULTI_ERR1_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank1
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR1_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK (0x40U)
#define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT (6U)
/*! MULTI_ERR2_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank2
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR2_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK (0x80U)
#define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT (7U)
/*! MULTI_ERR3_SIG_EN - Multiple Bits Error Interrupt Enable On OCRAM Bank3
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_MULTI_ERR3_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK (0x100U)
#define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT (8U)
/*! STRB_ERR0_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank0
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR0_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK (0x200U)
#define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT (9U)
/*! STRB_ERR1_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank1
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR1_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK (0x400U)
#define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT (10U)
/*! STRB_ERR2_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank2
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR2_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK (0x800U)
#define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT (11U)
/*! STRB_ERR3_SIG_EN - AXI Strobe Error Interrupt Enable On OCRAM Bank3
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_STRB_ERR3_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK (0x1000U)
#define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT (12U)
/*! ADDR_ERR0_SIG_EN - OCRAM Access Error Interrupt Enable On Bank0
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR0_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK (0x2000U)
#define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT (13U)
/*! ADDR_ERR1_SIG_EN - OCRAM Access Error Interrupt Enable On Bank1
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR1_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK (0x4000U)
#define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT (14U)
/*! ADDR_ERR2_SIG_EN - OCRAM Access Error Interrupt Enable On Bank2
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR2_SIG_EN_MASK)
#define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK (0x8000U)
#define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT (15U)
/*! ADDR_ERR3_SIG_EN - OCRAM Access Error Interrupt Enable On Bank3
* 0b0..Disabled
* 0b1..Enabled
*/
#define MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_SHIFT)) & MECC_ERR_SIG_EN_ADDR_ERR3_SIG_EN_MASK)
/*! @} */
/*! @name ERR_DATA_INJ_LOW0 - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data */
/*! @{ */
#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT (0U)
/*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank0 Write Data
*/
#define MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW0_ERR_DATA_INJ_MASK)
/*! @} */
/*! @name ERR_DATA_INJ_HIGH0 - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data */
/*! @{ */
#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT (0U)
/*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank0 Write Data
*/
#define MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH0_ERR_DATA_INJ_MASK)
/*! @} */
/*! @name ERR_ECC_INJ0 - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data */
/*! @{ */
#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK (0xFFU)
#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT (0U)
/*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank0 Write Data
*/
#define MECC_ERR_ECC_INJ0_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ0_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ0_ERR_ECC_INJ_MASK)
/*! @} */
/*! @name ERR_DATA_INJ_LOW1 - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data */
/*! @{ */
#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT (0U)
/*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank1 Write Data
*/
#define MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW1_ERR_DATA_INJ_MASK)
/*! @} */
/*! @name ERR_DATA_INJ_HIGH1 - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data */
/*! @{ */
#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT (0U)
/*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank1 Write Data
*/
#define MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH1_ERR_DATA_INJ_MASK)
/*! @} */
/*! @name ERR_ECC_INJ1 - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data */
/*! @{ */
#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK (0xFFU)
#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT (0U)
/*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank1 Write Data
*/
#define MECC_ERR_ECC_INJ1_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ1_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ1_ERR_ECC_INJ_MASK)
/*! @} */
/*! @name ERR_DATA_INJ_LOW2 - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data */
/*! @{ */
#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT (0U)
/*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank2 Write Data
*/
#define MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW2_ERR_DATA_INJ_MASK)
/*! @} */
/*! @name ERR_DATA_INJ_HIGH2 - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data */
/*! @{ */
#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT (0U)
/*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank2 Write Data
*/
#define MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH2_ERR_DATA_INJ_MASK)
/*! @} */
/*! @name ERR_ECC_INJ2 - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data */
/*! @{ */
#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK (0xFFU)
#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT (0U)
/*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank2 Write Data
*/
#define MECC_ERR_ECC_INJ2_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ2_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ2_ERR_ECC_INJ_MASK)
/*! @} */
/*! @name ERR_DATA_INJ_LOW3 - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data */
/*! @{ */
#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT (0U)
/*! ERR_DATA_INJ - Error Injection On LOW 32 bits Of OCRAM Bank3 Write Data
*/
#define MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_LOW3_ERR_DATA_INJ_MASK)
/*! @} */
/*! @name ERR_DATA_INJ_HIGH3 - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data */
/*! @{ */
#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT (0U)
/*! ERR_DATA_INJ - Error Injection On HIGH 32 bits Of OCRAM Bank3 Write Data
*/
#define MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_SHIFT)) & MECC_ERR_DATA_INJ_HIGH3_ERR_DATA_INJ_MASK)
/*! @} */
/*! @name ERR_ECC_INJ3 - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data */
/*! @{ */
#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK (0xFFU)
#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT (0U)
/*! ERR_ECC_INJ - Error Injection On 8 bits ECC code Of OCRAM Bank3 Write Data
*/
#define MECC_ERR_ECC_INJ3_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << MECC_ERR_ECC_INJ3_ERR_ECC_INJ_SHIFT)) & MECC_ERR_ECC_INJ3_ERR_ECC_INJ_MASK)
/*! @} */
/*! @name SINGLE_ERR_ADDR_ECC0 - Single Error Address And ECC code On OCRAM Bank0 */
/*! @{ */
#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK (0xFFU)
#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT (0U)
/*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank0
*/
#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ECC_MASK)
#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT (8U)
/*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank0
*/
#define MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC0_SINGLE_ERR_ADDR_MASK)
/*! @} */
/*! @name SINGLE_ERR_DATA_LOW0 - LOW 32 Bits Single Error Read Data On OCRAM Bank0 */
/*! @{ */
#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT (0U)
/*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank0
*/
#define MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW0_SINGLE_ERR_DATA_MASK)
/*! @} */
/*! @name SINGLE_ERR_DATA_HIGH0 - HIGH 32 Bits Single Error Read Data On OCRAM Bank0 */
/*! @{ */
#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT (0U)
/*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank0
*/
#define MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH0_SINGLE_ERR_DATA_MASK)
/*! @} */
/*! @name SINGLE_ERR_POS_LOW0 - LOW Single Error Bit Position On OCRAM Bank0 */
/*! @{ */
#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT (0U)
/*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank0
*/
#define MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW0_SINGLE_ERR_POS_MASK)
/*! @} */
/*! @name SINGLE_ERR_POS_HIGH0 - HIGH Single Error Bit Position On OCRAM Bank0 */
/*! @{ */
#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT (0U)
/*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank0
*/
#define MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH0_SINGLE_ERR_POS_MASK)
/*! @} */
/*! @name SINGLE_ERR_ADDR_ECC1 - Single Error Address And ECC code On OCRAM Bank1 */
/*! @{ */
#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK (0xFFU)
#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT (0U)
/*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank1
*/
#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ECC_MASK)
#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT (8U)
/*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank1
*/
#define MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC1_SINGLE_ERR_ADDR_MASK)
/*! @} */
/*! @name SINGLE_ERR_DATA_LOW1 - LOW 32 Bits Single Error Read Data On OCRAM Bank1 */
/*! @{ */
#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT (0U)
/*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank1
*/
#define MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW1_SINGLE_ERR_DATA_MASK)
/*! @} */
/*! @name SINGLE_ERR_DATA_HIGH1 - HIGH 32 Bits Single Error Read Data On OCRAM Bank1 */
/*! @{ */
#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT (0U)
/*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank1
*/
#define MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH1_SINGLE_ERR_DATA_MASK)
/*! @} */
/*! @name SINGLE_ERR_POS_LOW1 - LOW Single Error Bit Position On OCRAM Bank1 */
/*! @{ */
#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT (0U)
/*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank1
*/
#define MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW1_SINGLE_ERR_POS_MASK)
/*! @} */
/*! @name SINGLE_ERR_POS_HIGH1 - HIGH Single Error Bit Position On OCRAM Bank1 */
/*! @{ */
#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT (0U)
/*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank1
*/
#define MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH1_SINGLE_ERR_POS_MASK)
/*! @} */
/*! @name SINGLE_ERR_ADDR_ECC2 - Single Error Address And ECC code On OCRAM Bank2 */
/*! @{ */
#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK (0xFFU)
#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT (0U)
/*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank2
*/
#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ECC_MASK)
#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT (8U)
/*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank2
*/
#define MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC2_SINGLE_ERR_ADDR_MASK)
/*! @} */
/*! @name SINGLE_ERR_DATA_LOW2 - LOW 32 Bits Single Error Read Data On OCRAM Bank2 */
/*! @{ */
#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT (0U)
/*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank2
*/
#define MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW2_SINGLE_ERR_DATA_MASK)
/*! @} */
/*! @name SINGLE_ERR_DATA_HIGH2 - HIGH 32 Bits Single Error Read Data On OCRAM Bank2 */
/*! @{ */
#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT (0U)
/*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank2
*/
#define MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH2_SINGLE_ERR_DATA_MASK)
/*! @} */
/*! @name SINGLE_ERR_POS_LOW2 - LOW Single Error Bit Position On OCRAM Bank2 */
/*! @{ */
#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT (0U)
/*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank2
*/
#define MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW2_SINGLE_ERR_POS_MASK)
/*! @} */
/*! @name SINGLE_ERR_POS_HIGH2 - HIGH Single Error Bit Position On OCRAM Bank2 */
/*! @{ */
#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT (0U)
/*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank2
*/
#define MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH2_SINGLE_ERR_POS_MASK)
/*! @} */
/*! @name SINGLE_ERR_ADDR_ECC3 - Single Error Address And ECC code On OCRAM Bank3 */
/*! @{ */
#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK (0xFFU)
#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT (0U)
/*! SINGLE_ERR_ECC - Single Error ECC code On OCRAM Bank3
*/
#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ECC_MASK)
#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK (0x7FFFF00U)
#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT (8U)
/*! SINGLE_ERR_ADDR - Single Error Address On OCRAM Bank3
*/
#define MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_SHIFT)) & MECC_SINGLE_ERR_ADDR_ECC3_SINGLE_ERR_ADDR_MASK)
/*! @} */
/*! @name SINGLE_ERR_DATA_LOW3 - LOW 32 Bits Single Error Read Data On OCRAM Bank3 */
/*! @{ */
#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT (0U)
/*! SINGLE_ERR_DATA - LOW 32 Bits Single Error Read Data On OCRAM Bank3
*/
#define MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_LOW3_SINGLE_ERR_DATA_MASK)
/*! @} */
/*! @name SINGLE_ERR_DATA_HIGH3 - HIGH 32 Bits Single Error Read Data On OCRAM Bank3 */
/*! @{ */
#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT (0U)
/*! SINGLE_ERR_DATA - HIGH 32 Bits Single Error Read Data On OCRAM Bank3
*/
#define MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_SHIFT)) & MECC_SINGLE_ERR_DATA_HIGH3_SINGLE_ERR_DATA_MASK)
/*! @} */
/*! @name SINGLE_ERR_POS_LOW3 - LOW Single Error Bit Position On OCRAM Bank3 */
/*! @{ */
#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT (0U)
/*! SINGLE_ERR_POS - LOW Single Error Bit Position On OCRAM Bank3
*/
#define MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_LOW3_SINGLE_ERR_POS_MASK)
/*! @} */
/*! @name SINGLE_ERR_POS_HIGH3 - HIGH Single Error Bit Position On OCRAM Bank3 */
/*! @{ */
#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT (0U)
/*! SINGLE_ERR_POS - HIGH Single Error Bit Position On OCRAM Bank3
*/
#define MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_SHIFT)) & MECC_SINGLE_ERR_POS_HIGH3_SINGLE_ERR_POS_MASK)
/*! @} */
/*! @name MULTI_ERR_ADDR_ECC0 - Multiple Error Address And ECC code On OCRAM Bank0 */
/*! @{ */
#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK (0xFFU)
#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT (0U)
/*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank0
*/
#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ECC_MASK)
#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT (8U)
/*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank0
*/
#define MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC0_MULTI_ERR_ADDR_MASK)
/*! @} */
/*! @name MULTI_ERR_DATA_LOW0 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0 */
/*! @{ */
#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT (0U)
/*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank0
*/
#define MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW0_MULTI_ERR_DATA_MASK)
/*! @} */
/*! @name MULTI_ERR_DATA_HIGH0 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0 */
/*! @{ */
#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT (0U)
/*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank0
*/
#define MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH0_MULTI_ERR_DATA_MASK)
/*! @} */
/*! @name MULTI_ERR_ADDR_ECC1 - Multiple Error Address And ECC code On OCRAM Bank1 */
/*! @{ */
#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK (0xFFU)
#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT (0U)
/*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank1
*/
#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ECC_MASK)
#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT (8U)
/*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank1
*/
#define MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC1_MULTI_ERR_ADDR_MASK)
/*! @} */
/*! @name MULTI_ERR_DATA_LOW1 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1 */
/*! @{ */
#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT (0U)
/*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank1
*/
#define MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW1_MULTI_ERR_DATA_MASK)
/*! @} */
/*! @name MULTI_ERR_DATA_HIGH1 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1 */
/*! @{ */
#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT (0U)
/*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank1
*/
#define MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH1_MULTI_ERR_DATA_MASK)
/*! @} */
/*! @name MULTI_ERR_ADDR_ECC2 - Multiple Error Address And ECC code On OCRAM Bank2 */
/*! @{ */
#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK (0xFFU)
#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT (0U)
/*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank2
*/
#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ECC_MASK)
#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT (8U)
/*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank2
*/
#define MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC2_MULTI_ERR_ADDR_MASK)
/*! @} */
/*! @name MULTI_ERR_DATA_LOW2 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2 */
/*! @{ */
#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT (0U)
/*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank2
*/
#define MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW2_MULTI_ERR_DATA_MASK)
/*! @} */
/*! @name MULTI_ERR_DATA_HIGH2 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2 */
/*! @{ */
#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT (0U)
/*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank2
*/
#define MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH2_MULTI_ERR_DATA_MASK)
/*! @} */
/*! @name MULTI_ERR_ADDR_ECC3 - Multiple Error Address And ECC code On OCRAM Bank3 */
/*! @{ */
#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK (0xFFU)
#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT (0U)
/*! MULTI_ERR_ECC - Multiple Error ECC code On OCRAM Bank3
*/
#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ECC_MASK)
#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK (0x7FFFF00U)
#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT (8U)
/*! MULTI_ERR_ADDR - Multiple Error Address On OCRAM Bank3
*/
#define MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_SHIFT)) & MECC_MULTI_ERR_ADDR_ECC3_MULTI_ERR_ADDR_MASK)
/*! @} */
/*! @name MULTI_ERR_DATA_LOW3 - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3 */
/*! @{ */
#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT (0U)
/*! MULTI_ERR_DATA - LOW 32 Bits Multiple Error Read Data On OCRAM Bank3
*/
#define MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_LOW3_MULTI_ERR_DATA_MASK)
/*! @} */
/*! @name MULTI_ERR_DATA_HIGH3 - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3 */
/*! @{ */
#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT (0U)
/*! MULTI_ERR_DATA - HIGH 32 Bits Multiple Error Read Data On OCRAM Bank3
*/
#define MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_SHIFT)) & MECC_MULTI_ERR_DATA_HIGH3_MULTI_ERR_DATA_MASK)
/*! @} */
/*! @name PIPE_ECC_EN - OCRAM Pipeline And ECC Enable */
/*! @{ */
#define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK (0x1U)
#define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT (0U)
/*! READ_DATA_WAIT_EN - Read Data Wait Enable
* 0b0..Disable.
* 0b1..Enable.
*/
#define MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_DATA_WAIT_EN_MASK)
#define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK (0x2U)
#define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT (1U)
/*! READ_ADDR_PIPE_EN - Read Address Pipeline Enable
* 0b0..Disable.
* 0b1..Enable.
*/
#define MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_READ_ADDR_PIPE_EN_MASK)
#define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK (0x4U)
#define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT (2U)
/*! WRITE_DATA_PIPE_EN - Write Data Pipeline Enable
* 0b0..Disable.
* 0b1..Enable.
*/
#define MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_DATA_PIPE_EN_MASK)
#define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK (0x8U)
#define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT (3U)
/*! WRITE_ADDR_PIPE_EN - Write Address Pipeline Enable
* 0b0..Disable.
* 0b1..Enable.
*/
#define MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_SHIFT)) & MECC_PIPE_ECC_EN_WRITE_ADDR_PIPE_EN_MASK)
#define MECC_PIPE_ECC_EN_ECC_EN_MASK (0x10U)
#define MECC_PIPE_ECC_EN_ECC_EN_SHIFT (4U)
/*! ECC_EN - ECC Function Enable
* 0b0..Disable.
* 0b1..Enable.
*/
#define MECC_PIPE_ECC_EN_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << MECC_PIPE_ECC_EN_ECC_EN_SHIFT)) & MECC_PIPE_ECC_EN_ECC_EN_MASK)
/*! @} */
/*! @name PENDING_STAT - Pending Status */
/*! @{ */
#define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK (0x1U)
#define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT (0U)
/*! READ_DATA_WAIT_PENDING - Read Data Wait Pending
* 0b0..No update pending status for READ_DATA_WAIT_EN.
* 0b1..When READ_DATA_WAIT_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
*/
#define MECC_PENDING_STAT_READ_DATA_WAIT_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_DATA_WAIT_PENDING_MASK)
#define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK (0x2U)
#define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT (1U)
/*! READ_ADDR_PIPE_PENDING - Read Address Pipeline Pending
* 0b0..No update pending status for READ_ADDR_PIPE_EN.
* 0b1..When READ_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
*/
#define MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_READ_ADDR_PIPE_PENDING_MASK)
#define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK (0x4U)
#define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT (2U)
/*! WRITE_DATA_PIPE_PENDING - Write Data Pipeline Pending
* 0b0..No update pending status for WRITE_DATA_PIPE_EN.
* 0b1..When WRITE_DATA_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
*/
#define MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_DATA_PIPE_PENDING_MASK)
#define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK (0x8U)
#define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT (3U)
/*! WRITE_ADDR_PIPE_PENDING - Write Address Pipeline Pending
* 0b0..No update pending status for WRITE_ADDR_PIPE_EN.
* 0b1..When WRITE_ADDR_PIPE_EN register bit is changed, this register bit will be set until the new setup becomes valid in the controller.
*/
#define MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_SHIFT)) & MECC_PENDING_STAT_WRITE_ADDR_PIPE_PENDING_MASK)
/*! @} */
/*!
* @}
*/ /* end of group MECC_Register_Masks */
/* MECC - Peripheral instance base addresses */
/** Peripheral MECC1 base address */
#define MECC1_BASE (0x40014000u)
/** Peripheral MECC1 base pointer */
#define MECC1 ((MECC_Type *)MECC1_BASE)
/** Peripheral MECC2 base address */
#define MECC2_BASE (0x40018000u)
/** Peripheral MECC2 base pointer */
#define MECC2 ((MECC_Type *)MECC2_BASE)
/** Array initializer of MECC peripheral base addresses */
#define MECC_BASE_ADDRS { 0u, MECC1_BASE, MECC2_BASE }
/** Array initializer of MECC peripheral base pointers */
#define MECC_BASE_PTRS { (MECC_Type *)0u, MECC1, MECC2 }
/*!
* @}
*/ /* end of group MECC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MIPI_CSI2RX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MIPI_CSI2RX_Peripheral_Access_Layer MIPI_CSI2RX Peripheral Access Layer
* @{
*/
/** MIPI_CSI2RX - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[256];
__IO uint32_t CFG_NUM_LANES; /**< Lane Configuration Register, offset: 0x100 */
__IO uint32_t CFG_DISABLE_DATA_LANES; /**< Disable Data Lane Register, offset: 0x104 */
__I uint32_t BIT_ERR; /**< ECC and CRC Error Status Register, offset: 0x108 */
__I uint32_t IRQ_STATUS; /**< IRQ Status Register, offset: 0x10C */
__IO uint32_t IRQ_MASK; /**< IRQ Mask Setting Register, offset: 0x110 */
__I uint32_t ULPS_STATUS; /**< Ultra Low Power State (ULPS) Status Register, offset: 0x114 */
__I uint32_t PPI_ERRSOT_HS; /**< ERRSot HS Status Register, offset: 0x118 */
__I uint32_t PPI_ERRSOTSYNC_HS; /**< ErrSotSync HS Status Register, offset: 0x11C */
__I uint32_t PPI_ERRESC; /**< ErrEsc Status Register, offset: 0x120 */
__I uint32_t PPI_ERRSYNCESC; /**< ErrSyncEsc Status Register, offset: 0x124 */
__I uint32_t PPI_ERRCONTROL; /**< ErrControl Status Register, offset: 0x128 */
__IO uint32_t CFG_DISABLE_PAYLOAD_0; /**< Disable Payload 0 Register, offset: 0x12C */
__IO uint32_t CFG_DISABLE_PAYLOAD_1; /**< Disable Payload 1 Register, offset: 0x130 */
uint8_t RESERVED_1[76];
__IO uint32_t CFG_IGNORE_VC; /**< Ignore Virtual Channel Register, offset: 0x180 */
__IO uint32_t CFG_VID_VC; /**< Virtual Channel value Register, offset: 0x184 */
__IO uint32_t CFG_VID_P_FIFO_SEND_LEVEL; /**< FIFO Send Level Configuration Register, offset: 0x188 */
__IO uint32_t CFG_VID_VSYNC; /**< VSYNC Configuration Register, offset: 0x18C */
__IO uint32_t CFG_VID_HSYNC_FP; /**< Start of HSYNC Delay control Register, offset: 0x190 */
__IO uint32_t CFG_VID_HSYNC; /**< HSYNC Configuration Register, offset: 0x194 */
__IO uint32_t CFG_VID_HSYNC_BP; /**< End of HSYNC Delay Control Register, offset: 0x198 */
} MIPI_CSI2RX_Type;
/* ----------------------------------------------------------------------------
-- MIPI_CSI2RX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MIPI_CSI2RX_Register_Masks MIPI_CSI2RX Register Masks
* @{
*/
/*! @name CFG_NUM_LANES - Lane Configuration Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK (0x3U)
#define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT (0U)
/*! CFG_NUM_LANES - This field is used to set the number of active lanes for receiving data.
* 0b00..1 Lane
* 0b01..2 Lane
* 0b10-0b11..Reserved
*/
#define MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_SHIFT)) & MIPI_CSI2RX_CFG_NUM_LANES_CFG_NUM_LANES_MASK)
/*! @} */
/*! @name CFG_DISABLE_DATA_LANES - Disable Data Lane Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK (0xFU)
#define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT (0U)
/*! CFG_DISABLE_DATA_LANES - This field is used to disable data lanes.
*/
#define MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_DATA_LANES_CFG_DISABLE_DATA_LANES_MASK)
/*! @} */
/*! @name BIT_ERR - ECC and CRC Error Status Register */
/*! @{ */
#define MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK (0x3FFU)
#define MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT (0U)
/*! BIT_ERR - This field shows the error status of ECC and CRC
*/
#define MIPI_CSI2RX_BIT_ERR_BIT_ERR(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_BIT_ERR_BIT_ERR_SHIFT)) & MIPI_CSI2RX_BIT_ERR_BIT_ERR_MASK)
/*! @} */
/*! @name IRQ_STATUS - IRQ Status Register */
/*! @{ */
#define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK (0x1FFU)
#define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT (0U)
/*! IRQ_STATUS - This field shows the IRQ status
*/
#define MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_SHIFT)) & MIPI_CSI2RX_IRQ_STATUS_IRQ_STATUS_MASK)
/*! @} */
/*! @name IRQ_MASK - IRQ Mask Setting Register */
/*! @{ */
#define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK (0x1FFU)
#define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT (0U)
/*! IRQ_MASK - This field shows the IRQ Mask setting
*/
#define MIPI_CSI2RX_IRQ_MASK_IRQ_MASK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_SHIFT)) & MIPI_CSI2RX_IRQ_MASK_IRQ_MASK_MASK)
/*! @} */
/*! @name ULPS_STATUS - Ultra Low Power State (ULPS) Status Register */
/*! @{ */
#define MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK (0x3FFU)
#define MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT (0U)
/*! STATUS - This field shows the status of Rx D-PHY ULPS state
*/
#define MIPI_CSI2RX_ULPS_STATUS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_ULPS_STATUS_STATUS_SHIFT)) & MIPI_CSI2RX_ULPS_STATUS_STATUS_MASK)
/*! @} */
/*! @name PPI_ERRSOT_HS - ERRSot HS Status Register */
/*! @{ */
#define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK (0xFU)
#define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT (0U)
/*! STATUS - This field indicates PPI ErrSotHS captured status from D-PHY
*/
#define MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOT_HS_STATUS_MASK)
/*! @} */
/*! @name PPI_ERRSOTSYNC_HS - ErrSotSync HS Status Register */
/*! @{ */
#define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK (0xFU)
#define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT (0U)
/*! STATUS - This field indicates PPI ErrSotSync_HS captured status from D-PHY
*/
#define MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSOTSYNC_HS_STATUS_MASK)
/*! @} */
/*! @name PPI_ERRESC - ErrEsc Status Register */
/*! @{ */
#define MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK (0xFU)
#define MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT (0U)
/*! STATUS - This field indicates PPI ErrEsc captured status from D-PHY
*/
#define MIPI_CSI2RX_PPI_ERRESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRESC_STATUS_MASK)
/*! @} */
/*! @name PPI_ERRSYNCESC - ErrSyncEsc Status Register */
/*! @{ */
#define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK (0xFU)
#define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT (0U)
/*! STATUS - This field indicates PPI ErrSyncEsc captured status from D-PHY
*/
#define MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRSYNCESC_STATUS_MASK)
/*! @} */
/*! @name PPI_ERRCONTROL - ErrControl Status Register */
/*! @{ */
#define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK (0xFU)
#define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT (0U)
/*! STATUS - This field indicates PPI ErrControl captured status from D-PHY
*/
#define MIPI_CSI2RX_PPI_ERRCONTROL_STATUS(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_SHIFT)) & MIPI_CSI2RX_PPI_ERRCONTROL_STATUS_MASK)
/*! @} */
/*! @name CFG_DISABLE_PAYLOAD_0 - Disable Payload 0 Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK (0x1U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT (0U)
/*! DIS_PAYLOAD_NULL - Null
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_NULL_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK (0x2U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT (1U)
/*! DIS_PAYLOAD_BLANK - Blank
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_BLANK_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK (0x4U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT (2U)
/*! DIS_PAYLOAD_EMBEDDED - Embedded
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_EMBEDDED_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK (0x400U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT (10U)
/*! DIS_PAYLOAD_YUV420 - Legacy YUV 420 8 bit
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV420_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK (0x4000U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT (14U)
/*! DIS_PAYLOAD_YUV422_8BIT - YUV422 8 bit
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_YUV422_8BIT_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK (0x10000U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT (16U)
/*! DIS_PAYLOAD_RGB444 - RGB444
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB444_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK (0x20000U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT (17U)
/*! DIS_PAYLOAD_RGB555 - RGB555
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB555_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK (0x40000U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT (18U)
/*! DIS_PAYLOAD_RGB565 - RGB565
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB565_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK (0x80000U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT (19U)
/*! DIS_PAYLOAD_RGB666 - RGB666
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB666_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK (0x100000U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT (20U)
/*! DIS_PAYLOAD_RGB888 - RGB888
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_0_DIS_PAYLOAD_RGB888_MASK)
/*! @} */
/*! @name CFG_DISABLE_PAYLOAD_1 - Disable Payload 1 Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK (0x1U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT (0U)
/*! DIS_PAYLOAD_UDEF_30 - User defined type 0x31
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_30_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK (0x2U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT (1U)
/*! DIS_PAYLOAD_UDEF_31 - User defined type 0x32
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_31_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK (0x4U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT (2U)
/*! DIS_PAYLOAD_UDEF_32 - User defined type 0x33
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_32_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK (0x8U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT (3U)
/*! DIS_PAYLOAD_UDEF_33 - User defined type 0x34
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_33_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK (0x10U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT (4U)
/*! DIS_PAYLOAD_UDEF_34 - User defined type 0x35
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_34_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK (0x20U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT (5U)
/*! DIS_PAYLOAD_UDEF_35 - User defined type 0x35
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_35_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK (0x40U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT (6U)
/*! DIS_PAYLOAD_UDEF_36 - User defined type 0x36
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_36_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK (0x80U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT (7U)
/*! DIS_PAYLOAD_UDEF_37 - User defined type 0x37
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UDEF_37_MASK)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK (0x10000U)
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT (16U)
/*! DIS_PAYLOAD_UNSUPPORTED - Unsupported Data Types
*/
#define MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_SHIFT)) & MIPI_CSI2RX_CFG_DISABLE_PAYLOAD_1_DIS_PAYLOAD_UNSUPPORTED_MASK)
/*! @} */
/*! @name CFG_IGNORE_VC - Ignore Virtual Channel Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK (0x1U)
#define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT (0U)
#define MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_SHIFT)) & MIPI_CSI2RX_CFG_IGNORE_VC_IGNORE_VC_MASK)
/*! @} */
/*! @name CFG_VID_VC - Virtual Channel value Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK (0x3U)
#define MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT (0U)
#define MIPI_CSI2RX_CFG_VID_VC_VID_VC(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VC_VID_VC_SHIFT)) & MIPI_CSI2RX_CFG_VID_VC_VID_VC_MASK)
/*! @} */
/*! @name CFG_VID_P_FIFO_SEND_LEVEL - FIFO Send Level Configuration Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK (0xFFFFU)
#define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT (0U)
/*! SEND_LEVEL - FIFO Send Level field
*/
#define MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_SHIFT)) & MIPI_CSI2RX_CFG_VID_P_FIFO_SEND_LEVEL_SEND_LEVEL_MASK)
/*! @} */
/*! @name CFG_VID_VSYNC - VSYNC Configuration Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK (0xFFU)
#define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT (0U)
/*! WIDTH - Width of VSYNC
*/
#define MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_VSYNC_WIDTH_MASK)
/*! @} */
/*! @name CFG_VID_HSYNC_FP - Start of HSYNC Delay control Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK (0xFFU)
#define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT (0U)
/*! DELAY_CTL - Delay control for beginning of HSYNC pulse
*/
#define MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_FP_DELAY_CTL_MASK)
/*! @} */
/*! @name CFG_VID_HSYNC - HSYNC Configuration Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK (0xFFU)
#define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT (0U)
/*! WIDTH - Width of HSYNC
*/
#define MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_WIDTH_MASK)
/*! @} */
/*! @name CFG_VID_HSYNC_BP - End of HSYNC Delay Control Register */
/*! @{ */
#define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK (0xFFU)
#define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT (0U)
/*! DELAY_CTL - Delay Control for end of HSYNC pulse
*/
#define MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL(x) (((uint32_t)(((uint32_t)(x)) << MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_SHIFT)) & MIPI_CSI2RX_CFG_VID_HSYNC_BP_DELAY_CTL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group MIPI_CSI2RX_Register_Masks */
/* MIPI_CSI2RX - Peripheral instance base addresses */
/** Peripheral MIPI_CSI2RX base address */
#define MIPI_CSI2RX_BASE (0x40810000u)
/** Peripheral MIPI_CSI2RX base pointer */
#define MIPI_CSI2RX ((MIPI_CSI2RX_Type *)MIPI_CSI2RX_BASE)
/** Array initializer of MIPI_CSI2RX peripheral base addresses */
#define MIPI_CSI2RX_BASE_ADDRS { MIPI_CSI2RX_BASE }
/** Array initializer of MIPI_CSI2RX peripheral base pointers */
#define MIPI_CSI2RX_BASE_PTRS { MIPI_CSI2RX }
/*!
* @}
*/ /* end of group MIPI_CSI2RX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- MU Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup MU_Peripheral_Access_Layer MU Peripheral Access Layer
* @{
*/
/** MU - Register Layout Typedef */
typedef struct {
__IO uint32_t TR[4]; /**< Processor A Transmit Register 0..Processor A Transmit Register 3, array offset: 0x0, array step: 0x4 */
__I uint32_t RR[4]; /**< Processor A Receive Register 0..Processor A Receive Register 3, array offset: 0x10, array step: 0x4 */
__IO uint32_t SR; /**< Processor A Status Register, offset: 0x20 */
__IO uint32_t CR; /**< Processor A Control Register, offset: 0x24 */
} MU_Type;
/* ----------------------------------------------------------------------------
-- MU Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup MU_Register_Masks MU Register Masks
* @{
*/
/*! @name TR - Processor A Transmit Register 0..Processor A Transmit Register 3 */
/*! @{ */
#define MU_TR_DATA_MASK (0xFFFFFFFFU)
#define MU_TR_DATA_SHIFT (0U)
/*! DATA - TR3
*/
#define MU_TR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_TR_DATA_SHIFT)) & MU_TR_DATA_MASK)
/*! @} */
/* The count of MU_TR */
#define MU_TR_COUNT (4U)
/*! @name RR - Processor A Receive Register 0..Processor A Receive Register 3 */
/*! @{ */
#define MU_RR_DATA_MASK (0xFFFFFFFFU)
#define MU_RR_DATA_SHIFT (0U)
/*! DATA - RR3
*/
#define MU_RR_DATA(x) (((uint32_t)(((uint32_t)(x)) << MU_RR_DATA_SHIFT)) & MU_RR_DATA_MASK)
/*! @} */
/* The count of MU_RR */
#define MU_RR_COUNT (4U)
/*! @name SR - Processor A Status Register */
/*! @{ */
#define MU_SR_Fn_MASK (0x7U)
#define MU_SR_Fn_SHIFT (0U)
/*! Fn - Fn
* 0b000..BAFn bit in MUB.CR register is written 0 (default).
* 0b001..BAFn bit in MUB.CR register is written 1.
*/
#define MU_SR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_Fn_SHIFT)) & MU_SR_Fn_MASK)
#define MU_SR_EP_MASK (0x10U)
#define MU_SR_EP_SHIFT (4U)
/*! EP - EP
* 0b0..The Processor A-side event is not pending (default).
* 0b1..The Processor A-side event is pending.
*/
#define MU_SR_EP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_EP_SHIFT)) & MU_SR_EP_MASK)
#define MU_SR_RS_MASK (0x80U)
#define MU_SR_RS_SHIFT (7U)
/*! RS - RS
* 0b0..The Processor B-side of the MU is not in reset.
* 0b1..The Processor B-side of the MU is in reset.
*/
#define MU_SR_RS(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RS_SHIFT)) & MU_SR_RS_MASK)
#define MU_SR_FUP_MASK (0x100U)
#define MU_SR_FUP_SHIFT (8U)
/*! FUP - FUP
* 0b0..No flags updated, initiated by the Processor A, in progress (default)
* 0b1..Processor A initiated flags update, processing
*/
#define MU_SR_FUP(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_FUP_SHIFT)) & MU_SR_FUP_MASK)
#define MU_SR_TEn_MASK (0xF00000U)
#define MU_SR_TEn_SHIFT (20U)
/*! TEn - TEn
* 0b0000..MUA.TRn register is not empty.
* 0b0001..MUA.TRn register is empty (default).
*/
#define MU_SR_TEn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_TEn_SHIFT)) & MU_SR_TEn_MASK)
#define MU_SR_RFn_MASK (0xF000000U)
#define MU_SR_RFn_SHIFT (24U)
/*! RFn - RFn
* 0b0000..MUA.RRn register is not full (default).
* 0b0001..MUA.RRn register has received data from MUB.TRn register and is ready to be read by the Processor A.
*/
#define MU_SR_RFn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_RFn_SHIFT)) & MU_SR_RFn_MASK)
#define MU_SR_GIPn_MASK (0xF0000000U)
#define MU_SR_GIPn_SHIFT (28U)
/*! GIPn - GIPn
* 0b0000..Processor A general purpose interrupt n is not pending. (default)
* 0b0001..Processor A general purpose interrupt n is pending.
*/
#define MU_SR_GIPn(x) (((uint32_t)(((uint32_t)(x)) << MU_SR_GIPn_SHIFT)) & MU_SR_GIPn_MASK)
/*! @} */
/*! @name CR - Processor A Control Register */
/*! @{ */
#define MU_CR_Fn_MASK (0x7U)
#define MU_CR_Fn_SHIFT (0U)
/*! Fn - Fn
* 0b000..N/A. Self clearing bit (default).
* 0b001..Asserts the Processor A MU reset.
*/
#define MU_CR_Fn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_Fn_SHIFT)) & MU_CR_Fn_MASK)
#define MU_CR_MUR_MASK (0x20U)
#define MU_CR_MUR_SHIFT (5U)
/*! MUR - MUR
* 0b0..N/A. Self clearing bit (default).
* 0b1..Asserts the Processor A MU reset.
*/
#define MU_CR_MUR(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_MUR_SHIFT)) & MU_CR_MUR_MASK)
#define MU_CR_GIRn_MASK (0xF0000U)
#define MU_CR_GIRn_SHIFT (16U)
/*! GIRn - GIRn
* 0b0000..Processor A General Interrupt n is not requested to the Processor B (default).
* 0b0001..Processor A General Interrupt n is requested to the Processor B.
*/
#define MU_CR_GIRn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIRn_SHIFT)) & MU_CR_GIRn_MASK)
#define MU_CR_TIEn_MASK (0xF00000U)
#define MU_CR_TIEn_SHIFT (20U)
/*! TIEn - TIEn
* 0b0000..Disables Processor A Transmit Interrupt n. (default)
* 0b0001..Enables Processor A Transmit Interrupt n.
*/
#define MU_CR_TIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_TIEn_SHIFT)) & MU_CR_TIEn_MASK)
#define MU_CR_RIEn_MASK (0xF000000U)
#define MU_CR_RIEn_SHIFT (24U)
/*! RIEn - RIEn
* 0b0000..Disables Processor A Receive Interrupt n. (default)
* 0b0001..Enables Processor A Receive Interrupt n.
*/
#define MU_CR_RIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_RIEn_SHIFT)) & MU_CR_RIEn_MASK)
#define MU_CR_GIEn_MASK (0xF0000000U)
#define MU_CR_GIEn_SHIFT (28U)
/*! GIEn - GIEn
* 0b0000..Disables Processor A General Interrupt n. (default)
* 0b0001..Enables Processor A General Interrupt n.
*/
#define MU_CR_GIEn(x) (((uint32_t)(((uint32_t)(x)) << MU_CR_GIEn_SHIFT)) & MU_CR_GIEn_MASK)
/*! @} */
/*!
* @}
*/ /* end of group MU_Register_Masks */
/* MU - Peripheral instance base addresses */
/** Peripheral MUA base address */
#define MUA_BASE (0x40C48000u)
/** Peripheral MUA base pointer */
#define MUA ((MU_Type *)MUA_BASE)
/** Array initializer of MU peripheral base addresses */
#define MU_BASE_ADDRS { MUA_BASE }
/** Array initializer of MU peripheral base pointers */
#define MU_BASE_PTRS { MUA }
/** Interrupt vectors for the MU peripheral type */
#define MU_IRQS { MUA_IRQn }
/*!
* @}
*/ /* end of group MU_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- OCOTP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup OCOTP_Peripheral_Access_Layer OCOTP Peripheral Access Layer
* @{
*/
/** OCOTP - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< OTP Controller Control and Status Register, offset: 0x0 */
__IO uint32_t CTRL_SET; /**< OTP Controller Control and Status Register, offset: 0x4 */
__IO uint32_t CTRL_CLR; /**< OTP Controller Control and Status Register, offset: 0x8 */
__IO uint32_t CTRL_TOG; /**< OTP Controller Control and Status Register, offset: 0xC */
__IO uint32_t PDN; /**< OTP Controller PDN Register, offset: 0x10 */
uint8_t RESERVED_0[12];
__IO uint32_t DATA; /**< OTP Controller Write Data Register, offset: 0x20 */
uint8_t RESERVED_1[12];
__IO uint32_t READ_CTRL; /**< OTP Controller Read Control Register, offset: 0x30 */
uint8_t RESERVED_2[92];
__IO uint32_t OUT_STATUS; /**< 8K OTP Memory STATUS Register, offset: 0x90 */
__IO uint32_t OUT_STATUS_SET; /**< 8K OTP Memory STATUS Register, offset: 0x94 */
__IO uint32_t OUT_STATUS_CLR; /**< 8K OTP Memory STATUS Register, offset: 0x98 */
__IO uint32_t OUT_STATUS_TOG; /**< 8K OTP Memory STATUS Register, offset: 0x9C */
uint8_t RESERVED_3[16];
__I uint32_t VERSION; /**< OTP Controller Version Register, offset: 0xB0 */
uint8_t RESERVED_4[76];
struct { /* offset: 0x100, array step: 0x10 */
__IO uint32_t READ_FUSE_DATA; /**< OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register, array offset: 0x100, array step: 0x10 */
uint8_t RESERVED_0[12];
} READ_FUSE_DATAS[4];
__IO uint32_t SW_LOCK; /**< SW_LOCK Register, offset: 0x140 */
uint8_t RESERVED_5[12];
__IO uint32_t BIT_LOCK; /**< BIT_LOCK Register, offset: 0x150 */
uint8_t RESERVED_6[1196];
__I uint32_t LOCKED0; /**< OTP Controller Program Locked Status 0 Register, offset: 0x600 */
uint8_t RESERVED_7[12];
__I uint32_t LOCKED1; /**< OTP Controller Program Locked Status 1 Register, offset: 0x610 */
uint8_t RESERVED_8[12];
__I uint32_t LOCKED2; /**< OTP Controller Program Locked Status 2 Register, offset: 0x620 */
uint8_t RESERVED_9[12];
__I uint32_t LOCKED3; /**< OTP Controller Program Locked Status 3 Register, offset: 0x630 */
uint8_t RESERVED_10[12];
__I uint32_t LOCKED4; /**< OTP Controller Program Locked Status 4 Register, offset: 0x640 */
uint8_t RESERVED_11[444];
struct { /* offset: 0x800, array step: 0x10 */
__I uint32_t FUSE; /**< Value of fuse word 0..Value of fuse word 143, array offset: 0x800, array step: 0x10 */
uint8_t RESERVED_0[12];
} FUSEN[144];
} OCOTP_Type;
/* ----------------------------------------------------------------------------
-- OCOTP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup OCOTP_Register_Masks OCOTP Register Masks
* @{
*/
/*! @name CTRL - OTP Controller Control and Status Register */
/*! @{ */
#define OCOTP_CTRL_ADDR_MASK (0x3FFU)
#define OCOTP_CTRL_ADDR_SHIFT (0U)
/*! ADDR - OTP write and read access address register
* 0b0000000000-0b0000001111..Address of one of the 16 supplementary fuse words in OTP memory.
* 0b0000010000-0b0100001111..Address of one of the 256 user fuse words in OTP memory.
*/
#define OCOTP_CTRL_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ADDR_SHIFT)) & OCOTP_CTRL_ADDR_MASK)
#define OCOTP_CTRL_BUSY_MASK (0x400U)
#define OCOTP_CTRL_BUSY_SHIFT (10U)
/*! BUSY - OTP controller status bit
* 0b0..No write or read access to OTP started.
* 0b1..Write or read access to OTP started.
*/
#define OCOTP_CTRL_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_BUSY_SHIFT)) & OCOTP_CTRL_BUSY_MASK)
#define OCOTP_CTRL_ERROR_MASK (0x800U)
#define OCOTP_CTRL_ERROR_SHIFT (11U)
/*! ERROR - Locked Region Access Error
* 0b0..No error.
* 0b1..Error - access to a locked region requested.
*/
#define OCOTP_CTRL_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_ERROR_SHIFT)) & OCOTP_CTRL_ERROR_MASK)
#define OCOTP_CTRL_RELOAD_SHADOWS_MASK (0x1000U)
#define OCOTP_CTRL_RELOAD_SHADOWS_SHIFT (12U)
/*! RELOAD_SHADOWS - Reload Shadow Registers
* 0b0..Do not force shadow register re-load.
* 0b1..Force shadow register re-load. This bit is cleared automatically after shadow registers are re-loaded.
*/
#define OCOTP_CTRL_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_RELOAD_SHADOWS_MASK)
#define OCOTP_CTRL_WORDLOCK_MASK (0x8000U)
#define OCOTP_CTRL_WORDLOCK_SHIFT (15U)
/*! WORDLOCK - Lock fuse word
* 0b0..No change to LOCK bit when programming a word using redundancy
* 0b1..LOCK bit for fuse word will be set after successfully programming a word using redundancy
*/
#define OCOTP_CTRL_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WORDLOCK_SHIFT)) & OCOTP_CTRL_WORDLOCK_MASK)
#define OCOTP_CTRL_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_CTRL_WR_UNLOCK_SHIFT (16U)
/*! WR_UNLOCK - Write unlock
* 0b0000000000000000..OTP write access is locked.
* 0b0011111001110111..OTP write access is unlocked.
*/
#define OCOTP_CTRL_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_WR_UNLOCK_MASK)
/*! @} */
/*! @name CTRL_SET - OTP Controller Control and Status Register */
/*! @{ */
#define OCOTP_CTRL_SET_ADDR_MASK (0x3FFU)
#define OCOTP_CTRL_SET_ADDR_SHIFT (0U)
/*! ADDR - OTP write and read access address register
*/
#define OCOTP_CTRL_SET_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ADDR_SHIFT)) & OCOTP_CTRL_SET_ADDR_MASK)
#define OCOTP_CTRL_SET_BUSY_MASK (0x400U)
#define OCOTP_CTRL_SET_BUSY_SHIFT (10U)
/*! BUSY - OTP controller status bit
*/
#define OCOTP_CTRL_SET_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_BUSY_SHIFT)) & OCOTP_CTRL_SET_BUSY_MASK)
#define OCOTP_CTRL_SET_ERROR_MASK (0x800U)
#define OCOTP_CTRL_SET_ERROR_SHIFT (11U)
/*! ERROR - Locked Region Access Error
*/
#define OCOTP_CTRL_SET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_ERROR_SHIFT)) & OCOTP_CTRL_SET_ERROR_MASK)
#define OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK (0x1000U)
#define OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT (12U)
/*! RELOAD_SHADOWS - Reload Shadow Registers
*/
#define OCOTP_CTRL_SET_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_SET_RELOAD_SHADOWS_MASK)
#define OCOTP_CTRL_SET_WORDLOCK_MASK (0x8000U)
#define OCOTP_CTRL_SET_WORDLOCK_SHIFT (15U)
/*! WORDLOCK - Lock fuse word
*/
#define OCOTP_CTRL_SET_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WORDLOCK_SHIFT)) & OCOTP_CTRL_SET_WORDLOCK_MASK)
#define OCOTP_CTRL_SET_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_CTRL_SET_WR_UNLOCK_SHIFT (16U)
/*! WR_UNLOCK - Write unlock
*/
#define OCOTP_CTRL_SET_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_SET_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_SET_WR_UNLOCK_MASK)
/*! @} */
/*! @name CTRL_CLR - OTP Controller Control and Status Register */
/*! @{ */
#define OCOTP_CTRL_CLR_ADDR_MASK (0x3FFU)
#define OCOTP_CTRL_CLR_ADDR_SHIFT (0U)
/*! ADDR - OTP write and read access address register
*/
#define OCOTP_CTRL_CLR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ADDR_SHIFT)) & OCOTP_CTRL_CLR_ADDR_MASK)
#define OCOTP_CTRL_CLR_BUSY_MASK (0x400U)
#define OCOTP_CTRL_CLR_BUSY_SHIFT (10U)
/*! BUSY - OTP controller status bit
*/
#define OCOTP_CTRL_CLR_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_BUSY_SHIFT)) & OCOTP_CTRL_CLR_BUSY_MASK)
#define OCOTP_CTRL_CLR_ERROR_MASK (0x800U)
#define OCOTP_CTRL_CLR_ERROR_SHIFT (11U)
/*! ERROR - Locked Region Access Error
*/
#define OCOTP_CTRL_CLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_ERROR_SHIFT)) & OCOTP_CTRL_CLR_ERROR_MASK)
#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK (0x1000U)
#define OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT (12U)
/*! RELOAD_SHADOWS - Reload Shadow Registers
*/
#define OCOTP_CTRL_CLR_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_CLR_RELOAD_SHADOWS_MASK)
#define OCOTP_CTRL_CLR_WORDLOCK_MASK (0x8000U)
#define OCOTP_CTRL_CLR_WORDLOCK_SHIFT (15U)
/*! WORDLOCK - Lock fuse word
*/
#define OCOTP_CTRL_CLR_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WORDLOCK_SHIFT)) & OCOTP_CTRL_CLR_WORDLOCK_MASK)
#define OCOTP_CTRL_CLR_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT (16U)
/*! WR_UNLOCK - Write unlock
*/
#define OCOTP_CTRL_CLR_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_CLR_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_CLR_WR_UNLOCK_MASK)
/*! @} */
/*! @name CTRL_TOG - OTP Controller Control and Status Register */
/*! @{ */
#define OCOTP_CTRL_TOG_ADDR_MASK (0x3FFU)
#define OCOTP_CTRL_TOG_ADDR_SHIFT (0U)
/*! ADDR - OTP write and read access address register
*/
#define OCOTP_CTRL_TOG_ADDR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ADDR_SHIFT)) & OCOTP_CTRL_TOG_ADDR_MASK)
#define OCOTP_CTRL_TOG_BUSY_MASK (0x400U)
#define OCOTP_CTRL_TOG_BUSY_SHIFT (10U)
/*! BUSY - OTP controller status bit
*/
#define OCOTP_CTRL_TOG_BUSY(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_BUSY_SHIFT)) & OCOTP_CTRL_TOG_BUSY_MASK)
#define OCOTP_CTRL_TOG_ERROR_MASK (0x800U)
#define OCOTP_CTRL_TOG_ERROR_SHIFT (11U)
/*! ERROR - Locked Region Access Error
*/
#define OCOTP_CTRL_TOG_ERROR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_ERROR_SHIFT)) & OCOTP_CTRL_TOG_ERROR_MASK)
#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK (0x1000U)
#define OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT (12U)
/*! RELOAD_SHADOWS - Reload Shadow Registers
*/
#define OCOTP_CTRL_TOG_RELOAD_SHADOWS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_RELOAD_SHADOWS_SHIFT)) & OCOTP_CTRL_TOG_RELOAD_SHADOWS_MASK)
#define OCOTP_CTRL_TOG_WORDLOCK_MASK (0x8000U)
#define OCOTP_CTRL_TOG_WORDLOCK_SHIFT (15U)
/*! WORDLOCK - Lock fuse word
*/
#define OCOTP_CTRL_TOG_WORDLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WORDLOCK_SHIFT)) & OCOTP_CTRL_TOG_WORDLOCK_MASK)
#define OCOTP_CTRL_TOG_WR_UNLOCK_MASK (0xFFFF0000U)
#define OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT (16U)
/*! WR_UNLOCK - Write unlock
*/
#define OCOTP_CTRL_TOG_WR_UNLOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_CTRL_TOG_WR_UNLOCK_SHIFT)) & OCOTP_CTRL_TOG_WR_UNLOCK_MASK)
/*! @} */
/*! @name PDN - OTP Controller PDN Register */
/*! @{ */
#define OCOTP_PDN_PDN_MASK (0x1U)
#define OCOTP_PDN_PDN_SHIFT (0U)
/*! PDN - PDN value
* 0b0..OTP memory is not powered
* 0b1..OTP memory is powered
*/
#define OCOTP_PDN_PDN(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_PDN_PDN_SHIFT)) & OCOTP_PDN_PDN_MASK)
/*! @} */
/*! @name DATA - OTP Controller Write Data Register */
/*! @{ */
#define OCOTP_DATA_DATA_MASK (0xFFFFFFFFU)
#define OCOTP_DATA_DATA_SHIFT (0U)
/*! DATA - Data
*/
#define OCOTP_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_DATA_DATA_SHIFT)) & OCOTP_DATA_DATA_MASK)
/*! @} */
/*! @name READ_CTRL - OTP Controller Read Control Register */
/*! @{ */
#define OCOTP_READ_CTRL_READ_FUSE_MASK (0x1U)
#define OCOTP_READ_CTRL_READ_FUSE_SHIFT (0U)
/*! READ_FUSE - Read Fuse
* 0b0..Do not initiate a read from OTP
* 0b1..Initiate a read from OTP
*/
#define OCOTP_READ_CTRL_READ_FUSE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_MASK)
#define OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK (0x6U)
#define OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT (1U)
/*! READ_FUSE_CNTR - Number of words to read.
* 0b00..1 word
* 0b01..2 words
* 0b10..3 words
* 0b11..4 words
*/
#define OCOTP_READ_CTRL_READ_FUSE_CNTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_CNTR_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_CNTR_MASK)
#define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK (0x8U)
#define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT (3U)
/*! READ_FUSE_DONE_INTR_ENA - Enable read-done interrupt
* 0b0..Disable
* 0b1..Enable
*/
#define OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_DONE_INTR_ENA_MASK)
#define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK (0x10U)
#define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT (4U)
/*! READ_FUSE_ERROR_INTR_ENA - Enable read-error interrupt
* 0b0..Disable
* 0b1..Enable
*/
#define OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_SHIFT)) & OCOTP_READ_CTRL_READ_FUSE_ERROR_INTR_ENA_MASK)
/*! @} */
/*! @name OUT_STATUS - 8K OTP Memory STATUS Register */
/*! @{ */
#define OCOTP_OUT_STATUS_SEC_MASK (0x200U)
#define OCOTP_OUT_STATUS_SEC_SHIFT (9U)
/*! SEC - Single Error Correct
*/
#define OCOTP_OUT_STATUS_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_SHIFT)) & OCOTP_OUT_STATUS_SEC_MASK)
#define OCOTP_OUT_STATUS_DED_MASK (0x400U)
#define OCOTP_OUT_STATUS_DED_SHIFT (10U)
/*! DED - Double error detect
*/
#define OCOTP_OUT_STATUS_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_SHIFT)) & OCOTP_OUT_STATUS_DED_MASK)
#define OCOTP_OUT_STATUS_LOCKED_MASK (0x800U)
#define OCOTP_OUT_STATUS_LOCKED_SHIFT (11U)
/*! LOCKED - Word Locked
*/
#define OCOTP_OUT_STATUS_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_LOCKED_MASK)
#define OCOTP_OUT_STATUS_PROGFAIL_MASK (0x1000U)
#define OCOTP_OUT_STATUS_PROGFAIL_SHIFT (12U)
/*! PROGFAIL - Programming failed
*/
#define OCOTP_OUT_STATUS_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_PROGFAIL_MASK)
#define OCOTP_OUT_STATUS_ACK_MASK (0x2000U)
#define OCOTP_OUT_STATUS_ACK_SHIFT (13U)
/*! ACK - Acknowledge
*/
#define OCOTP_OUT_STATUS_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_ACK_SHIFT)) & OCOTP_OUT_STATUS_ACK_MASK)
#define OCOTP_OUT_STATUS_PWOK_MASK (0x4000U)
#define OCOTP_OUT_STATUS_PWOK_SHIFT (14U)
/*! PWOK - Power OK
*/
#define OCOTP_OUT_STATUS_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_PWOK_SHIFT)) & OCOTP_OUT_STATUS_PWOK_MASK)
#define OCOTP_OUT_STATUS_FLAGSTATE_MASK (0x78000U)
#define OCOTP_OUT_STATUS_FLAGSTATE_SHIFT (15U)
/*! FLAGSTATE - Flag state
*/
#define OCOTP_OUT_STATUS_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_FLAGSTATE_MASK)
#define OCOTP_OUT_STATUS_SEC_RELOAD_MASK (0x80000U)
#define OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT (19U)
/*! SEC_RELOAD - Indicates single error correction occured on reload
*/
#define OCOTP_OUT_STATUS_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SEC_RELOAD_MASK)
#define OCOTP_OUT_STATUS_DED_RELOAD_MASK (0x100000U)
#define OCOTP_OUT_STATUS_DED_RELOAD_SHIFT (20U)
/*! DED_RELOAD - Indicates double error detection occured on reload
*/
#define OCOTP_OUT_STATUS_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_DED_RELOAD_MASK)
#define OCOTP_OUT_STATUS_CALIBRATED_MASK (0x200000U)
#define OCOTP_OUT_STATUS_CALIBRATED_SHIFT (21U)
/*! CALIBRATED - Calibrated status
*/
#define OCOTP_OUT_STATUS_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CALIBRATED_MASK)
#define OCOTP_OUT_STATUS_READ_DONE_INTR_MASK (0x400000U)
#define OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT (22U)
/*! READ_DONE_INTR - Read fuse done
*/
#define OCOTP_OUT_STATUS_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_DONE_INTR_MASK)
#define OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK (0x800000U)
#define OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT (23U)
/*! READ_ERROR_INTR - Fuse read error
* 0b0..Read operation finished with out any error
* 0b1..Read operation finished with an error
*/
#define OCOTP_OUT_STATUS_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_READ_ERROR_INTR_MASK)
#define OCOTP_OUT_STATUS_DED0_MASK (0x1000000U)
#define OCOTP_OUT_STATUS_DED0_SHIFT (24U)
/*! DED0 - Double error detect
*/
#define OCOTP_OUT_STATUS_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED0_SHIFT)) & OCOTP_OUT_STATUS_DED0_MASK)
#define OCOTP_OUT_STATUS_DED1_MASK (0x2000000U)
#define OCOTP_OUT_STATUS_DED1_SHIFT (25U)
/*! DED1 - Double error detect
*/
#define OCOTP_OUT_STATUS_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED1_SHIFT)) & OCOTP_OUT_STATUS_DED1_MASK)
#define OCOTP_OUT_STATUS_DED2_MASK (0x4000000U)
#define OCOTP_OUT_STATUS_DED2_SHIFT (26U)
/*! DED2 - Double error detect
*/
#define OCOTP_OUT_STATUS_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED2_SHIFT)) & OCOTP_OUT_STATUS_DED2_MASK)
#define OCOTP_OUT_STATUS_DED3_MASK (0x8000000U)
#define OCOTP_OUT_STATUS_DED3_SHIFT (27U)
/*! DED3 - Double error detect
*/
#define OCOTP_OUT_STATUS_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_DED3_SHIFT)) & OCOTP_OUT_STATUS_DED3_MASK)
/*! @} */
/*! @name OUT_STATUS_SET - 8K OTP Memory STATUS Register */
/*! @{ */
#define OCOTP_OUT_STATUS_SET_SEC_MASK (0x200U)
#define OCOTP_OUT_STATUS_SET_SEC_SHIFT (9U)
/*! SEC - Single Error Correct
*/
#define OCOTP_OUT_STATUS_SET_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_MASK)
#define OCOTP_OUT_STATUS_SET_DED_MASK (0x400U)
#define OCOTP_OUT_STATUS_SET_DED_SHIFT (10U)
/*! DED - Double error detect
*/
#define OCOTP_OUT_STATUS_SET_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_MASK)
#define OCOTP_OUT_STATUS_SET_LOCKED_MASK (0x800U)
#define OCOTP_OUT_STATUS_SET_LOCKED_SHIFT (11U)
/*! LOCKED - Word Locked
*/
#define OCOTP_OUT_STATUS_SET_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_SET_LOCKED_MASK)
#define OCOTP_OUT_STATUS_SET_PROGFAIL_MASK (0x1000U)
#define OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT (12U)
/*! PROGFAIL - Programming failed
*/
#define OCOTP_OUT_STATUS_SET_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_SET_PROGFAIL_MASK)
#define OCOTP_OUT_STATUS_SET_ACK_MASK (0x2000U)
#define OCOTP_OUT_STATUS_SET_ACK_SHIFT (13U)
/*! ACK - Acknowledge
*/
#define OCOTP_OUT_STATUS_SET_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_ACK_SHIFT)) & OCOTP_OUT_STATUS_SET_ACK_MASK)
#define OCOTP_OUT_STATUS_SET_PWOK_MASK (0x4000U)
#define OCOTP_OUT_STATUS_SET_PWOK_SHIFT (14U)
/*! PWOK - Power OK
*/
#define OCOTP_OUT_STATUS_SET_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_PWOK_SHIFT)) & OCOTP_OUT_STATUS_SET_PWOK_MASK)
#define OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK (0x78000U)
#define OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT (15U)
/*! FLAGSTATE - Flag state
*/
#define OCOTP_OUT_STATUS_SET_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_SET_FLAGSTATE_MASK)
#define OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK (0x80000U)
#define OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT (19U)
/*! SEC_RELOAD - Indicates single error correction occured on reload
*/
#define OCOTP_OUT_STATUS_SET_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_SEC_RELOAD_MASK)
#define OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK (0x100000U)
#define OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT (20U)
/*! DED_RELOAD - Indicates double error detection occured on reload
*/
#define OCOTP_OUT_STATUS_SET_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_SET_DED_RELOAD_MASK)
#define OCOTP_OUT_STATUS_SET_CALIBRATED_MASK (0x200000U)
#define OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT (21U)
/*! CALIBRATED - Calibrated status
*/
#define OCOTP_OUT_STATUS_SET_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_SET_CALIBRATED_MASK)
#define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK (0x400000U)
#define OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT (22U)
/*! READ_DONE_INTR - Read fuse done
*/
#define OCOTP_OUT_STATUS_SET_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_DONE_INTR_MASK)
#define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK (0x800000U)
#define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT (23U)
/*! READ_ERROR_INTR - Fuse read error
*/
#define OCOTP_OUT_STATUS_SET_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_SET_READ_ERROR_INTR_MASK)
#define OCOTP_OUT_STATUS_SET_DED0_MASK (0x1000000U)
#define OCOTP_OUT_STATUS_SET_DED0_SHIFT (24U)
/*! DED0 - Double error detect
*/
#define OCOTP_OUT_STATUS_SET_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED0_SHIFT)) & OCOTP_OUT_STATUS_SET_DED0_MASK)
#define OCOTP_OUT_STATUS_SET_DED1_MASK (0x2000000U)
#define OCOTP_OUT_STATUS_SET_DED1_SHIFT (25U)
/*! DED1 - Double error detect
*/
#define OCOTP_OUT_STATUS_SET_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED1_SHIFT)) & OCOTP_OUT_STATUS_SET_DED1_MASK)
#define OCOTP_OUT_STATUS_SET_DED2_MASK (0x4000000U)
#define OCOTP_OUT_STATUS_SET_DED2_SHIFT (26U)
/*! DED2 - Double error detect
*/
#define OCOTP_OUT_STATUS_SET_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED2_SHIFT)) & OCOTP_OUT_STATUS_SET_DED2_MASK)
#define OCOTP_OUT_STATUS_SET_DED3_MASK (0x8000000U)
#define OCOTP_OUT_STATUS_SET_DED3_SHIFT (27U)
/*! DED3 - Double error detect
*/
#define OCOTP_OUT_STATUS_SET_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_SET_DED3_SHIFT)) & OCOTP_OUT_STATUS_SET_DED3_MASK)
/*! @} */
/*! @name OUT_STATUS_CLR - 8K OTP Memory STATUS Register */
/*! @{ */
#define OCOTP_OUT_STATUS_CLR_SEC_MASK (0x200U)
#define OCOTP_OUT_STATUS_CLR_SEC_SHIFT (9U)
/*! SEC - Single Error Correct
*/
#define OCOTP_OUT_STATUS_CLR_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_MASK)
#define OCOTP_OUT_STATUS_CLR_DED_MASK (0x400U)
#define OCOTP_OUT_STATUS_CLR_DED_SHIFT (10U)
/*! DED - Double error detect
*/
#define OCOTP_OUT_STATUS_CLR_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_MASK)
#define OCOTP_OUT_STATUS_CLR_LOCKED_MASK (0x800U)
#define OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT (11U)
/*! LOCKED - Word Locked
*/
#define OCOTP_OUT_STATUS_CLR_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_CLR_LOCKED_MASK)
#define OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK (0x1000U)
#define OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT (12U)
/*! PROGFAIL - Programming failed
*/
#define OCOTP_OUT_STATUS_CLR_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_CLR_PROGFAIL_MASK)
#define OCOTP_OUT_STATUS_CLR_ACK_MASK (0x2000U)
#define OCOTP_OUT_STATUS_CLR_ACK_SHIFT (13U)
/*! ACK - Acknowledge
*/
#define OCOTP_OUT_STATUS_CLR_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_ACK_SHIFT)) & OCOTP_OUT_STATUS_CLR_ACK_MASK)
#define OCOTP_OUT_STATUS_CLR_PWOK_MASK (0x4000U)
#define OCOTP_OUT_STATUS_CLR_PWOK_SHIFT (14U)
/*! PWOK - Power OK
*/
#define OCOTP_OUT_STATUS_CLR_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_PWOK_SHIFT)) & OCOTP_OUT_STATUS_CLR_PWOK_MASK)
#define OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK (0x78000U)
#define OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT (15U)
/*! FLAGSTATE - Flag state
*/
#define OCOTP_OUT_STATUS_CLR_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_CLR_FLAGSTATE_MASK)
#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK (0x80000U)
#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT (19U)
/*! SEC_RELOAD - Indicates single error correction occured on reload
*/
#define OCOTP_OUT_STATUS_CLR_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_SEC_RELOAD_MASK)
#define OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK (0x100000U)
#define OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT (20U)
/*! DED_RELOAD - Indicates double error detection occured on reload
*/
#define OCOTP_OUT_STATUS_CLR_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED_RELOAD_MASK)
#define OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK (0x200000U)
#define OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT (21U)
/*! CALIBRATED - Calibrated status
*/
#define OCOTP_OUT_STATUS_CLR_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_CLR_CALIBRATED_MASK)
#define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK (0x400000U)
#define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT (22U)
/*! READ_DONE_INTR - Read fuse done
*/
#define OCOTP_OUT_STATUS_CLR_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_DONE_INTR_MASK)
#define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK (0x800000U)
#define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT (23U)
/*! READ_ERROR_INTR - Fuse read error
*/
#define OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_CLR_READ_ERROR_INTR_MASK)
#define OCOTP_OUT_STATUS_CLR_DED0_MASK (0x1000000U)
#define OCOTP_OUT_STATUS_CLR_DED0_SHIFT (24U)
/*! DED0 - Double error detect
*/
#define OCOTP_OUT_STATUS_CLR_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED0_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED0_MASK)
#define OCOTP_OUT_STATUS_CLR_DED1_MASK (0x2000000U)
#define OCOTP_OUT_STATUS_CLR_DED1_SHIFT (25U)
/*! DED1 - Double error detect
*/
#define OCOTP_OUT_STATUS_CLR_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED1_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED1_MASK)
#define OCOTP_OUT_STATUS_CLR_DED2_MASK (0x4000000U)
#define OCOTP_OUT_STATUS_CLR_DED2_SHIFT (26U)
/*! DED2 - Double error detect
*/
#define OCOTP_OUT_STATUS_CLR_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED2_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED2_MASK)
#define OCOTP_OUT_STATUS_CLR_DED3_MASK (0x8000000U)
#define OCOTP_OUT_STATUS_CLR_DED3_SHIFT (27U)
/*! DED3 - Double error detect
*/
#define OCOTP_OUT_STATUS_CLR_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_CLR_DED3_SHIFT)) & OCOTP_OUT_STATUS_CLR_DED3_MASK)
/*! @} */
/*! @name OUT_STATUS_TOG - 8K OTP Memory STATUS Register */
/*! @{ */
#define OCOTP_OUT_STATUS_TOG_SEC_MASK (0x200U)
#define OCOTP_OUT_STATUS_TOG_SEC_SHIFT (9U)
/*! SEC - Single Error Correct
*/
#define OCOTP_OUT_STATUS_TOG_SEC(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_MASK)
#define OCOTP_OUT_STATUS_TOG_DED_MASK (0x400U)
#define OCOTP_OUT_STATUS_TOG_DED_SHIFT (10U)
/*! DED - Double error detect
*/
#define OCOTP_OUT_STATUS_TOG_DED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_MASK)
#define OCOTP_OUT_STATUS_TOG_LOCKED_MASK (0x800U)
#define OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT (11U)
/*! LOCKED - Word Locked
*/
#define OCOTP_OUT_STATUS_TOG_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_LOCKED_SHIFT)) & OCOTP_OUT_STATUS_TOG_LOCKED_MASK)
#define OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK (0x1000U)
#define OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT (12U)
/*! PROGFAIL - Programming failed
*/
#define OCOTP_OUT_STATUS_TOG_PROGFAIL(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PROGFAIL_SHIFT)) & OCOTP_OUT_STATUS_TOG_PROGFAIL_MASK)
#define OCOTP_OUT_STATUS_TOG_ACK_MASK (0x2000U)
#define OCOTP_OUT_STATUS_TOG_ACK_SHIFT (13U)
/*! ACK - Acknowledge
*/
#define OCOTP_OUT_STATUS_TOG_ACK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_ACK_SHIFT)) & OCOTP_OUT_STATUS_TOG_ACK_MASK)
#define OCOTP_OUT_STATUS_TOG_PWOK_MASK (0x4000U)
#define OCOTP_OUT_STATUS_TOG_PWOK_SHIFT (14U)
/*! PWOK - Power OK
*/
#define OCOTP_OUT_STATUS_TOG_PWOK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_PWOK_SHIFT)) & OCOTP_OUT_STATUS_TOG_PWOK_MASK)
#define OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK (0x78000U)
#define OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT (15U)
/*! FLAGSTATE - Flag state
*/
#define OCOTP_OUT_STATUS_TOG_FLAGSTATE(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_FLAGSTATE_SHIFT)) & OCOTP_OUT_STATUS_TOG_FLAGSTATE_MASK)
#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK (0x80000U)
#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT (19U)
/*! SEC_RELOAD - Indicates single error correction occured on reload
*/
#define OCOTP_OUT_STATUS_TOG_SEC_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_SEC_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_SEC_RELOAD_MASK)
#define OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK (0x100000U)
#define OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT (20U)
/*! DED_RELOAD - Indicates double error detection occured on reload
*/
#define OCOTP_OUT_STATUS_TOG_DED_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED_RELOAD_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED_RELOAD_MASK)
#define OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK (0x200000U)
#define OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT (21U)
/*! CALIBRATED - Calibrated status
*/
#define OCOTP_OUT_STATUS_TOG_CALIBRATED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_CALIBRATED_SHIFT)) & OCOTP_OUT_STATUS_TOG_CALIBRATED_MASK)
#define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK (0x400000U)
#define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT (22U)
/*! READ_DONE_INTR - Read fuse done
*/
#define OCOTP_OUT_STATUS_TOG_READ_DONE_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_DONE_INTR_MASK)
#define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK (0x800000U)
#define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT (23U)
/*! READ_ERROR_INTR - Fuse read error
*/
#define OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_SHIFT)) & OCOTP_OUT_STATUS_TOG_READ_ERROR_INTR_MASK)
#define OCOTP_OUT_STATUS_TOG_DED0_MASK (0x1000000U)
#define OCOTP_OUT_STATUS_TOG_DED0_SHIFT (24U)
/*! DED0 - Double error detect
*/
#define OCOTP_OUT_STATUS_TOG_DED0(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED0_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED0_MASK)
#define OCOTP_OUT_STATUS_TOG_DED1_MASK (0x2000000U)
#define OCOTP_OUT_STATUS_TOG_DED1_SHIFT (25U)
/*! DED1 - Double error detect
*/
#define OCOTP_OUT_STATUS_TOG_DED1(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED1_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED1_MASK)
#define OCOTP_OUT_STATUS_TOG_DED2_MASK (0x4000000U)
#define OCOTP_OUT_STATUS_TOG_DED2_SHIFT (26U)
/*! DED2 - Double error detect
*/
#define OCOTP_OUT_STATUS_TOG_DED2(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED2_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED2_MASK)
#define OCOTP_OUT_STATUS_TOG_DED3_MASK (0x8000000U)
#define OCOTP_OUT_STATUS_TOG_DED3_SHIFT (27U)
/*! DED3 - Double error detect
*/
#define OCOTP_OUT_STATUS_TOG_DED3(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_OUT_STATUS_TOG_DED3_SHIFT)) & OCOTP_OUT_STATUS_TOG_DED3_MASK)
/*! @} */
/*! @name VERSION - OTP Controller Version Register */
/*! @{ */
#define OCOTP_VERSION_STEP_MASK (0xFFFFU)
#define OCOTP_VERSION_STEP_SHIFT (0U)
/*! STEP - RTL Version Stepping
*/
#define OCOTP_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_STEP_SHIFT)) & OCOTP_VERSION_STEP_MASK)
#define OCOTP_VERSION_MINOR_MASK (0xFF0000U)
#define OCOTP_VERSION_MINOR_SHIFT (16U)
/*! MINOR - Minor RTL Version
*/
#define OCOTP_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MINOR_SHIFT)) & OCOTP_VERSION_MINOR_MASK)
#define OCOTP_VERSION_MAJOR_MASK (0xFF000000U)
#define OCOTP_VERSION_MAJOR_SHIFT (24U)
/*! MAJOR - Major RTL Version
*/
#define OCOTP_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_VERSION_MAJOR_SHIFT)) & OCOTP_VERSION_MAJOR_MASK)
/*! @} */
/*! @name READ_FUSE_DATA - OTP Controller Read Data 0 Register..OTP Controller Read Data 3 Register */
/*! @{ */
#define OCOTP_READ_FUSE_DATA_DATA_MASK (0xFFFFFFFFU)
#define OCOTP_READ_FUSE_DATA_DATA_SHIFT (0U)
/*! DATA - Data
*/
#define OCOTP_READ_FUSE_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_READ_FUSE_DATA_DATA_SHIFT)) & OCOTP_READ_FUSE_DATA_DATA_MASK)
/*! @} */
/* The count of OCOTP_READ_FUSE_DATA */
#define OCOTP_READ_FUSE_DATA_COUNT (4U)
/*! @name SW_LOCK - SW_LOCK Register */
/*! @{ */
#define OCOTP_SW_LOCK_SW_LOCK_MASK (0xFFFFFFFFU)
#define OCOTP_SW_LOCK_SW_LOCK_SHIFT (0U)
#define OCOTP_SW_LOCK_SW_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_SW_LOCK_SW_LOCK_SHIFT)) & OCOTP_SW_LOCK_SW_LOCK_MASK)
/*! @} */
/*! @name BIT_LOCK - BIT_LOCK Register */
/*! @{ */
#define OCOTP_BIT_LOCK_BIT_LOCK_MASK (0xFFFFFFFFU)
#define OCOTP_BIT_LOCK_BIT_LOCK_SHIFT (0U)
#define OCOTP_BIT_LOCK_BIT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_BIT_LOCK_BIT_LOCK_SHIFT)) & OCOTP_BIT_LOCK_BIT_LOCK_MASK)
/*! @} */
/*! @name LOCKED0 - OTP Controller Program Locked Status 0 Register */
/*! @{ */
#define OCOTP_LOCKED0_LOCKED_MASK (0xFFFFU)
#define OCOTP_LOCKED0_LOCKED_SHIFT (0U)
#define OCOTP_LOCKED0_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED0_LOCKED_SHIFT)) & OCOTP_LOCKED0_LOCKED_MASK)
/*! @} */
/*! @name LOCKED1 - OTP Controller Program Locked Status 1 Register */
/*! @{ */
#define OCOTP_LOCKED1_LOCKED_MASK (0xFFFFFFFFU)
#define OCOTP_LOCKED1_LOCKED_SHIFT (0U)
#define OCOTP_LOCKED1_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED1_LOCKED_SHIFT)) & OCOTP_LOCKED1_LOCKED_MASK)
/*! @} */
/*! @name LOCKED2 - OTP Controller Program Locked Status 2 Register */
/*! @{ */
#define OCOTP_LOCKED2_LOCKED_MASK (0xFFFFFFFFU)
#define OCOTP_LOCKED2_LOCKED_SHIFT (0U)
#define OCOTP_LOCKED2_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED2_LOCKED_SHIFT)) & OCOTP_LOCKED2_LOCKED_MASK)
/*! @} */
/*! @name LOCKED3 - OTP Controller Program Locked Status 3 Register */
/*! @{ */
#define OCOTP_LOCKED3_LOCKED_MASK (0xFFFFFFFFU)
#define OCOTP_LOCKED3_LOCKED_SHIFT (0U)
#define OCOTP_LOCKED3_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED3_LOCKED_SHIFT)) & OCOTP_LOCKED3_LOCKED_MASK)
/*! @} */
/*! @name LOCKED4 - OTP Controller Program Locked Status 4 Register */
/*! @{ */
#define OCOTP_LOCKED4_LOCKED_MASK (0xFFFFFFFFU)
#define OCOTP_LOCKED4_LOCKED_SHIFT (0U)
#define OCOTP_LOCKED4_LOCKED(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_LOCKED4_LOCKED_SHIFT)) & OCOTP_LOCKED4_LOCKED_MASK)
/*! @} */
/*! @name FUSE - Value of fuse word 0..Value of fuse word 143 */
/*! @{ */
#define OCOTP_FUSE_BITS_MASK (0xFFFFFFFFU)
#define OCOTP_FUSE_BITS_SHIFT (0U)
/*! BITS - Reflects value of the fuse word
*/
#define OCOTP_FUSE_BITS(x) (((uint32_t)(((uint32_t)(x)) << OCOTP_FUSE_BITS_SHIFT)) & OCOTP_FUSE_BITS_MASK)
/*! @} */
/* The count of OCOTP_FUSE */
#define OCOTP_FUSE_COUNT (144U)
/*!
* @}
*/ /* end of group OCOTP_Register_Masks */
/* OCOTP - Peripheral instance base addresses */
/** Peripheral OCOTP base address */
#define OCOTP_BASE (0x40CAC000u)
/** Peripheral OCOTP base pointer */
#define OCOTP ((OCOTP_Type *)OCOTP_BASE)
/** Array initializer of OCOTP peripheral base addresses */
#define OCOTP_BASE_ADDRS { OCOTP_BASE }
/** Array initializer of OCOTP peripheral base pointers */
#define OCOTP_BASE_PTRS { OCOTP }
/*!
* @}
*/ /* end of group OCOTP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- OSC_RC_400M Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup OSC_RC_400M_Peripheral_Access_Layer OSC_RC_400M Peripheral Access Layer
* @{
*/
/** OSC_RC_400M - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0 */
__IO uint32_t RW; /**< Control Register 0, offset: 0x0 */
__IO uint32_t SET; /**< Control Register 0, offset: 0x4 */
__IO uint32_t CLR; /**< Control Register 0, offset: 0x8 */
__IO uint32_t TOG; /**< Control Register 0, offset: 0xC */
} CTRL0;
struct { /* offset: 0x10 */
__IO uint32_t RW; /**< Control Register 1, offset: 0x10 */
__IO uint32_t SET; /**< Control Register 1, offset: 0x14 */
__IO uint32_t CLR; /**< Control Register 1, offset: 0x18 */
__IO uint32_t TOG; /**< Control Register 1, offset: 0x1C */
} CTRL1;
struct { /* offset: 0x20 */
__IO uint32_t RW; /**< Control Register 2, offset: 0x20 */
__IO uint32_t SET; /**< Control Register 2, offset: 0x24 */
__IO uint32_t CLR; /**< Control Register 2, offset: 0x28 */
__IO uint32_t TOG; /**< Control Register 2, offset: 0x2C */
} CTRL2;
struct { /* offset: 0x30 */
__IO uint32_t RW; /**< Control Register 3, offset: 0x30 */
__IO uint32_t SET; /**< Control Register 3, offset: 0x34 */
__IO uint32_t CLR; /**< Control Register 3, offset: 0x38 */
__IO uint32_t TOG; /**< Control Register 3, offset: 0x3C */
} CTRL3;
uint8_t RESERVED_0[16];
struct { /* offset: 0x50 */
__I uint32_t RW; /**< Status Register 0, offset: 0x50 */
__I uint32_t SET; /**< Status Register 0, offset: 0x54 */
__I uint32_t CLR; /**< Status Register 0, offset: 0x58 */
__I uint32_t TOG; /**< Status Register 0, offset: 0x5C */
} STAT0;
struct { /* offset: 0x60 */
__I uint32_t RW; /**< Status Register 1, offset: 0x60 */
__I uint32_t SET; /**< Status Register 1, offset: 0x64 */
__I uint32_t CLR; /**< Status Register 1, offset: 0x68 */
__I uint32_t TOG; /**< Status Register 1, offset: 0x6C */
} STAT1;
struct { /* offset: 0x70 */
__I uint32_t RW; /**< Status Register 2, offset: 0x70 */
__I uint32_t SET; /**< Status Register 2, offset: 0x74 */
__I uint32_t CLR; /**< Status Register 2, offset: 0x78 */
__I uint32_t TOG; /**< Status Register 2, offset: 0x7C */
} STAT2;
} OSC_RC_400M_Type;
/* ----------------------------------------------------------------------------
-- OSC_RC_400M Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup OSC_RC_400M_Register_Masks OSC_RC_400M Register Masks
* @{
*/
/*! @name CTRL0 - Control Register 0 */
/*! @{ */
#define OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK (0x3F000000U)
#define OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT (24U)
/*! REF_CLK_DIV - Divide value for ref_clk to generate slow_clk (used inside this IP)
*/
#define OSC_RC_400M_CTRL0_REF_CLK_DIV(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL0_REF_CLK_DIV_SHIFT)) & OSC_RC_400M_CTRL0_REF_CLK_DIV_MASK)
/*! @} */
/*! @name CTRL1 - Control Register 1 */
/*! @{ */
#define OSC_RC_400M_CTRL1_HYST_MINUS_MASK (0xFU)
#define OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT (0U)
/*! HYST_MINUS - Negative hysteresis value for the tuned clock
*/
#define OSC_RC_400M_CTRL1_HYST_MINUS(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_MINUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_MINUS_MASK)
#define OSC_RC_400M_CTRL1_HYST_PLUS_MASK (0xF00U)
#define OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT (8U)
/*! HYST_PLUS - Positive hysteresis value for the tuned clock
*/
#define OSC_RC_400M_CTRL1_HYST_PLUS(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_HYST_PLUS_SHIFT)) & OSC_RC_400M_CTRL1_HYST_PLUS_MASK)
#define OSC_RC_400M_CTRL1_TARGET_COUNT_MASK (0xFFFF0000U)
#define OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT (16U)
/*! TARGET_COUNT - Target count for the fast clock
*/
#define OSC_RC_400M_CTRL1_TARGET_COUNT(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL1_TARGET_COUNT_SHIFT)) & OSC_RC_400M_CTRL1_TARGET_COUNT_MASK)
/*! @} */
/*! @name CTRL2 - Control Register 2 */
/*! @{ */
#define OSC_RC_400M_CTRL2_TUNE_BYP_MASK (0x400U)
#define OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT (10U)
/*! TUNE_BYP - Bypass the tuning logic
* 0b0..Use the output of tuning logic to run the oscillator
* 0b1..Bypass the tuning logic and use the programmed OSC_TUNE_VAL to run the oscillator
*/
#define OSC_RC_400M_CTRL2_TUNE_BYP(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_BYP_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_BYP_MASK)
#define OSC_RC_400M_CTRL2_TUNE_EN_MASK (0x1000U)
#define OSC_RC_400M_CTRL2_TUNE_EN_SHIFT (12U)
/*! TUNE_EN - Freeze/Unfreeze the tuning value
* 0b0..Freezes the tuning at the current tuned value. Oscillator runs at the frozen tuning value
* 0b1..Unfreezes and continues the tuning operation
*/
#define OSC_RC_400M_CTRL2_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_EN_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_EN_MASK)
#define OSC_RC_400M_CTRL2_TUNE_START_MASK (0x4000U)
#define OSC_RC_400M_CTRL2_TUNE_START_SHIFT (14U)
/*! TUNE_START - Start/Stop tuning
* 0b0..Stop tuning and reset the tuning logic. Oscillator runs using programmed OSC_TUNE_VAL
* 0b1..Start tuning
*/
#define OSC_RC_400M_CTRL2_TUNE_START(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_TUNE_START_SHIFT)) & OSC_RC_400M_CTRL2_TUNE_START_MASK)
#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK (0xFF000000U)
#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT (24U)
/*! OSC_TUNE_VAL - Program the oscillator frequency
*/
#define OSC_RC_400M_CTRL2_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL2_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_CTRL2_OSC_TUNE_VAL_MASK)
/*! @} */
/*! @name CTRL3 - Control Register 3 */
/*! @{ */
#define OSC_RC_400M_CTRL3_CLR_ERR_MASK (0x1U)
#define OSC_RC_400M_CTRL3_CLR_ERR_SHIFT (0U)
/*! CLR_ERR - Clear the error flag CLK1M_ERR
* 0b0..No effect
* 0b1..Clears the error flag CLK1M_ERR in status register STAT0
*/
#define OSC_RC_400M_CTRL3_CLR_ERR(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_CLR_ERR_SHIFT)) & OSC_RC_400M_CTRL3_CLR_ERR_MASK)
#define OSC_RC_400M_CTRL3_EN_1M_CLK_MASK (0x100U)
#define OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT (8U)
/*! EN_1M_CLK - Enable 1MHz output Clock
* 0b0..Enable the output (clk_1m_out)
* 0b1..Disable the output (clk_1m_out)
*/
#define OSC_RC_400M_CTRL3_EN_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_EN_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_EN_1M_CLK_MASK)
#define OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK (0x400U)
#define OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT (10U)
/*! MUX_1M_CLK - Select free/locked 1MHz output
* 0b0..Select free-running 1MHz to be put out on clk_1m_out
* 0b1..Select locked 1MHz to be put out on clk_1m_out
*/
#define OSC_RC_400M_CTRL3_MUX_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_MUX_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_MUX_1M_CLK_MASK)
#define OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK (0xFFFF0000U)
#define OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT (16U)
/*! COUNT_1M_CLK - Count for the locked clk_1m_out
*/
#define OSC_RC_400M_CTRL3_COUNT_1M_CLK(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_CTRL3_COUNT_1M_CLK_SHIFT)) & OSC_RC_400M_CTRL3_COUNT_1M_CLK_MASK)
/*! @} */
/*! @name STAT0 - Status Register 0 */
/*! @{ */
#define OSC_RC_400M_STAT0_CLK1M_ERR_MASK (0x1U)
#define OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT (0U)
/*! CLK1M_ERR - Error flag for clk_1m_locked
* 0b0..No effect
* 0b1..The count value has been reached within one divided ref_clk period
*/
#define OSC_RC_400M_STAT0_CLK1M_ERR(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT0_CLK1M_ERR_SHIFT)) & OSC_RC_400M_STAT0_CLK1M_ERR_MASK)
/*! @} */
/*! @name STAT1 - Status Register 1 */
/*! @{ */
#define OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK (0xFFFF0000U)
#define OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT (16U)
/*! CURR_COUNT_VAL - Current count for the fast clock
*/
#define OSC_RC_400M_STAT1_CURR_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT1_CURR_COUNT_VAL_SHIFT)) & OSC_RC_400M_STAT1_CURR_COUNT_VAL_MASK)
/*! @} */
/*! @name STAT2 - Status Register 2 */
/*! @{ */
#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK (0xFF000000U)
#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT (24U)
/*! CURR_OSC_TUNE_VAL - Current tuning value used by oscillator
*/
#define OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL(x) (((uint32_t)(((uint32_t)(x)) << OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_SHIFT)) & OSC_RC_400M_STAT2_CURR_OSC_TUNE_VAL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group OSC_RC_400M_Register_Masks */
/* OSC_RC_400M - Peripheral instance base addresses */
/** Peripheral OSC_RC_400M base address */
#define OSC_RC_400M_BASE (0u)
/** Peripheral OSC_RC_400M base pointer */
#define OSC_RC_400M ((OSC_RC_400M_Type *)OSC_RC_400M_BASE)
/** Array initializer of OSC_RC_400M peripheral base addresses */
#define OSC_RC_400M_BASE_ADDRS { OSC_RC_400M_BASE }
/** Array initializer of OSC_RC_400M peripheral base pointers */
#define OSC_RC_400M_BASE_PTRS { OSC_RC_400M }
/*!
* @}
*/ /* end of group OSC_RC_400M_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- OTFAD Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup OTFAD_Peripheral_Access_Layer OTFAD Peripheral Access Layer
* @{
*/
/** OTFAD - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[3072];
__IO uint32_t CR; /**< Control Register, offset: 0xC00 */
__IO uint32_t SR; /**< Status Register, offset: 0xC04 */
uint8_t RESERVED_1[248];
struct { /* offset: 0xD00, array step: 0x40 */
__IO uint32_t KEY[4]; /**< AES Key Word, array offset: 0xD00, array step: index*0x40, index2*0x4 */
__IO uint32_t CTR[2]; /**< AES Counter Word, array offset: 0xD10, array step: index*0x40, index2*0x4 */
__IO uint32_t RGD_W0; /**< AES Region Descriptor Word0, array offset: 0xD18, array step: 0x40 */
__IO uint32_t RGD_W1; /**< AES Region Descriptor Word1, array offset: 0xD1C, array step: 0x40 */
uint8_t RESERVED_0[32];
} CTX[4];
} OTFAD_Type;
/* ----------------------------------------------------------------------------
-- OTFAD Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup OTFAD_Register_Masks OTFAD Register Masks
* @{
*/
/*! @name CR - Control Register */
/*! @{ */
#define OTFAD_CR_FERR_MASK (0x2U)
#define OTFAD_CR_FERR_SHIFT (1U)
/*! FERR - Force Error
* 0b0..No effect on the SR[KBERE] indicator.
* 0b1..SR[KBERR] is immediately set after a write with this data bit set.
*/
#define OTFAD_CR_FERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FERR_SHIFT)) & OTFAD_CR_FERR_MASK)
#define OTFAD_CR_FLDM_MASK (0x8U)
#define OTFAD_CR_FLDM_SHIFT (3U)
/*! FLDM - Force Logically Disabled Mode
* 0b0..No effect on the operating mode.
* 0b1..Force entry into LDM after a write with this data bit set. SR[MODE] signals the operating mode.
*/
#define OTFAD_CR_FLDM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_FLDM_SHIFT)) & OTFAD_CR_FLDM_MASK)
#define OTFAD_CR_KBSE_MASK (0x10U)
#define OTFAD_CR_KBSE_SHIFT (4U)
/*! KBSE - Key Blob Scramble Enable
* 0b0..Key blob KEK scrambling is disabled.
* 0b1..Key blob KEK scrambling is enabled.
*/
#define OTFAD_CR_KBSE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBSE_SHIFT)) & OTFAD_CR_KBSE_MASK)
#define OTFAD_CR_KBPE_MASK (0x20U)
#define OTFAD_CR_KBPE_SHIFT (5U)
/*! KBPE - Key Blob Processing Enable
* 0b0..Key blob processing is disabled.
* 0b1..Key blob processing is enabled.
*/
#define OTFAD_CR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_KBPE_SHIFT)) & OTFAD_CR_KBPE_MASK)
#define OTFAD_CR_RRAE_MASK (0x80U)
#define OTFAD_CR_RRAE_SHIFT (7U)
/*! RRAE - Restricted Register Access Enable
* 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
* 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
*/
#define OTFAD_CR_RRAE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_RRAE_SHIFT)) & OTFAD_CR_RRAE_MASK)
#define OTFAD_CR_SKBP_MASK (0x40000000U)
#define OTFAD_CR_SKBP_SHIFT (30U)
/*! SKBP - Start key blob processing
* 0b0..Key blob processing is not initiated.
* 0b1..Properly-enabled key blob processing is initiated.
*/
#define OTFAD_CR_SKBP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_SKBP_SHIFT)) & OTFAD_CR_SKBP_MASK)
#define OTFAD_CR_GE_MASK (0x80000000U)
#define OTFAD_CR_GE_SHIFT (31U)
/*! GE - Global OTFAD Enable
* 0b0..OTFAD has decryption disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
* 0b1..OTFAD has decryption enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
*/
#define OTFAD_CR_GE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CR_GE_SHIFT)) & OTFAD_CR_GE_MASK)
/*! @} */
/*! @name SR - Status Register */
/*! @{ */
#define OTFAD_SR_KBERR_MASK (0x1U)
#define OTFAD_SR_KBERR_SHIFT (0U)
/*! KBERR - Key Blob Error
* 0b0..No key blob error detected.
* 0b1..One or more key blob errors has been detected.
*/
#define OTFAD_SR_KBERR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBERR_SHIFT)) & OTFAD_SR_KBERR_MASK)
#define OTFAD_SR_MDPCP_MASK (0x2U)
#define OTFAD_SR_MDPCP_SHIFT (1U)
/*! MDPCP - MDPC Present
*/
#define OTFAD_SR_MDPCP(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MDPCP_SHIFT)) & OTFAD_SR_MDPCP_MASK)
#define OTFAD_SR_MODE_MASK (0xCU)
#define OTFAD_SR_MODE_SHIFT (2U)
/*! MODE - Operating Mode
* 0b00..Operating in Normal mode (NRM)
* 0b01..Unused (reserved)
* 0b10..Unused (reserved)
* 0b11..Operating in Logically Disabled Mode (LDM)
*/
#define OTFAD_SR_MODE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_MODE_SHIFT)) & OTFAD_SR_MODE_MASK)
#define OTFAD_SR_NCTX_MASK (0xF0U)
#define OTFAD_SR_NCTX_SHIFT (4U)
/*! NCTX - Number of Contexts
*/
#define OTFAD_SR_NCTX(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_NCTX_SHIFT)) & OTFAD_SR_NCTX_MASK)
#define OTFAD_SR_CTXER0_MASK (0x100U)
#define OTFAD_SR_CTXER0_SHIFT (8U)
/*! CTXER0 - Context Error
* 0b0..No key blob error was detected for context "n".
* 0b1..A key blob integrity error might have been detected in context "n".
*/
#define OTFAD_SR_CTXER0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER0_SHIFT)) & OTFAD_SR_CTXER0_MASK)
#define OTFAD_SR_CTXER1_MASK (0x200U)
#define OTFAD_SR_CTXER1_SHIFT (9U)
/*! CTXER1 - Context Error
* 0b0..No key blob error was detected for context "n".
* 0b1..A key blob integrity error might have been detected in context "n".
*/
#define OTFAD_SR_CTXER1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER1_SHIFT)) & OTFAD_SR_CTXER1_MASK)
#define OTFAD_SR_CTXER2_MASK (0x400U)
#define OTFAD_SR_CTXER2_SHIFT (10U)
/*! CTXER2 - Context Error
* 0b0..No key blob error was detected for context "n".
* 0b1..A key blob integrity error might have been detected in context "n".
*/
#define OTFAD_SR_CTXER2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER2_SHIFT)) & OTFAD_SR_CTXER2_MASK)
#define OTFAD_SR_CTXER3_MASK (0x800U)
#define OTFAD_SR_CTXER3_SHIFT (11U)
/*! CTXER3 - Context Error
* 0b0..No key blob error was detected for context "n".
* 0b1..A key blob integrity error might have been detected in context "n".
*/
#define OTFAD_SR_CTXER3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXER3_SHIFT)) & OTFAD_SR_CTXER3_MASK)
#define OTFAD_SR_CTXIE0_MASK (0x10000U)
#define OTFAD_SR_CTXIE0_SHIFT (16U)
/*! CTXIE0 - Context Integrity Error
* 0b0..No key blob integrity error was detected for context "n".
* 0b1..A key blob integrity error was detected in context "n".
*/
#define OTFAD_SR_CTXIE0(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE0_SHIFT)) & OTFAD_SR_CTXIE0_MASK)
#define OTFAD_SR_CTXIE1_MASK (0x20000U)
#define OTFAD_SR_CTXIE1_SHIFT (17U)
/*! CTXIE1 - Context Integrity Error
* 0b0..No key blob integrity error was detected for context "n".
* 0b1..A key blob integrity error was detected in context "n".
*/
#define OTFAD_SR_CTXIE1(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE1_SHIFT)) & OTFAD_SR_CTXIE1_MASK)
#define OTFAD_SR_CTXIE2_MASK (0x40000U)
#define OTFAD_SR_CTXIE2_SHIFT (18U)
/*! CTXIE2 - Context Integrity Error
* 0b0..No key blob integrity error was detected for context "n".
* 0b1..A key blob integrity error was detected in context "n".
*/
#define OTFAD_SR_CTXIE2(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE2_SHIFT)) & OTFAD_SR_CTXIE2_MASK)
#define OTFAD_SR_CTXIE3_MASK (0x80000U)
#define OTFAD_SR_CTXIE3_SHIFT (19U)
/*! CTXIE3 - Context Integrity Error
* 0b0..No key blob integrity error was detected for context "n".
* 0b1..A key blob integrity error was detected in context "n".
*/
#define OTFAD_SR_CTXIE3(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_CTXIE3_SHIFT)) & OTFAD_SR_CTXIE3_MASK)
#define OTFAD_SR_HRL_MASK (0xF000000U)
#define OTFAD_SR_HRL_SHIFT (24U)
/*! HRL - Hardware Revision Level
*/
#define OTFAD_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_HRL_SHIFT)) & OTFAD_SR_HRL_MASK)
#define OTFAD_SR_RRAM_MASK (0x10000000U)
#define OTFAD_SR_RRAM_SHIFT (28U)
/*! RRAM - Restricted Register Access Mode
* 0b0..Register access is fully enabled. The OTFAD programming model registers can be accessed "normally".
* 0b1..Register access is restricted and only the CR, SR and optional MDPC registers can be accessed; others are treated as RAZ/WI.
*/
#define OTFAD_SR_RRAM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_RRAM_SHIFT)) & OTFAD_SR_RRAM_MASK)
#define OTFAD_SR_GEM_MASK (0x20000000U)
#define OTFAD_SR_GEM_SHIFT (29U)
/*! GEM - Global Enable Mode
* 0b0..OTFAD is disabled. All data fetched by the FlexSPI bypasses OTFAD processing.
* 0b1..OTFAD is enabled, and processes data fetched by the FlexSPI as defined by the hardware configuration.
*/
#define OTFAD_SR_GEM(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_GEM_SHIFT)) & OTFAD_SR_GEM_MASK)
#define OTFAD_SR_KBPE_MASK (0x40000000U)
#define OTFAD_SR_KBPE_SHIFT (30U)
/*! KBPE - Key Blob Processing Enable
* 0b0..Key blob processing is not enabled.
* 0b1..Key blob processing is enabled.
*/
#define OTFAD_SR_KBPE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBPE_SHIFT)) & OTFAD_SR_KBPE_MASK)
#define OTFAD_SR_KBD_MASK (0x80000000U)
#define OTFAD_SR_KBD_SHIFT (31U)
/*! KBD - Key Blob Processing Done
* 0b0..Key blob processing was not enabled, or is not complete.
* 0b1..Key blob processing was enabled and is complete.
*/
#define OTFAD_SR_KBD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_SR_KBD_SHIFT)) & OTFAD_SR_KBD_MASK)
/*! @} */
/*! @name KEY - AES Key Word */
/*! @{ */
#define OTFAD_KEY_KEY_MASK (0xFFFFFFFFU)
#define OTFAD_KEY_KEY_SHIFT (0U)
/*! KEY - AES Key
*/
#define OTFAD_KEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_KEY_KEY_SHIFT)) & OTFAD_KEY_KEY_MASK)
/*! @} */
/* The count of OTFAD_KEY */
#define OTFAD_KEY_COUNT (4U)
/* The count of OTFAD_KEY */
#define OTFAD_KEY_COUNT2 (4U)
/*! @name CTR - AES Counter Word */
/*! @{ */
#define OTFAD_CTR_CTR_MASK (0xFFFFFFFFU)
#define OTFAD_CTR_CTR_SHIFT (0U)
/*! CTR - AES Counter
*/
#define OTFAD_CTR_CTR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_CTR_CTR_SHIFT)) & OTFAD_CTR_CTR_MASK)
/*! @} */
/* The count of OTFAD_CTR */
#define OTFAD_CTR_COUNT (4U)
/* The count of OTFAD_CTR */
#define OTFAD_CTR_COUNT2 (2U)
/*! @name RGD_W0 - AES Region Descriptor Word0 */
/*! @{ */
#define OTFAD_RGD_W0_SRTADDR_MASK (0xFFFFFC00U)
#define OTFAD_RGD_W0_SRTADDR_SHIFT (10U)
/*! SRTADDR - Start Address
*/
#define OTFAD_RGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W0_SRTADDR_SHIFT)) & OTFAD_RGD_W0_SRTADDR_MASK)
/*! @} */
/* The count of OTFAD_RGD_W0 */
#define OTFAD_RGD_W0_COUNT (4U)
/*! @name RGD_W1 - AES Region Descriptor Word1 */
/*! @{ */
#define OTFAD_RGD_W1_VLD_MASK (0x1U)
#define OTFAD_RGD_W1_VLD_SHIFT (0U)
/*! VLD - Valid
* 0b0..Context is invalid.
* 0b1..Context is valid.
*/
#define OTFAD_RGD_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_VLD_SHIFT)) & OTFAD_RGD_W1_VLD_MASK)
#define OTFAD_RGD_W1_ADE_MASK (0x2U)
#define OTFAD_RGD_W1_ADE_SHIFT (1U)
/*! ADE - AES Decryption Enable.
* 0b0..Bypass the fetched data.
* 0b1..Perform the CTR-AES128 mode decryption on the fetched data.
*/
#define OTFAD_RGD_W1_ADE(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ADE_SHIFT)) & OTFAD_RGD_W1_ADE_MASK)
#define OTFAD_RGD_W1_RO_MASK (0x4U)
#define OTFAD_RGD_W1_RO_SHIFT (2U)
/*! RO - Read-Only
* 0b0..The context registers can be accessed normally (as defined by SR[RRAM]).
* 0b1..The context registers are read-only and accesses may be further restricted based on SR[RRAM].
*/
#define OTFAD_RGD_W1_RO(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_RO_SHIFT)) & OTFAD_RGD_W1_RO_MASK)
#define OTFAD_RGD_W1_ENDADDR_MASK (0xFFFFFC00U)
#define OTFAD_RGD_W1_ENDADDR_SHIFT (10U)
/*! ENDADDR - End Address
*/
#define OTFAD_RGD_W1_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << OTFAD_RGD_W1_ENDADDR_SHIFT)) & OTFAD_RGD_W1_ENDADDR_MASK)
/*! @} */
/* The count of OTFAD_RGD_W1 */
#define OTFAD_RGD_W1_COUNT (4U)
/*!
* @}
*/ /* end of group OTFAD_Register_Masks */
/* OTFAD - Peripheral instance base addresses */
/** Peripheral OTFAD1 base address */
#define OTFAD1_BASE (0x400CC000u)
/** Peripheral OTFAD1 base pointer */
#define OTFAD1 ((OTFAD_Type *)OTFAD1_BASE)
/** Peripheral OTFAD2 base address */
#define OTFAD2_BASE (0x400D0000u)
/** Peripheral OTFAD2 base pointer */
#define OTFAD2 ((OTFAD_Type *)OTFAD2_BASE)
/** Array initializer of OTFAD peripheral base addresses */
#define OTFAD_BASE_ADDRS { 0u, OTFAD1_BASE, OTFAD2_BASE }
/** Array initializer of OTFAD peripheral base pointers */
#define OTFAD_BASE_PTRS { (OTFAD_Type *)0u, OTFAD1, OTFAD2 }
/*!
* @}
*/ /* end of group OTFAD_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PDM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PDM_Peripheral_Access_Layer PDM Peripheral Access Layer
* @{
*/
/** PDM - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL_1; /**< PDM Control register 1, offset: 0x0 */
__IO uint32_t CTRL_2; /**< PDM Control register 2, offset: 0x4 */
__IO uint32_t STAT; /**< PDM Status register, offset: 0x8 */
uint8_t RESERVED_0[4];
__IO uint32_t FIFO_CTRL; /**< PDM FIFO Control register, offset: 0x10 */
__IO uint32_t FIFO_STAT; /**< PDM FIFO Status register, offset: 0x14 */
uint8_t RESERVED_1[12];
__I uint32_t DATACH[8]; /**< PDM Output Result Register, array offset: 0x24, array step: 0x4 */
uint8_t RESERVED_2[32];
__IO uint32_t DC_CTRL; /**< PDM DC Remover Control register, offset: 0x64 */
uint8_t RESERVED_3[12];
__IO uint32_t RANGE_CTRL; /**< PDM Range Control register, offset: 0x74 */
uint8_t RESERVED_4[4];
__IO uint32_t RANGE_STAT; /**< PDM Range Status register, offset: 0x7C */
uint8_t RESERVED_5[16];
__IO uint32_t VAD0_CTRL_1; /**< Voice Activity Detector 0 Control register, offset: 0x90 */
__IO uint32_t VAD0_CTRL_2; /**< Voice Activity Detector 0 Control register, offset: 0x94 */
__IO uint32_t VAD0_STAT; /**< Voice Activity Detector 0 Status register, offset: 0x98 */
__IO uint32_t VAD0_SCONFIG; /**< Voice Activity Detector 0 Signal Configuration, offset: 0x9C */
__IO uint32_t VAD0_NCONFIG; /**< Voice Activity Detector 0 Noise Configuration, offset: 0xA0 */
__I uint32_t VAD0_NDATA; /**< Voice Activity Detector 0 Noise Data, offset: 0xA4 */
__IO uint32_t VAD0_ZCD; /**< Voice Activity Detector 0 Zero-Crossing Detector, offset: 0xA8 */
} PDM_Type;
/* ----------------------------------------------------------------------------
-- PDM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PDM_Register_Masks PDM Register Masks
* @{
*/
/*! @name CTRL_1 - PDM Control register 1 */
/*! @{ */
#define PDM_CTRL_1_CH0EN_MASK (0x1U)
#define PDM_CTRL_1_CH0EN_SHIFT (0U)
/*! CH0EN - Channel 0 Enable
*/
#define PDM_CTRL_1_CH0EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH0EN_SHIFT)) & PDM_CTRL_1_CH0EN_MASK)
#define PDM_CTRL_1_CH1EN_MASK (0x2U)
#define PDM_CTRL_1_CH1EN_SHIFT (1U)
/*! CH1EN - Channel 1 Enable
*/
#define PDM_CTRL_1_CH1EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH1EN_SHIFT)) & PDM_CTRL_1_CH1EN_MASK)
#define PDM_CTRL_1_CH2EN_MASK (0x4U)
#define PDM_CTRL_1_CH2EN_SHIFT (2U)
/*! CH2EN - Channel 2 Enable
*/
#define PDM_CTRL_1_CH2EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH2EN_SHIFT)) & PDM_CTRL_1_CH2EN_MASK)
#define PDM_CTRL_1_CH3EN_MASK (0x8U)
#define PDM_CTRL_1_CH3EN_SHIFT (3U)
/*! CH3EN - Channel 3 Enable
*/
#define PDM_CTRL_1_CH3EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH3EN_SHIFT)) & PDM_CTRL_1_CH3EN_MASK)
#define PDM_CTRL_1_CH4EN_MASK (0x10U)
#define PDM_CTRL_1_CH4EN_SHIFT (4U)
/*! CH4EN - Channel 4 Enable
*/
#define PDM_CTRL_1_CH4EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH4EN_SHIFT)) & PDM_CTRL_1_CH4EN_MASK)
#define PDM_CTRL_1_CH5EN_MASK (0x20U)
#define PDM_CTRL_1_CH5EN_SHIFT (5U)
/*! CH5EN - Channel 5 Enable
*/
#define PDM_CTRL_1_CH5EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH5EN_SHIFT)) & PDM_CTRL_1_CH5EN_MASK)
#define PDM_CTRL_1_CH6EN_MASK (0x40U)
#define PDM_CTRL_1_CH6EN_SHIFT (6U)
/*! CH6EN - Channel 6 Enable
*/
#define PDM_CTRL_1_CH6EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH6EN_SHIFT)) & PDM_CTRL_1_CH6EN_MASK)
#define PDM_CTRL_1_CH7EN_MASK (0x80U)
#define PDM_CTRL_1_CH7EN_SHIFT (7U)
/*! CH7EN - Channel 7 Enable
*/
#define PDM_CTRL_1_CH7EN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_CH7EN_SHIFT)) & PDM_CTRL_1_CH7EN_MASK)
#define PDM_CTRL_1_ERREN_MASK (0x800000U)
#define PDM_CTRL_1_ERREN_SHIFT (23U)
/*! ERREN - Error Interruption Enable
* 0b0..Error Interrupts disabled
* 0b1..Error Interrupts enabled
*/
#define PDM_CTRL_1_ERREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_ERREN_SHIFT)) & PDM_CTRL_1_ERREN_MASK)
#define PDM_CTRL_1_DISEL_MASK (0x3000000U)
#define PDM_CTRL_1_DISEL_SHIFT (24U)
/*! DISEL - DMA Interrupt Selection
* 0b00..DMA and interrupt requests disabled
* 0b01..DMA requests enabled
* 0b10..Interrupt requests enabled
* 0b11..Reserved
*/
#define PDM_CTRL_1_DISEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DISEL_SHIFT)) & PDM_CTRL_1_DISEL_MASK)
#define PDM_CTRL_1_DBGE_MASK (0x4000000U)
#define PDM_CTRL_1_DBGE_SHIFT (26U)
/*! DBGE - Module Enable in Debug
* 0b0..Disabled after completing the current frame
* 0b1..Enabled
*/
#define PDM_CTRL_1_DBGE(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBGE_SHIFT)) & PDM_CTRL_1_DBGE_MASK)
#define PDM_CTRL_1_SRES_MASK (0x8000000U)
#define PDM_CTRL_1_SRES_SHIFT (27U)
/*! SRES - Software-reset bit
* 0b0..No action
* 0b1..Software reset
*/
#define PDM_CTRL_1_SRES(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_SRES_SHIFT)) & PDM_CTRL_1_SRES_MASK)
#define PDM_CTRL_1_DBG_MASK (0x10000000U)
#define PDM_CTRL_1_DBG_SHIFT (28U)
/*! DBG - Debug Mode
* 0b0..Normal Mode
* 0b1..Debug Mode
*/
#define PDM_CTRL_1_DBG(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DBG_SHIFT)) & PDM_CTRL_1_DBG_MASK)
#define PDM_CTRL_1_PDMIEN_MASK (0x20000000U)
#define PDM_CTRL_1_PDMIEN_SHIFT (29U)
/*! PDMIEN - PDM Enable
* 0b0..PDM stopped
* 0b1..PDM operation started
*/
#define PDM_CTRL_1_PDMIEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_PDMIEN_SHIFT)) & PDM_CTRL_1_PDMIEN_MASK)
#define PDM_CTRL_1_DOZEN_MASK (0x40000000U)
#define PDM_CTRL_1_DOZEN_SHIFT (30U)
/*! DOZEN - DOZE enable
*/
#define PDM_CTRL_1_DOZEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_DOZEN_SHIFT)) & PDM_CTRL_1_DOZEN_MASK)
#define PDM_CTRL_1_MDIS_MASK (0x80000000U)
#define PDM_CTRL_1_MDIS_SHIFT (31U)
/*! MDIS - Module Disable
* 0b0..Normal Mode
* 0b1..Disable/Low Leakage Mode
*/
#define PDM_CTRL_1_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_1_MDIS_SHIFT)) & PDM_CTRL_1_MDIS_MASK)
/*! @} */
/*! @name CTRL_2 - PDM Control register 2 */
/*! @{ */
#define PDM_CTRL_2_CLKDIV_MASK (0xFFU)
#define PDM_CTRL_2_CLKDIV_SHIFT (0U)
/*! CLKDIV - Clock Divider
*/
#define PDM_CTRL_2_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CLKDIV_SHIFT)) & PDM_CTRL_2_CLKDIV_MASK)
#define PDM_CTRL_2_CICOSR_MASK (0xF0000U)
#define PDM_CTRL_2_CICOSR_SHIFT (16U)
/*! CICOSR - CIC Decimation Rate
*/
#define PDM_CTRL_2_CICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_CICOSR_SHIFT)) & PDM_CTRL_2_CICOSR_MASK)
#define PDM_CTRL_2_QSEL_MASK (0xE000000U)
#define PDM_CTRL_2_QSEL_SHIFT (25U)
/*! QSEL - Quality Mode
* 0b001..High quality mode
* 0b000..Medium quality mode
* 0b111..Low quality mode
* 0b110..Very low quality 0 mode
* 0b101..Very low quality 1 mode
* 0b100..Very low quality 2 mode
*/
#define PDM_CTRL_2_QSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_CTRL_2_QSEL_SHIFT)) & PDM_CTRL_2_QSEL_MASK)
/*! @} */
/*! @name STAT - PDM Status register */
/*! @{ */
#define PDM_STAT_CH0F_MASK (0x1U)
#define PDM_STAT_CH0F_SHIFT (0U)
/*! CH0F - Channel 0 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
*/
#define PDM_STAT_CH0F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH0F_SHIFT)) & PDM_STAT_CH0F_MASK)
#define PDM_STAT_CH1F_MASK (0x2U)
#define PDM_STAT_CH1F_SHIFT (1U)
/*! CH1F - Channel 1 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
*/
#define PDM_STAT_CH1F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH1F_SHIFT)) & PDM_STAT_CH1F_MASK)
#define PDM_STAT_CH2F_MASK (0x4U)
#define PDM_STAT_CH2F_SHIFT (2U)
/*! CH2F - Channel 2 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
*/
#define PDM_STAT_CH2F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH2F_SHIFT)) & PDM_STAT_CH2F_MASK)
#define PDM_STAT_CH3F_MASK (0x8U)
#define PDM_STAT_CH3F_SHIFT (3U)
/*! CH3F - Channel 3 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
*/
#define PDM_STAT_CH3F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH3F_SHIFT)) & PDM_STAT_CH3F_MASK)
#define PDM_STAT_CH4F_MASK (0x10U)
#define PDM_STAT_CH4F_SHIFT (4U)
/*! CH4F - Channel 4 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
*/
#define PDM_STAT_CH4F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH4F_SHIFT)) & PDM_STAT_CH4F_MASK)
#define PDM_STAT_CH5F_MASK (0x20U)
#define PDM_STAT_CH5F_SHIFT (5U)
/*! CH5F - Channel 5 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
*/
#define PDM_STAT_CH5F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH5F_SHIFT)) & PDM_STAT_CH5F_MASK)
#define PDM_STAT_CH6F_MASK (0x40U)
#define PDM_STAT_CH6F_SHIFT (6U)
/*! CH6F - Channel 6 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
*/
#define PDM_STAT_CH6F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH6F_SHIFT)) & PDM_STAT_CH6F_MASK)
#define PDM_STAT_CH7F_MASK (0x80U)
#define PDM_STAT_CH7F_SHIFT (7U)
/*! CH7F - Channel 7 Output Data Flag
* 0b0..Channel's FIFO did not reach the number of elements configured in watermark bit-field
* 0b1..Channel's FIFO reached the number of elements configured in watermark bit-field
*/
#define PDM_STAT_CH7F(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_CH7F_SHIFT)) & PDM_STAT_CH7F_MASK)
#define PDM_STAT_LOWFREQF_MASK (0x20000000U)
#define PDM_STAT_LOWFREQF_SHIFT (29U)
/*! LOWFREQF - Low Frequency Flag
* 0b0..CLKDIV value is OK
* 0b1..CLKDIV value is too low
*/
#define PDM_STAT_LOWFREQF(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_LOWFREQF_SHIFT)) & PDM_STAT_LOWFREQF_MASK)
#define PDM_STAT_FIR_RDY_MASK (0x40000000U)
#define PDM_STAT_FIR_RDY_SHIFT (30U)
/*! FIR_RDY - Filter Data Ready
* 0b0..Filter data is not reliable
* 0b1..Filter data is reliable
*/
#define PDM_STAT_FIR_RDY(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_FIR_RDY_SHIFT)) & PDM_STAT_FIR_RDY_MASK)
#define PDM_STAT_BSY_FIL_MASK (0x80000000U)
#define PDM_STAT_BSY_FIL_SHIFT (31U)
/*! BSY_FIL - Busy Flag
* 0b1..PDM is running
* 0b0..PDM is stopped
*/
#define PDM_STAT_BSY_FIL(x) (((uint32_t)(((uint32_t)(x)) << PDM_STAT_BSY_FIL_SHIFT)) & PDM_STAT_BSY_FIL_MASK)
/*! @} */
/*! @name FIFO_CTRL - PDM FIFO Control register */
/*! @{ */
#define PDM_FIFO_CTRL_FIFOWMK_MASK (0x7U)
#define PDM_FIFO_CTRL_FIFOWMK_SHIFT (0U)
/*! FIFOWMK - FIFO Watermark Control
*/
#define PDM_FIFO_CTRL_FIFOWMK(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_CTRL_FIFOWMK_SHIFT)) & PDM_FIFO_CTRL_FIFOWMK_MASK)
/*! @} */
/*! @name FIFO_STAT - PDM FIFO Status register */
/*! @{ */
#define PDM_FIFO_STAT_FIFOOVF0_MASK (0x1U)
#define PDM_FIFO_STAT_FIFOOVF0_SHIFT (0U)
/*! FIFOOVF0 - FIFO Overflow Exception flag for Channel 0
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF0_SHIFT)) & PDM_FIFO_STAT_FIFOOVF0_MASK)
#define PDM_FIFO_STAT_FIFOOVF1_MASK (0x2U)
#define PDM_FIFO_STAT_FIFOOVF1_SHIFT (1U)
/*! FIFOOVF1 - FIFO Overflow Exception flag for Channel 1
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF1_SHIFT)) & PDM_FIFO_STAT_FIFOOVF1_MASK)
#define PDM_FIFO_STAT_FIFOOVF2_MASK (0x4U)
#define PDM_FIFO_STAT_FIFOOVF2_SHIFT (2U)
/*! FIFOOVF2 - FIFO Overflow Exception flag for Channel 2
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF2_SHIFT)) & PDM_FIFO_STAT_FIFOOVF2_MASK)
#define PDM_FIFO_STAT_FIFOOVF3_MASK (0x8U)
#define PDM_FIFO_STAT_FIFOOVF3_SHIFT (3U)
/*! FIFOOVF3 - FIFO Overflow Exception flag for Channel 3
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF3_SHIFT)) & PDM_FIFO_STAT_FIFOOVF3_MASK)
#define PDM_FIFO_STAT_FIFOOVF4_MASK (0x10U)
#define PDM_FIFO_STAT_FIFOOVF4_SHIFT (4U)
/*! FIFOOVF4 - FIFO Overflow Exception flag for Channel 4
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF4_SHIFT)) & PDM_FIFO_STAT_FIFOOVF4_MASK)
#define PDM_FIFO_STAT_FIFOOVF5_MASK (0x20U)
#define PDM_FIFO_STAT_FIFOOVF5_SHIFT (5U)
/*! FIFOOVF5 - FIFO Overflow Exception flag for Channel 5
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF5_SHIFT)) & PDM_FIFO_STAT_FIFOOVF5_MASK)
#define PDM_FIFO_STAT_FIFOOVF6_MASK (0x40U)
#define PDM_FIFO_STAT_FIFOOVF6_SHIFT (6U)
/*! FIFOOVF6 - FIFO Overflow Exception flag for Channel 6
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF6_SHIFT)) & PDM_FIFO_STAT_FIFOOVF6_MASK)
#define PDM_FIFO_STAT_FIFOOVF7_MASK (0x80U)
#define PDM_FIFO_STAT_FIFOOVF7_SHIFT (7U)
/*! FIFOOVF7 - FIFO Overflow Exception flag for Channel 7
* 0b0..No exception by FIFO overflow
* 0b1..Exception by FIFO overflow
*/
#define PDM_FIFO_STAT_FIFOOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOOVF7_SHIFT)) & PDM_FIFO_STAT_FIFOOVF7_MASK)
#define PDM_FIFO_STAT_FIFOUND0_MASK (0x100U)
#define PDM_FIFO_STAT_FIFOUND0_SHIFT (8U)
/*! FIFOUND0 - FIFO Underflow Exception flag for Channel 0
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND0(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND0_SHIFT)) & PDM_FIFO_STAT_FIFOUND0_MASK)
#define PDM_FIFO_STAT_FIFOUND1_MASK (0x200U)
#define PDM_FIFO_STAT_FIFOUND1_SHIFT (9U)
/*! FIFOUND1 - FIFO Underflow Exception flag for Channel 1
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND1(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND1_SHIFT)) & PDM_FIFO_STAT_FIFOUND1_MASK)
#define PDM_FIFO_STAT_FIFOUND2_MASK (0x400U)
#define PDM_FIFO_STAT_FIFOUND2_SHIFT (10U)
/*! FIFOUND2 - FIFO Underflow Exception flag for Channel 2
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND2(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND2_SHIFT)) & PDM_FIFO_STAT_FIFOUND2_MASK)
#define PDM_FIFO_STAT_FIFOUND3_MASK (0x800U)
#define PDM_FIFO_STAT_FIFOUND3_SHIFT (11U)
/*! FIFOUND3 - FIFO Underflow Exception flag for Channel 3
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND3(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND3_SHIFT)) & PDM_FIFO_STAT_FIFOUND3_MASK)
#define PDM_FIFO_STAT_FIFOUND4_MASK (0x1000U)
#define PDM_FIFO_STAT_FIFOUND4_SHIFT (12U)
/*! FIFOUND4 - FIFO Underflow Exception flag for Channel 4
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND4(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND4_SHIFT)) & PDM_FIFO_STAT_FIFOUND4_MASK)
#define PDM_FIFO_STAT_FIFOUND5_MASK (0x2000U)
#define PDM_FIFO_STAT_FIFOUND5_SHIFT (13U)
/*! FIFOUND5 - FIFO Underflow Exception flag for Channel 5
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND5(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND5_SHIFT)) & PDM_FIFO_STAT_FIFOUND5_MASK)
#define PDM_FIFO_STAT_FIFOUND6_MASK (0x4000U)
#define PDM_FIFO_STAT_FIFOUND6_SHIFT (14U)
/*! FIFOUND6 - FIFO Underflow Exception flag for Channel 6
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND6(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND6_SHIFT)) & PDM_FIFO_STAT_FIFOUND6_MASK)
#define PDM_FIFO_STAT_FIFOUND7_MASK (0x8000U)
#define PDM_FIFO_STAT_FIFOUND7_SHIFT (15U)
/*! FIFOUND7 - FIFO Underflow Exception flag for Channel 7
* 0b0..No exception by FIFO Underflow
* 0b1..Exception by FIFO underflow
*/
#define PDM_FIFO_STAT_FIFOUND7(x) (((uint32_t)(((uint32_t)(x)) << PDM_FIFO_STAT_FIFOUND7_SHIFT)) & PDM_FIFO_STAT_FIFOUND7_MASK)
/*! @} */
/*! @name DATACH - PDM Output Result Register */
/*! @{ */
#define PDM_DATACH_DATA_MASK (0xFFFFFFFFU)
#define PDM_DATACH_DATA_SHIFT (0U)
/*! DATA - Channel n Data
*/
#define PDM_DATACH_DATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_DATACH_DATA_SHIFT)) & PDM_DATACH_DATA_MASK)
/*! @} */
/* The count of PDM_DATACH */
#define PDM_DATACH_COUNT (8U)
/*! @name DC_CTRL - PDM DC Remover Control register */
/*! @{ */
#define PDM_DC_CTRL_DCCONFIG0_MASK (0x3U)
#define PDM_DC_CTRL_DCCONFIG0_SHIFT (0U)
/*! DCCONFIG0 - Channel 0 DC Remover Configuration
* 0b11..DC Remover is bypassed
* 0b00..DC Remover cut-off at 21Hz
* 0b01..DC Remover cut-off at 83Hz
* 0b10..DC Remover cut-off at 152Hz
*/
#define PDM_DC_CTRL_DCCONFIG0(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG0_SHIFT)) & PDM_DC_CTRL_DCCONFIG0_MASK)
#define PDM_DC_CTRL_DCCONFIG1_MASK (0xCU)
#define PDM_DC_CTRL_DCCONFIG1_SHIFT (2U)
/*! DCCONFIG1 - Channel 1 DC Remover Configuration
* 0b11..DC Remover is bypassed
* 0b00..DC Remover cut-off at 21Hz
* 0b01..DC Remover cut-off at 83Hz
* 0b10..DC Remover cut-off at 152Hz
*/
#define PDM_DC_CTRL_DCCONFIG1(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG1_SHIFT)) & PDM_DC_CTRL_DCCONFIG1_MASK)
#define PDM_DC_CTRL_DCCONFIG2_MASK (0x30U)
#define PDM_DC_CTRL_DCCONFIG2_SHIFT (4U)
/*! DCCONFIG2 - Channel 2 DC Remover Configuration
* 0b11..DC Remover is bypassed
* 0b00..DC Remover cut-off at 21Hz
* 0b01..DC Remover cut-off at 83Hz
* 0b10..DC Remover cut-off at 152Hz
*/
#define PDM_DC_CTRL_DCCONFIG2(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG2_SHIFT)) & PDM_DC_CTRL_DCCONFIG2_MASK)
#define PDM_DC_CTRL_DCCONFIG3_MASK (0xC0U)
#define PDM_DC_CTRL_DCCONFIG3_SHIFT (6U)
/*! DCCONFIG3 - Channel 3 DC Remover Configuration
* 0b11..DC Remover is bypassed
* 0b00..DC Remover cut-off at 21Hz
* 0b01..DC Remover cut-off at 83Hz
* 0b10..DC Remover cut-off at 152Hz
*/
#define PDM_DC_CTRL_DCCONFIG3(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG3_SHIFT)) & PDM_DC_CTRL_DCCONFIG3_MASK)
#define PDM_DC_CTRL_DCCONFIG4_MASK (0x300U)
#define PDM_DC_CTRL_DCCONFIG4_SHIFT (8U)
/*! DCCONFIG4 - Channel 4 DC Remover Configuration
* 0b11..DC Remover is bypassed
* 0b00..DC Remover cut-off at 21Hz
* 0b01..DC Remover cut-off at 83Hz
* 0b10..DC Remover cut-off at 152Hz
*/
#define PDM_DC_CTRL_DCCONFIG4(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG4_SHIFT)) & PDM_DC_CTRL_DCCONFIG4_MASK)
#define PDM_DC_CTRL_DCCONFIG5_MASK (0xC00U)
#define PDM_DC_CTRL_DCCONFIG5_SHIFT (10U)
/*! DCCONFIG5 - Channel 5 DC Remover Configuration
* 0b11..DC Remover is bypassed
* 0b00..DC Remover cut-off at 21Hz
* 0b01..DC Remover cut-off at 83Hz
* 0b10..DC Remover cut-off at 152Hz
*/
#define PDM_DC_CTRL_DCCONFIG5(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG5_SHIFT)) & PDM_DC_CTRL_DCCONFIG5_MASK)
#define PDM_DC_CTRL_DCCONFIG6_MASK (0x3000U)
#define PDM_DC_CTRL_DCCONFIG6_SHIFT (12U)
/*! DCCONFIG6 - Channel 6 DC Remover Configuration
* 0b11..DC Remover is bypassed
* 0b00..DC Remover cut-off at 21Hz
* 0b01..DC Remover cut-off at 83Hz
* 0b10..DC Remover cut-off at 152Hz
*/
#define PDM_DC_CTRL_DCCONFIG6(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG6_SHIFT)) & PDM_DC_CTRL_DCCONFIG6_MASK)
#define PDM_DC_CTRL_DCCONFIG7_MASK (0xC000U)
#define PDM_DC_CTRL_DCCONFIG7_SHIFT (14U)
/*! DCCONFIG7 - Channel 7 DC Remover Configuration
* 0b11..DC Remover is bypassed
* 0b00..DC Remover cut-off at 21Hz
* 0b01..DC Remover cut-off at 83Hz
* 0b10..DC Remover cut-off at 152Hz
*/
#define PDM_DC_CTRL_DCCONFIG7(x) (((uint32_t)(((uint32_t)(x)) << PDM_DC_CTRL_DCCONFIG7_SHIFT)) & PDM_DC_CTRL_DCCONFIG7_MASK)
/*! @} */
/*! @name RANGE_CTRL - PDM Range Control register */
/*! @{ */
#define PDM_RANGE_CTRL_RANGEADJ0_MASK (0xFU)
#define PDM_RANGE_CTRL_RANGEADJ0_SHIFT (0U)
/*! RANGEADJ0 - Channel 0 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ0_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ0_MASK)
#define PDM_RANGE_CTRL_RANGEADJ1_MASK (0xF0U)
#define PDM_RANGE_CTRL_RANGEADJ1_SHIFT (4U)
/*! RANGEADJ1 - Channel 1 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ1_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ1_MASK)
#define PDM_RANGE_CTRL_RANGEADJ2_MASK (0xF00U)
#define PDM_RANGE_CTRL_RANGEADJ2_SHIFT (8U)
/*! RANGEADJ2 - Channel 2 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ2_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ2_MASK)
#define PDM_RANGE_CTRL_RANGEADJ3_MASK (0xF000U)
#define PDM_RANGE_CTRL_RANGEADJ3_SHIFT (12U)
/*! RANGEADJ3 - Channel 3 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ3_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ3_MASK)
#define PDM_RANGE_CTRL_RANGEADJ4_MASK (0xF0000U)
#define PDM_RANGE_CTRL_RANGEADJ4_SHIFT (16U)
/*! RANGEADJ4 - Channel 4 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ4_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ4_MASK)
#define PDM_RANGE_CTRL_RANGEADJ5_MASK (0xF00000U)
#define PDM_RANGE_CTRL_RANGEADJ5_SHIFT (20U)
/*! RANGEADJ5 - Channel 5 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ5_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ5_MASK)
#define PDM_RANGE_CTRL_RANGEADJ6_MASK (0xF000000U)
#define PDM_RANGE_CTRL_RANGEADJ6_SHIFT (24U)
/*! RANGEADJ6 - Channel 6 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ6_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ6_MASK)
#define PDM_RANGE_CTRL_RANGEADJ7_MASK (0xF0000000U)
#define PDM_RANGE_CTRL_RANGEADJ7_SHIFT (28U)
/*! RANGEADJ7 - Channel 7 Range Adjustment
*/
#define PDM_RANGE_CTRL_RANGEADJ7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_CTRL_RANGEADJ7_SHIFT)) & PDM_RANGE_CTRL_RANGEADJ7_MASK)
/*! @} */
/*! @name RANGE_STAT - PDM Range Status register */
/*! @{ */
#define PDM_RANGE_STAT_RANGEOVF0_MASK (0x1U)
#define PDM_RANGE_STAT_RANGEOVF0_SHIFT (0U)
/*! RANGEOVF0 - Channel 0 Range Overflow Error Flag
* 0b0..No exception by range overflow
* 0b1..Exception by range overflow
*/
#define PDM_RANGE_STAT_RANGEOVF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF0_SHIFT)) & PDM_RANGE_STAT_RANGEOVF0_MASK)
#define PDM_RANGE_STAT_RANGEOVF1_MASK (0x2U)
#define PDM_RANGE_STAT_RANGEOVF1_SHIFT (1U)
/*! RANGEOVF1 - Channel 1 Range Overflow Error Flag
* 0b0..No exception by range overflow
* 0b1..Exception by range overflow
*/
#define PDM_RANGE_STAT_RANGEOVF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF1_SHIFT)) & PDM_RANGE_STAT_RANGEOVF1_MASK)
#define PDM_RANGE_STAT_RANGEOVF2_MASK (0x4U)
#define PDM_RANGE_STAT_RANGEOVF2_SHIFT (2U)
/*! RANGEOVF2 - Channel 2 Range Overflow Error Flag
* 0b0..No exception by range overflow
* 0b1..Exception by range overflow
*/
#define PDM_RANGE_STAT_RANGEOVF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF2_SHIFT)) & PDM_RANGE_STAT_RANGEOVF2_MASK)
#define PDM_RANGE_STAT_RANGEOVF3_MASK (0x8U)
#define PDM_RANGE_STAT_RANGEOVF3_SHIFT (3U)
/*! RANGEOVF3 - Channel 3 Range Overflow Error Flag
* 0b0..No exception by range overflow
* 0b1..Exception by range overflow
*/
#define PDM_RANGE_STAT_RANGEOVF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF3_SHIFT)) & PDM_RANGE_STAT_RANGEOVF3_MASK)
#define PDM_RANGE_STAT_RANGEOVF4_MASK (0x10U)
#define PDM_RANGE_STAT_RANGEOVF4_SHIFT (4U)
/*! RANGEOVF4 - Channel 4 Range Overflow Error Flag
* 0b0..No exception by range overflow
* 0b1..Exception by range overflow
*/
#define PDM_RANGE_STAT_RANGEOVF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF4_SHIFT)) & PDM_RANGE_STAT_RANGEOVF4_MASK)
#define PDM_RANGE_STAT_RANGEOVF5_MASK (0x20U)
#define PDM_RANGE_STAT_RANGEOVF5_SHIFT (5U)
/*! RANGEOVF5 - Channel 5 Range Overflow Error Flag
* 0b0..No exception by range overflow
* 0b1..Exception by range overflow
*/
#define PDM_RANGE_STAT_RANGEOVF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF5_SHIFT)) & PDM_RANGE_STAT_RANGEOVF5_MASK)
#define PDM_RANGE_STAT_RANGEOVF6_MASK (0x40U)
#define PDM_RANGE_STAT_RANGEOVF6_SHIFT (6U)
/*! RANGEOVF6 - Channel 6 Range Overflow Error Flag
* 0b0..No exception by range overflow
* 0b1..Exception by range overflow
*/
#define PDM_RANGE_STAT_RANGEOVF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF6_SHIFT)) & PDM_RANGE_STAT_RANGEOVF6_MASK)
#define PDM_RANGE_STAT_RANGEOVF7_MASK (0x80U)
#define PDM_RANGE_STAT_RANGEOVF7_SHIFT (7U)
/*! RANGEOVF7 - Channel 7 Range Overflow Error Flag
* 0b0..No exception by range overflow
* 0b1..Exception by range overflow
*/
#define PDM_RANGE_STAT_RANGEOVF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEOVF7_SHIFT)) & PDM_RANGE_STAT_RANGEOVF7_MASK)
#define PDM_RANGE_STAT_RANGEUNF0_MASK (0x10000U)
#define PDM_RANGE_STAT_RANGEUNF0_SHIFT (16U)
/*! RANGEUNF0 - Channel 0 Range Underflow Error Flag
* 0b0..No exception by range underflow
* 0b1..Exception by range underflow
*/
#define PDM_RANGE_STAT_RANGEUNF0(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF0_SHIFT)) & PDM_RANGE_STAT_RANGEUNF0_MASK)
#define PDM_RANGE_STAT_RANGEUNF1_MASK (0x20000U)
#define PDM_RANGE_STAT_RANGEUNF1_SHIFT (17U)
/*! RANGEUNF1 - Channel 1 Range Underflow Error Flag
* 0b0..No exception by range underflow
* 0b1..Exception by range underflow
*/
#define PDM_RANGE_STAT_RANGEUNF1(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF1_SHIFT)) & PDM_RANGE_STAT_RANGEUNF1_MASK)
#define PDM_RANGE_STAT_RANGEUNF2_MASK (0x40000U)
#define PDM_RANGE_STAT_RANGEUNF2_SHIFT (18U)
/*! RANGEUNF2 - Channel 2 Range Underflow Error Flag
* 0b0..No exception by range underflow
* 0b1..Exception by range underflow
*/
#define PDM_RANGE_STAT_RANGEUNF2(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF2_SHIFT)) & PDM_RANGE_STAT_RANGEUNF2_MASK)
#define PDM_RANGE_STAT_RANGEUNF3_MASK (0x80000U)
#define PDM_RANGE_STAT_RANGEUNF3_SHIFT (19U)
/*! RANGEUNF3 - Channel 3 Range Underflow Error Flag
* 0b0..No exception by range underflow
* 0b1..Exception by range underflow
*/
#define PDM_RANGE_STAT_RANGEUNF3(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF3_SHIFT)) & PDM_RANGE_STAT_RANGEUNF3_MASK)
#define PDM_RANGE_STAT_RANGEUNF4_MASK (0x100000U)
#define PDM_RANGE_STAT_RANGEUNF4_SHIFT (20U)
/*! RANGEUNF4 - Channel 4 Range Underflow Error Flag
* 0b0..No exception by range underflow
* 0b1..Exception by range underflow
*/
#define PDM_RANGE_STAT_RANGEUNF4(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF4_SHIFT)) & PDM_RANGE_STAT_RANGEUNF4_MASK)
#define PDM_RANGE_STAT_RANGEUNF5_MASK (0x200000U)
#define PDM_RANGE_STAT_RANGEUNF5_SHIFT (21U)
/*! RANGEUNF5 - Channel 5 Range Underflow Error Flag
* 0b0..No exception by range underflow
* 0b1..Exception by range underflow
*/
#define PDM_RANGE_STAT_RANGEUNF5(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF5_SHIFT)) & PDM_RANGE_STAT_RANGEUNF5_MASK)
#define PDM_RANGE_STAT_RANGEUNF6_MASK (0x400000U)
#define PDM_RANGE_STAT_RANGEUNF6_SHIFT (22U)
/*! RANGEUNF6 - Channel 6 Range Underflow Error Flag
* 0b0..No exception by range underflow
* 0b1..Exception by range underflow
*/
#define PDM_RANGE_STAT_RANGEUNF6(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF6_SHIFT)) & PDM_RANGE_STAT_RANGEUNF6_MASK)
#define PDM_RANGE_STAT_RANGEUNF7_MASK (0x800000U)
#define PDM_RANGE_STAT_RANGEUNF7_SHIFT (23U)
/*! RANGEUNF7 - Channel 7 Range Underflow Error Flag
* 0b0..No exception by range underflow
* 0b1..Exception by range underflow
*/
#define PDM_RANGE_STAT_RANGEUNF7(x) (((uint32_t)(((uint32_t)(x)) << PDM_RANGE_STAT_RANGEUNF7_SHIFT)) & PDM_RANGE_STAT_RANGEUNF7_MASK)
/*! @} */
/*! @name VAD0_CTRL_1 - Voice Activity Detector 0 Control register */
/*! @{ */
#define PDM_VAD0_CTRL_1_VADEN_MASK (0x1U)
#define PDM_VAD0_CTRL_1_VADEN_SHIFT (0U)
/*! VADEN - Voice Activity Detector Enable
* 0b0..The HWVAD is disabled
* 0b1..The HWVAD is enabled
*/
#define PDM_VAD0_CTRL_1_VADEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADEN_SHIFT)) & PDM_VAD0_CTRL_1_VADEN_MASK)
#define PDM_VAD0_CTRL_1_VADRST_MASK (0x2U)
#define PDM_VAD0_CTRL_1_VADRST_SHIFT (1U)
/*! VADRST - Voice Activity Detector Reset
*/
#define PDM_VAD0_CTRL_1_VADRST(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADRST_SHIFT)) & PDM_VAD0_CTRL_1_VADRST_MASK)
#define PDM_VAD0_CTRL_1_VADIE_MASK (0x4U)
#define PDM_VAD0_CTRL_1_VADIE_SHIFT (2U)
/*! VADIE - Voice Activity Detector Interruption Enable
* 0b0..HWVAD Interrupts disabled
* 0b1..HWVAD Interrupts enabled
*/
#define PDM_VAD0_CTRL_1_VADIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADIE_SHIFT)) & PDM_VAD0_CTRL_1_VADIE_MASK)
#define PDM_VAD0_CTRL_1_VADERIE_MASK (0x8U)
#define PDM_VAD0_CTRL_1_VADERIE_SHIFT (3U)
/*! VADERIE - Voice Activity Detector Error Interruption Enable
* 0b0..HWVAD Error Interrupts disabled
* 0b1..HWVAD Error Interrupts enabled
*/
#define PDM_VAD0_CTRL_1_VADERIE(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADERIE_SHIFT)) & PDM_VAD0_CTRL_1_VADERIE_MASK)
#define PDM_VAD0_CTRL_1_VADST10_MASK (0x10U)
#define PDM_VAD0_CTRL_1_VADST10_SHIFT (4U)
/*! VADST10 - Voice Activity Detector Internal Filters Initialization
* 0b0..Normal operation.
* 0b1..Filters are initialized.
*/
#define PDM_VAD0_CTRL_1_VADST10(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADST10_SHIFT)) & PDM_VAD0_CTRL_1_VADST10_MASK)
#define PDM_VAD0_CTRL_1_VADINITT_MASK (0x1F00U)
#define PDM_VAD0_CTRL_1_VADINITT_SHIFT (8U)
/*! VADINITT - Voice Activity Detector Initialization Time
*/
#define PDM_VAD0_CTRL_1_VADINITT(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADINITT_SHIFT)) & PDM_VAD0_CTRL_1_VADINITT_MASK)
#define PDM_VAD0_CTRL_1_VADCICOSR_MASK (0xF0000U)
#define PDM_VAD0_CTRL_1_VADCICOSR_SHIFT (16U)
/*! VADCICOSR - Voice Activity Detector CIC Oversampling Rate
*/
#define PDM_VAD0_CTRL_1_VADCICOSR(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCICOSR_SHIFT)) & PDM_VAD0_CTRL_1_VADCICOSR_MASK)
#define PDM_VAD0_CTRL_1_VADCHSEL_MASK (0x7000000U)
#define PDM_VAD0_CTRL_1_VADCHSEL_SHIFT (24U)
/*! VADCHSEL - Voice Activity Detector Channel Selector
*/
#define PDM_VAD0_CTRL_1_VADCHSEL(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_1_VADCHSEL_SHIFT)) & PDM_VAD0_CTRL_1_VADCHSEL_MASK)
/*! @} */
/*! @name VAD0_CTRL_2 - Voice Activity Detector 0 Control register */
/*! @{ */
#define PDM_VAD0_CTRL_2_VADHPF_MASK (0x3U)
#define PDM_VAD0_CTRL_2_VADHPF_SHIFT (0U)
/*! VADHPF - Voice Activity Detector High-Pass Filter
* 0b00..Filter bypassed.
* 0b01..Cut-off frequency at 1750Hz.
* 0b10..Cut-off frequency at 215Hz.
* 0b11..Cut-off frequency at 102Hz.
*/
#define PDM_VAD0_CTRL_2_VADHPF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADHPF_SHIFT)) & PDM_VAD0_CTRL_2_VADHPF_MASK)
#define PDM_VAD0_CTRL_2_VADINPGAIN_MASK (0xF00U)
#define PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT (8U)
/*! VADINPGAIN - Voice Activity Detector Input Gain
*/
#define PDM_VAD0_CTRL_2_VADINPGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADINPGAIN_SHIFT)) & PDM_VAD0_CTRL_2_VADINPGAIN_MASK)
#define PDM_VAD0_CTRL_2_VADFRAMET_MASK (0x3F0000U)
#define PDM_VAD0_CTRL_2_VADFRAMET_SHIFT (16U)
/*! VADFRAMET - Voice Activity Detector Frame Time
*/
#define PDM_VAD0_CTRL_2_VADFRAMET(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRAMET_SHIFT)) & PDM_VAD0_CTRL_2_VADFRAMET_MASK)
#define PDM_VAD0_CTRL_2_VADFOUTDIS_MASK (0x10000000U)
#define PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT (28U)
/*! VADFOUTDIS - Voice Activity Detector Force Output Disable
* 0b0..Output is enabled.
* 0b1..Output is disabled.
*/
#define PDM_VAD0_CTRL_2_VADFOUTDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFOUTDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFOUTDIS_MASK)
#define PDM_VAD0_CTRL_2_VADPREFEN_MASK (0x40000000U)
#define PDM_VAD0_CTRL_2_VADPREFEN_SHIFT (30U)
/*! VADPREFEN - Voice Activity Detector Pre Filter Enable
* 0b0..Pre-filter is bypassed.
* 0b1..Pre-filter is enabled.
*/
#define PDM_VAD0_CTRL_2_VADPREFEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADPREFEN_SHIFT)) & PDM_VAD0_CTRL_2_VADPREFEN_MASK)
#define PDM_VAD0_CTRL_2_VADFRENDIS_MASK (0x80000000U)
#define PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT (31U)
/*! VADFRENDIS - Voice Activity Detector Frame Energy Disable
* 0b1..Frame energy calculus disabled.
* 0b0..Frame energy calculus enabled.
*/
#define PDM_VAD0_CTRL_2_VADFRENDIS(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_CTRL_2_VADFRENDIS_SHIFT)) & PDM_VAD0_CTRL_2_VADFRENDIS_MASK)
/*! @} */
/*! @name VAD0_STAT - Voice Activity Detector 0 Status register */
/*! @{ */
#define PDM_VAD0_STAT_VADIF_MASK (0x1U)
#define PDM_VAD0_STAT_VADIF_SHIFT (0U)
/*! VADIF - Voice Activity Detector Interrupt Flag
* 0b0..Voice activity not detected
* 0b1..Voice activity detected
*/
#define PDM_VAD0_STAT_VADIF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADIF_SHIFT)) & PDM_VAD0_STAT_VADIF_MASK)
#define PDM_VAD0_STAT_VADEF_MASK (0x8000U)
#define PDM_VAD0_STAT_VADEF_SHIFT (15U)
/*! VADEF - Voice Activity Detector Event Flag
* 0b0..Voice activity not detected
* 0b1..Voice activity detected
*/
#define PDM_VAD0_STAT_VADEF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADEF_SHIFT)) & PDM_VAD0_STAT_VADEF_MASK)
#define PDM_VAD0_STAT_VADINSATF_MASK (0x10000U)
#define PDM_VAD0_STAT_VADINSATF_SHIFT (16U)
/*! VADINSATF - Voice Activity Detector Input Saturation Flag
* 0b0..No exception
* 0b1..Exception
*/
#define PDM_VAD0_STAT_VADINSATF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINSATF_SHIFT)) & PDM_VAD0_STAT_VADINSATF_MASK)
#define PDM_VAD0_STAT_VADINITF_MASK (0x80000000U)
#define PDM_VAD0_STAT_VADINITF_SHIFT (31U)
/*! VADINITF - Voice Activity Detector Initialization Flag
* 0b0..HWVAD is not being initialized.
* 0b1..HWVAD is being initialized.
*/
#define PDM_VAD0_STAT_VADINITF(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_STAT_VADINITF_SHIFT)) & PDM_VAD0_STAT_VADINITF_MASK)
/*! @} */
/*! @name VAD0_SCONFIG - Voice Activity Detector 0 Signal Configuration */
/*! @{ */
#define PDM_VAD0_SCONFIG_VADSGAIN_MASK (0xFU)
#define PDM_VAD0_SCONFIG_VADSGAIN_SHIFT (0U)
/*! VADSGAIN - Voice Activity Detector Signal Gain
*/
#define PDM_VAD0_SCONFIG_VADSGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSGAIN_SHIFT)) & PDM_VAD0_SCONFIG_VADSGAIN_MASK)
#define PDM_VAD0_SCONFIG_VADSMAXEN_MASK (0x40000000U)
#define PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT (30U)
/*! VADSMAXEN - Voice Activity Detector Signal Maximum Enable
* 0b0..Maximum block is bypassed.
* 0b1..Maximum block is enabled.
*/
#define PDM_VAD0_SCONFIG_VADSMAXEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSMAXEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSMAXEN_MASK)
#define PDM_VAD0_SCONFIG_VADSFILEN_MASK (0x80000000U)
#define PDM_VAD0_SCONFIG_VADSFILEN_SHIFT (31U)
/*! VADSFILEN - Voice Activity Detector Signal Filter Enable
* 0b0..Signal filter is disabled.
* 0b1..Signal filter is enabled.
*/
#define PDM_VAD0_SCONFIG_VADSFILEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_SCONFIG_VADSFILEN_SHIFT)) & PDM_VAD0_SCONFIG_VADSFILEN_MASK)
/*! @} */
/*! @name VAD0_NCONFIG - Voice Activity Detector 0 Noise Configuration */
/*! @{ */
#define PDM_VAD0_NCONFIG_VADNGAIN_MASK (0xFU)
#define PDM_VAD0_NCONFIG_VADNGAIN_SHIFT (0U)
/*! VADNGAIN - Voice Activity Detector Noise Gain
*/
#define PDM_VAD0_NCONFIG_VADNGAIN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNGAIN_SHIFT)) & PDM_VAD0_NCONFIG_VADNGAIN_MASK)
#define PDM_VAD0_NCONFIG_VADNFILADJ_MASK (0x1F00U)
#define PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT (8U)
/*! VADNFILADJ - Voice Activity Detector Noise Filter Adjustment
*/
#define PDM_VAD0_NCONFIG_VADNFILADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILADJ_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILADJ_MASK)
#define PDM_VAD0_NCONFIG_VADNOREN_MASK (0x10000000U)
#define PDM_VAD0_NCONFIG_VADNOREN_SHIFT (28U)
/*! VADNOREN - Voice Activity Detector Noise OR Enable
* 0b0..Noise input is not decimated.
* 0b1..Noise input is decimated.
*/
#define PDM_VAD0_NCONFIG_VADNOREN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNOREN_SHIFT)) & PDM_VAD0_NCONFIG_VADNOREN_MASK)
#define PDM_VAD0_NCONFIG_VADNDECEN_MASK (0x20000000U)
#define PDM_VAD0_NCONFIG_VADNDECEN_SHIFT (29U)
/*! VADNDECEN - Voice Activity Detector Noise Decimation Enable
* 0b0..Noise input is not decimated.
* 0b1..Noise input is decimated.
*/
#define PDM_VAD0_NCONFIG_VADNDECEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNDECEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNDECEN_MASK)
#define PDM_VAD0_NCONFIG_VADNMINEN_MASK (0x40000000U)
#define PDM_VAD0_NCONFIG_VADNMINEN_SHIFT (30U)
/*! VADNMINEN - Voice Activity Detector Noise Minimum Enable
* 0b0..Minimum block is bypassed.
* 0b1..Minimum block is enabled.
*/
#define PDM_VAD0_NCONFIG_VADNMINEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNMINEN_SHIFT)) & PDM_VAD0_NCONFIG_VADNMINEN_MASK)
#define PDM_VAD0_NCONFIG_VADNFILAUTO_MASK (0x80000000U)
#define PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT (31U)
/*! VADNFILAUTO - Voice Activity Detector Noise Filter Auto
* 0b0..Noise filter is always enabled.
* 0b1..Noise filter is enabled/disabled based on voice activity information.
*/
#define PDM_VAD0_NCONFIG_VADNFILAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NCONFIG_VADNFILAUTO_SHIFT)) & PDM_VAD0_NCONFIG_VADNFILAUTO_MASK)
/*! @} */
/*! @name VAD0_NDATA - Voice Activity Detector 0 Noise Data */
/*! @{ */
#define PDM_VAD0_NDATA_VADNDATA_MASK (0xFFFFU)
#define PDM_VAD0_NDATA_VADNDATA_SHIFT (0U)
/*! VADNDATA - Voice Activity Detector Noise Data
*/
#define PDM_VAD0_NDATA_VADNDATA(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_NDATA_VADNDATA_SHIFT)) & PDM_VAD0_NDATA_VADNDATA_MASK)
/*! @} */
/*! @name VAD0_ZCD - Voice Activity Detector 0 Zero-Crossing Detector */
/*! @{ */
#define PDM_VAD0_ZCD_VADZCDEN_MASK (0x1U)
#define PDM_VAD0_ZCD_VADZCDEN_SHIFT (0U)
/*! VADZCDEN - Zero-Crossing Detector Enable
* 0b0..The ZCD is disabled
* 0b1..The ZCD is enabled
*/
#define PDM_VAD0_ZCD_VADZCDEN(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDEN_SHIFT)) & PDM_VAD0_ZCD_VADZCDEN_MASK)
#define PDM_VAD0_ZCD_VADZCDAUTO_MASK (0x4U)
#define PDM_VAD0_ZCD_VADZCDAUTO_SHIFT (2U)
/*! VADZCDAUTO - Zero-Crossing Detector Automatic Threshold
* 0b0..The ZCD threshold is not estimated automatically
* 0b1..The ZCD threshold is estimated automatically
*/
#define PDM_VAD0_ZCD_VADZCDAUTO(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAUTO_SHIFT)) & PDM_VAD0_ZCD_VADZCDAUTO_MASK)
#define PDM_VAD0_ZCD_VADZCDAND_MASK (0x10U)
#define PDM_VAD0_ZCD_VADZCDAND_SHIFT (4U)
/*! VADZCDAND - Zero-Crossing Detector AND Behavior
* 0b0..The ZCD result is OR'ed with the energy-based detection.
* 0b1..The ZCD result is AND'ed with the energy-based detection.
*/
#define PDM_VAD0_ZCD_VADZCDAND(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDAND_SHIFT)) & PDM_VAD0_ZCD_VADZCDAND_MASK)
#define PDM_VAD0_ZCD_VADZCDADJ_MASK (0xF00U)
#define PDM_VAD0_ZCD_VADZCDADJ_SHIFT (8U)
/*! VADZCDADJ - Zero-Crossing Detector Adjustment
*/
#define PDM_VAD0_ZCD_VADZCDADJ(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDADJ_SHIFT)) & PDM_VAD0_ZCD_VADZCDADJ_MASK)
#define PDM_VAD0_ZCD_VADZCDTH_MASK (0x3FF0000U)
#define PDM_VAD0_ZCD_VADZCDTH_SHIFT (16U)
/*! VADZCDTH - Zero-Crossing Detector Threshold
*/
#define PDM_VAD0_ZCD_VADZCDTH(x) (((uint32_t)(((uint32_t)(x)) << PDM_VAD0_ZCD_VADZCDTH_SHIFT)) & PDM_VAD0_ZCD_VADZCDTH_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PDM_Register_Masks */
/* PDM - Peripheral instance base addresses */
/** Peripheral PDM base address */
#define PDM_BASE (0x40C20000u)
/** Peripheral PDM base pointer */
#define PDM ((PDM_Type *)PDM_BASE)
/** Array initializer of PDM peripheral base addresses */
#define PDM_BASE_ADDRS { PDM_BASE }
/** Array initializer of PDM peripheral base pointers */
#define PDM_BASE_PTRS { PDM }
/*!
* @}
*/ /* end of group PDM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PGMC_BPC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PGMC_BPC_Peripheral_Access_Layer PGMC_BPC Peripheral Access Layer
* @{
*/
/** PGMC_BPC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t BPC_AUTHEN_CTRL; /**< BPC Authentication Control, offset: 0x4 */
uint8_t RESERVED_1[8];
__IO uint32_t BPC_MODE; /**< BPC Mode, offset: 0x10 */
__IO uint32_t BPC_POWER_CTRL; /**< BPC power control, offset: 0x14 */
uint8_t RESERVED_2[20];
__IO uint32_t BPC_FLAG; /**< BPC flag, offset: 0x2C */
uint8_t RESERVED_3[16];
__IO uint32_t BPC_SSAR_SAVE_CTRL; /**< BPC SSAR save control, offset: 0x40 */
__IO uint32_t BPC_SSAR_RESTORE_CTRL; /**< BPC SSAR restore control, offset: 0x44 */
} PGMC_BPC_Type;
/* ----------------------------------------------------------------------------
-- PGMC_BPC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PGMC_BPC_Register_Masks PGMC_BPC Register Masks
* @{
*/
/*! @name BPC_AUTHEN_CTRL - BPC Authentication Control */
/*! @{ */
#define PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK (0x1U)
#define PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT (0U)
/*! USER - Allow user mode access
* 0b0..Allow only privilege mode to access basic power control registers
* 0b1..Allow both privilege and user mode to access basic power control registers
*/
#define PGMC_BPC_BPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK)
#define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
#define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
/*! NONSECURE - Allow non-secure mode access
* 0b0..Allow only secure mode to access basic power control registers
* 0b1..Allow both secure and non-secure mode to access basic power control registers
*/
#define PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK)
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
#define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
#define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Domain ID white list
*/
#define PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK)
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - White list lock
*/
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK)
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
/*! LOCK_CFG - Configuration lock
*/
#define PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK)
/*! @} */
/*! @name BPC_MODE - BPC Mode */
/*! @{ */
#define PGMC_BPC_BPC_MODE_CTRL_MODE_MASK (0x3U)
#define PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT (0U)
/*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
* 0b00..Not affected by any low power mode
* 0b01..Controlled by CPU power mode of the domain
* 0b10..Controlled by Setpoint
* 0b11..Reserved
*/
#define PGMC_BPC_BPC_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_CTRL_MODE_SHIFT)) & PGMC_BPC_BPC_MODE_CTRL_MODE_MASK)
#define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK (0x30U)
#define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT (4U)
/*! DOMAIN_ASSIGN - Domain assignment of the BPC
* 0b00..Domain 0
* 0b01..Domain 1
* 0b10..Domain 2
* 0b11..Domain 3
*/
#define PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_BPC_BPC_MODE_DOMAIN_ASSIGN_MASK)
/*! @} */
/*! @name BPC_POWER_CTRL - BPC power control */
/*! @{ */
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)
/*! PWR_OFF_AT_WAIT - 0x1: Power off when domain enters WAIT mode
*/
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)
/*! PWR_OFF_AT_STOP - 0x1: Power off when domain enters STOP mode
*/
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_STOP_MASK)
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)
/*! PWR_OFF_AT_SUSPEND - 0x1: Power off when domain enters SUSPEND mode
*/
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)
#define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)
#define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)
/*! ISO_ON_SOFT - Software isolation on trigger
*/
#define PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_ON_SOFT_MASK)
#define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)
#define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)
/*! PSW_OFF_SOFT - Software power off trigger
*/
#define PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_OFF_SOFT_MASK)
#define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)
#define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)
/*! PSW_ON_SOFT - Software power on trigger
*/
#define PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PSW_ON_SOFT_MASK)
#define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)
#define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)
/*! ISO_OFF_SOFT - Software isolation off trigger
*/
#define PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_ISO_OFF_SOFT_MASK)
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK (0xFFFF0000U)
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT (16U)
/*! PWR_OFF_AT_SP - Power off when system enters Setpoint number
*/
#define PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_SHIFT)) & PGMC_BPC_BPC_POWER_CTRL_PWR_OFF_AT_SP_MASK)
/*! @} */
/*! @name BPC_FLAG - BPC flag */
/*! @{ */
#define PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK (0x1U)
#define PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT (0U)
/*! PDN_FLAG - set to 1 after power switch off, cleared by writing 1
*/
#define PGMC_BPC_BPC_FLAG_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_FLAG_PDN_FLAG_SHIFT)) & PGMC_BPC_BPC_FLAG_PDN_FLAG_MASK)
/*! @} */
/*! @name BPC_SSAR_SAVE_CTRL - BPC SSAR save control */
/*! @{ */
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK (0x1U)
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT (0U)
/*! SAVE_AT_RUN - Save data at RUN mode, software writting 0x1 to trigger SSARC to execute save process
*/
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_RUN_MASK)
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK (0x2U)
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT (1U)
/*! SAVE_AT_WAIT - Save data when domain enters WAIT mode
*/
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_WAIT_MASK)
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK (0x4U)
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT (2U)
/*! SAVE_AT_STOP - Save data when domain enters STOP mode
*/
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_STOP_MASK)
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK (0x8U)
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT (3U)
/*! SAVE_AT_SUSPEND - Save data when domain enters SUSPEND mode
*/
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SUSPEND_MASK)
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK (0xFFFF0000U)
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT (16U)
/*! SAVE_AT_SP - Save data when system enters a Setpoint.
*/
#define PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_SAVE_CTRL_SAVE_AT_SP_MASK)
/*! @} */
/*! @name BPC_SSAR_RESTORE_CTRL - BPC SSAR restore control */
/*! @{ */
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK (0x1U)
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT (0U)
/*! RESTORE_AT_RUN - Restore data at RUN mode
*/
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK)
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK (0xFFFF0000U)
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT (16U)
/*! RESTORE_AT_SP - Restore data when system enters a Setpoint.
*/
#define PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_SHIFT)) & PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PGMC_BPC_Register_Masks */
/* PGMC_BPC - Peripheral instance base addresses */
/** Peripheral PGMC_BPC0 base address */
#define PGMC_BPC0_BASE (0x40C88000u)
/** Peripheral PGMC_BPC0 base pointer */
#define PGMC_BPC0 ((PGMC_BPC_Type *)PGMC_BPC0_BASE)
/** Peripheral PGMC_BPC1 base address */
#define PGMC_BPC1_BASE (0x40C88200u)
/** Peripheral PGMC_BPC1 base pointer */
#define PGMC_BPC1 ((PGMC_BPC_Type *)PGMC_BPC1_BASE)
/** Peripheral PGMC_BPC2 base address */
#define PGMC_BPC2_BASE (0x40C88400u)
/** Peripheral PGMC_BPC2 base pointer */
#define PGMC_BPC2 ((PGMC_BPC_Type *)PGMC_BPC2_BASE)
/** Peripheral PGMC_BPC3 base address */
#define PGMC_BPC3_BASE (0x40C88600u)
/** Peripheral PGMC_BPC3 base pointer */
#define PGMC_BPC3 ((PGMC_BPC_Type *)PGMC_BPC3_BASE)
/** Peripheral PGMC_BPC4 base address */
#define PGMC_BPC4_BASE (0x40C88800u)
/** Peripheral PGMC_BPC4 base pointer */
#define PGMC_BPC4 ((PGMC_BPC_Type *)PGMC_BPC4_BASE)
/** Peripheral PGMC_BPC5 base address */
#define PGMC_BPC5_BASE (0x40C88A00u)
/** Peripheral PGMC_BPC5 base pointer */
#define PGMC_BPC5 ((PGMC_BPC_Type *)PGMC_BPC5_BASE)
/** Peripheral PGMC_BPC6 base address */
#define PGMC_BPC6_BASE (0x40C88C00u)
/** Peripheral PGMC_BPC6 base pointer */
#define PGMC_BPC6 ((PGMC_BPC_Type *)PGMC_BPC6_BASE)
/** Peripheral PGMC_BPC7 base address */
#define PGMC_BPC7_BASE (0x40C88E00u)
/** Peripheral PGMC_BPC7 base pointer */
#define PGMC_BPC7 ((PGMC_BPC_Type *)PGMC_BPC7_BASE)
/** Array initializer of PGMC_BPC peripheral base addresses */
#define PGMC_BPC_BASE_ADDRS { PGMC_BPC0_BASE, PGMC_BPC1_BASE, PGMC_BPC2_BASE, PGMC_BPC3_BASE, PGMC_BPC4_BASE, PGMC_BPC5_BASE, PGMC_BPC6_BASE, PGMC_BPC7_BASE }
/** Array initializer of PGMC_BPC peripheral base pointers */
#define PGMC_BPC_BASE_PTRS { PGMC_BPC0, PGMC_BPC1, PGMC_BPC2, PGMC_BPC3, PGMC_BPC4, PGMC_BPC5, PGMC_BPC6, PGMC_BPC7 }
/*!
* @}
*/ /* end of group PGMC_BPC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PGMC_CPC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PGMC_CPC_Peripheral_Access_Layer PGMC_CPC Peripheral Access Layer
* @{
*/
/** PGMC_CPC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t CPC_AUTHEN_CTRL; /**< CPC Authentication Control, offset: 0x4 */
uint8_t RESERVED_1[8];
__IO uint32_t CPC_CORE_MODE; /**< CPC Core Mode, offset: 0x10 */
__IO uint32_t CPC_CORE_POWER_CTRL; /**< CPC core power control, offset: 0x14 */
uint8_t RESERVED_2[20];
__IO uint32_t CPC_FLAG; /**< CPC flag, offset: 0x2C */
uint8_t RESERVED_3[16];
__IO uint32_t CPC_CACHE_MODE; /**< CPC Cache Mode, offset: 0x40 */
__IO uint32_t CPC_CACHE_CM_CTRL; /**< CPC cache CPU mode control, offset: 0x44 */
__IO uint32_t CPC_CACHE_SP_CTRL_0; /**< CPC cache Setpoint control 0, offset: 0x48 */
__IO uint32_t CPC_CACHE_SP_CTRL_1; /**< CPC cache Setpoint control 1, offset: 0x4C */
uint8_t RESERVED_4[112];
__IO uint32_t CPC_LMEM_MODE; /**< CPC local memory Mode, offset: 0xC0 */
__IO uint32_t CPC_LMEM_CM_CTRL; /**< CPC local memory CPU mode control, offset: 0xC4 */
__IO uint32_t CPC_LMEM_SP_CTRL_0; /**< CPC local memory Setpoint control 0, offset: 0xC8 */
__IO uint32_t CPC_LMEM_SP_CTRL_1; /**< CPC local memory Setpoint control 1, offset: 0xCC */
} PGMC_CPC_Type;
/* ----------------------------------------------------------------------------
-- PGMC_CPC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PGMC_CPC_Register_Masks PGMC_CPC Register Masks
* @{
*/
/*! @name CPC_AUTHEN_CTRL - CPC Authentication Control */
/*! @{ */
#define PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK (0x1U)
#define PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT (0U)
/*! USER - Allow user mode access
*/
#define PGMC_CPC_CPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK)
#define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
#define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
/*! NONSECURE - Allow non-secure mode access
*/
#define PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK)
#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
#define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
#define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Domain ID white list
*/
#define PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)
#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - White list lock
*/
#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK)
#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
/*! LOCK_CFG - Configuration lock
*/
#define PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK)
/*! @} */
/*! @name CPC_CORE_MODE - CPC Core Mode */
/*! @{ */
#define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK (0x3U)
#define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT (0U)
/*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
* 0b00..Not affected by any low power mode
* 0b01..Controlled by CPU power mode of the domain
* 0b10..Reserved
* 0b11..Reserved
*/
#define PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CORE_MODE_CTRL_MODE_MASK)
/*! @} */
/*! @name CPC_CORE_POWER_CTRL - CPC core power control */
/*! @{ */
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK (0x2U)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT (1U)
/*! PWR_OFF_AT_WAIT - Power off when domain enters WAIT mode
*/
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_WAIT_MASK)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK (0x4U)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT (2U)
/*! PWR_OFF_AT_STOP - Power off when domain enters STOP mode
*/
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_STOP_MASK)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK (0x8U)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT (3U)
/*! PWR_OFF_AT_SUSPEND - Power off when domain enters SUSPEND mode
*/
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PWR_OFF_AT_SUSPEND_MASK)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK (0x100U)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT (8U)
/*! ISO_ON_SOFT - Software isolation on trigger
*/
#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK (0x200U)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT (9U)
/*! PSW_OFF_SOFT - Software power off trigger
*/
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK (0x400U)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT (10U)
/*! PSW_ON_SOFT - Software power on trigger
*/
#define PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK (0x800U)
#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT (11U)
/*! ISO_OFF_SOFT - Software isolation off trigger
*/
#define PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_SHIFT)) & PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK)
/*! @} */
/*! @name CPC_FLAG - CPC flag */
/*! @{ */
#define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK (0x1U)
#define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT (0U)
/*! CORE_PDN_FLAG - set to 1 after core power switch off, cleared by writing 1
*/
#define PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_SHIFT)) & PGMC_CPC_CPC_FLAG_CORE_PDN_FLAG_MASK)
/*! @} */
/*! @name CPC_CACHE_MODE - CPC Cache Mode */
/*! @{ */
#define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK (0x3U)
#define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT (0U)
/*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
* 0b00..Not affected by any low power mode
* 0b01..Controlled by CPU power mode of the domain
* 0b10..Controlled by Setpoint
* 0b11..Reserved
*/
#define PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE_MASK)
/*! @} */
/*! @name CPC_CACHE_CM_CTRL - CPC cache CPU mode control */
/*! @{ */
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)
/*! MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode
*/
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_RUN_MASK)
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)
/*! MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_WAIT_MASK)
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)
/*! MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_STOP_MASK)
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)
/*! MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_AT_SUSPEND_MASK)
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK (0x10000U)
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT (16U)
/*! MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete
*/
#define PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_CACHE_CM_CTRL_MLPL_SOFT_MASK)
/*! @} */
/*! @name CPC_CACHE_SP_CTRL_0 - CPC cache Setpoint control 0 */
/*! @{ */
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)
/*! MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP0_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)
/*! MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP1_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)
/*! MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP2_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)
/*! MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP3_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)
/*! MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP4_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)
/*! MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP5_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)
/*! MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP6_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)
/*! MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_0_MLPL_AT_SP7_MASK)
/*! @} */
/*! @name CPC_CACHE_SP_CTRL_1 - CPC cache Setpoint control 1 */
/*! @{ */
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)
/*! MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP8_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)
/*! MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP9_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)
/*! MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP10_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)
/*! MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP11_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)
/*! MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP12_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)
/*! MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP13_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)
/*! MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP14_MASK)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)
/*! MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_CACHE_SP_CTRL_1_MLPL_AT_SP15_MASK)
/*! @} */
/*! @name CPC_LMEM_MODE - CPC local memory Mode */
/*! @{ */
#define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK (0x3U)
#define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT (0U)
/*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
* 0b00..Not affected by any low power mode
* 0b01..Controlled by CPU power mode of the domain
* 0b10..Controlled by Setpoint
* 0b11..Reserved
*/
#define PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_SHIFT)) & PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE_MASK)
/*! @} */
/*! @name CPC_LMEM_CM_CTRL - CPC local memory CPU mode control */
/*! @{ */
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK (0xFU)
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT (0U)
/*! MLPL_AT_RUN - Memory Low Power Level (MLPL) at RUN mode
*/
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_RUN_MASK)
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK (0xF0U)
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT (4U)
/*! MLPL_AT_WAIT - Memory Low Power Level (MLPL) at WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_WAIT_MASK)
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK (0xF00U)
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT (8U)
/*! MLPL_AT_STOP - Memory Low Power Level (MLPL) at STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_STOP_MASK)
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK (0xF000U)
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT (12U)
/*! MLPL_AT_SUSPEND - Memory Low Power Level (MLPL) at SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_AT_SUSPEND_MASK)
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK (0x10000U)
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT (16U)
/*! MLPL_SOFT - Memory Low Power Level (MLPL) software change request, keep 1 until MLPL transition complete
*/
#define PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_SHIFT)) & PGMC_CPC_CPC_LMEM_CM_CTRL_MLPL_SOFT_MASK)
/*! @} */
/*! @name CPC_LMEM_SP_CTRL_0 - CPC local memory Setpoint control 0 */
/*! @{ */
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK (0xFU)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT (0U)
/*! MLPL_AT_SP0 - Memory Low Power Level (MLPL) at Setpoint 0. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP0_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK (0xF0U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT (4U)
/*! MLPL_AT_SP1 - Memory Low Power Level (MLPL) at Setpoint 1. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP1_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK (0xF00U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT (8U)
/*! MLPL_AT_SP2 - Memory Low Power Level (MLPL) at Setpoint 2. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP2_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK (0xF000U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT (12U)
/*! MLPL_AT_SP3 - Memory Low Power Level (MLPL) at Setpoint 3. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP3_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK (0xF0000U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT (16U)
/*! MLPL_AT_SP4 - Memory Low Power Level (MLPL) at Setpoint 4. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP4_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK (0xF00000U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT (20U)
/*! MLPL_AT_SP5 - Memory Low Power Level (MLPL) at Setpoint 5. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP5_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK (0xF000000U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT (24U)
/*! MLPL_AT_SP6 - Memory Low Power Level (MLPL) at Setpoint 6. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP6_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK (0xF0000000U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT (28U)
/*! MLPL_AT_SP7 - Memory Low Power Level (MLPL) at Setpoint 7. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_0_MLPL_AT_SP7_MASK)
/*! @} */
/*! @name CPC_LMEM_SP_CTRL_1 - CPC local memory Setpoint control 1 */
/*! @{ */
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK (0xFU)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT (0U)
/*! MLPL_AT_SP8 - Memory Low Power Level (MLPL) at Setpoint 8. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP8_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK (0xF0U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT (4U)
/*! MLPL_AT_SP9 - Memory Low Power Level (MLPL) at Setpoint 9. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP9_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK (0xF00U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT (8U)
/*! MLPL_AT_SP10 - Memory Low Power Level (MLPL) at Setpoint 10. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP10_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK (0xF000U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT (12U)
/*! MLPL_AT_SP11 - Memory Low Power Level (MLPL) at Setpoint 11. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP11_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK (0xF0000U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT (16U)
/*! MLPL_AT_SP12 - Memory Low Power Level (MLPL) at Setpoint 12. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP12_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK (0xF00000U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT (20U)
/*! MLPL_AT_SP13 - Memory Low Power Level (MLPL) at Setpoint 13. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP13_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK (0xF000000U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT (24U)
/*! MLPL_AT_SP14 - Memory Low Power Level (MLPL) at Setpoint 14. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP14_MASK)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK (0xF0000000U)
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT (28U)
/*! MLPL_AT_SP15 - Memory Low Power Level (MLPL) at Setpoint 15. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15(x) (((uint32_t)(((uint32_t)(x)) << PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_SHIFT)) & PGMC_CPC_CPC_LMEM_SP_CTRL_1_MLPL_AT_SP15_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PGMC_CPC_Register_Masks */
/* PGMC_CPC - Peripheral instance base addresses */
/** Peripheral PGMC_CPC0 base address */
#define PGMC_CPC0_BASE (0x40C89000u)
/** Peripheral PGMC_CPC0 base pointer */
#define PGMC_CPC0 ((PGMC_CPC_Type *)PGMC_CPC0_BASE)
/** Peripheral PGMC_CPC1 base address */
#define PGMC_CPC1_BASE (0x40C89400u)
/** Peripheral PGMC_CPC1 base pointer */
#define PGMC_CPC1 ((PGMC_CPC_Type *)PGMC_CPC1_BASE)
/** Array initializer of PGMC_CPC peripheral base addresses */
#define PGMC_CPC_BASE_ADDRS { PGMC_CPC0_BASE, PGMC_CPC1_BASE }
/** Array initializer of PGMC_CPC peripheral base pointers */
#define PGMC_CPC_BASE_PTRS { PGMC_CPC0, PGMC_CPC1 }
/*!
* @}
*/ /* end of group PGMC_CPC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PGMC_MIF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PGMC_MIF_Peripheral_Access_Layer PGMC_MIF Peripheral Access Layer
* @{
*/
/** PGMC_MIF - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t MIF_AUTHEN_CTRL; /**< MIF Authentication Control, offset: 0x4 */
uint8_t RESERVED_1[8];
__IO uint32_t MIF_MLPL_SLEEP; /**< MIF MLPL control of SLEEP, offset: 0x10 */
uint8_t RESERVED_2[12];
__IO uint32_t MIF_MLPL_IG; /**< MIF MLPL control of IG, offset: 0x20 */
uint8_t RESERVED_3[12];
__IO uint32_t MIF_MLPL_LS; /**< MIF MLPL control of LS, offset: 0x30 */
uint8_t RESERVED_4[12];
__IO uint32_t MIF_MLPL_HS; /**< MIF MLPL control of HS, offset: 0x40 */
uint8_t RESERVED_5[12];
__IO uint32_t MIF_MLPL_STDBY; /**< MIF MLPL control of STDBY, offset: 0x50 */
uint8_t RESERVED_6[12];
__IO uint32_t MIF_MLPL_ARR_PDN; /**< MIF MLPL control of array power down, offset: 0x60 */
uint8_t RESERVED_7[12];
__IO uint32_t MIF_MLPL_PER_PDN; /**< MIF MLPL control of peripheral power down, offset: 0x70 */
uint8_t RESERVED_8[12];
__IO uint32_t MIF_MLPL_INITN; /**< MIF MLPL control of INITN, offset: 0x80 */
uint8_t RESERVED_9[44];
__IO uint32_t MIF_MLPL_ISO; /**< MIF MLPL control of isolation enable, offset: 0xB0 */
} PGMC_MIF_Type;
/* ----------------------------------------------------------------------------
-- PGMC_MIF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PGMC_MIF_Register_Masks PGMC_MIF Register Masks
* @{
*/
/*! @name MIF_AUTHEN_CTRL - MIF Authentication Control */
/*! @{ */
#define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
#define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
/*! LOCK_CFG - Configuration lock
*/
#define PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK)
/*! @} */
/*! @name MIF_MLPL_SLEEP - MIF MLPL control of SLEEP */
/*! @{ */
#define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK (0xFFFFU)
#define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT (0U)
/*! MLPL_CTRL - Signal behavior at each MLPL
*/
#define PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_SLEEP_MLPL_CTRL_MASK)
/*! @} */
/*! @name MIF_MLPL_IG - MIF MLPL control of IG */
/*! @{ */
#define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK (0xFFFFU)
#define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT (0U)
/*! MLPL_CTRL - Signal behavior at each MLPL
*/
#define PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_IG_MLPL_CTRL_MASK)
/*! @} */
/*! @name MIF_MLPL_LS - MIF MLPL control of LS */
/*! @{ */
#define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK (0xFFFFU)
#define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT (0U)
/*! MLPL_CTRL - Signal behavior at each MLPL
*/
#define PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_LS_MLPL_CTRL_MASK)
/*! @} */
/*! @name MIF_MLPL_HS - MIF MLPL control of HS */
/*! @{ */
#define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK (0xFFFFU)
#define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT (0U)
/*! MLPL_CTRL - Signal behavior at each MLPL
*/
#define PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_HS_MLPL_CTRL_MASK)
/*! @} */
/*! @name MIF_MLPL_STDBY - MIF MLPL control of STDBY */
/*! @{ */
#define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK (0xFFFFU)
#define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT (0U)
/*! MLPL_CTRL - Signal behavior at each MLPL
*/
#define PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_STDBY_MLPL_CTRL_MASK)
/*! @} */
/*! @name MIF_MLPL_ARR_PDN - MIF MLPL control of array power down */
/*! @{ */
#define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK (0xFFFFU)
#define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT (0U)
/*! MLPL_CTRL - Signal behavior at each MLPL
*/
#define PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ARR_PDN_MLPL_CTRL_MASK)
/*! @} */
/*! @name MIF_MLPL_PER_PDN - MIF MLPL control of peripheral power down */
/*! @{ */
#define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK (0xFFFFU)
#define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT (0U)
/*! MLPL_CTRL - Signal behavior at each MLPL
*/
#define PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_PER_PDN_MLPL_CTRL_MASK)
/*! @} */
/*! @name MIF_MLPL_INITN - MIF MLPL control of INITN */
/*! @{ */
#define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK (0xFFFFU)
#define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT (0U)
/*! MLPL_CTRL - Signal behavior at each MLPL
*/
#define PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_MLPL_CTRL_MASK)
#define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK (0x80000000U)
#define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT (31U)
/*! BYPASS_VDD_OK - Bypass vdd_ok. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_SHIFT)) & PGMC_MIF_MIF_MLPL_INITN_BYPASS_VDD_OK_MASK)
/*! @} */
/*! @name MIF_MLPL_ISO - MIF MLPL control of isolation enable */
/*! @{ */
#define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK (0xFFFFU)
#define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT (0U)
/*! MLPL_CTRL - Signal behavior at each MLPL
*/
#define PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_SHIFT)) & PGMC_MIF_MIF_MLPL_ISO_MLPL_CTRL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PGMC_MIF_Register_Masks */
/* PGMC_MIF - Peripheral instance base addresses */
/** Peripheral PGMC_CPC0_MIF0 base address */
#define PGMC_CPC0_MIF0_BASE (0x40C89100u)
/** Peripheral PGMC_CPC0_MIF0 base pointer */
#define PGMC_CPC0_MIF0 ((PGMC_MIF_Type *)PGMC_CPC0_MIF0_BASE)
/** Peripheral PGMC_CPC0_MIF1 base address */
#define PGMC_CPC0_MIF1_BASE (0x40C89200u)
/** Peripheral PGMC_CPC0_MIF1 base pointer */
#define PGMC_CPC0_MIF1 ((PGMC_MIF_Type *)PGMC_CPC0_MIF1_BASE)
/** Peripheral PGMC_CPC1_MIF0 base address */
#define PGMC_CPC1_MIF0_BASE (0x40C89500u)
/** Peripheral PGMC_CPC1_MIF0 base pointer */
#define PGMC_CPC1_MIF0 ((PGMC_MIF_Type *)PGMC_CPC1_MIF0_BASE)
/** Peripheral PGMC_CPC1_MIF1 base address */
#define PGMC_CPC1_MIF1_BASE (0x40C89600u)
/** Peripheral PGMC_CPC1_MIF1 base pointer */
#define PGMC_CPC1_MIF1 ((PGMC_MIF_Type *)PGMC_CPC1_MIF1_BASE)
/** Array initializer of PGMC_MIF peripheral base addresses */
#define PGMC_MIF_BASE_ADDRS { PGMC_CPC0_MIF0_BASE, PGMC_CPC0_MIF1_BASE, PGMC_CPC1_MIF0_BASE, PGMC_CPC1_MIF1_BASE }
/** Array initializer of PGMC_MIF peripheral base pointers */
#define PGMC_MIF_BASE_PTRS { PGMC_CPC0_MIF0, PGMC_CPC0_MIF1, PGMC_CPC1_MIF0, PGMC_CPC1_MIF1 }
/*!
* @}
*/ /* end of group PGMC_MIF_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PGMC_PPC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PGMC_PPC_Peripheral_Access_Layer PGMC_PPC Peripheral Access Layer
* @{
*/
/** PGMC_PPC - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[4];
__IO uint32_t PPC_AUTHEN_CTRL; /**< PPC Authentication Control, offset: 0x4 */
uint8_t RESERVED_1[8];
__IO uint32_t PPC_MODE; /**< PPC Mode, offset: 0x10 */
__IO uint32_t PPC_STBY_CM_CTRL; /**< PPC standby CPU mode control, offset: 0x14 */
__IO uint32_t PPC_STBY_SP_CTRL; /**< PPC standby Setpoint control, offset: 0x18 */
} PGMC_PPC_Type;
/* ----------------------------------------------------------------------------
-- PGMC_PPC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PGMC_PPC_Register_Masks PGMC_PPC Register Masks
* @{
*/
/*! @name PPC_AUTHEN_CTRL - PPC Authentication Control */
/*! @{ */
#define PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK (0x1U)
#define PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT (0U)
/*! USER - Allow user mode access
*/
#define PGMC_PPC_PPC_AUTHEN_CTRL_USER(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_USER_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK)
#define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK (0x2U)
#define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT (1U)
/*! NONSECURE - Allow non-secure mode access
*/
#define PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK)
#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK (0x10U)
#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT (4U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK)
#define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK (0xF00U)
#define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT (8U)
/*! WHITE_LIST - Domain ID white list
*/
#define PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK)
#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK (0x1000U)
#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT (12U)
/*! LOCK_LIST - White list lock
*/
#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK)
#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK (0x100000U)
#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT (20U)
/*! LOCK_CFG - Configuration lock
*/
#define PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_SHIFT)) & PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK)
/*! @} */
/*! @name PPC_MODE - PPC Mode */
/*! @{ */
#define PGMC_PPC_PPC_MODE_CTRL_MODE_MASK (0x3U)
#define PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT (0U)
/*! CTRL_MODE - Control mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
* 0b00..Not affected by any low power mode
* 0b01..Controlled by CPU power mode of the domain
* 0b10..Controlled by Setpoint and system standby
* 0b11..Reserved
*/
#define PGMC_PPC_PPC_MODE_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_CTRL_MODE_SHIFT)) & PGMC_PPC_PPC_MODE_CTRL_MODE_MASK)
#define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK (0x30U)
#define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT (4U)
/*! DOMAIN_ASSIGN - Domain assignment of the BPC
* 0b00..Domain 0
* 0b01..Domain 1
* 0b10..Domain 2
* 0b11..Domain 3
*/
#define PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_SHIFT)) & PGMC_PPC_PPC_MODE_DOMAIN_ASSIGN_MASK)
/*! @} */
/*! @name PPC_STBY_CM_CTRL - PPC standby CPU mode control */
/*! @{ */
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK (0x2U)
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT (1U)
/*! STBY_ON_AT_WAIT - PMIC Standby on when domain enters WAIT mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_WAIT_MASK)
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK (0x4U)
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT (2U)
/*! STBY_ON_AT_STOP - PMIC Standby on when domain enters STOP mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_STOP_MASK)
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK (0x8U)
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT (3U)
/*! STBY_ON_AT_SUSPEND - PMIC Standby on when domain enters SUSPEND mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_AT_SUSPEND_MASK)
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK (0x100U)
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT (8U)
/*! STBY_ON_SOFT - Software PMIC standby on trigger
*/
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK)
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK (0x200U)
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT (9U)
/*! STBY_OFF_SOFT - Software PMIC standby off trigger
*/
#define PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_SHIFT)) & PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK)
/*! @} */
/*! @name PPC_STBY_SP_CTRL - PPC standby Setpoint control */
/*! @{ */
#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK (0xFFFFU)
#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT (0U)
/*! STBY_ON_AT_SP_ACTIVE - PMIC standby on when system enters Setpoint number. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_ACTIVE_MASK)
#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK (0xFFFF0000U)
#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT (16U)
/*! STBY_ON_AT_SP_SLEEP - PMIC standby on when system enters Setpoint number and system is in
* standby mode. This field is locked by AUTHEN_CTRL[LOCK_CFG] field.
*/
#define PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP(x) (((uint32_t)(((uint32_t)(x)) << PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_SHIFT)) & PGMC_PPC_PPC_STBY_SP_CTRL_STBY_ON_AT_SP_SLEEP_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PGMC_PPC_Register_Masks */
/* PGMC_PPC - Peripheral instance base addresses */
/** Peripheral PGMC_PPC0 base address */
#define PGMC_PPC0_BASE (0x40C8B000u)
/** Peripheral PGMC_PPC0 base pointer */
#define PGMC_PPC0 ((PGMC_PPC_Type *)PGMC_PPC0_BASE)
/** Array initializer of PGMC_PPC peripheral base addresses */
#define PGMC_PPC_BASE_ADDRS { PGMC_PPC0_BASE }
/** Array initializer of PGMC_PPC peripheral base pointers */
#define PGMC_PPC_BASE_PTRS { PGMC_PPC0 }
/*!
* @}
*/ /* end of group PGMC_PPC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PHY_LDO Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PHY_LDO_Peripheral_Access_Layer PHY_LDO Peripheral Access Layer
* @{
*/
/** PHY_LDO - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0 */
__IO uint32_t RW; /**< Analog Control Register CTRL0, offset: 0x0 */
__IO uint32_t SET; /**< Analog Control Register CTRL0, offset: 0x4 */
__IO uint32_t CLR; /**< Analog Control Register CTRL0, offset: 0x8 */
__IO uint32_t TOG; /**< Analog Control Register CTRL0, offset: 0xC */
} CTRL0;
uint8_t RESERVED_0[64];
struct { /* offset: 0x50 */
__I uint32_t RW; /**< Analog Status Register STAT0, offset: 0x50 */
__I uint32_t SET; /**< Analog Status Register STAT0, offset: 0x54 */
__I uint32_t CLR; /**< Analog Status Register STAT0, offset: 0x58 */
__I uint32_t TOG; /**< Analog Status Register STAT0, offset: 0x5C */
} STAT0;
} PHY_LDO_Type;
/* ----------------------------------------------------------------------------
-- PHY_LDO Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PHY_LDO_Register_Masks PHY_LDO Register Masks
* @{
*/
/*! @name CTRL0 - Analog Control Register CTRL0 */
/*! @{ */
#define PHY_LDO_CTRL0_LINREG_EN_MASK (0x1U)
#define PHY_LDO_CTRL0_LINREG_EN_SHIFT (0U)
/*! LINREG_EN - LinrReg master enable
*/
#define PHY_LDO_CTRL0_LINREG_EN(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_EN_MASK)
#define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK (0x2U)
#define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT (1U)
/*! LINREG_PWRUPLOAD_DIS - LinReg power-up load disable
* 0b0..Internal pull-down enabled
* 0b1..Internal pull-down disabled
*/
#define PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_SHIFT)) & PHY_LDO_CTRL0_LINREG_PWRUPLOAD_DIS_MASK)
#define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK (0x4U)
#define PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT (2U)
/*! LINREG_ILIMIT_EN - LinReg current-limit enable
*/
#define PHY_LDO_CTRL0_LINREG_ILIMIT_EN(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_ILIMIT_EN_SHIFT)) & PHY_LDO_CTRL0_LINREG_ILIMIT_EN_MASK)
#define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK (0x1F0U)
#define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT (4U)
/*! LINREG_OUTPUT_TRG - LinReg output voltage target setting
* 0b00000..Set output voltage to x.xV
* 0b10000..Sets output voltage to 1.0V
* 0b11111..Set output voltage to x.xV
*/
#define PHY_LDO_CTRL0_LINREG_OUTPUT_TRG(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_SHIFT)) & PHY_LDO_CTRL0_LINREG_OUTPUT_TRG_MASK)
#define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK (0x8000U)
#define PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT (15U)
/*! LINREG_PHY_ISO_B - Isolation control for attached PHY load
*/
#define PHY_LDO_CTRL0_LINREG_PHY_ISO_B(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_CTRL0_LINREG_PHY_ISO_B_SHIFT)) & PHY_LDO_CTRL0_LINREG_PHY_ISO_B_MASK)
/*! @} */
/*! @name STAT0 - Analog Status Register STAT0 */
/*! @{ */
#define PHY_LDO_STAT0_LINREG_STAT_MASK (0xFU)
#define PHY_LDO_STAT0_LINREG_STAT_SHIFT (0U)
/*! LINREG_STAT - LinReg Status Bits
*/
#define PHY_LDO_STAT0_LINREG_STAT(x) (((uint32_t)(((uint32_t)(x)) << PHY_LDO_STAT0_LINREG_STAT_SHIFT)) & PHY_LDO_STAT0_LINREG_STAT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PHY_LDO_Register_Masks */
/* PHY_LDO - Peripheral instance base addresses */
/** Peripheral PHY_LDO base address */
#define PHY_LDO_BASE (0u)
/** Peripheral PHY_LDO base pointer */
#define PHY_LDO ((PHY_LDO_Type *)PHY_LDO_BASE)
/** Array initializer of PHY_LDO peripheral base addresses */
#define PHY_LDO_BASE_ADDRS { PHY_LDO_BASE }
/** Array initializer of PHY_LDO peripheral base pointers */
#define PHY_LDO_BASE_PTRS { PHY_LDO }
/*!
* @}
*/ /* end of group PHY_LDO_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PIT Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
* @{
*/
/** PIT - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
uint8_t RESERVED_0[220];
__I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */
__I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */
uint8_t RESERVED_1[24];
struct { /* offset: 0x100, array step: 0x10 */
__IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
__I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
__IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
__IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
} CHANNEL[4];
} PIT_Type;
/* ----------------------------------------------------------------------------
-- PIT Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PIT_Register_Masks PIT Register Masks
* @{
*/
/*! @name MCR - PIT Module Control Register */
/*! @{ */
#define PIT_MCR_FRZ_MASK (0x1U)
#define PIT_MCR_FRZ_SHIFT (0U)
/*! FRZ - Freeze
* 0b0..Timers continue to run in Debug mode.
* 0b1..Timers are stopped in Debug mode.
*/
#define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
#define PIT_MCR_MDIS_MASK (0x2U)
#define PIT_MCR_MDIS_SHIFT (1U)
/*! MDIS - Module Disable for PIT
* 0b0..Clock for standard PIT timers is enabled.
* 0b1..Clock for standard PIT timers is disabled.
*/
#define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
/*! @} */
/*! @name LTMR64H - PIT Upper Lifetime Timer Register */
/*! @{ */
#define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU)
#define PIT_LTMR64H_LTH_SHIFT (0U)
/*! LTH - Life Timer value
*/
#define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK)
/*! @} */
/*! @name LTMR64L - PIT Lower Lifetime Timer Register */
/*! @{ */
#define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU)
#define PIT_LTMR64L_LTL_SHIFT (0U)
/*! LTL - Life Timer value
*/
#define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK)
/*! @} */
/*! @name LDVAL - Timer Load Value Register */
/*! @{ */
#define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
#define PIT_LDVAL_TSV_SHIFT (0U)
/*! TSV - Timer Start Value
*/
#define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
/*! @} */
/* The count of PIT_LDVAL */
#define PIT_LDVAL_COUNT (4U)
/*! @name CVAL - Current Timer Value Register */
/*! @{ */
#define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
#define PIT_CVAL_TVL_SHIFT (0U)
/*! TVL - Current Timer Value
*/
#define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
/*! @} */
/* The count of PIT_CVAL */
#define PIT_CVAL_COUNT (4U)
/*! @name TCTRL - Timer Control Register */
/*! @{ */
#define PIT_TCTRL_TEN_MASK (0x1U)
#define PIT_TCTRL_TEN_SHIFT (0U)
/*! TEN - Timer Enable
* 0b0..Timer n is disabled.
* 0b1..Timer n is enabled.
*/
#define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
#define PIT_TCTRL_TIE_MASK (0x2U)
#define PIT_TCTRL_TIE_SHIFT (1U)
/*! TIE - Timer Interrupt Enable
* 0b0..Interrupt requests from Timer n are disabled.
* 0b1..Interrupt is requested whenever TIF is set.
*/
#define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
#define PIT_TCTRL_CHN_MASK (0x4U)
#define PIT_TCTRL_CHN_SHIFT (2U)
/*! CHN - Chain Mode
* 0b0..Timer is not chained.
* 0b1..Timer is chained to a previous timer. For example, for channel 2, if this field is set, Timer 2 is chained to Timer 1.
*/
#define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
/*! @} */
/* The count of PIT_TCTRL */
#define PIT_TCTRL_COUNT (4U)
/*! @name TFLG - Timer Flag Register */
/*! @{ */
#define PIT_TFLG_TIF_MASK (0x1U)
#define PIT_TFLG_TIF_SHIFT (0U)
/*! TIF - Timer Interrupt Flag
* 0b0..Timeout has not yet occurred.
* 0b1..Timeout has occurred.
*/
#define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
/*! @} */
/* The count of PIT_TFLG */
#define PIT_TFLG_COUNT (4U)
/*!
* @}
*/ /* end of group PIT_Register_Masks */
/* PIT - Peripheral instance base addresses */
/** Peripheral PIT1 base address */
#define PIT1_BASE (0x400D8000u)
/** Peripheral PIT1 base pointer */
#define PIT1 ((PIT_Type *)PIT1_BASE)
/** Peripheral PIT2 base address */
#define PIT2_BASE (0x40CB0000u)
/** Peripheral PIT2 base pointer */
#define PIT2 ((PIT_Type *)PIT2_BASE)
/** Array initializer of PIT peripheral base addresses */
#define PIT_BASE_ADDRS { 0u, PIT1_BASE, PIT2_BASE }
/** Array initializer of PIT peripheral base pointers */
#define PIT_BASE_PTRS { (PIT_Type *)0u, PIT1, PIT2 }
/** Interrupt vectors for the PIT peripheral type */
#define PIT_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PIT1_IRQn, PIT1_IRQn, PIT1_IRQn, PIT1_IRQn }, { PIT2_IRQn, PIT2_IRQn, PIT2_IRQn, PIT2_IRQn } }
/*!
* @}
*/ /* end of group PIT_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PUF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PUF_Peripheral_Access_Layer PUF Peripheral Access Layer
* @{
*/
/** PUF - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< PUF Control Register, offset: 0x0 */
__IO uint32_t KEYINDEX; /**< PUF Key Index Register, offset: 0x4 */
__IO uint32_t KEYSIZE; /**< PUF Key Size Register, offset: 0x8 */
uint8_t RESERVED_0[20];
__I uint32_t STAT; /**< PUF Status Register, offset: 0x20 */
uint8_t RESERVED_1[4];
__I uint32_t ALLOW; /**< PUF Allow Register, offset: 0x28 */
uint8_t RESERVED_2[20];
__O uint32_t KEYINPUT; /**< PUF Key Input Register, offset: 0x40 */
__O uint32_t CODEINPUT; /**< PUF Code Input Register, offset: 0x44 */
__I uint32_t CODEOUTPUT; /**< PUF Code Output Register, offset: 0x48 */
uint8_t RESERVED_3[20];
__I uint32_t KEYOUTINDEX; /**< PUF Key Output Index Register, offset: 0x60 */
__I uint32_t KEYOUTPUT; /**< PUF Key Output Register, offset: 0x64 */
uint8_t RESERVED_4[116];
__IO uint32_t IFSTAT; /**< PUF Interface Status Register, offset: 0xDC */
uint8_t RESERVED_5[28];
__I uint32_t VERSION; /**< PUF Version Register, offset: 0xFC */
__IO uint32_t INTEN; /**< PUF Interrupt Enable, offset: 0x100 */
__IO uint32_t INTSTAT; /**< PUF Interrupt Status, offset: 0x104 */
__IO uint32_t PWRCTRL; /**< PUF Power Control Of RAM, offset: 0x108 */
__IO uint32_t CFG; /**< PUF Configuration Register, offset: 0x10C */
uint8_t RESERVED_6[240];
__IO uint32_t KEYLOCK; /**< PUF Key Manager Lock, offset: 0x200 */
__IO uint32_t KEYENABLE; /**< PUF Key Manager Enable, offset: 0x204 */
__IO uint32_t KEYRESET; /**< PUF Key Manager Reset, offset: 0x208 */
__IO uint32_t IDXBLK; /**< PUF Index Block Key Output, offset: 0x20C */
__IO uint32_t IDXBLK_DP; /**< PUF Index Block Key Output, offset: 0x210 */
__IO uint32_t KEYMASK[2]; /**< PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable, array offset: 0x214, array step: 0x4 */
uint8_t RESERVED_7[56];
__I uint32_t IDXBLK_STATUS; /**< PUF Index Block Setting Status Register, offset: 0x254 */
__I uint32_t IDXBLK_SHIFT; /**< PUF Key Manager Shift Status, offset: 0x258 */
} PUF_Type;
/* ----------------------------------------------------------------------------
-- PUF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PUF_Register_Masks PUF Register Masks
* @{
*/
/*! @name CTRL - PUF Control Register */
/*! @{ */
#define PUF_CTRL_ZEROIZE_MASK (0x1U)
#define PUF_CTRL_ZEROIZE_SHIFT (0U)
/*! ZEROIZE - Begin Zeroize operation for PUF and go to Error state
* 0b0..No Zeroize operation in progress
* 0b1..Zeroize operation in progress
*/
#define PUF_CTRL_ZEROIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ZEROIZE_SHIFT)) & PUF_CTRL_ZEROIZE_MASK)
#define PUF_CTRL_ENROLL_MASK (0x2U)
#define PUF_CTRL_ENROLL_SHIFT (1U)
/*! ENROLL - Begin Enroll operation
* 0b0..No Enroll operation in progress
* 0b1..Enroll operation in progress
*/
#define PUF_CTRL_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_ENROLL_SHIFT)) & PUF_CTRL_ENROLL_MASK)
#define PUF_CTRL_START_MASK (0x4U)
#define PUF_CTRL_START_SHIFT (2U)
/*! START - Begin Start operation
* 0b0..No Start operation in progress
* 0b1..Start operation in progress
*/
#define PUF_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_START_SHIFT)) & PUF_CTRL_START_MASK)
#define PUF_CTRL_GENERATEKEY_MASK (0x8U)
#define PUF_CTRL_GENERATEKEY_SHIFT (3U)
/*! GENERATEKEY - Begin Set Intrinsic Key operation
* 0b0..No Set Intrinsic Key operation in progress
* 0b1..Set Intrinsic Key operation in progress
*/
#define PUF_CTRL_GENERATEKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GENERATEKEY_SHIFT)) & PUF_CTRL_GENERATEKEY_MASK)
#define PUF_CTRL_SETKEY_MASK (0x10U)
#define PUF_CTRL_SETKEY_SHIFT (4U)
/*! SETKEY - Begin Set User Key operation
* 0b0..No Set Key operation in progress
* 0b1..Set Key operation in progress
*/
#define PUF_CTRL_SETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_SETKEY_SHIFT)) & PUF_CTRL_SETKEY_MASK)
#define PUF_CTRL_GETKEY_MASK (0x40U)
#define PUF_CTRL_GETKEY_SHIFT (6U)
/*! GETKEY - Begin Get Key operation
* 0b0..No Get Key operation in progress
* 0b1..Get Key operation in progress
*/
#define PUF_CTRL_GETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CTRL_GETKEY_SHIFT)) & PUF_CTRL_GETKEY_MASK)
/*! @} */
/*! @name KEYINDEX - PUF Key Index Register */
/*! @{ */
#define PUF_KEYINDEX_KEYIDX_MASK (0xFU)
#define PUF_KEYINDEX_KEYIDX_SHIFT (0U)
/*! KEYIDX - PUF Key Index
* 0b0000..USE INDEX0
* 0b0001..USE INDEX1
* 0b0010..USE INDEX2
* 0b0011..USE INDEX3
* 0b0100..USE INDEX4
* 0b0101..USE INDEX5
* 0b0110..USE INDEX6
* 0b0111..USE INDEX7
* 0b1000..USE INDEX8
* 0b1001..USE INDEX9
* 0b1010..USE INDEX10
* 0b1011..USE INDEX11
* 0b1100..USE INDEX12
* 0b1101..USE INDEX13
* 0b1110..USE INDEX14
* 0b1111..USE INDEX15
*/
#define PUF_KEYINDEX_KEYIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINDEX_KEYIDX_SHIFT)) & PUF_KEYINDEX_KEYIDX_MASK)
/*! @} */
/*! @name KEYSIZE - PUF Key Size Register */
/*! @{ */
#define PUF_KEYSIZE_KEYSIZE_MASK (0x3FU)
#define PUF_KEYSIZE_KEYSIZE_SHIFT (0U)
/*! KEYSIZE - PUF Key Size
* 0b000001..Key Size is 8 Bytes and KC Size is 52 Bytes
* 0b000010..Key Size is 16 Bytes and KC Size is 52 Bytes
* 0b000011..Key Size is 24 Bytes and KC Size is 52 Bytes
* 0b000100..Key Size is 32 Bytes and KC Size is 52 Bytes
* 0b000101..Key Size is 40 Bytes and KC Size is 84 Bytes
* 0b000110..Key Size is 48 Bytes and KC Size is 84 Bytes
* 0b000111..Key Size is 56 Bytes and KC Size is 84 Bytes
* 0b001000..Key Size is 64 Bytes and KC Size is 84 Bytes
* 0b001001..Key Size is 72 Bytes and KC Size is 116 Bytes
* 0b001010..Key Size is 80 Bytes and KC Size is 116 Bytes
* 0b001011..Key Size is 88 Bytes and KC Size is 116 Bytes
* 0b001100..Key Size is 96 Bytes and KC Size is 116 Bytes
* 0b001101..Key Size is 104 Bytes and KC Size is 148 Bytes
* 0b001110..Key Size is 112 Bytes and KC Size is 148 Bytes
* 0b001111..Key Size is 120 Bytes and KC Size is 148 Bytes
* 0b010000..Key Size is 128 Bytes and KC Size is 148 Bytes
* 0b010001..Key Size is 136 Bytes and KC Size is 180 Bytes
* 0b010010..Key Size is 144 Bytes and KC Size is 180 Bytes
* 0b010011..Key Size is 152 Bytes and KC Size is 180 Bytes
* 0b010100..Key Size is 160 Bytes and KC Size is 180 Bytes
* 0b010101..Key Size is 168 Bytes and KC Size is 212 Bytes
* 0b010110..Key Size is 176 Bytes and KC Size is 212 Bytes
* 0b010111..Key Size is 184 Bytes and KC Size is 212 Bytes
* 0b011000..Key Size is 192 Bytes and KC Size is 212 Bytes
* 0b011001..Key Size is 200 Bytes and KC Size is 244 Bytes
* 0b011010..Key Size is 208 Bytes and KC Size is 244 Bytes
* 0b011011..Key Size is 216 Bytes and KC Size is 244 Bytes
* 0b011100..Key Size is 224 Bytes and KC Size is 244 Bytes
* 0b011101..Key Size is 232 Bytes and KC Size is 276 Bytes
* 0b011110..Key Size is 240 Bytes and KC Size is 276 Bytes
* 0b011111..Key Size is 248 Bytes and KC Size is 276 Bytes
* 0b100000..Key Size is 256 Bytes and KC Size is 276 Bytes
* 0b100001..Key Size is 264 Bytes and KC Size is 308 Bytes
* 0b100010..Key Size is 272 Bytes and KC Size is 308 Bytes
* 0b100011..Key Size is 280 Bytes and KC Size is 308 Bytes
* 0b100100..Key Size is 288 Bytes and KC Size is 308 Bytes
* 0b100101..Key Size is 296 Bytes and KC Size is 340 Bytes
* 0b100110..Key Size is 304 Bytes and KC Size is 340 Bytes
* 0b100111..Key Size is 312 Bytes and KC Size is 340 Bytes
* 0b101000..Key Size is 320 Bytes and KC Size is 340 Bytes
* 0b101001..Key Size is 328 Bytes and KC Size is 372 Bytes
* 0b101010..Key Size is 336 Bytes and KC Size is 372 Bytes
* 0b101011..Key Size is 344 Bytes and KC Size is 372 Bytes
* 0b101100..Key Size is 352 Bytes and KC Size is 372 Bytes
* 0b101101..Key Size is 360 Bytes and KC Size is 404 Bytes
* 0b101110..Key Size is 368 Bytes and KC Size is 404 Bytes
* 0b101111..Key Size is 376 Bytes and KC Size is 404 Bytes
* 0b110000..Key Size is 384 Bytes and KC Size is 404 Bytes
* 0b110001..Key Size is 392 Bytes and KC Size is 436 Bytes
* 0b110010..Key Size is 400 Bytes and KC Size is 436 Bytes
* 0b110011..Key Size is 408 Bytes and KC Size is 436 Bytes
* 0b110100..Key Size is 416 Bytes and KC Size is 436 Bytes
* 0b110101..Key Size is 424 Bytes and KC Size is 468 Bytes
* 0b110110..Key Size is 432 Bytes and KC Size is 468 Bytes
* 0b110111..Key Size is 440 Bytes and KC Size is 468 Bytes
* 0b111000..Key Size is 448 Bytes and KC Size is 468 Bytes
* 0b111001..Key Size is 456 Bytes and KC Size is 500 Bytes
* 0b111010..Key Size is 464 Bytes and KC Size is 500 Bytes
* 0b111011..Key Size is 472 Bytes and KC Size is 500 Bytes
* 0b111100..Key Size is 480 Bytes and KC Size is 500 Bytes
* 0b111101..Key Size is 488 Bytes and KC Size is 532 Bytes
* 0b111110..Key Size is 496 Bytes and KC Size is 532 Bytes
* 0b111111..Key Size is 504 Bytes and KC Size is 532 Bytes
* 0b000000..Key Size is 512 Bytes and KC Size is 532 Bytes
*/
#define PUF_KEYSIZE_KEYSIZE(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYSIZE_KEYSIZE_SHIFT)) & PUF_KEYSIZE_KEYSIZE_MASK)
/*! @} */
/*! @name STAT - PUF Status Register */
/*! @{ */
#define PUF_STAT_BUSY_MASK (0x1U)
#define PUF_STAT_BUSY_SHIFT (0U)
/*! BUSY - puf_busy
* 0b0..IDLE
* 0b1..BUSY
*/
#define PUF_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_BUSY_SHIFT)) & PUF_STAT_BUSY_MASK)
#define PUF_STAT_SUCCESS_MASK (0x2U)
#define PUF_STAT_SUCCESS_SHIFT (1U)
/*! SUCCESS - puf_ok
* 0b0..Last operation was unsuccessful
* 0b1..Last operation was successful
*/
#define PUF_STAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_SUCCESS_SHIFT)) & PUF_STAT_SUCCESS_MASK)
#define PUF_STAT_ERROR_MASK (0x4U)
#define PUF_STAT_ERROR_SHIFT (2U)
/*! ERROR - puf_error
* 0b0..PUF is not in the Error state
* 0b1..PUF is in the Error state
*/
#define PUF_STAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_ERROR_SHIFT)) & PUF_STAT_ERROR_MASK)
#define PUF_STAT_KEYINREQ_MASK (0x10U)
#define PUF_STAT_KEYINREQ_SHIFT (4U)
/*! KEYINREQ - KI_ir
* 0b0..No request for next part of key
* 0b1..Request for next part of key in KEYINPUT register
*/
#define PUF_STAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYINREQ_SHIFT)) & PUF_STAT_KEYINREQ_MASK)
#define PUF_STAT_KEYOUTAVAIL_MASK (0x20U)
#define PUF_STAT_KEYOUTAVAIL_SHIFT (5U)
/*! KEYOUTAVAIL - KO_or
* 0b0..Next part of key is not available
* 0b1..Next part of key is available in KEYOUTPUT register
*/
#define PUF_STAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_KEYOUTAVAIL_SHIFT)) & PUF_STAT_KEYOUTAVAIL_MASK)
#define PUF_STAT_CODEINREQ_MASK (0x40U)
#define PUF_STAT_CODEINREQ_SHIFT (6U)
/*! CODEINREQ - CI_ir
* 0b0..No request for next part of Activation Code/Key Code
* 0b1..request for next part of Activation Code/Key Code in CODEINPUT register
*/
#define PUF_STAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEINREQ_SHIFT)) & PUF_STAT_CODEINREQ_MASK)
#define PUF_STAT_CODEOUTAVAIL_MASK (0x80U)
#define PUF_STAT_CODEOUTAVAIL_SHIFT (7U)
/*! CODEOUTAVAIL - CO_or
* 0b0..Next part of Activation Code/Key Code is not available
* 0b1..Next part of Activation Code/Key Code is available in CODEOUTPUT register
*/
#define PUF_STAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_STAT_CODEOUTAVAIL_SHIFT)) & PUF_STAT_CODEOUTAVAIL_MASK)
/*! @} */
/*! @name ALLOW - PUF Allow Register */
/*! @{ */
#define PUF_ALLOW_ALLOWENROLL_MASK (0x1U)
#define PUF_ALLOW_ALLOWENROLL_SHIFT (0U)
/*! ALLOWENROLL - Allow Enroll operation
* 0b0..Specified operation is not currently allowed
* 0b1..Specified operation is allowed
*/
#define PUF_ALLOW_ALLOWENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWENROLL_SHIFT)) & PUF_ALLOW_ALLOWENROLL_MASK)
#define PUF_ALLOW_ALLOWSTART_MASK (0x2U)
#define PUF_ALLOW_ALLOWSTART_SHIFT (1U)
/*! ALLOWSTART - Allow Start operation
* 0b0..Specified operation is not currently allowed
* 0b1..Specified operation is allowed
*/
#define PUF_ALLOW_ALLOWSTART(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSTART_SHIFT)) & PUF_ALLOW_ALLOWSTART_MASK)
#define PUF_ALLOW_ALLOWSETKEY_MASK (0x4U)
#define PUF_ALLOW_ALLOWSETKEY_SHIFT (2U)
/*! ALLOWSETKEY - Allow Set Key operations
* 0b0..Specified operation is not currently allowed
* 0b1..Specified operation is allowed
*/
#define PUF_ALLOW_ALLOWSETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWSETKEY_SHIFT)) & PUF_ALLOW_ALLOWSETKEY_MASK)
#define PUF_ALLOW_ALLOWGETKEY_MASK (0x8U)
#define PUF_ALLOW_ALLOWGETKEY_SHIFT (3U)
/*! ALLOWGETKEY - Allow Get Key operation
* 0b0..Specified operation is not currently allowed
* 0b1..Specified operation is allowed
*/
#define PUF_ALLOW_ALLOWGETKEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_ALLOW_ALLOWGETKEY_SHIFT)) & PUF_ALLOW_ALLOWGETKEY_MASK)
/*! @} */
/*! @name KEYINPUT - PUF Key Input Register */
/*! @{ */
#define PUF_KEYINPUT_KEYIN_MASK (0xFFFFFFFFU)
#define PUF_KEYINPUT_KEYIN_SHIFT (0U)
/*! KEYIN - Key input data
*/
#define PUF_KEYINPUT_KEYIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYINPUT_KEYIN_SHIFT)) & PUF_KEYINPUT_KEYIN_MASK)
/*! @} */
/*! @name CODEINPUT - PUF Code Input Register */
/*! @{ */
#define PUF_CODEINPUT_CODEIN_MASK (0xFFFFFFFFU)
#define PUF_CODEINPUT_CODEIN_SHIFT (0U)
/*! CODEIN - AC/KC input data
*/
#define PUF_CODEINPUT_CODEIN(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEINPUT_CODEIN_SHIFT)) & PUF_CODEINPUT_CODEIN_MASK)
/*! @} */
/*! @name CODEOUTPUT - PUF Code Output Register */
/*! @{ */
#define PUF_CODEOUTPUT_CODEOUT_MASK (0xFFFFFFFFU)
#define PUF_CODEOUTPUT_CODEOUT_SHIFT (0U)
/*! CODEOUT - AC/KC output data
*/
#define PUF_CODEOUTPUT_CODEOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_CODEOUTPUT_CODEOUT_SHIFT)) & PUF_CODEOUTPUT_CODEOUT_MASK)
/*! @} */
/*! @name KEYOUTINDEX - PUF Key Output Index Register */
/*! @{ */
#define PUF_KEYOUTINDEX_KEYOUTIDX_MASK (0xFFFFFFFFU)
#define PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT (0U)
/*! KEYOUTIDX - Output Key index
*/
#define PUF_KEYOUTINDEX_KEYOUTIDX(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTINDEX_KEYOUTIDX_SHIFT)) & PUF_KEYOUTINDEX_KEYOUTIDX_MASK)
/*! @} */
/*! @name KEYOUTPUT - PUF Key Output Register */
/*! @{ */
#define PUF_KEYOUTPUT_KEYOUT_MASK (0xFFFFFFFFU)
#define PUF_KEYOUTPUT_KEYOUT_SHIFT (0U)
/*! KEYOUT - Key output data from a Get Key operation
*/
#define PUF_KEYOUTPUT_KEYOUT(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYOUTPUT_KEYOUT_SHIFT)) & PUF_KEYOUTPUT_KEYOUT_MASK)
/*! @} */
/*! @name IFSTAT - PUF Interface Status Register */
/*! @{ */
#define PUF_IFSTAT_ERROR_MASK (0x1U)
#define PUF_IFSTAT_ERROR_SHIFT (0U)
/*! ERROR - APB error has occurred
* 0b0..NOERROR
* 0b1..ERROR
*/
#define PUF_IFSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_IFSTAT_ERROR_SHIFT)) & PUF_IFSTAT_ERROR_MASK)
/*! @} */
/*! @name VERSION - PUF Version Register */
/*! @{ */
#define PUF_VERSION_VERSION_MASK (0xFFFFFFFFU)
#define PUF_VERSION_VERSION_SHIFT (0U)
/*! VERSION - Version of PUF
*/
#define PUF_VERSION_VERSION(x) (((uint32_t)(((uint32_t)(x)) << PUF_VERSION_VERSION_SHIFT)) & PUF_VERSION_VERSION_MASK)
/*! @} */
/*! @name INTEN - PUF Interrupt Enable */
/*! @{ */
#define PUF_INTEN_READYEN_MASK (0x1U)
#define PUF_INTEN_READYEN_SHIFT (0U)
/*! READYEN - PUF Ready Interrupt Enable
* 0b0..PUF ready interrupt disabled
* 0b1..PUF ready interrupt enabled
*/
#define PUF_INTEN_READYEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_READYEN_SHIFT)) & PUF_INTEN_READYEN_MASK)
#define PUF_INTEN_SUCCESSEN_MASK (0x2U)
#define PUF_INTEN_SUCCESSEN_SHIFT (1U)
/*! SUCCESSEN - PUF_OK Interrupt Enable
* 0b0..PUF successful interrupt disabled
* 0b1..PUF successful interrupt enabled
*/
#define PUF_INTEN_SUCCESSEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_SUCCESSEN_SHIFT)) & PUF_INTEN_SUCCESSEN_MASK)
#define PUF_INTEN_ERROREN_MASK (0x4U)
#define PUF_INTEN_ERROREN_SHIFT (2U)
/*! ERROREN - PUF Error Interrupt Enable
* 0b0..PUF error interrupt disabled
* 0b1..PUF error interrupt enabled
*/
#define PUF_INTEN_ERROREN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_ERROREN_SHIFT)) & PUF_INTEN_ERROREN_MASK)
#define PUF_INTEN_KEYINREQEN_MASK (0x10U)
#define PUF_INTEN_KEYINREQEN_SHIFT (4U)
/*! KEYINREQEN - PUF Key Input Register Interrupt Enable
* 0b0..Key interrupt request disabled
* 0b1..Key interrupt request enabled
*/
#define PUF_INTEN_KEYINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYINREQEN_SHIFT)) & PUF_INTEN_KEYINREQEN_MASK)
#define PUF_INTEN_KEYOUTAVAILEN_MASK (0x20U)
#define PUF_INTEN_KEYOUTAVAILEN_SHIFT (5U)
/*! KEYOUTAVAILEN - PUF Key Output Register Interrupt Enable
* 0b0..Key available interrupt disabled
* 0b1..Key available interrupt enabled
*/
#define PUF_INTEN_KEYOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_KEYOUTAVAILEN_SHIFT)) & PUF_INTEN_KEYOUTAVAILEN_MASK)
#define PUF_INTEN_CODEINREQEN_MASK (0x40U)
#define PUF_INTEN_CODEINREQEN_SHIFT (6U)
/*! CODEINREQEN - PUF Code Input Register Interrupt Enable
* 0b0..AC/KC interrupt request disabled
* 0b1..AC/KC interrupt request enabled
*/
#define PUF_INTEN_CODEINREQEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEINREQEN_SHIFT)) & PUF_INTEN_CODEINREQEN_MASK)
#define PUF_INTEN_CODEOUTAVAILEN_MASK (0x80U)
#define PUF_INTEN_CODEOUTAVAILEN_SHIFT (7U)
/*! CODEOUTAVAILEN - PUF Code Output Register Interrupt Enable
* 0b0..AC/KC available interrupt disabled
* 0b1..AC/KC available interrupt enabled
*/
#define PUF_INTEN_CODEOUTAVAILEN(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTEN_CODEOUTAVAILEN_SHIFT)) & PUF_INTEN_CODEOUTAVAILEN_MASK)
/*! @} */
/*! @name INTSTAT - PUF Interrupt Status */
/*! @{ */
#define PUF_INTSTAT_READY_MASK (0x1U)
#define PUF_INTSTAT_READY_SHIFT (0U)
/*! READY - PUF_FINISH Interrupt Status
* 0b0..Indicates that last operation not finished
* 0b1..Indicates that last operation is finished
*/
#define PUF_INTSTAT_READY(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_READY_SHIFT)) & PUF_INTSTAT_READY_MASK)
#define PUF_INTSTAT_SUCCESS_MASK (0x2U)
#define PUF_INTSTAT_SUCCESS_SHIFT (1U)
/*! SUCCESS - PUF_OK Interrupt Status
* 0b0..Indicates that last operation was not successful
* 0b1..Indicates that last operation was successful
*/
#define PUF_INTSTAT_SUCCESS(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_SUCCESS_SHIFT)) & PUF_INTSTAT_SUCCESS_MASK)
#define PUF_INTSTAT_ERROR_MASK (0x4U)
#define PUF_INTSTAT_ERROR_SHIFT (2U)
/*! ERROR - PUF_ERROR Interrupt Status
* 0b0..PUF is not in the Error state and operations can be performed
* 0b1..PUF is in the Error state and no operations can be performed
*/
#define PUF_INTSTAT_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_ERROR_SHIFT)) & PUF_INTSTAT_ERROR_MASK)
#define PUF_INTSTAT_KEYINREQ_MASK (0x10U)
#define PUF_INTSTAT_KEYINREQ_SHIFT (4U)
/*! KEYINREQ - PUF Key Input Register Interrupt Status
* 0b0..No request for next part of key
* 0b1..Request for next part of key
*/
#define PUF_INTSTAT_KEYINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYINREQ_SHIFT)) & PUF_INTSTAT_KEYINREQ_MASK)
#define PUF_INTSTAT_KEYOUTAVAIL_MASK (0x20U)
#define PUF_INTSTAT_KEYOUTAVAIL_SHIFT (5U)
/*! KEYOUTAVAIL - PUF Key Output Register Interrupt Status
* 0b0..Next part of key is not available
* 0b1..Next part of key is available
*/
#define PUF_INTSTAT_KEYOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_KEYOUTAVAIL_SHIFT)) & PUF_INTSTAT_KEYOUTAVAIL_MASK)
#define PUF_INTSTAT_CODEINREQ_MASK (0x40U)
#define PUF_INTSTAT_CODEINREQ_SHIFT (6U)
/*! CODEINREQ - PUF Code Input Register Interrupt Status
* 0b0..No request for next part of AC/KC
* 0b1..Request for next part of AC/KC
*/
#define PUF_INTSTAT_CODEINREQ(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEINREQ_SHIFT)) & PUF_INTSTAT_CODEINREQ_MASK)
#define PUF_INTSTAT_CODEOUTAVAIL_MASK (0x80U)
#define PUF_INTSTAT_CODEOUTAVAIL_SHIFT (7U)
/*! CODEOUTAVAIL - PUF Code Output Register Interrupt Status
* 0b0..Next part of AC/KC is not available
* 0b1..Next part of AC/KC is available
*/
#define PUF_INTSTAT_CODEOUTAVAIL(x) (((uint32_t)(((uint32_t)(x)) << PUF_INTSTAT_CODEOUTAVAIL_SHIFT)) & PUF_INTSTAT_CODEOUTAVAIL_MASK)
/*! @} */
/*! @name PWRCTRL - PUF Power Control Of RAM */
/*! @{ */
#define PUF_PWRCTRL_RAM_ON_MASK (0x1U)
#define PUF_PWRCTRL_RAM_ON_SHIFT (0U)
/*! RAM_ON - PUF RAM on
* 0b0..PUF RAM is in sleep mode (PUF operation disabled)
* 0b1..PUF RAM is awake (normal PUF operation enabled)
*/
#define PUF_PWRCTRL_RAM_ON(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_ON_SHIFT)) & PUF_PWRCTRL_RAM_ON_MASK)
#define PUF_PWRCTRL_CK_DIS_MASK (0x4U)
#define PUF_PWRCTRL_CK_DIS_SHIFT (2U)
/*! CK_DIS - Clock disable
* 0b0..PUF RAM is clocked (normal PUF operation enabled)
* 0b1..PUF RAM clock is gated/disabled (PUF operation disabled)
*/
#define PUF_PWRCTRL_CK_DIS(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_CK_DIS_SHIFT)) & PUF_PWRCTRL_CK_DIS_MASK)
#define PUF_PWRCTRL_RAM_INITN_MASK (0x8U)
#define PUF_PWRCTRL_RAM_INITN_SHIFT (3U)
/*! RAM_INITN - RAM initialization
* 0b0..Reset the PUF RAM (PUF operation disabled)
* 0b1..Do not reset the PUF RAM (normal PUF operation enabled)
*/
#define PUF_PWRCTRL_RAM_INITN(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_INITN_SHIFT)) & PUF_PWRCTRL_RAM_INITN_MASK)
#define PUF_PWRCTRL_RAM_PSW_MASK (0xF0U)
#define PUF_PWRCTRL_RAM_PSW_SHIFT (4U)
/*! RAM_PSW - PUF RAM power switches
*/
#define PUF_PWRCTRL_RAM_PSW(x) (((uint32_t)(((uint32_t)(x)) << PUF_PWRCTRL_RAM_PSW_SHIFT)) & PUF_PWRCTRL_RAM_PSW_MASK)
/*! @} */
/*! @name CFG - PUF Configuration Register */
/*! @{ */
#define PUF_CFG_PUF_BLOCK_SET_KEY_MASK (0x1U)
#define PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT (0U)
/*! PUF_BLOCK_SET_KEY - PUF Block Set Key Disable
* 0b0..Enable the Set Key state
* 0b1..Disable the Set Key state
*/
#define PUF_CFG_PUF_BLOCK_SET_KEY(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_SET_KEY_SHIFT)) & PUF_CFG_PUF_BLOCK_SET_KEY_MASK)
#define PUF_CFG_PUF_BLOCK_ENROLL_MASK (0x2U)
#define PUF_CFG_PUF_BLOCK_ENROLL_SHIFT (1U)
/*! PUF_BLOCK_ENROLL - PUF Block Enroll Disable
* 0b0..Enable the Enrollment state
* 0b1..Disable the Enrollment state
*/
#define PUF_CFG_PUF_BLOCK_ENROLL(x) (((uint32_t)(((uint32_t)(x)) << PUF_CFG_PUF_BLOCK_ENROLL_SHIFT)) & PUF_CFG_PUF_BLOCK_ENROLL_MASK)
/*! @} */
/*! @name KEYLOCK - PUF Key Manager Lock */
/*! @{ */
#define PUF_KEYLOCK_LOCK0_MASK (0x3U)
#define PUF_KEYLOCK_LOCK0_SHIFT (0U)
/*! LOCK0 - Lock Block 0
* 0b11..SNVS Key block locked
* 0b10..SNVS Key block unlocked
* 0b01..SNVS Key block locked
* 0b00..SNVS Key block locked
*/
#define PUF_KEYLOCK_LOCK0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK0_SHIFT)) & PUF_KEYLOCK_LOCK0_MASK)
#define PUF_KEYLOCK_LOCK1_MASK (0xCU)
#define PUF_KEYLOCK_LOCK1_SHIFT (2U)
/*! LOCK1 - Lock Block 1
* 0b11..OTFAD Key block locked
* 0b10..OTFAD Key block unlocked
* 0b01..OTFAD Key block locked
* 0b00..OTFAD Key block locked
*/
#define PUF_KEYLOCK_LOCK1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYLOCK_LOCK1_SHIFT)) & PUF_KEYLOCK_LOCK1_MASK)
/*! @} */
/*! @name KEYENABLE - PUF Key Manager Enable */
/*! @{ */
#define PUF_KEYENABLE_ENABLE0_MASK (0x3U)
#define PUF_KEYENABLE_ENABLE0_SHIFT (0U)
/*! ENABLE0 - Enable Block 0
* 0b11..Key block 0 disabled
* 0b10..Key block 0 enabled
* 0b01..Key block 0 disabled
* 0b00..Key block 0 disabled
*/
#define PUF_KEYENABLE_ENABLE0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE0_SHIFT)) & PUF_KEYENABLE_ENABLE0_MASK)
#define PUF_KEYENABLE_ENABLE1_MASK (0xCU)
#define PUF_KEYENABLE_ENABLE1_SHIFT (2U)
/*! ENABLE1 - Enable Block 1
* 0b11..Key block 1 disabled
* 0b10..Key block 1 enabled
* 0b01..Key block 1 disabled
* 0b00..Key block 1 disabled
*/
#define PUF_KEYENABLE_ENABLE1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYENABLE_ENABLE1_SHIFT)) & PUF_KEYENABLE_ENABLE1_MASK)
/*! @} */
/*! @name KEYRESET - PUF Key Manager Reset */
/*! @{ */
#define PUF_KEYRESET_RESET0_MASK (0x3U)
#define PUF_KEYRESET_RESET0_SHIFT (0U)
/*! RESET0 - Reset Block 0
* 0b11..Do not reset key block 0
* 0b10..Reset key block 0
* 0b01..Do not reset key block 0
* 0b00..Do not reset key block 0
*/
#define PUF_KEYRESET_RESET0(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET0_SHIFT)) & PUF_KEYRESET_RESET0_MASK)
#define PUF_KEYRESET_RESET1_MASK (0xCU)
#define PUF_KEYRESET_RESET1_SHIFT (2U)
/*! RESET1 - Reset Block 1
* 0b11..Do not reset key block 1
* 0b10..Reset key block 1
* 0b01..Do not reset key block 1
* 0b00..Do not reset key block 1
*/
#define PUF_KEYRESET_RESET1(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYRESET_RESET1_SHIFT)) & PUF_KEYRESET_RESET1_MASK)
/*! @} */
/*! @name IDXBLK - PUF Index Block Key Output */
/*! @{ */
#define PUF_IDXBLK_IDXBLK0_MASK (0x3U)
#define PUF_IDXBLK_IDXBLK0_SHIFT (0U)
/*! IDXBLK0 - idxblk0
*/
#define PUF_IDXBLK_IDXBLK0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK0_SHIFT)) & PUF_IDXBLK_IDXBLK0_MASK)
#define PUF_IDXBLK_IDXBLK1_MASK (0xCU)
#define PUF_IDXBLK_IDXBLK1_SHIFT (2U)
/*! IDXBLK1 - idxblk1
*/
#define PUF_IDXBLK_IDXBLK1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK1_SHIFT)) & PUF_IDXBLK_IDXBLK1_MASK)
#define PUF_IDXBLK_IDXBLK2_MASK (0x30U)
#define PUF_IDXBLK_IDXBLK2_SHIFT (4U)
/*! IDXBLK2 - idxblk2
*/
#define PUF_IDXBLK_IDXBLK2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK2_SHIFT)) & PUF_IDXBLK_IDXBLK2_MASK)
#define PUF_IDXBLK_IDXBLK3_MASK (0xC0U)
#define PUF_IDXBLK_IDXBLK3_SHIFT (6U)
/*! IDXBLK3 - idxblk3
*/
#define PUF_IDXBLK_IDXBLK3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK3_SHIFT)) & PUF_IDXBLK_IDXBLK3_MASK)
#define PUF_IDXBLK_IDXBLK4_MASK (0x300U)
#define PUF_IDXBLK_IDXBLK4_SHIFT (8U)
/*! IDXBLK4 - idxblk4
*/
#define PUF_IDXBLK_IDXBLK4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK4_SHIFT)) & PUF_IDXBLK_IDXBLK4_MASK)
#define PUF_IDXBLK_IDXBLK5_MASK (0xC00U)
#define PUF_IDXBLK_IDXBLK5_SHIFT (10U)
/*! IDXBLK5 - idxblk5
*/
#define PUF_IDXBLK_IDXBLK5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK5_SHIFT)) & PUF_IDXBLK_IDXBLK5_MASK)
#define PUF_IDXBLK_IDXBLK6_MASK (0x3000U)
#define PUF_IDXBLK_IDXBLK6_SHIFT (12U)
/*! IDXBLK6 - idxblk6
*/
#define PUF_IDXBLK_IDXBLK6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK6_SHIFT)) & PUF_IDXBLK_IDXBLK6_MASK)
#define PUF_IDXBLK_IDXBLK7_MASK (0xC000U)
#define PUF_IDXBLK_IDXBLK7_SHIFT (14U)
/*! IDXBLK7 - idxblk7
*/
#define PUF_IDXBLK_IDXBLK7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK7_SHIFT)) & PUF_IDXBLK_IDXBLK7_MASK)
#define PUF_IDXBLK_IDXBLK8_MASK (0x30000U)
#define PUF_IDXBLK_IDXBLK8_SHIFT (16U)
/*! IDXBLK8 - idxblk8
*/
#define PUF_IDXBLK_IDXBLK8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK8_SHIFT)) & PUF_IDXBLK_IDXBLK8_MASK)
#define PUF_IDXBLK_IDXBLK9_MASK (0xC0000U)
#define PUF_IDXBLK_IDXBLK9_SHIFT (18U)
/*! IDXBLK9 - idxblk9
*/
#define PUF_IDXBLK_IDXBLK9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK9_SHIFT)) & PUF_IDXBLK_IDXBLK9_MASK)
#define PUF_IDXBLK_IDXBLK10_MASK (0x300000U)
#define PUF_IDXBLK_IDXBLK10_SHIFT (20U)
/*! IDXBLK10 - idxblk10
*/
#define PUF_IDXBLK_IDXBLK10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK10_SHIFT)) & PUF_IDXBLK_IDXBLK10_MASK)
#define PUF_IDXBLK_IDXBLK11_MASK (0xC00000U)
#define PUF_IDXBLK_IDXBLK11_SHIFT (22U)
/*! IDXBLK11 - idxblk11
*/
#define PUF_IDXBLK_IDXBLK11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK11_SHIFT)) & PUF_IDXBLK_IDXBLK11_MASK)
#define PUF_IDXBLK_IDXBLK12_MASK (0x3000000U)
#define PUF_IDXBLK_IDXBLK12_SHIFT (24U)
/*! IDXBLK12 - idxblk12
*/
#define PUF_IDXBLK_IDXBLK12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK12_SHIFT)) & PUF_IDXBLK_IDXBLK12_MASK)
#define PUF_IDXBLK_IDXBLK13_MASK (0xC000000U)
#define PUF_IDXBLK_IDXBLK13_SHIFT (26U)
/*! IDXBLK13 - idxblk13
*/
#define PUF_IDXBLK_IDXBLK13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK13_SHIFT)) & PUF_IDXBLK_IDXBLK13_MASK)
#define PUF_IDXBLK_IDXBLK14_MASK (0x30000000U)
#define PUF_IDXBLK_IDXBLK14_SHIFT (28U)
/*! IDXBLK14 - idxblk14
*/
#define PUF_IDXBLK_IDXBLK14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK14_SHIFT)) & PUF_IDXBLK_IDXBLK14_MASK)
#define PUF_IDXBLK_IDXBLK15_MASK (0xC0000000U)
#define PUF_IDXBLK_IDXBLK15_SHIFT (30U)
/*! IDXBLK15 - idxblk15
*/
#define PUF_IDXBLK_IDXBLK15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_IDXBLK15_SHIFT)) & PUF_IDXBLK_IDXBLK15_MASK)
/*! @} */
/*! @name IDXBLK_DP - PUF Index Block Key Output */
/*! @{ */
#define PUF_IDXBLK_DP_IDXBLK_DP0_MASK (0x3U)
#define PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT (0U)
/*! IDXBLK_DP0 - idxblk_dp0
*/
#define PUF_IDXBLK_DP_IDXBLK_DP0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP0_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP0_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP1_MASK (0xCU)
#define PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT (2U)
/*! IDXBLK_DP1 - idxblk_dp1
*/
#define PUF_IDXBLK_DP_IDXBLK_DP1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP1_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP1_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP2_MASK (0x30U)
#define PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT (4U)
/*! IDXBLK_DP2 - idxblk_dp2
*/
#define PUF_IDXBLK_DP_IDXBLK_DP2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP2_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP2_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP3_MASK (0xC0U)
#define PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT (6U)
/*! IDXBLK_DP3 - idxblk_dp3
*/
#define PUF_IDXBLK_DP_IDXBLK_DP3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP3_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP3_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP4_MASK (0x300U)
#define PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT (8U)
/*! IDXBLK_DP4 - idxblk_dp4
*/
#define PUF_IDXBLK_DP_IDXBLK_DP4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP4_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP4_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP5_MASK (0xC00U)
#define PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT (10U)
/*! IDXBLK_DP5 - idxblk_dp5
*/
#define PUF_IDXBLK_DP_IDXBLK_DP5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP5_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP5_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP6_MASK (0x3000U)
#define PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT (12U)
/*! IDXBLK_DP6 - idxblk_dp6
*/
#define PUF_IDXBLK_DP_IDXBLK_DP6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP6_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP6_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP7_MASK (0xC000U)
#define PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT (14U)
/*! IDXBLK_DP7 - idxblk_dp7
*/
#define PUF_IDXBLK_DP_IDXBLK_DP7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP7_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP7_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP8_MASK (0x30000U)
#define PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT (16U)
/*! IDXBLK_DP8 - idxblk_dp8
*/
#define PUF_IDXBLK_DP_IDXBLK_DP8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP8_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP8_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP9_MASK (0xC0000U)
#define PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT (18U)
/*! IDXBLK_DP9 - idxblk_dp9
*/
#define PUF_IDXBLK_DP_IDXBLK_DP9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP9_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP9_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP10_MASK (0x300000U)
#define PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT (20U)
/*! IDXBLK_DP10 - idxblk_dp10
*/
#define PUF_IDXBLK_DP_IDXBLK_DP10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP10_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP10_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP11_MASK (0xC00000U)
#define PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT (22U)
/*! IDXBLK_DP11 - idxblk_dp11
*/
#define PUF_IDXBLK_DP_IDXBLK_DP11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP11_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP11_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP12_MASK (0x3000000U)
#define PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT (24U)
/*! IDXBLK_DP12 - idxblk_dp12
*/
#define PUF_IDXBLK_DP_IDXBLK_DP12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP12_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP12_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP13_MASK (0xC000000U)
#define PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT (26U)
/*! IDXBLK_DP13 - idxblk_dp13
*/
#define PUF_IDXBLK_DP_IDXBLK_DP13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP13_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP13_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP14_MASK (0x30000000U)
#define PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT (28U)
/*! IDXBLK_DP14 - idxblk_dp14
*/
#define PUF_IDXBLK_DP_IDXBLK_DP14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP14_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP14_MASK)
#define PUF_IDXBLK_DP_IDXBLK_DP15_MASK (0xC0000000U)
#define PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT (30U)
/*! IDXBLK_DP15 - idxblk_dp15
*/
#define PUF_IDXBLK_DP_IDXBLK_DP15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_DP_IDXBLK_DP15_SHIFT)) & PUF_IDXBLK_DP_IDXBLK_DP15_MASK)
/*! @} */
/*! @name KEYMASK - PUF Key Block 0 Mask Enable..PUF Key Block 1 Mask Enable */
/*! @{ */
#define PUF_KEYMASK_KEYMASK_MASK (0xFFFFFFFFU)
#define PUF_KEYMASK_KEYMASK_SHIFT (0U)
/*! KEYMASK - KEYMASK1
*/
#define PUF_KEYMASK_KEYMASK(x) (((uint32_t)(((uint32_t)(x)) << PUF_KEYMASK_KEYMASK_SHIFT)) & PUF_KEYMASK_KEYMASK_MASK)
/*! @} */
/* The count of PUF_KEYMASK */
#define PUF_KEYMASK_COUNT (2U)
/*! @name IDXBLK_STATUS - PUF Index Block Setting Status Register */
/*! @{ */
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK (0x3U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT (0U)
/*! IDXBLK_STATUS0 - idxblk_status0
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS0_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS0_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK (0xCU)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT (2U)
/*! IDXBLK_STATUS1 - idxblk_status1
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS1_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS1_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK (0x30U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT (4U)
/*! IDXBLK_STATUS2 - idxblk_status2
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS2(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS2_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS2_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK (0xC0U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT (6U)
/*! IDXBLK_STATUS3 - idxblk_status3
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS3(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS3_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS3_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK (0x300U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT (8U)
/*! IDXBLK_STATUS4 - idxblk_status4
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS4(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS4_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS4_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK (0xC00U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT (10U)
/*! IDXBLK_STATUS5 - idxblk_status5
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS5(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS5_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS5_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK (0x3000U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT (12U)
/*! IDXBLK_STATUS6 - idxblk_status6
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS6(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS6_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS6_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK (0xC000U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT (14U)
/*! IDXBLK_STATUS7 - idxblk_status7
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS7(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS7_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS7_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK (0x30000U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT (16U)
/*! IDXBLK_STATUS8 - idxblk_status8
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS8(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS8_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS8_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK (0xC0000U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT (18U)
/*! IDXBLK_STATUS9 - idxblk_status9
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS9(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS9_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS9_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK (0x300000U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT (20U)
/*! IDXBLK_STATUS10 - idxblk_status10
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS10(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS10_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS10_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK (0xC00000U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT (22U)
/*! IDXBLK_STATUS11 - idxblk_status11
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS11(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS11_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS11_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK (0x3000000U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT (24U)
/*! IDXBLK_STATUS12 - idxblk_status12
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS12(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS12_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS12_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK (0xC000000U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT (26U)
/*! IDXBLK_STATUS13 - idxblk_status13
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS13(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS13_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS13_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK (0x30000000U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT (28U)
/*! IDXBLK_STATUS14 - idxblk_status14
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS14(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS14_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS14_MASK)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK (0xC0000000U)
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT (30U)
/*! IDXBLK_STATUS15 - idxblk_status15
*/
#define PUF_IDXBLK_STATUS_IDXBLK_STATUS15(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_STATUS_IDXBLK_STATUS15_SHIFT)) & PUF_IDXBLK_STATUS_IDXBLK_STATUS15_MASK)
/*! @} */
/*! @name IDXBLK_SHIFT - PUF Key Manager Shift Status */
/*! @{ */
#define PUF_IDXBLK_SHIFT_IND_KEY0_MASK (0xFU)
#define PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT (0U)
/*! IND_KEY0 - Index of key space in block 0
*/
#define PUF_IDXBLK_SHIFT_IND_KEY0(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY0_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY0_MASK)
#define PUF_IDXBLK_SHIFT_IND_KEY1_MASK (0xF0U)
#define PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT (4U)
/*! IND_KEY1 - Index of key space in block 1
*/
#define PUF_IDXBLK_SHIFT_IND_KEY1(x) (((uint32_t)(((uint32_t)(x)) << PUF_IDXBLK_SHIFT_IND_KEY1_SHIFT)) & PUF_IDXBLK_SHIFT_IND_KEY1_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PUF_Register_Masks */
/* PUF - Peripheral instance base addresses */
/** Peripheral KEY_MANAGER__PUF base address */
#define KEY_MANAGER__PUF_BASE (0x40C82000u)
/** Peripheral KEY_MANAGER__PUF base pointer */
#define KEY_MANAGER__PUF ((PUF_Type *)KEY_MANAGER__PUF_BASE)
/** Array initializer of PUF peripheral base addresses */
#define PUF_BASE_ADDRS { KEY_MANAGER__PUF_BASE }
/** Array initializer of PUF peripheral base pointers */
#define PUF_BASE_PTRS { KEY_MANAGER__PUF }
/*!
* @}
*/ /* end of group PUF_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PWM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PWM_Peripheral_Access_Layer PWM Peripheral Access Layer
* @{
*/
/** PWM - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x60 */
__I uint16_t CNT; /**< Counter Register, array offset: 0x0, array step: 0x60 */
__IO uint16_t INIT; /**< Initial Count Register, array offset: 0x2, array step: 0x60 */
__IO uint16_t CTRL2; /**< Control 2 Register, array offset: 0x4, array step: 0x60 */
__IO uint16_t CTRL; /**< Control Register, array offset: 0x6, array step: 0x60 */
uint8_t RESERVED_0[2];
__IO uint16_t VAL0; /**< Value Register 0, array offset: 0xA, array step: 0x60 */
__IO uint16_t FRACVAL1; /**< Fractional Value Register 1, array offset: 0xC, array step: 0x60 */
__IO uint16_t VAL1; /**< Value Register 1, array offset: 0xE, array step: 0x60 */
__IO uint16_t FRACVAL2; /**< Fractional Value Register 2, array offset: 0x10, array step: 0x60 */
__IO uint16_t VAL2; /**< Value Register 2, array offset: 0x12, array step: 0x60 */
__IO uint16_t FRACVAL3; /**< Fractional Value Register 3, array offset: 0x14, array step: 0x60 */
__IO uint16_t VAL3; /**< Value Register 3, array offset: 0x16, array step: 0x60 */
__IO uint16_t FRACVAL4; /**< Fractional Value Register 4, array offset: 0x18, array step: 0x60 */
__IO uint16_t VAL4; /**< Value Register 4, array offset: 0x1A, array step: 0x60 */
__IO uint16_t FRACVAL5; /**< Fractional Value Register 5, array offset: 0x1C, array step: 0x60 */
__IO uint16_t VAL5; /**< Value Register 5, array offset: 0x1E, array step: 0x60 */
__IO uint16_t FRCTRL; /**< Fractional Control Register, array offset: 0x20, array step: 0x60 */
__IO uint16_t OCTRL; /**< Output Control Register, array offset: 0x22, array step: 0x60 */
__IO uint16_t STS; /**< Status Register, array offset: 0x24, array step: 0x60 */
__IO uint16_t INTEN; /**< Interrupt Enable Register, array offset: 0x26, array step: 0x60 */
__IO uint16_t DMAEN; /**< DMA Enable Register, array offset: 0x28, array step: 0x60 */
__IO uint16_t TCTRL; /**< Output Trigger Control Register, array offset: 0x2A, array step: 0x60 */
__IO uint16_t DISMAP[1]; /**< Fault Disable Mapping Register 0, array offset: 0x2C, array step: index*0x60, index2*0x2 */
uint8_t RESERVED_1[2];
__IO uint16_t DTCNT0; /**< Deadtime Count Register 0, array offset: 0x30, array step: 0x60 */
__IO uint16_t DTCNT1; /**< Deadtime Count Register 1, array offset: 0x32, array step: 0x60 */
__IO uint16_t CAPTCTRLA; /**< Capture Control A Register, array offset: 0x34, array step: 0x60 */
__IO uint16_t CAPTCOMPA; /**< Capture Compare A Register, array offset: 0x36, array step: 0x60 */
__IO uint16_t CAPTCTRLB; /**< Capture Control B Register, array offset: 0x38, array step: 0x60 */
__IO uint16_t CAPTCOMPB; /**< Capture Compare B Register, array offset: 0x3A, array step: 0x60 */
__IO uint16_t CAPTCTRLX; /**< Capture Control X Register, array offset: 0x3C, array step: 0x60 */
__IO uint16_t CAPTCOMPX; /**< Capture Compare X Register, array offset: 0x3E, array step: 0x60 */
__I uint16_t CVAL0; /**< Capture Value 0 Register, array offset: 0x40, array step: 0x60 */
__I uint16_t CVAL0CYC; /**< Capture Value 0 Cycle Register, array offset: 0x42, array step: 0x60 */
__I uint16_t CVAL1; /**< Capture Value 1 Register, array offset: 0x44, array step: 0x60 */
__I uint16_t CVAL1CYC; /**< Capture Value 1 Cycle Register, array offset: 0x46, array step: 0x60 */
__I uint16_t CVAL2; /**< Capture Value 2 Register, array offset: 0x48, array step: 0x60 */
__I uint16_t CVAL2CYC; /**< Capture Value 2 Cycle Register, array offset: 0x4A, array step: 0x60 */
__I uint16_t CVAL3; /**< Capture Value 3 Register, array offset: 0x4C, array step: 0x60 */
__I uint16_t CVAL3CYC; /**< Capture Value 3 Cycle Register, array offset: 0x4E, array step: 0x60 */
__I uint16_t CVAL4; /**< Capture Value 4 Register, array offset: 0x50, array step: 0x60 */
__I uint16_t CVAL4CYC; /**< Capture Value 4 Cycle Register, array offset: 0x52, array step: 0x60 */
__I uint16_t CVAL5; /**< Capture Value 5 Register, array offset: 0x54, array step: 0x60 */
__I uint16_t CVAL5CYC; /**< Capture Value 5 Cycle Register, array offset: 0x56, array step: 0x60 */
uint8_t RESERVED_2[8];
} SM[4];
__IO uint16_t OUTEN; /**< Output Enable Register, offset: 0x180 */
__IO uint16_t MASK; /**< Mask Register, offset: 0x182 */
__IO uint16_t SWCOUT; /**< Software Controlled Output Register, offset: 0x184 */
__IO uint16_t DTSRCSEL; /**< PWM Source Select Register, offset: 0x186 */
__IO uint16_t MCTRL; /**< Master Control Register, offset: 0x188 */
__IO uint16_t MCTRL2; /**< Master Control 2 Register, offset: 0x18A */
__IO uint16_t FCTRL; /**< Fault Control Register, offset: 0x18C */
__IO uint16_t FSTS; /**< Fault Status Register, offset: 0x18E */
__IO uint16_t FFILT; /**< Fault Filter Register, offset: 0x190 */
__IO uint16_t FTST; /**< Fault Test Register, offset: 0x192 */
__IO uint16_t FCTRL2; /**< Fault Control 2 Register, offset: 0x194 */
} PWM_Type;
/* ----------------------------------------------------------------------------
-- PWM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PWM_Register_Masks PWM Register Masks
* @{
*/
/*! @name CNT - Counter Register */
/*! @{ */
#define PWM_CNT_CNT_MASK (0xFFFFU)
#define PWM_CNT_CNT_SHIFT (0U)
/*! CNT - Counter Register Bits
*/
#define PWM_CNT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CNT_CNT_SHIFT)) & PWM_CNT_CNT_MASK)
/*! @} */
/* The count of PWM_CNT */
#define PWM_CNT_COUNT (4U)
/*! @name INIT - Initial Count Register */
/*! @{ */
#define PWM_INIT_INIT_MASK (0xFFFFU)
#define PWM_INIT_INIT_SHIFT (0U)
/*! INIT - Initial Count Register Bits
*/
#define PWM_INIT_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_INIT_INIT_SHIFT)) & PWM_INIT_INIT_MASK)
/*! @} */
/* The count of PWM_INIT */
#define PWM_INIT_COUNT (4U)
/*! @name CTRL2 - Control 2 Register */
/*! @{ */
#define PWM_CTRL2_CLK_SEL_MASK (0x3U)
#define PWM_CTRL2_CLK_SEL_SHIFT (0U)
/*! CLK_SEL - Clock Source Select
* 0b00..The IPBus clock is used as the clock for the local prescaler and counter.
* 0b01..EXT_CLK is used as the clock for the local prescaler and counter.
* 0b10..Submodule 0's clock (AUX_CLK) is used as the source clock for the local prescaler and counter. This
* setting should not be used in submodule 0 as it will force the clock to logic 0.
* 0b11..reserved
*/
#define PWM_CTRL2_CLK_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_CLK_SEL_SHIFT)) & PWM_CTRL2_CLK_SEL_MASK)
#define PWM_CTRL2_RELOAD_SEL_MASK (0x4U)
#define PWM_CTRL2_RELOAD_SEL_SHIFT (2U)
/*! RELOAD_SEL - Reload Source Select
* 0b0..The local RELOAD signal is used to reload registers.
* 0b1..The master RELOAD signal (from submodule 0) is used to reload registers. This setting should not be used
* in submodule 0 as it will force the RELOAD signal to logic 0.
*/
#define PWM_CTRL2_RELOAD_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_RELOAD_SEL_SHIFT)) & PWM_CTRL2_RELOAD_SEL_MASK)
#define PWM_CTRL2_FORCE_SEL_MASK (0x38U)
#define PWM_CTRL2_FORCE_SEL_SHIFT (3U)
/*! FORCE_SEL - This read/write bit determines the source of the FORCE OUTPUT signal for this submodule.
* 0b000..The local force signal, CTRL2[FORCE], from this submodule is used to force updates.
* 0b001..The master force signal from submodule 0 is used to force updates. This setting should not be used in
* submodule 0 as it will hold the FORCE OUTPUT signal to logic 0.
* 0b010..The local reload signal from this submodule is used to force updates without regard to the state of LDOK.
* 0b011..The master reload signal from submodule0 is used to force updates if LDOK is set. This setting should
* not be used in submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
* 0b100..The local sync signal from this submodule is used to force updates.
* 0b101..The master sync signal from submodule0 is used to force updates. This setting should not be used in
* submodule0 as it will hold the FORCE OUTPUT signal to logic 0.
* 0b110..The external force signal, EXT_FORCE, from outside the PWM module causes updates.
* 0b111..The external sync signal, EXT_SYNC, from outside the PWM module causes updates.
*/
#define PWM_CTRL2_FORCE_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SEL_SHIFT)) & PWM_CTRL2_FORCE_SEL_MASK)
#define PWM_CTRL2_FORCE_MASK (0x40U)
#define PWM_CTRL2_FORCE_SHIFT (6U)
/*! FORCE - Force Initialization
*/
#define PWM_CTRL2_FORCE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FORCE_SHIFT)) & PWM_CTRL2_FORCE_MASK)
#define PWM_CTRL2_FRCEN_MASK (0x80U)
#define PWM_CTRL2_FRCEN_SHIFT (7U)
/*! FRCEN - FRCEN
* 0b0..Initialization from a FORCE_OUT is disabled.
* 0b1..Initialization from a FORCE_OUT is enabled.
*/
#define PWM_CTRL2_FRCEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_FRCEN_SHIFT)) & PWM_CTRL2_FRCEN_MASK)
#define PWM_CTRL2_INIT_SEL_MASK (0x300U)
#define PWM_CTRL2_INIT_SEL_SHIFT (8U)
/*! INIT_SEL - Initialization Control Select
* 0b00..Local sync (PWM_X) causes initialization.
* 0b01..Master reload from submodule 0 causes initialization. This setting should not be used in submodule 0 as
* it will force the INIT signal to logic 0. The submodule counter will only reinitialize when a master
* reload occurs.
* 0b10..Master sync from submodule 0 causes initialization. This setting should not be used in submodule 0 as it
* will force the INIT signal to logic 0.
* 0b11..EXT_SYNC causes initialization.
*/
#define PWM_CTRL2_INIT_SEL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INIT_SEL_SHIFT)) & PWM_CTRL2_INIT_SEL_MASK)
#define PWM_CTRL2_PWMX_INIT_MASK (0x400U)
#define PWM_CTRL2_PWMX_INIT_SHIFT (10U)
/*! PWMX_INIT - PWM_X Initial Value
*/
#define PWM_CTRL2_PWMX_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWMX_INIT_SHIFT)) & PWM_CTRL2_PWMX_INIT_MASK)
#define PWM_CTRL2_PWM45_INIT_MASK (0x800U)
#define PWM_CTRL2_PWM45_INIT_SHIFT (11U)
/*! PWM45_INIT - PWM45 Initial Value
*/
#define PWM_CTRL2_PWM45_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM45_INIT_SHIFT)) & PWM_CTRL2_PWM45_INIT_MASK)
#define PWM_CTRL2_PWM23_INIT_MASK (0x1000U)
#define PWM_CTRL2_PWM23_INIT_SHIFT (12U)
/*! PWM23_INIT - PWM23 Initial Value
*/
#define PWM_CTRL2_PWM23_INIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_PWM23_INIT_SHIFT)) & PWM_CTRL2_PWM23_INIT_MASK)
#define PWM_CTRL2_INDEP_MASK (0x2000U)
#define PWM_CTRL2_INDEP_SHIFT (13U)
/*! INDEP - Independent or Complementary Pair Operation
* 0b0..PWM_A and PWM_B form a complementary PWM pair.
* 0b1..PWM_A and PWM_B outputs are independent PWMs.
*/
#define PWM_CTRL2_INDEP(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_INDEP_SHIFT)) & PWM_CTRL2_INDEP_MASK)
#define PWM_CTRL2_WAITEN_MASK (0x4000U)
#define PWM_CTRL2_WAITEN_SHIFT (14U)
/*! WAITEN - WAIT Enable
*/
#define PWM_CTRL2_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_WAITEN_SHIFT)) & PWM_CTRL2_WAITEN_MASK)
#define PWM_CTRL2_DBGEN_MASK (0x8000U)
#define PWM_CTRL2_DBGEN_SHIFT (15U)
/*! DBGEN - Debug Enable
*/
#define PWM_CTRL2_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL2_DBGEN_SHIFT)) & PWM_CTRL2_DBGEN_MASK)
/*! @} */
/* The count of PWM_CTRL2 */
#define PWM_CTRL2_COUNT (4U)
/*! @name CTRL - Control Register */
/*! @{ */
#define PWM_CTRL_DBLEN_MASK (0x1U)
#define PWM_CTRL_DBLEN_SHIFT (0U)
/*! DBLEN - Double Switching Enable
* 0b0..Double switching disabled.
* 0b1..Double switching enabled.
*/
#define PWM_CTRL_DBLEN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLEN_SHIFT)) & PWM_CTRL_DBLEN_MASK)
#define PWM_CTRL_DBLX_MASK (0x2U)
#define PWM_CTRL_DBLX_SHIFT (1U)
/*! DBLX - PWMX Double Switching Enable
* 0b0..PWMX double pulse disabled.
* 0b1..PWMX double pulse enabled.
*/
#define PWM_CTRL_DBLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DBLX_SHIFT)) & PWM_CTRL_DBLX_MASK)
#define PWM_CTRL_LDMOD_MASK (0x4U)
#define PWM_CTRL_LDMOD_SHIFT (2U)
/*! LDMOD - Load Mode Select
* 0b0..Buffered registers of this submodule are loaded and take effect at the next PWM reload if MCTRL[LDOK] is set.
* 0b1..Buffered registers of this submodule are loaded and take effect immediately upon MCTRL[LDOK] being set.
* In this case it is not necessary to set CTRL[FULL] or CTRL[HALF].
*/
#define PWM_CTRL_LDMOD(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDMOD_SHIFT)) & PWM_CTRL_LDMOD_MASK)
#define PWM_CTRL_SPLIT_MASK (0x8U)
#define PWM_CTRL_SPLIT_SHIFT (3U)
/*! SPLIT - Split the DBLPWM signal to PWMA and PWMB
* 0b0..DBLPWM is not split. PWMA and PWMB each have double pulses.
* 0b1..DBLPWM is split to PWMA and PWMB.
*/
#define PWM_CTRL_SPLIT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_SPLIT_SHIFT)) & PWM_CTRL_SPLIT_MASK)
#define PWM_CTRL_PRSC_MASK (0x70U)
#define PWM_CTRL_PRSC_SHIFT (4U)
/*! PRSC - Prescaler
* 0b000..Prescaler 1
* 0b001..Prescaler 2
* 0b010..Prescaler 4
* 0b011..Prescaler 8
* 0b100..Prescaler 16
* 0b101..Prescaler 32
* 0b110..Prescaler 64
* 0b111..Prescaler 128
*/
#define PWM_CTRL_PRSC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_PRSC_SHIFT)) & PWM_CTRL_PRSC_MASK)
#define PWM_CTRL_COMPMODE_MASK (0x80U)
#define PWM_CTRL_COMPMODE_SHIFT (7U)
/*! COMPMODE - Compare Mode
* 0b0..The VAL* registers and the PWM counter are compared using an "equal to" method. This means that PWM edges
* are only produced when the counter is equal to one of the VAL* register values. This implies that a PWMA
* output that is high at the end of a period will maintain this state until a match with VAL3 clears the
* output in the following period.
* 0b1..The VAL* registers and the PWM counter are compared using an "equal to or greater than" method. This
* means that PWM edges are produced when the counter is equal to or greater than one of the VAL* register
* values. This implies that a PWMA output that is high at the end of a period could go low at the start of the
* next period if the starting counter value is greater than (but not necessarily equal to) the new VAL3 value.
*/
#define PWM_CTRL_COMPMODE(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_COMPMODE_SHIFT)) & PWM_CTRL_COMPMODE_MASK)
#define PWM_CTRL_DT_MASK (0x300U)
#define PWM_CTRL_DT_SHIFT (8U)
/*! DT - Deadtime
*/
#define PWM_CTRL_DT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_DT_SHIFT)) & PWM_CTRL_DT_MASK)
#define PWM_CTRL_FULL_MASK (0x400U)
#define PWM_CTRL_FULL_SHIFT (10U)
/*! FULL - Full Cycle Reload
* 0b0..Full-cycle reloads disabled.
* 0b1..Full-cycle reloads enabled.
*/
#define PWM_CTRL_FULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_FULL_SHIFT)) & PWM_CTRL_FULL_MASK)
#define PWM_CTRL_HALF_MASK (0x800U)
#define PWM_CTRL_HALF_SHIFT (11U)
/*! HALF - Half Cycle Reload
* 0b0..Half-cycle reloads disabled.
* 0b1..Half-cycle reloads enabled.
*/
#define PWM_CTRL_HALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_HALF_SHIFT)) & PWM_CTRL_HALF_MASK)
#define PWM_CTRL_LDFQ_MASK (0xF000U)
#define PWM_CTRL_LDFQ_SHIFT (12U)
/*! LDFQ - Load Frequency
* 0b0000..Every PWM opportunity
* 0b0001..Every 2 PWM opportunities
* 0b0010..Every 3 PWM opportunities
* 0b0011..Every 4 PWM opportunities
* 0b0100..Every 5 PWM opportunities
* 0b0101..Every 6 PWM opportunities
* 0b0110..Every 7 PWM opportunities
* 0b0111..Every 8 PWM opportunities
* 0b1000..Every 9 PWM opportunities
* 0b1001..Every 10 PWM opportunities
* 0b1010..Every 11 PWM opportunities
* 0b1011..Every 12 PWM opportunities
* 0b1100..Every 13 PWM opportunities
* 0b1101..Every 14 PWM opportunities
* 0b1110..Every 15 PWM opportunities
* 0b1111..Every 16 PWM opportunities
*/
#define PWM_CTRL_LDFQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_CTRL_LDFQ_SHIFT)) & PWM_CTRL_LDFQ_MASK)
/*! @} */
/* The count of PWM_CTRL */
#define PWM_CTRL_COUNT (4U)
/*! @name VAL0 - Value Register 0 */
/*! @{ */
#define PWM_VAL0_VAL0_MASK (0xFFFFU)
#define PWM_VAL0_VAL0_SHIFT (0U)
/*! VAL0 - Value Register 0
*/
#define PWM_VAL0_VAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL0_VAL0_SHIFT)) & PWM_VAL0_VAL0_MASK)
/*! @} */
/* The count of PWM_VAL0 */
#define PWM_VAL0_COUNT (4U)
/*! @name FRACVAL1 - Fractional Value Register 1 */
/*! @{ */
#define PWM_FRACVAL1_FRACVAL1_MASK (0xF800U)
#define PWM_FRACVAL1_FRACVAL1_SHIFT (11U)
/*! FRACVAL1 - Fractional Value 1 Register
*/
#define PWM_FRACVAL1_FRACVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL1_FRACVAL1_SHIFT)) & PWM_FRACVAL1_FRACVAL1_MASK)
/*! @} */
/* The count of PWM_FRACVAL1 */
#define PWM_FRACVAL1_COUNT (4U)
/*! @name VAL1 - Value Register 1 */
/*! @{ */
#define PWM_VAL1_VAL1_MASK (0xFFFFU)
#define PWM_VAL1_VAL1_SHIFT (0U)
/*! VAL1 - Value Register 1
*/
#define PWM_VAL1_VAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL1_VAL1_SHIFT)) & PWM_VAL1_VAL1_MASK)
/*! @} */
/* The count of PWM_VAL1 */
#define PWM_VAL1_COUNT (4U)
/*! @name FRACVAL2 - Fractional Value Register 2 */
/*! @{ */
#define PWM_FRACVAL2_FRACVAL2_MASK (0xF800U)
#define PWM_FRACVAL2_FRACVAL2_SHIFT (11U)
/*! FRACVAL2 - Fractional Value 2
*/
#define PWM_FRACVAL2_FRACVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL2_FRACVAL2_SHIFT)) & PWM_FRACVAL2_FRACVAL2_MASK)
/*! @} */
/* The count of PWM_FRACVAL2 */
#define PWM_FRACVAL2_COUNT (4U)
/*! @name VAL2 - Value Register 2 */
/*! @{ */
#define PWM_VAL2_VAL2_MASK (0xFFFFU)
#define PWM_VAL2_VAL2_SHIFT (0U)
/*! VAL2 - Value Register 2
*/
#define PWM_VAL2_VAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL2_VAL2_SHIFT)) & PWM_VAL2_VAL2_MASK)
/*! @} */
/* The count of PWM_VAL2 */
#define PWM_VAL2_COUNT (4U)
/*! @name FRACVAL3 - Fractional Value Register 3 */
/*! @{ */
#define PWM_FRACVAL3_FRACVAL3_MASK (0xF800U)
#define PWM_FRACVAL3_FRACVAL3_SHIFT (11U)
/*! FRACVAL3 - Fractional Value 3
*/
#define PWM_FRACVAL3_FRACVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL3_FRACVAL3_SHIFT)) & PWM_FRACVAL3_FRACVAL3_MASK)
/*! @} */
/* The count of PWM_FRACVAL3 */
#define PWM_FRACVAL3_COUNT (4U)
/*! @name VAL3 - Value Register 3 */
/*! @{ */
#define PWM_VAL3_VAL3_MASK (0xFFFFU)
#define PWM_VAL3_VAL3_SHIFT (0U)
/*! VAL3 - Value Register 3
*/
#define PWM_VAL3_VAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL3_VAL3_SHIFT)) & PWM_VAL3_VAL3_MASK)
/*! @} */
/* The count of PWM_VAL3 */
#define PWM_VAL3_COUNT (4U)
/*! @name FRACVAL4 - Fractional Value Register 4 */
/*! @{ */
#define PWM_FRACVAL4_FRACVAL4_MASK (0xF800U)
#define PWM_FRACVAL4_FRACVAL4_SHIFT (11U)
/*! FRACVAL4 - Fractional Value 4
*/
#define PWM_FRACVAL4_FRACVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL4_FRACVAL4_SHIFT)) & PWM_FRACVAL4_FRACVAL4_MASK)
/*! @} */
/* The count of PWM_FRACVAL4 */
#define PWM_FRACVAL4_COUNT (4U)
/*! @name VAL4 - Value Register 4 */
/*! @{ */
#define PWM_VAL4_VAL4_MASK (0xFFFFU)
#define PWM_VAL4_VAL4_SHIFT (0U)
/*! VAL4 - Value Register 4
*/
#define PWM_VAL4_VAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL4_VAL4_SHIFT)) & PWM_VAL4_VAL4_MASK)
/*! @} */
/* The count of PWM_VAL4 */
#define PWM_VAL4_COUNT (4U)
/*! @name FRACVAL5 - Fractional Value Register 5 */
/*! @{ */
#define PWM_FRACVAL5_FRACVAL5_MASK (0xF800U)
#define PWM_FRACVAL5_FRACVAL5_SHIFT (11U)
/*! FRACVAL5 - Fractional Value 5
*/
#define PWM_FRACVAL5_FRACVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRACVAL5_FRACVAL5_SHIFT)) & PWM_FRACVAL5_FRACVAL5_MASK)
/*! @} */
/* The count of PWM_FRACVAL5 */
#define PWM_FRACVAL5_COUNT (4U)
/*! @name VAL5 - Value Register 5 */
/*! @{ */
#define PWM_VAL5_VAL5_MASK (0xFFFFU)
#define PWM_VAL5_VAL5_SHIFT (0U)
/*! VAL5 - Value Register 5
*/
#define PWM_VAL5_VAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_VAL5_VAL5_SHIFT)) & PWM_VAL5_VAL5_MASK)
/*! @} */
/* The count of PWM_VAL5 */
#define PWM_VAL5_COUNT (4U)
/*! @name FRCTRL - Fractional Control Register */
/*! @{ */
#define PWM_FRCTRL_FRAC1_EN_MASK (0x2U)
#define PWM_FRCTRL_FRAC1_EN_SHIFT (1U)
/*! FRAC1_EN - Fractional Cycle PWM Period Enable
* 0b0..Disable fractional cycle length for the PWM period.
* 0b1..Enable fractional cycle length for the PWM period.
*/
#define PWM_FRCTRL_FRAC1_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC1_EN_SHIFT)) & PWM_FRCTRL_FRAC1_EN_MASK)
#define PWM_FRCTRL_FRAC23_EN_MASK (0x4U)
#define PWM_FRCTRL_FRAC23_EN_SHIFT (2U)
/*! FRAC23_EN - Fractional Cycle Placement Enable for PWM_A
* 0b0..Disable fractional cycle placement for PWM_A.
* 0b1..Enable fractional cycle placement for PWM_A.
*/
#define PWM_FRCTRL_FRAC23_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC23_EN_SHIFT)) & PWM_FRCTRL_FRAC23_EN_MASK)
#define PWM_FRCTRL_FRAC45_EN_MASK (0x10U)
#define PWM_FRCTRL_FRAC45_EN_SHIFT (4U)
/*! FRAC45_EN - Fractional Cycle Placement Enable for PWM_B
* 0b0..Disable fractional cycle placement for PWM_B.
* 0b1..Enable fractional cycle placement for PWM_B.
*/
#define PWM_FRCTRL_FRAC45_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_FRAC45_EN_SHIFT)) & PWM_FRCTRL_FRAC45_EN_MASK)
#define PWM_FRCTRL_TEST_MASK (0x8000U)
#define PWM_FRCTRL_TEST_SHIFT (15U)
/*! TEST - Test Status Bit
*/
#define PWM_FRCTRL_TEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FRCTRL_TEST_SHIFT)) & PWM_FRCTRL_TEST_MASK)
/*! @} */
/* The count of PWM_FRCTRL */
#define PWM_FRCTRL_COUNT (4U)
/*! @name OCTRL - Output Control Register */
/*! @{ */
#define PWM_OCTRL_PWMXFS_MASK (0x3U)
#define PWM_OCTRL_PWMXFS_SHIFT (0U)
/*! PWMXFS - PWM_X Fault State
* 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
* 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
* 0b10, 0b11..Output is tristated.
*/
#define PWM_OCTRL_PWMXFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMXFS_SHIFT)) & PWM_OCTRL_PWMXFS_MASK)
#define PWM_OCTRL_PWMBFS_MASK (0xCU)
#define PWM_OCTRL_PWMBFS_SHIFT (2U)
/*! PWMBFS - PWM_B Fault State
* 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
* 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
* 0b10, 0b11..Output is tristated.
*/
#define PWM_OCTRL_PWMBFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMBFS_SHIFT)) & PWM_OCTRL_PWMBFS_MASK)
#define PWM_OCTRL_PWMAFS_MASK (0x30U)
#define PWM_OCTRL_PWMAFS_SHIFT (4U)
/*! PWMAFS - PWM_A Fault State
* 0b00..Output is forced to logic 0 state prior to consideration of output polarity control.
* 0b01..Output is forced to logic 1 state prior to consideration of output polarity control.
* 0b10, 0b11..Output is tristated.
*/
#define PWM_OCTRL_PWMAFS(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMAFS_SHIFT)) & PWM_OCTRL_PWMAFS_MASK)
#define PWM_OCTRL_POLX_MASK (0x100U)
#define PWM_OCTRL_POLX_SHIFT (8U)
/*! POLX - PWM_X Output Polarity
* 0b0..PWM_X output not inverted. A high level on the PWM_X pin represents the "on" or "active" state.
* 0b1..PWM_X output inverted. A low level on the PWM_X pin represents the "on" or "active" state.
*/
#define PWM_OCTRL_POLX(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLX_SHIFT)) & PWM_OCTRL_POLX_MASK)
#define PWM_OCTRL_POLB_MASK (0x200U)
#define PWM_OCTRL_POLB_SHIFT (9U)
/*! POLB - PWM_B Output Polarity
* 0b0..PWM_B output not inverted. A high level on the PWM_B pin represents the "on" or "active" state.
* 0b1..PWM_B output inverted. A low level on the PWM_B pin represents the "on" or "active" state.
*/
#define PWM_OCTRL_POLB(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLB_SHIFT)) & PWM_OCTRL_POLB_MASK)
#define PWM_OCTRL_POLA_MASK (0x400U)
#define PWM_OCTRL_POLA_SHIFT (10U)
/*! POLA - PWM_A Output Polarity
* 0b0..PWM_A output not inverted. A high level on the PWM_A pin represents the "on" or "active" state.
* 0b1..PWM_A output inverted. A low level on the PWM_A pin represents the "on" or "active" state.
*/
#define PWM_OCTRL_POLA(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_POLA_SHIFT)) & PWM_OCTRL_POLA_MASK)
#define PWM_OCTRL_PWMX_IN_MASK (0x2000U)
#define PWM_OCTRL_PWMX_IN_SHIFT (13U)
/*! PWMX_IN - PWM_X Input
*/
#define PWM_OCTRL_PWMX_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMX_IN_SHIFT)) & PWM_OCTRL_PWMX_IN_MASK)
#define PWM_OCTRL_PWMB_IN_MASK (0x4000U)
#define PWM_OCTRL_PWMB_IN_SHIFT (14U)
/*! PWMB_IN - PWM_B Input
*/
#define PWM_OCTRL_PWMB_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMB_IN_SHIFT)) & PWM_OCTRL_PWMB_IN_MASK)
#define PWM_OCTRL_PWMA_IN_MASK (0x8000U)
#define PWM_OCTRL_PWMA_IN_SHIFT (15U)
/*! PWMA_IN - PWM_A Input
*/
#define PWM_OCTRL_PWMA_IN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OCTRL_PWMA_IN_SHIFT)) & PWM_OCTRL_PWMA_IN_MASK)
/*! @} */
/* The count of PWM_OCTRL */
#define PWM_OCTRL_COUNT (4U)
/*! @name STS - Status Register */
/*! @{ */
#define PWM_STS_CMPF_MASK (0x3FU)
#define PWM_STS_CMPF_SHIFT (0U)
/*! CMPF - Compare Flags
* 0b000000..No compare event has occurred for a particular VALx value.
* 0b000001..A compare event has occurred for a particular VALx value.
*/
#define PWM_STS_CMPF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CMPF_SHIFT)) & PWM_STS_CMPF_MASK)
#define PWM_STS_CFX0_MASK (0x40U)
#define PWM_STS_CFX0_SHIFT (6U)
/*! CFX0 - Capture Flag X0
*/
#define PWM_STS_CFX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX0_SHIFT)) & PWM_STS_CFX0_MASK)
#define PWM_STS_CFX1_MASK (0x80U)
#define PWM_STS_CFX1_SHIFT (7U)
/*! CFX1 - Capture Flag X1
*/
#define PWM_STS_CFX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFX1_SHIFT)) & PWM_STS_CFX1_MASK)
#define PWM_STS_CFB0_MASK (0x100U)
#define PWM_STS_CFB0_SHIFT (8U)
/*! CFB0 - Capture Flag B0
*/
#define PWM_STS_CFB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB0_SHIFT)) & PWM_STS_CFB0_MASK)
#define PWM_STS_CFB1_MASK (0x200U)
#define PWM_STS_CFB1_SHIFT (9U)
/*! CFB1 - Capture Flag B1
*/
#define PWM_STS_CFB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFB1_SHIFT)) & PWM_STS_CFB1_MASK)
#define PWM_STS_CFA0_MASK (0x400U)
#define PWM_STS_CFA0_SHIFT (10U)
/*! CFA0 - Capture Flag A0
*/
#define PWM_STS_CFA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA0_SHIFT)) & PWM_STS_CFA0_MASK)
#define PWM_STS_CFA1_MASK (0x800U)
#define PWM_STS_CFA1_SHIFT (11U)
/*! CFA1 - Capture Flag A1
*/
#define PWM_STS_CFA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_CFA1_SHIFT)) & PWM_STS_CFA1_MASK)
#define PWM_STS_RF_MASK (0x1000U)
#define PWM_STS_RF_SHIFT (12U)
/*! RF - Reload Flag
* 0b0..No new reload cycle since last STS[RF] clearing
* 0b1..New reload cycle since last STS[RF] clearing
*/
#define PWM_STS_RF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RF_SHIFT)) & PWM_STS_RF_MASK)
#define PWM_STS_REF_MASK (0x2000U)
#define PWM_STS_REF_SHIFT (13U)
/*! REF - Reload Error Flag
* 0b0..No reload error occurred.
* 0b1..Reload signal occurred with non-coherent data and MCTRL[LDOK] = 0.
*/
#define PWM_STS_REF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_REF_SHIFT)) & PWM_STS_REF_MASK)
#define PWM_STS_RUF_MASK (0x4000U)
#define PWM_STS_RUF_SHIFT (14U)
/*! RUF - Registers Updated Flag
* 0b0..No register update has occurred since last reload.
* 0b1..At least one of the double buffered registers has been updated since the last reload.
*/
#define PWM_STS_RUF(x) (((uint16_t)(((uint16_t)(x)) << PWM_STS_RUF_SHIFT)) & PWM_STS_RUF_MASK)
/*! @} */
/* The count of PWM_STS */
#define PWM_STS_COUNT (4U)
/*! @name INTEN - Interrupt Enable Register */
/*! @{ */
#define PWM_INTEN_CMPIE_MASK (0x3FU)
#define PWM_INTEN_CMPIE_SHIFT (0U)
/*! CMPIE - Compare Interrupt Enables
* 0b000000..The corresponding STS[CMPF] bit will not cause an interrupt request.
* 0b000001..The corresponding STS[CMPF] bit will cause an interrupt request.
*/
#define PWM_INTEN_CMPIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CMPIE_SHIFT)) & PWM_INTEN_CMPIE_MASK)
#define PWM_INTEN_CX0IE_MASK (0x40U)
#define PWM_INTEN_CX0IE_SHIFT (6U)
/*! CX0IE - Capture X 0 Interrupt Enable
* 0b0..Interrupt request disabled for STS[CFX0].
* 0b1..Interrupt request enabled for STS[CFX0].
*/
#define PWM_INTEN_CX0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX0IE_SHIFT)) & PWM_INTEN_CX0IE_MASK)
#define PWM_INTEN_CX1IE_MASK (0x80U)
#define PWM_INTEN_CX1IE_SHIFT (7U)
/*! CX1IE - Capture X 1 Interrupt Enable
* 0b0..Interrupt request disabled for STS[CFX1].
* 0b1..Interrupt request enabled for STS[CFX1].
*/
#define PWM_INTEN_CX1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CX1IE_SHIFT)) & PWM_INTEN_CX1IE_MASK)
#define PWM_INTEN_CB0IE_MASK (0x100U)
#define PWM_INTEN_CB0IE_SHIFT (8U)
/*! CB0IE - Capture B 0 Interrupt Enable
* 0b0..Interrupt request disabled for STS[CFB0].
* 0b1..Interrupt request enabled for STS[CFB0].
*/
#define PWM_INTEN_CB0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB0IE_SHIFT)) & PWM_INTEN_CB0IE_MASK)
#define PWM_INTEN_CB1IE_MASK (0x200U)
#define PWM_INTEN_CB1IE_SHIFT (9U)
/*! CB1IE - Capture B 1 Interrupt Enable
* 0b0..Interrupt request disabled for STS[CFB1].
* 0b1..Interrupt request enabled for STS[CFB1].
*/
#define PWM_INTEN_CB1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CB1IE_SHIFT)) & PWM_INTEN_CB1IE_MASK)
#define PWM_INTEN_CA0IE_MASK (0x400U)
#define PWM_INTEN_CA0IE_SHIFT (10U)
/*! CA0IE - Capture A 0 Interrupt Enable
* 0b0..Interrupt request disabled for STS[CFA0].
* 0b1..Interrupt request enabled for STS[CFA0].
*/
#define PWM_INTEN_CA0IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA0IE_SHIFT)) & PWM_INTEN_CA0IE_MASK)
#define PWM_INTEN_CA1IE_MASK (0x800U)
#define PWM_INTEN_CA1IE_SHIFT (11U)
/*! CA1IE - Capture A 1 Interrupt Enable
* 0b0..Interrupt request disabled for STS[CFA1].
* 0b1..Interrupt request enabled for STS[CFA1].
*/
#define PWM_INTEN_CA1IE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_CA1IE_SHIFT)) & PWM_INTEN_CA1IE_MASK)
#define PWM_INTEN_RIE_MASK (0x1000U)
#define PWM_INTEN_RIE_SHIFT (12U)
/*! RIE - Reload Interrupt Enable
* 0b0..STS[RF] CPU interrupt requests disabled
* 0b1..STS[RF] CPU interrupt requests enabled
*/
#define PWM_INTEN_RIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_RIE_SHIFT)) & PWM_INTEN_RIE_MASK)
#define PWM_INTEN_REIE_MASK (0x2000U)
#define PWM_INTEN_REIE_SHIFT (13U)
/*! REIE - Reload Error Interrupt Enable
* 0b0..STS[REF] CPU interrupt requests disabled
* 0b1..STS[REF] CPU interrupt requests enabled
*/
#define PWM_INTEN_REIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_INTEN_REIE_SHIFT)) & PWM_INTEN_REIE_MASK)
/*! @} */
/* The count of PWM_INTEN */
#define PWM_INTEN_COUNT (4U)
/*! @name DMAEN - DMA Enable Register */
/*! @{ */
#define PWM_DMAEN_CX0DE_MASK (0x1U)
#define PWM_DMAEN_CX0DE_SHIFT (0U)
/*! CX0DE - Capture X0 FIFO DMA Enable
*/
#define PWM_DMAEN_CX0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX0DE_SHIFT)) & PWM_DMAEN_CX0DE_MASK)
#define PWM_DMAEN_CX1DE_MASK (0x2U)
#define PWM_DMAEN_CX1DE_SHIFT (1U)
/*! CX1DE - Capture X1 FIFO DMA Enable
*/
#define PWM_DMAEN_CX1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CX1DE_SHIFT)) & PWM_DMAEN_CX1DE_MASK)
#define PWM_DMAEN_CB0DE_MASK (0x4U)
#define PWM_DMAEN_CB0DE_SHIFT (2U)
/*! CB0DE - Capture B0 FIFO DMA Enable
*/
#define PWM_DMAEN_CB0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB0DE_SHIFT)) & PWM_DMAEN_CB0DE_MASK)
#define PWM_DMAEN_CB1DE_MASK (0x8U)
#define PWM_DMAEN_CB1DE_SHIFT (3U)
/*! CB1DE - Capture B1 FIFO DMA Enable
*/
#define PWM_DMAEN_CB1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CB1DE_SHIFT)) & PWM_DMAEN_CB1DE_MASK)
#define PWM_DMAEN_CA0DE_MASK (0x10U)
#define PWM_DMAEN_CA0DE_SHIFT (4U)
/*! CA0DE - Capture A0 FIFO DMA Enable
*/
#define PWM_DMAEN_CA0DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA0DE_SHIFT)) & PWM_DMAEN_CA0DE_MASK)
#define PWM_DMAEN_CA1DE_MASK (0x20U)
#define PWM_DMAEN_CA1DE_SHIFT (5U)
/*! CA1DE - Capture A1 FIFO DMA Enable
*/
#define PWM_DMAEN_CA1DE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CA1DE_SHIFT)) & PWM_DMAEN_CA1DE_MASK)
#define PWM_DMAEN_CAPTDE_MASK (0xC0U)
#define PWM_DMAEN_CAPTDE_SHIFT (6U)
/*! CAPTDE - Capture DMA Enable Source Select
* 0b00..Read DMA requests disabled.
* 0b01..Exceeding a FIFO watermark sets the DMA read request. This requires at least one of DMAEN[CA1DE],
* DMAEN[CA0DE], DMAEN[CB1DE], DMAEN[CB0DE], DMAEN[CX1DE], or DMAEN[CX0DE] to also be set in order to determine to
* which watermark(s) the DMA request is sensitive.
* 0b10..A local sync (VAL1 matches counter) sets the read DMA request.
* 0b11..A local reload (STS[RF] being set) sets the read DMA request.
*/
#define PWM_DMAEN_CAPTDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_CAPTDE_SHIFT)) & PWM_DMAEN_CAPTDE_MASK)
#define PWM_DMAEN_FAND_MASK (0x100U)
#define PWM_DMAEN_FAND_SHIFT (8U)
/*! FAND - FIFO Watermark AND Control
* 0b0..Selected FIFO watermarks are OR'ed together.
* 0b1..Selected FIFO watermarks are AND'ed together.
*/
#define PWM_DMAEN_FAND(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_FAND_SHIFT)) & PWM_DMAEN_FAND_MASK)
#define PWM_DMAEN_VALDE_MASK (0x200U)
#define PWM_DMAEN_VALDE_SHIFT (9U)
/*! VALDE - Value Registers DMA Enable
* 0b0..DMA write requests disabled
* 0b1..Enabled
*/
#define PWM_DMAEN_VALDE(x) (((uint16_t)(((uint16_t)(x)) << PWM_DMAEN_VALDE_SHIFT)) & PWM_DMAEN_VALDE_MASK)
/*! @} */
/* The count of PWM_DMAEN */
#define PWM_DMAEN_COUNT (4U)
/*! @name TCTRL - Output Trigger Control Register */
/*! @{ */
#define PWM_TCTRL_OUT_TRIG_EN_MASK (0x3FU)
#define PWM_TCTRL_OUT_TRIG_EN_SHIFT (0U)
/*! OUT_TRIG_EN - Output Trigger Enables
* 0bxxxxx1..PWM_OUT_TRIG0 will set when the counter value matches the VAL0 value.
* 0bxxxx1x..PWM_OUT_TRIG1 will set when the counter value matches the VAL1 value.
* 0bxxx1xx..PWM_OUT_TRIG0 will set when the counter value matches the VAL2 value.
* 0bxx1xxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL3 value.
* 0bx1xxxx..PWM_OUT_TRIG0 will set when the counter value matches the VAL4 value.
* 0b1xxxxx..PWM_OUT_TRIG1 will set when the counter value matches the VAL5 value.
*/
#define PWM_TCTRL_OUT_TRIG_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_OUT_TRIG_EN_SHIFT)) & PWM_TCTRL_OUT_TRIG_EN_MASK)
#define PWM_TCTRL_TRGFRQ_MASK (0x1000U)
#define PWM_TCTRL_TRGFRQ_SHIFT (12U)
/*! TRGFRQ - Trigger frequency
* 0b0..Trigger outputs are generated during every PWM period even if the PWM is not reloaded every period due to CTRL[LDFQ] being non-zero.
* 0b1..Trigger outputs are generated only during the final PWM period prior to a reload opportunity when the PWM
* is not reloaded every period due to CTRL[LDFQ] being non-zero.
*/
#define PWM_TCTRL_TRGFRQ(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_TRGFRQ_SHIFT)) & PWM_TCTRL_TRGFRQ_MASK)
#define PWM_TCTRL_PWBOT1_MASK (0x4000U)
#define PWM_TCTRL_PWBOT1_SHIFT (14U)
/*! PWBOT1 - Output Trigger 1 Source Select
* 0b0..Route the PWM_OUT_TRIG1 signal to PWM_OUT_TRIG1 port.
* 0b1..Route the PWMB output to the PWM_OUT_TRIG1 port.
*/
#define PWM_TCTRL_PWBOT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWBOT1_SHIFT)) & PWM_TCTRL_PWBOT1_MASK)
#define PWM_TCTRL_PWAOT0_MASK (0x8000U)
#define PWM_TCTRL_PWAOT0_SHIFT (15U)
/*! PWAOT0 - Output Trigger 0 Source Select
* 0b0..Route the PWM_OUT_TRIG0 signal to PWM_OUT_TRIG0 port.
* 0b1..Route the PWMA output to the PWM_OUT_TRIG0 port.
*/
#define PWM_TCTRL_PWAOT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_TCTRL_PWAOT0_SHIFT)) & PWM_TCTRL_PWAOT0_MASK)
/*! @} */
/* The count of PWM_TCTRL */
#define PWM_TCTRL_COUNT (4U)
/*! @name DISMAP - Fault Disable Mapping Register 0 */
/*! @{ */
#define PWM_DISMAP_DIS0A_MASK (0xFU)
#define PWM_DISMAP_DIS0A_SHIFT (0U)
/*! DIS0A - PWM_A Fault Disable Mask 0
*/
#define PWM_DISMAP_DIS0A(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0A_SHIFT)) & PWM_DISMAP_DIS0A_MASK)
#define PWM_DISMAP_DIS0B_MASK (0xF0U)
#define PWM_DISMAP_DIS0B_SHIFT (4U)
/*! DIS0B - PWM_B Fault Disable Mask 0
*/
#define PWM_DISMAP_DIS0B(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0B_SHIFT)) & PWM_DISMAP_DIS0B_MASK)
#define PWM_DISMAP_DIS0X_MASK (0xF00U)
#define PWM_DISMAP_DIS0X_SHIFT (8U)
/*! DIS0X - PWM_X Fault Disable Mask 0
*/
#define PWM_DISMAP_DIS0X(x) (((uint16_t)(((uint16_t)(x)) << PWM_DISMAP_DIS0X_SHIFT)) & PWM_DISMAP_DIS0X_MASK)
/*! @} */
/* The count of PWM_DISMAP */
#define PWM_DISMAP_COUNT (4U)
/* The count of PWM_DISMAP */
#define PWM_DISMAP_COUNT2 (1U)
/*! @name DTCNT0 - Deadtime Count Register 0 */
/*! @{ */
#define PWM_DTCNT0_DTCNT0_MASK (0xFFFFU)
#define PWM_DTCNT0_DTCNT0_SHIFT (0U)
/*! DTCNT0 - DTCNT0
*/
#define PWM_DTCNT0_DTCNT0(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT0_DTCNT0_SHIFT)) & PWM_DTCNT0_DTCNT0_MASK)
/*! @} */
/* The count of PWM_DTCNT0 */
#define PWM_DTCNT0_COUNT (4U)
/*! @name DTCNT1 - Deadtime Count Register 1 */
/*! @{ */
#define PWM_DTCNT1_DTCNT1_MASK (0xFFFFU)
#define PWM_DTCNT1_DTCNT1_SHIFT (0U)
/*! DTCNT1 - DTCNT1
*/
#define PWM_DTCNT1_DTCNT1(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTCNT1_DTCNT1_SHIFT)) & PWM_DTCNT1_DTCNT1_MASK)
/*! @} */
/* The count of PWM_DTCNT1 */
#define PWM_DTCNT1_COUNT (4U)
/*! @name CAPTCTRLA - Capture Control A Register */
/*! @{ */
#define PWM_CAPTCTRLA_ARMA_MASK (0x1U)
#define PWM_CAPTCTRLA_ARMA_SHIFT (0U)
/*! ARMA - Arm A
* 0b0..Input capture operation is disabled.
* 0b1..Input capture operation as specified by CAPTCTRLA[EDGAx] is enabled.
*/
#define PWM_CAPTCTRLA_ARMA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ARMA_SHIFT)) & PWM_CAPTCTRLA_ARMA_MASK)
#define PWM_CAPTCTRLA_ONESHOTA_MASK (0x2U)
#define PWM_CAPTCTRLA_ONESHOTA_SHIFT (1U)
/*! ONESHOTA - One Shot Mode A
* 0b0..Free Running
* 0b1..One Shot
*/
#define PWM_CAPTCTRLA_ONESHOTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_ONESHOTA_SHIFT)) & PWM_CAPTCTRLA_ONESHOTA_MASK)
#define PWM_CAPTCTRLA_EDGA0_MASK (0xCU)
#define PWM_CAPTCTRLA_EDGA0_SHIFT (2U)
/*! EDGA0 - Edge A 0
* 0b00..Disabled
* 0b01..Capture falling edges
* 0b10..Capture rising edges
* 0b11..Capture any edge
*/
#define PWM_CAPTCTRLA_EDGA0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA0_SHIFT)) & PWM_CAPTCTRLA_EDGA0_MASK)
#define PWM_CAPTCTRLA_EDGA1_MASK (0x30U)
#define PWM_CAPTCTRLA_EDGA1_SHIFT (4U)
/*! EDGA1 - Edge A 1
* 0b00..Disabled
* 0b01..Capture falling edges
* 0b10..Capture rising edges
* 0b11..Capture any edge
*/
#define PWM_CAPTCTRLA_EDGA1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGA1_SHIFT)) & PWM_CAPTCTRLA_EDGA1_MASK)
#define PWM_CAPTCTRLA_INP_SELA_MASK (0x40U)
#define PWM_CAPTCTRLA_INP_SELA_SHIFT (6U)
/*! INP_SELA - Input Select A
* 0b0..Raw PWM_A input signal selected as source.
* 0b1..Edge Counter
*/
#define PWM_CAPTCTRLA_INP_SELA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_INP_SELA_SHIFT)) & PWM_CAPTCTRLA_INP_SELA_MASK)
#define PWM_CAPTCTRLA_EDGCNTA_EN_MASK (0x80U)
#define PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT (7U)
/*! EDGCNTA_EN - Edge Counter A Enable
* 0b0..Edge counter disabled and held in reset
* 0b1..Edge counter enabled
*/
#define PWM_CAPTCTRLA_EDGCNTA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_EDGCNTA_EN_SHIFT)) & PWM_CAPTCTRLA_EDGCNTA_EN_MASK)
#define PWM_CAPTCTRLA_CFAWM_MASK (0x300U)
#define PWM_CAPTCTRLA_CFAWM_SHIFT (8U)
/*! CFAWM - Capture A FIFOs Water Mark
*/
#define PWM_CAPTCTRLA_CFAWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CFAWM_SHIFT)) & PWM_CAPTCTRLA_CFAWM_MASK)
#define PWM_CAPTCTRLA_CA0CNT_MASK (0x1C00U)
#define PWM_CAPTCTRLA_CA0CNT_SHIFT (10U)
/*! CA0CNT - Capture A0 FIFO Word Count
*/
#define PWM_CAPTCTRLA_CA0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA0CNT_SHIFT)) & PWM_CAPTCTRLA_CA0CNT_MASK)
#define PWM_CAPTCTRLA_CA1CNT_MASK (0xE000U)
#define PWM_CAPTCTRLA_CA1CNT_SHIFT (13U)
/*! CA1CNT - Capture A1 FIFO Word Count
*/
#define PWM_CAPTCTRLA_CA1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLA_CA1CNT_SHIFT)) & PWM_CAPTCTRLA_CA1CNT_MASK)
/*! @} */
/* The count of PWM_CAPTCTRLA */
#define PWM_CAPTCTRLA_COUNT (4U)
/*! @name CAPTCOMPA - Capture Compare A Register */
/*! @{ */
#define PWM_CAPTCOMPA_EDGCMPA_MASK (0xFFU)
#define PWM_CAPTCOMPA_EDGCMPA_SHIFT (0U)
/*! EDGCMPA - Edge Compare A
*/
#define PWM_CAPTCOMPA_EDGCMPA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCMPA_SHIFT)) & PWM_CAPTCOMPA_EDGCMPA_MASK)
#define PWM_CAPTCOMPA_EDGCNTA_MASK (0xFF00U)
#define PWM_CAPTCOMPA_EDGCNTA_SHIFT (8U)
/*! EDGCNTA - Edge Counter A
*/
#define PWM_CAPTCOMPA_EDGCNTA(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPA_EDGCNTA_SHIFT)) & PWM_CAPTCOMPA_EDGCNTA_MASK)
/*! @} */
/* The count of PWM_CAPTCOMPA */
#define PWM_CAPTCOMPA_COUNT (4U)
/*! @name CAPTCTRLB - Capture Control B Register */
/*! @{ */
#define PWM_CAPTCTRLB_ARMB_MASK (0x1U)
#define PWM_CAPTCTRLB_ARMB_SHIFT (0U)
/*! ARMB - Arm B
* 0b0..Input capture operation is disabled.
* 0b1..Input capture operation as specified by CAPTCTRLB[EDGBx] is enabled.
*/
#define PWM_CAPTCTRLB_ARMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ARMB_SHIFT)) & PWM_CAPTCTRLB_ARMB_MASK)
#define PWM_CAPTCTRLB_ONESHOTB_MASK (0x2U)
#define PWM_CAPTCTRLB_ONESHOTB_SHIFT (1U)
/*! ONESHOTB - One Shot Mode B
* 0b0..Free Running
* 0b1..One Shot
*/
#define PWM_CAPTCTRLB_ONESHOTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_ONESHOTB_SHIFT)) & PWM_CAPTCTRLB_ONESHOTB_MASK)
#define PWM_CAPTCTRLB_EDGB0_MASK (0xCU)
#define PWM_CAPTCTRLB_EDGB0_SHIFT (2U)
/*! EDGB0 - Edge B 0
* 0b00..Disabled
* 0b01..Capture falling edges
* 0b10..Capture rising edges
* 0b11..Capture any edge
*/
#define PWM_CAPTCTRLB_EDGB0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB0_SHIFT)) & PWM_CAPTCTRLB_EDGB0_MASK)
#define PWM_CAPTCTRLB_EDGB1_MASK (0x30U)
#define PWM_CAPTCTRLB_EDGB1_SHIFT (4U)
/*! EDGB1 - Edge B 1
* 0b00..Disabled
* 0b01..Capture falling edges
* 0b10..Capture rising edges
* 0b11..Capture any edge
*/
#define PWM_CAPTCTRLB_EDGB1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGB1_SHIFT)) & PWM_CAPTCTRLB_EDGB1_MASK)
#define PWM_CAPTCTRLB_INP_SELB_MASK (0x40U)
#define PWM_CAPTCTRLB_INP_SELB_SHIFT (6U)
/*! INP_SELB - Input Select B
* 0b0..Raw PWM_B input signal selected as source.
* 0b1..Edge Counter
*/
#define PWM_CAPTCTRLB_INP_SELB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_INP_SELB_SHIFT)) & PWM_CAPTCTRLB_INP_SELB_MASK)
#define PWM_CAPTCTRLB_EDGCNTB_EN_MASK (0x80U)
#define PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT (7U)
/*! EDGCNTB_EN - Edge Counter B Enable
* 0b0..Edge counter disabled and held in reset
* 0b1..Edge counter enabled
*/
#define PWM_CAPTCTRLB_EDGCNTB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_EDGCNTB_EN_SHIFT)) & PWM_CAPTCTRLB_EDGCNTB_EN_MASK)
#define PWM_CAPTCTRLB_CFBWM_MASK (0x300U)
#define PWM_CAPTCTRLB_CFBWM_SHIFT (8U)
/*! CFBWM - Capture B FIFOs Water Mark
*/
#define PWM_CAPTCTRLB_CFBWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CFBWM_SHIFT)) & PWM_CAPTCTRLB_CFBWM_MASK)
#define PWM_CAPTCTRLB_CB0CNT_MASK (0x1C00U)
#define PWM_CAPTCTRLB_CB0CNT_SHIFT (10U)
/*! CB0CNT - Capture B0 FIFO Word Count
*/
#define PWM_CAPTCTRLB_CB0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB0CNT_SHIFT)) & PWM_CAPTCTRLB_CB0CNT_MASK)
#define PWM_CAPTCTRLB_CB1CNT_MASK (0xE000U)
#define PWM_CAPTCTRLB_CB1CNT_SHIFT (13U)
/*! CB1CNT - Capture B1 FIFO Word Count
*/
#define PWM_CAPTCTRLB_CB1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLB_CB1CNT_SHIFT)) & PWM_CAPTCTRLB_CB1CNT_MASK)
/*! @} */
/* The count of PWM_CAPTCTRLB */
#define PWM_CAPTCTRLB_COUNT (4U)
/*! @name CAPTCOMPB - Capture Compare B Register */
/*! @{ */
#define PWM_CAPTCOMPB_EDGCMPB_MASK (0xFFU)
#define PWM_CAPTCOMPB_EDGCMPB_SHIFT (0U)
/*! EDGCMPB - Edge Compare B
*/
#define PWM_CAPTCOMPB_EDGCMPB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCMPB_SHIFT)) & PWM_CAPTCOMPB_EDGCMPB_MASK)
#define PWM_CAPTCOMPB_EDGCNTB_MASK (0xFF00U)
#define PWM_CAPTCOMPB_EDGCNTB_SHIFT (8U)
/*! EDGCNTB - Edge Counter B
*/
#define PWM_CAPTCOMPB_EDGCNTB(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPB_EDGCNTB_SHIFT)) & PWM_CAPTCOMPB_EDGCNTB_MASK)
/*! @} */
/* The count of PWM_CAPTCOMPB */
#define PWM_CAPTCOMPB_COUNT (4U)
/*! @name CAPTCTRLX - Capture Control X Register */
/*! @{ */
#define PWM_CAPTCTRLX_ARMX_MASK (0x1U)
#define PWM_CAPTCTRLX_ARMX_SHIFT (0U)
/*! ARMX - Arm X
* 0b0..Input capture operation is disabled.
* 0b1..Input capture operation as specified by CAPTCTRLX[EDGXx] is enabled.
*/
#define PWM_CAPTCTRLX_ARMX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ARMX_SHIFT)) & PWM_CAPTCTRLX_ARMX_MASK)
#define PWM_CAPTCTRLX_ONESHOTX_MASK (0x2U)
#define PWM_CAPTCTRLX_ONESHOTX_SHIFT (1U)
/*! ONESHOTX - One Shot Mode Aux
* 0b0..Free Running
* 0b1..One Shot
*/
#define PWM_CAPTCTRLX_ONESHOTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_ONESHOTX_SHIFT)) & PWM_CAPTCTRLX_ONESHOTX_MASK)
#define PWM_CAPTCTRLX_EDGX0_MASK (0xCU)
#define PWM_CAPTCTRLX_EDGX0_SHIFT (2U)
/*! EDGX0 - Edge X 0
* 0b00..Disabled
* 0b01..Capture falling edges
* 0b10..Capture rising edges
* 0b11..Capture any edge
*/
#define PWM_CAPTCTRLX_EDGX0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX0_SHIFT)) & PWM_CAPTCTRLX_EDGX0_MASK)
#define PWM_CAPTCTRLX_EDGX1_MASK (0x30U)
#define PWM_CAPTCTRLX_EDGX1_SHIFT (4U)
/*! EDGX1 - Edge X 1
* 0b00..Disabled
* 0b01..Capture falling edges
* 0b10..Capture rising edges
* 0b11..Capture any edge
*/
#define PWM_CAPTCTRLX_EDGX1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGX1_SHIFT)) & PWM_CAPTCTRLX_EDGX1_MASK)
#define PWM_CAPTCTRLX_INP_SELX_MASK (0x40U)
#define PWM_CAPTCTRLX_INP_SELX_SHIFT (6U)
/*! INP_SELX - Input Select X
* 0b0..Raw PWM_X input signal selected as source.
* 0b1..Edge Counter
*/
#define PWM_CAPTCTRLX_INP_SELX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_INP_SELX_SHIFT)) & PWM_CAPTCTRLX_INP_SELX_MASK)
#define PWM_CAPTCTRLX_EDGCNTX_EN_MASK (0x80U)
#define PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT (7U)
/*! EDGCNTX_EN - Edge Counter X Enable
* 0b0..Edge counter disabled and held in reset
* 0b1..Edge counter enabled
*/
#define PWM_CAPTCTRLX_EDGCNTX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_EDGCNTX_EN_SHIFT)) & PWM_CAPTCTRLX_EDGCNTX_EN_MASK)
#define PWM_CAPTCTRLX_CFXWM_MASK (0x300U)
#define PWM_CAPTCTRLX_CFXWM_SHIFT (8U)
/*! CFXWM - Capture X FIFOs Water Mark
*/
#define PWM_CAPTCTRLX_CFXWM(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CFXWM_SHIFT)) & PWM_CAPTCTRLX_CFXWM_MASK)
#define PWM_CAPTCTRLX_CX0CNT_MASK (0x1C00U)
#define PWM_CAPTCTRLX_CX0CNT_SHIFT (10U)
/*! CX0CNT - Capture X0 FIFO Word Count
*/
#define PWM_CAPTCTRLX_CX0CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX0CNT_SHIFT)) & PWM_CAPTCTRLX_CX0CNT_MASK)
#define PWM_CAPTCTRLX_CX1CNT_MASK (0xE000U)
#define PWM_CAPTCTRLX_CX1CNT_SHIFT (13U)
/*! CX1CNT - Capture X1 FIFO Word Count
*/
#define PWM_CAPTCTRLX_CX1CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCTRLX_CX1CNT_SHIFT)) & PWM_CAPTCTRLX_CX1CNT_MASK)
/*! @} */
/* The count of PWM_CAPTCTRLX */
#define PWM_CAPTCTRLX_COUNT (4U)
/*! @name CAPTCOMPX - Capture Compare X Register */
/*! @{ */
#define PWM_CAPTCOMPX_EDGCMPX_MASK (0xFFU)
#define PWM_CAPTCOMPX_EDGCMPX_SHIFT (0U)
/*! EDGCMPX - Edge Compare X
*/
#define PWM_CAPTCOMPX_EDGCMPX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCMPX_SHIFT)) & PWM_CAPTCOMPX_EDGCMPX_MASK)
#define PWM_CAPTCOMPX_EDGCNTX_MASK (0xFF00U)
#define PWM_CAPTCOMPX_EDGCNTX_SHIFT (8U)
/*! EDGCNTX - Edge Counter X
*/
#define PWM_CAPTCOMPX_EDGCNTX(x) (((uint16_t)(((uint16_t)(x)) << PWM_CAPTCOMPX_EDGCNTX_SHIFT)) & PWM_CAPTCOMPX_EDGCNTX_MASK)
/*! @} */
/* The count of PWM_CAPTCOMPX */
#define PWM_CAPTCOMPX_COUNT (4U)
/*! @name CVAL0 - Capture Value 0 Register */
/*! @{ */
#define PWM_CVAL0_CAPTVAL0_MASK (0xFFFFU)
#define PWM_CVAL0_CAPTVAL0_SHIFT (0U)
/*! CAPTVAL0 - CAPTVAL0
*/
#define PWM_CVAL0_CAPTVAL0(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0_CAPTVAL0_SHIFT)) & PWM_CVAL0_CAPTVAL0_MASK)
/*! @} */
/* The count of PWM_CVAL0 */
#define PWM_CVAL0_COUNT (4U)
/*! @name CVAL0CYC - Capture Value 0 Cycle Register */
/*! @{ */
#define PWM_CVAL0CYC_CVAL0CYC_MASK (0xFU)
#define PWM_CVAL0CYC_CVAL0CYC_SHIFT (0U)
/*! CVAL0CYC - CVAL0CYC
*/
#define PWM_CVAL0CYC_CVAL0CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL0CYC_CVAL0CYC_SHIFT)) & PWM_CVAL0CYC_CVAL0CYC_MASK)
/*! @} */
/* The count of PWM_CVAL0CYC */
#define PWM_CVAL0CYC_COUNT (4U)
/*! @name CVAL1 - Capture Value 1 Register */
/*! @{ */
#define PWM_CVAL1_CAPTVAL1_MASK (0xFFFFU)
#define PWM_CVAL1_CAPTVAL1_SHIFT (0U)
/*! CAPTVAL1 - CAPTVAL1
*/
#define PWM_CVAL1_CAPTVAL1(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1_CAPTVAL1_SHIFT)) & PWM_CVAL1_CAPTVAL1_MASK)
/*! @} */
/* The count of PWM_CVAL1 */
#define PWM_CVAL1_COUNT (4U)
/*! @name CVAL1CYC - Capture Value 1 Cycle Register */
/*! @{ */
#define PWM_CVAL1CYC_CVAL1CYC_MASK (0xFU)
#define PWM_CVAL1CYC_CVAL1CYC_SHIFT (0U)
/*! CVAL1CYC - CVAL1CYC
*/
#define PWM_CVAL1CYC_CVAL1CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL1CYC_CVAL1CYC_SHIFT)) & PWM_CVAL1CYC_CVAL1CYC_MASK)
/*! @} */
/* The count of PWM_CVAL1CYC */
#define PWM_CVAL1CYC_COUNT (4U)
/*! @name CVAL2 - Capture Value 2 Register */
/*! @{ */
#define PWM_CVAL2_CAPTVAL2_MASK (0xFFFFU)
#define PWM_CVAL2_CAPTVAL2_SHIFT (0U)
/*! CAPTVAL2 - CAPTVAL2
*/
#define PWM_CVAL2_CAPTVAL2(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2_CAPTVAL2_SHIFT)) & PWM_CVAL2_CAPTVAL2_MASK)
/*! @} */
/* The count of PWM_CVAL2 */
#define PWM_CVAL2_COUNT (4U)
/*! @name CVAL2CYC - Capture Value 2 Cycle Register */
/*! @{ */
#define PWM_CVAL2CYC_CVAL2CYC_MASK (0xFU)
#define PWM_CVAL2CYC_CVAL2CYC_SHIFT (0U)
/*! CVAL2CYC - CVAL2CYC
*/
#define PWM_CVAL2CYC_CVAL2CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL2CYC_CVAL2CYC_SHIFT)) & PWM_CVAL2CYC_CVAL2CYC_MASK)
/*! @} */
/* The count of PWM_CVAL2CYC */
#define PWM_CVAL2CYC_COUNT (4U)
/*! @name CVAL3 - Capture Value 3 Register */
/*! @{ */
#define PWM_CVAL3_CAPTVAL3_MASK (0xFFFFU)
#define PWM_CVAL3_CAPTVAL3_SHIFT (0U)
/*! CAPTVAL3 - CAPTVAL3
*/
#define PWM_CVAL3_CAPTVAL3(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3_CAPTVAL3_SHIFT)) & PWM_CVAL3_CAPTVAL3_MASK)
/*! @} */
/* The count of PWM_CVAL3 */
#define PWM_CVAL3_COUNT (4U)
/*! @name CVAL3CYC - Capture Value 3 Cycle Register */
/*! @{ */
#define PWM_CVAL3CYC_CVAL3CYC_MASK (0xFU)
#define PWM_CVAL3CYC_CVAL3CYC_SHIFT (0U)
/*! CVAL3CYC - CVAL3CYC
*/
#define PWM_CVAL3CYC_CVAL3CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL3CYC_CVAL3CYC_SHIFT)) & PWM_CVAL3CYC_CVAL3CYC_MASK)
/*! @} */
/* The count of PWM_CVAL3CYC */
#define PWM_CVAL3CYC_COUNT (4U)
/*! @name CVAL4 - Capture Value 4 Register */
/*! @{ */
#define PWM_CVAL4_CAPTVAL4_MASK (0xFFFFU)
#define PWM_CVAL4_CAPTVAL4_SHIFT (0U)
/*! CAPTVAL4 - CAPTVAL4
*/
#define PWM_CVAL4_CAPTVAL4(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4_CAPTVAL4_SHIFT)) & PWM_CVAL4_CAPTVAL4_MASK)
/*! @} */
/* The count of PWM_CVAL4 */
#define PWM_CVAL4_COUNT (4U)
/*! @name CVAL4CYC - Capture Value 4 Cycle Register */
/*! @{ */
#define PWM_CVAL4CYC_CVAL4CYC_MASK (0xFU)
#define PWM_CVAL4CYC_CVAL4CYC_SHIFT (0U)
/*! CVAL4CYC - CVAL4CYC
*/
#define PWM_CVAL4CYC_CVAL4CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL4CYC_CVAL4CYC_SHIFT)) & PWM_CVAL4CYC_CVAL4CYC_MASK)
/*! @} */
/* The count of PWM_CVAL4CYC */
#define PWM_CVAL4CYC_COUNT (4U)
/*! @name CVAL5 - Capture Value 5 Register */
/*! @{ */
#define PWM_CVAL5_CAPTVAL5_MASK (0xFFFFU)
#define PWM_CVAL5_CAPTVAL5_SHIFT (0U)
/*! CAPTVAL5 - CAPTVAL5
*/
#define PWM_CVAL5_CAPTVAL5(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5_CAPTVAL5_SHIFT)) & PWM_CVAL5_CAPTVAL5_MASK)
/*! @} */
/* The count of PWM_CVAL5 */
#define PWM_CVAL5_COUNT (4U)
/*! @name CVAL5CYC - Capture Value 5 Cycle Register */
/*! @{ */
#define PWM_CVAL5CYC_CVAL5CYC_MASK (0xFU)
#define PWM_CVAL5CYC_CVAL5CYC_SHIFT (0U)
/*! CVAL5CYC - CVAL5CYC
*/
#define PWM_CVAL5CYC_CVAL5CYC(x) (((uint16_t)(((uint16_t)(x)) << PWM_CVAL5CYC_CVAL5CYC_SHIFT)) & PWM_CVAL5CYC_CVAL5CYC_MASK)
/*! @} */
/* The count of PWM_CVAL5CYC */
#define PWM_CVAL5CYC_COUNT (4U)
/*! @name OUTEN - Output Enable Register */
/*! @{ */
#define PWM_OUTEN_PWMX_EN_MASK (0xFU)
#define PWM_OUTEN_PWMX_EN_SHIFT (0U)
/*! PWMX_EN - PWM_X Output Enables
* 0b0000..PWM_X output disabled.
* 0b0001..PWM_X output enabled.
*/
#define PWM_OUTEN_PWMX_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMX_EN_SHIFT)) & PWM_OUTEN_PWMX_EN_MASK)
#define PWM_OUTEN_PWMB_EN_MASK (0xF0U)
#define PWM_OUTEN_PWMB_EN_SHIFT (4U)
/*! PWMB_EN - PWM_B Output Enables
* 0b0000..PWM_B output disabled.
* 0b0001..PWM_B output enabled.
*/
#define PWM_OUTEN_PWMB_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMB_EN_SHIFT)) & PWM_OUTEN_PWMB_EN_MASK)
#define PWM_OUTEN_PWMA_EN_MASK (0xF00U)
#define PWM_OUTEN_PWMA_EN_SHIFT (8U)
/*! PWMA_EN - PWM_A Output Enables
* 0b0000..PWM_A output disabled.
* 0b0001..PWM_A output enabled.
*/
#define PWM_OUTEN_PWMA_EN(x) (((uint16_t)(((uint16_t)(x)) << PWM_OUTEN_PWMA_EN_SHIFT)) & PWM_OUTEN_PWMA_EN_MASK)
/*! @} */
/*! @name MASK - Mask Register */
/*! @{ */
#define PWM_MASK_MASKX_MASK (0xFU)
#define PWM_MASK_MASKX_SHIFT (0U)
/*! MASKX - PWM_X Masks
* 0b0000..PWM_X output normal.
* 0b0001..PWM_X output masked.
*/
#define PWM_MASK_MASKX(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKX_SHIFT)) & PWM_MASK_MASKX_MASK)
#define PWM_MASK_MASKB_MASK (0xF0U)
#define PWM_MASK_MASKB_SHIFT (4U)
/*! MASKB - PWM_B Masks
* 0b0000..PWM_B output normal.
* 0b0001..PWM_B output masked.
*/
#define PWM_MASK_MASKB(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKB_SHIFT)) & PWM_MASK_MASKB_MASK)
#define PWM_MASK_MASKA_MASK (0xF00U)
#define PWM_MASK_MASKA_SHIFT (8U)
/*! MASKA - PWM_A Masks
* 0b0000..PWM_A output normal.
* 0b0001..PWM_A output masked.
*/
#define PWM_MASK_MASKA(x) (((uint16_t)(((uint16_t)(x)) << PWM_MASK_MASKA_SHIFT)) & PWM_MASK_MASKA_MASK)
/*! @} */
/*! @name SWCOUT - Software Controlled Output Register */
/*! @{ */
#define PWM_SWCOUT_SM0OUT45_MASK (0x1U)
#define PWM_SWCOUT_SM0OUT45_SHIFT (0U)
/*! SM0OUT45 - Submodule 0 Software Controlled Output 45
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM45.
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM45.
*/
#define PWM_SWCOUT_SM0OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT45_SHIFT)) & PWM_SWCOUT_SM0OUT45_MASK)
#define PWM_SWCOUT_SM0OUT23_MASK (0x2U)
#define PWM_SWCOUT_SM0OUT23_SHIFT (1U)
/*! SM0OUT23 - Submodule 0 Software Controlled Output 23
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 0 instead of PWM23.
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 0 instead of PWM23.
*/
#define PWM_SWCOUT_SM0OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM0OUT23_SHIFT)) & PWM_SWCOUT_SM0OUT23_MASK)
#define PWM_SWCOUT_SM1OUT45_MASK (0x4U)
#define PWM_SWCOUT_SM1OUT45_SHIFT (2U)
/*! SM1OUT45 - Submodule 1 Software Controlled Output 45
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM45.
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM45.
*/
#define PWM_SWCOUT_SM1OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT45_SHIFT)) & PWM_SWCOUT_SM1OUT45_MASK)
#define PWM_SWCOUT_SM1OUT23_MASK (0x8U)
#define PWM_SWCOUT_SM1OUT23_SHIFT (3U)
/*! SM1OUT23 - Submodule 1 Software Controlled Output 23
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 1 instead of PWM23.
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 1 instead of PWM23.
*/
#define PWM_SWCOUT_SM1OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM1OUT23_SHIFT)) & PWM_SWCOUT_SM1OUT23_MASK)
#define PWM_SWCOUT_SM2OUT45_MASK (0x10U)
#define PWM_SWCOUT_SM2OUT45_SHIFT (4U)
/*! SM2OUT45 - Submodule 2 Software Controlled Output 45
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM45.
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM45.
*/
#define PWM_SWCOUT_SM2OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT45_SHIFT)) & PWM_SWCOUT_SM2OUT45_MASK)
#define PWM_SWCOUT_SM2OUT23_MASK (0x20U)
#define PWM_SWCOUT_SM2OUT23_SHIFT (5U)
/*! SM2OUT23 - Submodule 2 Software Controlled Output 23
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 2 instead of PWM23.
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 2 instead of PWM23.
*/
#define PWM_SWCOUT_SM2OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM2OUT23_SHIFT)) & PWM_SWCOUT_SM2OUT23_MASK)
#define PWM_SWCOUT_SM3OUT45_MASK (0x40U)
#define PWM_SWCOUT_SM3OUT45_SHIFT (6U)
/*! SM3OUT45 - Submodule 3 Software Controlled Output 45
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM45.
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM45.
*/
#define PWM_SWCOUT_SM3OUT45(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT45_SHIFT)) & PWM_SWCOUT_SM3OUT45_MASK)
#define PWM_SWCOUT_SM3OUT23_MASK (0x80U)
#define PWM_SWCOUT_SM3OUT23_SHIFT (7U)
/*! SM3OUT23 - Submodule 3 Software Controlled Output 23
* 0b0..A logic 0 is supplied to the deadtime generator of submodule 3 instead of PWM23.
* 0b1..A logic 1 is supplied to the deadtime generator of submodule 3 instead of PWM23.
*/
#define PWM_SWCOUT_SM3OUT23(x) (((uint16_t)(((uint16_t)(x)) << PWM_SWCOUT_SM3OUT23_SHIFT)) & PWM_SWCOUT_SM3OUT23_MASK)
/*! @} */
/*! @name DTSRCSEL - PWM Source Select Register */
/*! @{ */
#define PWM_DTSRCSEL_SM0SEL45_MASK (0x3U)
#define PWM_DTSRCSEL_SM0SEL45_SHIFT (0U)
/*! SM0SEL45 - Submodule 0 PWM45 Control Select
* 0b00..Generated SM0PWM45 signal is used by the deadtime logic.
* 0b01..Inverted generated SM0PWM45 signal is used by the deadtime logic.
* 0b10..SWCOUT[SM0OUT45] is used by the deadtime logic.
* 0b11..PWM0_EXTB signal is used by the deadtime logic.
*/
#define PWM_DTSRCSEL_SM0SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL45_SHIFT)) & PWM_DTSRCSEL_SM0SEL45_MASK)
#define PWM_DTSRCSEL_SM0SEL23_MASK (0xCU)
#define PWM_DTSRCSEL_SM0SEL23_SHIFT (2U)
/*! SM0SEL23 - Submodule 0 PWM23 Control Select
* 0b00..Generated SM0PWM23 signal is used by the deadtime logic.
* 0b01..Inverted generated SM0PWM23 signal is used by the deadtime logic.
* 0b10..SWCOUT[SM0OUT23] is used by the deadtime logic.
* 0b11..PWM0_EXTA signal is used by the deadtime logic.
*/
#define PWM_DTSRCSEL_SM0SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM0SEL23_SHIFT)) & PWM_DTSRCSEL_SM0SEL23_MASK)
#define PWM_DTSRCSEL_SM1SEL45_MASK (0x30U)
#define PWM_DTSRCSEL_SM1SEL45_SHIFT (4U)
/*! SM1SEL45 - Submodule 1 PWM45 Control Select
* 0b00..Generated SM1PWM45 signal is used by the deadtime logic.
* 0b01..Inverted generated SM1PWM45 signal is used by the deadtime logic.
* 0b10..SWCOUT[SM1OUT45] is used by the deadtime logic.
* 0b11..PWM1_EXTB signal is used by the deadtime logic.
*/
#define PWM_DTSRCSEL_SM1SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL45_SHIFT)) & PWM_DTSRCSEL_SM1SEL45_MASK)
#define PWM_DTSRCSEL_SM1SEL23_MASK (0xC0U)
#define PWM_DTSRCSEL_SM1SEL23_SHIFT (6U)
/*! SM1SEL23 - Submodule 1 PWM23 Control Select
* 0b00..Generated SM1PWM23 signal is used by the deadtime logic.
* 0b01..Inverted generated SM1PWM23 signal is used by the deadtime logic.
* 0b10..SWCOUT[SM1OUT23] is used by the deadtime logic.
* 0b11..PWM1_EXTA signal is used by the deadtime logic.
*/
#define PWM_DTSRCSEL_SM1SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM1SEL23_SHIFT)) & PWM_DTSRCSEL_SM1SEL23_MASK)
#define PWM_DTSRCSEL_SM2SEL45_MASK (0x300U)
#define PWM_DTSRCSEL_SM2SEL45_SHIFT (8U)
/*! SM2SEL45 - Submodule 2 PWM45 Control Select
* 0b00..Generated SM2PWM45 signal is used by the deadtime logic.
* 0b01..Inverted generated SM2PWM45 signal is used by the deadtime logic.
* 0b10..SWCOUT[SM2OUT45] is used by the deadtime logic.
* 0b11..PWM2_EXTB signal is used by the deadtime logic.
*/
#define PWM_DTSRCSEL_SM2SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL45_SHIFT)) & PWM_DTSRCSEL_SM2SEL45_MASK)
#define PWM_DTSRCSEL_SM2SEL23_MASK (0xC00U)
#define PWM_DTSRCSEL_SM2SEL23_SHIFT (10U)
/*! SM2SEL23 - Submodule 2 PWM23 Control Select
* 0b00..Generated SM2PWM23 signal is used by the deadtime logic.
* 0b01..Inverted generated SM2PWM23 signal is used by the deadtime logic.
* 0b10..SWCOUT[SM2OUT23] is used by the deadtime logic.
* 0b11..PWM2_EXTA signal is used by the deadtime logic.
*/
#define PWM_DTSRCSEL_SM2SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM2SEL23_SHIFT)) & PWM_DTSRCSEL_SM2SEL23_MASK)
#define PWM_DTSRCSEL_SM3SEL45_MASK (0x3000U)
#define PWM_DTSRCSEL_SM3SEL45_SHIFT (12U)
/*! SM3SEL45 - Submodule 3 PWM45 Control Select
* 0b00..Generated SM3PWM45 signal is used by the deadtime logic.
* 0b01..Inverted generated SM3PWM45 signal is used by the deadtime logic.
* 0b10..SWCOUT[SM3OUT45] is used by the deadtime logic.
* 0b11..PWM3_EXTB signal is used by the deadtime logic.
*/
#define PWM_DTSRCSEL_SM3SEL45(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL45_SHIFT)) & PWM_DTSRCSEL_SM3SEL45_MASK)
#define PWM_DTSRCSEL_SM3SEL23_MASK (0xC000U)
#define PWM_DTSRCSEL_SM3SEL23_SHIFT (14U)
/*! SM3SEL23 - Submodule 3 PWM23 Control Select
* 0b00..Generated SM3PWM23 signal is used by the deadtime logic.
* 0b01..Inverted generated SM3PWM23 signal is used by the deadtime logic.
* 0b10..SWCOUT[SM3OUT23] is used by the deadtime logic.
* 0b11..PWM3_EXTA signal is used by the deadtime logic.
*/
#define PWM_DTSRCSEL_SM3SEL23(x) (((uint16_t)(((uint16_t)(x)) << PWM_DTSRCSEL_SM3SEL23_SHIFT)) & PWM_DTSRCSEL_SM3SEL23_MASK)
/*! @} */
/*! @name MCTRL - Master Control Register */
/*! @{ */
#define PWM_MCTRL_LDOK_MASK (0xFU)
#define PWM_MCTRL_LDOK_SHIFT (0U)
/*! LDOK - Load Okay
* 0b0000..Do not load new values.
* 0b0001..Load prescaler, modulus, and PWM values of the corresponding submodule.
*/
#define PWM_MCTRL_LDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_LDOK_SHIFT)) & PWM_MCTRL_LDOK_MASK)
#define PWM_MCTRL_CLDOK_MASK (0xF0U)
#define PWM_MCTRL_CLDOK_SHIFT (4U)
/*! CLDOK - Clear Load Okay
*/
#define PWM_MCTRL_CLDOK(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_CLDOK_SHIFT)) & PWM_MCTRL_CLDOK_MASK)
#define PWM_MCTRL_RUN_MASK (0xF00U)
#define PWM_MCTRL_RUN_SHIFT (8U)
/*! RUN - Run
* 0b0000..PWM counter is stopped, but PWM outputs will hold the current state.
* 0b0001..PWM counter is started in the corresponding submodule.
*/
#define PWM_MCTRL_RUN(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_RUN_SHIFT)) & PWM_MCTRL_RUN_MASK)
#define PWM_MCTRL_IPOL_MASK (0xF000U)
#define PWM_MCTRL_IPOL_SHIFT (12U)
/*! IPOL - Current Polarity
* 0b0000..PWM23 is used to generate complementary PWM pair in the corresponding submodule.
* 0b0001..PWM45 is used to generate complementary PWM pair in the corresponding submodule.
*/
#define PWM_MCTRL_IPOL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL_IPOL_SHIFT)) & PWM_MCTRL_IPOL_MASK)
/*! @} */
/*! @name MCTRL2 - Master Control 2 Register */
/*! @{ */
#define PWM_MCTRL2_MONPLL_MASK (0x3U)
#define PWM_MCTRL2_MONPLL_SHIFT (0U)
/*! MONPLL - Monitor PLL State
* 0b00..Not locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock will be controlled by software.
* 0b01..Not locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL encounters problems.
* 0b10..Locked. Do not monitor PLL operation. Resetting of the fractional delay block in case of PLL losing lock
* will be controlled by software. These bits are write protected until the next reset.
* 0b11..Locked. Monitor PLL operation to automatically disable the fractional delay block when the PLL
* encounters problems. These bits are write protected until the next reset.
*/
#define PWM_MCTRL2_MONPLL(x) (((uint16_t)(((uint16_t)(x)) << PWM_MCTRL2_MONPLL_SHIFT)) & PWM_MCTRL2_MONPLL_MASK)
/*! @} */
/*! @name FCTRL - Fault Control Register */
/*! @{ */
#define PWM_FCTRL_FIE_MASK (0xFU)
#define PWM_FCTRL_FIE_SHIFT (0U)
/*! FIE - Fault Interrupt Enables
* 0b0000..FAULTx CPU interrupt requests disabled.
* 0b0001..FAULTx CPU interrupt requests enabled.
*/
#define PWM_FCTRL_FIE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FIE_SHIFT)) & PWM_FCTRL_FIE_MASK)
#define PWM_FCTRL_FSAFE_MASK (0xF0U)
#define PWM_FCTRL_FSAFE_SHIFT (4U)
/*! FSAFE - Fault Safety Mode
* 0b0000..Normal mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear at the
* start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without regard
* to the state of FSTS[FFPINx]. If neither FHALF nor FFULL is set then the fault condition cannot be
* cleared. The PWM outputs disabled by this fault input will not be re-enabled until the actual FAULTx input
* signal de-asserts since the fault input will combinationally disable the PWM outputs (as programmed in
* DISMAPn).
* 0b0001..Safe mode. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear and
* FSTS[FFPINx] is clear at the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and
* FSTS[FFULL]. If neither FHLAF nor FFULL is set, then the fault condition cannot be cleared.
*/
#define PWM_FCTRL_FSAFE(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FSAFE_SHIFT)) & PWM_FCTRL_FSAFE_MASK)
#define PWM_FCTRL_FAUTO_MASK (0xF00U)
#define PWM_FCTRL_FAUTO_SHIFT (8U)
/*! FAUTO - Automatic Fault Clearing
* 0b0000..Manual fault clearing. PWM outputs disabled by this fault are not enabled until FSTS[FFLAGx] is clear
* at the start of a half cycle or full cycle depending the states of FSTS[FHALF] and FSTS[FFULL]. If
* neither FFULL nor FHALF is set, then the fault condition cannot be cleared. This is further controlled by
* FCTRL[FSAFE].
* 0b0001..Automatic fault clearing. PWM outputs disabled by this fault are enabled when FSTS[FFPINx] is clear at
* the start of a half cycle or full cycle depending on the states of FSTS[FHALF] and FSTS[FFULL] without
* regard to the state of FSTS[FFLAGx]. If neither FFULL nor FHALF is set, then the fault condition
* cannot be cleared.
*/
#define PWM_FCTRL_FAUTO(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FAUTO_SHIFT)) & PWM_FCTRL_FAUTO_MASK)
#define PWM_FCTRL_FLVL_MASK (0xF000U)
#define PWM_FCTRL_FLVL_SHIFT (12U)
/*! FLVL - Fault Level
* 0b0000..A logic 0 on the fault input indicates a fault condition.
* 0b0001..A logic 1 on the fault input indicates a fault condition.
*/
#define PWM_FCTRL_FLVL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL_FLVL_SHIFT)) & PWM_FCTRL_FLVL_MASK)
/*! @} */
/*! @name FSTS - Fault Status Register */
/*! @{ */
#define PWM_FSTS_FFLAG_MASK (0xFU)
#define PWM_FSTS_FFLAG_SHIFT (0U)
/*! FFLAG - Fault Flags
* 0b0000..No fault on the FAULTx pin.
* 0b0001..Fault on the FAULTx pin.
*/
#define PWM_FSTS_FFLAG(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFLAG_SHIFT)) & PWM_FSTS_FFLAG_MASK)
#define PWM_FSTS_FFULL_MASK (0xF0U)
#define PWM_FSTS_FFULL_SHIFT (4U)
/*! FFULL - Full Cycle
* 0b0000..PWM outputs are not re-enabled at the start of a full cycle
* 0b0001..PWM outputs are re-enabled at the start of a full cycle
*/
#define PWM_FSTS_FFULL(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFULL_SHIFT)) & PWM_FSTS_FFULL_MASK)
#define PWM_FSTS_FFPIN_MASK (0xF00U)
#define PWM_FSTS_FFPIN_SHIFT (8U)
/*! FFPIN - Filtered Fault Pins
*/
#define PWM_FSTS_FFPIN(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FFPIN_SHIFT)) & PWM_FSTS_FFPIN_MASK)
#define PWM_FSTS_FHALF_MASK (0xF000U)
#define PWM_FSTS_FHALF_SHIFT (12U)
/*! FHALF - Half Cycle Fault Recovery
* 0b0000..PWM outputs are not re-enabled at the start of a half cycle.
* 0b0001..PWM outputs are re-enabled at the start of a half cycle (as defined by VAL0).
*/
#define PWM_FSTS_FHALF(x) (((uint16_t)(((uint16_t)(x)) << PWM_FSTS_FHALF_SHIFT)) & PWM_FSTS_FHALF_MASK)
/*! @} */
/*! @name FFILT - Fault Filter Register */
/*! @{ */
#define PWM_FFILT_FILT_PER_MASK (0xFFU)
#define PWM_FFILT_FILT_PER_SHIFT (0U)
/*! FILT_PER - Fault Filter Period
*/
#define PWM_FFILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_PER_SHIFT)) & PWM_FFILT_FILT_PER_MASK)
#define PWM_FFILT_FILT_CNT_MASK (0x700U)
#define PWM_FFILT_FILT_CNT_SHIFT (8U)
/*! FILT_CNT - Fault Filter Count
*/
#define PWM_FFILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_FILT_CNT_SHIFT)) & PWM_FFILT_FILT_CNT_MASK)
#define PWM_FFILT_GSTR_MASK (0x8000U)
#define PWM_FFILT_GSTR_SHIFT (15U)
/*! GSTR - Fault Glitch Stretch Enable
* 0b0..Fault input glitch stretching is disabled.
* 0b1..Input fault signals will be stretched to at least 2 IPBus clock cycles.
*/
#define PWM_FFILT_GSTR(x) (((uint16_t)(((uint16_t)(x)) << PWM_FFILT_GSTR_SHIFT)) & PWM_FFILT_GSTR_MASK)
/*! @} */
/*! @name FTST - Fault Test Register */
/*! @{ */
#define PWM_FTST_FTEST_MASK (0x1U)
#define PWM_FTST_FTEST_SHIFT (0U)
/*! FTEST - Fault Test
* 0b0..No fault
* 0b1..Cause a simulated fault
*/
#define PWM_FTST_FTEST(x) (((uint16_t)(((uint16_t)(x)) << PWM_FTST_FTEST_SHIFT)) & PWM_FTST_FTEST_MASK)
/*! @} */
/*! @name FCTRL2 - Fault Control 2 Register */
/*! @{ */
#define PWM_FCTRL2_NOCOMB_MASK (0xFU)
#define PWM_FCTRL2_NOCOMB_SHIFT (0U)
/*! NOCOMB - No Combinational Path From Fault Input To PWM Output
* 0b0000..There is a combinational link from the fault inputs to the PWM outputs. The fault inputs are combined
* with the filtered and latched fault signals to disable the PWM outputs.
* 0b0001..The direct combinational path from the fault inputs to the PWM outputs is disabled and the filtered
* and latched fault signals are used to disable the PWM outputs.
*/
#define PWM_FCTRL2_NOCOMB(x) (((uint16_t)(((uint16_t)(x)) << PWM_FCTRL2_NOCOMB_SHIFT)) & PWM_FCTRL2_NOCOMB_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PWM_Register_Masks */
/* PWM - Peripheral instance base addresses */
/** Peripheral PWM1 base address */
#define PWM1_BASE (0x4018C000u)
/** Peripheral PWM1 base pointer */
#define PWM1 ((PWM_Type *)PWM1_BASE)
/** Peripheral PWM2 base address */
#define PWM2_BASE (0x40190000u)
/** Peripheral PWM2 base pointer */
#define PWM2 ((PWM_Type *)PWM2_BASE)
/** Peripheral PWM3 base address */
#define PWM3_BASE (0x40194000u)
/** Peripheral PWM3 base pointer */
#define PWM3 ((PWM_Type *)PWM3_BASE)
/** Peripheral PWM4 base address */
#define PWM4_BASE (0x40198000u)
/** Peripheral PWM4 base pointer */
#define PWM4 ((PWM_Type *)PWM4_BASE)
/** Array initializer of PWM peripheral base addresses */
#define PWM_BASE_ADDRS { 0u, PWM1_BASE, PWM2_BASE, PWM3_BASE, PWM4_BASE }
/** Array initializer of PWM peripheral base pointers */
#define PWM_BASE_PTRS { (PWM_Type *)0u, PWM1, PWM2, PWM3, PWM4 }
/** Interrupt vectors for the PWM peripheral type */
#define PWM_CMP_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define PWM_RELOAD_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define PWM_CAPTURE_IRQS { { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }, { PWM1_0_IRQn, PWM1_1_IRQn, PWM1_2_IRQn, PWM1_3_IRQn }, { PWM2_0_IRQn, PWM2_1_IRQn, PWM2_2_IRQn, PWM2_3_IRQn }, { PWM3_0_IRQn, PWM3_1_IRQn, PWM3_2_IRQn, PWM3_3_IRQn }, { PWM4_0_IRQn, PWM4_1_IRQn, PWM4_2_IRQn, PWM4_3_IRQn } }
#define PWM_FAULT_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
#define PWM_RELOAD_ERROR_IRQS { NotAvail_IRQn, PWM1_FAULT_IRQn, PWM2_FAULT_IRQn, PWM3_FAULT_IRQn, PWM4_FAULT_IRQn }
/*!
* @}
*/ /* end of group PWM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- PXP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup PXP_Peripheral_Access_Layer PXP Peripheral Access Layer
* @{
*/
/** PXP - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL; /**< Control Register 0, offset: 0x0 */
__IO uint32_t CTRL_SET; /**< Control Register 0, offset: 0x4 */
__IO uint32_t CTRL_CLR; /**< Control Register 0, offset: 0x8 */
__IO uint32_t CTRL_TOG; /**< Control Register 0, offset: 0xC */
__IO uint32_t STAT; /**< Status Register, offset: 0x10 */
__IO uint32_t STAT_SET; /**< Status Register, offset: 0x14 */
__IO uint32_t STAT_CLR; /**< Status Register, offset: 0x18 */
__IO uint32_t STAT_TOG; /**< Status Register, offset: 0x1C */
__IO uint32_t OUT_CTRL; /**< Output Buffer Control Register, offset: 0x20 */
__IO uint32_t OUT_CTRL_SET; /**< Output Buffer Control Register, offset: 0x24 */
__IO uint32_t OUT_CTRL_CLR; /**< Output Buffer Control Register, offset: 0x28 */
__IO uint32_t OUT_CTRL_TOG; /**< Output Buffer Control Register, offset: 0x2C */
__IO uint32_t OUT_BUF; /**< Output Frame Buffer Pointer, offset: 0x30 */
uint8_t RESERVED_0[12];
__IO uint32_t OUT_BUF2; /**< Output Frame Buffer Pointer #2, offset: 0x40 */
uint8_t RESERVED_1[12];
__IO uint32_t OUT_PITCH; /**< Output Buffer Pitch, offset: 0x50 */
uint8_t RESERVED_2[12];
__IO uint32_t OUT_LRC; /**< Output Surface Lower Right Coordinate, offset: 0x60 */
uint8_t RESERVED_3[12];
__IO uint32_t OUT_PS_ULC; /**< Processed Surface Upper Left Coordinate, offset: 0x70 */
uint8_t RESERVED_4[12];
__IO uint32_t OUT_PS_LRC; /**< Processed Surface Lower Right Coordinate, offset: 0x80 */
uint8_t RESERVED_5[12];
__IO uint32_t OUT_AS_ULC; /**< Alpha Surface Upper Left Coordinate, offset: 0x90 */
uint8_t RESERVED_6[12];
__IO uint32_t OUT_AS_LRC; /**< Alpha Surface Lower Right Coordinate, offset: 0xA0 */
uint8_t RESERVED_7[12];
__IO uint32_t PS_CTRL; /**< Processed Surface (PS) Control Register, offset: 0xB0 */
__IO uint32_t PS_CTRL_SET; /**< Processed Surface (PS) Control Register, offset: 0xB4 */
__IO uint32_t PS_CTRL_CLR; /**< Processed Surface (PS) Control Register, offset: 0xB8 */
__IO uint32_t PS_CTRL_TOG; /**< Processed Surface (PS) Control Register, offset: 0xBC */
__IO uint32_t PS_BUF; /**< PS Input Buffer Address, offset: 0xC0 */
uint8_t RESERVED_8[12];
__IO uint32_t PS_UBUF; /**< PS U/Cb or 2 Plane UV Input Buffer Address, offset: 0xD0 */
uint8_t RESERVED_9[12];
__IO uint32_t PS_VBUF; /**< PS V/Cr Input Buffer Address, offset: 0xE0 */
uint8_t RESERVED_10[12];
__IO uint32_t PS_PITCH; /**< Processed Surface Pitch, offset: 0xF0 */
uint8_t RESERVED_11[12];
__IO uint32_t PS_BACKGROUND; /**< PS Background Color, offset: 0x100 */
uint8_t RESERVED_12[12];
__IO uint32_t PS_SCALE; /**< PS Scale Factor Register, offset: 0x110 */
uint8_t RESERVED_13[12];
__IO uint32_t PS_OFFSET; /**< PS Scale Offset Register, offset: 0x120 */
uint8_t RESERVED_14[12];
__IO uint32_t PS_CLRKEYLOW; /**< PS Color Key Low, offset: 0x130 */
uint8_t RESERVED_15[12];
__IO uint32_t PS_CLRKEYHIGH; /**< PS Color Key High, offset: 0x140 */
uint8_t RESERVED_16[12];
__IO uint32_t AS_CTRL; /**< Alpha Surface Control, offset: 0x150 */
uint8_t RESERVED_17[12];
__IO uint32_t AS_BUF; /**< Alpha Surface Buffer Pointer, offset: 0x160 */
uint8_t RESERVED_18[12];
__IO uint32_t AS_PITCH; /**< Alpha Surface Pitch, offset: 0x170 */
uint8_t RESERVED_19[12];
__IO uint32_t AS_CLRKEYLOW; /**< Overlay Color Key Low, offset: 0x180 */
uint8_t RESERVED_20[12];
__IO uint32_t AS_CLRKEYHIGH; /**< Overlay Color Key High, offset: 0x190 */
uint8_t RESERVED_21[12];
__IO uint32_t CSC1_COEF0; /**< Color Space Conversion Coefficient Register 0, offset: 0x1A0 */
uint8_t RESERVED_22[12];
__IO uint32_t CSC1_COEF1; /**< Color Space Conversion Coefficient Register 1, offset: 0x1B0 */
uint8_t RESERVED_23[12];
__IO uint32_t CSC1_COEF2; /**< Color Space Conversion Coefficient Register 2, offset: 0x1C0 */
uint8_t RESERVED_24[348];
__IO uint32_t POWER; /**< PXP Power Control Register, offset: 0x320 */
uint8_t RESERVED_25[220];
__IO uint32_t NEXT; /**< Next Frame Pointer, offset: 0x400 */
uint8_t RESERVED_26[60];
__IO uint32_t PORTER_DUFF_CTRL; /**< PXP Alpha Engine A Control Register., offset: 0x440 */
} PXP_Type;
/* ----------------------------------------------------------------------------
-- PXP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup PXP_Register_Masks PXP Register Masks
* @{
*/
/*! @name CTRL - Control Register 0 */
/*! @{ */
#define PXP_CTRL_ENABLE_MASK (0x1U)
#define PXP_CTRL_ENABLE_SHIFT (0U)
/*! ENABLE
* 0b1..PXP is enabled
* 0b0..PXP is disabled
*/
#define PXP_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_SHIFT)) & PXP_CTRL_ENABLE_MASK)
#define PXP_CTRL_IRQ_ENABLE_MASK (0x2U)
#define PXP_CTRL_IRQ_ENABLE_SHIFT (1U)
/*! IRQ_ENABLE
* 0b1..PXP interrupt is enabled
* 0b0..PXP interrupt is disabled
*/
#define PXP_CTRL_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_IRQ_ENABLE_SHIFT)) & PXP_CTRL_IRQ_ENABLE_MASK)
#define PXP_CTRL_NEXT_IRQ_ENABLE_MASK (0x4U)
#define PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT (2U)
/*! NEXT_IRQ_ENABLE
* 0b0..Disabled
* 0b1..Enabled
*/
#define PXP_CTRL_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_NEXT_IRQ_ENABLE_MASK)
#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define PXP_CTRL_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_ENABLE_LCD_HANDSHAKE_MASK)
#define PXP_CTRL_ROTATE_MASK (0x300U)
#define PXP_CTRL_ROTATE_SHIFT (8U)
/*! ROTATE
* 0b00..ROT_0
* 0b01..ROT_90
* 0b10..ROT_180
* 0b11..ROT_270
*/
#define PXP_CTRL_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROTATE_SHIFT)) & PXP_CTRL_ROTATE_MASK)
#define PXP_CTRL_HFLIP_MASK (0x400U)
#define PXP_CTRL_HFLIP_SHIFT (10U)
/*! HFLIP
* 0b0..Horizontal Flip is disabled
* 0b1..Horizontal Flip is enabled
*/
#define PXP_CTRL_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_HFLIP_SHIFT)) & PXP_CTRL_HFLIP_MASK)
#define PXP_CTRL_VFLIP_MASK (0x800U)
#define PXP_CTRL_VFLIP_SHIFT (11U)
/*! VFLIP
* 0b0..Vertical Flip is disabled
* 0b1..Vertical Flip is enabled
*/
#define PXP_CTRL_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_VFLIP_SHIFT)) & PXP_CTRL_VFLIP_MASK)
#define PXP_CTRL_ROT_POS_MASK (0x400000U)
#define PXP_CTRL_ROT_POS_SHIFT (22U)
#define PXP_CTRL_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_ROT_POS_SHIFT)) & PXP_CTRL_ROT_POS_MASK)
#define PXP_CTRL_BLOCK_SIZE_MASK (0x800000U)
#define PXP_CTRL_BLOCK_SIZE_SHIFT (23U)
/*! BLOCK_SIZE
* 0b0..Process 8x8 pixel blocks.
* 0b1..Process 16x16 pixel blocks.
*/
#define PXP_CTRL_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_BLOCK_SIZE_SHIFT)) & PXP_CTRL_BLOCK_SIZE_MASK)
#define PXP_CTRL_EN_REPEAT_MASK (0x10000000U)
#define PXP_CTRL_EN_REPEAT_SHIFT (28U)
/*! EN_REPEAT
* 0b1..PXP will repeat based on the current configuration register settings
* 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
*/
#define PXP_CTRL_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_EN_REPEAT_SHIFT)) & PXP_CTRL_EN_REPEAT_MASK)
#define PXP_CTRL_CLKGATE_MASK (0x40000000U)
#define PXP_CTRL_CLKGATE_SHIFT (30U)
/*! CLKGATE
* 0b0..Normal operation
* 0b1..All clocks to PXP is gated-off
*/
#define PXP_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLKGATE_SHIFT)) & PXP_CTRL_CLKGATE_MASK)
#define PXP_CTRL_SFTRST_MASK (0x80000000U)
#define PXP_CTRL_SFTRST_SHIFT (31U)
/*! SFTRST
* 0b0..Normal PXP operation is enabled
* 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
*/
#define PXP_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SFTRST_SHIFT)) & PXP_CTRL_SFTRST_MASK)
/*! @} */
/*! @name CTRL_SET - Control Register 0 */
/*! @{ */
#define PXP_CTRL_SET_ENABLE_MASK (0x1U)
#define PXP_CTRL_SET_ENABLE_SHIFT (0U)
/*! ENABLE
* 0b1..PXP is enabled
* 0b0..PXP is disabled
*/
#define PXP_CTRL_SET_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_SHIFT)) & PXP_CTRL_SET_ENABLE_MASK)
#define PXP_CTRL_SET_IRQ_ENABLE_MASK (0x2U)
#define PXP_CTRL_SET_IRQ_ENABLE_SHIFT (1U)
/*! IRQ_ENABLE
* 0b1..PXP interrupt is enabled
* 0b0..PXP interrupt is disabled
*/
#define PXP_CTRL_SET_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_IRQ_ENABLE_MASK)
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK (0x4U)
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT (2U)
/*! NEXT_IRQ_ENABLE
* 0b0..Disabled
* 0b1..Enabled
*/
#define PXP_CTRL_SET_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_SET_NEXT_IRQ_ENABLE_MASK)
#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_SET_ENABLE_LCD_HANDSHAKE_MASK)
#define PXP_CTRL_SET_ROTATE_MASK (0x300U)
#define PXP_CTRL_SET_ROTATE_SHIFT (8U)
/*! ROTATE
* 0b00..ROT_0
* 0b01..ROT_90
* 0b10..ROT_180
* 0b11..ROT_270
*/
#define PXP_CTRL_SET_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROTATE_SHIFT)) & PXP_CTRL_SET_ROTATE_MASK)
#define PXP_CTRL_SET_HFLIP_MASK (0x400U)
#define PXP_CTRL_SET_HFLIP_SHIFT (10U)
/*! HFLIP
* 0b0..Horizontal Flip is disabled
* 0b1..Horizontal Flip is enabled
*/
#define PXP_CTRL_SET_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_HFLIP_SHIFT)) & PXP_CTRL_SET_HFLIP_MASK)
#define PXP_CTRL_SET_VFLIP_MASK (0x800U)
#define PXP_CTRL_SET_VFLIP_SHIFT (11U)
/*! VFLIP
* 0b0..Vertical Flip is disabled
* 0b1..Vertical Flip is enabled
*/
#define PXP_CTRL_SET_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_VFLIP_SHIFT)) & PXP_CTRL_SET_VFLIP_MASK)
#define PXP_CTRL_SET_ROT_POS_MASK (0x400000U)
#define PXP_CTRL_SET_ROT_POS_SHIFT (22U)
#define PXP_CTRL_SET_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_ROT_POS_SHIFT)) & PXP_CTRL_SET_ROT_POS_MASK)
#define PXP_CTRL_SET_BLOCK_SIZE_MASK (0x800000U)
#define PXP_CTRL_SET_BLOCK_SIZE_SHIFT (23U)
/*! BLOCK_SIZE
* 0b0..Process 8x8 pixel blocks.
* 0b1..Process 16x16 pixel blocks.
*/
#define PXP_CTRL_SET_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_BLOCK_SIZE_SHIFT)) & PXP_CTRL_SET_BLOCK_SIZE_MASK)
#define PXP_CTRL_SET_EN_REPEAT_MASK (0x10000000U)
#define PXP_CTRL_SET_EN_REPEAT_SHIFT (28U)
/*! EN_REPEAT
* 0b1..PXP will repeat based on the current configuration register settings
* 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
*/
#define PXP_CTRL_SET_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_EN_REPEAT_SHIFT)) & PXP_CTRL_SET_EN_REPEAT_MASK)
#define PXP_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define PXP_CTRL_SET_CLKGATE_SHIFT (30U)
/*! CLKGATE
* 0b0..Normal operation
* 0b1..All clocks to PXP is gated-off
*/
#define PXP_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_CLKGATE_SHIFT)) & PXP_CTRL_SET_CLKGATE_MASK)
#define PXP_CTRL_SET_SFTRST_MASK (0x80000000U)
#define PXP_CTRL_SET_SFTRST_SHIFT (31U)
/*! SFTRST
* 0b0..Normal PXP operation is enabled
* 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
*/
#define PXP_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_SET_SFTRST_SHIFT)) & PXP_CTRL_SET_SFTRST_MASK)
/*! @} */
/*! @name CTRL_CLR - Control Register 0 */
/*! @{ */
#define PXP_CTRL_CLR_ENABLE_MASK (0x1U)
#define PXP_CTRL_CLR_ENABLE_SHIFT (0U)
/*! ENABLE
* 0b1..PXP is enabled
* 0b0..PXP is disabled
*/
#define PXP_CTRL_CLR_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_SHIFT)) & PXP_CTRL_CLR_ENABLE_MASK)
#define PXP_CTRL_CLR_IRQ_ENABLE_MASK (0x2U)
#define PXP_CTRL_CLR_IRQ_ENABLE_SHIFT (1U)
/*! IRQ_ENABLE
* 0b1..PXP interrupt is enabled
* 0b0..PXP interrupt is disabled
*/
#define PXP_CTRL_CLR_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_IRQ_ENABLE_MASK)
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK (0x4U)
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT (2U)
/*! NEXT_IRQ_ENABLE
* 0b0..Disabled
* 0b1..Enabled
*/
#define PXP_CTRL_CLR_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_CLR_NEXT_IRQ_ENABLE_MASK)
#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_CLR_ENABLE_LCD_HANDSHAKE_MASK)
#define PXP_CTRL_CLR_ROTATE_MASK (0x300U)
#define PXP_CTRL_CLR_ROTATE_SHIFT (8U)
/*! ROTATE
* 0b00..ROT_0
* 0b01..ROT_90
* 0b10..ROT_180
* 0b11..ROT_270
*/
#define PXP_CTRL_CLR_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROTATE_SHIFT)) & PXP_CTRL_CLR_ROTATE_MASK)
#define PXP_CTRL_CLR_HFLIP_MASK (0x400U)
#define PXP_CTRL_CLR_HFLIP_SHIFT (10U)
/*! HFLIP
* 0b0..Horizontal Flip is disabled
* 0b1..Horizontal Flip is enabled
*/
#define PXP_CTRL_CLR_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_HFLIP_SHIFT)) & PXP_CTRL_CLR_HFLIP_MASK)
#define PXP_CTRL_CLR_VFLIP_MASK (0x800U)
#define PXP_CTRL_CLR_VFLIP_SHIFT (11U)
/*! VFLIP
* 0b0..Vertical Flip is disabled
* 0b1..Vertical Flip is enabled
*/
#define PXP_CTRL_CLR_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_VFLIP_SHIFT)) & PXP_CTRL_CLR_VFLIP_MASK)
#define PXP_CTRL_CLR_ROT_POS_MASK (0x400000U)
#define PXP_CTRL_CLR_ROT_POS_SHIFT (22U)
#define PXP_CTRL_CLR_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_ROT_POS_SHIFT)) & PXP_CTRL_CLR_ROT_POS_MASK)
#define PXP_CTRL_CLR_BLOCK_SIZE_MASK (0x800000U)
#define PXP_CTRL_CLR_BLOCK_SIZE_SHIFT (23U)
/*! BLOCK_SIZE
* 0b0..Process 8x8 pixel blocks.
* 0b1..Process 16x16 pixel blocks.
*/
#define PXP_CTRL_CLR_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_BLOCK_SIZE_SHIFT)) & PXP_CTRL_CLR_BLOCK_SIZE_MASK)
#define PXP_CTRL_CLR_EN_REPEAT_MASK (0x10000000U)
#define PXP_CTRL_CLR_EN_REPEAT_SHIFT (28U)
/*! EN_REPEAT
* 0b1..PXP will repeat based on the current configuration register settings
* 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
*/
#define PXP_CTRL_CLR_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_EN_REPEAT_SHIFT)) & PXP_CTRL_CLR_EN_REPEAT_MASK)
#define PXP_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define PXP_CTRL_CLR_CLKGATE_SHIFT (30U)
/*! CLKGATE
* 0b0..Normal operation
* 0b1..All clocks to PXP is gated-off
*/
#define PXP_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_CLKGATE_SHIFT)) & PXP_CTRL_CLR_CLKGATE_MASK)
#define PXP_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define PXP_CTRL_CLR_SFTRST_SHIFT (31U)
/*! SFTRST
* 0b0..Normal PXP operation is enabled
* 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
*/
#define PXP_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_CLR_SFTRST_SHIFT)) & PXP_CTRL_CLR_SFTRST_MASK)
/*! @} */
/*! @name CTRL_TOG - Control Register 0 */
/*! @{ */
#define PXP_CTRL_TOG_ENABLE_MASK (0x1U)
#define PXP_CTRL_TOG_ENABLE_SHIFT (0U)
/*! ENABLE
* 0b1..PXP is enabled
* 0b0..PXP is disabled
*/
#define PXP_CTRL_TOG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_SHIFT)) & PXP_CTRL_TOG_ENABLE_MASK)
#define PXP_CTRL_TOG_IRQ_ENABLE_MASK (0x2U)
#define PXP_CTRL_TOG_IRQ_ENABLE_SHIFT (1U)
/*! IRQ_ENABLE
* 0b1..PXP interrupt is enabled
* 0b0..PXP interrupt is disabled
*/
#define PXP_CTRL_TOG_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_IRQ_ENABLE_MASK)
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK (0x4U)
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT (2U)
/*! NEXT_IRQ_ENABLE
* 0b0..Disabled
* 0b1..Enabled
*/
#define PXP_CTRL_TOG_NEXT_IRQ_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_NEXT_IRQ_ENABLE_SHIFT)) & PXP_CTRL_TOG_NEXT_IRQ_ENABLE_MASK)
#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK (0x10U)
#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT (4U)
#define PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_SHIFT)) & PXP_CTRL_TOG_ENABLE_LCD_HANDSHAKE_MASK)
#define PXP_CTRL_TOG_ROTATE_MASK (0x300U)
#define PXP_CTRL_TOG_ROTATE_SHIFT (8U)
/*! ROTATE
* 0b00..ROT_0
* 0b01..ROT_90
* 0b10..ROT_180
* 0b11..ROT_270
*/
#define PXP_CTRL_TOG_ROTATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROTATE_SHIFT)) & PXP_CTRL_TOG_ROTATE_MASK)
#define PXP_CTRL_TOG_HFLIP_MASK (0x400U)
#define PXP_CTRL_TOG_HFLIP_SHIFT (10U)
/*! HFLIP
* 0b0..Horizontal Flip is disabled
* 0b1..Horizontal Flip is enabled
*/
#define PXP_CTRL_TOG_HFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_HFLIP_SHIFT)) & PXP_CTRL_TOG_HFLIP_MASK)
#define PXP_CTRL_TOG_VFLIP_MASK (0x800U)
#define PXP_CTRL_TOG_VFLIP_SHIFT (11U)
/*! VFLIP
* 0b0..Vertical Flip is disabled
* 0b1..Vertical Flip is enabled
*/
#define PXP_CTRL_TOG_VFLIP(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_VFLIP_SHIFT)) & PXP_CTRL_TOG_VFLIP_MASK)
#define PXP_CTRL_TOG_ROT_POS_MASK (0x400000U)
#define PXP_CTRL_TOG_ROT_POS_SHIFT (22U)
#define PXP_CTRL_TOG_ROT_POS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_ROT_POS_SHIFT)) & PXP_CTRL_TOG_ROT_POS_MASK)
#define PXP_CTRL_TOG_BLOCK_SIZE_MASK (0x800000U)
#define PXP_CTRL_TOG_BLOCK_SIZE_SHIFT (23U)
/*! BLOCK_SIZE
* 0b0..Process 8x8 pixel blocks.
* 0b1..Process 16x16 pixel blocks.
*/
#define PXP_CTRL_TOG_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_BLOCK_SIZE_SHIFT)) & PXP_CTRL_TOG_BLOCK_SIZE_MASK)
#define PXP_CTRL_TOG_EN_REPEAT_MASK (0x10000000U)
#define PXP_CTRL_TOG_EN_REPEAT_SHIFT (28U)
/*! EN_REPEAT
* 0b1..PXP will repeat based on the current configuration register settings
* 0b0..PXP will complete the process and enter the idle state ready to accept the next frame to be processed
*/
#define PXP_CTRL_TOG_EN_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_EN_REPEAT_SHIFT)) & PXP_CTRL_TOG_EN_REPEAT_MASK)
#define PXP_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define PXP_CTRL_TOG_CLKGATE_SHIFT (30U)
/*! CLKGATE
* 0b0..Normal operation
* 0b1..All clocks to PXP is gated-off
*/
#define PXP_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_CLKGATE_SHIFT)) & PXP_CTRL_TOG_CLKGATE_MASK)
#define PXP_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define PXP_CTRL_TOG_SFTRST_SHIFT (31U)
/*! SFTRST
* 0b0..Normal PXP operation is enabled
* 0b1..Clocking with PXP is disabled and held in its reset (lowest power) state. This is the default value.
*/
#define PXP_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << PXP_CTRL_TOG_SFTRST_SHIFT)) & PXP_CTRL_TOG_SFTRST_MASK)
/*! @} */
/*! @name STAT - Status Register */
/*! @{ */
#define PXP_STAT_IRQ_MASK (0x1U)
#define PXP_STAT_IRQ_SHIFT (0U)
/*! IRQ
* 0b0..No interrupt
* 0b1..Interrupt generated
*/
#define PXP_STAT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_IRQ_SHIFT)) & PXP_STAT_IRQ_MASK)
#define PXP_STAT_AXI_WRITE_ERROR_MASK (0x2U)
#define PXP_STAT_AXI_WRITE_ERROR_SHIFT (1U)
/*! AXI_WRITE_ERROR
* 0b0..AXI write is normal
* 0b1..AXI write error has occurred
*/
#define PXP_STAT_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_AXI_WRITE_ERROR_MASK)
#define PXP_STAT_AXI_READ_ERROR_MASK (0x4U)
#define PXP_STAT_AXI_READ_ERROR_SHIFT (2U)
/*! AXI_READ_ERROR
* 0b0..AXI read is normal
* 0b1..AXI read error has occurred
*/
#define PXP_STAT_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_READ_ERROR_SHIFT)) & PXP_STAT_AXI_READ_ERROR_MASK)
#define PXP_STAT_NEXT_IRQ_MASK (0x8U)
#define PXP_STAT_NEXT_IRQ_SHIFT (3U)
#define PXP_STAT_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_NEXT_IRQ_SHIFT)) & PXP_STAT_NEXT_IRQ_MASK)
#define PXP_STAT_AXI_ERROR_ID_MASK (0xF0U)
#define PXP_STAT_AXI_ERROR_ID_SHIFT (4U)
#define PXP_STAT_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_AXI_ERROR_ID_SHIFT)) & PXP_STAT_AXI_ERROR_ID_MASK)
#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
/*! LUT_DMA_LOAD_DONE_IRQ
* 0b0..LUT DMA LOAD transfer is active
* 0b1..LUT DMA LOAD transfer is complete
*/
#define PXP_STAT_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define PXP_STAT_BLOCKY_MASK (0xFF0000U)
#define PXP_STAT_BLOCKY_SHIFT (16U)
#define PXP_STAT_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKY_SHIFT)) & PXP_STAT_BLOCKY_MASK)
#define PXP_STAT_BLOCKX_MASK (0xFF000000U)
#define PXP_STAT_BLOCKX_SHIFT (24U)
#define PXP_STAT_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_BLOCKX_SHIFT)) & PXP_STAT_BLOCKX_MASK)
/*! @} */
/*! @name STAT_SET - Status Register */
/*! @{ */
#define PXP_STAT_SET_IRQ_MASK (0x1U)
#define PXP_STAT_SET_IRQ_SHIFT (0U)
/*! IRQ
* 0b0..No interrupt
* 0b1..Interrupt generated
*/
#define PXP_STAT_SET_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_IRQ_SHIFT)) & PXP_STAT_SET_IRQ_MASK)
#define PXP_STAT_SET_AXI_WRITE_ERROR_MASK (0x2U)
#define PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT (1U)
/*! AXI_WRITE_ERROR
* 0b0..AXI write is normal
* 0b1..AXI write error has occurred
*/
#define PXP_STAT_SET_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_SET_AXI_WRITE_ERROR_MASK)
#define PXP_STAT_SET_AXI_READ_ERROR_MASK (0x4U)
#define PXP_STAT_SET_AXI_READ_ERROR_SHIFT (2U)
/*! AXI_READ_ERROR
* 0b0..AXI read is normal
* 0b1..AXI read error has occurred
*/
#define PXP_STAT_SET_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_READ_ERROR_SHIFT)) & PXP_STAT_SET_AXI_READ_ERROR_MASK)
#define PXP_STAT_SET_NEXT_IRQ_MASK (0x8U)
#define PXP_STAT_SET_NEXT_IRQ_SHIFT (3U)
#define PXP_STAT_SET_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_NEXT_IRQ_SHIFT)) & PXP_STAT_SET_NEXT_IRQ_MASK)
#define PXP_STAT_SET_AXI_ERROR_ID_MASK (0xF0U)
#define PXP_STAT_SET_AXI_ERROR_ID_SHIFT (4U)
#define PXP_STAT_SET_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_AXI_ERROR_ID_SHIFT)) & PXP_STAT_SET_AXI_ERROR_ID_MASK)
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
/*! LUT_DMA_LOAD_DONE_IRQ
* 0b0..LUT DMA LOAD transfer is active
* 0b1..LUT DMA LOAD transfer is complete
*/
#define PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_SET_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define PXP_STAT_SET_BLOCKY_MASK (0xFF0000U)
#define PXP_STAT_SET_BLOCKY_SHIFT (16U)
#define PXP_STAT_SET_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKY_SHIFT)) & PXP_STAT_SET_BLOCKY_MASK)
#define PXP_STAT_SET_BLOCKX_MASK (0xFF000000U)
#define PXP_STAT_SET_BLOCKX_SHIFT (24U)
#define PXP_STAT_SET_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_SET_BLOCKX_SHIFT)) & PXP_STAT_SET_BLOCKX_MASK)
/*! @} */
/*! @name STAT_CLR - Status Register */
/*! @{ */
#define PXP_STAT_CLR_IRQ_MASK (0x1U)
#define PXP_STAT_CLR_IRQ_SHIFT (0U)
/*! IRQ
* 0b0..No interrupt
* 0b1..Interrupt generated
*/
#define PXP_STAT_CLR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_IRQ_SHIFT)) & PXP_STAT_CLR_IRQ_MASK)
#define PXP_STAT_CLR_AXI_WRITE_ERROR_MASK (0x2U)
#define PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT (1U)
/*! AXI_WRITE_ERROR
* 0b0..AXI write is normal
* 0b1..AXI write error has occurred
*/
#define PXP_STAT_CLR_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_WRITE_ERROR_MASK)
#define PXP_STAT_CLR_AXI_READ_ERROR_MASK (0x4U)
#define PXP_STAT_CLR_AXI_READ_ERROR_SHIFT (2U)
/*! AXI_READ_ERROR
* 0b0..AXI read is normal
* 0b1..AXI read error has occurred
*/
#define PXP_STAT_CLR_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_READ_ERROR_SHIFT)) & PXP_STAT_CLR_AXI_READ_ERROR_MASK)
#define PXP_STAT_CLR_NEXT_IRQ_MASK (0x8U)
#define PXP_STAT_CLR_NEXT_IRQ_SHIFT (3U)
#define PXP_STAT_CLR_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_NEXT_IRQ_SHIFT)) & PXP_STAT_CLR_NEXT_IRQ_MASK)
#define PXP_STAT_CLR_AXI_ERROR_ID_MASK (0xF0U)
#define PXP_STAT_CLR_AXI_ERROR_ID_SHIFT (4U)
#define PXP_STAT_CLR_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_AXI_ERROR_ID_SHIFT)) & PXP_STAT_CLR_AXI_ERROR_ID_MASK)
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
/*! LUT_DMA_LOAD_DONE_IRQ
* 0b0..LUT DMA LOAD transfer is active
* 0b1..LUT DMA LOAD transfer is complete
*/
#define PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_CLR_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define PXP_STAT_CLR_BLOCKY_MASK (0xFF0000U)
#define PXP_STAT_CLR_BLOCKY_SHIFT (16U)
#define PXP_STAT_CLR_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKY_SHIFT)) & PXP_STAT_CLR_BLOCKY_MASK)
#define PXP_STAT_CLR_BLOCKX_MASK (0xFF000000U)
#define PXP_STAT_CLR_BLOCKX_SHIFT (24U)
#define PXP_STAT_CLR_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_CLR_BLOCKX_SHIFT)) & PXP_STAT_CLR_BLOCKX_MASK)
/*! @} */
/*! @name STAT_TOG - Status Register */
/*! @{ */
#define PXP_STAT_TOG_IRQ_MASK (0x1U)
#define PXP_STAT_TOG_IRQ_SHIFT (0U)
/*! IRQ
* 0b0..No interrupt
* 0b1..Interrupt generated
*/
#define PXP_STAT_TOG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_IRQ_SHIFT)) & PXP_STAT_TOG_IRQ_MASK)
#define PXP_STAT_TOG_AXI_WRITE_ERROR_MASK (0x2U)
#define PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT (1U)
/*! AXI_WRITE_ERROR
* 0b0..AXI write is normal
* 0b1..AXI write error has occurred
*/
#define PXP_STAT_TOG_AXI_WRITE_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_WRITE_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_WRITE_ERROR_MASK)
#define PXP_STAT_TOG_AXI_READ_ERROR_MASK (0x4U)
#define PXP_STAT_TOG_AXI_READ_ERROR_SHIFT (2U)
/*! AXI_READ_ERROR
* 0b0..AXI read is normal
* 0b1..AXI read error has occurred
*/
#define PXP_STAT_TOG_AXI_READ_ERROR(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_READ_ERROR_SHIFT)) & PXP_STAT_TOG_AXI_READ_ERROR_MASK)
#define PXP_STAT_TOG_NEXT_IRQ_MASK (0x8U)
#define PXP_STAT_TOG_NEXT_IRQ_SHIFT (3U)
#define PXP_STAT_TOG_NEXT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_NEXT_IRQ_SHIFT)) & PXP_STAT_TOG_NEXT_IRQ_MASK)
#define PXP_STAT_TOG_AXI_ERROR_ID_MASK (0xF0U)
#define PXP_STAT_TOG_AXI_ERROR_ID_SHIFT (4U)
#define PXP_STAT_TOG_AXI_ERROR_ID(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_AXI_ERROR_ID_SHIFT)) & PXP_STAT_TOG_AXI_ERROR_ID_MASK)
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK (0x100U)
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT (8U)
/*! LUT_DMA_LOAD_DONE_IRQ
* 0b0..LUT DMA LOAD transfer is active
* 0b1..LUT DMA LOAD transfer is complete
*/
#define PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_SHIFT)) & PXP_STAT_TOG_LUT_DMA_LOAD_DONE_IRQ_MASK)
#define PXP_STAT_TOG_BLOCKY_MASK (0xFF0000U)
#define PXP_STAT_TOG_BLOCKY_SHIFT (16U)
#define PXP_STAT_TOG_BLOCKY(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKY_SHIFT)) & PXP_STAT_TOG_BLOCKY_MASK)
#define PXP_STAT_TOG_BLOCKX_MASK (0xFF000000U)
#define PXP_STAT_TOG_BLOCKX_SHIFT (24U)
#define PXP_STAT_TOG_BLOCKX(x) (((uint32_t)(((uint32_t)(x)) << PXP_STAT_TOG_BLOCKX_SHIFT)) & PXP_STAT_TOG_BLOCKX_MASK)
/*! @} */
/*! @name OUT_CTRL - Output Buffer Control Register */
/*! @{ */
#define PXP_OUT_CTRL_FORMAT_MASK (0x1FU)
#define PXP_OUT_CTRL_FORMAT_SHIFT (0U)
/*! FORMAT
* 0b00000..32-bit pixels
* 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
* 0b00101..24-bit pixels (packed 24-bit format)
* 0b01000..16-bit pixels
* 0b01001..16-bit pixels
* 0b01100..16-bit pixels
* 0b01101..16-bit pixels
* 0b01110..16-bit pixels
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
* 0b11001..16-bit pixels (2-plane UV)
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
* 0b11011..16-bit pixels (2-plane VU)
*/
#define PXP_OUT_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_FORMAT_SHIFT)) & PXP_OUT_CTRL_FORMAT_MASK)
#define PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK (0x300U)
#define PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT (8U)
/*! INTERLACED_OUTPUT
* 0b00..All data written in progressive format to the OUTBUF Pointer.
* 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
* 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
* 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
*/
#define PXP_OUT_CTRL_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_INTERLACED_OUTPUT_MASK)
#define PXP_OUT_CTRL_ALPHA_OUTPUT_MASK (0x800000U)
#define PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT (23U)
/*! ALPHA_OUTPUT
* 0b0..Retain
* 0b1..Overwritten
*/
#define PXP_OUT_CTRL_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_ALPHA_OUTPUT_MASK)
#define PXP_OUT_CTRL_ALPHA_MASK (0xFF000000U)
#define PXP_OUT_CTRL_ALPHA_SHIFT (24U)
#define PXP_OUT_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_ALPHA_SHIFT)) & PXP_OUT_CTRL_ALPHA_MASK)
/*! @} */
/*! @name OUT_CTRL_SET - Output Buffer Control Register */
/*! @{ */
#define PXP_OUT_CTRL_SET_FORMAT_MASK (0x1FU)
#define PXP_OUT_CTRL_SET_FORMAT_SHIFT (0U)
/*! FORMAT
* 0b00000..32-bit pixels
* 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
* 0b00101..24-bit pixels (packed 24-bit format)
* 0b01000..16-bit pixels
* 0b01001..16-bit pixels
* 0b01100..16-bit pixels
* 0b01101..16-bit pixels
* 0b01110..16-bit pixels
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
* 0b11001..16-bit pixels (2-plane UV)
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
* 0b11011..16-bit pixels (2-plane VU)
*/
#define PXP_OUT_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_FORMAT_SHIFT)) & PXP_OUT_CTRL_SET_FORMAT_MASK)
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK (0x300U)
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT (8U)
/*! INTERLACED_OUTPUT
* 0b00..All data written in progressive format to the OUTBUF Pointer.
* 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
* 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
* 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
*/
#define PXP_OUT_CTRL_SET_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_INTERLACED_OUTPUT_MASK)
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK (0x800000U)
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT (23U)
/*! ALPHA_OUTPUT
* 0b0..Retain
* 0b1..Overwritten
*/
#define PXP_OUT_CTRL_SET_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_OUTPUT_MASK)
#define PXP_OUT_CTRL_SET_ALPHA_MASK (0xFF000000U)
#define PXP_OUT_CTRL_SET_ALPHA_SHIFT (24U)
#define PXP_OUT_CTRL_SET_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_SET_ALPHA_SHIFT)) & PXP_OUT_CTRL_SET_ALPHA_MASK)
/*! @} */
/*! @name OUT_CTRL_CLR - Output Buffer Control Register */
/*! @{ */
#define PXP_OUT_CTRL_CLR_FORMAT_MASK (0x1FU)
#define PXP_OUT_CTRL_CLR_FORMAT_SHIFT (0U)
/*! FORMAT
* 0b00000..32-bit pixels
* 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
* 0b00101..24-bit pixels (packed 24-bit format)
* 0b01000..16-bit pixels
* 0b01001..16-bit pixels
* 0b01100..16-bit pixels
* 0b01101..16-bit pixels
* 0b01110..16-bit pixels
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
* 0b11001..16-bit pixels (2-plane UV)
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
* 0b11011..16-bit pixels (2-plane VU)
*/
#define PXP_OUT_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_FORMAT_SHIFT)) & PXP_OUT_CTRL_CLR_FORMAT_MASK)
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK (0x300U)
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT (8U)
/*! INTERLACED_OUTPUT
* 0b00..All data written in progressive format to the OUTBUF Pointer.
* 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
* 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
* 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
*/
#define PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_INTERLACED_OUTPUT_MASK)
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK (0x800000U)
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT (23U)
/*! ALPHA_OUTPUT
* 0b0..Retain
* 0b1..Overwritten
*/
#define PXP_OUT_CTRL_CLR_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_OUTPUT_MASK)
#define PXP_OUT_CTRL_CLR_ALPHA_MASK (0xFF000000U)
#define PXP_OUT_CTRL_CLR_ALPHA_SHIFT (24U)
#define PXP_OUT_CTRL_CLR_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_CLR_ALPHA_SHIFT)) & PXP_OUT_CTRL_CLR_ALPHA_MASK)
/*! @} */
/*! @name OUT_CTRL_TOG - Output Buffer Control Register */
/*! @{ */
#define PXP_OUT_CTRL_TOG_FORMAT_MASK (0x1FU)
#define PXP_OUT_CTRL_TOG_FORMAT_SHIFT (0U)
/*! FORMAT
* 0b00000..32-bit pixels
* 0b00100..32-bit pixels (unpacked 24-bit pixel in 32 bit DWORD.)
* 0b00101..24-bit pixels (packed 24-bit format)
* 0b01000..16-bit pixels
* 0b01001..16-bit pixels
* 0b01100..16-bit pixels
* 0b01101..16-bit pixels
* 0b01110..16-bit pixels
* 0b10000..32-bit pixels (1-plane XYUV unpacked)
* 0b10010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
* 0b10011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
* 0b10100..8-bit monochrome pixels (1-plane Y luma output)
* 0b10101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
* 0b11000..16-bit pixels (2-plane UV interleaved bytes)
* 0b11001..16-bit pixels (2-plane UV)
* 0b11010..16-bit pixels (2-plane VU interleaved bytes)
* 0b11011..16-bit pixels (2-plane VU)
*/
#define PXP_OUT_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_FORMAT_SHIFT)) & PXP_OUT_CTRL_TOG_FORMAT_MASK)
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK (0x300U)
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT (8U)
/*! INTERLACED_OUTPUT
* 0b00..All data written in progressive format to the OUTBUF Pointer.
* 0b01..Interlaced output: only data for field 0 is written to the OUTBUF Pointer.
* 0b10..Interlaced output: only data for field 1 is written to the OUTBUF2 Pointer.
* 0b11..Interlaced output: data for field 0 is written to OUTBUF and data for field 1 is written to OUTBUF2.
*/
#define PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_INTERLACED_OUTPUT_MASK)
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK (0x800000U)
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT (23U)
/*! ALPHA_OUTPUT
* 0b0..Retain
* 0b1..Overwritten
*/
#define PXP_OUT_CTRL_TOG_ALPHA_OUTPUT(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_OUTPUT_MASK)
#define PXP_OUT_CTRL_TOG_ALPHA_MASK (0xFF000000U)
#define PXP_OUT_CTRL_TOG_ALPHA_SHIFT (24U)
#define PXP_OUT_CTRL_TOG_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_CTRL_TOG_ALPHA_SHIFT)) & PXP_OUT_CTRL_TOG_ALPHA_MASK)
/*! @} */
/*! @name OUT_BUF - Output Frame Buffer Pointer */
/*! @{ */
#define PXP_OUT_BUF_ADDR_MASK (0xFFFFFFFFU)
#define PXP_OUT_BUF_ADDR_SHIFT (0U)
#define PXP_OUT_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF_ADDR_SHIFT)) & PXP_OUT_BUF_ADDR_MASK)
/*! @} */
/*! @name OUT_BUF2 - Output Frame Buffer Pointer #2 */
/*! @{ */
#define PXP_OUT_BUF2_ADDR_MASK (0xFFFFFFFFU)
#define PXP_OUT_BUF2_ADDR_SHIFT (0U)
#define PXP_OUT_BUF2_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_BUF2_ADDR_SHIFT)) & PXP_OUT_BUF2_ADDR_MASK)
/*! @} */
/*! @name OUT_PITCH - Output Buffer Pitch */
/*! @{ */
#define PXP_OUT_PITCH_PITCH_MASK (0xFFFFU)
#define PXP_OUT_PITCH_PITCH_SHIFT (0U)
#define PXP_OUT_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PITCH_PITCH_SHIFT)) & PXP_OUT_PITCH_PITCH_MASK)
/*! @} */
/*! @name OUT_LRC - Output Surface Lower Right Coordinate */
/*! @{ */
#define PXP_OUT_LRC_Y_MASK (0x3FFFU)
#define PXP_OUT_LRC_Y_SHIFT (0U)
#define PXP_OUT_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_Y_SHIFT)) & PXP_OUT_LRC_Y_MASK)
#define PXP_OUT_LRC_X_MASK (0x3FFF0000U)
#define PXP_OUT_LRC_X_SHIFT (16U)
#define PXP_OUT_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_LRC_X_SHIFT)) & PXP_OUT_LRC_X_MASK)
/*! @} */
/*! @name OUT_PS_ULC - Processed Surface Upper Left Coordinate */
/*! @{ */
#define PXP_OUT_PS_ULC_Y_MASK (0x3FFFU)
#define PXP_OUT_PS_ULC_Y_SHIFT (0U)
#define PXP_OUT_PS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_Y_SHIFT)) & PXP_OUT_PS_ULC_Y_MASK)
#define PXP_OUT_PS_ULC_X_MASK (0x3FFF0000U)
#define PXP_OUT_PS_ULC_X_SHIFT (16U)
#define PXP_OUT_PS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_ULC_X_SHIFT)) & PXP_OUT_PS_ULC_X_MASK)
/*! @} */
/*! @name OUT_PS_LRC - Processed Surface Lower Right Coordinate */
/*! @{ */
#define PXP_OUT_PS_LRC_Y_MASK (0x3FFFU)
#define PXP_OUT_PS_LRC_Y_SHIFT (0U)
#define PXP_OUT_PS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_Y_SHIFT)) & PXP_OUT_PS_LRC_Y_MASK)
#define PXP_OUT_PS_LRC_X_MASK (0x3FFF0000U)
#define PXP_OUT_PS_LRC_X_SHIFT (16U)
#define PXP_OUT_PS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_PS_LRC_X_SHIFT)) & PXP_OUT_PS_LRC_X_MASK)
/*! @} */
/*! @name OUT_AS_ULC - Alpha Surface Upper Left Coordinate */
/*! @{ */
#define PXP_OUT_AS_ULC_Y_MASK (0x3FFFU)
#define PXP_OUT_AS_ULC_Y_SHIFT (0U)
#define PXP_OUT_AS_ULC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_Y_SHIFT)) & PXP_OUT_AS_ULC_Y_MASK)
#define PXP_OUT_AS_ULC_X_MASK (0x3FFF0000U)
#define PXP_OUT_AS_ULC_X_SHIFT (16U)
#define PXP_OUT_AS_ULC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_ULC_X_SHIFT)) & PXP_OUT_AS_ULC_X_MASK)
/*! @} */
/*! @name OUT_AS_LRC - Alpha Surface Lower Right Coordinate */
/*! @{ */
#define PXP_OUT_AS_LRC_Y_MASK (0x3FFFU)
#define PXP_OUT_AS_LRC_Y_SHIFT (0U)
#define PXP_OUT_AS_LRC_Y(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_Y_SHIFT)) & PXP_OUT_AS_LRC_Y_MASK)
#define PXP_OUT_AS_LRC_X_MASK (0x3FFF0000U)
#define PXP_OUT_AS_LRC_X_SHIFT (16U)
#define PXP_OUT_AS_LRC_X(x) (((uint32_t)(((uint32_t)(x)) << PXP_OUT_AS_LRC_X_SHIFT)) & PXP_OUT_AS_LRC_X_MASK)
/*! @} */
/*! @name PS_CTRL - Processed Surface (PS) Control Register */
/*! @{ */
#define PXP_PS_CTRL_FORMAT_MASK (0x3FU)
#define PXP_PS_CTRL_FORMAT_SHIFT (0U)
/*! FORMAT
* 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
* 0b001100..16-bit pixels with/without alpha at high 1bit
* 0b001101..16-bit pixels with/without alpha at high 4 bits
* 0b001110..16-bit pixels
* 0b010000..32-bit pixels (1-plane XYUV unpacked)
* 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
* 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
* 0b010100..8-bit monochrome pixels (1-plane Y luma output)
* 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
* 0b011000..16-bit pixels (2-plane UV interleaved bytes)
* 0b011001..16-bit pixels (2-plane UV)
* 0b011010..16-bit pixels (2-plane VU interleaved bytes)
* 0b011011..16-bit pixels (2-plane VU)
* 0b011110..16-bit pixels (3-plane format)
* 0b011111..16-bit pixels (3-plane format)
* 0b100100..2-bit pixels with alpha at the low 8 bits
* 0b101100..16-bit pixels with alpha at the low 1bits
* 0b101101..16-bit pixels with alpha at the low 4 bits
*/
#define PXP_PS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_FORMAT_SHIFT)) & PXP_PS_CTRL_FORMAT_MASK)
#define PXP_PS_CTRL_WB_SWAP_MASK (0x40U)
#define PXP_PS_CTRL_WB_SWAP_SHIFT (6U)
/*! WB_SWAP
* 0b0..Byte swap is disabled
* 0b1..Byte swap is enabled
*/
#define PXP_PS_CTRL_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_WB_SWAP_SHIFT)) & PXP_PS_CTRL_WB_SWAP_MASK)
#define PXP_PS_CTRL_DECY_MASK (0x300U)
#define PXP_PS_CTRL_DECY_SHIFT (8U)
/*! DECY
* 0b00..Disable pre-decimation filter.
* 0b01..Decimate PS by 2.
* 0b10..Decimate PS by 4.
* 0b11..Decimate PS by 8.
*/
#define PXP_PS_CTRL_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECY_SHIFT)) & PXP_PS_CTRL_DECY_MASK)
#define PXP_PS_CTRL_DECX_MASK (0xC00U)
#define PXP_PS_CTRL_DECX_SHIFT (10U)
/*! DECX
* 0b00..Disable pre-decimation filter.
* 0b01..Decimate PS by 2.
* 0b10..Decimate PS by 4.
* 0b11..Decimate PS by 8.
*/
#define PXP_PS_CTRL_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_DECX_SHIFT)) & PXP_PS_CTRL_DECX_MASK)
/*! @} */
/*! @name PS_CTRL_SET - Processed Surface (PS) Control Register */
/*! @{ */
#define PXP_PS_CTRL_SET_FORMAT_MASK (0x3FU)
#define PXP_PS_CTRL_SET_FORMAT_SHIFT (0U)
/*! FORMAT
* 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
* 0b001100..16-bit pixels with/without alpha at high 1bit
* 0b001101..16-bit pixels with/without alpha at high 4 bits
* 0b001110..16-bit pixels
* 0b010000..32-bit pixels (1-plane XYUV unpacked)
* 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
* 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
* 0b010100..8-bit monochrome pixels (1-plane Y luma output)
* 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
* 0b011000..16-bit pixels (2-plane UV interleaved bytes)
* 0b011001..16-bit pixels (2-plane UV)
* 0b011010..16-bit pixels (2-plane VU interleaved bytes)
* 0b011011..16-bit pixels (2-plane VU)
* 0b011110..16-bit pixels (3-plane format)
* 0b011111..16-bit pixels (3-plane format)
* 0b100100..2-bit pixels with alpha at the low 8 bits
* 0b101100..16-bit pixels with alpha at the low 1bits
* 0b101101..16-bit pixels with alpha at the low 4 bits
*/
#define PXP_PS_CTRL_SET_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_FORMAT_SHIFT)) & PXP_PS_CTRL_SET_FORMAT_MASK)
#define PXP_PS_CTRL_SET_WB_SWAP_MASK (0x40U)
#define PXP_PS_CTRL_SET_WB_SWAP_SHIFT (6U)
/*! WB_SWAP
* 0b0..Byte swap is disabled
* 0b1..Byte swap is enabled
*/
#define PXP_PS_CTRL_SET_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_WB_SWAP_SHIFT)) & PXP_PS_CTRL_SET_WB_SWAP_MASK)
#define PXP_PS_CTRL_SET_DECY_MASK (0x300U)
#define PXP_PS_CTRL_SET_DECY_SHIFT (8U)
/*! DECY
* 0b00..Disable pre-decimation filter.
* 0b01..Decimate PS by 2.
* 0b10..Decimate PS by 4.
* 0b11..Decimate PS by 8.
*/
#define PXP_PS_CTRL_SET_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECY_SHIFT)) & PXP_PS_CTRL_SET_DECY_MASK)
#define PXP_PS_CTRL_SET_DECX_MASK (0xC00U)
#define PXP_PS_CTRL_SET_DECX_SHIFT (10U)
/*! DECX
* 0b00..Disable pre-decimation filter.
* 0b01..Decimate PS by 2.
* 0b10..Decimate PS by 4.
* 0b11..Decimate PS by 8.
*/
#define PXP_PS_CTRL_SET_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_SET_DECX_SHIFT)) & PXP_PS_CTRL_SET_DECX_MASK)
/*! @} */
/*! @name PS_CTRL_CLR - Processed Surface (PS) Control Register */
/*! @{ */
#define PXP_PS_CTRL_CLR_FORMAT_MASK (0x3FU)
#define PXP_PS_CTRL_CLR_FORMAT_SHIFT (0U)
/*! FORMAT
* 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
* 0b001100..16-bit pixels with/without alpha at high 1bit
* 0b001101..16-bit pixels with/without alpha at high 4 bits
* 0b001110..16-bit pixels
* 0b010000..32-bit pixels (1-plane XYUV unpacked)
* 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
* 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
* 0b010100..8-bit monochrome pixels (1-plane Y luma output)
* 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
* 0b011000..16-bit pixels (2-plane UV interleaved bytes)
* 0b011001..16-bit pixels (2-plane UV)
* 0b011010..16-bit pixels (2-plane VU interleaved bytes)
* 0b011011..16-bit pixels (2-plane VU)
* 0b011110..16-bit pixels (3-plane format)
* 0b011111..16-bit pixels (3-plane format)
* 0b100100..2-bit pixels with alpha at the low 8 bits
* 0b101100..16-bit pixels with alpha at the low 1bits
* 0b101101..16-bit pixels with alpha at the low 4 bits
*/
#define PXP_PS_CTRL_CLR_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_FORMAT_SHIFT)) & PXP_PS_CTRL_CLR_FORMAT_MASK)
#define PXP_PS_CTRL_CLR_WB_SWAP_MASK (0x40U)
#define PXP_PS_CTRL_CLR_WB_SWAP_SHIFT (6U)
/*! WB_SWAP
* 0b0..Byte swap is disabled
* 0b1..Byte swap is enabled
*/
#define PXP_PS_CTRL_CLR_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_WB_SWAP_SHIFT)) & PXP_PS_CTRL_CLR_WB_SWAP_MASK)
#define PXP_PS_CTRL_CLR_DECY_MASK (0x300U)
#define PXP_PS_CTRL_CLR_DECY_SHIFT (8U)
/*! DECY
* 0b00..Disable pre-decimation filter.
* 0b01..Decimate PS by 2.
* 0b10..Decimate PS by 4.
* 0b11..Decimate PS by 8.
*/
#define PXP_PS_CTRL_CLR_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECY_SHIFT)) & PXP_PS_CTRL_CLR_DECY_MASK)
#define PXP_PS_CTRL_CLR_DECX_MASK (0xC00U)
#define PXP_PS_CTRL_CLR_DECX_SHIFT (10U)
/*! DECX
* 0b00..Disable pre-decimation filter.
* 0b01..Decimate PS by 2.
* 0b10..Decimate PS by 4.
* 0b11..Decimate PS by 8.
*/
#define PXP_PS_CTRL_CLR_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_CLR_DECX_SHIFT)) & PXP_PS_CTRL_CLR_DECX_MASK)
/*! @} */
/*! @name PS_CTRL_TOG - Processed Surface (PS) Control Register */
/*! @{ */
#define PXP_PS_CTRL_TOG_FORMAT_MASK (0x3FU)
#define PXP_PS_CTRL_TOG_FORMAT_SHIFT (0U)
/*! FORMAT
* 0b000100..32-bit pixels (unpacked 24-bit format with/without alpha at high 8bits)
* 0b001100..16-bit pixels with/without alpha at high 1bit
* 0b001101..16-bit pixels with/without alpha at high 4 bits
* 0b001110..16-bit pixels
* 0b010000..32-bit pixels (1-plane XYUV unpacked)
* 0b010010..16-bit pixels (1-plane U0,Y0,V0,Y1 interleaved bytes)
* 0b010011..16-bit pixels (1-plane V0,Y0,U0,Y1 interleaved bytes)
* 0b010100..8-bit monochrome pixels (1-plane Y luma output)
* 0b010101..4-bit monochrome pixels (1-plane Y luma, 4 bit truncation)
* 0b011000..16-bit pixels (2-plane UV interleaved bytes)
* 0b011001..16-bit pixels (2-plane UV)
* 0b011010..16-bit pixels (2-plane VU interleaved bytes)
* 0b011011..16-bit pixels (2-plane VU)
* 0b011110..16-bit pixels (3-plane format)
* 0b011111..16-bit pixels (3-plane format)
* 0b100100..2-bit pixels with alpha at the low 8 bits
* 0b101100..16-bit pixels with alpha at the low 1bits
* 0b101101..16-bit pixels with alpha at the low 4 bits
*/
#define PXP_PS_CTRL_TOG_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_FORMAT_SHIFT)) & PXP_PS_CTRL_TOG_FORMAT_MASK)
#define PXP_PS_CTRL_TOG_WB_SWAP_MASK (0x40U)
#define PXP_PS_CTRL_TOG_WB_SWAP_SHIFT (6U)
/*! WB_SWAP
* 0b0..Byte swap is disabled
* 0b1..Byte swap is enabled
*/
#define PXP_PS_CTRL_TOG_WB_SWAP(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_WB_SWAP_SHIFT)) & PXP_PS_CTRL_TOG_WB_SWAP_MASK)
#define PXP_PS_CTRL_TOG_DECY_MASK (0x300U)
#define PXP_PS_CTRL_TOG_DECY_SHIFT (8U)
/*! DECY
* 0b00..Disable pre-decimation filter.
* 0b01..Decimate PS by 2.
* 0b10..Decimate PS by 4.
* 0b11..Decimate PS by 8.
*/
#define PXP_PS_CTRL_TOG_DECY(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECY_SHIFT)) & PXP_PS_CTRL_TOG_DECY_MASK)
#define PXP_PS_CTRL_TOG_DECX_MASK (0xC00U)
#define PXP_PS_CTRL_TOG_DECX_SHIFT (10U)
/*! DECX
* 0b00..Disable pre-decimation filter.
* 0b01..Decimate PS by 2.
* 0b10..Decimate PS by 4.
* 0b11..Decimate PS by 8.
*/
#define PXP_PS_CTRL_TOG_DECX(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CTRL_TOG_DECX_SHIFT)) & PXP_PS_CTRL_TOG_DECX_MASK)
/*! @} */
/*! @name PS_BUF - PS Input Buffer Address */
/*! @{ */
#define PXP_PS_BUF_ADDR_MASK (0xFFFFFFFFU)
#define PXP_PS_BUF_ADDR_SHIFT (0U)
#define PXP_PS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BUF_ADDR_SHIFT)) & PXP_PS_BUF_ADDR_MASK)
/*! @} */
/*! @name PS_UBUF - PS U/Cb or 2 Plane UV Input Buffer Address */
/*! @{ */
#define PXP_PS_UBUF_ADDR_MASK (0xFFFFFFFFU)
#define PXP_PS_UBUF_ADDR_SHIFT (0U)
#define PXP_PS_UBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_UBUF_ADDR_SHIFT)) & PXP_PS_UBUF_ADDR_MASK)
/*! @} */
/*! @name PS_VBUF - PS V/Cr Input Buffer Address */
/*! @{ */
#define PXP_PS_VBUF_ADDR_MASK (0xFFFFFFFFU)
#define PXP_PS_VBUF_ADDR_SHIFT (0U)
#define PXP_PS_VBUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_VBUF_ADDR_SHIFT)) & PXP_PS_VBUF_ADDR_MASK)
/*! @} */
/*! @name PS_PITCH - Processed Surface Pitch */
/*! @{ */
#define PXP_PS_PITCH_PITCH_MASK (0xFFFFU)
#define PXP_PS_PITCH_PITCH_SHIFT (0U)
#define PXP_PS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_PITCH_PITCH_SHIFT)) & PXP_PS_PITCH_PITCH_MASK)
/*! @} */
/*! @name PS_BACKGROUND - PS Background Color */
/*! @{ */
#define PXP_PS_BACKGROUND_COLOR_MASK (0xFFFFFFU)
#define PXP_PS_BACKGROUND_COLOR_SHIFT (0U)
#define PXP_PS_BACKGROUND_COLOR(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_BACKGROUND_COLOR_SHIFT)) & PXP_PS_BACKGROUND_COLOR_MASK)
/*! @} */
/*! @name PS_SCALE - PS Scale Factor Register */
/*! @{ */
#define PXP_PS_SCALE_XSCALE_MASK (0x7FFFU)
#define PXP_PS_SCALE_XSCALE_SHIFT (0U)
#define PXP_PS_SCALE_XSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_XSCALE_SHIFT)) & PXP_PS_SCALE_XSCALE_MASK)
#define PXP_PS_SCALE_YSCALE_MASK (0x7FFF0000U)
#define PXP_PS_SCALE_YSCALE_SHIFT (16U)
#define PXP_PS_SCALE_YSCALE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_SCALE_YSCALE_SHIFT)) & PXP_PS_SCALE_YSCALE_MASK)
/*! @} */
/*! @name PS_OFFSET - PS Scale Offset Register */
/*! @{ */
#define PXP_PS_OFFSET_XOFFSET_MASK (0xFFFU)
#define PXP_PS_OFFSET_XOFFSET_SHIFT (0U)
#define PXP_PS_OFFSET_XOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_XOFFSET_SHIFT)) & PXP_PS_OFFSET_XOFFSET_MASK)
#define PXP_PS_OFFSET_YOFFSET_MASK (0xFFF0000U)
#define PXP_PS_OFFSET_YOFFSET_SHIFT (16U)
#define PXP_PS_OFFSET_YOFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_OFFSET_YOFFSET_SHIFT)) & PXP_PS_OFFSET_YOFFSET_MASK)
/*! @} */
/*! @name PS_CLRKEYLOW - PS Color Key Low */
/*! @{ */
#define PXP_PS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
#define PXP_PS_CLRKEYLOW_PIXEL_SHIFT (0U)
#define PXP_PS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_PS_CLRKEYLOW_PIXEL_MASK)
/*! @} */
/*! @name PS_CLRKEYHIGH - PS Color Key High */
/*! @{ */
#define PXP_PS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
#define PXP_PS_CLRKEYHIGH_PIXEL_SHIFT (0U)
#define PXP_PS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_PS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_PS_CLRKEYHIGH_PIXEL_MASK)
/*! @} */
/*! @name AS_CTRL - Alpha Surface Control */
/*! @{ */
#define PXP_AS_CTRL_ALPHA_CTRL_MASK (0x6U)
#define PXP_AS_CTRL_ALPHA_CTRL_SHIFT (1U)
/*! ALPHA_CTRL
* 0b00..Indicates that the AS pixel alpha value will be used to blend the AS with PS. The ALPHA field is ignored.
* 0b01..Indicates that the value in the ALPHA field should be used instead of the alpha values present in the input pixels.
* 0b10..Indicates that the value in the ALPHA field should be used to scale all pixel alpha values. Each pixel
* alpha is multiplied by the value in the ALPHA field.
* 0b11..Enable ROPs. The ROP field indicates an operation to be performed on the alpha surface and PS pixels.
*/
#define PXP_AS_CTRL_ALPHA_CTRL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_CTRL_SHIFT)) & PXP_AS_CTRL_ALPHA_CTRL_MASK)
#define PXP_AS_CTRL_ENABLE_COLORKEY_MASK (0x8U)
#define PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT (3U)
/*! ENABLE_COLORKEY
* 0b0..Disabled
* 0b1..Enabled
*/
#define PXP_AS_CTRL_ENABLE_COLORKEY(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ENABLE_COLORKEY_SHIFT)) & PXP_AS_CTRL_ENABLE_COLORKEY_MASK)
#define PXP_AS_CTRL_FORMAT_MASK (0xF0U)
#define PXP_AS_CTRL_FORMAT_SHIFT (4U)
/*! FORMAT
* 0b0000..32-bit pixels with alpha
* 0b0001..2-bit pixel with alpha at low 8 bits
* 0b0100..32-bit pixels without alpha (unpacked 24-bit format)
* 0b1000..16-bit pixels with alpha
* 0b1001..16-bit pixels with alpha
* 0b1010..16-bit pixel with alpha at low 1 bit
* 0b1011..16-bit pixel with alpha at low 4 bits
* 0b1100..16-bit pixels without alpha
* 0b1101..16-bit pixels without alpha
* 0b1110..16-bit pixels without alpha
*/
#define PXP_AS_CTRL_FORMAT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_FORMAT_SHIFT)) & PXP_AS_CTRL_FORMAT_MASK)
#define PXP_AS_CTRL_ALPHA_MASK (0xFF00U)
#define PXP_AS_CTRL_ALPHA_SHIFT (8U)
#define PXP_AS_CTRL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_SHIFT)) & PXP_AS_CTRL_ALPHA_MASK)
#define PXP_AS_CTRL_ROP_MASK (0xF0000U)
#define PXP_AS_CTRL_ROP_SHIFT (16U)
/*! ROP
* 0b0000..AS AND PS
* 0b0001..nAS AND PS
* 0b0010..AS AND nPS
* 0b0011..AS OR PS
* 0b0100..nAS OR PS
* 0b0101..AS OR nPS
* 0b0110..nAS
* 0b0111..nPS
* 0b1000..AS NAND PS
* 0b1001..AS NOR PS
* 0b1010..AS XOR PS
* 0b1011..AS XNOR PS
*/
#define PXP_AS_CTRL_ROP(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ROP_SHIFT)) & PXP_AS_CTRL_ROP_MASK)
#define PXP_AS_CTRL_ALPHA_INVERT_MASK (0x100000U)
#define PXP_AS_CTRL_ALPHA_INVERT_SHIFT (20U)
/*! ALPHA_INVERT
* 0b0..Not inverted
* 0b1..Inverted
*/
#define PXP_AS_CTRL_ALPHA_INVERT(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CTRL_ALPHA_INVERT_SHIFT)) & PXP_AS_CTRL_ALPHA_INVERT_MASK)
/*! @} */
/*! @name AS_BUF - Alpha Surface Buffer Pointer */
/*! @{ */
#define PXP_AS_BUF_ADDR_MASK (0xFFFFFFFFU)
#define PXP_AS_BUF_ADDR_SHIFT (0U)
#define PXP_AS_BUF_ADDR(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_BUF_ADDR_SHIFT)) & PXP_AS_BUF_ADDR_MASK)
/*! @} */
/*! @name AS_PITCH - Alpha Surface Pitch */
/*! @{ */
#define PXP_AS_PITCH_PITCH_MASK (0xFFFFU)
#define PXP_AS_PITCH_PITCH_SHIFT (0U)
#define PXP_AS_PITCH_PITCH(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_PITCH_PITCH_SHIFT)) & PXP_AS_PITCH_PITCH_MASK)
/*! @} */
/*! @name AS_CLRKEYLOW - Overlay Color Key Low */
/*! @{ */
#define PXP_AS_CLRKEYLOW_PIXEL_MASK (0xFFFFFFU)
#define PXP_AS_CLRKEYLOW_PIXEL_SHIFT (0U)
#define PXP_AS_CLRKEYLOW_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYLOW_PIXEL_SHIFT)) & PXP_AS_CLRKEYLOW_PIXEL_MASK)
/*! @} */
/*! @name AS_CLRKEYHIGH - Overlay Color Key High */
/*! @{ */
#define PXP_AS_CLRKEYHIGH_PIXEL_MASK (0xFFFFFFU)
#define PXP_AS_CLRKEYHIGH_PIXEL_SHIFT (0U)
#define PXP_AS_CLRKEYHIGH_PIXEL(x) (((uint32_t)(((uint32_t)(x)) << PXP_AS_CLRKEYHIGH_PIXEL_SHIFT)) & PXP_AS_CLRKEYHIGH_PIXEL_MASK)
/*! @} */
/*! @name CSC1_COEF0 - Color Space Conversion Coefficient Register 0 */
/*! @{ */
#define PXP_CSC1_COEF0_Y_OFFSET_MASK (0x1FFU)
#define PXP_CSC1_COEF0_Y_OFFSET_SHIFT (0U)
#define PXP_CSC1_COEF0_Y_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_Y_OFFSET_SHIFT)) & PXP_CSC1_COEF0_Y_OFFSET_MASK)
#define PXP_CSC1_COEF0_UV_OFFSET_MASK (0x3FE00U)
#define PXP_CSC1_COEF0_UV_OFFSET_SHIFT (9U)
#define PXP_CSC1_COEF0_UV_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_UV_OFFSET_SHIFT)) & PXP_CSC1_COEF0_UV_OFFSET_MASK)
#define PXP_CSC1_COEF0_C0_MASK (0x1FFC0000U)
#define PXP_CSC1_COEF0_C0_SHIFT (18U)
#define PXP_CSC1_COEF0_C0(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_C0_SHIFT)) & PXP_CSC1_COEF0_C0_MASK)
#define PXP_CSC1_COEF0_BYPASS_MASK (0x40000000U)
#define PXP_CSC1_COEF0_BYPASS_SHIFT (30U)
#define PXP_CSC1_COEF0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_BYPASS_SHIFT)) & PXP_CSC1_COEF0_BYPASS_MASK)
#define PXP_CSC1_COEF0_YCBCR_MODE_MASK (0x80000000U)
#define PXP_CSC1_COEF0_YCBCR_MODE_SHIFT (31U)
/*! YCBCR_MODE
* 0b0..YUV to RGB
* 0b1..YCbCr to RGB
*/
#define PXP_CSC1_COEF0_YCBCR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF0_YCBCR_MODE_SHIFT)) & PXP_CSC1_COEF0_YCBCR_MODE_MASK)
/*! @} */
/*! @name CSC1_COEF1 - Color Space Conversion Coefficient Register 1 */
/*! @{ */
#define PXP_CSC1_COEF1_C4_MASK (0x7FFU)
#define PXP_CSC1_COEF1_C4_SHIFT (0U)
#define PXP_CSC1_COEF1_C4(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C4_SHIFT)) & PXP_CSC1_COEF1_C4_MASK)
#define PXP_CSC1_COEF1_C1_MASK (0x7FF0000U)
#define PXP_CSC1_COEF1_C1_SHIFT (16U)
#define PXP_CSC1_COEF1_C1(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF1_C1_SHIFT)) & PXP_CSC1_COEF1_C1_MASK)
/*! @} */
/*! @name CSC1_COEF2 - Color Space Conversion Coefficient Register 2 */
/*! @{ */
#define PXP_CSC1_COEF2_C3_MASK (0x7FFU)
#define PXP_CSC1_COEF2_C3_SHIFT (0U)
#define PXP_CSC1_COEF2_C3(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C3_SHIFT)) & PXP_CSC1_COEF2_C3_MASK)
#define PXP_CSC1_COEF2_C2_MASK (0x7FF0000U)
#define PXP_CSC1_COEF2_C2_SHIFT (16U)
#define PXP_CSC1_COEF2_C2(x) (((uint32_t)(((uint32_t)(x)) << PXP_CSC1_COEF2_C2_SHIFT)) & PXP_CSC1_COEF2_C2_MASK)
/*! @} */
/*! @name POWER - PXP Power Control Register */
/*! @{ */
#define PXP_POWER_ROT_MEM_LP_STATE_MASK (0xE00U)
#define PXP_POWER_ROT_MEM_LP_STATE_SHIFT (9U)
/*! ROT_MEM_LP_STATE
* 0b000..Memory is not in low power state.
* 0b001..Light Sleep Mode. Low leakage mode, maintain memory contents.
* 0b010..Deep Sleep Mode. Low leakage mode, maintain memory contents.
* 0b100..Shut Down Mode. Shut Down periphery and core, no memory retention.
*/
#define PXP_POWER_ROT_MEM_LP_STATE(x) (((uint32_t)(((uint32_t)(x)) << PXP_POWER_ROT_MEM_LP_STATE_SHIFT)) & PXP_POWER_ROT_MEM_LP_STATE_MASK)
/*! @} */
/*! @name NEXT - Next Frame Pointer */
/*! @{ */
#define PXP_NEXT_ENABLED_MASK (0x1U)
#define PXP_NEXT_ENABLED_SHIFT (0U)
#define PXP_NEXT_ENABLED(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_ENABLED_SHIFT)) & PXP_NEXT_ENABLED_MASK)
#define PXP_NEXT_POINTER_MASK (0xFFFFFFFCU)
#define PXP_NEXT_POINTER_SHIFT (2U)
#define PXP_NEXT_POINTER(x) (((uint32_t)(((uint32_t)(x)) << PXP_NEXT_POINTER_SHIFT)) & PXP_NEXT_POINTER_MASK)
/*! @} */
/*! @name PORTER_DUFF_CTRL - PXP Alpha Engine A Control Register. */
/*! @{ */
#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK (0x1U)
#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT (0U)
/*! PORTER_DUFF_ENABLE
* 0b0..Disabled
* 0b1..Enabled
*/
#define PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_SHIFT)) & PXP_PORTER_DUFF_CTRL_PORTER_DUFF_ENABLE_MASK)
#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK (0x6U)
#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT (1U)
/*! S0_S1_FACTOR_MODE
* 0b00..1
* 0b01..0
* 0b10..Straight alpha
* 0b11..Inverse alpha
*/
#define PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_S1_FACTOR_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK (0x18U)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT (3U)
/*! S0_GLOBAL_ALPHA_MODE
* 0b00..Global alpha
* 0b01..Local alpha
* 0b10..Scaled alpha
* 0b11..Scaled alpha
*/
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK (0x20U)
#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT (5U)
/*! S0_ALPHA_MODE
* 0b0..Straight mode
* 0b1..Inverted mode
*/
#define PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_ALPHA_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK (0x40U)
#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT (6U)
/*! S0_COLOR_MODE
* 0b0..Original pixel
* 0b1..Scaled pixel
*/
#define PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_COLOR_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK (0x300U)
#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT (8U)
/*! S1_S0_FACTOR_MODE
* 0b00..1
* 0b01..0
* 0b10..Straight alpha
* 0b11..Inverse alpha
*/
#define PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_S0_FACTOR_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK (0xC00U)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT (10U)
/*! S1_GLOBAL_ALPHA_MODE
* 0b00..Global alpha
* 0b01..Local alpha
* 0b10..Scaled alpha
* 0b11..Scaled alpha
*/
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK (0x1000U)
#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT (12U)
/*! S1_ALPHA_MODE
* 0b0..Straight mode
* 0b1..Inverted mode
*/
#define PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_ALPHA_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK (0x2000U)
#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT (13U)
/*! S1_COLOR_MODE
* 0b0..Original pixel
* 0b1..Scaled pixel
*/
#define PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_COLOR_MODE_MASK)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK (0xFF0000U)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT (16U)
#define PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S0_GLOBAL_ALPHA_MASK)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK (0xFF000000U)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT (24U)
#define PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA(x) (((uint32_t)(((uint32_t)(x)) << PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_SHIFT)) & PXP_PORTER_DUFF_CTRL_S1_GLOBAL_ALPHA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group PXP_Register_Masks */
/* PXP - Peripheral instance base addresses */
/** Peripheral PXP base address */
#define PXP_BASE (0x40814000u)
/** Peripheral PXP base pointer */
#define PXP ((PXP_Type *)PXP_BASE)
/** Array initializer of PXP peripheral base addresses */
#define PXP_BASE_ADDRS { PXP_BASE }
/** Array initializer of PXP peripheral base pointers */
#define PXP_BASE_PTRS { PXP }
/** Interrupt vectors for the PXP peripheral type */
#define PXP_IRQ0_IRQS { PXP_IRQn }
/*!
* @}
*/ /* end of group PXP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RDC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RDC_Peripheral_Access_Layer RDC Peripheral Access Layer
* @{
*/
/** RDC - Register Layout Typedef */
typedef struct {
__I uint32_t VIR; /**< Version Information, offset: 0x0 */
uint8_t RESERVED_0[32];
__IO uint32_t STAT; /**< Status, offset: 0x24 */
__IO uint32_t INTCTRL; /**< Interrupt and Control, offset: 0x28 */
__IO uint32_t INTSTAT; /**< Interrupt Status, offset: 0x2C */
uint8_t RESERVED_1[464];
__IO uint32_t MDA[12]; /**< Master Domain Assignment, array offset: 0x200, array step: 0x4 */
uint8_t RESERVED_2[464];
__IO uint32_t PDAP[128]; /**< Peripheral Domain Access Permissions, array offset: 0x400, array step: 0x4 */
uint8_t RESERVED_3[512];
struct { /* offset: 0x800, array step: 0x10 */
__IO uint32_t MRSA; /**< Memory Region Start Address, array offset: 0x800, array step: 0x10 */
__IO uint32_t MREA; /**< Memory Region End Address, array offset: 0x804, array step: 0x10 */
__IO uint32_t MRC; /**< Memory Region Control, array offset: 0x808, array step: 0x10 */
__IO uint32_t MRVS; /**< Memory Region Violation Status, array offset: 0x80C, array step: 0x10 */
} MR[59];
} RDC_Type;
/* ----------------------------------------------------------------------------
-- RDC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RDC_Register_Masks RDC Register Masks
* @{
*/
/*! @name VIR - Version Information */
/*! @{ */
#define RDC_VIR_NDID_MASK (0xFU)
#define RDC_VIR_NDID_SHIFT (0U)
/*! NDID - Number of Domains
*/
#define RDC_VIR_NDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NDID_SHIFT)) & RDC_VIR_NDID_MASK)
#define RDC_VIR_NMSTR_MASK (0xFF0U)
#define RDC_VIR_NMSTR_SHIFT (4U)
/*! NMSTR - Number of Masters
*/
#define RDC_VIR_NMSTR(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NMSTR_SHIFT)) & RDC_VIR_NMSTR_MASK)
#define RDC_VIR_NPER_MASK (0xFF000U)
#define RDC_VIR_NPER_SHIFT (12U)
/*! NPER - Number of Peripherals
*/
#define RDC_VIR_NPER(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NPER_SHIFT)) & RDC_VIR_NPER_MASK)
#define RDC_VIR_NRGN_MASK (0xFF00000U)
#define RDC_VIR_NRGN_SHIFT (20U)
/*! NRGN - Number of Memory Regions
*/
#define RDC_VIR_NRGN(x) (((uint32_t)(((uint32_t)(x)) << RDC_VIR_NRGN_SHIFT)) & RDC_VIR_NRGN_MASK)
/*! @} */
/*! @name STAT - Status */
/*! @{ */
#define RDC_STAT_DID_MASK (0xFU)
#define RDC_STAT_DID_SHIFT (0U)
/*! DID - Domain ID
*/
#define RDC_STAT_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_DID_SHIFT)) & RDC_STAT_DID_MASK)
#define RDC_STAT_PDS_MASK (0x100U)
#define RDC_STAT_PDS_SHIFT (8U)
/*! PDS - Power Domain Status
* 0b0..Power Down Domain is OFF
* 0b1..Power Down Domain is ON
*/
#define RDC_STAT_PDS(x) (((uint32_t)(((uint32_t)(x)) << RDC_STAT_PDS_SHIFT)) & RDC_STAT_PDS_MASK)
/*! @} */
/*! @name INTCTRL - Interrupt and Control */
/*! @{ */
#define RDC_INTCTRL_RCI_EN_MASK (0x1U)
#define RDC_INTCTRL_RCI_EN_SHIFT (0U)
/*! RCI_EN - Restoration Complete Interrupt
* 0b0..Interrupt Disabled
* 0b1..Interrupt Enabled
*/
#define RDC_INTCTRL_RCI_EN(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTCTRL_RCI_EN_SHIFT)) & RDC_INTCTRL_RCI_EN_MASK)
/*! @} */
/*! @name INTSTAT - Interrupt Status */
/*! @{ */
#define RDC_INTSTAT_INT_MASK (0x1U)
#define RDC_INTSTAT_INT_SHIFT (0U)
/*! INT - Interrupt Status
* 0b0..No Interrupt Pending
* 0b1..Interrupt Pending
*/
#define RDC_INTSTAT_INT(x) (((uint32_t)(((uint32_t)(x)) << RDC_INTSTAT_INT_SHIFT)) & RDC_INTSTAT_INT_MASK)
/*! @} */
/*! @name MDA - Master Domain Assignment */
/*! @{ */
#define RDC_MDA_DID_MASK (0x3U)
#define RDC_MDA_DID_SHIFT (0U)
/*! DID - Domain ID
* 0b00..Master assigned to Processing Domain 0
* 0b01..Master assigned to Processing Domain 1
* 0b10..Reserved
* 0b11..Reserved
*/
#define RDC_MDA_DID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_DID_SHIFT)) & RDC_MDA_DID_MASK)
#define RDC_MDA_LCK_MASK (0x80000000U)
#define RDC_MDA_LCK_SHIFT (31U)
/*! LCK - Assignment Lock
* 0b0..Not Locked
* 0b1..Locked
*/
#define RDC_MDA_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MDA_LCK_SHIFT)) & RDC_MDA_LCK_MASK)
/*! @} */
/* The count of RDC_MDA */
#define RDC_MDA_COUNT (12U)
/*! @name PDAP - Peripheral Domain Access Permissions */
/*! @{ */
#define RDC_PDAP_D0W_MASK (0x1U)
#define RDC_PDAP_D0W_SHIFT (0U)
/*! D0W - Domain 0 Write Access
* 0b0..No Write Access
* 0b1..Write Access Allowed
*/
#define RDC_PDAP_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0W_SHIFT)) & RDC_PDAP_D0W_MASK)
#define RDC_PDAP_D0R_MASK (0x2U)
#define RDC_PDAP_D0R_SHIFT (1U)
/*! D0R - Domain 0 Read Access
* 0b0..No Read Access
* 0b1..Read Access Allowed
*/
#define RDC_PDAP_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D0R_SHIFT)) & RDC_PDAP_D0R_MASK)
#define RDC_PDAP_D1W_MASK (0x4U)
#define RDC_PDAP_D1W_SHIFT (2U)
/*! D1W - Domain 1 Write Access
* 0b0..No Write Access
* 0b1..Write Access Allowed
*/
#define RDC_PDAP_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1W_SHIFT)) & RDC_PDAP_D1W_MASK)
#define RDC_PDAP_D1R_MASK (0x8U)
#define RDC_PDAP_D1R_SHIFT (3U)
/*! D1R - Domain 1 Read Access
* 0b0..No Read Access
* 0b1..Read Access Allowed
*/
#define RDC_PDAP_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_D1R_SHIFT)) & RDC_PDAP_D1R_MASK)
#define RDC_PDAP_SREQ_MASK (0x40000000U)
#define RDC_PDAP_SREQ_SHIFT (30U)
/*! SREQ - Semaphore Required
* 0b0..Semaphores have no effect
* 0b1..Semaphores are enforced
*/
#define RDC_PDAP_SREQ(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_SREQ_SHIFT)) & RDC_PDAP_SREQ_MASK)
#define RDC_PDAP_LCK_MASK (0x80000000U)
#define RDC_PDAP_LCK_SHIFT (31U)
/*! LCK - Peripheral Permissions Lock
* 0b0..Not Locked
* 0b1..Locked
*/
#define RDC_PDAP_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_PDAP_LCK_SHIFT)) & RDC_PDAP_LCK_MASK)
/*! @} */
/* The count of RDC_PDAP */
#define RDC_PDAP_COUNT (128U)
/*! @name MRSA - Memory Region Start Address */
/*! @{ */
#define RDC_MRSA_SADR_MASK (0xFFFFFF80U)
#define RDC_MRSA_SADR_SHIFT (7U)
/*! SADR - Start address for memory region
*/
#define RDC_MRSA_SADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRSA_SADR_SHIFT)) & RDC_MRSA_SADR_MASK)
/*! @} */
/* The count of RDC_MRSA */
#define RDC_MRSA_COUNT (59U)
/*! @name MREA - Memory Region End Address */
/*! @{ */
#define RDC_MREA_EADR_MASK (0xFFFFFF80U)
#define RDC_MREA_EADR_SHIFT (7U)
/*! EADR - Upper bound for memory region
*/
#define RDC_MREA_EADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MREA_EADR_SHIFT)) & RDC_MREA_EADR_MASK)
/*! @} */
/* The count of RDC_MREA */
#define RDC_MREA_COUNT (59U)
/*! @name MRC - Memory Region Control */
/*! @{ */
#define RDC_MRC_D0W_MASK (0x1U)
#define RDC_MRC_D0W_SHIFT (0U)
/*! D0W - Domain 0 Write Access to Region
* 0b0..Processing Domain 0 does not have Write access to the memory region
* 0b1..Processing Domain 0 has Write access to the memory region
*/
#define RDC_MRC_D0W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0W_SHIFT)) & RDC_MRC_D0W_MASK)
#define RDC_MRC_D0R_MASK (0x2U)
#define RDC_MRC_D0R_SHIFT (1U)
/*! D0R - Domain 0 Read Access to Region
* 0b0..Processing Domain 0 does not have Read access to the memory region
* 0b1..Processing Domain 0 has Read access to the memory region
*/
#define RDC_MRC_D0R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D0R_SHIFT)) & RDC_MRC_D0R_MASK)
#define RDC_MRC_D1W_MASK (0x4U)
#define RDC_MRC_D1W_SHIFT (2U)
/*! D1W - Domain 1 Write Access to Region
* 0b0..Processing Domain 1 does not have Write access to the memory region
* 0b1..Processing Domain 1 has Write access to the memory region
*/
#define RDC_MRC_D1W(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1W_SHIFT)) & RDC_MRC_D1W_MASK)
#define RDC_MRC_D1R_MASK (0x8U)
#define RDC_MRC_D1R_SHIFT (3U)
/*! D1R - Domain 1 Read Access to Region
* 0b0..Processing Domain 1 does not have Read access to the memory region
* 0b1..Processing Domain 1 has Read access to the memory region
*/
#define RDC_MRC_D1R(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_D1R_SHIFT)) & RDC_MRC_D1R_MASK)
#define RDC_MRC_ENA_MASK (0x40000000U)
#define RDC_MRC_ENA_SHIFT (30U)
/*! ENA - Region Enable
* 0b0..Memory region is not defined or restricted.
* 0b1..Memory boundaries, domain permissions and controls are in effect.
*/
#define RDC_MRC_ENA(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_ENA_SHIFT)) & RDC_MRC_ENA_MASK)
#define RDC_MRC_LCK_MASK (0x80000000U)
#define RDC_MRC_LCK_SHIFT (31U)
/*! LCK - Region Lock
* 0b0..No Lock. All fields in this register may be modified.
* 0b1..Locked. No fields in this register may be modified except ENA, which may be set but not cleared.
*/
#define RDC_MRC_LCK(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRC_LCK_SHIFT)) & RDC_MRC_LCK_MASK)
/*! @} */
/* The count of RDC_MRC */
#define RDC_MRC_COUNT (59U)
/*! @name MRVS - Memory Region Violation Status */
/*! @{ */
#define RDC_MRVS_VDID_MASK (0x3U)
#define RDC_MRVS_VDID_SHIFT (0U)
/*! VDID - Violating Domain ID
* 0b00..Processing Domain 0
* 0b01..Processing Domain 1
* 0b10..Reserved
* 0b11..Reserved
*/
#define RDC_MRVS_VDID(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VDID_SHIFT)) & RDC_MRVS_VDID_MASK)
#define RDC_MRVS_AD_MASK (0x10U)
#define RDC_MRVS_AD_SHIFT (4U)
/*! AD - Access Denied
*/
#define RDC_MRVS_AD(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_AD_SHIFT)) & RDC_MRVS_AD_MASK)
#define RDC_MRVS_VADR_MASK (0xFFFFFFE0U)
#define RDC_MRVS_VADR_SHIFT (5U)
/*! VADR - Violating Address
*/
#define RDC_MRVS_VADR(x) (((uint32_t)(((uint32_t)(x)) << RDC_MRVS_VADR_SHIFT)) & RDC_MRVS_VADR_MASK)
/*! @} */
/* The count of RDC_MRVS */
#define RDC_MRVS_COUNT (59U)
/*!
* @}
*/ /* end of group RDC_Register_Masks */
/* RDC - Peripheral instance base addresses */
/** Peripheral RDC base address */
#define RDC_BASE (0x40C78000u)
/** Peripheral RDC base pointer */
#define RDC ((RDC_Type *)RDC_BASE)
/** Array initializer of RDC peripheral base addresses */
#define RDC_BASE_ADDRS { RDC_BASE }
/** Array initializer of RDC peripheral base pointers */
#define RDC_BASE_PTRS { RDC }
/** Interrupt vectors for the RDC peripheral type */
#define RDC_IRQS { RDC_IRQn }
/*!
* @}
*/ /* end of group RDC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RDC_SEMAPHORE Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RDC_SEMAPHORE_Peripheral_Access_Layer RDC_SEMAPHORE Peripheral Access Layer
* @{
*/
/** RDC_SEMAPHORE - Register Layout Typedef */
typedef struct {
__IO uint8_t GATE[64]; /**< Gate Register, array offset: 0x0, array step: 0x1 */
uint8_t RESERVED_0[2];
union { /* offset: 0x42 */
__IO uint16_t RSTGT_R; /**< Reset Gate Read, offset: 0x42 */
__IO uint16_t RSTGT_W; /**< Reset Gate Write, offset: 0x42 */
};
} RDC_SEMAPHORE_Type;
/* ----------------------------------------------------------------------------
-- RDC_SEMAPHORE Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RDC_SEMAPHORE_Register_Masks RDC_SEMAPHORE Register Masks
* @{
*/
/*! @name GATE - Gate Register */
/*! @{ */
#define RDC_SEMAPHORE_GATE_GTFSM_MASK (0xFU)
#define RDC_SEMAPHORE_GATE_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b0000..The gate is unlocked (free).
* 0b0001..The gate has been locked by processor with master_index = 0.
* 0b0010..The gate has been locked by processor with master_index = 1.
* 0b0011..The gate has been locked by processor with master_index = 2.
* 0b0100..The gate has been locked by processor with master_index = 3.
* 0b0101..The gate has been locked by processor with master_index = 4.
* 0b0110..The gate has been locked by processor with master_index = 5.
* 0b0111..The gate has been locked by processor with master_index = 6.
* 0b1000..The gate has been locked by processor with master_index = 7.
* 0b1001..The gate has been locked by processor with master_index = 8.
* 0b1010..The gate has been locked by processor with master_index = 9.
* 0b1011..The gate has been locked by processor with master_index = 10.
* 0b1100..The gate has been locked by processor with master_index = 11.
* 0b1101..The gate has been locked by processor with master_index = 12.
* 0b1110..The gate has been locked by processor with master_index = 13.
* 0b1111..The gate has been locked by processor with master_index = 14.
*/
#define RDC_SEMAPHORE_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_GTFSM_SHIFT)) & RDC_SEMAPHORE_GATE_GTFSM_MASK)
#define RDC_SEMAPHORE_GATE_LDOM_MASK (0x30U)
#define RDC_SEMAPHORE_GATE_LDOM_SHIFT (4U)
/*! LDOM
* 0b00..The gate is locked by domain 0. (True if the field GTFSM does not equal to 0000.)
* 0b01..The gate has been locked by domain 1.
* 0b10..Reserved
* 0b11..Reserved
*/
#define RDC_SEMAPHORE_GATE_LDOM(x) (((uint8_t)(((uint8_t)(x)) << RDC_SEMAPHORE_GATE_LDOM_SHIFT)) & RDC_SEMAPHORE_GATE_LDOM_MASK)
/*! @} */
/* The count of RDC_SEMAPHORE_GATE */
#define RDC_SEMAPHORE_GATE_COUNT (64U)
/*! @name RSTGT_R - Reset Gate Read */
/*! @{ */
#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK (0xFU)
#define RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT (0U)
#define RDC_SEMAPHORE_RSTGT_R_RSTGMS(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGMS_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGMS_MASK)
#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK (0x30U)
#define RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT (4U)
/*! RSTGSM
* 0b00..Idle, waiting for the first data pattern write.
* 0b01..Waiting for the second data pattern write.
* 0b10..The 2-write sequence has completed. Generate the specified gate reset(s). After the reset is performed,
* this machine returns to the idle (waiting for first data pattern write) state. The "01" state persists
* for only one clock cycle. Software will never be able to observe this state.
* 0b11..This state encoding is never used and therefore reserved.
*/
#define RDC_SEMAPHORE_RSTGT_R_RSTGSM(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGSM_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGSM_MASK)
#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK (0xFF00U)
#define RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT (8U)
#define RDC_SEMAPHORE_RSTGT_R_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_R_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_R_RSTGTN_MASK)
/*! @} */
/*! @name RSTGT_W - Reset Gate Write */
/*! @{ */
#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK (0xFFU)
#define RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT (0U)
#define RDC_SEMAPHORE_RSTGT_W_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGDP_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGDP_MASK)
#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK (0xFF00U)
#define RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT (8U)
#define RDC_SEMAPHORE_RSTGT_W_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << RDC_SEMAPHORE_RSTGT_W_RSTGTN_SHIFT)) & RDC_SEMAPHORE_RSTGT_W_RSTGTN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group RDC_SEMAPHORE_Register_Masks */
/* RDC_SEMAPHORE - Peripheral instance base addresses */
/** Peripheral RDC_SEMAPHORE1 base address */
#define RDC_SEMAPHORE1_BASE (0x40C44000u)
/** Peripheral RDC_SEMAPHORE1 base pointer */
#define RDC_SEMAPHORE1 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE1_BASE)
/** Peripheral RDC_SEMAPHORE2 base address */
#define RDC_SEMAPHORE2_BASE (0x40CCC000u)
/** Peripheral RDC_SEMAPHORE2 base pointer */
#define RDC_SEMAPHORE2 ((RDC_SEMAPHORE_Type *)RDC_SEMAPHORE2_BASE)
/** Array initializer of RDC_SEMAPHORE peripheral base addresses */
#define RDC_SEMAPHORE_BASE_ADDRS { RDC_SEMAPHORE1_BASE, RDC_SEMAPHORE2_BASE }
/** Array initializer of RDC_SEMAPHORE peripheral base pointers */
#define RDC_SEMAPHORE_BASE_PTRS { RDC_SEMAPHORE1, RDC_SEMAPHORE2 }
/*!
* @}
*/ /* end of group RDC_SEMAPHORE_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- RTWDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTWDOG_Peripheral_Access_Layer RTWDOG Peripheral Access Layer
* @{
*/
/** RTWDOG - Register Layout Typedef */
typedef struct {
__IO uint32_t CS; /**< Watchdog Control and Status Register, offset: 0x0 */
__IO uint32_t CNT; /**< Watchdog Counter Register, offset: 0x4 */
__IO uint32_t TOVAL; /**< Watchdog Timeout Value Register, offset: 0x8 */
__IO uint32_t WIN; /**< Watchdog Window Register, offset: 0xC */
} RTWDOG_Type;
/* ----------------------------------------------------------------------------
-- RTWDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup RTWDOG_Register_Masks RTWDOG Register Masks
* @{
*/
/*! @name CS - Watchdog Control and Status Register */
/*! @{ */
#define RTWDOG_CS_STOP_MASK (0x1U)
#define RTWDOG_CS_STOP_SHIFT (0U)
/*! STOP - Stop Enable
* 0b0..Watchdog disabled in chip stop mode.
* 0b1..Watchdog enabled in chip stop mode.
*/
#define RTWDOG_CS_STOP(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_STOP_SHIFT)) & RTWDOG_CS_STOP_MASK)
#define RTWDOG_CS_WAIT_MASK (0x2U)
#define RTWDOG_CS_WAIT_SHIFT (1U)
/*! WAIT - Wait Enable
* 0b0..Watchdog disabled in chip wait mode.
* 0b1..Watchdog enabled in chip wait mode.
*/
#define RTWDOG_CS_WAIT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WAIT_SHIFT)) & RTWDOG_CS_WAIT_MASK)
#define RTWDOG_CS_DBG_MASK (0x4U)
#define RTWDOG_CS_DBG_SHIFT (2U)
/*! DBG - Debug Enable
* 0b0..Watchdog disabled in chip debug mode.
* 0b1..Watchdog enabled in chip debug mode.
*/
#define RTWDOG_CS_DBG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_DBG_SHIFT)) & RTWDOG_CS_DBG_MASK)
#define RTWDOG_CS_TST_MASK (0x18U)
#define RTWDOG_CS_TST_SHIFT (3U)
/*! TST - Watchdog Test
* 0b00..Watchdog test mode disabled.
* 0b01..Watchdog user mode enabled. (Watchdog test mode disabled.) After testing the watchdog, software should
* use this setting to indicate that the watchdog is functioning normally in user mode.
* 0b10..Watchdog test mode enabled, only the low byte is used. CNT[CNTLOW] is compared with TOVAL[TOVALLOW].
* 0b11..Watchdog test mode enabled, only the high byte is used. CNT[CNTHIGH] is compared with TOVAL[TOVALHIGH].
*/
#define RTWDOG_CS_TST(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_TST_SHIFT)) & RTWDOG_CS_TST_MASK)
#define RTWDOG_CS_UPDATE_MASK (0x20U)
#define RTWDOG_CS_UPDATE_SHIFT (5U)
/*! UPDATE - Allow updates
* 0b0..Updates not allowed. After the initial configuration, the watchdog cannot be later modified without forcing a reset.
* 0b1..Updates allowed. Software can modify the watchdog configuration registers within 255 bus clocks after performing the unlock write sequence.
*/
#define RTWDOG_CS_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_UPDATE_SHIFT)) & RTWDOG_CS_UPDATE_MASK)
#define RTWDOG_CS_INT_MASK (0x40U)
#define RTWDOG_CS_INT_SHIFT (6U)
/*! INT - Watchdog Interrupt
* 0b0..Watchdog interrupts are disabled. Watchdog resets are not delayed.
* 0b1..Watchdog interrupts are enabled. Watchdog resets are delayed by 255 bus clocks from the interrupt vector fetch.
*/
#define RTWDOG_CS_INT(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_INT_SHIFT)) & RTWDOG_CS_INT_MASK)
#define RTWDOG_CS_EN_MASK (0x80U)
#define RTWDOG_CS_EN_SHIFT (7U)
/*! EN - Watchdog Enable
* 0b0..Watchdog disabled.
* 0b1..Watchdog enabled.
*/
#define RTWDOG_CS_EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_EN_SHIFT)) & RTWDOG_CS_EN_MASK)
#define RTWDOG_CS_CLK_MASK (0x300U)
#define RTWDOG_CS_CLK_SHIFT (8U)
/*! CLK - Watchdog Clock
*/
#define RTWDOG_CS_CLK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CLK_SHIFT)) & RTWDOG_CS_CLK_MASK)
#define RTWDOG_CS_RCS_MASK (0x400U)
#define RTWDOG_CS_RCS_SHIFT (10U)
/*! RCS - Reconfiguration Success
* 0b0..Reconfiguring WDOG.
* 0b1..Reconfiguration is successful.
*/
#define RTWDOG_CS_RCS(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_RCS_SHIFT)) & RTWDOG_CS_RCS_MASK)
#define RTWDOG_CS_ULK_MASK (0x800U)
#define RTWDOG_CS_ULK_SHIFT (11U)
/*! ULK - Unlock status
* 0b0..WDOG is locked.
* 0b1..WDOG is unlocked.
*/
#define RTWDOG_CS_ULK(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_ULK_SHIFT)) & RTWDOG_CS_ULK_MASK)
#define RTWDOG_CS_PRES_MASK (0x1000U)
#define RTWDOG_CS_PRES_SHIFT (12U)
/*! PRES - Watchdog prescaler
* 0b0..256 prescaler disabled.
* 0b1..256 prescaler enabled.
*/
#define RTWDOG_CS_PRES(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_PRES_SHIFT)) & RTWDOG_CS_PRES_MASK)
#define RTWDOG_CS_CMD32EN_MASK (0x2000U)
#define RTWDOG_CS_CMD32EN_SHIFT (13U)
/*! CMD32EN - Enables or disables WDOG support for 32-bit (otherwise 16-bit or 8-bit) refresh/unlock command write words
* 0b0..Disables support for 32-bit refresh/unlock command write words. Only 16-bit or 8-bit is supported.
* 0b1..Enables support for 32-bit refresh/unlock command write words. 16-bit or 8-bit is NOT supported.
*/
#define RTWDOG_CS_CMD32EN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_CMD32EN_SHIFT)) & RTWDOG_CS_CMD32EN_MASK)
#define RTWDOG_CS_FLG_MASK (0x4000U)
#define RTWDOG_CS_FLG_SHIFT (14U)
/*! FLG - Watchdog Interrupt Flag
* 0b0..No interrupt occurred.
* 0b1..An interrupt occurred.
*/
#define RTWDOG_CS_FLG(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_FLG_SHIFT)) & RTWDOG_CS_FLG_MASK)
#define RTWDOG_CS_WIN_MASK (0x8000U)
#define RTWDOG_CS_WIN_SHIFT (15U)
/*! WIN - Watchdog Window
* 0b0..Window mode disabled.
* 0b1..Window mode enabled.
*/
#define RTWDOG_CS_WIN(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CS_WIN_SHIFT)) & RTWDOG_CS_WIN_MASK)
/*! @} */
/*! @name CNT - Watchdog Counter Register */
/*! @{ */
#define RTWDOG_CNT_CNTLOW_MASK (0xFFU)
#define RTWDOG_CNT_CNTLOW_SHIFT (0U)
/*! CNTLOW - Low byte of the Watchdog Counter
*/
#define RTWDOG_CNT_CNTLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTLOW_SHIFT)) & RTWDOG_CNT_CNTLOW_MASK)
#define RTWDOG_CNT_CNTHIGH_MASK (0xFF00U)
#define RTWDOG_CNT_CNTHIGH_SHIFT (8U)
/*! CNTHIGH - High byte of the Watchdog Counter
*/
#define RTWDOG_CNT_CNTHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_CNT_CNTHIGH_SHIFT)) & RTWDOG_CNT_CNTHIGH_MASK)
/*! @} */
/*! @name TOVAL - Watchdog Timeout Value Register */
/*! @{ */
#define RTWDOG_TOVAL_TOVALLOW_MASK (0xFFU)
#define RTWDOG_TOVAL_TOVALLOW_SHIFT (0U)
/*! TOVALLOW - Low byte of the timeout value
*/
#define RTWDOG_TOVAL_TOVALLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALLOW_SHIFT)) & RTWDOG_TOVAL_TOVALLOW_MASK)
#define RTWDOG_TOVAL_TOVALHIGH_MASK (0xFF00U)
#define RTWDOG_TOVAL_TOVALHIGH_SHIFT (8U)
/*! TOVALHIGH - High byte of the timeout value
*/
#define RTWDOG_TOVAL_TOVALHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_TOVAL_TOVALHIGH_SHIFT)) & RTWDOG_TOVAL_TOVALHIGH_MASK)
/*! @} */
/*! @name WIN - Watchdog Window Register */
/*! @{ */
#define RTWDOG_WIN_WINLOW_MASK (0xFFU)
#define RTWDOG_WIN_WINLOW_SHIFT (0U)
/*! WINLOW - Low byte of Watchdog Window
*/
#define RTWDOG_WIN_WINLOW(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINLOW_SHIFT)) & RTWDOG_WIN_WINLOW_MASK)
#define RTWDOG_WIN_WINHIGH_MASK (0xFF00U)
#define RTWDOG_WIN_WINHIGH_SHIFT (8U)
/*! WINHIGH - High byte of Watchdog Window
*/
#define RTWDOG_WIN_WINHIGH(x) (((uint32_t)(((uint32_t)(x)) << RTWDOG_WIN_WINHIGH_SHIFT)) & RTWDOG_WIN_WINHIGH_MASK)
/*! @} */
/*!
* @}
*/ /* end of group RTWDOG_Register_Masks */
/* RTWDOG - Peripheral instance base addresses */
/** Peripheral RTWDOG3 base address */
#define RTWDOG3_BASE (0x40038000u)
/** Peripheral RTWDOG3 base pointer */
#define RTWDOG3 ((RTWDOG_Type *)RTWDOG3_BASE)
/** Peripheral RTWDOG4 base address */
#define RTWDOG4_BASE (0x40C10000u)
/** Peripheral RTWDOG4 base pointer */
#define RTWDOG4 ((RTWDOG_Type *)RTWDOG4_BASE)
/** Array initializer of RTWDOG peripheral base addresses */
#define RTWDOG_BASE_ADDRS { 0u, 0u, 0u, RTWDOG3_BASE, RTWDOG4_BASE }
/** Array initializer of RTWDOG peripheral base pointers */
#define RTWDOG_BASE_PTRS { (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, (RTWDOG_Type *)0u, RTWDOG3, RTWDOG4 }
/** Interrupt vectors for the RTWDOG peripheral type */
#define RTWDOG_IRQS { NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, RTWDOG3_IRQn, NotAvail_IRQn }
/* Extra definition */
#define RTWDOG_UPDATE_KEY (0xD928C520U)
#define RTWDOG_REFRESH_KEY (0xB480A602U)
/*!
* @}
*/ /* end of group RTWDOG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SEMA4 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEMA4_Peripheral_Access_Layer SEMA4 Peripheral Access Layer
* @{
*/
/** SEMA4 - Register Layout Typedef */
typedef struct {
__IO uint8_t GATE[16]; /**< Semaphores Gate n Register, array offset: 0x0, array step: 0x1 */
uint8_t RESERVED_0[48];
struct { /* offset: 0x40, array step: 0x8 */
__IO uint16_t CPINE; /**< Semaphores Processor n IRQ Notification Enable, array offset: 0x40, array step: 0x8 */
uint8_t RESERVED_0[6];
} CPINE[2];
uint8_t RESERVED_1[48];
struct { /* offset: 0x80, array step: 0x8 */
__I uint16_t CPNTF; /**< Semaphores Processor n IRQ Notification, array offset: 0x80, array step: 0x8 */
uint8_t RESERVED_0[6];
} CPNTF[2];
uint8_t RESERVED_2[112];
__IO uint16_t RSTGT; /**< Semaphores (Secure) Reset Gate n, offset: 0x100 */
uint8_t RESERVED_3[2];
__IO uint16_t RSTNTF; /**< Semaphores (Secure) Reset IRQ Notification, offset: 0x104 */
} SEMA4_Type;
/* ----------------------------------------------------------------------------
-- SEMA4 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEMA4_Register_Masks SEMA4 Register Masks
* @{
*/
/*! @name GATE - Semaphores Gate n Register */
/*! @{ */
#define SEMA4_GATE_GTFSM_MASK (0x3U)
#define SEMA4_GATE_GTFSM_SHIFT (0U)
/*! GTFSM - Gate Finite State Machine.
* 0b00..The gate is unlocked (free).
* 0b01..The gate has been locked by processor 0.
* 0b10..The gate has been locked by processor 1.
* 0b11..This state encoding is never used and therefore reserved. Attempted writes of 0x03 are treated as "no
* operation" and do not affect the gate state machine.
*/
#define SEMA4_GATE_GTFSM(x) (((uint8_t)(((uint8_t)(x)) << SEMA4_GATE_GTFSM_SHIFT)) & SEMA4_GATE_GTFSM_MASK)
/*! @} */
/* The count of SEMA4_GATE */
#define SEMA4_GATE_COUNT (16U)
/*! @name CPINE - Semaphores Processor n IRQ Notification Enable */
/*! @{ */
#define SEMA4_CPINE_INE7_MASK (0x1U)
#define SEMA4_CPINE_INE7_SHIFT (0U)
/*! INE7 - Interrupt Request Notification Enable 7. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 7.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE7_SHIFT)) & SEMA4_CPINE_INE7_MASK)
#define SEMA4_CPINE_INE6_MASK (0x2U)
#define SEMA4_CPINE_INE6_SHIFT (1U)
/*! INE6 - Interrupt Request Notification Enable 6. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 6.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE6_SHIFT)) & SEMA4_CPINE_INE6_MASK)
#define SEMA4_CPINE_INE5_MASK (0x4U)
#define SEMA4_CPINE_INE5_SHIFT (2U)
/*! INE5 - Interrupt Request Notification Enable 5. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 5.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE5_SHIFT)) & SEMA4_CPINE_INE5_MASK)
#define SEMA4_CPINE_INE4_MASK (0x8U)
#define SEMA4_CPINE_INE4_SHIFT (3U)
/*! INE4 - Interrupt Request Notification Enable 4. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 4.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE4_SHIFT)) & SEMA4_CPINE_INE4_MASK)
#define SEMA4_CPINE_INE3_MASK (0x10U)
#define SEMA4_CPINE_INE3_SHIFT (4U)
/*! INE3
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE3_SHIFT)) & SEMA4_CPINE_INE3_MASK)
#define SEMA4_CPINE_INE2_MASK (0x20U)
#define SEMA4_CPINE_INE2_SHIFT (5U)
/*! INE2
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE2_SHIFT)) & SEMA4_CPINE_INE2_MASK)
#define SEMA4_CPINE_INE1_MASK (0x40U)
#define SEMA4_CPINE_INE1_SHIFT (6U)
/*! INE1
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE1_SHIFT)) & SEMA4_CPINE_INE1_MASK)
#define SEMA4_CPINE_INE0_MASK (0x80U)
#define SEMA4_CPINE_INE0_SHIFT (7U)
/*! INE0
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE0_SHIFT)) & SEMA4_CPINE_INE0_MASK)
#define SEMA4_CPINE_INE15_MASK (0x100U)
#define SEMA4_CPINE_INE15_SHIFT (8U)
/*! INE15 - Interrupt Request Notification Enable 15. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 15.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE15_SHIFT)) & SEMA4_CPINE_INE15_MASK)
#define SEMA4_CPINE_INE14_MASK (0x200U)
#define SEMA4_CPINE_INE14_SHIFT (9U)
/*! INE14 - Interrupt Request Notification Enable 14. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 14.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE14_SHIFT)) & SEMA4_CPINE_INE14_MASK)
#define SEMA4_CPINE_INE13_MASK (0x400U)
#define SEMA4_CPINE_INE13_SHIFT (10U)
/*! INE13 - Interrupt Request Notification Enable 13. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 13.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE13_SHIFT)) & SEMA4_CPINE_INE13_MASK)
#define SEMA4_CPINE_INE12_MASK (0x800U)
#define SEMA4_CPINE_INE12_SHIFT (11U)
/*! INE12 - Interrupt Request Notification Enable 12. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 12.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE12_SHIFT)) & SEMA4_CPINE_INE12_MASK)
#define SEMA4_CPINE_INE11_MASK (0x1000U)
#define SEMA4_CPINE_INE11_SHIFT (12U)
/*! INE11 - Interrupt Request Notification Enable 11. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 11.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE11_SHIFT)) & SEMA4_CPINE_INE11_MASK)
#define SEMA4_CPINE_INE10_MASK (0x2000U)
#define SEMA4_CPINE_INE10_SHIFT (13U)
/*! INE10 - Interrupt Request Notification Enable 10. This field is a bitmap to enable the
* generation of an interrupt notification from a failed attempt to lock gate 10.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE10_SHIFT)) & SEMA4_CPINE_INE10_MASK)
#define SEMA4_CPINE_INE9_MASK (0x4000U)
#define SEMA4_CPINE_INE9_SHIFT (14U)
/*! INE9 - Interrupt Request Notification Enable 9. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 9.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE9_SHIFT)) & SEMA4_CPINE_INE9_MASK)
#define SEMA4_CPINE_INE8_MASK (0x8000U)
#define SEMA4_CPINE_INE8_SHIFT (15U)
/*! INE8 - Interrupt Request Notification Enable 8. This field is a bitmap to enable the generation
* of an interrupt notification from a failed attempt to lock gate 8.
* 0b0..The generation of the notification interrupt is disabled.
* 0b1..The generation of the notification interrupt is enabled.
*/
#define SEMA4_CPINE_INE8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPINE_INE8_SHIFT)) & SEMA4_CPINE_INE8_MASK)
/*! @} */
/* The count of SEMA4_CPINE */
#define SEMA4_CPINE_COUNT (2U)
/*! @name CPNTF - Semaphores Processor n IRQ Notification */
/*! @{ */
#define SEMA4_CPNTF_GN7_MASK (0x1U)
#define SEMA4_CPNTF_GN7_SHIFT (0U)
#define SEMA4_CPNTF_GN7(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN7_SHIFT)) & SEMA4_CPNTF_GN7_MASK)
#define SEMA4_CPNTF_GN6_MASK (0x2U)
#define SEMA4_CPNTF_GN6_SHIFT (1U)
#define SEMA4_CPNTF_GN6(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN6_SHIFT)) & SEMA4_CPNTF_GN6_MASK)
#define SEMA4_CPNTF_GN5_MASK (0x4U)
#define SEMA4_CPNTF_GN5_SHIFT (2U)
#define SEMA4_CPNTF_GN5(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN5_SHIFT)) & SEMA4_CPNTF_GN5_MASK)
#define SEMA4_CPNTF_GN4_MASK (0x8U)
#define SEMA4_CPNTF_GN4_SHIFT (3U)
#define SEMA4_CPNTF_GN4(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN4_SHIFT)) & SEMA4_CPNTF_GN4_MASK)
#define SEMA4_CPNTF_GN3_MASK (0x10U)
#define SEMA4_CPNTF_GN3_SHIFT (4U)
#define SEMA4_CPNTF_GN3(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN3_SHIFT)) & SEMA4_CPNTF_GN3_MASK)
#define SEMA4_CPNTF_GN2_MASK (0x20U)
#define SEMA4_CPNTF_GN2_SHIFT (5U)
#define SEMA4_CPNTF_GN2(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN2_SHIFT)) & SEMA4_CPNTF_GN2_MASK)
#define SEMA4_CPNTF_GN1_MASK (0x40U)
#define SEMA4_CPNTF_GN1_SHIFT (6U)
#define SEMA4_CPNTF_GN1(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN1_SHIFT)) & SEMA4_CPNTF_GN1_MASK)
#define SEMA4_CPNTF_GN0_MASK (0x80U)
#define SEMA4_CPNTF_GN0_SHIFT (7U)
#define SEMA4_CPNTF_GN0(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN0_SHIFT)) & SEMA4_CPNTF_GN0_MASK)
#define SEMA4_CPNTF_GN15_MASK (0x100U)
#define SEMA4_CPNTF_GN15_SHIFT (8U)
#define SEMA4_CPNTF_GN15(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN15_SHIFT)) & SEMA4_CPNTF_GN15_MASK)
#define SEMA4_CPNTF_GN14_MASK (0x200U)
#define SEMA4_CPNTF_GN14_SHIFT (9U)
#define SEMA4_CPNTF_GN14(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN14_SHIFT)) & SEMA4_CPNTF_GN14_MASK)
#define SEMA4_CPNTF_GN13_MASK (0x400U)
#define SEMA4_CPNTF_GN13_SHIFT (10U)
#define SEMA4_CPNTF_GN13(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN13_SHIFT)) & SEMA4_CPNTF_GN13_MASK)
#define SEMA4_CPNTF_GN12_MASK (0x800U)
#define SEMA4_CPNTF_GN12_SHIFT (11U)
#define SEMA4_CPNTF_GN12(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN12_SHIFT)) & SEMA4_CPNTF_GN12_MASK)
#define SEMA4_CPNTF_GN11_MASK (0x1000U)
#define SEMA4_CPNTF_GN11_SHIFT (12U)
#define SEMA4_CPNTF_GN11(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN11_SHIFT)) & SEMA4_CPNTF_GN11_MASK)
#define SEMA4_CPNTF_GN10_MASK (0x2000U)
#define SEMA4_CPNTF_GN10_SHIFT (13U)
#define SEMA4_CPNTF_GN10(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN10_SHIFT)) & SEMA4_CPNTF_GN10_MASK)
#define SEMA4_CPNTF_GN9_MASK (0x4000U)
#define SEMA4_CPNTF_GN9_SHIFT (14U)
#define SEMA4_CPNTF_GN9(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN9_SHIFT)) & SEMA4_CPNTF_GN9_MASK)
#define SEMA4_CPNTF_GN8_MASK (0x8000U)
#define SEMA4_CPNTF_GN8_SHIFT (15U)
#define SEMA4_CPNTF_GN8(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_CPNTF_GN8_SHIFT)) & SEMA4_CPNTF_GN8_MASK)
/*! @} */
/* The count of SEMA4_CPNTF */
#define SEMA4_CPNTF_COUNT (2U)
/*! @name RSTGT - Semaphores (Secure) Reset Gate n */
/*! @{ */
#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK (0xFFU)
#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT (0U)
#define SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_SHIFT)) & SEMA4_RSTGT_RSTGSM_RSTGMS_RSTGDP_MASK)
#define SEMA4_RSTGT_RSTGTN_MASK (0xFF00U)
#define SEMA4_RSTGT_RSTGTN_SHIFT (8U)
#define SEMA4_RSTGT_RSTGTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTGT_RSTGTN_SHIFT)) & SEMA4_RSTGT_RSTGTN_MASK)
/*! @} */
/*! @name RSTNTF - Semaphores (Secure) Reset IRQ Notification */
/*! @{ */
#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK (0xFFU)
#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT (0U)
#define SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_SHIFT)) & SEMA4_RSTNTF_RSTNSM_RSTNMS_RSTNDP_MASK)
#define SEMA4_RSTNTF_RSTNTN_MASK (0xFF00U)
#define SEMA4_RSTNTF_RSTNTN_SHIFT (8U)
#define SEMA4_RSTNTF_RSTNTN(x) (((uint16_t)(((uint16_t)(x)) << SEMA4_RSTNTF_RSTNTN_SHIFT)) & SEMA4_RSTNTF_RSTNTN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SEMA4_Register_Masks */
/* SEMA4 - Peripheral instance base addresses */
/** Peripheral SEMA4 base address */
#define SEMA4_BASE (0x40CC8000u)
/** Peripheral SEMA4 base pointer */
#define SEMA4 ((SEMA4_Type *)SEMA4_BASE)
/** Array initializer of SEMA4 peripheral base addresses */
#define SEMA4_BASE_ADDRS { SEMA4_BASE }
/** Array initializer of SEMA4 peripheral base pointers */
#define SEMA4_BASE_PTRS { SEMA4 }
/*!
* @}
*/ /* end of group SEMA4_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SEMC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEMC_Peripheral_Access_Layer SEMC Peripheral Access Layer
* @{
*/
/** SEMC - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */
__IO uint32_t IOCR; /**< IO MUX Control Register, offset: 0x4 */
__IO uint32_t BMCR0; /**< Bus (AXI) Master Control Register 0, offset: 0x8 */
__IO uint32_t BMCR1; /**< Bus (AXI) Master Control Register 1, offset: 0xC */
__IO uint32_t BR[9]; /**< Base Register 0..Base Register 8, array offset: 0x10, array step: 0x4 */
__IO uint32_t DLLCR; /**< DLL Control Register, offset: 0x34 */
__IO uint32_t INTEN; /**< Interrupt Enable Register, offset: 0x38 */
__IO uint32_t INTR; /**< Interrupt Register, offset: 0x3C */
__IO uint32_t SDRAMCR0; /**< SDRAM Control Register 0, offset: 0x40 */
__IO uint32_t SDRAMCR1; /**< SDRAM Control Register 1, offset: 0x44 */
__IO uint32_t SDRAMCR2; /**< SDRAM Control Register 2, offset: 0x48 */
__IO uint32_t SDRAMCR3; /**< SDRAM Control Register 3, offset: 0x4C */
__IO uint32_t NANDCR0; /**< NAND Control Register 0, offset: 0x50 */
__IO uint32_t NANDCR1; /**< NAND Control Register 1, offset: 0x54 */
__IO uint32_t NANDCR2; /**< NAND Control Register 2, offset: 0x58 */
__IO uint32_t NANDCR3; /**< NAND Control Register 3, offset: 0x5C */
__IO uint32_t NORCR0; /**< NOR Control Register 0, offset: 0x60 */
__IO uint32_t NORCR1; /**< NOR Control Register 1, offset: 0x64 */
__IO uint32_t NORCR2; /**< NOR Control Register 2, offset: 0x68 */
__IO uint32_t NORCR3; /**< NOR Control Register 3, offset: 0x6C */
__IO uint32_t SRAMCR0; /**< SRAM Control Register 0, offset: 0x70 */
__IO uint32_t SRAMCR1; /**< SRAM Control Register 1, offset: 0x74 */
__IO uint32_t SRAMCR2; /**< SRAM Control Register 2, offset: 0x78 */
uint32_t SRAMCR3; /**< SRAM Control Register 3, offset: 0x7C */
__IO uint32_t DBICR0; /**< DBI-B Control Register 0, offset: 0x80 */
__IO uint32_t DBICR1; /**< DBI-B Control Register 1, offset: 0x84 */
__IO uint32_t DBICR2; /**< DBI-B Control Register 2, offset: 0x88 */
uint8_t RESERVED_0[4];
__IO uint32_t IPCR0; /**< IP Command Control Register 0, offset: 0x90 */
__IO uint32_t IPCR1; /**< IP Command Control Register 1, offset: 0x94 */
__IO uint32_t IPCR2; /**< IP Command Control Register 2, offset: 0x98 */
__IO uint32_t IPCMD; /**< IP Command Register, offset: 0x9C */
__IO uint32_t IPTXDAT; /**< TX DATA Register, offset: 0xA0 */
uint8_t RESERVED_1[12];
__I uint32_t IPRXDAT; /**< RX DATA Register, offset: 0xB0 */
uint8_t RESERVED_2[12];
__I uint32_t STS0; /**< Status Register 0, offset: 0xC0 */
uint32_t STS1; /**< Status Register 1, offset: 0xC4 */
__I uint32_t STS2; /**< Status Register 2, offset: 0xC8 */
uint32_t STS3; /**< Status Register 3, offset: 0xCC */
uint32_t STS4; /**< Status Register 4, offset: 0xD0 */
uint32_t STS5; /**< Status Register 5, offset: 0xD4 */
uint32_t STS6; /**< Status Register 6, offset: 0xD8 */
uint32_t STS7; /**< Status Register 7, offset: 0xDC */
uint32_t STS8; /**< Status Register 8, offset: 0xE0 */
uint32_t STS9; /**< Status Register 9, offset: 0xE4 */
uint32_t STS10; /**< Status Register 10, offset: 0xE8 */
uint32_t STS11; /**< Status Register 11, offset: 0xEC */
__I uint32_t STS12; /**< Status Register 12, offset: 0xF0 */
__I uint32_t STS13; /**< Status Register 13, offset: 0xF4 */
uint32_t STS14; /**< Status Register 14, offset: 0xF8 */
uint32_t STS15; /**< Status Register 15, offset: 0xFC */
__IO uint32_t BR9; /**< Base Register 9, offset: 0x100 */
__IO uint32_t BR10; /**< Base Register 10, offset: 0x104 */
__IO uint32_t BR11; /**< Base Register 11, offset: 0x108 */
uint8_t RESERVED_3[20];
__IO uint32_t SRAMCR4; /**< SRAM Control Register 4, offset: 0x120 */
__IO uint32_t SRAMCR5; /**< SRAM Control Register 5, offset: 0x124 */
__IO uint32_t SRAMCR6; /**< SRAM Control Register 6, offset: 0x128 */
uint8_t RESERVED_4[36];
__IO uint32_t DCCR; /**< Delay Chain Control Register, offset: 0x150 */
} SEMC_Type;
/* ----------------------------------------------------------------------------
-- SEMC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SEMC_Register_Masks SEMC Register Masks
* @{
*/
/*! @name MCR - Module Control Register */
/*! @{ */
#define SEMC_MCR_SWRST_MASK (0x1U)
#define SEMC_MCR_SWRST_SHIFT (0U)
/*! SWRST - Software Reset
* 0b0..No reset
* 0b1..Reset
*/
#define SEMC_MCR_SWRST(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_SWRST_SHIFT)) & SEMC_MCR_SWRST_MASK)
#define SEMC_MCR_MDIS_MASK (0x2U)
#define SEMC_MCR_MDIS_SHIFT (1U)
/*! MDIS - Module Disable
* 0b0..Module enabled
* 0b1..Module disabled
*/
#define SEMC_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_MDIS_SHIFT)) & SEMC_MCR_MDIS_MASK)
#define SEMC_MCR_DQSMD_MASK (0x4U)
#define SEMC_MCR_DQSMD_SHIFT (2U)
/*! DQSMD - DQS (read strobe) mode
* 0b0..Dummy read strobe loopbacked internally
* 0b1..Dummy read strobe loopbacked from DQS pad
*/
#define SEMC_MCR_DQSMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_DQSMD_SHIFT)) & SEMC_MCR_DQSMD_MASK)
#define SEMC_MCR_WPOL0_MASK (0x40U)
#define SEMC_MCR_WPOL0_SHIFT (6U)
/*! WPOL0 - WAIT/RDY polarity for SRAM/NOR
* 0b0..WAIT/RDY polarity is not changed.
* 0b1..WAIT/RDY polarity is inverted.
*/
#define SEMC_MCR_WPOL0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL0_SHIFT)) & SEMC_MCR_WPOL0_MASK)
#define SEMC_MCR_WPOL1_MASK (0x80U)
#define SEMC_MCR_WPOL1_SHIFT (7U)
/*! WPOL1 - R/B# polarity for NAND device
* 0b0..R/B# polarity is not changed.
* 0b1..R/B# polarity is inverted.
*/
#define SEMC_MCR_WPOL1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_WPOL1_SHIFT)) & SEMC_MCR_WPOL1_MASK)
#define SEMC_MCR_CTO_MASK (0xFF0000U)
#define SEMC_MCR_CTO_SHIFT (16U)
/*! CTO - Command Execution timeout cycles
*/
#define SEMC_MCR_CTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_CTO_SHIFT)) & SEMC_MCR_CTO_MASK)
#define SEMC_MCR_BTO_MASK (0x1F000000U)
#define SEMC_MCR_BTO_SHIFT (24U)
/*! BTO - Bus timeout cycles
* 0b00000..255*1
* 0b00001..255*2
* 0b11111..255*231
*/
#define SEMC_MCR_BTO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_MCR_BTO_SHIFT)) & SEMC_MCR_BTO_MASK)
/*! @} */
/*! @name IOCR - IO MUX Control Register */
/*! @{ */
#define SEMC_IOCR_MUX_A8_MASK (0xFU)
#define SEMC_IOCR_MUX_A8_SHIFT (0U)
/*! MUX_A8 - SEMC_ADDR08 output selection
* 0b0000-0b0011..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode
* 0b0100..NAND CE#
* 0b0101..NOR CE#
* 0b0110..SRAM CE# 0
* 0b0111..DBI CSX
* 0b1000..SRAM CE# 1
* 0b1001..SRAM CE# 2
* 0b1010..SRAM CE# 3
* 0b1011-0b1111..SDRAM Address bit 8 (A8) or NOR/SRAM Address bit 24 (A24) in ADMUX 16bit mode
*/
#define SEMC_IOCR_MUX_A8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_A8_SHIFT)) & SEMC_IOCR_MUX_A8_MASK)
#define SEMC_IOCR_MUX_CSX0_MASK (0xF0U)
#define SEMC_IOCR_MUX_CSX0_SHIFT (4U)
/*! MUX_CSX0 - SEMC_CSX0 output selection
* 0b0000..NOR/SRAM Address bit 24 (A24) in Non-ADMUX mode
* 0b0001..SDRAM CS1
* 0b0010..SDRAM CS2
* 0b0011..SDRAM CS3
* 0b0100..NAND CE#
* 0b0101..NOR CE#
* 0b0110..SRAM CE# 0
* 0b0111..DBI CSX
* 0b1000..SRAM CE# 1
* 0b1001..SRAM CE# 2
* 0b1010..SRAM CE# 3
* 0b1011-0b1111..NOR/SRAM Address bit 24 (A24)
*/
#define SEMC_IOCR_MUX_CSX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX0_SHIFT)) & SEMC_IOCR_MUX_CSX0_MASK)
#define SEMC_IOCR_MUX_CSX1_MASK (0xF00U)
#define SEMC_IOCR_MUX_CSX1_SHIFT (8U)
/*! MUX_CSX1 - SEMC_CSX1 output selection
* 0b0000..NOR/SRAM Address bit 25 (A25) in Non-ADMUX mode
* 0b0001..SDRAM CS1
* 0b0010..SDRAM CS2
* 0b0011..SDRAM CS3
* 0b0100..NAND CE#
* 0b0101..NOR CE#
* 0b0110..SRAM CE# 0
* 0b0111..DBI CSX
* 0b1000..SRAM CE# 1
* 0b1001..SRAM CE# 2
* 0b1010..SRAM CE# 3
* 0b1011-0b1111..NOR/SRAM Address bit 25 (A25)
*/
#define SEMC_IOCR_MUX_CSX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX1_SHIFT)) & SEMC_IOCR_MUX_CSX1_MASK)
#define SEMC_IOCR_MUX_CSX2_MASK (0xF000U)
#define SEMC_IOCR_MUX_CSX2_SHIFT (12U)
/*! MUX_CSX2 - SEMC_CSX2 output selection
* 0b0000..NOR/SRAM Address bit 26 (A26) in Non-ADMUX mode
* 0b0001..SDRAM CS1
* 0b0010..SDRAM CS2
* 0b0011..SDRAM CS3
* 0b0100..NAND CE#
* 0b0101..NOR CE#
* 0b0110..SRAM CE# 0
* 0b0111..DBI CSX
* 0b1000..SRAM CE# 1
* 0b1001..SRAM CE# 2
* 0b1010..SRAM CE# 3
* 0b1011-0b1111..NOR/SRAM Address bit 26 (A26)
*/
#define SEMC_IOCR_MUX_CSX2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX2_SHIFT)) & SEMC_IOCR_MUX_CSX2_MASK)
#define SEMC_IOCR_MUX_CSX3_MASK (0xF0000U)
#define SEMC_IOCR_MUX_CSX3_SHIFT (16U)
/*! MUX_CSX3 - SEMC_CSX3 output selection
* 0b0000..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode
* 0b0001..SDRAM CS1
* 0b0010..SDRAM CS2
* 0b0011..SDRAM CS3
* 0b0100..NAND CE#
* 0b0101..NOR CE#
* 0b0110..SRAM CE# 0
* 0b0111..DBI CSX
* 0b1000..SRAM CE# 1
* 0b1001..SRAM CE# 2
* 0b1010..SRAM CE# 3
* 0b1011-0b1111..NOR/SRAM Address bit 27 (A27)
*/
#define SEMC_IOCR_MUX_CSX3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CSX3_SHIFT)) & SEMC_IOCR_MUX_CSX3_MASK)
#define SEMC_IOCR_MUX_RDY_MASK (0xF00000U)
#define SEMC_IOCR_MUX_RDY_SHIFT (20U)
/*! MUX_RDY - SEMC_RDY function selection
* 0b0000..NAND R/B# input
* 0b0001..SDRAM CS1
* 0b0010..SDRAM CS2
* 0b0011..SDRAM CS3
* 0b0100..NOR/SRAM Address bit 27 (A27) in Non-ADMUX mode
* 0b0101..NOR CE#
* 0b0110..SRAM CE# 0
* 0b0111..DBI CSX
* 0b1000..SRAM CE# 1
* 0b1001..SRAM CE# 2
* 0b1010..SRAM CE# 3
* 0b1011-0b1111..NOR/SRAM Address bit 27
*/
#define SEMC_IOCR_MUX_RDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_RDY_SHIFT)) & SEMC_IOCR_MUX_RDY_MASK)
#define SEMC_IOCR_MUX_CLKX0_MASK (0x3000000U)
#define SEMC_IOCR_MUX_CLKX0_SHIFT (24U)
/*! MUX_CLKX0 - SEMC_CLKX0 function selection
* 0b00..Keep low
* 0b01..NOR clock
* 0b10..SRAM clock
* 0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
*/
#define SEMC_IOCR_MUX_CLKX0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX0_SHIFT)) & SEMC_IOCR_MUX_CLKX0_MASK)
#define SEMC_IOCR_MUX_CLKX1_MASK (0xC000000U)
#define SEMC_IOCR_MUX_CLKX1_SHIFT (26U)
/*! MUX_CLKX1 - SEMC_CLKX1 function selection
* 0b00..Keep low
* 0b01..NOR clock
* 0b10..SRAM clock
* 0b11..NOR and SRAM clock, suitable for Multi-Chip Product package
*/
#define SEMC_IOCR_MUX_CLKX1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_MUX_CLKX1_SHIFT)) & SEMC_IOCR_MUX_CLKX1_MASK)
#define SEMC_IOCR_CLKX0_AO_MASK (0x10000000U)
#define SEMC_IOCR_CLKX0_AO_SHIFT (28U)
/*! CLKX0_AO - SEMC_CLKX0 Always On
* 0b0..SEMC_CLKX0 is controlled by MUX_CLKX0
* 0b1..SEMC_CLKX0 is always on
*/
#define SEMC_IOCR_CLKX0_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX0_AO_SHIFT)) & SEMC_IOCR_CLKX0_AO_MASK)
#define SEMC_IOCR_CLKX1_AO_MASK (0x20000000U)
#define SEMC_IOCR_CLKX1_AO_SHIFT (29U)
/*! CLKX1_AO - SEMC_CLKX1 Always On
* 0b0..SEMC_CLKX1 is controlled by MUX_CLKX1
* 0b1..SEMC_CLKX1 is always on
*/
#define SEMC_IOCR_CLKX1_AO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IOCR_CLKX1_AO_SHIFT)) & SEMC_IOCR_CLKX1_AO_MASK)
/*! @} */
/*! @name BMCR0 - Bus (AXI) Master Control Register 0 */
/*! @{ */
#define SEMC_BMCR0_WQOS_MASK (0xFU)
#define SEMC_BMCR0_WQOS_SHIFT (0U)
/*! WQOS - Weight of QOS
*/
#define SEMC_BMCR0_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WQOS_SHIFT)) & SEMC_BMCR0_WQOS_MASK)
#define SEMC_BMCR0_WAGE_MASK (0xF0U)
#define SEMC_BMCR0_WAGE_SHIFT (4U)
/*! WAGE - Weight of AGE
*/
#define SEMC_BMCR0_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WAGE_SHIFT)) & SEMC_BMCR0_WAGE_MASK)
#define SEMC_BMCR0_WSH_MASK (0xFF00U)
#define SEMC_BMCR0_WSH_SHIFT (8U)
/*! WSH - Weight of Slave Hit without read/write switch
*/
#define SEMC_BMCR0_WSH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WSH_SHIFT)) & SEMC_BMCR0_WSH_MASK)
#define SEMC_BMCR0_WRWS_MASK (0xFF0000U)
#define SEMC_BMCR0_WRWS_SHIFT (16U)
/*! WRWS - Weight of slave hit with Read/Write Switch
*/
#define SEMC_BMCR0_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR0_WRWS_SHIFT)) & SEMC_BMCR0_WRWS_MASK)
/*! @} */
/*! @name BMCR1 - Bus (AXI) Master Control Register 1 */
/*! @{ */
#define SEMC_BMCR1_WQOS_MASK (0xFU)
#define SEMC_BMCR1_WQOS_SHIFT (0U)
/*! WQOS - Weight of QOS
*/
#define SEMC_BMCR1_WQOS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WQOS_SHIFT)) & SEMC_BMCR1_WQOS_MASK)
#define SEMC_BMCR1_WAGE_MASK (0xF0U)
#define SEMC_BMCR1_WAGE_SHIFT (4U)
/*! WAGE - Weight of AGE
*/
#define SEMC_BMCR1_WAGE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WAGE_SHIFT)) & SEMC_BMCR1_WAGE_MASK)
#define SEMC_BMCR1_WPH_MASK (0xFF00U)
#define SEMC_BMCR1_WPH_SHIFT (8U)
/*! WPH - Weight of Page Hit
*/
#define SEMC_BMCR1_WPH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WPH_SHIFT)) & SEMC_BMCR1_WPH_MASK)
#define SEMC_BMCR1_WRWS_MASK (0xFF0000U)
#define SEMC_BMCR1_WRWS_SHIFT (16U)
/*! WRWS - Weight of slave hit without Read/Write Switch
*/
#define SEMC_BMCR1_WRWS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WRWS_SHIFT)) & SEMC_BMCR1_WRWS_MASK)
#define SEMC_BMCR1_WBR_MASK (0xFF000000U)
#define SEMC_BMCR1_WBR_SHIFT (24U)
/*! WBR - Weight of Bank Rotation
*/
#define SEMC_BMCR1_WBR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BMCR1_WBR_SHIFT)) & SEMC_BMCR1_WBR_MASK)
/*! @} */
/*! @name BR - Base Register 0..Base Register 8 */
/*! @{ */
#define SEMC_BR_VLD_MASK (0x1U)
#define SEMC_BR_VLD_SHIFT (0U)
/*! VLD - Valid
* 0b0..The memory is invalid, can not be accessed.
* 0b1..The memory is valid, can be accessed.
*/
#define SEMC_BR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_VLD_SHIFT)) & SEMC_BR_VLD_MASK)
#define SEMC_BR_MS_MASK (0x3EU)
#define SEMC_BR_MS_SHIFT (1U)
/*! MS - Memory size
* 0b00000..4KB
* 0b00001..8KB
* 0b00010..16KB
* 0b00011..32KB
* 0b00100..64KB
* 0b00101..128KB
* 0b00110..256KB
* 0b00111..512KB
* 0b01000..1MB
* 0b01001..2MB
* 0b01010..4MB
* 0b01011..8MB
* 0b01100..16MB
* 0b01101..32MB
* 0b01110..64MB
* 0b01111..128MB
* 0b10000..256MB
* 0b10001..512MB
* 0b10010..1GB
* 0b10011..2GB
* 0b10100-0b11111..4GB
*/
#define SEMC_BR_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_MS_SHIFT)) & SEMC_BR_MS_MASK)
#define SEMC_BR_BA_MASK (0xFFFFF000U)
#define SEMC_BR_BA_SHIFT (12U)
/*! BA - Base Address
*/
#define SEMC_BR_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR_BA_SHIFT)) & SEMC_BR_BA_MASK)
/*! @} */
/* The count of SEMC_BR */
#define SEMC_BR_COUNT (9U)
/*! @name DLLCR - DLL Control Register */
/*! @{ */
#define SEMC_DLLCR_DLLEN_MASK (0x1U)
#define SEMC_DLLCR_DLLEN_SHIFT (0U)
/*! DLLEN - DLL calibration enable
* 0b0..DLL calibration is disabled.
* 0b1..DLL calibration is enabled.
*/
#define SEMC_DLLCR_DLLEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLEN_SHIFT)) & SEMC_DLLCR_DLLEN_MASK)
#define SEMC_DLLCR_DLLRESET_MASK (0x2U)
#define SEMC_DLLCR_DLLRESET_SHIFT (1U)
/*! DLLRESET - DLL Reset
* 0b0..DLL is not reset.
* 0b1..DLL is reset.
*/
#define SEMC_DLLCR_DLLRESET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_DLLRESET_SHIFT)) & SEMC_DLLCR_DLLRESET_MASK)
#define SEMC_DLLCR_SLVDLYTARGET_MASK (0x78U)
#define SEMC_DLLCR_SLVDLYTARGET_SHIFT (3U)
/*! SLVDLYTARGET - Delay Target for Slave
*/
#define SEMC_DLLCR_SLVDLYTARGET(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_SLVDLYTARGET_SHIFT)) & SEMC_DLLCR_SLVDLYTARGET_MASK)
#define SEMC_DLLCR_OVRDEN_MASK (0x100U)
#define SEMC_DLLCR_OVRDEN_SHIFT (8U)
/*! OVRDEN - Override Enable
* 0b0..The delay cell number is not overridden.
* 0b1..The delay cell number is overridden.
*/
#define SEMC_DLLCR_OVRDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDEN_SHIFT)) & SEMC_DLLCR_OVRDEN_MASK)
#define SEMC_DLLCR_OVRDVAL_MASK (0x7E00U)
#define SEMC_DLLCR_OVRDVAL_SHIFT (9U)
/*! OVRDVAL - Override Value
*/
#define SEMC_DLLCR_OVRDVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DLLCR_OVRDVAL_SHIFT)) & SEMC_DLLCR_OVRDVAL_MASK)
/*! @} */
/*! @name INTEN - Interrupt Enable Register */
/*! @{ */
#define SEMC_INTEN_IPCMDDONEEN_MASK (0x1U)
#define SEMC_INTEN_IPCMDDONEEN_SHIFT (0U)
/*! IPCMDDONEEN - IP command done interrupt enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define SEMC_INTEN_IPCMDDONEEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDDONEEN_SHIFT)) & SEMC_INTEN_IPCMDDONEEN_MASK)
#define SEMC_INTEN_IPCMDERREN_MASK (0x2U)
#define SEMC_INTEN_IPCMDERREN_SHIFT (1U)
/*! IPCMDERREN - IP command error interrupt enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define SEMC_INTEN_IPCMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_IPCMDERREN_SHIFT)) & SEMC_INTEN_IPCMDERREN_MASK)
#define SEMC_INTEN_AXICMDERREN_MASK (0x4U)
#define SEMC_INTEN_AXICMDERREN_SHIFT (2U)
/*! AXICMDERREN - AXI command error interrupt enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define SEMC_INTEN_AXICMDERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXICMDERREN_SHIFT)) & SEMC_INTEN_AXICMDERREN_MASK)
#define SEMC_INTEN_AXIBUSERREN_MASK (0x8U)
#define SEMC_INTEN_AXIBUSERREN_SHIFT (3U)
/*! AXIBUSERREN - AXI bus error interrupt enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define SEMC_INTEN_AXIBUSERREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_AXIBUSERREN_SHIFT)) & SEMC_INTEN_AXIBUSERREN_MASK)
#define SEMC_INTEN_NDPAGEENDEN_MASK (0x10U)
#define SEMC_INTEN_NDPAGEENDEN_SHIFT (4U)
/*! NDPAGEENDEN - NAND page end interrupt enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define SEMC_INTEN_NDPAGEENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDPAGEENDEN_SHIFT)) & SEMC_INTEN_NDPAGEENDEN_MASK)
#define SEMC_INTEN_NDNOPENDEN_MASK (0x20U)
#define SEMC_INTEN_NDNOPENDEN_SHIFT (5U)
/*! NDNOPENDEN - NAND no pending AXI access interrupt enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define SEMC_INTEN_NDNOPENDEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTEN_NDNOPENDEN_SHIFT)) & SEMC_INTEN_NDNOPENDEN_MASK)
/*! @} */
/*! @name INTR - Interrupt Register */
/*! @{ */
#define SEMC_INTR_IPCMDDONE_MASK (0x1U)
#define SEMC_INTR_IPCMDDONE_SHIFT (0U)
/*! IPCMDDONE - IP command normal done interrupt
* 0b0..IP command is not done.
* 0b1..IP command is done.
*/
#define SEMC_INTR_IPCMDDONE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDDONE_SHIFT)) & SEMC_INTR_IPCMDDONE_MASK)
#define SEMC_INTR_IPCMDERR_MASK (0x2U)
#define SEMC_INTR_IPCMDERR_SHIFT (1U)
/*! IPCMDERR - IP command error done interrupt
* 0b0..No IP command error.
* 0b1..IP command error occurs.
*/
#define SEMC_INTR_IPCMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_IPCMDERR_SHIFT)) & SEMC_INTR_IPCMDERR_MASK)
#define SEMC_INTR_AXICMDERR_MASK (0x4U)
#define SEMC_INTR_AXICMDERR_SHIFT (2U)
/*! AXICMDERR - AXI command error interrupt
* 0b0..No AXI command error.
* 0b1..AXI command error occurs.
*/
#define SEMC_INTR_AXICMDERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXICMDERR_SHIFT)) & SEMC_INTR_AXICMDERR_MASK)
#define SEMC_INTR_AXIBUSERR_MASK (0x8U)
#define SEMC_INTR_AXIBUSERR_SHIFT (3U)
/*! AXIBUSERR - AXI bus error interrupt
* 0b0..No AXI bus error.
* 0b1..AXI bus error occurs.
*/
#define SEMC_INTR_AXIBUSERR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_AXIBUSERR_SHIFT)) & SEMC_INTR_AXIBUSERR_MASK)
#define SEMC_INTR_NDPAGEEND_MASK (0x10U)
#define SEMC_INTR_NDPAGEEND_SHIFT (4U)
/*! NDPAGEEND - NAND page end interrupt
* 0b0..The last address of main space in the NAND is not written by AXI command.
* 0b1..The last address of main space in the NAND is written by AXI command.
*/
#define SEMC_INTR_NDPAGEEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDPAGEEND_SHIFT)) & SEMC_INTR_NDPAGEEND_MASK)
#define SEMC_INTR_NDNOPEND_MASK (0x20U)
#define SEMC_INTR_NDNOPEND_SHIFT (5U)
/*! NDNOPEND - NAND no pending AXI write transaction interrupt
* 0b0..At least one NAND AXI write transaction is pending or no NAND write transaction is sent to the queue.
* 0b1..All NAND AXI write pending transactions are finished.
*/
#define SEMC_INTR_NDNOPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_INTR_NDNOPEND_SHIFT)) & SEMC_INTR_NDNOPEND_MASK)
/*! @} */
/*! @name SDRAMCR0 - SDRAM Control Register 0 */
/*! @{ */
#define SEMC_SDRAMCR0_PS_MASK (0x3U)
#define SEMC_SDRAMCR0_PS_SHIFT (0U)
/*! PS - Port Size
* 0b00..8bit
* 0b01..16bit
* 0b10..32bit
* 0b11..Reserved
*/
#define SEMC_SDRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_PS_SHIFT)) & SEMC_SDRAMCR0_PS_MASK)
#define SEMC_SDRAMCR0_BL_MASK (0x70U)
#define SEMC_SDRAMCR0_BL_SHIFT (4U)
/*! BL - Burst Length
* 0b000..1
* 0b001..2
* 0b010..4
* 0b011..8
* 0b100..8
* 0b101..8
* 0b110..8
* 0b111..8
*/
#define SEMC_SDRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BL_SHIFT)) & SEMC_SDRAMCR0_BL_MASK)
#define SEMC_SDRAMCR0_COL8_MASK (0x80U)
#define SEMC_SDRAMCR0_COL8_SHIFT (7U)
/*! COL8 - Column 8 selection
* 0b0..Column address bit number is decided by COL field.
* 0b1..Column address bit number is 8. COL field is ignored.
*/
#define SEMC_SDRAMCR0_COL8(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL8_SHIFT)) & SEMC_SDRAMCR0_COL8_MASK)
#define SEMC_SDRAMCR0_COL_MASK (0x300U)
#define SEMC_SDRAMCR0_COL_SHIFT (8U)
/*! COL - Column address bit number
* 0b00..12
* 0b01..11
* 0b10..10
* 0b11..9
*/
#define SEMC_SDRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_COL_SHIFT)) & SEMC_SDRAMCR0_COL_MASK)
#define SEMC_SDRAMCR0_CL_MASK (0xC00U)
#define SEMC_SDRAMCR0_CL_SHIFT (10U)
/*! CL - CAS Latency
* 0b00..1
* 0b01..1
* 0b10..2
* 0b11..3
*/
#define SEMC_SDRAMCR0_CL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_CL_SHIFT)) & SEMC_SDRAMCR0_CL_MASK)
#define SEMC_SDRAMCR0_BANK2_MASK (0x4000U)
#define SEMC_SDRAMCR0_BANK2_SHIFT (14U)
/*! BANK2 - 2 Bank selection bit
* 0b0..SDRAM device has 4 banks.
* 0b1..SDRAM device has 2 banks.
*/
#define SEMC_SDRAMCR0_BANK2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR0_BANK2_SHIFT)) & SEMC_SDRAMCR0_BANK2_MASK)
/*! @} */
/*! @name SDRAMCR1 - SDRAM Control Register 1 */
/*! @{ */
#define SEMC_SDRAMCR1_PRE2ACT_MASK (0xFU)
#define SEMC_SDRAMCR1_PRE2ACT_SHIFT (0U)
/*! PRE2ACT - PRECHARGE to ACTIVE/REFRESH command wait time
*/
#define SEMC_SDRAMCR1_PRE2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_PRE2ACT_SHIFT)) & SEMC_SDRAMCR1_PRE2ACT_MASK)
#define SEMC_SDRAMCR1_ACT2RW_MASK (0xF0U)
#define SEMC_SDRAMCR1_ACT2RW_SHIFT (4U)
/*! ACT2RW - ACTIVE to READ/WRITE delay
*/
#define SEMC_SDRAMCR1_ACT2RW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2RW_SHIFT)) & SEMC_SDRAMCR1_ACT2RW_MASK)
#define SEMC_SDRAMCR1_RFRC_MASK (0x1F00U)
#define SEMC_SDRAMCR1_RFRC_SHIFT (8U)
/*! RFRC - REFRESH recovery time
*/
#define SEMC_SDRAMCR1_RFRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_RFRC_SHIFT)) & SEMC_SDRAMCR1_RFRC_MASK)
#define SEMC_SDRAMCR1_WRC_MASK (0xE000U)
#define SEMC_SDRAMCR1_WRC_SHIFT (13U)
/*! WRC - WRITE recovery time
*/
#define SEMC_SDRAMCR1_WRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_WRC_SHIFT)) & SEMC_SDRAMCR1_WRC_MASK)
#define SEMC_SDRAMCR1_CKEOFF_MASK (0xF0000U)
#define SEMC_SDRAMCR1_CKEOFF_SHIFT (16U)
/*! CKEOFF - CKE off minimum time
*/
#define SEMC_SDRAMCR1_CKEOFF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_CKEOFF_SHIFT)) & SEMC_SDRAMCR1_CKEOFF_MASK)
#define SEMC_SDRAMCR1_ACT2PRE_MASK (0xF00000U)
#define SEMC_SDRAMCR1_ACT2PRE_SHIFT (20U)
/*! ACT2PRE - ACTIVE to PRECHARGE minimum time
*/
#define SEMC_SDRAMCR1_ACT2PRE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR1_ACT2PRE_SHIFT)) & SEMC_SDRAMCR1_ACT2PRE_MASK)
/*! @} */
/*! @name SDRAMCR2 - SDRAM Control Register 2 */
/*! @{ */
#define SEMC_SDRAMCR2_SRRC_MASK (0xFFU)
#define SEMC_SDRAMCR2_SRRC_SHIFT (0U)
/*! SRRC - SELF REFRESH recovery time
*/
#define SEMC_SDRAMCR2_SRRC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_SRRC_SHIFT)) & SEMC_SDRAMCR2_SRRC_MASK)
#define SEMC_SDRAMCR2_REF2REF_MASK (0xFF00U)
#define SEMC_SDRAMCR2_REF2REF_SHIFT (8U)
/*! REF2REF - REFRESH to REFRESH delay
*/
#define SEMC_SDRAMCR2_REF2REF(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_REF2REF_SHIFT)) & SEMC_SDRAMCR2_REF2REF_MASK)
#define SEMC_SDRAMCR2_ACT2ACT_MASK (0xFF0000U)
#define SEMC_SDRAMCR2_ACT2ACT_SHIFT (16U)
/*! ACT2ACT - ACTIVE to ACTIVE delay
*/
#define SEMC_SDRAMCR2_ACT2ACT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ACT2ACT_SHIFT)) & SEMC_SDRAMCR2_ACT2ACT_MASK)
#define SEMC_SDRAMCR2_ITO_MASK (0xFF000000U)
#define SEMC_SDRAMCR2_ITO_SHIFT (24U)
/*! ITO - SDRAM idle timeout
* 0b00000000..IDLE timeout period is 256*Prescale period.
* 0b00000001-0b11111111..IDLE timeout period is ITO*Prescale period.
*/
#define SEMC_SDRAMCR2_ITO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR2_ITO_SHIFT)) & SEMC_SDRAMCR2_ITO_MASK)
/*! @} */
/*! @name SDRAMCR3 - SDRAM Control Register 3 */
/*! @{ */
#define SEMC_SDRAMCR3_REN_MASK (0x1U)
#define SEMC_SDRAMCR3_REN_SHIFT (0U)
/*! REN - Refresh enable
* 0b0..The SEMC does not send AUTO REFRESH command automatically
* 0b1..The SEMC sends AUTO REFRESH command automatically
*/
#define SEMC_SDRAMCR3_REN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REN_SHIFT)) & SEMC_SDRAMCR3_REN_MASK)
#define SEMC_SDRAMCR3_REBL_MASK (0xEU)
#define SEMC_SDRAMCR3_REBL_SHIFT (1U)
/*! REBL - Refresh burst length
* 0b000..1
* 0b001..2
* 0b010..3
* 0b011..4
* 0b100..5
* 0b101..6
* 0b110..7
* 0b111..8
*/
#define SEMC_SDRAMCR3_REBL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_REBL_SHIFT)) & SEMC_SDRAMCR3_REBL_MASK)
#define SEMC_SDRAMCR3_PRESCALE_MASK (0xFF00U)
#define SEMC_SDRAMCR3_PRESCALE_SHIFT (8U)
/*! PRESCALE - Prescaler period
* 0b00000000..(256*16+1) clock cycles
* 0b00000001-0b11111111..(PRESCALE*16+1) clock cycles
*/
#define SEMC_SDRAMCR3_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_PRESCALE_SHIFT)) & SEMC_SDRAMCR3_PRESCALE_MASK)
#define SEMC_SDRAMCR3_RT_MASK (0xFF0000U)
#define SEMC_SDRAMCR3_RT_SHIFT (16U)
/*! RT - Refresh timer period
* 0b00000000..(256+1)*(Prescaler period)
* 0b00000001-0b11111111..(RT+1)*(Prescaler period)
*/
#define SEMC_SDRAMCR3_RT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_RT_SHIFT)) & SEMC_SDRAMCR3_RT_MASK)
#define SEMC_SDRAMCR3_UT_MASK (0xFF000000U)
#define SEMC_SDRAMCR3_UT_SHIFT (24U)
/*! UT - Urgent refresh threshold
* 0b00000000..256*(Prescaler period)
* 0b00000001-0b11111111..UT*(Prescaler period)
*/
#define SEMC_SDRAMCR3_UT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SDRAMCR3_UT_SHIFT)) & SEMC_SDRAMCR3_UT_MASK)
/*! @} */
/*! @name NANDCR0 - NAND Control Register 0 */
/*! @{ */
#define SEMC_NANDCR0_PS_MASK (0x1U)
#define SEMC_NANDCR0_PS_SHIFT (0U)
/*! PS - Port Size
* 0b0..8bit
* 0b1..16bit
*/
#define SEMC_NANDCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_PS_SHIFT)) & SEMC_NANDCR0_PS_MASK)
#define SEMC_NANDCR0_SYNCEN_MASK (0x2U)
#define SEMC_NANDCR0_SYNCEN_SHIFT (1U)
/*! SYNCEN - Synchronous Mode Enable
* 0b0..Asynchronous mode is enabled.
* 0b1..Synchronous mode is enabled.
*/
#define SEMC_NANDCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_SYNCEN_SHIFT)) & SEMC_NANDCR0_SYNCEN_MASK)
#define SEMC_NANDCR0_BL_MASK (0x70U)
#define SEMC_NANDCR0_BL_SHIFT (4U)
/*! BL - Burst Length
* 0b000..1
* 0b001..2
* 0b010..4
* 0b011..8
* 0b100..16
* 0b101..32
* 0b110..64
* 0b111..64
*/
#define SEMC_NANDCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_BL_SHIFT)) & SEMC_NANDCR0_BL_MASK)
#define SEMC_NANDCR0_EDO_MASK (0x80U)
#define SEMC_NANDCR0_EDO_SHIFT (7U)
/*! EDO - EDO mode enabled
* 0b0..EDO mode disabled
* 0b1..EDO mode enabled
*/
#define SEMC_NANDCR0_EDO(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_EDO_SHIFT)) & SEMC_NANDCR0_EDO_MASK)
#define SEMC_NANDCR0_COL_MASK (0x700U)
#define SEMC_NANDCR0_COL_SHIFT (8U)
/*! COL - Column address bit number
* 0b000..16
* 0b001..15
* 0b010..14
* 0b011..13
* 0b100..12
* 0b101..11
* 0b110..10
* 0b111..9
*/
#define SEMC_NANDCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR0_COL_SHIFT)) & SEMC_NANDCR0_COL_MASK)
/*! @} */
/*! @name NANDCR1 - NAND Control Register 1 */
/*! @{ */
#define SEMC_NANDCR1_CES_MASK (0xFU)
#define SEMC_NANDCR1_CES_SHIFT (0U)
/*! CES - CE# setup time
*/
#define SEMC_NANDCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CES_SHIFT)) & SEMC_NANDCR1_CES_MASK)
#define SEMC_NANDCR1_CEH_MASK (0xF0U)
#define SEMC_NANDCR1_CEH_SHIFT (4U)
/*! CEH - CE# hold time
*/
#define SEMC_NANDCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEH_SHIFT)) & SEMC_NANDCR1_CEH_MASK)
#define SEMC_NANDCR1_WEL_MASK (0xF00U)
#define SEMC_NANDCR1_WEL_SHIFT (8U)
/*! WEL - WE# low time
*/
#define SEMC_NANDCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEL_SHIFT)) & SEMC_NANDCR1_WEL_MASK)
#define SEMC_NANDCR1_WEH_MASK (0xF000U)
#define SEMC_NANDCR1_WEH_SHIFT (12U)
/*! WEH - WE# high time
*/
#define SEMC_NANDCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_WEH_SHIFT)) & SEMC_NANDCR1_WEH_MASK)
#define SEMC_NANDCR1_REL_MASK (0xF0000U)
#define SEMC_NANDCR1_REL_SHIFT (16U)
/*! REL - RE# low time
*/
#define SEMC_NANDCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REL_SHIFT)) & SEMC_NANDCR1_REL_MASK)
#define SEMC_NANDCR1_REH_MASK (0xF00000U)
#define SEMC_NANDCR1_REH_SHIFT (20U)
/*! REH - RE# high time
*/
#define SEMC_NANDCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_REH_SHIFT)) & SEMC_NANDCR1_REH_MASK)
#define SEMC_NANDCR1_TA_MASK (0xF000000U)
#define SEMC_NANDCR1_TA_SHIFT (24U)
/*! TA - Turnaround time
*/
#define SEMC_NANDCR1_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_TA_SHIFT)) & SEMC_NANDCR1_TA_MASK)
#define SEMC_NANDCR1_CEITV_MASK (0xF0000000U)
#define SEMC_NANDCR1_CEITV_SHIFT (28U)
/*! CEITV - CE# interval time
*/
#define SEMC_NANDCR1_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR1_CEITV_SHIFT)) & SEMC_NANDCR1_CEITV_MASK)
/*! @} */
/*! @name NANDCR2 - NAND Control Register 2 */
/*! @{ */
#define SEMC_NANDCR2_TWHR_MASK (0x3FU)
#define SEMC_NANDCR2_TWHR_SHIFT (0U)
/*! TWHR - WE# high to RE# low time
*/
#define SEMC_NANDCR2_TWHR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWHR_SHIFT)) & SEMC_NANDCR2_TWHR_MASK)
#define SEMC_NANDCR2_TRHW_MASK (0xFC0U)
#define SEMC_NANDCR2_TRHW_SHIFT (6U)
/*! TRHW - RE# high to WE# low time
*/
#define SEMC_NANDCR2_TRHW(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRHW_SHIFT)) & SEMC_NANDCR2_TRHW_MASK)
#define SEMC_NANDCR2_TADL_MASK (0x3F000U)
#define SEMC_NANDCR2_TADL_SHIFT (12U)
/*! TADL - Address cycle to data loading time
*/
#define SEMC_NANDCR2_TADL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TADL_SHIFT)) & SEMC_NANDCR2_TADL_MASK)
#define SEMC_NANDCR2_TRR_MASK (0xFC0000U)
#define SEMC_NANDCR2_TRR_SHIFT (18U)
/*! TRR - Ready to RE# low time
*/
#define SEMC_NANDCR2_TRR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TRR_SHIFT)) & SEMC_NANDCR2_TRR_MASK)
#define SEMC_NANDCR2_TWB_MASK (0x3F000000U)
#define SEMC_NANDCR2_TWB_SHIFT (24U)
/*! TWB - WE# high to busy time
*/
#define SEMC_NANDCR2_TWB(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR2_TWB_SHIFT)) & SEMC_NANDCR2_TWB_MASK)
/*! @} */
/*! @name NANDCR3 - NAND Control Register 3 */
/*! @{ */
#define SEMC_NANDCR3_NDOPT1_MASK (0x1U)
#define SEMC_NANDCR3_NDOPT1_SHIFT (0U)
/*! NDOPT1 - NAND option bit 1
*/
#define SEMC_NANDCR3_NDOPT1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT1_SHIFT)) & SEMC_NANDCR3_NDOPT1_MASK)
#define SEMC_NANDCR3_NDOPT2_MASK (0x2U)
#define SEMC_NANDCR3_NDOPT2_SHIFT (1U)
/*! NDOPT2 - NAND option bit 2
*/
#define SEMC_NANDCR3_NDOPT2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT2_SHIFT)) & SEMC_NANDCR3_NDOPT2_MASK)
#define SEMC_NANDCR3_NDOPT3_MASK (0x4U)
#define SEMC_NANDCR3_NDOPT3_SHIFT (2U)
/*! NDOPT3 - NAND option bit 3
*/
#define SEMC_NANDCR3_NDOPT3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_NDOPT3_SHIFT)) & SEMC_NANDCR3_NDOPT3_MASK)
#define SEMC_NANDCR3_CLE_MASK (0x8U)
#define SEMC_NANDCR3_CLE_SHIFT (3U)
/*! CLE - NAND CLE Option
*/
#define SEMC_NANDCR3_CLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_CLE_SHIFT)) & SEMC_NANDCR3_CLE_MASK)
#define SEMC_NANDCR3_RDS_MASK (0xF0000U)
#define SEMC_NANDCR3_RDS_SHIFT (16U)
/*! RDS - Read Data Setup time
*/
#define SEMC_NANDCR3_RDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDS_SHIFT)) & SEMC_NANDCR3_RDS_MASK)
#define SEMC_NANDCR3_RDH_MASK (0xF00000U)
#define SEMC_NANDCR3_RDH_SHIFT (20U)
/*! RDH - Read Data Hold time
*/
#define SEMC_NANDCR3_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_RDH_SHIFT)) & SEMC_NANDCR3_RDH_MASK)
#define SEMC_NANDCR3_WDS_MASK (0xF000000U)
#define SEMC_NANDCR3_WDS_SHIFT (24U)
/*! WDS - Write Data Setup time
*/
#define SEMC_NANDCR3_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDS_SHIFT)) & SEMC_NANDCR3_WDS_MASK)
#define SEMC_NANDCR3_WDH_MASK (0xF0000000U)
#define SEMC_NANDCR3_WDH_SHIFT (28U)
/*! WDH - Write Data Hold time
*/
#define SEMC_NANDCR3_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NANDCR3_WDH_SHIFT)) & SEMC_NANDCR3_WDH_MASK)
/*! @} */
/*! @name NORCR0 - NOR Control Register 0 */
/*! @{ */
#define SEMC_NORCR0_PS_MASK (0x1U)
#define SEMC_NORCR0_PS_SHIFT (0U)
/*! PS - Port Size
* 0b0..8bit
* 0b1..16bit
*/
#define SEMC_NORCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_PS_SHIFT)) & SEMC_NORCR0_PS_MASK)
#define SEMC_NORCR0_SYNCEN_MASK (0x2U)
#define SEMC_NORCR0_SYNCEN_SHIFT (1U)
/*! SYNCEN - Synchronous Mode Enable
* 0b0..Asynchronous mode is enabled.
* 0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
*/
#define SEMC_NORCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_SYNCEN_SHIFT)) & SEMC_NORCR0_SYNCEN_MASK)
#define SEMC_NORCR0_BL_MASK (0x70U)
#define SEMC_NORCR0_BL_SHIFT (4U)
/*! BL - Burst Length
* 0b000..1
* 0b001..2
* 0b010..4
* 0b011..8
* 0b100..16
* 0b101..32
* 0b110..64
* 0b111..64
*/
#define SEMC_NORCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_BL_SHIFT)) & SEMC_NORCR0_BL_MASK)
#define SEMC_NORCR0_AM_MASK (0x300U)
#define SEMC_NORCR0_AM_SHIFT (8U)
/*! AM - Address Mode
* 0b00..Address/Data MUX mode (ADMUX)
* 0b01..Advanced Address/Data MUX mode (AADM)
* 0b10..Address/Data non-MUX mode (Non-ADMUX)
* 0b11..Address/Data non-MUX mode (Non-ADMUX)
*/
#define SEMC_NORCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_AM_SHIFT)) & SEMC_NORCR0_AM_MASK)
#define SEMC_NORCR0_ADVP_MASK (0x400U)
#define SEMC_NORCR0_ADVP_SHIFT (10U)
/*! ADVP - ADV# Polarity
* 0b0..ADV# is active low.
* 0b1..ADV# is active high.
*/
#define SEMC_NORCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVP_SHIFT)) & SEMC_NORCR0_ADVP_MASK)
#define SEMC_NORCR0_ADVH_MASK (0x800U)
#define SEMC_NORCR0_ADVH_SHIFT (11U)
/*! ADVH - ADV# level control during address hold state
* 0b0..ADV# is high during address hold state.
* 0b1..ADV# is low during address hold state.
*/
#define SEMC_NORCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_ADVH_SHIFT)) & SEMC_NORCR0_ADVH_MASK)
#define SEMC_NORCR0_COL_MASK (0xF000U)
#define SEMC_NORCR0_COL_SHIFT (12U)
/*! COL - Column Address bit width
* 0b0000..12 Bits
* 0b0001..11 Bits
* 0b0010..10 Bits
* 0b0011..9 Bits
* 0b0100..8 Bits
* 0b0101..7 Bits
* 0b0110..6 Bits
* 0b0111..5 Bits
* 0b1000..4 Bits
* 0b1001..3 Bits
* 0b1010..2 Bits
* 0b1011..12 Bits
* 0b1100..12 Bits
* 0b1101..12 Bits
* 0b1110..12 Bits
* 0b1111..12 Bits
*/
#define SEMC_NORCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR0_COL_SHIFT)) & SEMC_NORCR0_COL_MASK)
/*! @} */
/*! @name NORCR1 - NOR Control Register 1 */
/*! @{ */
#define SEMC_NORCR1_CES_MASK (0xFU)
#define SEMC_NORCR1_CES_SHIFT (0U)
/*! CES - CE setup time
*/
#define SEMC_NORCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CES_SHIFT)) & SEMC_NORCR1_CES_MASK)
#define SEMC_NORCR1_CEH_MASK (0xF0U)
#define SEMC_NORCR1_CEH_SHIFT (4U)
/*! CEH - CE hold time
*/
#define SEMC_NORCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_CEH_SHIFT)) & SEMC_NORCR1_CEH_MASK)
#define SEMC_NORCR1_AS_MASK (0xF00U)
#define SEMC_NORCR1_AS_SHIFT (8U)
/*! AS - Address setup time
*/
#define SEMC_NORCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AS_SHIFT)) & SEMC_NORCR1_AS_MASK)
#define SEMC_NORCR1_AH_MASK (0xF000U)
#define SEMC_NORCR1_AH_SHIFT (12U)
/*! AH - Address hold time
*/
#define SEMC_NORCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_AH_SHIFT)) & SEMC_NORCR1_AH_MASK)
#define SEMC_NORCR1_WEL_MASK (0xF0000U)
#define SEMC_NORCR1_WEL_SHIFT (16U)
/*! WEL - WE low time
*/
#define SEMC_NORCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEL_SHIFT)) & SEMC_NORCR1_WEL_MASK)
#define SEMC_NORCR1_WEH_MASK (0xF00000U)
#define SEMC_NORCR1_WEH_SHIFT (20U)
/*! WEH - WE high time
*/
#define SEMC_NORCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_WEH_SHIFT)) & SEMC_NORCR1_WEH_MASK)
#define SEMC_NORCR1_REL_MASK (0xF000000U)
#define SEMC_NORCR1_REL_SHIFT (24U)
/*! REL - RE low time
*/
#define SEMC_NORCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REL_SHIFT)) & SEMC_NORCR1_REL_MASK)
#define SEMC_NORCR1_REH_MASK (0xF0000000U)
#define SEMC_NORCR1_REH_SHIFT (28U)
/*! REH - RE high time
*/
#define SEMC_NORCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR1_REH_SHIFT)) & SEMC_NORCR1_REH_MASK)
/*! @} */
/*! @name NORCR2 - NOR Control Register 2 */
/*! @{ */
#define SEMC_NORCR2_TA_MASK (0xF00U)
#define SEMC_NORCR2_TA_SHIFT (8U)
/*! TA - Turnaround time
*/
#define SEMC_NORCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_TA_SHIFT)) & SEMC_NORCR2_TA_MASK)
#define SEMC_NORCR2_AWDH_MASK (0xF000U)
#define SEMC_NORCR2_AWDH_SHIFT (12U)
/*! AWDH - Address to write data hold time
*/
#define SEMC_NORCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_AWDH_SHIFT)) & SEMC_NORCR2_AWDH_MASK)
#define SEMC_NORCR2_LC_MASK (0xF0000U)
#define SEMC_NORCR2_LC_SHIFT (16U)
/*! LC - Latency count
*/
#define SEMC_NORCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_LC_SHIFT)) & SEMC_NORCR2_LC_MASK)
#define SEMC_NORCR2_RD_MASK (0xF00000U)
#define SEMC_NORCR2_RD_SHIFT (20U)
/*! RD - Read time
*/
#define SEMC_NORCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RD_SHIFT)) & SEMC_NORCR2_RD_MASK)
#define SEMC_NORCR2_CEITV_MASK (0xF000000U)
#define SEMC_NORCR2_CEITV_SHIFT (24U)
/*! CEITV - CE# interval time
*/
#define SEMC_NORCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_CEITV_SHIFT)) & SEMC_NORCR2_CEITV_MASK)
#define SEMC_NORCR2_RDH_MASK (0xF0000000U)
#define SEMC_NORCR2_RDH_SHIFT (28U)
/*! RDH - Read hold time
*/
#define SEMC_NORCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR2_RDH_SHIFT)) & SEMC_NORCR2_RDH_MASK)
/*! @} */
/*! @name NORCR3 - NOR Control Register 3 */
/*! @{ */
#define SEMC_NORCR3_ASSR_MASK (0xFU)
#define SEMC_NORCR3_ASSR_SHIFT (0U)
/*! ASSR - Address setup time for SYNC read
*/
#define SEMC_NORCR3_ASSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_ASSR_SHIFT)) & SEMC_NORCR3_ASSR_MASK)
#define SEMC_NORCR3_AHSR_MASK (0xF0U)
#define SEMC_NORCR3_AHSR_SHIFT (4U)
/*! AHSR - Address hold time for SYNC read
*/
#define SEMC_NORCR3_AHSR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_NORCR3_AHSR_SHIFT)) & SEMC_NORCR3_AHSR_MASK)
/*! @} */
/*! @name SRAMCR0 - SRAM Control Register 0 */
/*! @{ */
#define SEMC_SRAMCR0_PS_MASK (0x1U)
#define SEMC_SRAMCR0_PS_SHIFT (0U)
/*! PS - Port Size
* 0b0..8bit
* 0b1..16bit
*/
#define SEMC_SRAMCR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_PS_SHIFT)) & SEMC_SRAMCR0_PS_MASK)
#define SEMC_SRAMCR0_SYNCEN_MASK (0x2U)
#define SEMC_SRAMCR0_SYNCEN_SHIFT (1U)
/*! SYNCEN - Synchronous Mode Enable
* 0b0..Asynchronous mode is enabled.
* 0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
*/
#define SEMC_SRAMCR0_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_SYNCEN_SHIFT)) & SEMC_SRAMCR0_SYNCEN_MASK)
#define SEMC_SRAMCR0_WAITEN_MASK (0x4U)
#define SEMC_SRAMCR0_WAITEN_SHIFT (2U)
/*! WAITEN - Wait Enable
* 0b0..The SEMC does not monitor wait pin.
* 0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
*/
#define SEMC_SRAMCR0_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITEN_SHIFT)) & SEMC_SRAMCR0_WAITEN_MASK)
#define SEMC_SRAMCR0_WAITSP_MASK (0x8U)
#define SEMC_SRAMCR0_WAITSP_SHIFT (3U)
/*! WAITSP - Wait Sample
* 0b0..Wait pin is directly used by the SEMC.
* 0b1..Wait pin is sampled by internal clock before it is used.
*/
#define SEMC_SRAMCR0_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_WAITSP_SHIFT)) & SEMC_SRAMCR0_WAITSP_MASK)
#define SEMC_SRAMCR0_BL_MASK (0x70U)
#define SEMC_SRAMCR0_BL_SHIFT (4U)
/*! BL - Burst Length
* 0b000..1
* 0b001..2
* 0b010..4
* 0b011..8
* 0b100..16
* 0b101..32
* 0b110..64
* 0b111..64
*/
#define SEMC_SRAMCR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_BL_SHIFT)) & SEMC_SRAMCR0_BL_MASK)
#define SEMC_SRAMCR0_AM_MASK (0x300U)
#define SEMC_SRAMCR0_AM_SHIFT (8U)
/*! AM - Address Mode
* 0b00..Address/Data MUX mode (ADMUX)
* 0b01..Advanced Address/Data MUX mode (AADM)
* 0b10..Address/Data non-MUX mode (Non-ADMUX)
* 0b11..Address/Data non-MUX mode (Non-ADMUX)
*/
#define SEMC_SRAMCR0_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_AM_SHIFT)) & SEMC_SRAMCR0_AM_MASK)
#define SEMC_SRAMCR0_ADVP_MASK (0x400U)
#define SEMC_SRAMCR0_ADVP_SHIFT (10U)
/*! ADVP - ADV# polarity
* 0b0..ADV# is active low.
* 0b1..ADV# is active high.
*/
#define SEMC_SRAMCR0_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVP_SHIFT)) & SEMC_SRAMCR0_ADVP_MASK)
#define SEMC_SRAMCR0_ADVH_MASK (0x800U)
#define SEMC_SRAMCR0_ADVH_SHIFT (11U)
/*! ADVH - ADV# level control during address hold state
* 0b0..ADV# is high during address hold state.
* 0b1..ADV# is low during address hold state.
*/
#define SEMC_SRAMCR0_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_ADVH_SHIFT)) & SEMC_SRAMCR0_ADVH_MASK)
#define SEMC_SRAMCR0_COL_MASK (0xF000U)
#define SEMC_SRAMCR0_COL_SHIFT (12U)
/*! COL - Column Address bit width
* 0b0000..12 Bits
* 0b0001..11 Bits
* 0b0010..10 Bits
* 0b0011..9 Bits
* 0b0100..8 Bits
* 0b0101..7 Bits
* 0b0110..6 Bits
* 0b0111..5 Bits
* 0b1000..4 Bits
* 0b1001..3 Bits
* 0b1010..2 Bits
* 0b1011..12 Bits
* 0b1100..12 Bits
* 0b1101..12 Bits
* 0b1110..12 Bits
* 0b1111..12 Bits
*/
#define SEMC_SRAMCR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR0_COL_SHIFT)) & SEMC_SRAMCR0_COL_MASK)
/*! @} */
/*! @name SRAMCR1 - SRAM Control Register 1 */
/*! @{ */
#define SEMC_SRAMCR1_CES_MASK (0xFU)
#define SEMC_SRAMCR1_CES_SHIFT (0U)
/*! CES - CE setup time
*/
#define SEMC_SRAMCR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CES_SHIFT)) & SEMC_SRAMCR1_CES_MASK)
#define SEMC_SRAMCR1_CEH_MASK (0xF0U)
#define SEMC_SRAMCR1_CEH_SHIFT (4U)
/*! CEH - CE hold time
*/
#define SEMC_SRAMCR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_CEH_SHIFT)) & SEMC_SRAMCR1_CEH_MASK)
#define SEMC_SRAMCR1_AS_MASK (0xF00U)
#define SEMC_SRAMCR1_AS_SHIFT (8U)
/*! AS - Address setup time
*/
#define SEMC_SRAMCR1_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AS_SHIFT)) & SEMC_SRAMCR1_AS_MASK)
#define SEMC_SRAMCR1_AH_MASK (0xF000U)
#define SEMC_SRAMCR1_AH_SHIFT (12U)
/*! AH - Address hold time
*/
#define SEMC_SRAMCR1_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_AH_SHIFT)) & SEMC_SRAMCR1_AH_MASK)
#define SEMC_SRAMCR1_WEL_MASK (0xF0000U)
#define SEMC_SRAMCR1_WEL_SHIFT (16U)
/*! WEL - WE low time
*/
#define SEMC_SRAMCR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEL_SHIFT)) & SEMC_SRAMCR1_WEL_MASK)
#define SEMC_SRAMCR1_WEH_MASK (0xF00000U)
#define SEMC_SRAMCR1_WEH_SHIFT (20U)
/*! WEH - WE high time
*/
#define SEMC_SRAMCR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_WEH_SHIFT)) & SEMC_SRAMCR1_WEH_MASK)
#define SEMC_SRAMCR1_REL_MASK (0xF000000U)
#define SEMC_SRAMCR1_REL_SHIFT (24U)
/*! REL - RE low time
*/
#define SEMC_SRAMCR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REL_SHIFT)) & SEMC_SRAMCR1_REL_MASK)
#define SEMC_SRAMCR1_REH_MASK (0xF0000000U)
#define SEMC_SRAMCR1_REH_SHIFT (28U)
/*! REH - RE high time
*/
#define SEMC_SRAMCR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR1_REH_SHIFT)) & SEMC_SRAMCR1_REH_MASK)
/*! @} */
/*! @name SRAMCR2 - SRAM Control Register 2 */
/*! @{ */
#define SEMC_SRAMCR2_WDS_MASK (0xFU)
#define SEMC_SRAMCR2_WDS_SHIFT (0U)
/*! WDS - Write Data setup time
*/
#define SEMC_SRAMCR2_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDS_SHIFT)) & SEMC_SRAMCR2_WDS_MASK)
#define SEMC_SRAMCR2_WDH_MASK (0xF0U)
#define SEMC_SRAMCR2_WDH_SHIFT (4U)
/*! WDH - Write Data hold time
*/
#define SEMC_SRAMCR2_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_WDH_SHIFT)) & SEMC_SRAMCR2_WDH_MASK)
#define SEMC_SRAMCR2_TA_MASK (0xF00U)
#define SEMC_SRAMCR2_TA_SHIFT (8U)
/*! TA - Turnaround time
*/
#define SEMC_SRAMCR2_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_TA_SHIFT)) & SEMC_SRAMCR2_TA_MASK)
#define SEMC_SRAMCR2_AWDH_MASK (0xF000U)
#define SEMC_SRAMCR2_AWDH_SHIFT (12U)
/*! AWDH - Address to write data hold time
*/
#define SEMC_SRAMCR2_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_AWDH_SHIFT)) & SEMC_SRAMCR2_AWDH_MASK)
#define SEMC_SRAMCR2_LC_MASK (0xF0000U)
#define SEMC_SRAMCR2_LC_SHIFT (16U)
/*! LC - Latency count
*/
#define SEMC_SRAMCR2_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_LC_SHIFT)) & SEMC_SRAMCR2_LC_MASK)
#define SEMC_SRAMCR2_RD_MASK (0xF00000U)
#define SEMC_SRAMCR2_RD_SHIFT (20U)
/*! RD - Read time
*/
#define SEMC_SRAMCR2_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RD_SHIFT)) & SEMC_SRAMCR2_RD_MASK)
#define SEMC_SRAMCR2_CEITV_MASK (0xF000000U)
#define SEMC_SRAMCR2_CEITV_SHIFT (24U)
/*! CEITV - CE# interval time
*/
#define SEMC_SRAMCR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_CEITV_SHIFT)) & SEMC_SRAMCR2_CEITV_MASK)
#define SEMC_SRAMCR2_RDH_MASK (0xF0000000U)
#define SEMC_SRAMCR2_RDH_SHIFT (28U)
/*! RDH - Read hold time
*/
#define SEMC_SRAMCR2_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR2_RDH_SHIFT)) & SEMC_SRAMCR2_RDH_MASK)
/*! @} */
/*! @name DBICR0 - DBI-B Control Register 0 */
/*! @{ */
#define SEMC_DBICR0_PS_MASK (0x1U)
#define SEMC_DBICR0_PS_SHIFT (0U)
/*! PS - Port Size
* 0b0..8bit
* 0b1..16bit
*/
#define SEMC_DBICR0_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_PS_SHIFT)) & SEMC_DBICR0_PS_MASK)
#define SEMC_DBICR0_BL_MASK (0x70U)
#define SEMC_DBICR0_BL_SHIFT (4U)
/*! BL - Burst Length
* 0b000..1
* 0b001..2
* 0b010..4
* 0b011..8
* 0b100..16
* 0b101..32
* 0b110..64
* 0b111..64
*/
#define SEMC_DBICR0_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_BL_SHIFT)) & SEMC_DBICR0_BL_MASK)
#define SEMC_DBICR0_COL_MASK (0xF000U)
#define SEMC_DBICR0_COL_SHIFT (12U)
/*! COL - Column Address bit width
* 0b0000..12 Bits
* 0b0001..11 Bits
* 0b0010..10 Bits
* 0b0011..9 Bits
* 0b0100..8 Bits
* 0b0101..7 Bits
* 0b0110..6 Bits
* 0b0111..5 Bits
* 0b1000..4 Bits
* 0b1001..3 Bits
* 0b1010..2 Bits
* 0b1011..12 Bits
* 0b1100..12 Bits
* 0b1101..12 Bits
* 0b1110..12 Bits
* 0b1111..12 Bits
*/
#define SEMC_DBICR0_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR0_COL_SHIFT)) & SEMC_DBICR0_COL_MASK)
/*! @} */
/*! @name DBICR1 - DBI-B Control Register 1 */
/*! @{ */
#define SEMC_DBICR1_CES_MASK (0xFU)
#define SEMC_DBICR1_CES_SHIFT (0U)
/*! CES - CSX Setup Time
*/
#define SEMC_DBICR1_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CES_SHIFT)) & SEMC_DBICR1_CES_MASK)
#define SEMC_DBICR1_CEH_MASK (0xF0U)
#define SEMC_DBICR1_CEH_SHIFT (4U)
/*! CEH - CSX Hold Time
*/
#define SEMC_DBICR1_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_CEH_SHIFT)) & SEMC_DBICR1_CEH_MASK)
#define SEMC_DBICR1_WEL_MASK (0xF00U)
#define SEMC_DBICR1_WEL_SHIFT (8U)
/*! WEL - WRX Low Time
*/
#define SEMC_DBICR1_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEL_SHIFT)) & SEMC_DBICR1_WEL_MASK)
#define SEMC_DBICR1_WEH_MASK (0xF000U)
#define SEMC_DBICR1_WEH_SHIFT (12U)
/*! WEH - WRX High Time
*/
#define SEMC_DBICR1_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_WEH_SHIFT)) & SEMC_DBICR1_WEH_MASK)
#define SEMC_DBICR1_REL_MASK (0x7F0000U)
#define SEMC_DBICR1_REL_SHIFT (16U)
/*! REL - RDX Low Time
*/
#define SEMC_DBICR1_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REL_SHIFT)) & SEMC_DBICR1_REL_MASK)
#define SEMC_DBICR1_REH_MASK (0x7F000000U)
#define SEMC_DBICR1_REH_SHIFT (24U)
/*! REH - RDX High Time
*/
#define SEMC_DBICR1_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR1_REH_SHIFT)) & SEMC_DBICR1_REH_MASK)
/*! @} */
/*! @name DBICR2 - DBI-B Control Register 2 */
/*! @{ */
#define SEMC_DBICR2_CEITV_MASK (0xFU)
#define SEMC_DBICR2_CEITV_SHIFT (0U)
/*! CEITV - CSX interval time
*/
#define SEMC_DBICR2_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DBICR2_CEITV_SHIFT)) & SEMC_DBICR2_CEITV_MASK)
/*! @} */
/*! @name IPCR0 - IP Command Control Register 0 */
/*! @{ */
#define SEMC_IPCR0_SA_MASK (0xFFFFFFFFU)
#define SEMC_IPCR0_SA_SHIFT (0U)
/*! SA - Slave address
*/
#define SEMC_IPCR0_SA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR0_SA_SHIFT)) & SEMC_IPCR0_SA_MASK)
/*! @} */
/*! @name IPCR1 - IP Command Control Register 1 */
/*! @{ */
#define SEMC_IPCR1_DATSZ_MASK (0x7U)
#define SEMC_IPCR1_DATSZ_SHIFT (0U)
/*! DATSZ - Data Size in Byte
* 0b000..4
* 0b001..1
* 0b010..2
* 0b011..3
* 0b100..4
* 0b101..4
* 0b110..4
* 0b111..4
*/
#define SEMC_IPCR1_DATSZ(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_DATSZ_SHIFT)) & SEMC_IPCR1_DATSZ_MASK)
#define SEMC_IPCR1_NAND_EXT_ADDR_MASK (0xFF00U)
#define SEMC_IPCR1_NAND_EXT_ADDR_SHIFT (8U)
/*! NAND_EXT_ADDR - NAND Extended Address
*/
#define SEMC_IPCR1_NAND_EXT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR1_NAND_EXT_ADDR_SHIFT)) & SEMC_IPCR1_NAND_EXT_ADDR_MASK)
/*! @} */
/*! @name IPCR2 - IP Command Control Register 2 */
/*! @{ */
#define SEMC_IPCR2_BM0_MASK (0x1U)
#define SEMC_IPCR2_BM0_SHIFT (0U)
/*! BM0 - Byte Mask for Byte 0 (IPTXDAT bit 7:0)
* 0b0..Byte is unmasked
* 0b1..Byte is masked
*/
#define SEMC_IPCR2_BM0(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM0_SHIFT)) & SEMC_IPCR2_BM0_MASK)
#define SEMC_IPCR2_BM1_MASK (0x2U)
#define SEMC_IPCR2_BM1_SHIFT (1U)
/*! BM1 - Byte Mask for Byte 1 (IPTXDAT bit 15:8)
* 0b0..Byte is unmasked
* 0b1..Byte is masked
*/
#define SEMC_IPCR2_BM1(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM1_SHIFT)) & SEMC_IPCR2_BM1_MASK)
#define SEMC_IPCR2_BM2_MASK (0x4U)
#define SEMC_IPCR2_BM2_SHIFT (2U)
/*! BM2 - Byte Mask for Byte 2 (IPTXDAT bit 23:16)
* 0b0..Byte is unmasked
* 0b1..Byte is masked
*/
#define SEMC_IPCR2_BM2(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM2_SHIFT)) & SEMC_IPCR2_BM2_MASK)
#define SEMC_IPCR2_BM3_MASK (0x8U)
#define SEMC_IPCR2_BM3_SHIFT (3U)
/*! BM3 - Byte Mask for Byte 3 (IPTXDAT bit 31:24)
* 0b0..Byte is unmasked
* 0b1..Byte is masked
*/
#define SEMC_IPCR2_BM3(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCR2_BM3_SHIFT)) & SEMC_IPCR2_BM3_MASK)
/*! @} */
/*! @name IPCMD - IP Command Register */
/*! @{ */
#define SEMC_IPCMD_CMD_MASK (0xFFFFU)
#define SEMC_IPCMD_CMD_SHIFT (0U)
#define SEMC_IPCMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_CMD_SHIFT)) & SEMC_IPCMD_CMD_MASK)
#define SEMC_IPCMD_KEY_MASK (0xFFFF0000U)
#define SEMC_IPCMD_KEY_SHIFT (16U)
#define SEMC_IPCMD_KEY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPCMD_KEY_SHIFT)) & SEMC_IPCMD_KEY_MASK)
/*! @} */
/*! @name IPTXDAT - TX DATA Register */
/*! @{ */
#define SEMC_IPTXDAT_DAT_MASK (0xFFFFFFFFU)
#define SEMC_IPTXDAT_DAT_SHIFT (0U)
#define SEMC_IPTXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPTXDAT_DAT_SHIFT)) & SEMC_IPTXDAT_DAT_MASK)
/*! @} */
/*! @name IPRXDAT - RX DATA Register */
/*! @{ */
#define SEMC_IPRXDAT_DAT_MASK (0xFFFFFFFFU)
#define SEMC_IPRXDAT_DAT_SHIFT (0U)
#define SEMC_IPRXDAT_DAT(x) (((uint32_t)(((uint32_t)(x)) << SEMC_IPRXDAT_DAT_SHIFT)) & SEMC_IPRXDAT_DAT_MASK)
/*! @} */
/*! @name STS0 - Status Register 0 */
/*! @{ */
#define SEMC_STS0_IDLE_MASK (0x1U)
#define SEMC_STS0_IDLE_SHIFT (0U)
/*! IDLE - Indicating whether the SEMC is in idle state.
*/
#define SEMC_STS0_IDLE(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_IDLE_SHIFT)) & SEMC_STS0_IDLE_MASK)
#define SEMC_STS0_NARDY_MASK (0x2U)
#define SEMC_STS0_NARDY_SHIFT (1U)
/*! NARDY - Indicating NAND device Ready/WAIT# pin level.
* 0b0..NAND device is not ready
* 0b1..NAND device is ready
*/
#define SEMC_STS0_NARDY(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS0_NARDY_SHIFT)) & SEMC_STS0_NARDY_MASK)
/*! @} */
/*! @name STS2 - Status Register 2 */
/*! @{ */
#define SEMC_STS2_NDWRPEND_MASK (0x8U)
#define SEMC_STS2_NDWRPEND_SHIFT (3U)
/*! NDWRPEND - This field indicating whether there is pending AXI command (write) to NAND device.
* 0b0..No pending
* 0b1..Pending
*/
#define SEMC_STS2_NDWRPEND(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS2_NDWRPEND_SHIFT)) & SEMC_STS2_NDWRPEND_MASK)
/*! @} */
/*! @name STS12 - Status Register 12 */
/*! @{ */
#define SEMC_STS12_NDADDR_MASK (0xFFFFFFFFU)
#define SEMC_STS12_NDADDR_SHIFT (0U)
/*! NDADDR - This field indicating the last write address (AXI command) to NAND device (without base address in SEMC_BR4).
*/
#define SEMC_STS12_NDADDR(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS12_NDADDR_SHIFT)) & SEMC_STS12_NDADDR_MASK)
/*! @} */
/*! @name STS13 - Status Register 13 */
/*! @{ */
#define SEMC_STS13_SLVLOCK_MASK (0x1U)
#define SEMC_STS13_SLVLOCK_SHIFT (0U)
/*! SLVLOCK - Sample clock slave delay line locked.
* 0b0..Slave delay line is not locked.
* 0b1..Slave delay line is locked.
*/
#define SEMC_STS13_SLVLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVLOCK_SHIFT)) & SEMC_STS13_SLVLOCK_MASK)
#define SEMC_STS13_REFLOCK_MASK (0x2U)
#define SEMC_STS13_REFLOCK_SHIFT (1U)
/*! REFLOCK - Sample clock reference delay line locked.
* 0b0..Reference delay line is not locked.
* 0b1..Reference delay line is locked.
*/
#define SEMC_STS13_REFLOCK(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFLOCK_SHIFT)) & SEMC_STS13_REFLOCK_MASK)
#define SEMC_STS13_SLVSEL_MASK (0xFCU)
#define SEMC_STS13_SLVSEL_SHIFT (2U)
/*! SLVSEL - Sample clock slave delay line delay cell number selection.
*/
#define SEMC_STS13_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_SLVSEL_SHIFT)) & SEMC_STS13_SLVSEL_MASK)
#define SEMC_STS13_REFSEL_MASK (0x3F00U)
#define SEMC_STS13_REFSEL_SHIFT (8U)
/*! REFSEL - Sample clock reference delay line delay cell number selection.
*/
#define SEMC_STS13_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_STS13_REFSEL_SHIFT)) & SEMC_STS13_REFSEL_MASK)
/*! @} */
/*! @name BR9 - Base Register 9 */
/*! @{ */
#define SEMC_BR9_VLD_MASK (0x1U)
#define SEMC_BR9_VLD_SHIFT (0U)
/*! VLD - Valid
* 0b0..The memory is invalid, can not be accessed.
* 0b1..The memory is valid, can be accessed.
*/
#define SEMC_BR9_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_VLD_SHIFT)) & SEMC_BR9_VLD_MASK)
#define SEMC_BR9_MS_MASK (0x3EU)
#define SEMC_BR9_MS_SHIFT (1U)
/*! MS - Memory size
* 0b00000..4KB
* 0b00001..8KB
* 0b00010..16KB
* 0b00011..32KB
* 0b00100..64KB
* 0b00101..128KB
* 0b00110..256KB
* 0b00111..512KB
* 0b01000..1MB
* 0b01001..2MB
* 0b01010..4MB
* 0b01011..8MB
* 0b01100..16MB
* 0b01101..32MB
* 0b01110..64MB
* 0b01111..128MB
* 0b10000..256MB
* 0b10001..512MB
* 0b10010..1GB
* 0b10011..2GB
* 0b10100-0b11111..4GB
*/
#define SEMC_BR9_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_MS_SHIFT)) & SEMC_BR9_MS_MASK)
#define SEMC_BR9_BA_MASK (0xFFFFF000U)
#define SEMC_BR9_BA_SHIFT (12U)
/*! BA - Base Address
*/
#define SEMC_BR9_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR9_BA_SHIFT)) & SEMC_BR9_BA_MASK)
/*! @} */
/*! @name BR10 - Base Register 10 */
/*! @{ */
#define SEMC_BR10_VLD_MASK (0x1U)
#define SEMC_BR10_VLD_SHIFT (0U)
/*! VLD - Valid
* 0b0..The memory is invalid, can not be accessed.
* 0b1..The memory is valid, can be accessed.
*/
#define SEMC_BR10_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_VLD_SHIFT)) & SEMC_BR10_VLD_MASK)
#define SEMC_BR10_MS_MASK (0x3EU)
#define SEMC_BR10_MS_SHIFT (1U)
/*! MS - Memory size
* 0b00000..4KB
* 0b00001..8KB
* 0b00010..16KB
* 0b00011..32KB
* 0b00100..64KB
* 0b00101..128KB
* 0b00110..256KB
* 0b00111..512KB
* 0b01000..1MB
* 0b01001..2MB
* 0b01010..4MB
* 0b01011..8MB
* 0b01100..16MB
* 0b01101..32MB
* 0b01110..64MB
* 0b01111..128MB
* 0b10000..256MB
* 0b10001..512MB
* 0b10010..1GB
* 0b10011..2GB
* 0b10100-0b11111..4GB
*/
#define SEMC_BR10_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_MS_SHIFT)) & SEMC_BR10_MS_MASK)
#define SEMC_BR10_BA_MASK (0xFFFFF000U)
#define SEMC_BR10_BA_SHIFT (12U)
/*! BA - Base Address
*/
#define SEMC_BR10_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR10_BA_SHIFT)) & SEMC_BR10_BA_MASK)
/*! @} */
/*! @name BR11 - Base Register 11 */
/*! @{ */
#define SEMC_BR11_VLD_MASK (0x1U)
#define SEMC_BR11_VLD_SHIFT (0U)
/*! VLD - Valid
* 0b0..The memory is invalid, can not be accessed.
* 0b1..The memory is valid, can be accessed.
*/
#define SEMC_BR11_VLD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_VLD_SHIFT)) & SEMC_BR11_VLD_MASK)
#define SEMC_BR11_MS_MASK (0x3EU)
#define SEMC_BR11_MS_SHIFT (1U)
/*! MS - Memory size
* 0b00000..4KB
* 0b00001..8KB
* 0b00010..16KB
* 0b00011..32KB
* 0b00100..64KB
* 0b00101..128KB
* 0b00110..256KB
* 0b00111..512KB
* 0b01000..1MB
* 0b01001..2MB
* 0b01010..4MB
* 0b01011..8MB
* 0b01100..16MB
* 0b01101..32MB
* 0b01110..64MB
* 0b01111..128MB
* 0b10000..256MB
* 0b10001..512MB
* 0b10010..1GB
* 0b10011..2GB
* 0b10100-0b11111..4GB
*/
#define SEMC_BR11_MS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_MS_SHIFT)) & SEMC_BR11_MS_MASK)
#define SEMC_BR11_BA_MASK (0xFFFFF000U)
#define SEMC_BR11_BA_SHIFT (12U)
/*! BA - Base Address
*/
#define SEMC_BR11_BA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_BR11_BA_SHIFT)) & SEMC_BR11_BA_MASK)
/*! @} */
/*! @name SRAMCR4 - SRAM Control Register 4 */
/*! @{ */
#define SEMC_SRAMCR4_PS_MASK (0x1U)
#define SEMC_SRAMCR4_PS_SHIFT (0U)
/*! PS - Port Size
* 0b0..8bit
* 0b1..16bit
*/
#define SEMC_SRAMCR4_PS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_PS_SHIFT)) & SEMC_SRAMCR4_PS_MASK)
#define SEMC_SRAMCR4_SYNCEN_MASK (0x2U)
#define SEMC_SRAMCR4_SYNCEN_SHIFT (1U)
/*! SYNCEN - Synchronous Mode Enable
* 0b0..Asynchronous mode is enabled.
* 0b1..Synchronous mode is enabled. Only fixed latency mode is supported.
*/
#define SEMC_SRAMCR4_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_SYNCEN_SHIFT)) & SEMC_SRAMCR4_SYNCEN_MASK)
#define SEMC_SRAMCR4_WAITEN_MASK (0x4U)
#define SEMC_SRAMCR4_WAITEN_SHIFT (2U)
/*! WAITEN - Wait Enable
* 0b0..The SEMC does not monitor wait pin.
* 0b1..The SEMC monitors wait pin. The SEMC does not transfer/receive data when wait pin is asserted.
*/
#define SEMC_SRAMCR4_WAITEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITEN_SHIFT)) & SEMC_SRAMCR4_WAITEN_MASK)
#define SEMC_SRAMCR4_WAITSP_MASK (0x8U)
#define SEMC_SRAMCR4_WAITSP_SHIFT (3U)
/*! WAITSP - Wait Sample
* 0b0..Wait pin is directly used by the SEMC.
* 0b1..Wait pin is sampled by internal clock before it is used.
*/
#define SEMC_SRAMCR4_WAITSP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_WAITSP_SHIFT)) & SEMC_SRAMCR4_WAITSP_MASK)
#define SEMC_SRAMCR4_BL_MASK (0x70U)
#define SEMC_SRAMCR4_BL_SHIFT (4U)
/*! BL - Burst Length
* 0b000..1
* 0b001..2
* 0b010..4
* 0b011..8
* 0b100..16
* 0b101..32
* 0b110..64
* 0b111..64
*/
#define SEMC_SRAMCR4_BL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_BL_SHIFT)) & SEMC_SRAMCR4_BL_MASK)
#define SEMC_SRAMCR4_AM_MASK (0x300U)
#define SEMC_SRAMCR4_AM_SHIFT (8U)
/*! AM - Address Mode
* 0b00..Address/Data MUX mode (ADMUX)
* 0b01..Advanced Address/Data MUX mode (AADM)
* 0b10..Address/Data non-MUX mode (Non-ADMUX)
* 0b11..Address/Data non-MUX mode (Non-ADMUX)
*/
#define SEMC_SRAMCR4_AM(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_AM_SHIFT)) & SEMC_SRAMCR4_AM_MASK)
#define SEMC_SRAMCR4_ADVP_MASK (0x400U)
#define SEMC_SRAMCR4_ADVP_SHIFT (10U)
/*! ADVP - ADV# polarity
* 0b0..ADV# is active low.
* 0b1..ADV# is active high.
*/
#define SEMC_SRAMCR4_ADVP(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVP_SHIFT)) & SEMC_SRAMCR4_ADVP_MASK)
#define SEMC_SRAMCR4_ADVH_MASK (0x800U)
#define SEMC_SRAMCR4_ADVH_SHIFT (11U)
/*! ADVH - ADV# level control during address hold state
* 0b0..ADV# is high during address hold state.
* 0b1..ADV# is low during address hold state.
*/
#define SEMC_SRAMCR4_ADVH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_ADVH_SHIFT)) & SEMC_SRAMCR4_ADVH_MASK)
#define SEMC_SRAMCR4_COL_MASK (0xF000U)
#define SEMC_SRAMCR4_COL_SHIFT (12U)
/*! COL - Column Address bit width
* 0b0000..12 Bits
* 0b0001..11 Bits
* 0b0010..10 Bits
* 0b0011..9 Bits
* 0b0100..8 Bits
* 0b0101..7 Bits
* 0b0110..6 Bits
* 0b0111..5 Bits
* 0b1000..4 Bits
* 0b1001..3 Bits
* 0b1010..2 Bits
* 0b1011..12 Bits
* 0b1100..12 Bits
* 0b1101..12 Bits
* 0b1110..12 Bits
* 0b1111..12 Bits
*/
#define SEMC_SRAMCR4_COL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR4_COL_SHIFT)) & SEMC_SRAMCR4_COL_MASK)
/*! @} */
/*! @name SRAMCR5 - SRAM Control Register 5 */
/*! @{ */
#define SEMC_SRAMCR5_CES_MASK (0xFU)
#define SEMC_SRAMCR5_CES_SHIFT (0U)
/*! CES - CE setup time
*/
#define SEMC_SRAMCR5_CES(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CES_SHIFT)) & SEMC_SRAMCR5_CES_MASK)
#define SEMC_SRAMCR5_CEH_MASK (0xF0U)
#define SEMC_SRAMCR5_CEH_SHIFT (4U)
/*! CEH - CE hold time
*/
#define SEMC_SRAMCR5_CEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_CEH_SHIFT)) & SEMC_SRAMCR5_CEH_MASK)
#define SEMC_SRAMCR5_AS_MASK (0xF00U)
#define SEMC_SRAMCR5_AS_SHIFT (8U)
/*! AS - Address setup time
*/
#define SEMC_SRAMCR5_AS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AS_SHIFT)) & SEMC_SRAMCR5_AS_MASK)
#define SEMC_SRAMCR5_AH_MASK (0xF000U)
#define SEMC_SRAMCR5_AH_SHIFT (12U)
/*! AH - Address hold time
*/
#define SEMC_SRAMCR5_AH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_AH_SHIFT)) & SEMC_SRAMCR5_AH_MASK)
#define SEMC_SRAMCR5_WEL_MASK (0xF0000U)
#define SEMC_SRAMCR5_WEL_SHIFT (16U)
/*! WEL - WE low time
*/
#define SEMC_SRAMCR5_WEL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEL_SHIFT)) & SEMC_SRAMCR5_WEL_MASK)
#define SEMC_SRAMCR5_WEH_MASK (0xF00000U)
#define SEMC_SRAMCR5_WEH_SHIFT (20U)
/*! WEH - WE high time
*/
#define SEMC_SRAMCR5_WEH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_WEH_SHIFT)) & SEMC_SRAMCR5_WEH_MASK)
#define SEMC_SRAMCR5_REL_MASK (0xF000000U)
#define SEMC_SRAMCR5_REL_SHIFT (24U)
/*! REL - RE low time
*/
#define SEMC_SRAMCR5_REL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REL_SHIFT)) & SEMC_SRAMCR5_REL_MASK)
#define SEMC_SRAMCR5_REH_MASK (0xF0000000U)
#define SEMC_SRAMCR5_REH_SHIFT (28U)
/*! REH - RE high time
*/
#define SEMC_SRAMCR5_REH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR5_REH_SHIFT)) & SEMC_SRAMCR5_REH_MASK)
/*! @} */
/*! @name SRAMCR6 - SRAM Control Register 6 */
/*! @{ */
#define SEMC_SRAMCR6_WDS_MASK (0xFU)
#define SEMC_SRAMCR6_WDS_SHIFT (0U)
/*! WDS - Write Data setup time
*/
#define SEMC_SRAMCR6_WDS(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDS_SHIFT)) & SEMC_SRAMCR6_WDS_MASK)
#define SEMC_SRAMCR6_WDH_MASK (0xF0U)
#define SEMC_SRAMCR6_WDH_SHIFT (4U)
/*! WDH - Write Data hold time
*/
#define SEMC_SRAMCR6_WDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_WDH_SHIFT)) & SEMC_SRAMCR6_WDH_MASK)
#define SEMC_SRAMCR6_TA_MASK (0xF00U)
#define SEMC_SRAMCR6_TA_SHIFT (8U)
/*! TA - Turnaround time
*/
#define SEMC_SRAMCR6_TA(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_TA_SHIFT)) & SEMC_SRAMCR6_TA_MASK)
#define SEMC_SRAMCR6_AWDH_MASK (0xF000U)
#define SEMC_SRAMCR6_AWDH_SHIFT (12U)
/*! AWDH - Address to write data hold time
*/
#define SEMC_SRAMCR6_AWDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_AWDH_SHIFT)) & SEMC_SRAMCR6_AWDH_MASK)
#define SEMC_SRAMCR6_LC_MASK (0xF0000U)
#define SEMC_SRAMCR6_LC_SHIFT (16U)
/*! LC - Latency count
*/
#define SEMC_SRAMCR6_LC(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_LC_SHIFT)) & SEMC_SRAMCR6_LC_MASK)
#define SEMC_SRAMCR6_RD_MASK (0xF00000U)
#define SEMC_SRAMCR6_RD_SHIFT (20U)
/*! RD - Read time
*/
#define SEMC_SRAMCR6_RD(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RD_SHIFT)) & SEMC_SRAMCR6_RD_MASK)
#define SEMC_SRAMCR6_CEITV_MASK (0xF000000U)
#define SEMC_SRAMCR6_CEITV_SHIFT (24U)
/*! CEITV - CE# interval time
*/
#define SEMC_SRAMCR6_CEITV(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_CEITV_SHIFT)) & SEMC_SRAMCR6_CEITV_MASK)
#define SEMC_SRAMCR6_RDH_MASK (0xF0000000U)
#define SEMC_SRAMCR6_RDH_SHIFT (28U)
/*! RDH - Read hold time
*/
#define SEMC_SRAMCR6_RDH(x) (((uint32_t)(((uint32_t)(x)) << SEMC_SRAMCR6_RDH_SHIFT)) & SEMC_SRAMCR6_RDH_MASK)
/*! @} */
/*! @name DCCR - Delay Chain Control Register */
/*! @{ */
#define SEMC_DCCR_SDRAMEN_MASK (0x1U)
#define SEMC_DCCR_SDRAMEN_SHIFT (0U)
/*! SDRAMEN - Delay chain insertion enable for SRAM device.
* 0b0..Delay chain is not inserted.
* 0b1..Delay chain is inserted.
*/
#define SEMC_DCCR_SDRAMEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMEN_SHIFT)) & SEMC_DCCR_SDRAMEN_MASK)
#define SEMC_DCCR_SDRAMVAL_MASK (0x3EU)
#define SEMC_DCCR_SDRAMVAL_SHIFT (1U)
/*! SDRAMVAL - Clock delay line delay cell number selection value for SDRAM device.
*/
#define SEMC_DCCR_SDRAMVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SDRAMVAL_SHIFT)) & SEMC_DCCR_SDRAMVAL_MASK)
#define SEMC_DCCR_NOREN_MASK (0x100U)
#define SEMC_DCCR_NOREN_SHIFT (8U)
/*! NOREN - Delay chain insertion enable for NOR device.
* 0b0..Delay chain is not inserted.
* 0b1..Delay chain is inserted.
*/
#define SEMC_DCCR_NOREN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NOREN_SHIFT)) & SEMC_DCCR_NOREN_MASK)
#define SEMC_DCCR_NORVAL_MASK (0x3E00U)
#define SEMC_DCCR_NORVAL_SHIFT (9U)
/*! NORVAL - Clock delay line delay cell number selection value for NOR device.
*/
#define SEMC_DCCR_NORVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_NORVAL_SHIFT)) & SEMC_DCCR_NORVAL_MASK)
#define SEMC_DCCR_SRAM0EN_MASK (0x10000U)
#define SEMC_DCCR_SRAM0EN_SHIFT (16U)
/*! SRAM0EN - Delay chain insertion enable for SRAM device 0.
* 0b0..Delay chain is not inserted.
* 0b1..Delay chain is inserted.
*/
#define SEMC_DCCR_SRAM0EN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0EN_SHIFT)) & SEMC_DCCR_SRAM0EN_MASK)
#define SEMC_DCCR_SRAM0VAL_MASK (0x3E0000U)
#define SEMC_DCCR_SRAM0VAL_SHIFT (17U)
/*! SRAM0VAL - Clock delay line delay cell number selection value for SRAM device 0.
*/
#define SEMC_DCCR_SRAM0VAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAM0VAL_SHIFT)) & SEMC_DCCR_SRAM0VAL_MASK)
#define SEMC_DCCR_SRAMXEN_MASK (0x1000000U)
#define SEMC_DCCR_SRAMXEN_SHIFT (24U)
/*! SRAMXEN - Delay chain insertion enable for SRAM device 1-3.
* 0b0..Delay chain is not inserted.
* 0b1..Delay chain is inserted.
*/
#define SEMC_DCCR_SRAMXEN(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXEN_SHIFT)) & SEMC_DCCR_SRAMXEN_MASK)
#define SEMC_DCCR_SRAMXVAL_MASK (0x3E000000U)
#define SEMC_DCCR_SRAMXVAL_SHIFT (25U)
/*! SRAMXVAL - Clock delay line delay cell number selection value for SRAM device 1-3.
*/
#define SEMC_DCCR_SRAMXVAL(x) (((uint32_t)(((uint32_t)(x)) << SEMC_DCCR_SRAMXVAL_SHIFT)) & SEMC_DCCR_SRAMXVAL_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SEMC_Register_Masks */
/* SEMC - Peripheral instance base addresses */
/** Peripheral SEMC base address */
#define SEMC_BASE (0x400D4000u)
/** Peripheral SEMC base pointer */
#define SEMC ((SEMC_Type *)SEMC_BASE)
/** Array initializer of SEMC peripheral base addresses */
#define SEMC_BASE_ADDRS { SEMC_BASE }
/** Array initializer of SEMC peripheral base pointers */
#define SEMC_BASE_PTRS { SEMC }
/** Interrupt vectors for the SEMC peripheral type */
#define SEMC_IRQS { SEMC_IRQn }
/*!
* @}
*/ /* end of group SEMC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SNVS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SNVS_Peripheral_Access_Layer SNVS Peripheral Access Layer
* @{
*/
/** SNVS - Register Layout Typedef */
typedef struct {
__IO uint32_t HPLR; /**< SNVS_HP Lock Register, offset: 0x0 */
__IO uint32_t HPCOMR; /**< SNVS_HP Command Register, offset: 0x4 */
__IO uint32_t HPCR; /**< SNVS_HP Control Register, offset: 0x8 */
__IO uint32_t HPSICR; /**< SNVS_HP Security Interrupt Control Register, offset: 0xC */
__IO uint32_t HPSVCR; /**< SNVS_HP Security Violation Control Register, offset: 0x10 */
__IO uint32_t HPSR; /**< SNVS_HP Status Register, offset: 0x14 */
__IO uint32_t HPSVSR; /**< SNVS_HP Security Violation Status Register, offset: 0x18 */
__IO uint32_t HPHACIVR; /**< SNVS_HP High Assurance Counter IV Register, offset: 0x1C */
__I uint32_t HPHACR; /**< SNVS_HP High Assurance Counter Register, offset: 0x20 */
__IO uint32_t HPRTCMR; /**< SNVS_HP Real Time Counter MSB Register, offset: 0x24 */
__IO uint32_t HPRTCLR; /**< SNVS_HP Real Time Counter LSB Register, offset: 0x28 */
__IO uint32_t HPTAMR; /**< SNVS_HP Time Alarm MSB Register, offset: 0x2C */
__IO uint32_t HPTALR; /**< SNVS_HP Time Alarm LSB Register, offset: 0x30 */
__IO uint32_t LPLR; /**< SNVS_LP Lock Register, offset: 0x34 */
__IO uint32_t LPCR; /**< SNVS_LP Control Register, offset: 0x38 */
__IO uint32_t LPMKCR; /**< SNVS_LP Master Key Control Register, offset: 0x3C */
__IO uint32_t LPSVCR; /**< SNVS_LP Security Violation Control Register, offset: 0x40 */
__IO uint32_t LPTGFCR; /**< SNVS_LP Tamper Glitch Filters Configuration Register, offset: 0x44 */
__IO uint32_t LPTDCR; /**< SNVS_LP Tamper Detect Configuration Register, offset: 0x48 */
__IO uint32_t LPSR; /**< SNVS_LP Status Register, offset: 0x4C */
__IO uint32_t LPSRTCMR; /**< SNVS_LP Secure Real Time Counter MSB Register, offset: 0x50 */
__IO uint32_t LPSRTCLR; /**< SNVS_LP Secure Real Time Counter LSB Register, offset: 0x54 */
__IO uint32_t LPTAR; /**< SNVS_LP Time Alarm Register, offset: 0x58 */
__IO uint32_t LPSMCMR; /**< SNVS_LP Secure Monotonic Counter MSB Register, offset: 0x5C */
__IO uint32_t LPSMCLR; /**< SNVS_LP Secure Monotonic Counter LSB Register, offset: 0x60 */
__IO uint32_t LPLVDR; /**< SNVS_LP Digital Low-Voltage Detector Register, offset: 0x64 */
__IO uint32_t LPGPR0_LEGACY_ALIAS; /**< SNVS_LP General Purpose Register 0 (legacy alias), offset: 0x68 */
__IO uint32_t LPZMKR[8]; /**< SNVS_LP Zeroizable Master Key Register, array offset: 0x6C, array step: 0x4 */
uint8_t RESERVED_0[4];
__IO uint32_t LPGPR_ALIAS[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x90, array step: 0x4 */
__IO uint32_t LPTDC2R; /**< SNVS_LP Tamper Detectors Config 2 Register, offset: 0xA0 */
__IO uint32_t LPTDSR; /**< SNVS_LP Tamper Detectors Status Register, offset: 0xA4 */
__IO uint32_t LPTGF1CR; /**< SNVS_LP Tamper Glitch Filter 1 Configuration Register, offset: 0xA8 */
__IO uint32_t LPTGF2CR; /**< SNVS_LP Tamper Glitch Filter 2 Configuration Register, offset: 0xAC */
uint8_t RESERVED_1[16];
__O uint32_t LPATCR[5]; /**< SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register, array offset: 0xC0, array step: 0x4 */
uint8_t RESERVED_2[12];
__IO uint32_t LPATCTLR; /**< SNVS_LP Active Tamper Control Register, offset: 0xE0 */
__IO uint32_t LPATCLKR; /**< SNVS_LP Active Tamper Clock Control Register, offset: 0xE4 */
__IO uint32_t LPATRC1R; /**< SNVS_LP Active Tamper Routing Control 1 Register, offset: 0xE8 */
__IO uint32_t LPATRC2R; /**< SNVS_LP Active Tamper Routing Control 2 Register, offset: 0xEC */
uint8_t RESERVED_3[16];
__IO uint32_t LPGPR[4]; /**< SNVS_LP General Purpose Registers 0 .. 3, array offset: 0x100, array step: 0x4 */
uint8_t RESERVED_4[2792];
__I uint32_t HPVIDR1; /**< SNVS_HP Version ID Register 1, offset: 0xBF8 */
__I uint32_t HPVIDR2; /**< SNVS_HP Version ID Register 2, offset: 0xBFC */
} SNVS_Type;
/* ----------------------------------------------------------------------------
-- SNVS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SNVS_Register_Masks SNVS Register Masks
* @{
*/
/*! @name HPLR - SNVS_HP Lock Register */
/*! @{ */
#define SNVS_HPLR_ZMK_WSL_MASK (0x1U)
#define SNVS_HPLR_ZMK_WSL_SHIFT (0U)
/*! ZMK_WSL
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_ZMK_WSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_WSL_SHIFT)) & SNVS_HPLR_ZMK_WSL_MASK)
#define SNVS_HPLR_ZMK_RSL_MASK (0x2U)
#define SNVS_HPLR_ZMK_RSL_SHIFT (1U)
/*! ZMK_RSL
* 0b0..Read access is allowed (only in software Programming mode)
* 0b1..Read access is not allowed
*/
#define SNVS_HPLR_ZMK_RSL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_ZMK_RSL_SHIFT)) & SNVS_HPLR_ZMK_RSL_MASK)
#define SNVS_HPLR_SRTC_SL_MASK (0x4U)
#define SNVS_HPLR_SRTC_SL_SHIFT (2U)
/*! SRTC_SL
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_SRTC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_SRTC_SL_SHIFT)) & SNVS_HPLR_SRTC_SL_MASK)
#define SNVS_HPLR_LPCALB_SL_MASK (0x8U)
#define SNVS_HPLR_LPCALB_SL_SHIFT (3U)
/*! LPCALB_SL
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_LPCALB_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPCALB_SL_SHIFT)) & SNVS_HPLR_LPCALB_SL_MASK)
#define SNVS_HPLR_MC_SL_MASK (0x10U)
#define SNVS_HPLR_MC_SL_SHIFT (4U)
/*! MC_SL
* 0b0..Write access (increment) is allowed
* 0b1..Write access (increment) is not allowed
*/
#define SNVS_HPLR_MC_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MC_SL_SHIFT)) & SNVS_HPLR_MC_SL_MASK)
#define SNVS_HPLR_GPR_SL_MASK (0x20U)
#define SNVS_HPLR_GPR_SL_SHIFT (5U)
/*! GPR_SL
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_GPR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_GPR_SL_SHIFT)) & SNVS_HPLR_GPR_SL_MASK)
#define SNVS_HPLR_LPSVCR_SL_MASK (0x40U)
#define SNVS_HPLR_LPSVCR_SL_SHIFT (6U)
/*! LPSVCR_SL
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_LPSVCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSVCR_SL_SHIFT)) & SNVS_HPLR_LPSVCR_SL_MASK)
#define SNVS_HPLR_LPTGFCR_SL_MASK (0x80U)
#define SNVS_HPLR_LPTGFCR_SL_SHIFT (7U)
/*! LPTGFCR_SL
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_LPTGFCR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPTGFCR_SL_SHIFT)) & SNVS_HPLR_LPTGFCR_SL_MASK)
#define SNVS_HPLR_LPSECR_SL_MASK (0x100U)
#define SNVS_HPLR_LPSECR_SL_SHIFT (8U)
/*! LPSECR_SL
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_LPSECR_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_LPSECR_SL_SHIFT)) & SNVS_HPLR_LPSECR_SL_MASK)
#define SNVS_HPLR_MKS_SL_MASK (0x200U)
#define SNVS_HPLR_MKS_SL_SHIFT (9U)
/*! MKS_SL
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_MKS_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_MKS_SL_SHIFT)) & SNVS_HPLR_MKS_SL_MASK)
#define SNVS_HPLR_HPSVCR_L_MASK (0x10000U)
#define SNVS_HPLR_HPSVCR_L_SHIFT (16U)
/*! HPSVCR_L
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_HPSVCR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSVCR_L_SHIFT)) & SNVS_HPLR_HPSVCR_L_MASK)
#define SNVS_HPLR_HPSICR_L_MASK (0x20000U)
#define SNVS_HPLR_HPSICR_L_SHIFT (17U)
/*! HPSICR_L
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_HPSICR_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HPSICR_L_SHIFT)) & SNVS_HPLR_HPSICR_L_MASK)
#define SNVS_HPLR_HAC_L_MASK (0x40000U)
#define SNVS_HPLR_HAC_L_SHIFT (18U)
/*! HAC_L
* 0b0..Write access is allowed
* 0b1..Write access is not allowed
*/
#define SNVS_HPLR_HAC_L(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_HAC_L_SHIFT)) & SNVS_HPLR_HAC_L_MASK)
#define SNVS_HPLR_AT1_SL_MASK (0x1000000U)
#define SNVS_HPLR_AT1_SL_SHIFT (24U)
/*! AT1_SL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_HPLR_AT1_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT1_SL_SHIFT)) & SNVS_HPLR_AT1_SL_MASK)
#define SNVS_HPLR_AT2_SL_MASK (0x2000000U)
#define SNVS_HPLR_AT2_SL_SHIFT (25U)
/*! AT2_SL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_HPLR_AT2_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT2_SL_SHIFT)) & SNVS_HPLR_AT2_SL_MASK)
#define SNVS_HPLR_AT3_SL_MASK (0x4000000U)
#define SNVS_HPLR_AT3_SL_SHIFT (26U)
/*! AT3_SL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_HPLR_AT3_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT3_SL_SHIFT)) & SNVS_HPLR_AT3_SL_MASK)
#define SNVS_HPLR_AT4_SL_MASK (0x8000000U)
#define SNVS_HPLR_AT4_SL_SHIFT (27U)
/*! AT4_SL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_HPLR_AT4_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT4_SL_SHIFT)) & SNVS_HPLR_AT4_SL_MASK)
#define SNVS_HPLR_AT5_SL_MASK (0x10000000U)
#define SNVS_HPLR_AT5_SL_SHIFT (28U)
/*! AT5_SL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_HPLR_AT5_SL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPLR_AT5_SL_SHIFT)) & SNVS_HPLR_AT5_SL_MASK)
/*! @} */
/*! @name HPCOMR - SNVS_HP Command Register */
/*! @{ */
#define SNVS_HPCOMR_SSM_ST_MASK (0x1U)
#define SNVS_HPCOMR_SSM_ST_SHIFT (0U)
#define SNVS_HPCOMR_SSM_ST(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_SHIFT)) & SNVS_HPCOMR_SSM_ST_MASK)
#define SNVS_HPCOMR_SSM_ST_DIS_MASK (0x2U)
#define SNVS_HPCOMR_SSM_ST_DIS_SHIFT (1U)
/*! SSM_ST_DIS
* 0b0..Secure to Trusted State transition is enabled
* 0b1..Secure to Trusted State transition is disabled
*/
#define SNVS_HPCOMR_SSM_ST_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_ST_DIS_SHIFT)) & SNVS_HPCOMR_SSM_ST_DIS_MASK)
#define SNVS_HPCOMR_SSM_SFNS_DIS_MASK (0x4U)
#define SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT (2U)
/*! SSM_SFNS_DIS
* 0b0..Soft Fail to Non-Secure State transition is enabled
* 0b1..Soft Fail to Non-Secure State transition is disabled
*/
#define SNVS_HPCOMR_SSM_SFNS_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SSM_SFNS_DIS_SHIFT)) & SNVS_HPCOMR_SSM_SFNS_DIS_MASK)
#define SNVS_HPCOMR_LP_SWR_MASK (0x10U)
#define SNVS_HPCOMR_LP_SWR_SHIFT (4U)
/*! LP_SWR
* 0b0..No Action
* 0b1..Reset LP section
*/
#define SNVS_HPCOMR_LP_SWR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_SHIFT)) & SNVS_HPCOMR_LP_SWR_MASK)
#define SNVS_HPCOMR_LP_SWR_DIS_MASK (0x20U)
#define SNVS_HPCOMR_LP_SWR_DIS_SHIFT (5U)
/*! LP_SWR_DIS
* 0b0..LP software reset is enabled
* 0b1..LP software reset is disabled
*/
#define SNVS_HPCOMR_LP_SWR_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_LP_SWR_DIS_SHIFT)) & SNVS_HPCOMR_LP_SWR_DIS_MASK)
#define SNVS_HPCOMR_SW_SV_MASK (0x100U)
#define SNVS_HPCOMR_SW_SV_SHIFT (8U)
#define SNVS_HPCOMR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_SV_SHIFT)) & SNVS_HPCOMR_SW_SV_MASK)
#define SNVS_HPCOMR_SW_FSV_MASK (0x200U)
#define SNVS_HPCOMR_SW_FSV_SHIFT (9U)
#define SNVS_HPCOMR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_FSV_SHIFT)) & SNVS_HPCOMR_SW_FSV_MASK)
#define SNVS_HPCOMR_SW_LPSV_MASK (0x400U)
#define SNVS_HPCOMR_SW_LPSV_SHIFT (10U)
#define SNVS_HPCOMR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_SW_LPSV_SHIFT)) & SNVS_HPCOMR_SW_LPSV_MASK)
#define SNVS_HPCOMR_PROG_ZMK_MASK (0x1000U)
#define SNVS_HPCOMR_PROG_ZMK_SHIFT (12U)
/*! PROG_ZMK
* 0b0..No Action
* 0b1..Activate hardware key programming mechanism
*/
#define SNVS_HPCOMR_PROG_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_PROG_ZMK_SHIFT)) & SNVS_HPCOMR_PROG_ZMK_MASK)
#define SNVS_HPCOMR_MKS_EN_MASK (0x2000U)
#define SNVS_HPCOMR_MKS_EN_SHIFT (13U)
/*! MKS_EN
* 0b0..OTP master key is selected as an SNVS master key
* 0b1..SNVS master key is selected according to the setting of the MASTER_KEY_SEL field of LPMKCR
*/
#define SNVS_HPCOMR_MKS_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_MKS_EN_SHIFT)) & SNVS_HPCOMR_MKS_EN_MASK)
#define SNVS_HPCOMR_HAC_EN_MASK (0x10000U)
#define SNVS_HPCOMR_HAC_EN_SHIFT (16U)
/*! HAC_EN
* 0b0..High Assurance Counter is disabled
* 0b1..High Assurance Counter is enabled
*/
#define SNVS_HPCOMR_HAC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_EN_SHIFT)) & SNVS_HPCOMR_HAC_EN_MASK)
#define SNVS_HPCOMR_HAC_LOAD_MASK (0x20000U)
#define SNVS_HPCOMR_HAC_LOAD_SHIFT (17U)
/*! HAC_LOAD
* 0b0..No Action
* 0b1..Load the HAC
*/
#define SNVS_HPCOMR_HAC_LOAD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_LOAD_SHIFT)) & SNVS_HPCOMR_HAC_LOAD_MASK)
#define SNVS_HPCOMR_HAC_CLEAR_MASK (0x40000U)
#define SNVS_HPCOMR_HAC_CLEAR_SHIFT (18U)
/*! HAC_CLEAR
* 0b0..No Action
* 0b1..Clear the HAC
*/
#define SNVS_HPCOMR_HAC_CLEAR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_CLEAR_SHIFT)) & SNVS_HPCOMR_HAC_CLEAR_MASK)
#define SNVS_HPCOMR_HAC_STOP_MASK (0x80000U)
#define SNVS_HPCOMR_HAC_STOP_SHIFT (19U)
#define SNVS_HPCOMR_HAC_STOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_HAC_STOP_SHIFT)) & SNVS_HPCOMR_HAC_STOP_MASK)
#define SNVS_HPCOMR_NPSWA_EN_MASK (0x80000000U)
#define SNVS_HPCOMR_NPSWA_EN_SHIFT (31U)
#define SNVS_HPCOMR_NPSWA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCOMR_NPSWA_EN_SHIFT)) & SNVS_HPCOMR_NPSWA_EN_MASK)
/*! @} */
/*! @name HPCR - SNVS_HP Control Register */
/*! @{ */
#define SNVS_HPCR_RTC_EN_MASK (0x1U)
#define SNVS_HPCR_RTC_EN_SHIFT (0U)
/*! RTC_EN
* 0b0..RTC is disabled
* 0b1..RTC is enabled
*/
#define SNVS_HPCR_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_RTC_EN_SHIFT)) & SNVS_HPCR_RTC_EN_MASK)
#define SNVS_HPCR_HPTA_EN_MASK (0x2U)
#define SNVS_HPCR_HPTA_EN_SHIFT (1U)
/*! HPTA_EN
* 0b0..HP Time Alarm Interrupt is disabled
* 0b1..HP Time Alarm Interrupt is enabled
*/
#define SNVS_HPCR_HPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPTA_EN_SHIFT)) & SNVS_HPCR_HPTA_EN_MASK)
#define SNVS_HPCR_DIS_PI_MASK (0x4U)
#define SNVS_HPCR_DIS_PI_SHIFT (2U)
/*! DIS_PI
* 0b0..Periodic interrupt will trigger a functional interrupt
* 0b1..Disable periodic interrupt in the function interrupt
*/
#define SNVS_HPCR_DIS_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_DIS_PI_SHIFT)) & SNVS_HPCR_DIS_PI_MASK)
#define SNVS_HPCR_PI_EN_MASK (0x8U)
#define SNVS_HPCR_PI_EN_SHIFT (3U)
/*! PI_EN
* 0b0..HP Periodic Interrupt is disabled
* 0b1..HP Periodic Interrupt is enabled
*/
#define SNVS_HPCR_PI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_EN_SHIFT)) & SNVS_HPCR_PI_EN_MASK)
#define SNVS_HPCR_PI_FREQ_MASK (0xF0U)
#define SNVS_HPCR_PI_FREQ_SHIFT (4U)
/*! PI_FREQ
* 0b0000..- bit 0 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b0001..- bit 1 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b0010..- bit 2 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b0011..- bit 3 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b0100..- bit 4 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b0101..- bit 5 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b0110..- bit 6 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b0111..- bit 7 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b1000..- bit 8 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b1001..- bit 9 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b1010..- bit 10 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b1011..- bit 11 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b1100..- bit 12 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b1101..- bit 13 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b1110..- bit 14 of the HPRTCLR is selected as a source of the periodic interrupt
* 0b1111..- bit 15 of the HPRTCLR is selected as a source of the periodic interrupt
*/
#define SNVS_HPCR_PI_FREQ(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_PI_FREQ_SHIFT)) & SNVS_HPCR_PI_FREQ_MASK)
#define SNVS_HPCR_HPCALB_EN_MASK (0x100U)
#define SNVS_HPCR_HPCALB_EN_SHIFT (8U)
/*! HPCALB_EN
* 0b0..HP Timer calibration disabled
* 0b1..HP Timer calibration enabled
*/
#define SNVS_HPCR_HPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_EN_SHIFT)) & SNVS_HPCR_HPCALB_EN_MASK)
#define SNVS_HPCR_HPCALB_VAL_MASK (0x7C00U)
#define SNVS_HPCR_HPCALB_VAL_SHIFT (10U)
/*! HPCALB_VAL
* 0b00000..+0 counts per each 32768 ticks of the counter
* 0b00001..+1 counts per each 32768 ticks of the counter
* 0b00010..+2 counts per each 32768 ticks of the counter
* 0b01111..+15 counts per each 32768 ticks of the counter
* 0b10000..-16 counts per each 32768 ticks of the counter
* 0b10001..-15 counts per each 32768 ticks of the counter
* 0b11110..-2 counts per each 32768 ticks of the counter
* 0b11111..-1 counts per each 32768 ticks of the counter
*/
#define SNVS_HPCR_HPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HPCALB_VAL_SHIFT)) & SNVS_HPCR_HPCALB_VAL_MASK)
#define SNVS_HPCR_HP_TS_MASK (0x10000U)
#define SNVS_HPCR_HP_TS_SHIFT (16U)
/*! HP_TS
* 0b0..No Action
* 0b1..Synchronize the HP Time Counter to the LP Time Counter
*/
#define SNVS_HPCR_HP_TS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_HP_TS_SHIFT)) & SNVS_HPCR_HP_TS_MASK)
#define SNVS_HPCR_BTN_CONFIG_MASK (0x7000000U)
#define SNVS_HPCR_BTN_CONFIG_SHIFT (24U)
#define SNVS_HPCR_BTN_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_CONFIG_SHIFT)) & SNVS_HPCR_BTN_CONFIG_MASK)
#define SNVS_HPCR_BTN_MASK_MASK (0x8000000U)
#define SNVS_HPCR_BTN_MASK_SHIFT (27U)
#define SNVS_HPCR_BTN_MASK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPCR_BTN_MASK_SHIFT)) & SNVS_HPCR_BTN_MASK_MASK)
/*! @} */
/*! @name HPSICR - SNVS_HP Security Interrupt Control Register */
/*! @{ */
#define SNVS_HPSICR_CAAM_EN_MASK (0x1U)
#define SNVS_HPSICR_CAAM_EN_SHIFT (0U)
/*! CAAM_EN
* 0b0..CAAM Security Violation Interrupt is Disabled
* 0b1..CAAM Security Violation Interrupt is Enabled
*/
#define SNVS_HPSICR_CAAM_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_CAAM_EN_SHIFT)) & SNVS_HPSICR_CAAM_EN_MASK)
#define SNVS_HPSICR_JTAGC_EN_MASK (0x2U)
#define SNVS_HPSICR_JTAGC_EN_SHIFT (1U)
/*! JTAGC_EN
* 0b0..JTAG Active Interrupt is Disabled
* 0b1..JTAG Active Interrupt is Enabled
*/
#define SNVS_HPSICR_JTAGC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_JTAGC_EN_SHIFT)) & SNVS_HPSICR_JTAGC_EN_MASK)
#define SNVS_HPSICR_WDOG2_EN_MASK (0x4U)
#define SNVS_HPSICR_WDOG2_EN_SHIFT (2U)
/*! WDOG2_EN
* 0b0..Watchdog 2 Reset Interrupt is Disabled
* 0b1..Watchdog 2 Reset Interrupt is Enabled
*/
#define SNVS_HPSICR_WDOG2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_WDOG2_EN_SHIFT)) & SNVS_HPSICR_WDOG2_EN_MASK)
#define SNVS_HPSICR_SRC_EN_MASK (0x10U)
#define SNVS_HPSICR_SRC_EN_SHIFT (4U)
/*! SRC_EN
* 0b0..Internal Boot Interrupt is Disabled
* 0b1..Internal Boot Interrupt is Enabled
*/
#define SNVS_HPSICR_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_SRC_EN_SHIFT)) & SNVS_HPSICR_SRC_EN_MASK)
#define SNVS_HPSICR_OCOTP_EN_MASK (0x20U)
#define SNVS_HPSICR_OCOTP_EN_SHIFT (5U)
/*! OCOTP_EN
* 0b0..OCOTP attack error Interrupt is Disabled
* 0b1..OCOTP attack error Interrupt is Enabled
*/
#define SNVS_HPSICR_OCOTP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_OCOTP_EN_SHIFT)) & SNVS_HPSICR_OCOTP_EN_MASK)
#define SNVS_HPSICR_LPSVI_EN_MASK (0x80000000U)
#define SNVS_HPSICR_LPSVI_EN_SHIFT (31U)
/*! LPSVI_EN
* 0b0..LP Security Violation Interrupt is Disabled
* 0b1..LP Security Violation Interrupt is Enabled
*/
#define SNVS_HPSICR_LPSVI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSICR_LPSVI_EN_SHIFT)) & SNVS_HPSICR_LPSVI_EN_MASK)
/*! @} */
/*! @name HPSVCR - SNVS_HP Security Violation Control Register */
/*! @{ */
#define SNVS_HPSVCR_CAAM_CFG_MASK (0x1U)
#define SNVS_HPSVCR_CAAM_CFG_SHIFT (0U)
/*! CAAM_CFG
* 0b0..CAAM Security Violation is a non-fatal violation
* 0b1..CAAM Security Violation is a fatal violation
*/
#define SNVS_HPSVCR_CAAM_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_CAAM_CFG_SHIFT)) & SNVS_HPSVCR_CAAM_CFG_MASK)
#define SNVS_HPSVCR_JTAGC_CFG_MASK (0x2U)
#define SNVS_HPSVCR_JTAGC_CFG_SHIFT (1U)
/*! JTAGC_CFG
* 0b0..JTAG Active is a non-fatal violation
* 0b1..JTAG Active is a fatal violation
*/
#define SNVS_HPSVCR_JTAGC_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_JTAGC_CFG_SHIFT)) & SNVS_HPSVCR_JTAGC_CFG_MASK)
#define SNVS_HPSVCR_WDOG2_CFG_MASK (0x4U)
#define SNVS_HPSVCR_WDOG2_CFG_SHIFT (2U)
/*! WDOG2_CFG
* 0b0..Watchdog 2 Reset is a non-fatal violation
* 0b1..Watchdog 2 Reset is a fatal violation
*/
#define SNVS_HPSVCR_WDOG2_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_WDOG2_CFG_SHIFT)) & SNVS_HPSVCR_WDOG2_CFG_MASK)
#define SNVS_HPSVCR_SRC_CFG_MASK (0x10U)
#define SNVS_HPSVCR_SRC_CFG_SHIFT (4U)
/*! SRC_CFG
* 0b0..Internal Boot is a non-fatal violation
* 0b1..Internal Boot is a fatal violation
*/
#define SNVS_HPSVCR_SRC_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_SRC_CFG_SHIFT)) & SNVS_HPSVCR_SRC_CFG_MASK)
#define SNVS_HPSVCR_OCOTP_CFG_MASK (0x60U)
#define SNVS_HPSVCR_OCOTP_CFG_SHIFT (5U)
/*! OCOTP_CFG
* 0b00..OCOTP attack error is disabled
* 0b01..OCOTP attack error is a non-fatal violation
* 0b1x..OCOTP attack error is a fatal violation
*/
#define SNVS_HPSVCR_OCOTP_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_OCOTP_CFG_SHIFT)) & SNVS_HPSVCR_OCOTP_CFG_MASK)
#define SNVS_HPSVCR_LPSV_CFG_MASK (0xC0000000U)
#define SNVS_HPSVCR_LPSV_CFG_SHIFT (30U)
/*! LPSV_CFG
* 0b00..LP security violation is disabled
* 0b01..LP security violation is a non-fatal violation
* 0b1x..LP security violation is a fatal violation
*/
#define SNVS_HPSVCR_LPSV_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVCR_LPSV_CFG_SHIFT)) & SNVS_HPSVCR_LPSV_CFG_MASK)
/*! @} */
/*! @name HPSR - SNVS_HP Status Register */
/*! @{ */
#define SNVS_HPSR_HPTA_MASK (0x1U)
#define SNVS_HPSR_HPTA_SHIFT (0U)
/*! HPTA
* 0b0..No time alarm interrupt occurred.
* 0b1..A time alarm interrupt occurred.
*/
#define SNVS_HPSR_HPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_HPTA_SHIFT)) & SNVS_HPSR_HPTA_MASK)
#define SNVS_HPSR_PI_MASK (0x2U)
#define SNVS_HPSR_PI_SHIFT (1U)
/*! PI
* 0b0..No periodic interrupt occurred.
* 0b1..A periodic interrupt occurred.
*/
#define SNVS_HPSR_PI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_PI_SHIFT)) & SNVS_HPSR_PI_MASK)
#define SNVS_HPSR_LPDIS_MASK (0x10U)
#define SNVS_HPSR_LPDIS_SHIFT (4U)
#define SNVS_HPSR_LPDIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_LPDIS_SHIFT)) & SNVS_HPSR_LPDIS_MASK)
#define SNVS_HPSR_BTN_MASK (0x40U)
#define SNVS_HPSR_BTN_SHIFT (6U)
#define SNVS_HPSR_BTN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BTN_SHIFT)) & SNVS_HPSR_BTN_MASK)
#define SNVS_HPSR_BI_MASK (0x80U)
#define SNVS_HPSR_BI_SHIFT (7U)
#define SNVS_HPSR_BI(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_BI_SHIFT)) & SNVS_HPSR_BI_MASK)
#define SNVS_HPSR_SSM_STATE_MASK (0xF00U)
#define SNVS_HPSR_SSM_STATE_SHIFT (8U)
/*! SSM_STATE
* 0b0000..Init
* 0b0001..Hard Fail
* 0b0011..Soft Fail
* 0b1000..Init Intermediate (transition state between Init and Check - SSM stays in this state only one clock cycle)
* 0b1001..Check
* 0b1011..Non-Secure
* 0b1101..Trusted
* 0b1111..Secure
*/
#define SNVS_HPSR_SSM_STATE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SSM_STATE_SHIFT)) & SNVS_HPSR_SSM_STATE_MASK)
#define SNVS_HPSR_SYS_SECURITY_CFG_MASK (0x7000U)
#define SNVS_HPSR_SYS_SECURITY_CFG_SHIFT (12U)
/*! SYS_SECURITY_CFG
* 0b000..Fab Configuration - the default configuration of newly fabricated chips
* 0b001..Open Configuration - the configuration after NXP-programmable fuses have been blown
* 0b011..Closed Configuration - the configuration after OEM-programmable fuses have been blown
* 0b111..Field Return Configuration - the configuration of chips that are returned to NXP for analysis
*/
#define SNVS_HPSR_SYS_SECURITY_CFG(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURITY_CFG_SHIFT)) & SNVS_HPSR_SYS_SECURITY_CFG_MASK)
#define SNVS_HPSR_SYS_SECURE_BOOT_MASK (0x8000U)
#define SNVS_HPSR_SYS_SECURE_BOOT_SHIFT (15U)
#define SNVS_HPSR_SYS_SECURE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_SYS_SECURE_BOOT_SHIFT)) & SNVS_HPSR_SYS_SECURE_BOOT_MASK)
#define SNVS_HPSR_OTPMK_ZERO_MASK (0x8000000U)
#define SNVS_HPSR_OTPMK_ZERO_SHIFT (27U)
/*! OTPMK_ZERO
* 0b0..The OTPMK is not zero.
* 0b1..The OTPMK is zero.
*/
#define SNVS_HPSR_OTPMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_OTPMK_ZERO_SHIFT)) & SNVS_HPSR_OTPMK_ZERO_MASK)
#define SNVS_HPSR_ZMK_ZERO_MASK (0x80000000U)
#define SNVS_HPSR_ZMK_ZERO_SHIFT (31U)
/*! ZMK_ZERO
* 0b0..The ZMK is not zero.
* 0b1..The ZMK is zero.
*/
#define SNVS_HPSR_ZMK_ZERO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSR_ZMK_ZERO_SHIFT)) & SNVS_HPSR_ZMK_ZERO_MASK)
/*! @} */
/*! @name HPSVSR - SNVS_HP Security Violation Status Register */
/*! @{ */
#define SNVS_HPSVSR_CAAM_MASK (0x1U)
#define SNVS_HPSVSR_CAAM_SHIFT (0U)
/*! CAAM
* 0b0..No CAAM Security Violation security violation was detected.
* 0b1..CAAM Security Violation security violation was detected.
*/
#define SNVS_HPSVSR_CAAM(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_CAAM_SHIFT)) & SNVS_HPSVSR_CAAM_MASK)
#define SNVS_HPSVSR_JTAGC_MASK (0x2U)
#define SNVS_HPSVSR_JTAGC_SHIFT (1U)
/*! JTAGC
* 0b0..No JTAG Active security violation was detected.
* 0b1..JTAG Active security violation was detected.
*/
#define SNVS_HPSVSR_JTAGC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_JTAGC_SHIFT)) & SNVS_HPSVSR_JTAGC_MASK)
#define SNVS_HPSVSR_WDOG2_MASK (0x4U)
#define SNVS_HPSVSR_WDOG2_SHIFT (2U)
/*! WDOG2
* 0b0..No Watchdog 2 Reset security violation was detected.
* 0b1..Watchdog 2 Reset security violation was detected.
*/
#define SNVS_HPSVSR_WDOG2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_WDOG2_SHIFT)) & SNVS_HPSVSR_WDOG2_MASK)
#define SNVS_HPSVSR_SRC_MASK (0x10U)
#define SNVS_HPSVSR_SRC_SHIFT (4U)
/*! SRC
* 0b0..No Internal Boot security violation was detected.
* 0b1..Internal Boot security violation was detected.
*/
#define SNVS_HPSVSR_SRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SRC_SHIFT)) & SNVS_HPSVSR_SRC_MASK)
#define SNVS_HPSVSR_OCOTP_MASK (0x20U)
#define SNVS_HPSVSR_OCOTP_SHIFT (5U)
/*! OCOTP
* 0b0..No OCOTP attack error security violation was detected.
* 0b1..OCOTP attack error security violation was detected.
*/
#define SNVS_HPSVSR_OCOTP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_OCOTP_SHIFT)) & SNVS_HPSVSR_OCOTP_MASK)
#define SNVS_HPSVSR_SW_SV_MASK (0x2000U)
#define SNVS_HPSVSR_SW_SV_SHIFT (13U)
#define SNVS_HPSVSR_SW_SV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_SV_SHIFT)) & SNVS_HPSVSR_SW_SV_MASK)
#define SNVS_HPSVSR_SW_FSV_MASK (0x4000U)
#define SNVS_HPSVSR_SW_FSV_SHIFT (14U)
#define SNVS_HPSVSR_SW_FSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_FSV_SHIFT)) & SNVS_HPSVSR_SW_FSV_MASK)
#define SNVS_HPSVSR_SW_LPSV_MASK (0x8000U)
#define SNVS_HPSVSR_SW_LPSV_SHIFT (15U)
#define SNVS_HPSVSR_SW_LPSV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_SW_LPSV_SHIFT)) & SNVS_HPSVSR_SW_LPSV_MASK)
#define SNVS_HPSVSR_ZMK_SYNDROME_MASK (0x1FF0000U)
#define SNVS_HPSVSR_ZMK_SYNDROME_SHIFT (16U)
#define SNVS_HPSVSR_ZMK_SYNDROME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_SYNDROME_SHIFT)) & SNVS_HPSVSR_ZMK_SYNDROME_MASK)
#define SNVS_HPSVSR_ZMK_ECC_FAIL_MASK (0x8000000U)
#define SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT (27U)
/*! ZMK_ECC_FAIL
* 0b0..ZMK ECC Failure was not detected.
* 0b1..ZMK ECC Failure was detected.
*/
#define SNVS_HPSVSR_ZMK_ECC_FAIL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_ZMK_ECC_FAIL_SHIFT)) & SNVS_HPSVSR_ZMK_ECC_FAIL_MASK)
#define SNVS_HPSVSR_LP_SEC_VIO_MASK (0x80000000U)
#define SNVS_HPSVSR_LP_SEC_VIO_SHIFT (31U)
#define SNVS_HPSVSR_LP_SEC_VIO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPSVSR_LP_SEC_VIO_SHIFT)) & SNVS_HPSVSR_LP_SEC_VIO_MASK)
/*! @} */
/*! @name HPHACIVR - SNVS_HP High Assurance Counter IV Register */
/*! @{ */
#define SNVS_HPHACIVR_HAC_COUNTER_IV_MASK (0xFFFFFFFFU)
#define SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT (0U)
#define SNVS_HPHACIVR_HAC_COUNTER_IV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACIVR_HAC_COUNTER_IV_SHIFT)) & SNVS_HPHACIVR_HAC_COUNTER_IV_MASK)
/*! @} */
/*! @name HPHACR - SNVS_HP High Assurance Counter Register */
/*! @{ */
#define SNVS_HPHACR_HAC_COUNTER_MASK (0xFFFFFFFFU)
#define SNVS_HPHACR_HAC_COUNTER_SHIFT (0U)
#define SNVS_HPHACR_HAC_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPHACR_HAC_COUNTER_SHIFT)) & SNVS_HPHACR_HAC_COUNTER_MASK)
/*! @} */
/*! @name HPRTCMR - SNVS_HP Real Time Counter MSB Register */
/*! @{ */
#define SNVS_HPRTCMR_RTC_MASK (0x7FFFU)
#define SNVS_HPRTCMR_RTC_SHIFT (0U)
#define SNVS_HPRTCMR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCMR_RTC_SHIFT)) & SNVS_HPRTCMR_RTC_MASK)
/*! @} */
/*! @name HPRTCLR - SNVS_HP Real Time Counter LSB Register */
/*! @{ */
#define SNVS_HPRTCLR_RTC_MASK (0xFFFFFFFFU)
#define SNVS_HPRTCLR_RTC_SHIFT (0U)
#define SNVS_HPRTCLR_RTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPRTCLR_RTC_SHIFT)) & SNVS_HPRTCLR_RTC_MASK)
/*! @} */
/*! @name HPTAMR - SNVS_HP Time Alarm MSB Register */
/*! @{ */
#define SNVS_HPTAMR_HPTA_MS_MASK (0x7FFFU)
#define SNVS_HPTAMR_HPTA_MS_SHIFT (0U)
#define SNVS_HPTAMR_HPTA_MS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTAMR_HPTA_MS_SHIFT)) & SNVS_HPTAMR_HPTA_MS_MASK)
/*! @} */
/*! @name HPTALR - SNVS_HP Time Alarm LSB Register */
/*! @{ */
#define SNVS_HPTALR_HPTA_LS_MASK (0xFFFFFFFFU)
#define SNVS_HPTALR_HPTA_LS_SHIFT (0U)
#define SNVS_HPTALR_HPTA_LS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPTALR_HPTA_LS_SHIFT)) & SNVS_HPTALR_HPTA_LS_MASK)
/*! @} */
/*! @name LPLR - SNVS_LP Lock Register */
/*! @{ */
#define SNVS_LPLR_ZMK_WHL_MASK (0x1U)
#define SNVS_LPLR_ZMK_WHL_SHIFT (0U)
/*! ZMK_WHL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_ZMK_WHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_WHL_SHIFT)) & SNVS_LPLR_ZMK_WHL_MASK)
#define SNVS_LPLR_ZMK_RHL_MASK (0x2U)
#define SNVS_LPLR_ZMK_RHL_SHIFT (1U)
/*! ZMK_RHL
* 0b0..Read access is allowed (only in software programming mode).
* 0b1..Read access is not allowed.
*/
#define SNVS_LPLR_ZMK_RHL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_ZMK_RHL_SHIFT)) & SNVS_LPLR_ZMK_RHL_MASK)
#define SNVS_LPLR_SRTC_HL_MASK (0x4U)
#define SNVS_LPLR_SRTC_HL_SHIFT (2U)
/*! SRTC_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_SRTC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_SRTC_HL_SHIFT)) & SNVS_LPLR_SRTC_HL_MASK)
#define SNVS_LPLR_LPCALB_HL_MASK (0x8U)
#define SNVS_LPLR_LPCALB_HL_SHIFT (3U)
/*! LPCALB_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_LPCALB_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPCALB_HL_SHIFT)) & SNVS_LPLR_LPCALB_HL_MASK)
#define SNVS_LPLR_MC_HL_MASK (0x10U)
#define SNVS_LPLR_MC_HL_SHIFT (4U)
/*! MC_HL
* 0b0..Write access (increment) is allowed.
* 0b1..Write access (increment) is not allowed.
*/
#define SNVS_LPLR_MC_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MC_HL_SHIFT)) & SNVS_LPLR_MC_HL_MASK)
#define SNVS_LPLR_GPR_HL_MASK (0x20U)
#define SNVS_LPLR_GPR_HL_SHIFT (5U)
/*! GPR_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_GPR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_GPR_HL_SHIFT)) & SNVS_LPLR_GPR_HL_MASK)
#define SNVS_LPLR_LPSVCR_HL_MASK (0x40U)
#define SNVS_LPLR_LPSVCR_HL_SHIFT (6U)
/*! LPSVCR_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_LPSVCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSVCR_HL_SHIFT)) & SNVS_LPLR_LPSVCR_HL_MASK)
#define SNVS_LPLR_LPTGFCR_HL_MASK (0x80U)
#define SNVS_LPLR_LPTGFCR_HL_SHIFT (7U)
/*! LPTGFCR_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_LPTGFCR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPTGFCR_HL_SHIFT)) & SNVS_LPLR_LPTGFCR_HL_MASK)
#define SNVS_LPLR_LPSECR_HL_MASK (0x100U)
#define SNVS_LPLR_LPSECR_HL_SHIFT (8U)
/*! LPSECR_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_LPSECR_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_LPSECR_HL_SHIFT)) & SNVS_LPLR_LPSECR_HL_MASK)
#define SNVS_LPLR_MKS_HL_MASK (0x200U)
#define SNVS_LPLR_MKS_HL_SHIFT (9U)
/*! MKS_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_MKS_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_MKS_HL_SHIFT)) & SNVS_LPLR_MKS_HL_MASK)
#define SNVS_LPLR_AT1_HL_MASK (0x1000000U)
#define SNVS_LPLR_AT1_HL_SHIFT (24U)
/*! AT1_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_AT1_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT1_HL_SHIFT)) & SNVS_LPLR_AT1_HL_MASK)
#define SNVS_LPLR_AT2_HL_MASK (0x2000000U)
#define SNVS_LPLR_AT2_HL_SHIFT (25U)
/*! AT2_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_AT2_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT2_HL_SHIFT)) & SNVS_LPLR_AT2_HL_MASK)
#define SNVS_LPLR_AT3_HL_MASK (0x4000000U)
#define SNVS_LPLR_AT3_HL_SHIFT (26U)
/*! AT3_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_AT3_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT3_HL_SHIFT)) & SNVS_LPLR_AT3_HL_MASK)
#define SNVS_LPLR_AT4_HL_MASK (0x8000000U)
#define SNVS_LPLR_AT4_HL_SHIFT (27U)
/*! AT4_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_AT4_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT4_HL_SHIFT)) & SNVS_LPLR_AT4_HL_MASK)
#define SNVS_LPLR_AT5_HL_MASK (0x10000000U)
#define SNVS_LPLR_AT5_HL_SHIFT (28U)
/*! AT5_HL
* 0b0..Write access is allowed.
* 0b1..Write access is not allowed.
*/
#define SNVS_LPLR_AT5_HL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLR_AT5_HL_SHIFT)) & SNVS_LPLR_AT5_HL_MASK)
/*! @} */
/*! @name LPCR - SNVS_LP Control Register */
/*! @{ */
#define SNVS_LPCR_SRTC_ENV_MASK (0x1U)
#define SNVS_LPCR_SRTC_ENV_SHIFT (0U)
/*! SRTC_ENV
* 0b0..SRTC is disabled or invalid.
* 0b1..SRTC is enabled and valid.
*/
#define SNVS_LPCR_SRTC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_ENV_SHIFT)) & SNVS_LPCR_SRTC_ENV_MASK)
#define SNVS_LPCR_LPTA_EN_MASK (0x2U)
#define SNVS_LPCR_LPTA_EN_SHIFT (1U)
/*! LPTA_EN
* 0b0..LP time alarm interrupt is disabled.
* 0b1..LP time alarm interrupt is enabled.
*/
#define SNVS_LPCR_LPTA_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPTA_EN_SHIFT)) & SNVS_LPCR_LPTA_EN_MASK)
#define SNVS_LPCR_MC_ENV_MASK (0x4U)
#define SNVS_LPCR_MC_ENV_SHIFT (2U)
/*! MC_ENV
* 0b0..MC is disabled or invalid.
* 0b1..MC is enabled and valid.
*/
#define SNVS_LPCR_MC_ENV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_MC_ENV_SHIFT)) & SNVS_LPCR_MC_ENV_MASK)
#define SNVS_LPCR_LPWUI_EN_MASK (0x8U)
#define SNVS_LPCR_LPWUI_EN_SHIFT (3U)
#define SNVS_LPCR_LPWUI_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPWUI_EN_SHIFT)) & SNVS_LPCR_LPWUI_EN_MASK)
#define SNVS_LPCR_SRTC_INV_EN_MASK (0x10U)
#define SNVS_LPCR_SRTC_INV_EN_SHIFT (4U)
/*! SRTC_INV_EN
* 0b0..SRTC stays valid in the case of security violation (other than a software violation (HPSVSR[SW_LPSV] = 1 or HPCOMR[SW_LPSV] = 1)).
* 0b1..SRTC is invalidated in the case of security violation.
*/
#define SNVS_LPCR_SRTC_INV_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_SRTC_INV_EN_SHIFT)) & SNVS_LPCR_SRTC_INV_EN_MASK)
#define SNVS_LPCR_DP_EN_MASK (0x20U)
#define SNVS_LPCR_DP_EN_SHIFT (5U)
/*! DP_EN
* 0b0..Smart PMIC enabled.
* 0b1..Dumb PMIC enabled.
*/
#define SNVS_LPCR_DP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DP_EN_SHIFT)) & SNVS_LPCR_DP_EN_MASK)
#define SNVS_LPCR_TOP_MASK (0x40U)
#define SNVS_LPCR_TOP_SHIFT (6U)
/*! TOP
* 0b0..Leave system power on.
* 0b1..Turn off system power.
*/
#define SNVS_LPCR_TOP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_TOP_SHIFT)) & SNVS_LPCR_TOP_MASK)
#define SNVS_LPCR_LVD_EN_MASK (0x80U)
#define SNVS_LPCR_LVD_EN_SHIFT (7U)
#define SNVS_LPCR_LVD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LVD_EN_SHIFT)) & SNVS_LPCR_LVD_EN_MASK)
#define SNVS_LPCR_LPCALB_EN_MASK (0x100U)
#define SNVS_LPCR_LPCALB_EN_SHIFT (8U)
/*! LPCALB_EN
* 0b0..SRTC Time calibration is disabled.
* 0b1..SRTC Time calibration is enabled.
*/
#define SNVS_LPCR_LPCALB_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_EN_SHIFT)) & SNVS_LPCR_LPCALB_EN_MASK)
#define SNVS_LPCR_LPCALB_VAL_MASK (0x7C00U)
#define SNVS_LPCR_LPCALB_VAL_SHIFT (10U)
/*! LPCALB_VAL
* 0b00000..+0 counts per each 32768 ticks of the counter clock
* 0b00001..+1 counts per each 32768 ticks of the counter clock
* 0b00010..+2 counts per each 32768 ticks of the counter clock
* 0b01111..+15 counts per each 32768 ticks of the counter clock
* 0b10000..-16 counts per each 32768 ticks of the counter clock
* 0b10001..-15 counts per each 32768 ticks of the counter clock
* 0b11110..-2 counts per each 32768 ticks of the counter clock
* 0b11111..-1 counts per each 32768 ticks of the counter clock
*/
#define SNVS_LPCR_LPCALB_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_LPCALB_VAL_SHIFT)) & SNVS_LPCR_LPCALB_VAL_MASK)
#define SNVS_LPCR_BTN_PRESS_TIME_MASK (0x30000U)
#define SNVS_LPCR_BTN_PRESS_TIME_SHIFT (16U)
#define SNVS_LPCR_BTN_PRESS_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_BTN_PRESS_TIME_SHIFT)) & SNVS_LPCR_BTN_PRESS_TIME_MASK)
#define SNVS_LPCR_DEBOUNCE_MASK (0xC0000U)
#define SNVS_LPCR_DEBOUNCE_SHIFT (18U)
#define SNVS_LPCR_DEBOUNCE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_DEBOUNCE_SHIFT)) & SNVS_LPCR_DEBOUNCE_MASK)
#define SNVS_LPCR_ON_TIME_MASK (0x300000U)
#define SNVS_LPCR_ON_TIME_SHIFT (20U)
#define SNVS_LPCR_ON_TIME(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_ON_TIME_SHIFT)) & SNVS_LPCR_ON_TIME_MASK)
#define SNVS_LPCR_PK_EN_MASK (0x400000U)
#define SNVS_LPCR_PK_EN_SHIFT (22U)
#define SNVS_LPCR_PK_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_EN_SHIFT)) & SNVS_LPCR_PK_EN_MASK)
#define SNVS_LPCR_PK_OVERRIDE_MASK (0x800000U)
#define SNVS_LPCR_PK_OVERRIDE_SHIFT (23U)
#define SNVS_LPCR_PK_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_PK_OVERRIDE_SHIFT)) & SNVS_LPCR_PK_OVERRIDE_MASK)
#define SNVS_LPCR_GPR_Z_DIS_MASK (0x1000000U)
#define SNVS_LPCR_GPR_Z_DIS_SHIFT (24U)
#define SNVS_LPCR_GPR_Z_DIS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPCR_GPR_Z_DIS_SHIFT)) & SNVS_LPCR_GPR_Z_DIS_MASK)
/*! @} */
/*! @name LPMKCR - SNVS_LP Master Key Control Register */
/*! @{ */
#define SNVS_LPMKCR_MASTER_KEY_SEL_MASK (0x3U)
#define SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT (0U)
/*! MASTER_KEY_SEL
* 0b0x..Select one time programmable master key.
* 0b10..Select zeroizable master key when MKS_EN bit is set .
* 0b11..Select combined master key when MKS_EN bit is set .
*/
#define SNVS_LPMKCR_MASTER_KEY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_MASTER_KEY_SEL_SHIFT)) & SNVS_LPMKCR_MASTER_KEY_SEL_MASK)
#define SNVS_LPMKCR_ZMK_HWP_MASK (0x4U)
#define SNVS_LPMKCR_ZMK_HWP_SHIFT (2U)
/*! ZMK_HWP
* 0b0..ZMK is in the software programming mode.
* 0b1..ZMK is in the hardware programming mode.
*/
#define SNVS_LPMKCR_ZMK_HWP(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_HWP_SHIFT)) & SNVS_LPMKCR_ZMK_HWP_MASK)
#define SNVS_LPMKCR_ZMK_VAL_MASK (0x8U)
#define SNVS_LPMKCR_ZMK_VAL_SHIFT (3U)
/*! ZMK_VAL
* 0b0..ZMK is not valid.
* 0b1..ZMK is valid.
*/
#define SNVS_LPMKCR_ZMK_VAL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_VAL_SHIFT)) & SNVS_LPMKCR_ZMK_VAL_MASK)
#define SNVS_LPMKCR_ZMK_ECC_EN_MASK (0x10U)
#define SNVS_LPMKCR_ZMK_ECC_EN_SHIFT (4U)
/*! ZMK_ECC_EN
* 0b0..ZMK ECC check is disabled.
* 0b1..ZMK ECC check is enabled.
*/
#define SNVS_LPMKCR_ZMK_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_EN_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_EN_MASK)
#define SNVS_LPMKCR_ZMK_ECC_VALUE_MASK (0xFF80U)
#define SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT (7U)
#define SNVS_LPMKCR_ZMK_ECC_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPMKCR_ZMK_ECC_VALUE_SHIFT)) & SNVS_LPMKCR_ZMK_ECC_VALUE_MASK)
/*! @} */
/*! @name LPSVCR - SNVS_LP Security Violation Control Register */
/*! @{ */
#define SNVS_LPSVCR_CAAM_EN_MASK (0x1U)
#define SNVS_LPSVCR_CAAM_EN_SHIFT (0U)
/*! CAAM_EN
* 0b0..CAAM Security Violation is disabled in the LP domain.
* 0b1..CAAM Security Violation is enabled in the LP domain.
*/
#define SNVS_LPSVCR_CAAM_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_CAAM_EN_SHIFT)) & SNVS_LPSVCR_CAAM_EN_MASK)
#define SNVS_LPSVCR_JTAGC_EN_MASK (0x2U)
#define SNVS_LPSVCR_JTAGC_EN_SHIFT (1U)
/*! JTAGC_EN
* 0b0..JTAG Active is disabled in the LP domain.
* 0b1..JTAG Active is enabled in the LP domain.
*/
#define SNVS_LPSVCR_JTAGC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_JTAGC_EN_SHIFT)) & SNVS_LPSVCR_JTAGC_EN_MASK)
#define SNVS_LPSVCR_WDOG2_EN_MASK (0x4U)
#define SNVS_LPSVCR_WDOG2_EN_SHIFT (2U)
/*! WDOG2_EN
* 0b0..Watchdog 2 Reset is disabled in the LP domain.
* 0b1..Watchdog 2 Reset is enabled in the LP domain.
*/
#define SNVS_LPSVCR_WDOG2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_WDOG2_EN_SHIFT)) & SNVS_LPSVCR_WDOG2_EN_MASK)
#define SNVS_LPSVCR_SRC_EN_MASK (0x10U)
#define SNVS_LPSVCR_SRC_EN_SHIFT (4U)
/*! SRC_EN
* 0b0..Internal Boot is disabled in the LP domain.
* 0b1..Internal Boot is enabled in the LP domain.
*/
#define SNVS_LPSVCR_SRC_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_SRC_EN_SHIFT)) & SNVS_LPSVCR_SRC_EN_MASK)
#define SNVS_LPSVCR_OCOTP_EN_MASK (0x20U)
#define SNVS_LPSVCR_OCOTP_EN_SHIFT (5U)
/*! OCOTP_EN
* 0b0..OCOTP attack error is disabled in the LP domain.
* 0b1..OCOTP attack error is enabled in the LP domain.
*/
#define SNVS_LPSVCR_OCOTP_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSVCR_OCOTP_EN_SHIFT)) & SNVS_LPSVCR_OCOTP_EN_MASK)
/*! @} */
/*! @name LPTGFCR - SNVS_LP Tamper Glitch Filters Configuration Register */
/*! @{ */
#define SNVS_LPTGFCR_WMTGF_MASK (0x1FU)
#define SNVS_LPTGFCR_WMTGF_SHIFT (0U)
#define SNVS_LPTGFCR_WMTGF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_SHIFT)) & SNVS_LPTGFCR_WMTGF_MASK)
#define SNVS_LPTGFCR_WMTGF_EN_MASK (0x80U)
#define SNVS_LPTGFCR_WMTGF_EN_SHIFT (7U)
/*! WMTGF_EN
* 0b0..Wire-mesh tamper glitch filter is bypassed.
* 0b1..Wire-mesh tamper glitch filter is enabled.
*/
#define SNVS_LPTGFCR_WMTGF_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_WMTGF_EN_SHIFT)) & SNVS_LPTGFCR_WMTGF_EN_MASK)
#define SNVS_LPTGFCR_ETGF1_MASK (0x7F0000U)
#define SNVS_LPTGFCR_ETGF1_SHIFT (16U)
#define SNVS_LPTGFCR_ETGF1(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_SHIFT)) & SNVS_LPTGFCR_ETGF1_MASK)
#define SNVS_LPTGFCR_ETGF1_EN_MASK (0x800000U)
#define SNVS_LPTGFCR_ETGF1_EN_SHIFT (23U)
/*! ETGF1_EN
* 0b0..External tamper glitch filter 1 is bypassed.
* 0b1..External tamper glitch filter 1 is enabled.
*/
#define SNVS_LPTGFCR_ETGF1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF1_EN_SHIFT)) & SNVS_LPTGFCR_ETGF1_EN_MASK)
#define SNVS_LPTGFCR_ETGF2_MASK (0x7F000000U)
#define SNVS_LPTGFCR_ETGF2_SHIFT (24U)
#define SNVS_LPTGFCR_ETGF2(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_SHIFT)) & SNVS_LPTGFCR_ETGF2_MASK)
#define SNVS_LPTGFCR_ETGF2_EN_MASK (0x80000000U)
#define SNVS_LPTGFCR_ETGF2_EN_SHIFT (31U)
/*! ETGF2_EN
* 0b0..External tamper glitch filter 2 is bypassed.
* 0b1..External tamper glitch filter 2 is enabled.
*/
#define SNVS_LPTGFCR_ETGF2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGFCR_ETGF2_EN_SHIFT)) & SNVS_LPTGFCR_ETGF2_EN_MASK)
/*! @} */
/*! @name LPTDCR - SNVS_LP Tamper Detect Configuration Register */
/*! @{ */
#define SNVS_LPTDCR_SRTCR_EN_MASK (0x2U)
#define SNVS_LPTDCR_SRTCR_EN_SHIFT (1U)
/*! SRTCR_EN
* 0b0..SRTC rollover is disabled.
* 0b1..SRTC rollover is enabled.
*/
#define SNVS_LPTDCR_SRTCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_SRTCR_EN_SHIFT)) & SNVS_LPTDCR_SRTCR_EN_MASK)
#define SNVS_LPTDCR_MCR_EN_MASK (0x4U)
#define SNVS_LPTDCR_MCR_EN_SHIFT (2U)
/*! MCR_EN
* 0b0..MC rollover is disabled.
* 0b1..MC rollover is enabled.
*/
#define SNVS_LPTDCR_MCR_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_MCR_EN_SHIFT)) & SNVS_LPTDCR_MCR_EN_MASK)
#define SNVS_LPTDCR_CT_EN_MASK (0x10U)
#define SNVS_LPTDCR_CT_EN_SHIFT (4U)
/*! CT_EN
* 0b0..Clock tamper is disabled.
* 0b1..Clock tamper is enabled.
*/
#define SNVS_LPTDCR_CT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_CT_EN_SHIFT)) & SNVS_LPTDCR_CT_EN_MASK)
#define SNVS_LPTDCR_TT_EN_MASK (0x20U)
#define SNVS_LPTDCR_TT_EN_SHIFT (5U)
/*! TT_EN
* 0b0..Temperature tamper is disabled.
* 0b1..Temperature tamper is enabled.
*/
#define SNVS_LPTDCR_TT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_TT_EN_SHIFT)) & SNVS_LPTDCR_TT_EN_MASK)
#define SNVS_LPTDCR_VT_EN_MASK (0x40U)
#define SNVS_LPTDCR_VT_EN_SHIFT (6U)
/*! VT_EN
* 0b0..Voltage tamper is disabled.
* 0b1..Voltage tamper is enabled.
*/
#define SNVS_LPTDCR_VT_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VT_EN_SHIFT)) & SNVS_LPTDCR_VT_EN_MASK)
#define SNVS_LPTDCR_WMT1_EN_MASK (0x80U)
#define SNVS_LPTDCR_WMT1_EN_SHIFT (7U)
/*! WMT1_EN
* 0b0..Wire-mesh tamper 1 is disabled.
* 0b1..Wire-mesh tamper 1 is enabled.
*/
#define SNVS_LPTDCR_WMT1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT1_EN_SHIFT)) & SNVS_LPTDCR_WMT1_EN_MASK)
#define SNVS_LPTDCR_WMT2_EN_MASK (0x100U)
#define SNVS_LPTDCR_WMT2_EN_SHIFT (8U)
/*! WMT2_EN
* 0b0..Wire-mesh tamper 2 is disabled.
* 0b1..Wire-mesh tamper 2 is enabled.
*/
#define SNVS_LPTDCR_WMT2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_WMT2_EN_SHIFT)) & SNVS_LPTDCR_WMT2_EN_MASK)
#define SNVS_LPTDCR_ET1_EN_MASK (0x200U)
#define SNVS_LPTDCR_ET1_EN_SHIFT (9U)
/*! ET1_EN
* 0b0..External tamper 1 is disabled.
* 0b1..External tamper 1 is enabled.
*/
#define SNVS_LPTDCR_ET1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1_EN_SHIFT)) & SNVS_LPTDCR_ET1_EN_MASK)
#define SNVS_LPTDCR_ET2_EN_MASK (0x400U)
#define SNVS_LPTDCR_ET2_EN_SHIFT (10U)
/*! ET2_EN
* 0b0..External tamper 2 is disabled.
* 0b1..External tamper 2 is enabled.
*/
#define SNVS_LPTDCR_ET2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2_EN_SHIFT)) & SNVS_LPTDCR_ET2_EN_MASK)
#define SNVS_LPTDCR_ET1P_MASK (0x800U)
#define SNVS_LPTDCR_ET1P_SHIFT (11U)
/*! ET1P
* 0b0..External tamper 1 is active low.
* 0b1..External tamper 1 is active high.
*/
#define SNVS_LPTDCR_ET1P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET1P_SHIFT)) & SNVS_LPTDCR_ET1P_MASK)
#define SNVS_LPTDCR_ET2P_MASK (0x1000U)
#define SNVS_LPTDCR_ET2P_SHIFT (12U)
/*! ET2P
* 0b0..External tamper 2 is active low.
* 0b1..External tamper 2 is active high.
*/
#define SNVS_LPTDCR_ET2P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_ET2P_SHIFT)) & SNVS_LPTDCR_ET2P_MASK)
#define SNVS_LPTDCR_PFD_OBSERV_MASK (0x4000U)
#define SNVS_LPTDCR_PFD_OBSERV_SHIFT (14U)
#define SNVS_LPTDCR_PFD_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_PFD_OBSERV_SHIFT)) & SNVS_LPTDCR_PFD_OBSERV_MASK)
#define SNVS_LPTDCR_POR_OBSERV_MASK (0x8000U)
#define SNVS_LPTDCR_POR_OBSERV_SHIFT (15U)
#define SNVS_LPTDCR_POR_OBSERV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_POR_OBSERV_SHIFT)) & SNVS_LPTDCR_POR_OBSERV_MASK)
#define SNVS_LPTDCR_LTDC_MASK (0x70000U)
#define SNVS_LPTDCR_LTDC_SHIFT (16U)
#define SNVS_LPTDCR_LTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_LTDC_SHIFT)) & SNVS_LPTDCR_LTDC_MASK)
#define SNVS_LPTDCR_HTDC_MASK (0x700000U)
#define SNVS_LPTDCR_HTDC_SHIFT (20U)
#define SNVS_LPTDCR_HTDC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_HTDC_SHIFT)) & SNVS_LPTDCR_HTDC_MASK)
#define SNVS_LPTDCR_VRC_MASK (0x7000000U)
#define SNVS_LPTDCR_VRC_SHIFT (24U)
#define SNVS_LPTDCR_VRC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_VRC_SHIFT)) & SNVS_LPTDCR_VRC_MASK)
#define SNVS_LPTDCR_OSCB_MASK (0x10000000U)
#define SNVS_LPTDCR_OSCB_SHIFT (28U)
/*! OSCB
* 0b0..Normal SRTC clock oscillator not bypassed.
* 0b1..Normal SRTC clock oscillator bypassed. Alternate clock can drive the SRTC clock source.
*/
#define SNVS_LPTDCR_OSCB(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDCR_OSCB_SHIFT)) & SNVS_LPTDCR_OSCB_MASK)
/*! @} */
/*! @name LPSR - SNVS_LP Status Register */
/*! @{ */
#define SNVS_LPSR_LPTA_MASK (0x1U)
#define SNVS_LPSR_LPTA_SHIFT (0U)
/*! LPTA
* 0b0..No time alarm interrupt occurred.
* 0b1..A time alarm interrupt occurred.
*/
#define SNVS_LPSR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPTA_SHIFT)) & SNVS_LPSR_LPTA_MASK)
#define SNVS_LPSR_SRTCR_MASK (0x2U)
#define SNVS_LPSR_SRTCR_SHIFT (1U)
/*! SRTCR
* 0b0..SRTC has not reached its maximum value.
* 0b1..SRTC has reached its maximum value.
*/
#define SNVS_LPSR_SRTCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SRTCR_SHIFT)) & SNVS_LPSR_SRTCR_MASK)
#define SNVS_LPSR_MCR_MASK (0x4U)
#define SNVS_LPSR_MCR_SHIFT (2U)
/*! MCR
* 0b0..MC has not reached its maximum value.
* 0b1..MC has reached its maximum value.
*/
#define SNVS_LPSR_MCR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_MCR_SHIFT)) & SNVS_LPSR_MCR_MASK)
#define SNVS_LPSR_LVD_MASK (0x8U)
#define SNVS_LPSR_LVD_SHIFT (3U)
/*! LVD
* 0b0..No low voltage event detected.
* 0b1..Low voltage event is detected.
*/
#define SNVS_LPSR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LVD_SHIFT)) & SNVS_LPSR_LVD_MASK)
#define SNVS_LPSR_CTD_MASK (0x10U)
#define SNVS_LPSR_CTD_SHIFT (4U)
/*! CTD
* 0b0..No clock tamper.
* 0b1..Clock tamper is detected.
*/
#define SNVS_LPSR_CTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_CTD_SHIFT)) & SNVS_LPSR_CTD_MASK)
#define SNVS_LPSR_TTD_MASK (0x20U)
#define SNVS_LPSR_TTD_SHIFT (5U)
/*! TTD
* 0b0..No temperature tamper.
* 0b1..Temperature tamper is detected.
*/
#define SNVS_LPSR_TTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_TTD_SHIFT)) & SNVS_LPSR_TTD_MASK)
#define SNVS_LPSR_VTD_MASK (0x40U)
#define SNVS_LPSR_VTD_SHIFT (6U)
/*! VTD
* 0b0..Voltage tampering not detected.
* 0b1..Voltage tampering detected.
*/
#define SNVS_LPSR_VTD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_VTD_SHIFT)) & SNVS_LPSR_VTD_MASK)
#define SNVS_LPSR_WMT1D_MASK (0x80U)
#define SNVS_LPSR_WMT1D_SHIFT (7U)
/*! WMT1D
* 0b0..Wire-mesh tampering 1 not detected.
* 0b1..Wire-mesh tampering 1 detected.
*/
#define SNVS_LPSR_WMT1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT1D_SHIFT)) & SNVS_LPSR_WMT1D_MASK)
#define SNVS_LPSR_WMT2D_MASK (0x100U)
#define SNVS_LPSR_WMT2D_SHIFT (8U)
/*! WMT2D
* 0b0..Wire-mesh tampering 2 not detected.
* 0b1..Wire-mesh tampering 2 detected.
*/
#define SNVS_LPSR_WMT2D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_WMT2D_SHIFT)) & SNVS_LPSR_WMT2D_MASK)
#define SNVS_LPSR_ET1D_MASK (0x200U)
#define SNVS_LPSR_ET1D_SHIFT (9U)
/*! ET1D
* 0b0..External tampering 1 not detected.
* 0b1..External tampering 1 detected.
*/
#define SNVS_LPSR_ET1D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET1D_SHIFT)) & SNVS_LPSR_ET1D_MASK)
#define SNVS_LPSR_ET2D_MASK (0x400U)
#define SNVS_LPSR_ET2D_SHIFT (10U)
/*! ET2D
* 0b0..External tampering 2 not detected.
* 0b1..External tampering 2 detected.
*/
#define SNVS_LPSR_ET2D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ET2D_SHIFT)) & SNVS_LPSR_ET2D_MASK)
#define SNVS_LPSR_ESVD_MASK (0x10000U)
#define SNVS_LPSR_ESVD_SHIFT (16U)
/*! ESVD
* 0b0..No external security violation.
* 0b1..External security violation is detected.
*/
#define SNVS_LPSR_ESVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_ESVD_SHIFT)) & SNVS_LPSR_ESVD_MASK)
#define SNVS_LPSR_EO_MASK (0x20000U)
#define SNVS_LPSR_EO_SHIFT (17U)
/*! EO
* 0b0..Emergency off was not detected.
* 0b1..Emergency off was detected.
*/
#define SNVS_LPSR_EO(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_EO_SHIFT)) & SNVS_LPSR_EO_MASK)
#define SNVS_LPSR_SPOF_MASK (0x40000U)
#define SNVS_LPSR_SPOF_SHIFT (18U)
/*! SPOF
* 0b0..Set Power Off was not detected.
* 0b1..Set Power Off was detected.
*/
#define SNVS_LPSR_SPOF(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_SPOF_SHIFT)) & SNVS_LPSR_SPOF_MASK)
#define SNVS_LPSR_LPNS_MASK (0x40000000U)
#define SNVS_LPSR_LPNS_SHIFT (30U)
/*! LPNS
* 0b0..LP section was not programmed in the non-secure state.
* 0b1..LP section was programmed in the non-secure state.
*/
#define SNVS_LPSR_LPNS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPNS_SHIFT)) & SNVS_LPSR_LPNS_MASK)
#define SNVS_LPSR_LPS_MASK (0x80000000U)
#define SNVS_LPSR_LPS_SHIFT (31U)
/*! LPS
* 0b0..LP section was not programmed in secure or trusted state.
* 0b1..LP section was programmed in secure or trusted state.
*/
#define SNVS_LPSR_LPS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSR_LPS_SHIFT)) & SNVS_LPSR_LPS_MASK)
/*! @} */
/*! @name LPSRTCMR - SNVS_LP Secure Real Time Counter MSB Register */
/*! @{ */
#define SNVS_LPSRTCMR_SRTC_MASK (0x7FFFU)
#define SNVS_LPSRTCMR_SRTC_SHIFT (0U)
#define SNVS_LPSRTCMR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCMR_SRTC_SHIFT)) & SNVS_LPSRTCMR_SRTC_MASK)
/*! @} */
/*! @name LPSRTCLR - SNVS_LP Secure Real Time Counter LSB Register */
/*! @{ */
#define SNVS_LPSRTCLR_SRTC_MASK (0xFFFFFFFFU)
#define SNVS_LPSRTCLR_SRTC_SHIFT (0U)
#define SNVS_LPSRTCLR_SRTC(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSRTCLR_SRTC_SHIFT)) & SNVS_LPSRTCLR_SRTC_MASK)
/*! @} */
/*! @name LPTAR - SNVS_LP Time Alarm Register */
/*! @{ */
#define SNVS_LPTAR_LPTA_MASK (0xFFFFFFFFU)
#define SNVS_LPTAR_LPTA_SHIFT (0U)
#define SNVS_LPTAR_LPTA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTAR_LPTA_SHIFT)) & SNVS_LPTAR_LPTA_MASK)
/*! @} */
/*! @name LPSMCMR - SNVS_LP Secure Monotonic Counter MSB Register */
/*! @{ */
#define SNVS_LPSMCMR_MON_COUNTER_MASK (0xFFFFU)
#define SNVS_LPSMCMR_MON_COUNTER_SHIFT (0U)
#define SNVS_LPSMCMR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MON_COUNTER_SHIFT)) & SNVS_LPSMCMR_MON_COUNTER_MASK)
#define SNVS_LPSMCMR_MC_ERA_BITS_MASK (0xFFFF0000U)
#define SNVS_LPSMCMR_MC_ERA_BITS_SHIFT (16U)
#define SNVS_LPSMCMR_MC_ERA_BITS(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCMR_MC_ERA_BITS_SHIFT)) & SNVS_LPSMCMR_MC_ERA_BITS_MASK)
/*! @} */
/*! @name LPSMCLR - SNVS_LP Secure Monotonic Counter LSB Register */
/*! @{ */
#define SNVS_LPSMCLR_MON_COUNTER_MASK (0xFFFFFFFFU)
#define SNVS_LPSMCLR_MON_COUNTER_SHIFT (0U)
#define SNVS_LPSMCLR_MON_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPSMCLR_MON_COUNTER_SHIFT)) & SNVS_LPSMCLR_MON_COUNTER_MASK)
/*! @} */
/*! @name LPLVDR - SNVS_LP Digital Low-Voltage Detector Register */
/*! @{ */
#define SNVS_LPLVDR_LVD_MASK (0xFFFFFFFFU)
#define SNVS_LPLVDR_LVD_SHIFT (0U)
#define SNVS_LPLVDR_LVD(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPLVDR_LVD_SHIFT)) & SNVS_LPLVDR_LVD_MASK)
/*! @} */
/*! @name LPGPR0_LEGACY_ALIAS - SNVS_LP General Purpose Register 0 (legacy alias) */
/*! @{ */
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK (0xFFFFFFFFU)
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT (0U)
#define SNVS_LPGPR0_LEGACY_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR0_LEGACY_ALIAS_GPR_SHIFT)) & SNVS_LPGPR0_LEGACY_ALIAS_GPR_MASK)
/*! @} */
/*! @name LPZMKR - SNVS_LP Zeroizable Master Key Register */
/*! @{ */
#define SNVS_LPZMKR_ZMK_MASK (0xFFFFFFFFU)
#define SNVS_LPZMKR_ZMK_SHIFT (0U)
#define SNVS_LPZMKR_ZMK(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPZMKR_ZMK_SHIFT)) & SNVS_LPZMKR_ZMK_MASK)
/*! @} */
/* The count of SNVS_LPZMKR */
#define SNVS_LPZMKR_COUNT (8U)
/*! @name LPGPR_ALIAS - SNVS_LP General Purpose Registers 0 .. 3 */
/*! @{ */
#define SNVS_LPGPR_ALIAS_GPR_MASK (0xFFFFFFFFU)
#define SNVS_LPGPR_ALIAS_GPR_SHIFT (0U)
#define SNVS_LPGPR_ALIAS_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_ALIAS_GPR_SHIFT)) & SNVS_LPGPR_ALIAS_GPR_MASK)
/*! @} */
/* The count of SNVS_LPGPR_ALIAS */
#define SNVS_LPGPR_ALIAS_COUNT (4U)
/*! @name LPTDC2R - SNVS_LP Tamper Detectors Config 2 Register */
/*! @{ */
#define SNVS_LPTDC2R_ET3_EN_MASK (0x1U)
#define SNVS_LPTDC2R_ET3_EN_SHIFT (0U)
/*! ET3_EN
* 0b0..External tamper 3 is disabled.
* 0b1..External tamper 3 is enabled.
*/
#define SNVS_LPTDC2R_ET3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3_EN_SHIFT)) & SNVS_LPTDC2R_ET3_EN_MASK)
#define SNVS_LPTDC2R_ET4_EN_MASK (0x2U)
#define SNVS_LPTDC2R_ET4_EN_SHIFT (1U)
/*! ET4_EN
* 0b0..External tamper 4 is disabled.
* 0b1..External tamper 4 is enabled.
*/
#define SNVS_LPTDC2R_ET4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4_EN_SHIFT)) & SNVS_LPTDC2R_ET4_EN_MASK)
#define SNVS_LPTDC2R_ET5_EN_MASK (0x4U)
#define SNVS_LPTDC2R_ET5_EN_SHIFT (2U)
/*! ET5_EN
* 0b0..External tamper 5 is disabled.
* 0b1..External tamper 5 is enabled.
*/
#define SNVS_LPTDC2R_ET5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5_EN_SHIFT)) & SNVS_LPTDC2R_ET5_EN_MASK)
#define SNVS_LPTDC2R_ET6_EN_MASK (0x8U)
#define SNVS_LPTDC2R_ET6_EN_SHIFT (3U)
/*! ET6_EN
* 0b0..External tamper 6 is disabled.
* 0b1..External tamper 6 is enabled.
*/
#define SNVS_LPTDC2R_ET6_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6_EN_SHIFT)) & SNVS_LPTDC2R_ET6_EN_MASK)
#define SNVS_LPTDC2R_ET7_EN_MASK (0x10U)
#define SNVS_LPTDC2R_ET7_EN_SHIFT (4U)
/*! ET7_EN
* 0b0..External tamper 7 is disabled.
* 0b1..External tamper 7 is enabled.
*/
#define SNVS_LPTDC2R_ET7_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7_EN_SHIFT)) & SNVS_LPTDC2R_ET7_EN_MASK)
#define SNVS_LPTDC2R_ET8_EN_MASK (0x20U)
#define SNVS_LPTDC2R_ET8_EN_SHIFT (5U)
/*! ET8_EN
* 0b0..External tamper 8 is disabled.
* 0b1..External tamper 8 is enabled.
*/
#define SNVS_LPTDC2R_ET8_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8_EN_SHIFT)) & SNVS_LPTDC2R_ET8_EN_MASK)
#define SNVS_LPTDC2R_ET9_EN_MASK (0x40U)
#define SNVS_LPTDC2R_ET9_EN_SHIFT (6U)
/*! ET9_EN
* 0b0..External tamper 9 is disabled.
* 0b1..External tamper 9 is enabled.
*/
#define SNVS_LPTDC2R_ET9_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9_EN_SHIFT)) & SNVS_LPTDC2R_ET9_EN_MASK)
#define SNVS_LPTDC2R_ET10_EN_MASK (0x80U)
#define SNVS_LPTDC2R_ET10_EN_SHIFT (7U)
/*! ET10_EN
* 0b0..External tamper 10 is disabled.
* 0b1..External tamper 10 is enabled.
*/
#define SNVS_LPTDC2R_ET10_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10_EN_SHIFT)) & SNVS_LPTDC2R_ET10_EN_MASK)
#define SNVS_LPTDC2R_ET3P_MASK (0x10000U)
#define SNVS_LPTDC2R_ET3P_SHIFT (16U)
/*! ET3P
* 0b0..External tamper 3 active low.
* 0b1..External tamper 3 active high.
*/
#define SNVS_LPTDC2R_ET3P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET3P_SHIFT)) & SNVS_LPTDC2R_ET3P_MASK)
#define SNVS_LPTDC2R_ET4P_MASK (0x20000U)
#define SNVS_LPTDC2R_ET4P_SHIFT (17U)
/*! ET4P
* 0b0..External tamper 4 is active low.
* 0b1..External tamper 4 is active high.
*/
#define SNVS_LPTDC2R_ET4P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET4P_SHIFT)) & SNVS_LPTDC2R_ET4P_MASK)
#define SNVS_LPTDC2R_ET5P_MASK (0x40000U)
#define SNVS_LPTDC2R_ET5P_SHIFT (18U)
/*! ET5P
* 0b0..External tamper 5 is active low.
* 0b1..External tamper 5 is active high.
*/
#define SNVS_LPTDC2R_ET5P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET5P_SHIFT)) & SNVS_LPTDC2R_ET5P_MASK)
#define SNVS_LPTDC2R_ET6P_MASK (0x80000U)
#define SNVS_LPTDC2R_ET6P_SHIFT (19U)
/*! ET6P
* 0b0..External tamper 6 is active low.
* 0b1..External tamper 6 is active high.
*/
#define SNVS_LPTDC2R_ET6P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET6P_SHIFT)) & SNVS_LPTDC2R_ET6P_MASK)
#define SNVS_LPTDC2R_ET7P_MASK (0x100000U)
#define SNVS_LPTDC2R_ET7P_SHIFT (20U)
/*! ET7P
* 0b0..External tamper 7 is active low.
* 0b1..External tamper 7 is active high.
*/
#define SNVS_LPTDC2R_ET7P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET7P_SHIFT)) & SNVS_LPTDC2R_ET7P_MASK)
#define SNVS_LPTDC2R_ET8P_MASK (0x200000U)
#define SNVS_LPTDC2R_ET8P_SHIFT (21U)
/*! ET8P
* 0b0..External tamper 8 is active low.
* 0b1..External tamper 8 is active high.
*/
#define SNVS_LPTDC2R_ET8P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET8P_SHIFT)) & SNVS_LPTDC2R_ET8P_MASK)
#define SNVS_LPTDC2R_ET9P_MASK (0x400000U)
#define SNVS_LPTDC2R_ET9P_SHIFT (22U)
/*! ET9P
* 0b0..External tamper 9 is active low.
* 0b1..External tamper 9 is active high.
*/
#define SNVS_LPTDC2R_ET9P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET9P_SHIFT)) & SNVS_LPTDC2R_ET9P_MASK)
#define SNVS_LPTDC2R_ET10P_MASK (0x800000U)
#define SNVS_LPTDC2R_ET10P_SHIFT (23U)
/*! ET10P
* 0b0..External tamper 10 is active low.
* 0b1..External tamper 10 is active high.
*/
#define SNVS_LPTDC2R_ET10P(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDC2R_ET10P_SHIFT)) & SNVS_LPTDC2R_ET10P_MASK)
/*! @} */
/*! @name LPTDSR - SNVS_LP Tamper Detectors Status Register */
/*! @{ */
#define SNVS_LPTDSR_ET3D_MASK (0x1U)
#define SNVS_LPTDSR_ET3D_SHIFT (0U)
/*! ET3D
* 0b0..External tamper 3 is not detected.
* 0b1..External tamper 3 is detected.
*/
#define SNVS_LPTDSR_ET3D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET3D_SHIFT)) & SNVS_LPTDSR_ET3D_MASK)
#define SNVS_LPTDSR_ET4D_MASK (0x2U)
#define SNVS_LPTDSR_ET4D_SHIFT (1U)
/*! ET4D
* 0b0..External tamper 4 is not detected.
* 0b1..External tamper 4 is detected.
*/
#define SNVS_LPTDSR_ET4D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET4D_SHIFT)) & SNVS_LPTDSR_ET4D_MASK)
#define SNVS_LPTDSR_ET5D_MASK (0x4U)
#define SNVS_LPTDSR_ET5D_SHIFT (2U)
/*! ET5D
* 0b0..External tamper 5 is not detected.
* 0b1..External tamper 5 is detected.
*/
#define SNVS_LPTDSR_ET5D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET5D_SHIFT)) & SNVS_LPTDSR_ET5D_MASK)
#define SNVS_LPTDSR_ET6D_MASK (0x8U)
#define SNVS_LPTDSR_ET6D_SHIFT (3U)
/*! ET6D
* 0b0..External tamper 6 is not detected.
* 0b1..External tamper 6 is detected.
*/
#define SNVS_LPTDSR_ET6D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET6D_SHIFT)) & SNVS_LPTDSR_ET6D_MASK)
#define SNVS_LPTDSR_ET7D_MASK (0x10U)
#define SNVS_LPTDSR_ET7D_SHIFT (4U)
/*! ET7D
* 0b0..External tamper 7 is not detected.
* 0b1..External tamper 7 is detected.
*/
#define SNVS_LPTDSR_ET7D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET7D_SHIFT)) & SNVS_LPTDSR_ET7D_MASK)
#define SNVS_LPTDSR_ET8D_MASK (0x20U)
#define SNVS_LPTDSR_ET8D_SHIFT (5U)
/*! ET8D
* 0b0..External tamper 8 is not detected.
* 0b1..External tamper 8 is detected.
*/
#define SNVS_LPTDSR_ET8D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET8D_SHIFT)) & SNVS_LPTDSR_ET8D_MASK)
#define SNVS_LPTDSR_ET9D_MASK (0x40U)
#define SNVS_LPTDSR_ET9D_SHIFT (6U)
/*! ET9D
* 0b0..External tamper 9 is not detected.
* 0b1..External tamper 9 is detected.
*/
#define SNVS_LPTDSR_ET9D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET9D_SHIFT)) & SNVS_LPTDSR_ET9D_MASK)
#define SNVS_LPTDSR_ET10D_MASK (0x80U)
#define SNVS_LPTDSR_ET10D_SHIFT (7U)
/*! ET10D
* 0b0..External tamper 10 is not detected.
* 0b1..External tamper 10 is detected.
*/
#define SNVS_LPTDSR_ET10D(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTDSR_ET10D_SHIFT)) & SNVS_LPTDSR_ET10D_MASK)
/*! @} */
/*! @name LPTGF1CR - SNVS_LP Tamper Glitch Filter 1 Configuration Register */
/*! @{ */
#define SNVS_LPTGF1CR_ETGF3_MASK (0x7FU)
#define SNVS_LPTGF1CR_ETGF3_SHIFT (0U)
#define SNVS_LPTGF1CR_ETGF3(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_SHIFT)) & SNVS_LPTGF1CR_ETGF3_MASK)
#define SNVS_LPTGF1CR_ETGF3_EN_MASK (0x80U)
#define SNVS_LPTGF1CR_ETGF3_EN_SHIFT (7U)
/*! ETGF3_EN
* 0b0..External tamper glitch filter 3 is bypassed.
* 0b1..External tamper glitch filter 3 is enabled.
*/
#define SNVS_LPTGF1CR_ETGF3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF3_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF3_EN_MASK)
#define SNVS_LPTGF1CR_ETGF4_MASK (0x7F00U)
#define SNVS_LPTGF1CR_ETGF4_SHIFT (8U)
#define SNVS_LPTGF1CR_ETGF4(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_SHIFT)) & SNVS_LPTGF1CR_ETGF4_MASK)
#define SNVS_LPTGF1CR_ETGF4_EN_MASK (0x8000U)
#define SNVS_LPTGF1CR_ETGF4_EN_SHIFT (15U)
/*! ETGF4_EN
* 0b0..External tamper glitch filter 4 is bypassed.
* 0b1..External tamper glitch filter 4 is enabled.
*/
#define SNVS_LPTGF1CR_ETGF4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF4_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF4_EN_MASK)
#define SNVS_LPTGF1CR_ETGF5_MASK (0x7F0000U)
#define SNVS_LPTGF1CR_ETGF5_SHIFT (16U)
#define SNVS_LPTGF1CR_ETGF5(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_SHIFT)) & SNVS_LPTGF1CR_ETGF5_MASK)
#define SNVS_LPTGF1CR_ETGF5_EN_MASK (0x800000U)
#define SNVS_LPTGF1CR_ETGF5_EN_SHIFT (23U)
/*! ETGF5_EN
* 0b0..External tamper glitch filter 5 is bypassed.
* 0b1..External tamper glitch filter 5 is enabled.
*/
#define SNVS_LPTGF1CR_ETGF5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF5_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF5_EN_MASK)
#define SNVS_LPTGF1CR_ETGF6_MASK (0x7F000000U)
#define SNVS_LPTGF1CR_ETGF6_SHIFT (24U)
#define SNVS_LPTGF1CR_ETGF6(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_SHIFT)) & SNVS_LPTGF1CR_ETGF6_MASK)
#define SNVS_LPTGF1CR_ETGF6_EN_MASK (0x80000000U)
#define SNVS_LPTGF1CR_ETGF6_EN_SHIFT (31U)
/*! ETGF6_EN
* 0b0..External tamper glitch filter 6 is bypassed.
* 0b1..External tamper glitch filter 6 is enabled.
*/
#define SNVS_LPTGF1CR_ETGF6_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF1CR_ETGF6_EN_SHIFT)) & SNVS_LPTGF1CR_ETGF6_EN_MASK)
/*! @} */
/*! @name LPTGF2CR - SNVS_LP Tamper Glitch Filter 2 Configuration Register */
/*! @{ */
#define SNVS_LPTGF2CR_ETGF7_MASK (0x7FU)
#define SNVS_LPTGF2CR_ETGF7_SHIFT (0U)
#define SNVS_LPTGF2CR_ETGF7(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_SHIFT)) & SNVS_LPTGF2CR_ETGF7_MASK)
#define SNVS_LPTGF2CR_ETGF7_EN_MASK (0x80U)
#define SNVS_LPTGF2CR_ETGF7_EN_SHIFT (7U)
/*! ETGF7_EN
* 0b0..External tamper glitch filter 7 is bypassed.
* 0b1..External tamper glitch filter 7 is enabled.
*/
#define SNVS_LPTGF2CR_ETGF7_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF7_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF7_EN_MASK)
#define SNVS_LPTGF2CR_ETGF8_MASK (0x7F00U)
#define SNVS_LPTGF2CR_ETGF8_SHIFT (8U)
#define SNVS_LPTGF2CR_ETGF8(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_SHIFT)) & SNVS_LPTGF2CR_ETGF8_MASK)
#define SNVS_LPTGF2CR_ETGF8_EN_MASK (0x8000U)
#define SNVS_LPTGF2CR_ETGF8_EN_SHIFT (15U)
/*! ETGF8_EN
* 0b0..External tamper glitch filter 8 is bypassed.
* 0b1..External tamper glitch filter 8 is enabled.
*/
#define SNVS_LPTGF2CR_ETGF8_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF8_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF8_EN_MASK)
#define SNVS_LPTGF2CR_ETGF9_MASK (0x7F0000U)
#define SNVS_LPTGF2CR_ETGF9_SHIFT (16U)
#define SNVS_LPTGF2CR_ETGF9(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_SHIFT)) & SNVS_LPTGF2CR_ETGF9_MASK)
#define SNVS_LPTGF2CR_ETGF9_EN_MASK (0x800000U)
#define SNVS_LPTGF2CR_ETGF9_EN_SHIFT (23U)
/*! ETGF9_EN
* 0b0..External tamper glitch filter 9 is bypassed.
* 0b1..External tamper glitch filter 9 is enabled.
*/
#define SNVS_LPTGF2CR_ETGF9_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF9_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF9_EN_MASK)
#define SNVS_LPTGF2CR_ETGF10_MASK (0x7F000000U)
#define SNVS_LPTGF2CR_ETGF10_SHIFT (24U)
#define SNVS_LPTGF2CR_ETGF10(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_SHIFT)) & SNVS_LPTGF2CR_ETGF10_MASK)
#define SNVS_LPTGF2CR_ETGF10_EN_MASK (0x80000000U)
#define SNVS_LPTGF2CR_ETGF10_EN_SHIFT (31U)
/*! ETGF10_EN
* 0b0..External tamper glitch filter 10 is bypassed.
* 0b1..External tamper glitch filter 10 is enabled.
*/
#define SNVS_LPTGF2CR_ETGF10_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPTGF2CR_ETGF10_EN_SHIFT)) & SNVS_LPTGF2CR_ETGF10_EN_MASK)
/*! @} */
/*! @name LPATCR - SNVS_LP Active Tamper 1 Configuration Register..SNVS_LP Active Tamper 5 Configuration Register */
/*! @{ */
#define SNVS_LPATCR_Seed_MASK (0xFFFFU)
#define SNVS_LPATCR_Seed_SHIFT (0U)
#define SNVS_LPATCR_Seed(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Seed_SHIFT)) & SNVS_LPATCR_Seed_MASK)
#define SNVS_LPATCR_Polynomial_MASK (0xFFFF0000U)
#define SNVS_LPATCR_Polynomial_SHIFT (16U)
#define SNVS_LPATCR_Polynomial(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCR_Polynomial_SHIFT)) & SNVS_LPATCR_Polynomial_MASK)
/*! @} */
/* The count of SNVS_LPATCR */
#define SNVS_LPATCR_COUNT (5U)
/*! @name LPATCTLR - SNVS_LP Active Tamper Control Register */
/*! @{ */
#define SNVS_LPATCTLR_AT1_EN_MASK (0x1U)
#define SNVS_LPATCTLR_AT1_EN_SHIFT (0U)
/*! AT1_EN
* 0b0..Active Tamper 1 is disabled.
* 0b1..Active Tamper 1 is enabled.
*/
#define SNVS_LPATCTLR_AT1_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_EN_SHIFT)) & SNVS_LPATCTLR_AT1_EN_MASK)
#define SNVS_LPATCTLR_AT2_EN_MASK (0x2U)
#define SNVS_LPATCTLR_AT2_EN_SHIFT (1U)
/*! AT2_EN
* 0b0..Active Tamper 2 is disabled.
* 0b1..Active Tamper 2 is enabled.
*/
#define SNVS_LPATCTLR_AT2_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_EN_SHIFT)) & SNVS_LPATCTLR_AT2_EN_MASK)
#define SNVS_LPATCTLR_AT3_EN_MASK (0x4U)
#define SNVS_LPATCTLR_AT3_EN_SHIFT (2U)
/*! AT3_EN
* 0b0..Active Tamper 3 is disabled.
* 0b1..Active Tamper 3 is enabled.
*/
#define SNVS_LPATCTLR_AT3_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_EN_SHIFT)) & SNVS_LPATCTLR_AT3_EN_MASK)
#define SNVS_LPATCTLR_AT4_EN_MASK (0x8U)
#define SNVS_LPATCTLR_AT4_EN_SHIFT (3U)
/*! AT4_EN
* 0b0..Active Tamper 4 is disabled.
* 0b1..Active Tamper 4 is enabled.
*/
#define SNVS_LPATCTLR_AT4_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_EN_SHIFT)) & SNVS_LPATCTLR_AT4_EN_MASK)
#define SNVS_LPATCTLR_AT5_EN_MASK (0x10U)
#define SNVS_LPATCTLR_AT5_EN_SHIFT (4U)
/*! AT5_EN
* 0b0..Active Tamper 5 is disabled.
* 0b1..Active Tamper 5 is enabled.
*/
#define SNVS_LPATCTLR_AT5_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_EN_SHIFT)) & SNVS_LPATCTLR_AT5_EN_MASK)
#define SNVS_LPATCTLR_AT1_PAD_EN_MASK (0x10000U)
#define SNVS_LPATCTLR_AT1_PAD_EN_SHIFT (16U)
/*! AT1_PAD_EN
* 0b0..Active Tamper 1 is disabled.
* 0b1..Active Tamper 1 is enabled.
*/
#define SNVS_LPATCTLR_AT1_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT1_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT1_PAD_EN_MASK)
#define SNVS_LPATCTLR_AT2_PAD_EN_MASK (0x20000U)
#define SNVS_LPATCTLR_AT2_PAD_EN_SHIFT (17U)
/*! AT2_PAD_EN
* 0b0..Active Tamper 2 is disabled.
* 0b1..Active Tamper 2 is enabled.
*/
#define SNVS_LPATCTLR_AT2_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT2_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT2_PAD_EN_MASK)
#define SNVS_LPATCTLR_AT3_PAD_EN_MASK (0x40000U)
#define SNVS_LPATCTLR_AT3_PAD_EN_SHIFT (18U)
/*! AT3_PAD_EN
* 0b0..Active Tamper 3 is disabled.
* 0b1..Active Tamper 3 is enabled
*/
#define SNVS_LPATCTLR_AT3_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT3_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT3_PAD_EN_MASK)
#define SNVS_LPATCTLR_AT4_PAD_EN_MASK (0x80000U)
#define SNVS_LPATCTLR_AT4_PAD_EN_SHIFT (19U)
/*! AT4_PAD_EN
* 0b0..Active Tamper 4 is disabled.
* 0b1..Active Tamper 4 is enabled.
*/
#define SNVS_LPATCTLR_AT4_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT4_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT4_PAD_EN_MASK)
#define SNVS_LPATCTLR_AT5_PAD_EN_MASK (0x100000U)
#define SNVS_LPATCTLR_AT5_PAD_EN_SHIFT (20U)
/*! AT5_PAD_EN
* 0b0..Active Tamper 5 is disabled.
* 0b1..Active Tamper 5 is enabled.
*/
#define SNVS_LPATCTLR_AT5_PAD_EN(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCTLR_AT5_PAD_EN_SHIFT)) & SNVS_LPATCTLR_AT5_PAD_EN_MASK)
/*! @} */
/*! @name LPATCLKR - SNVS_LP Active Tamper Clock Control Register */
/*! @{ */
#define SNVS_LPATCLKR_AT1_CLK_CTL_MASK (0x3U)
#define SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT (0U)
#define SNVS_LPATCLKR_AT1_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT1_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT1_CLK_CTL_MASK)
#define SNVS_LPATCLKR_AT2_CLK_CTL_MASK (0x30U)
#define SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT (4U)
#define SNVS_LPATCLKR_AT2_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT2_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT2_CLK_CTL_MASK)
#define SNVS_LPATCLKR_AT3_CLK_CTL_MASK (0x300U)
#define SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT (8U)
#define SNVS_LPATCLKR_AT3_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT3_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT3_CLK_CTL_MASK)
#define SNVS_LPATCLKR_AT4_CLK_CTL_MASK (0x3000U)
#define SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT (12U)
#define SNVS_LPATCLKR_AT4_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT4_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT4_CLK_CTL_MASK)
#define SNVS_LPATCLKR_AT5_CLK_CTL_MASK (0x30000U)
#define SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT (16U)
#define SNVS_LPATCLKR_AT5_CLK_CTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATCLKR_AT5_CLK_CTL_SHIFT)) & SNVS_LPATCLKR_AT5_CLK_CTL_MASK)
/*! @} */
/*! @name LPATRC1R - SNVS_LP Active Tamper Routing Control 1 Register */
/*! @{ */
#define SNVS_LPATRC1R_ET1RCTL_MASK (0x7U)
#define SNVS_LPATRC1R_ET1RCTL_SHIFT (0U)
#define SNVS_LPATRC1R_ET1RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET1RCTL_SHIFT)) & SNVS_LPATRC1R_ET1RCTL_MASK)
#define SNVS_LPATRC1R_ET2RCTL_MASK (0x70U)
#define SNVS_LPATRC1R_ET2RCTL_SHIFT (4U)
#define SNVS_LPATRC1R_ET2RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET2RCTL_SHIFT)) & SNVS_LPATRC1R_ET2RCTL_MASK)
#define SNVS_LPATRC1R_ET3RCTL_MASK (0x700U)
#define SNVS_LPATRC1R_ET3RCTL_SHIFT (8U)
#define SNVS_LPATRC1R_ET3RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET3RCTL_SHIFT)) & SNVS_LPATRC1R_ET3RCTL_MASK)
#define SNVS_LPATRC1R_ET4RCTL_MASK (0x7000U)
#define SNVS_LPATRC1R_ET4RCTL_SHIFT (12U)
#define SNVS_LPATRC1R_ET4RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET4RCTL_SHIFT)) & SNVS_LPATRC1R_ET4RCTL_MASK)
#define SNVS_LPATRC1R_ET5RCTL_MASK (0x70000U)
#define SNVS_LPATRC1R_ET5RCTL_SHIFT (16U)
#define SNVS_LPATRC1R_ET5RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET5RCTL_SHIFT)) & SNVS_LPATRC1R_ET5RCTL_MASK)
#define SNVS_LPATRC1R_ET6RCTL_MASK (0x700000U)
#define SNVS_LPATRC1R_ET6RCTL_SHIFT (20U)
#define SNVS_LPATRC1R_ET6RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET6RCTL_SHIFT)) & SNVS_LPATRC1R_ET6RCTL_MASK)
#define SNVS_LPATRC1R_ET7RCTL_MASK (0x7000000U)
#define SNVS_LPATRC1R_ET7RCTL_SHIFT (24U)
#define SNVS_LPATRC1R_ET7RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET7RCTL_SHIFT)) & SNVS_LPATRC1R_ET7RCTL_MASK)
#define SNVS_LPATRC1R_ET8RCTL_MASK (0x70000000U)
#define SNVS_LPATRC1R_ET8RCTL_SHIFT (28U)
#define SNVS_LPATRC1R_ET8RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC1R_ET8RCTL_SHIFT)) & SNVS_LPATRC1R_ET8RCTL_MASK)
/*! @} */
/*! @name LPATRC2R - SNVS_LP Active Tamper Routing Control 2 Register */
/*! @{ */
#define SNVS_LPATRC2R_ET9RCTL_MASK (0x7U)
#define SNVS_LPATRC2R_ET9RCTL_SHIFT (0U)
#define SNVS_LPATRC2R_ET9RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET9RCTL_SHIFT)) & SNVS_LPATRC2R_ET9RCTL_MASK)
#define SNVS_LPATRC2R_ET10RCTL_MASK (0x70U)
#define SNVS_LPATRC2R_ET10RCTL_SHIFT (4U)
#define SNVS_LPATRC2R_ET10RCTL(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPATRC2R_ET10RCTL_SHIFT)) & SNVS_LPATRC2R_ET10RCTL_MASK)
/*! @} */
/*! @name LPGPR - SNVS_LP General Purpose Registers 0 .. 3 */
/*! @{ */
#define SNVS_LPGPR_GPR_MASK (0xFFFFFFFFU)
#define SNVS_LPGPR_GPR_SHIFT (0U)
#define SNVS_LPGPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SNVS_LPGPR_GPR_SHIFT)) & SNVS_LPGPR_GPR_MASK)
/*! @} */
/* The count of SNVS_LPGPR */
#define SNVS_LPGPR_COUNT (4U)
/*! @name HPVIDR1 - SNVS_HP Version ID Register 1 */
/*! @{ */
#define SNVS_HPVIDR1_MINOR_REV_MASK (0xFFU)
#define SNVS_HPVIDR1_MINOR_REV_SHIFT (0U)
#define SNVS_HPVIDR1_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MINOR_REV_SHIFT)) & SNVS_HPVIDR1_MINOR_REV_MASK)
#define SNVS_HPVIDR1_MAJOR_REV_MASK (0xFF00U)
#define SNVS_HPVIDR1_MAJOR_REV_SHIFT (8U)
#define SNVS_HPVIDR1_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_MAJOR_REV_SHIFT)) & SNVS_HPVIDR1_MAJOR_REV_MASK)
#define SNVS_HPVIDR1_IP_ID_MASK (0xFFFF0000U)
#define SNVS_HPVIDR1_IP_ID_SHIFT (16U)
#define SNVS_HPVIDR1_IP_ID(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR1_IP_ID_SHIFT)) & SNVS_HPVIDR1_IP_ID_MASK)
/*! @} */
/*! @name HPVIDR2 - SNVS_HP Version ID Register 2 */
/*! @{ */
#define SNVS_HPVIDR2_ECO_REV_MASK (0xFF00U)
#define SNVS_HPVIDR2_ECO_REV_SHIFT (8U)
#define SNVS_HPVIDR2_ECO_REV(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_ECO_REV_SHIFT)) & SNVS_HPVIDR2_ECO_REV_MASK)
#define SNVS_HPVIDR2_IP_ERA_MASK (0xFF000000U)
#define SNVS_HPVIDR2_IP_ERA_SHIFT (24U)
#define SNVS_HPVIDR2_IP_ERA(x) (((uint32_t)(((uint32_t)(x)) << SNVS_HPVIDR2_IP_ERA_SHIFT)) & SNVS_HPVIDR2_IP_ERA_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SNVS_Register_Masks */
/* SNVS - Peripheral instance base addresses */
/** Peripheral SNVS base address */
#define SNVS_BASE (0x40C90000u)
/** Peripheral SNVS base pointer */
#define SNVS ((SNVS_Type *)SNVS_BASE)
/** Array initializer of SNVS peripheral base addresses */
#define SNVS_BASE_ADDRS { SNVS_BASE }
/** Array initializer of SNVS peripheral base pointers */
#define SNVS_BASE_PTRS { SNVS }
/** Interrupt vectors for the SNVS peripheral type */
#define SNVS_IRQS { SNVS_PULSE_EVENT_IRQn }
#define SNVS_CONSOLIDATED_IRQS { SNVS_HP_NON_TZ_IRQn }
#define SNVS_SECURITY_IRQS { SNVS_HP_TZ_IRQn }
/*!
* @}
*/ /* end of group SNVS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SPDIF Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPDIF_Peripheral_Access_Layer SPDIF Peripheral Access Layer
* @{
*/
/** SPDIF - Register Layout Typedef */
typedef struct {
__IO uint32_t SCR; /**< SPDIF Configuration Register, offset: 0x0 */
__IO uint32_t SRCD; /**< CDText Control Register, offset: 0x4 */
__IO uint32_t SRPC; /**< PhaseConfig Register, offset: 0x8 */
__IO uint32_t SIE; /**< InterruptEn Register, offset: 0xC */
union { /* offset: 0x10 */
__O uint32_t SIC; /**< InterruptClear Register, offset: 0x10 */
__I uint32_t SIS; /**< InterruptStat Register, offset: 0x10 */
};
__I uint32_t SRL; /**< SPDIFRxLeft Register, offset: 0x14 */
__I uint32_t SRR; /**< SPDIFRxRight Register, offset: 0x18 */
__I uint32_t SRCSH; /**< SPDIFRxCChannel_h Register, offset: 0x1C */
__I uint32_t SRCSL; /**< SPDIFRxCChannel_l Register, offset: 0x20 */
__I uint32_t SRU; /**< UchannelRx Register, offset: 0x24 */
__I uint32_t SRQ; /**< QchannelRx Register, offset: 0x28 */
__O uint32_t STL; /**< SPDIFTxLeft Register, offset: 0x2C */
__O uint32_t STR; /**< SPDIFTxRight Register, offset: 0x30 */
__IO uint32_t STCSCH; /**< SPDIFTxCChannelCons_h Register, offset: 0x34 */
__IO uint32_t STCSCL; /**< SPDIFTxCChannelCons_l Register, offset: 0x38 */
uint8_t RESERVED_0[8];
__I uint32_t SRFM; /**< FreqMeas Register, offset: 0x44 */
uint8_t RESERVED_1[8];
__IO uint32_t STC; /**< SPDIFTxClk Register, offset: 0x50 */
} SPDIF_Type;
/* ----------------------------------------------------------------------------
-- SPDIF Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SPDIF_Register_Masks SPDIF Register Masks
* @{
*/
/*! @name SCR - SPDIF Configuration Register */
/*! @{ */
#define SPDIF_SCR_USRC_SEL_MASK (0x3U)
#define SPDIF_SCR_USRC_SEL_SHIFT (0U)
/*! USrc_Sel - USrc_Sel
* 0b00..No embedded U channel
* 0b01..U channel from SPDIF receive block (CD mode)
* 0b10..Reserved
* 0b11..U channel from on chip transmitter
*/
#define SPDIF_SCR_USRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_USRC_SEL_SHIFT)) & SPDIF_SCR_USRC_SEL_MASK)
#define SPDIF_SCR_TXSEL_MASK (0x1CU)
#define SPDIF_SCR_TXSEL_SHIFT (2U)
/*! TxSel - TxSel
* 0b000..Off and output 0
* 0b001..Feed-through SPDIFIN
* 0b101..Tx Normal operation
*/
#define SPDIF_SCR_TXSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXSEL_SHIFT)) & SPDIF_SCR_TXSEL_MASK)
#define SPDIF_SCR_VALCTRL_MASK (0x20U)
#define SPDIF_SCR_VALCTRL_SHIFT (5U)
/*! ValCtrl - ValCtrl
* 0b0..Outgoing Validity always set
* 0b1..Outgoing Validity always clear
*/
#define SPDIF_SCR_VALCTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_VALCTRL_SHIFT)) & SPDIF_SCR_VALCTRL_MASK)
#define SPDIF_SCR_INPUTSRCSEL_MASK (0xC0U)
#define SPDIF_SCR_INPUTSRCSEL_SHIFT (6U)
/*! InputSrcSel - InputSrcSel
* 0b00..SPDIF_IN
* 0b01-0b11..None
*/
#define SPDIF_SCR_INPUTSRCSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_INPUTSRCSEL_SHIFT)) & SPDIF_SCR_INPUTSRCSEL_MASK)
#define SPDIF_SCR_DMA_TX_EN_MASK (0x100U)
#define SPDIF_SCR_DMA_TX_EN_SHIFT (8U)
/*! DMA_TX_En - DMA_TX_En
*/
#define SPDIF_SCR_DMA_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_TX_EN_SHIFT)) & SPDIF_SCR_DMA_TX_EN_MASK)
#define SPDIF_SCR_DMA_RX_EN_MASK (0x200U)
#define SPDIF_SCR_DMA_RX_EN_SHIFT (9U)
/*! DMA_Rx_En - DMA_Rx_En
*/
#define SPDIF_SCR_DMA_RX_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_DMA_RX_EN_SHIFT)) & SPDIF_SCR_DMA_RX_EN_MASK)
#define SPDIF_SCR_TXFIFO_CTRL_MASK (0xC00U)
#define SPDIF_SCR_TXFIFO_CTRL_SHIFT (10U)
/*! TxFIFO_Ctrl - TxFIFO_Ctrl
* 0b00..Send out digital zero on SPDIF Tx
* 0b01..Tx Normal operation
* 0b10..Reset to 1 sample remaining
* 0b11..Reserved
*/
#define SPDIF_SCR_TXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFO_CTRL_SHIFT)) & SPDIF_SCR_TXFIFO_CTRL_MASK)
#define SPDIF_SCR_SOFT_RESET_MASK (0x1000U)
#define SPDIF_SCR_SOFT_RESET_SHIFT (12U)
/*! soft_reset - soft_reset
*/
#define SPDIF_SCR_SOFT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_SOFT_RESET_SHIFT)) & SPDIF_SCR_SOFT_RESET_MASK)
#define SPDIF_SCR_LOW_POWER_MASK (0x2000U)
#define SPDIF_SCR_LOW_POWER_SHIFT (13U)
/*! LOW_POWER - LOW_POWER
*/
#define SPDIF_SCR_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_LOW_POWER_SHIFT)) & SPDIF_SCR_LOW_POWER_MASK)
#define SPDIF_SCR_TXFIFOEMPTY_SEL_MASK (0x18000U)
#define SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT (15U)
/*! TxFIFOEmpty_Sel - TxFIFOEmpty_Sel
* 0b00..Empty interrupt if 0 sample in Tx left and right FIFOs
* 0b01..Empty interrupt if at most 4 sample in Tx left and right FIFOs
* 0b10..Empty interrupt if at most 8 sample in Tx left and right FIFOs
* 0b11..Empty interrupt if at most 12 sample in Tx left and right FIFOs
*/
#define SPDIF_SCR_TXFIFOEMPTY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXFIFOEMPTY_SEL_SHIFT)) & SPDIF_SCR_TXFIFOEMPTY_SEL_MASK)
#define SPDIF_SCR_TXAUTOSYNC_MASK (0x20000U)
#define SPDIF_SCR_TXAUTOSYNC_SHIFT (17U)
/*! TxAutoSync - TxAutoSync
* 0b0..Tx FIFO auto sync off
* 0b1..Tx FIFO auto sync on
*/
#define SPDIF_SCR_TXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_TXAUTOSYNC_SHIFT)) & SPDIF_SCR_TXAUTOSYNC_MASK)
#define SPDIF_SCR_RXAUTOSYNC_MASK (0x40000U)
#define SPDIF_SCR_RXAUTOSYNC_SHIFT (18U)
/*! RxAutoSync - RxAutoSync
* 0b0..Rx FIFO auto sync off
* 0b1..RxFIFO auto sync on
*/
#define SPDIF_SCR_RXAUTOSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXAUTOSYNC_SHIFT)) & SPDIF_SCR_RXAUTOSYNC_MASK)
#define SPDIF_SCR_RXFIFOFULL_SEL_MASK (0x180000U)
#define SPDIF_SCR_RXFIFOFULL_SEL_SHIFT (19U)
/*! RxFIFOFull_Sel - RxFIFOFull_Sel
* 0b00..Full interrupt if at least 1 sample in Rx left and right FIFOs
* 0b01..Full interrupt if at least 4 sample in Rx left and right FIFOs
* 0b10..Full interrupt if at least 8 sample in Rx left and right FIFOs
* 0b11..Full interrupt if at least 16 sample in Rx left and right FIFO
*/
#define SPDIF_SCR_RXFIFOFULL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFOFULL_SEL_SHIFT)) & SPDIF_SCR_RXFIFOFULL_SEL_MASK)
#define SPDIF_SCR_RXFIFO_RST_MASK (0x200000U)
#define SPDIF_SCR_RXFIFO_RST_SHIFT (21U)
/*! RxFIFO_Rst - RxFIFO_Rst
* 0b0..Normal operation
* 0b1..Reset register to 1 sample remaining
*/
#define SPDIF_SCR_RXFIFO_RST(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_RST_SHIFT)) & SPDIF_SCR_RXFIFO_RST_MASK)
#define SPDIF_SCR_RXFIFO_OFF_ON_MASK (0x400000U)
#define SPDIF_SCR_RXFIFO_OFF_ON_SHIFT (22U)
/*! RxFIFO_Off_On - RxFIFO_Off_On
* 0b0..SPDIF Rx FIFO is on
* 0b1..SPDIF Rx FIFO is off. Does not accept data from interface
*/
#define SPDIF_SCR_RXFIFO_OFF_ON(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_OFF_ON_SHIFT)) & SPDIF_SCR_RXFIFO_OFF_ON_MASK)
#define SPDIF_SCR_RXFIFO_CTRL_MASK (0x800000U)
#define SPDIF_SCR_RXFIFO_CTRL_SHIFT (23U)
/*! RxFIFO_Ctrl - RxFIFO_Ctrl
* 0b0..Normal operation
* 0b1..Always read zero from Rx data register
*/
#define SPDIF_SCR_RXFIFO_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SCR_RXFIFO_CTRL_SHIFT)) & SPDIF_SCR_RXFIFO_CTRL_MASK)
/*! @} */
/*! @name SRCD - CDText Control Register */
/*! @{ */
#define SPDIF_SRCD_USYNCMODE_MASK (0x2U)
#define SPDIF_SRCD_USYNCMODE_SHIFT (1U)
/*! USyncMode - USyncMode
* 0b0..Non-CD data
* 0b1..CD user channel subcode
*/
#define SPDIF_SRCD_USYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCD_USYNCMODE_SHIFT)) & SPDIF_SRCD_USYNCMODE_MASK)
/*! @} */
/*! @name SRPC - PhaseConfig Register */
/*! @{ */
#define SPDIF_SRPC_GAINSEL_MASK (0x38U)
#define SPDIF_SRPC_GAINSEL_SHIFT (3U)
/*! GainSel - GainSel
* 0b000..24*(2**10)
* 0b001..16*(2**10)
* 0b010..12*(2**10)
* 0b011..8*(2**10)
* 0b100..6*(2**10)
* 0b101..4*(2**10)
* 0b110..3*(2**10)
*/
#define SPDIF_SRPC_GAINSEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_GAINSEL_SHIFT)) & SPDIF_SRPC_GAINSEL_MASK)
#define SPDIF_SRPC_LOCK_MASK (0x40U)
#define SPDIF_SRPC_LOCK_SHIFT (6U)
/*! LOCK - LOCK
*/
#define SPDIF_SRPC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_LOCK_SHIFT)) & SPDIF_SRPC_LOCK_MASK)
#define SPDIF_SRPC_CLKSRC_SEL_MASK (0x780U)
#define SPDIF_SRPC_CLKSRC_SEL_SHIFT (7U)
/*! ClkSrc_Sel - ClkSrc_Sel
* 0b0000..if (DPLL Locked) SPDIF_RxClk else REF_CLK_32K (XTALOSC)
* 0b0001..if (DPLL Locked) SPDIF_RxClk else tx_clk (SPDIF0_CLK_ROOT)
* 0b0011..if (DPLL Locked) SPDIF_RxClk else SPDIF_EXT_CLK
* 0b0101..REF_CLK_32K (XTALOSC)
* 0b0110..tx_clk (SPDIF0_CLK_ROOT)
* 0b1000..SPDIF_EXT_CLK
*/
#define SPDIF_SRPC_CLKSRC_SEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRPC_CLKSRC_SEL_SHIFT)) & SPDIF_SRPC_CLKSRC_SEL_MASK)
/*! @} */
/*! @name SIE - InterruptEn Register */
/*! @{ */
#define SPDIF_SIE_RXFIFOFUL_MASK (0x1U)
#define SPDIF_SIE_RXFIFOFUL_SHIFT (0U)
/*! RxFIFOFul - RxFIFOFul
*/
#define SPDIF_SIE_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOFUL_SHIFT)) & SPDIF_SIE_RXFIFOFUL_MASK)
#define SPDIF_SIE_TXEM_MASK (0x2U)
#define SPDIF_SIE_TXEM_SHIFT (1U)
/*! TxEm - TxEm
*/
#define SPDIF_SIE_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXEM_SHIFT)) & SPDIF_SIE_TXEM_MASK)
#define SPDIF_SIE_LOCKLOSS_MASK (0x4U)
#define SPDIF_SIE_LOCKLOSS_SHIFT (2U)
/*! LockLoss - LockLoss
*/
#define SPDIF_SIE_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCKLOSS_SHIFT)) & SPDIF_SIE_LOCKLOSS_MASK)
#define SPDIF_SIE_RXFIFORESYN_MASK (0x8U)
#define SPDIF_SIE_RXFIFORESYN_SHIFT (3U)
/*! RxFIFOResyn - RxFIFOResyn
*/
#define SPDIF_SIE_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFORESYN_SHIFT)) & SPDIF_SIE_RXFIFORESYN_MASK)
#define SPDIF_SIE_RXFIFOUNOV_MASK (0x10U)
#define SPDIF_SIE_RXFIFOUNOV_SHIFT (4U)
/*! RxFIFOUnOv - RxFIFOUnOv
*/
#define SPDIF_SIE_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_RXFIFOUNOV_SHIFT)) & SPDIF_SIE_RXFIFOUNOV_MASK)
#define SPDIF_SIE_UQERR_MASK (0x20U)
#define SPDIF_SIE_UQERR_SHIFT (5U)
/*! UQErr - UQErr
*/
#define SPDIF_SIE_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQERR_SHIFT)) & SPDIF_SIE_UQERR_MASK)
#define SPDIF_SIE_UQSYNC_MASK (0x40U)
#define SPDIF_SIE_UQSYNC_SHIFT (6U)
/*! UQSync - UQSync
*/
#define SPDIF_SIE_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_UQSYNC_SHIFT)) & SPDIF_SIE_UQSYNC_MASK)
#define SPDIF_SIE_QRXOV_MASK (0x80U)
#define SPDIF_SIE_QRXOV_SHIFT (7U)
/*! QRxOv - QRxOv
*/
#define SPDIF_SIE_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXOV_SHIFT)) & SPDIF_SIE_QRXOV_MASK)
#define SPDIF_SIE_QRXFUL_MASK (0x100U)
#define SPDIF_SIE_QRXFUL_SHIFT (8U)
/*! QRxFul - QRxFul
*/
#define SPDIF_SIE_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_QRXFUL_SHIFT)) & SPDIF_SIE_QRXFUL_MASK)
#define SPDIF_SIE_URXOV_MASK (0x200U)
#define SPDIF_SIE_URXOV_SHIFT (9U)
/*! URxOv - URxOv
*/
#define SPDIF_SIE_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXOV_SHIFT)) & SPDIF_SIE_URXOV_MASK)
#define SPDIF_SIE_URXFUL_MASK (0x400U)
#define SPDIF_SIE_URXFUL_SHIFT (10U)
/*! URxFul - URxFul
*/
#define SPDIF_SIE_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_URXFUL_SHIFT)) & SPDIF_SIE_URXFUL_MASK)
#define SPDIF_SIE_BITERR_MASK (0x4000U)
#define SPDIF_SIE_BITERR_SHIFT (14U)
/*! BitErr - BitErr
*/
#define SPDIF_SIE_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_BITERR_SHIFT)) & SPDIF_SIE_BITERR_MASK)
#define SPDIF_SIE_SYMERR_MASK (0x8000U)
#define SPDIF_SIE_SYMERR_SHIFT (15U)
/*! SymErr - SymErr
*/
#define SPDIF_SIE_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_SYMERR_SHIFT)) & SPDIF_SIE_SYMERR_MASK)
#define SPDIF_SIE_VALNOGOOD_MASK (0x10000U)
#define SPDIF_SIE_VALNOGOOD_SHIFT (16U)
/*! ValNoGood - ValNoGood
*/
#define SPDIF_SIE_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_VALNOGOOD_SHIFT)) & SPDIF_SIE_VALNOGOOD_MASK)
#define SPDIF_SIE_CNEW_MASK (0x20000U)
#define SPDIF_SIE_CNEW_SHIFT (17U)
/*! CNew - CNew
*/
#define SPDIF_SIE_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_CNEW_SHIFT)) & SPDIF_SIE_CNEW_MASK)
#define SPDIF_SIE_TXRESYN_MASK (0x40000U)
#define SPDIF_SIE_TXRESYN_SHIFT (18U)
/*! TxResyn - TxResyn
*/
#define SPDIF_SIE_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXRESYN_SHIFT)) & SPDIF_SIE_TXRESYN_MASK)
#define SPDIF_SIE_TXUNOV_MASK (0x80000U)
#define SPDIF_SIE_TXUNOV_SHIFT (19U)
/*! TxUnOv - TxUnOv
*/
#define SPDIF_SIE_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_TXUNOV_SHIFT)) & SPDIF_SIE_TXUNOV_MASK)
#define SPDIF_SIE_LOCK_MASK (0x100000U)
#define SPDIF_SIE_LOCK_SHIFT (20U)
/*! Lock - Lock
*/
#define SPDIF_SIE_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIE_LOCK_SHIFT)) & SPDIF_SIE_LOCK_MASK)
/*! @} */
/*! @name SIC - InterruptClear Register */
/*! @{ */
#define SPDIF_SIC_LOCKLOSS_MASK (0x4U)
#define SPDIF_SIC_LOCKLOSS_SHIFT (2U)
/*! LockLoss - LockLoss
*/
#define SPDIF_SIC_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCKLOSS_SHIFT)) & SPDIF_SIC_LOCKLOSS_MASK)
#define SPDIF_SIC_RXFIFORESYN_MASK (0x8U)
#define SPDIF_SIC_RXFIFORESYN_SHIFT (3U)
/*! RxFIFOResyn - RxFIFOResyn
*/
#define SPDIF_SIC_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFORESYN_SHIFT)) & SPDIF_SIC_RXFIFORESYN_MASK)
#define SPDIF_SIC_RXFIFOUNOV_MASK (0x10U)
#define SPDIF_SIC_RXFIFOUNOV_SHIFT (4U)
/*! RxFIFOUnOv - RxFIFOUnOv
*/
#define SPDIF_SIC_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_RXFIFOUNOV_SHIFT)) & SPDIF_SIC_RXFIFOUNOV_MASK)
#define SPDIF_SIC_UQERR_MASK (0x20U)
#define SPDIF_SIC_UQERR_SHIFT (5U)
/*! UQErr - UQErr
*/
#define SPDIF_SIC_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQERR_SHIFT)) & SPDIF_SIC_UQERR_MASK)
#define SPDIF_SIC_UQSYNC_MASK (0x40U)
#define SPDIF_SIC_UQSYNC_SHIFT (6U)
/*! UQSync - UQSync
*/
#define SPDIF_SIC_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_UQSYNC_SHIFT)) & SPDIF_SIC_UQSYNC_MASK)
#define SPDIF_SIC_QRXOV_MASK (0x80U)
#define SPDIF_SIC_QRXOV_SHIFT (7U)
/*! QRxOv - QRxOv
*/
#define SPDIF_SIC_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_QRXOV_SHIFT)) & SPDIF_SIC_QRXOV_MASK)
#define SPDIF_SIC_URXOV_MASK (0x200U)
#define SPDIF_SIC_URXOV_SHIFT (9U)
/*! URxOv - URxOv
*/
#define SPDIF_SIC_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_URXOV_SHIFT)) & SPDIF_SIC_URXOV_MASK)
#define SPDIF_SIC_BITERR_MASK (0x4000U)
#define SPDIF_SIC_BITERR_SHIFT (14U)
/*! BitErr - BitErr
*/
#define SPDIF_SIC_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_BITERR_SHIFT)) & SPDIF_SIC_BITERR_MASK)
#define SPDIF_SIC_SYMERR_MASK (0x8000U)
#define SPDIF_SIC_SYMERR_SHIFT (15U)
/*! SymErr - SymErr
*/
#define SPDIF_SIC_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_SYMERR_SHIFT)) & SPDIF_SIC_SYMERR_MASK)
#define SPDIF_SIC_VALNOGOOD_MASK (0x10000U)
#define SPDIF_SIC_VALNOGOOD_SHIFT (16U)
/*! ValNoGood - ValNoGood
*/
#define SPDIF_SIC_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_VALNOGOOD_SHIFT)) & SPDIF_SIC_VALNOGOOD_MASK)
#define SPDIF_SIC_CNEW_MASK (0x20000U)
#define SPDIF_SIC_CNEW_SHIFT (17U)
/*! CNew - CNew
*/
#define SPDIF_SIC_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_CNEW_SHIFT)) & SPDIF_SIC_CNEW_MASK)
#define SPDIF_SIC_TXRESYN_MASK (0x40000U)
#define SPDIF_SIC_TXRESYN_SHIFT (18U)
/*! TxResyn - TxResyn
*/
#define SPDIF_SIC_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXRESYN_SHIFT)) & SPDIF_SIC_TXRESYN_MASK)
#define SPDIF_SIC_TXUNOV_MASK (0x80000U)
#define SPDIF_SIC_TXUNOV_SHIFT (19U)
/*! TxUnOv - TxUnOv
*/
#define SPDIF_SIC_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_TXUNOV_SHIFT)) & SPDIF_SIC_TXUNOV_MASK)
#define SPDIF_SIC_LOCK_MASK (0x100000U)
#define SPDIF_SIC_LOCK_SHIFT (20U)
/*! Lock - Lock
*/
#define SPDIF_SIC_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIC_LOCK_SHIFT)) & SPDIF_SIC_LOCK_MASK)
/*! @} */
/*! @name SIS - InterruptStat Register */
/*! @{ */
#define SPDIF_SIS_RXFIFOFUL_MASK (0x1U)
#define SPDIF_SIS_RXFIFOFUL_SHIFT (0U)
/*! RxFIFOFul - RxFIFOFul
*/
#define SPDIF_SIS_RXFIFOFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOFUL_SHIFT)) & SPDIF_SIS_RXFIFOFUL_MASK)
#define SPDIF_SIS_TXEM_MASK (0x2U)
#define SPDIF_SIS_TXEM_SHIFT (1U)
/*! TxEm - TxEm
*/
#define SPDIF_SIS_TXEM(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXEM_SHIFT)) & SPDIF_SIS_TXEM_MASK)
#define SPDIF_SIS_LOCKLOSS_MASK (0x4U)
#define SPDIF_SIS_LOCKLOSS_SHIFT (2U)
/*! LockLoss - LockLoss
*/
#define SPDIF_SIS_LOCKLOSS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCKLOSS_SHIFT)) & SPDIF_SIS_LOCKLOSS_MASK)
#define SPDIF_SIS_RXFIFORESYN_MASK (0x8U)
#define SPDIF_SIS_RXFIFORESYN_SHIFT (3U)
/*! RxFIFOResyn - RxFIFOResyn
*/
#define SPDIF_SIS_RXFIFORESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFORESYN_SHIFT)) & SPDIF_SIS_RXFIFORESYN_MASK)
#define SPDIF_SIS_RXFIFOUNOV_MASK (0x10U)
#define SPDIF_SIS_RXFIFOUNOV_SHIFT (4U)
/*! RxFIFOUnOv - RxFIFOUnOv
*/
#define SPDIF_SIS_RXFIFOUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_RXFIFOUNOV_SHIFT)) & SPDIF_SIS_RXFIFOUNOV_MASK)
#define SPDIF_SIS_UQERR_MASK (0x20U)
#define SPDIF_SIS_UQERR_SHIFT (5U)
/*! UQErr - UQErr
*/
#define SPDIF_SIS_UQERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQERR_SHIFT)) & SPDIF_SIS_UQERR_MASK)
#define SPDIF_SIS_UQSYNC_MASK (0x40U)
#define SPDIF_SIS_UQSYNC_SHIFT (6U)
/*! UQSync - UQSync
*/
#define SPDIF_SIS_UQSYNC(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_UQSYNC_SHIFT)) & SPDIF_SIS_UQSYNC_MASK)
#define SPDIF_SIS_QRXOV_MASK (0x80U)
#define SPDIF_SIS_QRXOV_SHIFT (7U)
/*! QRxOv - QRxOv
*/
#define SPDIF_SIS_QRXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXOV_SHIFT)) & SPDIF_SIS_QRXOV_MASK)
#define SPDIF_SIS_QRXFUL_MASK (0x100U)
#define SPDIF_SIS_QRXFUL_SHIFT (8U)
/*! QRxFul - QRxFul
*/
#define SPDIF_SIS_QRXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_QRXFUL_SHIFT)) & SPDIF_SIS_QRXFUL_MASK)
#define SPDIF_SIS_URXOV_MASK (0x200U)
#define SPDIF_SIS_URXOV_SHIFT (9U)
/*! URxOv - URxOv
*/
#define SPDIF_SIS_URXOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXOV_SHIFT)) & SPDIF_SIS_URXOV_MASK)
#define SPDIF_SIS_URXFUL_MASK (0x400U)
#define SPDIF_SIS_URXFUL_SHIFT (10U)
/*! URxFul - URxFul
*/
#define SPDIF_SIS_URXFUL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_URXFUL_SHIFT)) & SPDIF_SIS_URXFUL_MASK)
#define SPDIF_SIS_BITERR_MASK (0x4000U)
#define SPDIF_SIS_BITERR_SHIFT (14U)
/*! BitErr - BitErr
*/
#define SPDIF_SIS_BITERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_BITERR_SHIFT)) & SPDIF_SIS_BITERR_MASK)
#define SPDIF_SIS_SYMERR_MASK (0x8000U)
#define SPDIF_SIS_SYMERR_SHIFT (15U)
/*! SymErr - SymErr
*/
#define SPDIF_SIS_SYMERR(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_SYMERR_SHIFT)) & SPDIF_SIS_SYMERR_MASK)
#define SPDIF_SIS_VALNOGOOD_MASK (0x10000U)
#define SPDIF_SIS_VALNOGOOD_SHIFT (16U)
/*! ValNoGood - ValNoGood
*/
#define SPDIF_SIS_VALNOGOOD(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_VALNOGOOD_SHIFT)) & SPDIF_SIS_VALNOGOOD_MASK)
#define SPDIF_SIS_CNEW_MASK (0x20000U)
#define SPDIF_SIS_CNEW_SHIFT (17U)
/*! CNew - CNew
*/
#define SPDIF_SIS_CNEW(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_CNEW_SHIFT)) & SPDIF_SIS_CNEW_MASK)
#define SPDIF_SIS_TXRESYN_MASK (0x40000U)
#define SPDIF_SIS_TXRESYN_SHIFT (18U)
/*! TxResyn - TxResyn
*/
#define SPDIF_SIS_TXRESYN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXRESYN_SHIFT)) & SPDIF_SIS_TXRESYN_MASK)
#define SPDIF_SIS_TXUNOV_MASK (0x80000U)
#define SPDIF_SIS_TXUNOV_SHIFT (19U)
/*! TxUnOv - TxUnOv
*/
#define SPDIF_SIS_TXUNOV(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_TXUNOV_SHIFT)) & SPDIF_SIS_TXUNOV_MASK)
#define SPDIF_SIS_LOCK_MASK (0x100000U)
#define SPDIF_SIS_LOCK_SHIFT (20U)
/*! Lock - Lock
*/
#define SPDIF_SIS_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SIS_LOCK_SHIFT)) & SPDIF_SIS_LOCK_MASK)
/*! @} */
/*! @name SRL - SPDIFRxLeft Register */
/*! @{ */
#define SPDIF_SRL_RXDATALEFT_MASK (0xFFFFFFU)
#define SPDIF_SRL_RXDATALEFT_SHIFT (0U)
/*! RxDataLeft - RxDataLeft
*/
#define SPDIF_SRL_RXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRL_RXDATALEFT_SHIFT)) & SPDIF_SRL_RXDATALEFT_MASK)
/*! @} */
/*! @name SRR - SPDIFRxRight Register */
/*! @{ */
#define SPDIF_SRR_RXDATARIGHT_MASK (0xFFFFFFU)
#define SPDIF_SRR_RXDATARIGHT_SHIFT (0U)
/*! RxDataRight - RxDataRight
*/
#define SPDIF_SRR_RXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRR_RXDATARIGHT_SHIFT)) & SPDIF_SRR_RXDATARIGHT_MASK)
/*! @} */
/*! @name SRCSH - SPDIFRxCChannel_h Register */
/*! @{ */
#define SPDIF_SRCSH_RXCCHANNEL_H_MASK (0xFFFFFFU)
#define SPDIF_SRCSH_RXCCHANNEL_H_SHIFT (0U)
/*! RxCChannel_h - RxCChannel_h
*/
#define SPDIF_SRCSH_RXCCHANNEL_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSH_RXCCHANNEL_H_SHIFT)) & SPDIF_SRCSH_RXCCHANNEL_H_MASK)
/*! @} */
/*! @name SRCSL - SPDIFRxCChannel_l Register */
/*! @{ */
#define SPDIF_SRCSL_RXCCHANNEL_L_MASK (0xFFFFFFU)
#define SPDIF_SRCSL_RXCCHANNEL_L_SHIFT (0U)
/*! RxCChannel_l - RxCChannel_l
*/
#define SPDIF_SRCSL_RXCCHANNEL_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRCSL_RXCCHANNEL_L_SHIFT)) & SPDIF_SRCSL_RXCCHANNEL_L_MASK)
/*! @} */
/*! @name SRU - UchannelRx Register */
/*! @{ */
#define SPDIF_SRU_RXUCHANNEL_MASK (0xFFFFFFU)
#define SPDIF_SRU_RXUCHANNEL_SHIFT (0U)
/*! RxUChannel - RxUChannel
*/
#define SPDIF_SRU_RXUCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRU_RXUCHANNEL_SHIFT)) & SPDIF_SRU_RXUCHANNEL_MASK)
/*! @} */
/*! @name SRQ - QchannelRx Register */
/*! @{ */
#define SPDIF_SRQ_RXQCHANNEL_MASK (0xFFFFFFU)
#define SPDIF_SRQ_RXQCHANNEL_SHIFT (0U)
/*! RxQChannel - RxQChannel
*/
#define SPDIF_SRQ_RXQCHANNEL(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRQ_RXQCHANNEL_SHIFT)) & SPDIF_SRQ_RXQCHANNEL_MASK)
/*! @} */
/*! @name STL - SPDIFTxLeft Register */
/*! @{ */
#define SPDIF_STL_TXDATALEFT_MASK (0xFFFFFFU)
#define SPDIF_STL_TXDATALEFT_SHIFT (0U)
/*! TxDataLeft - TxDataLeft
*/
#define SPDIF_STL_TXDATALEFT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STL_TXDATALEFT_SHIFT)) & SPDIF_STL_TXDATALEFT_MASK)
/*! @} */
/*! @name STR - SPDIFTxRight Register */
/*! @{ */
#define SPDIF_STR_TXDATARIGHT_MASK (0xFFFFFFU)
#define SPDIF_STR_TXDATARIGHT_SHIFT (0U)
/*! TxDataRight - TxDataRight
*/
#define SPDIF_STR_TXDATARIGHT(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STR_TXDATARIGHT_SHIFT)) & SPDIF_STR_TXDATARIGHT_MASK)
/*! @} */
/*! @name STCSCH - SPDIFTxCChannelCons_h Register */
/*! @{ */
#define SPDIF_STCSCH_TXCCHANNELCONS_H_MASK (0xFFFFFFU)
#define SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT (0U)
/*! TxCChannelCons_h - TxCChannelCons_h
*/
#define SPDIF_STCSCH_TXCCHANNELCONS_H(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCH_TXCCHANNELCONS_H_SHIFT)) & SPDIF_STCSCH_TXCCHANNELCONS_H_MASK)
/*! @} */
/*! @name STCSCL - SPDIFTxCChannelCons_l Register */
/*! @{ */
#define SPDIF_STCSCL_TXCCHANNELCONS_L_MASK (0xFFFFFFU)
#define SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT (0U)
/*! TxCChannelCons_l - TxCChannelCons_l
*/
#define SPDIF_STCSCL_TXCCHANNELCONS_L(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STCSCL_TXCCHANNELCONS_L_SHIFT)) & SPDIF_STCSCL_TXCCHANNELCONS_L_MASK)
/*! @} */
/*! @name SRFM - FreqMeas Register */
/*! @{ */
#define SPDIF_SRFM_FREQMEAS_MASK (0xFFFFFFU)
#define SPDIF_SRFM_FREQMEAS_SHIFT (0U)
/*! FreqMeas - FreqMeas
*/
#define SPDIF_SRFM_FREQMEAS(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_SRFM_FREQMEAS_SHIFT)) & SPDIF_SRFM_FREQMEAS_MASK)
/*! @} */
/*! @name STC - SPDIFTxClk Register */
/*! @{ */
#define SPDIF_STC_TXCLK_DF_MASK (0x7FU)
#define SPDIF_STC_TXCLK_DF_SHIFT (0U)
/*! TxClk_DF - TxClk_DF
* 0b0000000..divider factor is 1
* 0b0000001..divider factor is 2
* 0b1111111..divider factor is 128
*/
#define SPDIF_STC_TXCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_DF_SHIFT)) & SPDIF_STC_TXCLK_DF_MASK)
#define SPDIF_STC_TX_ALL_CLK_EN_MASK (0x80U)
#define SPDIF_STC_TX_ALL_CLK_EN_SHIFT (7U)
/*! tx_all_clk_en - tx_all_clk_en
* 0b0..disable transfer clock.
* 0b1..enable transfer clock.
*/
#define SPDIF_STC_TX_ALL_CLK_EN(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TX_ALL_CLK_EN_SHIFT)) & SPDIF_STC_TX_ALL_CLK_EN_MASK)
#define SPDIF_STC_TXCLK_SOURCE_MASK (0x700U)
#define SPDIF_STC_TXCLK_SOURCE_SHIFT (8U)
/*! TxClk_Source - TxClk_Source
* 0b000..REF_CLK_32K input (XTALOSC 32 kHz clock)
* 0b001..tx_clk input (from SPDIF0_CLK_ROOT. See clock control block for more information.)
* 0b011..SPDIF_EXT_CLK, from pads
* 0b101..ipg_clk input (frequency divided)
*/
#define SPDIF_STC_TXCLK_SOURCE(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_TXCLK_SOURCE_SHIFT)) & SPDIF_STC_TXCLK_SOURCE_MASK)
#define SPDIF_STC_SYSCLK_DF_MASK (0xFF800U)
#define SPDIF_STC_SYSCLK_DF_SHIFT (11U)
/*! SYSCLK_DF - SYSCLK_DF
* 0b000000000..no clock signal
* 0b000000001..divider factor is 2
* 0b111111111..divider factor is 512
*/
#define SPDIF_STC_SYSCLK_DF(x) (((uint32_t)(((uint32_t)(x)) << SPDIF_STC_SYSCLK_DF_SHIFT)) & SPDIF_STC_SYSCLK_DF_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SPDIF_Register_Masks */
/* SPDIF - Peripheral instance base addresses */
/** Peripheral SPDIF base address */
#define SPDIF_BASE (0x40400000u)
/** Peripheral SPDIF base pointer */
#define SPDIF ((SPDIF_Type *)SPDIF_BASE)
/** Array initializer of SPDIF peripheral base addresses */
#define SPDIF_BASE_ADDRS { SPDIF_BASE }
/** Array initializer of SPDIF peripheral base pointers */
#define SPDIF_BASE_PTRS { SPDIF }
/** Interrupt vectors for the SPDIF peripheral type */
#define SPDIF_IRQS { SPDIF_IRQn }
/*!
* @}
*/ /* end of group SPDIF_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SRAM Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SRAM_Peripheral_Access_Layer SRAM Peripheral Access Layer
* @{
*/
/** SRAM - Register Layout Typedef */
typedef struct {
uint8_t RESERVED_0[12288];
__IO uint32_t CTRL; /**< Control Register, offset: 0x3000 */
} SRAM_Type;
/* ----------------------------------------------------------------------------
-- SRAM Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SRAM_Register_Masks SRAM Register Masks
* @{
*/
/*! @name CTRL - Control Register */
/*! @{ */
#define SRAM_CTRL_RAM_RD_EN_MASK (0x1U)
#define SRAM_CTRL_RAM_RD_EN_SHIFT (0U)
/*! RAM_RD_EN - RAM Read Enable (with lock)
* 0b0..Disable read access
* 0b1..Enable read access
*/
#define SRAM_CTRL_RAM_RD_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_RD_EN_SHIFT)) & SRAM_CTRL_RAM_RD_EN_MASK)
#define SRAM_CTRL_RAM_WR_EN_MASK (0x2U)
#define SRAM_CTRL_RAM_WR_EN_SHIFT (1U)
/*! RAM_WR_EN - RAM Write Enable (with lock)
* 0b0..Disable write access
* 0b1..Enable write access
*/
#define SRAM_CTRL_RAM_WR_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_RAM_WR_EN_SHIFT)) & SRAM_CTRL_RAM_WR_EN_MASK)
#define SRAM_CTRL_PWR_EN_MASK (0x3CU)
#define SRAM_CTRL_PWR_EN_SHIFT (2U)
/*! PWR_EN - Power Enable (with lock)
*/
#define SRAM_CTRL_PWR_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_PWR_EN_SHIFT)) & SRAM_CTRL_PWR_EN_MASK)
#define SRAM_CTRL_TAMPER_BLOCK_EN_MASK (0x40U)
#define SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT (6U)
/*! TAMPER_BLOCK_EN - Tamper Block Enable (with lock)
* 0b0..Allow R/W access to secure RAM when tamper is detected
* 0b1..Block R/W access to secure RAM when tamper is detected
*/
#define SRAM_CTRL_TAMPER_BLOCK_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_BLOCK_EN_SHIFT)) & SRAM_CTRL_TAMPER_BLOCK_EN_MASK)
#define SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK (0x80U)
#define SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT (7U)
/*! TAMPER_PWR_OFF_EN - Turn off power on tamper event (with lock)
* 0b0..Disable the turn off function when tamper is detected
* 0b1..Turn off power for all secure RAM banks when tamper is detected
*/
#define SRAM_CTRL_TAMPER_PWR_OFF_EN(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_TAMPER_PWR_OFF_EN_SHIFT)) & SRAM_CTRL_TAMPER_PWR_OFF_EN_MASK)
#define SRAM_CTRL_LOCK_BIT_MASK (0xFF0000U)
#define SRAM_CTRL_LOCK_BIT_SHIFT (16U)
/*! LOCK_BIT - Lock bits
*/
#define SRAM_CTRL_LOCK_BIT(x) (((uint32_t)(((uint32_t)(x)) << SRAM_CTRL_LOCK_BIT_SHIFT)) & SRAM_CTRL_LOCK_BIT_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SRAM_Register_Masks */
/* SRAM - Peripheral instance base addresses */
/** Peripheral SRAM base address */
#define SRAM_BASE (0x40C9C000u)
/** Peripheral SRAM base pointer */
#define SRAM ((SRAM_Type *)SRAM_BASE)
/** Array initializer of SRAM peripheral base addresses */
#define SRAM_BASE_ADDRS { SRAM_BASE }
/** Array initializer of SRAM peripheral base pointers */
#define SRAM_BASE_PTRS { SRAM }
/*!
* @}
*/ /* end of group SRAM_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SRC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SRC_Peripheral_Access_Layer SRC Peripheral Access Layer
* @{
*/
/** SRC - Register Layout Typedef */
typedef struct {
__IO uint32_t SCR; /**< SRC Control Register, offset: 0x0 */
__IO uint32_t SRMR; /**< SRC Reset Mode Register, offset: 0x4 */
__I uint32_t SBMR1; /**< SRC Boot Mode Register 1, offset: 0x8 */
__I uint32_t SBMR2; /**< SRC Boot Mode Register 2, offset: 0xC */
__IO uint32_t SRSR; /**< SRC Reset Status Register, offset: 0x10 */
__IO uint32_t GPR[20]; /**< SRC General Purpose Register, array offset: 0x14, array step: 0x4 */
uint8_t RESERVED_0[412];
__IO uint32_t AUTHEN_MEGA; /**< Slice Authentication Register, offset: 0x200 */
__IO uint32_t CTRL_MEGA; /**< Slice Control Register, offset: 0x204 */
__IO uint32_t SETPOINT_MEGA; /**< Slice Setpoint Config Register, offset: 0x208 */
__IO uint32_t DOMAIN_MEGA; /**< Slice Domain Config Register, offset: 0x20C */
__IO uint32_t STAT_MEGA; /**< Slice Status Register, offset: 0x210 */
uint8_t RESERVED_1[12];
__IO uint32_t AUTHEN_DISPLAY; /**< Slice Authentication Register, offset: 0x220 */
__IO uint32_t CTRL_DISPLAY; /**< Slice Control Register, offset: 0x224 */
__IO uint32_t SETPOINT_DISPLAY; /**< Slice Setpoint Config Register, offset: 0x228 */
__IO uint32_t DOMAIN_DISPLAY; /**< Slice Domain Config Register, offset: 0x22C */
__IO uint32_t STAT_DISPLAY; /**< Slice Status Register, offset: 0x230 */
uint8_t RESERVED_2[12];
__IO uint32_t AUTHEN_WAKEUP; /**< Slice Authentication Register, offset: 0x240 */
__IO uint32_t CTRL_WAKEUP; /**< Slice Control Register, offset: 0x244 */
__IO uint32_t SETPOINT_WAKEUP; /**< Slice Setpoint Config Register, offset: 0x248 */
__IO uint32_t DOMAIN_WAKEUP; /**< Slice Domain Config Register, offset: 0x24C */
__IO uint32_t STAT_WAKEUP; /**< Slice Status Register, offset: 0x250 */
uint8_t RESERVED_3[44];
__IO uint32_t AUTHEN_M4CORE; /**< Slice Authentication Register, offset: 0x280 */
__IO uint32_t CTRL_M4CORE; /**< Slice Control Register, offset: 0x284 */
__IO uint32_t SETPOINT_M4CORE; /**< Slice Setpoint Config Register, offset: 0x288 */
__IO uint32_t DOMAIN_M4CORE; /**< Slice Domain Config Register, offset: 0x28C */
__IO uint32_t STAT_M4CORE; /**< Slice Status Register, offset: 0x290 */
uint8_t RESERVED_4[12];
__IO uint32_t AUTHEN_M7CORE; /**< Slice Authentication Register, offset: 0x2A0 */
__IO uint32_t CTRL_M7CORE; /**< Slice Control Register, offset: 0x2A4 */
__IO uint32_t SETPOINT_M7CORE; /**< Slice Setpoint Config Register, offset: 0x2A8 */
__IO uint32_t DOMAIN_M7CORE; /**< Slice Domain Config Register, offset: 0x2AC */
__IO uint32_t STAT_M7CORE; /**< Slice Status Register, offset: 0x2B0 */
uint8_t RESERVED_5[12];
__IO uint32_t AUTHEN_M4DEBUG; /**< Slice Authentication Register, offset: 0x2C0 */
__IO uint32_t CTRL_M4DEBUG; /**< Slice Control Register, offset: 0x2C4 */
__IO uint32_t SETPOINT_M4DEBUG; /**< Slice Setpoint Config Register, offset: 0x2C8 */
__IO uint32_t DOMAIN_M4DEBUG; /**< Slice Domain Config Register, offset: 0x2CC */
__IO uint32_t STAT_M4DEBUG; /**< Slice Status Register, offset: 0x2D0 */
uint8_t RESERVED_6[12];
__IO uint32_t AUTHEN_M7DEBUG; /**< Slice Authentication Register, offset: 0x2E0 */
__IO uint32_t CTRL_M7DEBUG; /**< Slice Control Register, offset: 0x2E4 */
__IO uint32_t SETPOINT_M7DEBUG; /**< Slice Setpoint Config Register, offset: 0x2E8 */
__IO uint32_t DOMAIN_M7DEBUG; /**< Slice Domain Config Register, offset: 0x2EC */
__IO uint32_t STAT_M7DEBUG; /**< Slice Status Register, offset: 0x2F0 */
uint8_t RESERVED_7[12];
__IO uint32_t AUTHEN_USBPHY1; /**< Slice Authentication Register, offset: 0x300 */
__IO uint32_t CTRL_USBPHY1; /**< Slice Control Register, offset: 0x304 */
__IO uint32_t SETPOINT_USBPHY1; /**< Slice Setpoint Config Register, offset: 0x308 */
__IO uint32_t DOMAIN_USBPHY1; /**< Slice Domain Config Register, offset: 0x30C */
__IO uint32_t STAT_USBPHY1; /**< Slice Status Register, offset: 0x310 */
uint8_t RESERVED_8[12];
__IO uint32_t AUTHEN_USBPHY2; /**< Slice Authentication Register, offset: 0x320 */
__IO uint32_t CTRL_USBPHY2; /**< Slice Control Register, offset: 0x324 */
__IO uint32_t SETPOINT_USBPHY2; /**< Slice Setpoint Config Register, offset: 0x328 */
__IO uint32_t DOMAIN_USBPHY2; /**< Slice Domain Config Register, offset: 0x32C */
__IO uint32_t STAT_USBPHY2; /**< Slice Status Register, offset: 0x330 */
} SRC_Type;
/* ----------------------------------------------------------------------------
-- SRC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SRC_Register_Masks SRC Register Masks
* @{
*/
/*! @name SCR - SRC Control Register */
/*! @{ */
#define SRC_SCR_BT_RELEASE_M4_MASK (0x1U)
#define SRC_SCR_BT_RELEASE_M4_SHIFT (0U)
/*! BT_RELEASE_M4
* 0b0..cm4 core reset is asserted
* 0b1..cm4 core reset is released
*/
#define SRC_SCR_BT_RELEASE_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M4_SHIFT)) & SRC_SCR_BT_RELEASE_M4_MASK)
#define SRC_SCR_BT_RELEASE_M7_MASK (0x2U)
#define SRC_SCR_BT_RELEASE_M7_SHIFT (1U)
/*! BT_RELEASE_M7
* 0b0..cm7 core reset is asserted
* 0b1..cm7 core reset is released
*/
#define SRC_SCR_BT_RELEASE_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SCR_BT_RELEASE_M7_SHIFT)) & SRC_SCR_BT_RELEASE_M7_MASK)
/*! @} */
/*! @name SRMR - SRC Reset Mode Register */
/*! @{ */
#define SRC_SRMR_WDOG_RESET_MODE_MASK (0x3U)
#define SRC_SRMR_WDOG_RESET_MODE_SHIFT (0U)
/*! WDOG_RESET_MODE - Wdog reset mode configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_WDOG_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG_RESET_MODE_MASK)
#define SRC_SRMR_WDOG3_RESET_MODE_MASK (0xCU)
#define SRC_SRMR_WDOG3_RESET_MODE_SHIFT (2U)
/*! WDOG3_RESET_MODE - Wdog3 reset mode configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_WDOG3_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG3_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG3_RESET_MODE_MASK)
#define SRC_SRMR_WDOG4_RESET_MODE_MASK (0x30U)
#define SRC_SRMR_WDOG4_RESET_MODE_SHIFT (4U)
/*! WDOG4_RESET_MODE - Wdog4 reset mode configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_WDOG4_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_WDOG4_RESET_MODE_SHIFT)) & SRC_SRMR_WDOG4_RESET_MODE_MASK)
#define SRC_SRMR_M4LOCKUP_RESET_MODE_MASK (0xC0U)
#define SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT (6U)
/*! M4LOCKUP_RESET_MODE - M4 core lockup reset mode configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_M4LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M4LOCKUP_RESET_MODE_MASK)
#define SRC_SRMR_M7LOCKUP_RESET_MODE_MASK (0x300U)
#define SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT (8U)
/*! M7LOCKUP_RESET_MODE - M7 core lockup reset mode configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_M7LOCKUP_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7LOCKUP_RESET_MODE_SHIFT)) & SRC_SRMR_M7LOCKUP_RESET_MODE_MASK)
#define SRC_SRMR_M4REQ_RESET_MODE_MASK (0xC00U)
#define SRC_SRMR_M4REQ_RESET_MODE_SHIFT (10U)
/*! M4REQ_RESET_MODE - M4 request reset configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_M4REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M4REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M4REQ_RESET_MODE_MASK)
#define SRC_SRMR_M7REQ_RESET_MODE_MASK (0x3000U)
#define SRC_SRMR_M7REQ_RESET_MODE_SHIFT (12U)
/*! M7REQ_RESET_MODE - M7 request reset configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_M7REQ_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_M7REQ_RESET_MODE_SHIFT)) & SRC_SRMR_M7REQ_RESET_MODE_MASK)
#define SRC_SRMR_TEMPSENSE_RESET_MODE_MASK (0xC000U)
#define SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT (14U)
/*! TEMPSENSE_RESET_MODE - Tempsense reset mode configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_TEMPSENSE_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_TEMPSENSE_RESET_MODE_SHIFT)) & SRC_SRMR_TEMPSENSE_RESET_MODE_MASK)
#define SRC_SRMR_CSU_RESET_MODE_MASK (0x30000U)
#define SRC_SRMR_CSU_RESET_MODE_SHIFT (16U)
/*! CSU_RESET_MODE - CSU reset mode configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_CSU_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_CSU_RESET_MODE_SHIFT)) & SRC_SRMR_CSU_RESET_MODE_MASK)
#define SRC_SRMR_JTAGSW_RESET_MODE_MASK (0xC0000U)
#define SRC_SRMR_JTAGSW_RESET_MODE_SHIFT (18U)
/*! JTAGSW_RESET_MODE - Jtag SW reset mode configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_JTAGSW_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_JTAGSW_RESET_MODE_SHIFT)) & SRC_SRMR_JTAGSW_RESET_MODE_MASK)
#define SRC_SRMR_OVERVOLT_RESET_MODE_MASK (0x300000U)
#define SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT (20U)
/*! OVERVOLT_RESET_MODE - Jtag SW reset mode configuration
* 0b00..reset system
* 0b01..reserved
* 0b10..reserved
* 0b11..do not reset anything
*/
#define SRC_SRMR_OVERVOLT_RESET_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRMR_OVERVOLT_RESET_MODE_SHIFT)) & SRC_SRMR_OVERVOLT_RESET_MODE_MASK)
/*! @} */
/*! @name SBMR1 - SRC Boot Mode Register 1 */
/*! @{ */
#define SRC_SBMR1_BOOT_CFG1_MASK (0xFFU)
#define SRC_SBMR1_BOOT_CFG1_SHIFT (0U)
#define SRC_SBMR1_BOOT_CFG1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG1_SHIFT)) & SRC_SBMR1_BOOT_CFG1_MASK)
#define SRC_SBMR1_BOOT_CFG2_MASK (0xFF00U)
#define SRC_SBMR1_BOOT_CFG2_SHIFT (8U)
#define SRC_SBMR1_BOOT_CFG2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG2_SHIFT)) & SRC_SBMR1_BOOT_CFG2_MASK)
#define SRC_SBMR1_BOOT_CFG3_MASK (0xFF0000U)
#define SRC_SBMR1_BOOT_CFG3_SHIFT (16U)
#define SRC_SBMR1_BOOT_CFG3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG3_SHIFT)) & SRC_SBMR1_BOOT_CFG3_MASK)
#define SRC_SBMR1_BOOT_CFG4_MASK (0xFF000000U)
#define SRC_SBMR1_BOOT_CFG4_SHIFT (24U)
#define SRC_SBMR1_BOOT_CFG4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR1_BOOT_CFG4_SHIFT)) & SRC_SBMR1_BOOT_CFG4_MASK)
/*! @} */
/*! @name SBMR2 - SRC Boot Mode Register 2 */
/*! @{ */
#define SRC_SBMR2_SEC_CONFIG_MASK (0x3U)
#define SRC_SBMR2_SEC_CONFIG_SHIFT (0U)
#define SRC_SBMR2_SEC_CONFIG(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_SEC_CONFIG_SHIFT)) & SRC_SBMR2_SEC_CONFIG_MASK)
#define SRC_SBMR2_BT_FUSE_SEL_MASK (0x10U)
#define SRC_SBMR2_BT_FUSE_SEL_SHIFT (4U)
#define SRC_SBMR2_BT_FUSE_SEL(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BT_FUSE_SEL_SHIFT)) & SRC_SBMR2_BT_FUSE_SEL_MASK)
#define SRC_SBMR2_BMOD_MASK (0x3000000U)
#define SRC_SBMR2_BMOD_SHIFT (24U)
#define SRC_SBMR2_BMOD(x) (((uint32_t)(((uint32_t)(x)) << SRC_SBMR2_BMOD_SHIFT)) & SRC_SBMR2_BMOD_MASK)
/*! @} */
/*! @name SRSR - SRC Reset Status Register */
/*! @{ */
#define SRC_SRSR_IPP_RESET_B_M7_MASK (0x1U)
#define SRC_SRSR_IPP_RESET_B_M7_SHIFT (0U)
/*! IPP_RESET_B_M7
* 0b0..Reset is not a result of ipp_reset_b pin.
* 0b1..Reset is a result of ipp_reset_b pin.
*/
#define SRC_SRSR_IPP_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_RESET_B_M7_MASK)
#define SRC_SRSR_M7_REQUEST_M7_MASK (0x2U)
#define SRC_SRSR_M7_REQUEST_M7_SHIFT (1U)
/*! M7_REQUEST_M7
* 0b0..Reset is not a result of m7 reset request.
* 0b1..Reset is a result of m7 reset request.
*/
#define SRC_SRSR_M7_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M7_SHIFT)) & SRC_SRSR_M7_REQUEST_M7_MASK)
#define SRC_SRSR_M7_LOCKUP_M7_MASK (0x4U)
#define SRC_SRSR_M7_LOCKUP_M7_SHIFT (2U)
/*! M7_LOCKUP_M7
* 0b0..Reset is not a result of the mentioned case.
* 0b1..Reset is a result of the mentioned case.
*/
#define SRC_SRSR_M7_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M7_SHIFT)) & SRC_SRSR_M7_LOCKUP_M7_MASK)
#define SRC_SRSR_CSU_RESET_B_M7_MASK (0x8U)
#define SRC_SRSR_CSU_RESET_B_M7_SHIFT (3U)
/*! CSU_RESET_B_M7
* 0b0..Reset is not a result of the csu_reset_b event.
* 0b1..Reset is a result of the csu_reset_b event.
*/
#define SRC_SRSR_CSU_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M7_SHIFT)) & SRC_SRSR_CSU_RESET_B_M7_MASK)
#define SRC_SRSR_IPP_USER_RESET_B_M7_MASK (0x10U)
#define SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT (4U)
/*! IPP_USER_RESET_B_M7
* 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
* 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
*/
#define SRC_SRSR_IPP_USER_RESET_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M7_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M7_MASK)
#define SRC_SRSR_WDOG_RST_B_M7_MASK (0x20U)
#define SRC_SRSR_WDOG_RST_B_M7_SHIFT (5U)
/*! WDOG_RST_B_M7
* 0b0..Reset is not a result of the watchdog time-out event.
* 0b1..Reset is a result of the watchdog time-out event.
*/
#define SRC_SRSR_WDOG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG_RST_B_M7_MASK)
#define SRC_SRSR_JTAG_RST_B_M7_MASK (0x40U)
#define SRC_SRSR_JTAG_RST_B_M7_SHIFT (6U)
/*! JTAG_RST_B_M7
* 0b0..Reset is not a result of HIGH-Z reset from JTAG.
* 0b1..Reset is a result of HIGH-Z reset from JTAG.
*/
#define SRC_SRSR_JTAG_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M7_SHIFT)) & SRC_SRSR_JTAG_RST_B_M7_MASK)
#define SRC_SRSR_JTAG_SW_RST_M7_MASK (0x80U)
#define SRC_SRSR_JTAG_SW_RST_M7_SHIFT (7U)
/*! JTAG_SW_RST_M7
* 0b0..Reset is not a result of software reset from JTAG.
* 0b1..Reset is a result of software reset from JTAG.
*/
#define SRC_SRSR_JTAG_SW_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M7_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M7_MASK)
#define SRC_SRSR_WDOG3_RST_B_M7_MASK (0x100U)
#define SRC_SRSR_WDOG3_RST_B_M7_SHIFT (8U)
/*! WDOG3_RST_B_M7
* 0b0..Reset is not a result of the watchdog3 time-out event.
* 0b1..Reset is a result of the watchdog3 time-out event.
*/
#define SRC_SRSR_WDOG3_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M7_MASK)
#define SRC_SRSR_WDOG4_RST_B_M7_MASK (0x200U)
#define SRC_SRSR_WDOG4_RST_B_M7_SHIFT (9U)
/*! WDOG4_RST_B_M7
* 0b0..Reset is not a result of the watchdog4 time-out event.
* 0b1..Reset is a result of the watchdog4 time-out event.
*/
#define SRC_SRSR_WDOG4_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M7_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M7_MASK)
#define SRC_SRSR_TEMPSENSE_RST_B_M7_MASK (0x400U)
#define SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT (10U)
/*! TEMPSENSE_RST_B_M7
* 0b0..Reset is not a result of software reset from Temperature Sensor.
* 0b1..Reset is a result of software reset from Temperature Sensor.
*/
#define SRC_SRSR_TEMPSENSE_RST_B_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M7_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M7_MASK)
#define SRC_SRSR_M4_REQUEST_M7_MASK (0x800U)
#define SRC_SRSR_M4_REQUEST_M7_SHIFT (11U)
/*! M4_REQUEST_M7
* 0b0..Reset is not a result of m4 reset request.
* 0b1..Reset is a result of m4 reset request.
*/
#define SRC_SRSR_M4_REQUEST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M7_SHIFT)) & SRC_SRSR_M4_REQUEST_M7_MASK)
#define SRC_SRSR_M4_LOCKUP_M7_MASK (0x1000U)
#define SRC_SRSR_M4_LOCKUP_M7_SHIFT (12U)
/*! M4_LOCKUP_M7
* 0b0..Reset is not a result of the mentioned case.
* 0b1..Reset is a result of the mentioned case.
*/
#define SRC_SRSR_M4_LOCKUP_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M7_SHIFT)) & SRC_SRSR_M4_LOCKUP_M7_MASK)
#define SRC_SRSR_OVERVOLT_RST_M7_MASK (0x2000U)
#define SRC_SRSR_OVERVOLT_RST_M7_SHIFT (13U)
/*! OVERVOLT_RST_M7
* 0b0..Reset is not a result of the mentioned case.
* 0b1..Reset is a result of the mentioned case.
*/
#define SRC_SRSR_OVERVOLT_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M7_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M7_MASK)
#define SRC_SRSR_CDOG_RST_M7_MASK (0x4000U)
#define SRC_SRSR_CDOG_RST_M7_SHIFT (14U)
/*! CDOG_RST_M7
* 0b0..Reset is not a result of the mentioned case.
* 0b1..Reset is a result of the mentioned case.
*/
#define SRC_SRSR_CDOG_RST_M7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M7_SHIFT)) & SRC_SRSR_CDOG_RST_M7_MASK)
#define SRC_SRSR_IPP_RESET_B_M4_MASK (0x10000U)
#define SRC_SRSR_IPP_RESET_B_M4_SHIFT (16U)
/*! IPP_RESET_B_M4
* 0b0..Reset is not a result of ipp_reset_b pin.
* 0b1..Reset is a result of ipp_reset_b pin.
*/
#define SRC_SRSR_IPP_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_RESET_B_M4_MASK)
#define SRC_SRSR_M4_REQUEST_M4_MASK (0x20000U)
#define SRC_SRSR_M4_REQUEST_M4_SHIFT (17U)
/*! M4_REQUEST_M4
* 0b0..Reset is not a result of m4 reset request.
* 0b1..Reset is a result of m4 reset request.
*/
#define SRC_SRSR_M4_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_REQUEST_M4_SHIFT)) & SRC_SRSR_M4_REQUEST_M4_MASK)
#define SRC_SRSR_M4_LOCKUP_M4_MASK (0x40000U)
#define SRC_SRSR_M4_LOCKUP_M4_SHIFT (18U)
/*! M4_LOCKUP_M4
* 0b0..Reset is not a result of the mentioned case.
* 0b1..Reset is a result of the mentioned case.
*/
#define SRC_SRSR_M4_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M4_LOCKUP_M4_SHIFT)) & SRC_SRSR_M4_LOCKUP_M4_MASK)
#define SRC_SRSR_CSU_RESET_B_M4_MASK (0x80000U)
#define SRC_SRSR_CSU_RESET_B_M4_SHIFT (19U)
/*! CSU_RESET_B_M4
* 0b0..Reset is not a result of the csu_reset_b event.
* 0b1..Reset is a result of the csu_reset_b event.
*/
#define SRC_SRSR_CSU_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CSU_RESET_B_M4_SHIFT)) & SRC_SRSR_CSU_RESET_B_M4_MASK)
#define SRC_SRSR_IPP_USER_RESET_B_M4_MASK (0x100000U)
#define SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT (20U)
/*! IPP_USER_RESET_B_M4
* 0b0..Reset is not a result of the ipp_user_reset_b qualified as COLD reset event.
* 0b1..Reset is a result of the ipp_user_reset_b qualified as COLD reset event.
*/
#define SRC_SRSR_IPP_USER_RESET_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_IPP_USER_RESET_B_M4_SHIFT)) & SRC_SRSR_IPP_USER_RESET_B_M4_MASK)
#define SRC_SRSR_WDOG_RST_B_M4_MASK (0x200000U)
#define SRC_SRSR_WDOG_RST_B_M4_SHIFT (21U)
/*! WDOG_RST_B_M4
* 0b0..Reset is not a result of the watchdog time-out event.
* 0b1..Reset is a result of the watchdog time-out event.
*/
#define SRC_SRSR_WDOG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG_RST_B_M4_MASK)
#define SRC_SRSR_JTAG_RST_B_M4_MASK (0x400000U)
#define SRC_SRSR_JTAG_RST_B_M4_SHIFT (22U)
/*! JTAG_RST_B_M4
* 0b0..Reset is not a result of HIGH-Z reset from JTAG.
* 0b1..Reset is a result of HIGH-Z reset from JTAG.
*/
#define SRC_SRSR_JTAG_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_RST_B_M4_SHIFT)) & SRC_SRSR_JTAG_RST_B_M4_MASK)
#define SRC_SRSR_JTAG_SW_RST_M4_MASK (0x800000U)
#define SRC_SRSR_JTAG_SW_RST_M4_SHIFT (23U)
/*! JTAG_SW_RST_M4
* 0b0..Reset is not a result of software reset from JTAG.
* 0b1..Reset is a result of software reset from JTAG.
*/
#define SRC_SRSR_JTAG_SW_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_JTAG_SW_RST_M4_SHIFT)) & SRC_SRSR_JTAG_SW_RST_M4_MASK)
#define SRC_SRSR_WDOG3_RST_B_M4_MASK (0x1000000U)
#define SRC_SRSR_WDOG3_RST_B_M4_SHIFT (24U)
/*! WDOG3_RST_B_M4
* 0b0..Reset is not a result of the watchdog3 time-out event.
* 0b1..Reset is a result of the watchdog3 time-out event.
*/
#define SRC_SRSR_WDOG3_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG3_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG3_RST_B_M4_MASK)
#define SRC_SRSR_WDOG4_RST_B_M4_MASK (0x2000000U)
#define SRC_SRSR_WDOG4_RST_B_M4_SHIFT (25U)
/*! WDOG4_RST_B_M4
* 0b0..Reset is not a result of the watchdog4 time-out event.
* 0b1..Reset is a result of the watchdog4 time-out event.
*/
#define SRC_SRSR_WDOG4_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_WDOG4_RST_B_M4_SHIFT)) & SRC_SRSR_WDOG4_RST_B_M4_MASK)
#define SRC_SRSR_TEMPSENSE_RST_B_M4_MASK (0x4000000U)
#define SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT (26U)
/*! TEMPSENSE_RST_B_M4
* 0b0..Reset is not a result of software reset from Temperature Sensor.
* 0b1..Reset is a result of software reset from Temperature Sensor.
*/
#define SRC_SRSR_TEMPSENSE_RST_B_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_TEMPSENSE_RST_B_M4_SHIFT)) & SRC_SRSR_TEMPSENSE_RST_B_M4_MASK)
#define SRC_SRSR_M7_REQUEST_M4_MASK (0x8000000U)
#define SRC_SRSR_M7_REQUEST_M4_SHIFT (27U)
/*! M7_REQUEST_M4
* 0b0..Reset is not a result of m7 reset request.
* 0b1..Reset is a result of m7 reset request.
*/
#define SRC_SRSR_M7_REQUEST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_REQUEST_M4_SHIFT)) & SRC_SRSR_M7_REQUEST_M4_MASK)
#define SRC_SRSR_M7_LOCKUP_M4_MASK (0x10000000U)
#define SRC_SRSR_M7_LOCKUP_M4_SHIFT (28U)
/*! M7_LOCKUP_M4
* 0b0..Reset is not a result of the mentioned case.
* 0b1..Reset is a result of the mentioned case.
*/
#define SRC_SRSR_M7_LOCKUP_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_M7_LOCKUP_M4_SHIFT)) & SRC_SRSR_M7_LOCKUP_M4_MASK)
#define SRC_SRSR_OVERVOLT_RST_M4_MASK (0x20000000U)
#define SRC_SRSR_OVERVOLT_RST_M4_SHIFT (29U)
/*! OVERVOLT_RST_M4
* 0b0..Reset is not a result of the mentioned case.
* 0b1..Reset is a result of the mentioned case.
*/
#define SRC_SRSR_OVERVOLT_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_OVERVOLT_RST_M4_SHIFT)) & SRC_SRSR_OVERVOLT_RST_M4_MASK)
#define SRC_SRSR_CDOG_RST_M4_MASK (0x40000000U)
#define SRC_SRSR_CDOG_RST_M4_SHIFT (30U)
/*! CDOG_RST_M4
* 0b0..Reset is not a result of the mentioned case.
* 0b1..Reset is a result of the mentioned case.
*/
#define SRC_SRSR_CDOG_RST_M4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SRSR_CDOG_RST_M4_SHIFT)) & SRC_SRSR_CDOG_RST_M4_MASK)
/*! @} */
/*! @name GPR - SRC General Purpose Register */
/*! @{ */
#define SRC_GPR_GPR_MASK (0xFFFFFFFFU)
#define SRC_GPR_GPR_SHIFT (0U)
/*! GPR - General Purpose Register.
*/
#define SRC_GPR_GPR(x) (((uint32_t)(((uint32_t)(x)) << SRC_GPR_GPR_SHIFT)) & SRC_GPR_GPR_MASK)
/*! @} */
/* The count of SRC_GPR */
#define SRC_GPR_COUNT (20U)
/*! @name AUTHEN_MEGA - Slice Authentication Register */
/*! @{ */
#define SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK (0x1U)
#define SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT (0U)
/*! DOMAIN_MODE
* 0b0..slice hardware reset will NOT be triggered by CPU power mode transition
* 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
*/
#define SRC_AUTHEN_MEGA_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_MEGA_DOMAIN_MODE_MASK)
#define SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK (0x2U)
#define SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT (1U)
/*! SETPOINT_MODE
* 0b0..slice hardware reset will NOT be triggered by Setpoint transition
* 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
*/
#define SRC_AUTHEN_MEGA_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_MEGA_SETPOINT_MODE_MASK)
#define SRC_AUTHEN_MEGA_LOCK_MODE_MASK (0x80U)
#define SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT (7U)
/*! LOCK_MODE - Domain/Setpoint mode lock
*/
#define SRC_AUTHEN_MEGA_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_MODE_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_MODE_MASK)
#define SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK (0xF00U)
#define SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT (8U)
#define SRC_AUTHEN_MEGA_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_MEGA_ASSIGN_LIST_MASK)
#define SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK (0x8000U)
#define SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT (15U)
/*! LOCK_ASSIGN - Assign list lock
*/
#define SRC_AUTHEN_MEGA_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_ASSIGN_MASK)
#define SRC_AUTHEN_MEGA_WHITE_LIST_MASK (0xF0000U)
#define SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT (16U)
/*! WHITE_LIST - Domain ID white list
*/
#define SRC_AUTHEN_MEGA_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_WHITE_LIST_SHIFT)) & SRC_AUTHEN_MEGA_WHITE_LIST_MASK)
#define SRC_AUTHEN_MEGA_LOCK_LIST_MASK (0x800000U)
#define SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT (23U)
/*! LOCK_LIST - White list lock
*/
#define SRC_AUTHEN_MEGA_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_LIST_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_LIST_MASK)
#define SRC_AUTHEN_MEGA_USER_MASK (0x1000000U)
#define SRC_AUTHEN_MEGA_USER_SHIFT (24U)
/*! USER - Allow user mode access
*/
#define SRC_AUTHEN_MEGA_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_USER_SHIFT)) & SRC_AUTHEN_MEGA_USER_MASK)
#define SRC_AUTHEN_MEGA_NONSECURE_MASK (0x2000000U)
#define SRC_AUTHEN_MEGA_NONSECURE_SHIFT (25U)
/*! NONSECURE - Allow non-secure mode access
*/
#define SRC_AUTHEN_MEGA_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_NONSECURE_SHIFT)) & SRC_AUTHEN_MEGA_NONSECURE_MASK)
#define SRC_AUTHEN_MEGA_LOCK_SETTING_MASK (0x80000000U)
#define SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT (31U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define SRC_AUTHEN_MEGA_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_MEGA_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_MEGA_LOCK_SETTING_MASK)
/*! @} */
/*! @name CTRL_MEGA - Slice Control Register */
/*! @{ */
#define SRC_CTRL_MEGA_SW_RESET_MASK (0x1U)
#define SRC_CTRL_MEGA_SW_RESET_SHIFT (0U)
/*! SW_RESET
* 0b0..do not assert slice software reset
* 0b1..assert slice software reset
*/
#define SRC_CTRL_MEGA_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_MEGA_SW_RESET_SHIFT)) & SRC_CTRL_MEGA_SW_RESET_MASK)
/*! @} */
/*! @name SETPOINT_MEGA - Slice Setpoint Config Register */
/*! @{ */
#define SRC_SETPOINT_MEGA_SETPOINT0_MASK (0x1U)
#define SRC_SETPOINT_MEGA_SETPOINT0_SHIFT (0U)
/*! SETPOINT0 - SETPOINT0
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT0_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT0_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT1_MASK (0x2U)
#define SRC_SETPOINT_MEGA_SETPOINT1_SHIFT (1U)
/*! SETPOINT1 - SETPOINT1
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT1_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT1_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT2_MASK (0x4U)
#define SRC_SETPOINT_MEGA_SETPOINT2_SHIFT (2U)
/*! SETPOINT2 - SETPOINT2
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT2_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT2_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT3_MASK (0x8U)
#define SRC_SETPOINT_MEGA_SETPOINT3_SHIFT (3U)
/*! SETPOINT3 - SETPOINT3
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT3_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT3_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT4_MASK (0x10U)
#define SRC_SETPOINT_MEGA_SETPOINT4_SHIFT (4U)
/*! SETPOINT4 - SETPOINT4
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT4_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT4_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT5_MASK (0x20U)
#define SRC_SETPOINT_MEGA_SETPOINT5_SHIFT (5U)
/*! SETPOINT5 - SETPOINT5
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT5_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT5_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT6_MASK (0x40U)
#define SRC_SETPOINT_MEGA_SETPOINT6_SHIFT (6U)
/*! SETPOINT6 - SETPOINT6
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT6_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT6_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT7_MASK (0x80U)
#define SRC_SETPOINT_MEGA_SETPOINT7_SHIFT (7U)
/*! SETPOINT7 - SETPOINT7
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT7_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT7_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT8_MASK (0x100U)
#define SRC_SETPOINT_MEGA_SETPOINT8_SHIFT (8U)
/*! SETPOINT8 - SETPOINT8
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT8_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT8_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT9_MASK (0x200U)
#define SRC_SETPOINT_MEGA_SETPOINT9_SHIFT (9U)
/*! SETPOINT9 - SETPOINT9
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT9_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT9_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT10_MASK (0x400U)
#define SRC_SETPOINT_MEGA_SETPOINT10_SHIFT (10U)
/*! SETPOINT10 - SETPOINT10
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT10_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT10_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT11_MASK (0x800U)
#define SRC_SETPOINT_MEGA_SETPOINT11_SHIFT (11U)
/*! SETPOINT11 - SETPOINT11
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT11_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT11_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT12_MASK (0x1000U)
#define SRC_SETPOINT_MEGA_SETPOINT12_SHIFT (12U)
/*! SETPOINT12 - SETPOINT12
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT12_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT12_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT13_MASK (0x2000U)
#define SRC_SETPOINT_MEGA_SETPOINT13_SHIFT (13U)
/*! SETPOINT13 - SETPOINT13
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT13_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT13_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT14_MASK (0x4000U)
#define SRC_SETPOINT_MEGA_SETPOINT14_SHIFT (14U)
/*! SETPOINT14 - SETPOINT14
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT14_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT14_MASK)
#define SRC_SETPOINT_MEGA_SETPOINT15_MASK (0x8000U)
#define SRC_SETPOINT_MEGA_SETPOINT15_SHIFT (15U)
/*! SETPOINT15 - SETPOINT15
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_MEGA_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_MEGA_SETPOINT15_SHIFT)) & SRC_SETPOINT_MEGA_SETPOINT15_MASK)
/*! @} */
/*! @name DOMAIN_MEGA - Slice Domain Config Register */
/*! @{ */
#define SRC_DOMAIN_MEGA_CPU0_RUN_MASK (0x1U)
#define SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT (0U)
/*! CPU0_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU0 in RUN mode
* 0b1..Slice reset will be asserted when CPU0 in RUN mode
*/
#define SRC_DOMAIN_MEGA_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_RUN_MASK)
#define SRC_DOMAIN_MEGA_CPU0_WAIT_MASK (0x2U)
#define SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT (1U)
/*! CPU0_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
* 0b1..Slice reset will be asserted when CPU0 in WAIT mode
*/
#define SRC_DOMAIN_MEGA_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_WAIT_MASK)
#define SRC_DOMAIN_MEGA_CPU0_STOP_MASK (0x4U)
#define SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT (2U)
/*! CPU0_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU0 in STOP mode
* 0b1..Slice reset will be asserted when CPU0 in STOP mode
*/
#define SRC_DOMAIN_MEGA_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_STOP_MASK)
#define SRC_DOMAIN_MEGA_CPU0_SUSP_MASK (0x8U)
#define SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT (3U)
/*! CPU0_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
*/
#define SRC_DOMAIN_MEGA_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU0_SUSP_MASK)
#define SRC_DOMAIN_MEGA_CPU1_RUN_MASK (0x10U)
#define SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT (4U)
/*! CPU1_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU1 in RUN mode
* 0b1..Slice reset will be asserted when CPU1 in RUN mode
*/
#define SRC_DOMAIN_MEGA_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_RUN_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_RUN_MASK)
#define SRC_DOMAIN_MEGA_CPU1_WAIT_MASK (0x20U)
#define SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT (5U)
/*! CPU1_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
* 0b1..Slice reset will be asserted when CPU1 in WAIT mode
*/
#define SRC_DOMAIN_MEGA_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_WAIT_MASK)
#define SRC_DOMAIN_MEGA_CPU1_STOP_MASK (0x40U)
#define SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT (6U)
/*! CPU1_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU1 in STOP mode
* 0b1..Slice reset will be asserted when CPU1 in STOP mode
*/
#define SRC_DOMAIN_MEGA_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_STOP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_STOP_MASK)
#define SRC_DOMAIN_MEGA_CPU1_SUSP_MASK (0x80U)
#define SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT (7U)
/*! CPU1_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
*/
#define SRC_DOMAIN_MEGA_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_MEGA_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_MEGA_CPU1_SUSP_MASK)
/*! @} */
/*! @name STAT_MEGA - Slice Status Register */
/*! @{ */
#define SRC_STAT_MEGA_UNDER_RST_MASK (0x1U)
#define SRC_STAT_MEGA_UNDER_RST_SHIFT (0U)
/*! UNDER_RST
* 0b0..the reset is finished
* 0b1..the reset is in process
*/
#define SRC_STAT_MEGA_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_UNDER_RST_SHIFT)) & SRC_STAT_MEGA_UNDER_RST_MASK)
#define SRC_STAT_MEGA_RST_BY_HW_MASK (0x4U)
#define SRC_STAT_MEGA_RST_BY_HW_SHIFT (2U)
/*! RST_BY_HW
* 0b0..the reset is not caused by the power mode transfer
* 0b1..the reset is caused by the power mode transfer
*/
#define SRC_STAT_MEGA_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_HW_SHIFT)) & SRC_STAT_MEGA_RST_BY_HW_MASK)
#define SRC_STAT_MEGA_RST_BY_SW_MASK (0x8U)
#define SRC_STAT_MEGA_RST_BY_SW_SHIFT (3U)
/*! RST_BY_SW
* 0b0..the reset is not caused by software setting
* 0b1..the reset is caused by software setting
*/
#define SRC_STAT_MEGA_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_MEGA_RST_BY_SW_SHIFT)) & SRC_STAT_MEGA_RST_BY_SW_MASK)
/*! @} */
/*! @name AUTHEN_DISPLAY - Slice Authentication Register */
/*! @{ */
#define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK (0x1U)
#define SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT (0U)
/*! DOMAIN_MODE
* 0b0..slice hardware reset will NOT be triggered by CPU power mode transition
* 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
*/
#define SRC_AUTHEN_DISPLAY_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_DOMAIN_MODE_MASK)
#define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK (0x2U)
#define SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT (1U)
/*! SETPOINT_MODE
* 0b0..slice hardware reset will NOT be triggered by Setpoint transition
* 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
*/
#define SRC_AUTHEN_DISPLAY_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_SETPOINT_MODE_MASK)
#define SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK (0x80U)
#define SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT (7U)
/*! LOCK_MODE - Domain/Setpoint mode lock
*/
#define SRC_AUTHEN_DISPLAY_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_MODE_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_MODE_MASK)
#define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK (0xF00U)
#define SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT (8U)
#define SRC_AUTHEN_DISPLAY_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_ASSIGN_LIST_MASK)
#define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK (0x8000U)
#define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT (15U)
/*! LOCK_ASSIGN - Assign list lock
*/
#define SRC_AUTHEN_DISPLAY_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_ASSIGN_MASK)
#define SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK (0xF0000U)
#define SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT (16U)
/*! WHITE_LIST - Domain ID white list
*/
#define SRC_AUTHEN_DISPLAY_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_WHITE_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_WHITE_LIST_MASK)
#define SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK (0x800000U)
#define SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT (23U)
/*! LOCK_LIST - White list lock
*/
#define SRC_AUTHEN_DISPLAY_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_LIST_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_LIST_MASK)
#define SRC_AUTHEN_DISPLAY_USER_MASK (0x1000000U)
#define SRC_AUTHEN_DISPLAY_USER_SHIFT (24U)
/*! USER - Allow user mode access
*/
#define SRC_AUTHEN_DISPLAY_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_USER_SHIFT)) & SRC_AUTHEN_DISPLAY_USER_MASK)
#define SRC_AUTHEN_DISPLAY_NONSECURE_MASK (0x2000000U)
#define SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT (25U)
/*! NONSECURE - Allow non-secure mode access
*/
#define SRC_AUTHEN_DISPLAY_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_NONSECURE_SHIFT)) & SRC_AUTHEN_DISPLAY_NONSECURE_MASK)
#define SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK (0x80000000U)
#define SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT (31U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define SRC_AUTHEN_DISPLAY_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_DISPLAY_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_DISPLAY_LOCK_SETTING_MASK)
/*! @} */
/*! @name CTRL_DISPLAY - Slice Control Register */
/*! @{ */
#define SRC_CTRL_DISPLAY_SW_RESET_MASK (0x1U)
#define SRC_CTRL_DISPLAY_SW_RESET_SHIFT (0U)
/*! SW_RESET
* 0b0..do not assert slice software reset
* 0b1..assert slice software reset
*/
#define SRC_CTRL_DISPLAY_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_DISPLAY_SW_RESET_SHIFT)) & SRC_CTRL_DISPLAY_SW_RESET_MASK)
/*! @} */
/*! @name SETPOINT_DISPLAY - Slice Setpoint Config Register */
/*! @{ */
#define SRC_SETPOINT_DISPLAY_SETPOINT0_MASK (0x1U)
#define SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT (0U)
/*! SETPOINT0 - SETPOINT0
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT0_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT0_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT1_MASK (0x2U)
#define SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT (1U)
/*! SETPOINT1 - SETPOINT1
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT1_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT1_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT2_MASK (0x4U)
#define SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT (2U)
/*! SETPOINT2 - SETPOINT2
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT2_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT2_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT3_MASK (0x8U)
#define SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT (3U)
/*! SETPOINT3 - SETPOINT3
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT3_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT3_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT4_MASK (0x10U)
#define SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT (4U)
/*! SETPOINT4 - SETPOINT4
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT4_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT4_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT5_MASK (0x20U)
#define SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT (5U)
/*! SETPOINT5 - SETPOINT5
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT5_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT5_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT6_MASK (0x40U)
#define SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT (6U)
/*! SETPOINT6 - SETPOINT6
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT6_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT6_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT7_MASK (0x80U)
#define SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT (7U)
/*! SETPOINT7 - SETPOINT7
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT7_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT7_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT8_MASK (0x100U)
#define SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT (8U)
/*! SETPOINT8 - SETPOINT8
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT8_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT8_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT9_MASK (0x200U)
#define SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT (9U)
/*! SETPOINT9 - SETPOINT9
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT9_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT9_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT10_MASK (0x400U)
#define SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT (10U)
/*! SETPOINT10 - SETPOINT10
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT10_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT10_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT11_MASK (0x800U)
#define SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT (11U)
/*! SETPOINT11 - SETPOINT11
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT11_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT11_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT12_MASK (0x1000U)
#define SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT (12U)
/*! SETPOINT12 - SETPOINT12
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT12_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT12_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT13_MASK (0x2000U)
#define SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT (13U)
/*! SETPOINT13 - SETPOINT13
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT13_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT13_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT14_MASK (0x4000U)
#define SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT (14U)
/*! SETPOINT14 - SETPOINT14
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT14_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT14_MASK)
#define SRC_SETPOINT_DISPLAY_SETPOINT15_MASK (0x8000U)
#define SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT (15U)
/*! SETPOINT15 - SETPOINT15
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_DISPLAY_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_DISPLAY_SETPOINT15_SHIFT)) & SRC_SETPOINT_DISPLAY_SETPOINT15_MASK)
/*! @} */
/*! @name DOMAIN_DISPLAY - Slice Domain Config Register */
/*! @{ */
#define SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK (0x1U)
#define SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT (0U)
/*! CPU0_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU0 in RUN mode
* 0b1..Slice reset will be asserted when CPU0 in RUN mode
*/
#define SRC_DOMAIN_DISPLAY_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_RUN_MASK)
#define SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK (0x2U)
#define SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT (1U)
/*! CPU0_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
* 0b1..Slice reset will be asserted when CPU0 in WAIT mode
*/
#define SRC_DOMAIN_DISPLAY_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_WAIT_MASK)
#define SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK (0x4U)
#define SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT (2U)
/*! CPU0_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU0 in STOP mode
* 0b1..Slice reset will be asserted when CPU0 in STOP mode
*/
#define SRC_DOMAIN_DISPLAY_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_STOP_MASK)
#define SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK (0x8U)
#define SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT (3U)
/*! CPU0_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
*/
#define SRC_DOMAIN_DISPLAY_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU0_SUSP_MASK)
#define SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK (0x10U)
#define SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT (4U)
/*! CPU1_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU1 in RUN mode
* 0b1..Slice reset will be asserted when CPU1 in RUN mode
*/
#define SRC_DOMAIN_DISPLAY_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_RUN_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_RUN_MASK)
#define SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK (0x20U)
#define SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT (5U)
/*! CPU1_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
* 0b1..Slice reset will be asserted when CPU1 in WAIT mode
*/
#define SRC_DOMAIN_DISPLAY_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_WAIT_MASK)
#define SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK (0x40U)
#define SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT (6U)
/*! CPU1_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU1 in STOP mode
* 0b1..Slice reset will be asserted when CPU1 in STOP mode
*/
#define SRC_DOMAIN_DISPLAY_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_STOP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_STOP_MASK)
#define SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK (0x80U)
#define SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT (7U)
/*! CPU1_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
*/
#define SRC_DOMAIN_DISPLAY_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_DISPLAY_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_DISPLAY_CPU1_SUSP_MASK)
/*! @} */
/*! @name STAT_DISPLAY - Slice Status Register */
/*! @{ */
#define SRC_STAT_DISPLAY_UNDER_RST_MASK (0x1U)
#define SRC_STAT_DISPLAY_UNDER_RST_SHIFT (0U)
/*! UNDER_RST
* 0b0..the reset is finished
* 0b1..the reset is in process
*/
#define SRC_STAT_DISPLAY_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_UNDER_RST_SHIFT)) & SRC_STAT_DISPLAY_UNDER_RST_MASK)
#define SRC_STAT_DISPLAY_RST_BY_HW_MASK (0x4U)
#define SRC_STAT_DISPLAY_RST_BY_HW_SHIFT (2U)
/*! RST_BY_HW
* 0b0..the reset is not caused by the power mode transfer
* 0b1..the reset is caused by the power mode transfer
*/
#define SRC_STAT_DISPLAY_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_HW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_HW_MASK)
#define SRC_STAT_DISPLAY_RST_BY_SW_MASK (0x8U)
#define SRC_STAT_DISPLAY_RST_BY_SW_SHIFT (3U)
/*! RST_BY_SW
* 0b0..the reset is not caused by software setting
* 0b1..the reset is caused by software setting
*/
#define SRC_STAT_DISPLAY_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_DISPLAY_RST_BY_SW_SHIFT)) & SRC_STAT_DISPLAY_RST_BY_SW_MASK)
/*! @} */
/*! @name AUTHEN_WAKEUP - Slice Authentication Register */
/*! @{ */
#define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK (0x1U)
#define SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT (0U)
/*! DOMAIN_MODE
* 0b0..slice hardware reset will NOT be triggered by CPU power mode transition
* 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
*/
#define SRC_AUTHEN_WAKEUP_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_DOMAIN_MODE_MASK)
#define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK (0x2U)
#define SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT (1U)
/*! SETPOINT_MODE
* 0b0..slice hardware reset will NOT be triggered by Setpoint transition
* 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
*/
#define SRC_AUTHEN_WAKEUP_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_SETPOINT_MODE_MASK)
#define SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK (0x80U)
#define SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT (7U)
/*! LOCK_MODE - Domain/Setpoint mode lock
*/
#define SRC_AUTHEN_WAKEUP_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_MODE_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_MODE_MASK)
#define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK (0xF00U)
#define SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT (8U)
#define SRC_AUTHEN_WAKEUP_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_ASSIGN_LIST_MASK)
#define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK (0x8000U)
#define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT (15U)
/*! LOCK_ASSIGN - Assign list lock
*/
#define SRC_AUTHEN_WAKEUP_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_ASSIGN_MASK)
#define SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK (0xF0000U)
#define SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT (16U)
/*! WHITE_LIST - Domain ID white list
*/
#define SRC_AUTHEN_WAKEUP_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_WHITE_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_WHITE_LIST_MASK)
#define SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK (0x800000U)
#define SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT (23U)
/*! LOCK_LIST - White list lock
*/
#define SRC_AUTHEN_WAKEUP_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_LIST_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_LIST_MASK)
#define SRC_AUTHEN_WAKEUP_USER_MASK (0x1000000U)
#define SRC_AUTHEN_WAKEUP_USER_SHIFT (24U)
/*! USER - Allow user mode access
*/
#define SRC_AUTHEN_WAKEUP_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_USER_SHIFT)) & SRC_AUTHEN_WAKEUP_USER_MASK)
#define SRC_AUTHEN_WAKEUP_NONSECURE_MASK (0x2000000U)
#define SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT (25U)
/*! NONSECURE - Allow non-secure mode access
*/
#define SRC_AUTHEN_WAKEUP_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_NONSECURE_SHIFT)) & SRC_AUTHEN_WAKEUP_NONSECURE_MASK)
#define SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK (0x80000000U)
#define SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT (31U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define SRC_AUTHEN_WAKEUP_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_WAKEUP_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_WAKEUP_LOCK_SETTING_MASK)
/*! @} */
/*! @name CTRL_WAKEUP - Slice Control Register */
/*! @{ */
#define SRC_CTRL_WAKEUP_SW_RESET_MASK (0x1U)
#define SRC_CTRL_WAKEUP_SW_RESET_SHIFT (0U)
/*! SW_RESET
* 0b0..do not assert slice software reset
* 0b1..assert slice software reset
*/
#define SRC_CTRL_WAKEUP_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_WAKEUP_SW_RESET_SHIFT)) & SRC_CTRL_WAKEUP_SW_RESET_MASK)
/*! @} */
/*! @name SETPOINT_WAKEUP - Slice Setpoint Config Register */
/*! @{ */
#define SRC_SETPOINT_WAKEUP_SETPOINT0_MASK (0x1U)
#define SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT (0U)
/*! SETPOINT0 - SETPOINT0
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT0_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT0_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT1_MASK (0x2U)
#define SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT (1U)
/*! SETPOINT1 - SETPOINT1
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT1_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT1_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT2_MASK (0x4U)
#define SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT (2U)
/*! SETPOINT2 - SETPOINT2
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT2_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT2_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT3_MASK (0x8U)
#define SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT (3U)
/*! SETPOINT3 - SETPOINT3
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT3_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT3_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT4_MASK (0x10U)
#define SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT (4U)
/*! SETPOINT4 - SETPOINT4
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT4_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT4_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT5_MASK (0x20U)
#define SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT (5U)
/*! SETPOINT5 - SETPOINT5
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT5_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT5_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT6_MASK (0x40U)
#define SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT (6U)
/*! SETPOINT6 - SETPOINT6
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT6_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT6_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT7_MASK (0x80U)
#define SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT (7U)
/*! SETPOINT7 - SETPOINT7
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT7_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT7_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT8_MASK (0x100U)
#define SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT (8U)
/*! SETPOINT8 - SETPOINT8
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT8_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT8_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT9_MASK (0x200U)
#define SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT (9U)
/*! SETPOINT9 - SETPOINT9
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT9_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT9_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT10_MASK (0x400U)
#define SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT (10U)
/*! SETPOINT10 - SETPOINT10
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT10_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT10_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT11_MASK (0x800U)
#define SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT (11U)
/*! SETPOINT11 - SETPOINT11
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT11_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT11_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT12_MASK (0x1000U)
#define SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT (12U)
/*! SETPOINT12 - SETPOINT12
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT12_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT12_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT13_MASK (0x2000U)
#define SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT (13U)
/*! SETPOINT13 - SETPOINT13
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT13_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT13_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT14_MASK (0x4000U)
#define SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT (14U)
/*! SETPOINT14 - SETPOINT14
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT14_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT14_MASK)
#define SRC_SETPOINT_WAKEUP_SETPOINT15_MASK (0x8000U)
#define SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT (15U)
/*! SETPOINT15 - SETPOINT15
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_WAKEUP_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_WAKEUP_SETPOINT15_SHIFT)) & SRC_SETPOINT_WAKEUP_SETPOINT15_MASK)
/*! @} */
/*! @name DOMAIN_WAKEUP - Slice Domain Config Register */
/*! @{ */
#define SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK (0x1U)
#define SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT (0U)
/*! CPU0_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU0 in RUN mode
* 0b1..Slice reset will be asserted when CPU0 in RUN mode
*/
#define SRC_DOMAIN_WAKEUP_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_RUN_MASK)
#define SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK (0x2U)
#define SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT (1U)
/*! CPU0_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
* 0b1..Slice reset will be asserted when CPU0 in WAIT mode
*/
#define SRC_DOMAIN_WAKEUP_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_WAIT_MASK)
#define SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK (0x4U)
#define SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT (2U)
/*! CPU0_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU0 in STOP mode
* 0b1..Slice reset will be asserted when CPU0 in STOP mode
*/
#define SRC_DOMAIN_WAKEUP_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_STOP_MASK)
#define SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK (0x8U)
#define SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT (3U)
/*! CPU0_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
*/
#define SRC_DOMAIN_WAKEUP_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU0_SUSP_MASK)
#define SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK (0x10U)
#define SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT (4U)
/*! CPU1_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU1 in RUN mode
* 0b1..Slice reset will be asserted when CPU1 in RUN mode
*/
#define SRC_DOMAIN_WAKEUP_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_RUN_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_RUN_MASK)
#define SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK (0x20U)
#define SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT (5U)
/*! CPU1_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
* 0b1..Slice reset will be asserted when CPU1 in WAIT mode
*/
#define SRC_DOMAIN_WAKEUP_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_WAIT_MASK)
#define SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK (0x40U)
#define SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT (6U)
/*! CPU1_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU1 in STOP mode
* 0b1..Slice reset will be asserted when CPU1 in STOP mode
*/
#define SRC_DOMAIN_WAKEUP_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_STOP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_STOP_MASK)
#define SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK (0x80U)
#define SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT (7U)
/*! CPU1_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
*/
#define SRC_DOMAIN_WAKEUP_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_WAKEUP_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_WAKEUP_CPU1_SUSP_MASK)
/*! @} */
/*! @name STAT_WAKEUP - Slice Status Register */
/*! @{ */
#define SRC_STAT_WAKEUP_UNDER_RST_MASK (0x1U)
#define SRC_STAT_WAKEUP_UNDER_RST_SHIFT (0U)
/*! UNDER_RST
* 0b0..the reset is finished
* 0b1..the reset is in process
*/
#define SRC_STAT_WAKEUP_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_UNDER_RST_SHIFT)) & SRC_STAT_WAKEUP_UNDER_RST_MASK)
#define SRC_STAT_WAKEUP_RST_BY_HW_MASK (0x4U)
#define SRC_STAT_WAKEUP_RST_BY_HW_SHIFT (2U)
/*! RST_BY_HW
* 0b0..the reset is not caused by the power mode transfer
* 0b1..the reset is caused by the power mode transfer
*/
#define SRC_STAT_WAKEUP_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_HW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_HW_MASK)
#define SRC_STAT_WAKEUP_RST_BY_SW_MASK (0x8U)
#define SRC_STAT_WAKEUP_RST_BY_SW_SHIFT (3U)
/*! RST_BY_SW
* 0b0..the reset is not caused by software setting
* 0b1..the reset is caused by software setting
*/
#define SRC_STAT_WAKEUP_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_WAKEUP_RST_BY_SW_SHIFT)) & SRC_STAT_WAKEUP_RST_BY_SW_MASK)
/*! @} */
/*! @name AUTHEN_M4CORE - Slice Authentication Register */
/*! @{ */
#define SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK (0x1U)
#define SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT (0U)
/*! DOMAIN_MODE
* 0b0..slice hardware reset will NOT be triggered by CPU power mode transition
* 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
*/
#define SRC_AUTHEN_M4CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_DOMAIN_MODE_MASK)
#define SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK (0x2U)
#define SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT (1U)
/*! SETPOINT_MODE
* 0b0..slice hardware reset will NOT be triggered by Setpoint transition
* 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
*/
#define SRC_AUTHEN_M4CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_SETPOINT_MODE_MASK)
#define SRC_AUTHEN_M4CORE_LOCK_MODE_MASK (0x80U)
#define SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT (7U)
/*! LOCK_MODE - Domain/Setpoint mode lock
*/
#define SRC_AUTHEN_M4CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_MODE_MASK)
#define SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK (0xF00U)
#define SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT (8U)
#define SRC_AUTHEN_M4CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_ASSIGN_LIST_MASK)
#define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK (0x8000U)
#define SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT (15U)
/*! LOCK_ASSIGN - Assign list lock
*/
#define SRC_AUTHEN_M4CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_ASSIGN_MASK)
#define SRC_AUTHEN_M4CORE_WHITE_LIST_MASK (0xF0000U)
#define SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT (16U)
/*! WHITE_LIST - Domain ID white list
*/
#define SRC_AUTHEN_M4CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_WHITE_LIST_MASK)
#define SRC_AUTHEN_M4CORE_LOCK_LIST_MASK (0x800000U)
#define SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT (23U)
/*! LOCK_LIST - White list lock
*/
#define SRC_AUTHEN_M4CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_LIST_MASK)
#define SRC_AUTHEN_M4CORE_USER_MASK (0x1000000U)
#define SRC_AUTHEN_M4CORE_USER_SHIFT (24U)
/*! USER - Allow user mode access
*/
#define SRC_AUTHEN_M4CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_USER_SHIFT)) & SRC_AUTHEN_M4CORE_USER_MASK)
#define SRC_AUTHEN_M4CORE_NONSECURE_MASK (0x2000000U)
#define SRC_AUTHEN_M4CORE_NONSECURE_SHIFT (25U)
/*! NONSECURE - Allow non-secure mode access
*/
#define SRC_AUTHEN_M4CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M4CORE_NONSECURE_MASK)
#define SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK (0x80000000U)
#define SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT (31U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define SRC_AUTHEN_M4CORE_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4CORE_LOCK_SETTING_MASK)
/*! @} */
/*! @name CTRL_M4CORE - Slice Control Register */
/*! @{ */
#define SRC_CTRL_M4CORE_SW_RESET_MASK (0x1U)
#define SRC_CTRL_M4CORE_SW_RESET_SHIFT (0U)
/*! SW_RESET
* 0b0..do not assert slice software reset
* 0b1..assert slice software reset
*/
#define SRC_CTRL_M4CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4CORE_SW_RESET_SHIFT)) & SRC_CTRL_M4CORE_SW_RESET_MASK)
/*! @} */
/*! @name SETPOINT_M4CORE - Slice Setpoint Config Register */
/*! @{ */
#define SRC_SETPOINT_M4CORE_SETPOINT0_MASK (0x1U)
#define SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT (0U)
/*! SETPOINT0 - SETPOINT0
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT0_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT1_MASK (0x2U)
#define SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT (1U)
/*! SETPOINT1 - SETPOINT1
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT1_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT2_MASK (0x4U)
#define SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT (2U)
/*! SETPOINT2 - SETPOINT2
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT2_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT3_MASK (0x8U)
#define SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT (3U)
/*! SETPOINT3 - SETPOINT3
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT3_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT4_MASK (0x10U)
#define SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT (4U)
/*! SETPOINT4 - SETPOINT4
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT4_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT5_MASK (0x20U)
#define SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT (5U)
/*! SETPOINT5 - SETPOINT5
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT5_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT6_MASK (0x40U)
#define SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT (6U)
/*! SETPOINT6 - SETPOINT6
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT6_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT7_MASK (0x80U)
#define SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT (7U)
/*! SETPOINT7 - SETPOINT7
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT7_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT8_MASK (0x100U)
#define SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT (8U)
/*! SETPOINT8 - SETPOINT8
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT8_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT9_MASK (0x200U)
#define SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT (9U)
/*! SETPOINT9 - SETPOINT9
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT9_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT10_MASK (0x400U)
#define SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT (10U)
/*! SETPOINT10 - SETPOINT10
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT10_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT11_MASK (0x800U)
#define SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT (11U)
/*! SETPOINT11 - SETPOINT11
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT11_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT12_MASK (0x1000U)
#define SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT (12U)
/*! SETPOINT12 - SETPOINT12
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT12_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT13_MASK (0x2000U)
#define SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT (13U)
/*! SETPOINT13 - SETPOINT13
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT13_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT14_MASK (0x4000U)
#define SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT (14U)
/*! SETPOINT14 - SETPOINT14
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT14_MASK)
#define SRC_SETPOINT_M4CORE_SETPOINT15_MASK (0x8000U)
#define SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT (15U)
/*! SETPOINT15 - SETPOINT15
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4CORE_SETPOINT15_MASK)
/*! @} */
/*! @name DOMAIN_M4CORE - Slice Domain Config Register */
/*! @{ */
#define SRC_DOMAIN_M4CORE_CPU0_RUN_MASK (0x1U)
#define SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT (0U)
/*! CPU0_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU0 in RUN mode
* 0b1..Slice reset will be asserted when CPU0 in RUN mode
*/
#define SRC_DOMAIN_M4CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_RUN_MASK)
#define SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK (0x2U)
#define SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT (1U)
/*! CPU0_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
* 0b1..Slice reset will be asserted when CPU0 in WAIT mode
*/
#define SRC_DOMAIN_M4CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_WAIT_MASK)
#define SRC_DOMAIN_M4CORE_CPU0_STOP_MASK (0x4U)
#define SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT (2U)
/*! CPU0_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU0 in STOP mode
* 0b1..Slice reset will be asserted when CPU0 in STOP mode
*/
#define SRC_DOMAIN_M4CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_STOP_MASK)
#define SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK (0x8U)
#define SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT (3U)
/*! CPU0_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
*/
#define SRC_DOMAIN_M4CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU0_SUSP_MASK)
#define SRC_DOMAIN_M4CORE_CPU1_RUN_MASK (0x10U)
#define SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT (4U)
/*! CPU1_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU1 in RUN mode
* 0b1..Slice reset will be asserted when CPU1 in RUN mode
*/
#define SRC_DOMAIN_M4CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_RUN_MASK)
#define SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK (0x20U)
#define SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT (5U)
/*! CPU1_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
* 0b1..Slice reset will be asserted when CPU1 in WAIT mode
*/
#define SRC_DOMAIN_M4CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_WAIT_MASK)
#define SRC_DOMAIN_M4CORE_CPU1_STOP_MASK (0x40U)
#define SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT (6U)
/*! CPU1_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU1 in STOP mode
* 0b1..Slice reset will be asserted when CPU1 in STOP mode
*/
#define SRC_DOMAIN_M4CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_STOP_MASK)
#define SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK (0x80U)
#define SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT (7U)
/*! CPU1_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
*/
#define SRC_DOMAIN_M4CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4CORE_CPU1_SUSP_MASK)
/*! @} */
/*! @name STAT_M4CORE - Slice Status Register */
/*! @{ */
#define SRC_STAT_M4CORE_UNDER_RST_MASK (0x1U)
#define SRC_STAT_M4CORE_UNDER_RST_SHIFT (0U)
/*! UNDER_RST
* 0b0..the reset is finished
* 0b1..the reset is in process
*/
#define SRC_STAT_M4CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_UNDER_RST_SHIFT)) & SRC_STAT_M4CORE_UNDER_RST_MASK)
#define SRC_STAT_M4CORE_RST_BY_HW_MASK (0x4U)
#define SRC_STAT_M4CORE_RST_BY_HW_SHIFT (2U)
/*! RST_BY_HW
* 0b0..the reset is not caused by the power mode transfer
* 0b1..the reset is caused by the power mode transfer
*/
#define SRC_STAT_M4CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_HW_MASK)
#define SRC_STAT_M4CORE_RST_BY_SW_MASK (0x8U)
#define SRC_STAT_M4CORE_RST_BY_SW_SHIFT (3U)
/*! RST_BY_SW
* 0b0..the reset is not caused by software setting
* 0b1..the reset is caused by software setting
*/
#define SRC_STAT_M4CORE_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M4CORE_RST_BY_SW_MASK)
/*! @} */
/*! @name AUTHEN_M7CORE - Slice Authentication Register */
/*! @{ */
#define SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK (0x1U)
#define SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT (0U)
/*! DOMAIN_MODE
* 0b0..slice hardware reset will NOT be triggered by CPU power mode transition
* 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
*/
#define SRC_AUTHEN_M7CORE_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_DOMAIN_MODE_MASK)
#define SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK (0x2U)
#define SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT (1U)
/*! SETPOINT_MODE
* 0b0..slice hardware reset will NOT be triggered by Setpoint transition
* 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
*/
#define SRC_AUTHEN_M7CORE_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_SETPOINT_MODE_MASK)
#define SRC_AUTHEN_M7CORE_LOCK_MODE_MASK (0x80U)
#define SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT (7U)
/*! LOCK_MODE - Domain/Setpoint mode lock
*/
#define SRC_AUTHEN_M7CORE_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_MODE_MASK)
#define SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK (0xF00U)
#define SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT (8U)
#define SRC_AUTHEN_M7CORE_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_ASSIGN_LIST_MASK)
#define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK (0x8000U)
#define SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT (15U)
/*! LOCK_ASSIGN - Assign list lock
*/
#define SRC_AUTHEN_M7CORE_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_ASSIGN_MASK)
#define SRC_AUTHEN_M7CORE_WHITE_LIST_MASK (0xF0000U)
#define SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT (16U)
/*! WHITE_LIST - Domain ID white list
*/
#define SRC_AUTHEN_M7CORE_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_WHITE_LIST_MASK)
#define SRC_AUTHEN_M7CORE_LOCK_LIST_MASK (0x800000U)
#define SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT (23U)
/*! LOCK_LIST - White list lock
*/
#define SRC_AUTHEN_M7CORE_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_LIST_MASK)
#define SRC_AUTHEN_M7CORE_USER_MASK (0x1000000U)
#define SRC_AUTHEN_M7CORE_USER_SHIFT (24U)
/*! USER - Allow user mode access
*/
#define SRC_AUTHEN_M7CORE_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_USER_SHIFT)) & SRC_AUTHEN_M7CORE_USER_MASK)
#define SRC_AUTHEN_M7CORE_NONSECURE_MASK (0x2000000U)
#define SRC_AUTHEN_M7CORE_NONSECURE_SHIFT (25U)
/*! NONSECURE - Allow non-secure mode access
*/
#define SRC_AUTHEN_M7CORE_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_NONSECURE_SHIFT)) & SRC_AUTHEN_M7CORE_NONSECURE_MASK)
#define SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK (0x80000000U)
#define SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT (31U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define SRC_AUTHEN_M7CORE_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7CORE_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7CORE_LOCK_SETTING_MASK)
/*! @} */
/*! @name CTRL_M7CORE - Slice Control Register */
/*! @{ */
#define SRC_CTRL_M7CORE_SW_RESET_MASK (0x1U)
#define SRC_CTRL_M7CORE_SW_RESET_SHIFT (0U)
/*! SW_RESET
* 0b0..do not assert slice software reset
* 0b1..assert slice software reset
*/
#define SRC_CTRL_M7CORE_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7CORE_SW_RESET_SHIFT)) & SRC_CTRL_M7CORE_SW_RESET_MASK)
/*! @} */
/*! @name SETPOINT_M7CORE - Slice Setpoint Config Register */
/*! @{ */
#define SRC_SETPOINT_M7CORE_SETPOINT0_MASK (0x1U)
#define SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT (0U)
/*! SETPOINT0 - SETPOINT0
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT0_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT1_MASK (0x2U)
#define SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT (1U)
/*! SETPOINT1 - SETPOINT1
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT1_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT2_MASK (0x4U)
#define SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT (2U)
/*! SETPOINT2 - SETPOINT2
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT2_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT3_MASK (0x8U)
#define SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT (3U)
/*! SETPOINT3 - SETPOINT3
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT3_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT4_MASK (0x10U)
#define SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT (4U)
/*! SETPOINT4 - SETPOINT4
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT4_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT5_MASK (0x20U)
#define SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT (5U)
/*! SETPOINT5 - SETPOINT5
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT5_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT6_MASK (0x40U)
#define SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT (6U)
/*! SETPOINT6 - SETPOINT6
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT6_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT7_MASK (0x80U)
#define SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT (7U)
/*! SETPOINT7 - SETPOINT7
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT7_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT8_MASK (0x100U)
#define SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT (8U)
/*! SETPOINT8 - SETPOINT8
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT8_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT9_MASK (0x200U)
#define SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT (9U)
/*! SETPOINT9 - SETPOINT9
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT9_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT10_MASK (0x400U)
#define SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT (10U)
/*! SETPOINT10 - SETPOINT10
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT10_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT11_MASK (0x800U)
#define SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT (11U)
/*! SETPOINT11 - SETPOINT11
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT11_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT12_MASK (0x1000U)
#define SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT (12U)
/*! SETPOINT12 - SETPOINT12
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT12_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT13_MASK (0x2000U)
#define SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT (13U)
/*! SETPOINT13 - SETPOINT13
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT13_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT14_MASK (0x4000U)
#define SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT (14U)
/*! SETPOINT14 - SETPOINT14
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT14_MASK)
#define SRC_SETPOINT_M7CORE_SETPOINT15_MASK (0x8000U)
#define SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT (15U)
/*! SETPOINT15 - SETPOINT15
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7CORE_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7CORE_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7CORE_SETPOINT15_MASK)
/*! @} */
/*! @name DOMAIN_M7CORE - Slice Domain Config Register */
/*! @{ */
#define SRC_DOMAIN_M7CORE_CPU0_RUN_MASK (0x1U)
#define SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT (0U)
/*! CPU0_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU0 in RUN mode
* 0b1..Slice reset will be asserted when CPU0 in RUN mode
*/
#define SRC_DOMAIN_M7CORE_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_RUN_MASK)
#define SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK (0x2U)
#define SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT (1U)
/*! CPU0_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
* 0b1..Slice reset will be asserted when CPU0 in WAIT mode
*/
#define SRC_DOMAIN_M7CORE_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_WAIT_MASK)
#define SRC_DOMAIN_M7CORE_CPU0_STOP_MASK (0x4U)
#define SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT (2U)
/*! CPU0_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU0 in STOP mode
* 0b1..Slice reset will be asserted when CPU0 in STOP mode
*/
#define SRC_DOMAIN_M7CORE_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_STOP_MASK)
#define SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK (0x8U)
#define SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT (3U)
/*! CPU0_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
*/
#define SRC_DOMAIN_M7CORE_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU0_SUSP_MASK)
#define SRC_DOMAIN_M7CORE_CPU1_RUN_MASK (0x10U)
#define SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT (4U)
/*! CPU1_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU1 in RUN mode
* 0b1..Slice reset will be asserted when CPU1 in RUN mode
*/
#define SRC_DOMAIN_M7CORE_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_RUN_MASK)
#define SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK (0x20U)
#define SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT (5U)
/*! CPU1_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
* 0b1..Slice reset will be asserted when CPU1 in WAIT mode
*/
#define SRC_DOMAIN_M7CORE_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_WAIT_MASK)
#define SRC_DOMAIN_M7CORE_CPU1_STOP_MASK (0x40U)
#define SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT (6U)
/*! CPU1_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU1 in STOP mode
* 0b1..Slice reset will be asserted when CPU1 in STOP mode
*/
#define SRC_DOMAIN_M7CORE_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_STOP_MASK)
#define SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK (0x80U)
#define SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT (7U)
/*! CPU1_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
*/
#define SRC_DOMAIN_M7CORE_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7CORE_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7CORE_CPU1_SUSP_MASK)
/*! @} */
/*! @name STAT_M7CORE - Slice Status Register */
/*! @{ */
#define SRC_STAT_M7CORE_UNDER_RST_MASK (0x1U)
#define SRC_STAT_M7CORE_UNDER_RST_SHIFT (0U)
/*! UNDER_RST
* 0b0..the reset is finished
* 0b1..the reset is in process
*/
#define SRC_STAT_M7CORE_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_UNDER_RST_SHIFT)) & SRC_STAT_M7CORE_UNDER_RST_MASK)
#define SRC_STAT_M7CORE_RST_BY_HW_MASK (0x4U)
#define SRC_STAT_M7CORE_RST_BY_HW_SHIFT (2U)
/*! RST_BY_HW
* 0b0..the reset is not caused by the power mode transfer
* 0b1..the reset is caused by the power mode transfer
*/
#define SRC_STAT_M7CORE_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_HW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_HW_MASK)
#define SRC_STAT_M7CORE_RST_BY_SW_MASK (0x8U)
#define SRC_STAT_M7CORE_RST_BY_SW_SHIFT (3U)
/*! RST_BY_SW
* 0b0..the reset is not caused by software setting
* 0b1..the reset is caused by software setting
*/
#define SRC_STAT_M7CORE_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7CORE_RST_BY_SW_SHIFT)) & SRC_STAT_M7CORE_RST_BY_SW_MASK)
/*! @} */
/*! @name AUTHEN_M4DEBUG - Slice Authentication Register */
/*! @{ */
#define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK (0x1U)
#define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT (0U)
/*! DOMAIN_MODE
* 0b0..slice hardware reset will NOT be triggered by CPU power mode transition
* 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
*/
#define SRC_AUTHEN_M4DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_DOMAIN_MODE_MASK)
#define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK (0x2U)
#define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT (1U)
/*! SETPOINT_MODE
* 0b0..slice hardware reset will NOT be triggered by Setpoint transition
* 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
*/
#define SRC_AUTHEN_M4DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_SETPOINT_MODE_MASK)
#define SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK (0x80U)
#define SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT (7U)
/*! LOCK_MODE - Domain/Setpoint mode lock
*/
#define SRC_AUTHEN_M4DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_MODE_MASK)
#define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK (0xF00U)
#define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT (8U)
#define SRC_AUTHEN_M4DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_ASSIGN_LIST_MASK)
#define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK (0x8000U)
#define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT (15U)
/*! LOCK_ASSIGN - Assign list lock
*/
#define SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_ASSIGN_MASK)
#define SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK (0xF0000U)
#define SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT (16U)
/*! WHITE_LIST - Domain ID white list
*/
#define SRC_AUTHEN_M4DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_WHITE_LIST_MASK)
#define SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK (0x800000U)
#define SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT (23U)
/*! LOCK_LIST - White list lock
*/
#define SRC_AUTHEN_M4DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_LIST_MASK)
#define SRC_AUTHEN_M4DEBUG_USER_MASK (0x1000000U)
#define SRC_AUTHEN_M4DEBUG_USER_SHIFT (24U)
/*! USER - Allow user mode access
*/
#define SRC_AUTHEN_M4DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_USER_SHIFT)) & SRC_AUTHEN_M4DEBUG_USER_MASK)
#define SRC_AUTHEN_M4DEBUG_NONSECURE_MASK (0x2000000U)
#define SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT (25U)
/*! NONSECURE - Allow non-secure mode access
*/
#define SRC_AUTHEN_M4DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M4DEBUG_NONSECURE_MASK)
#define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK (0x80000000U)
#define SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT (31U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define SRC_AUTHEN_M4DEBUG_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M4DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M4DEBUG_LOCK_SETTING_MASK)
/*! @} */
/*! @name CTRL_M4DEBUG - Slice Control Register */
/*! @{ */
#define SRC_CTRL_M4DEBUG_SW_RESET_MASK (0x1U)
#define SRC_CTRL_M4DEBUG_SW_RESET_SHIFT (0U)
/*! SW_RESET
* 0b0..do not assert slice software reset
* 0b1..assert slice software reset
*/
#define SRC_CTRL_M4DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M4DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M4DEBUG_SW_RESET_MASK)
/*! @} */
/*! @name SETPOINT_M4DEBUG - Slice Setpoint Config Register */
/*! @{ */
#define SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK (0x1U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT (0U)
/*! SETPOINT0 - SETPOINT0
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT0_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK (0x2U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT (1U)
/*! SETPOINT1 - SETPOINT1
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT1_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK (0x4U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT (2U)
/*! SETPOINT2 - SETPOINT2
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT2_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK (0x8U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT (3U)
/*! SETPOINT3 - SETPOINT3
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT3_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK (0x10U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT (4U)
/*! SETPOINT4 - SETPOINT4
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT4_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK (0x20U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT (5U)
/*! SETPOINT5 - SETPOINT5
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT5_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK (0x40U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT (6U)
/*! SETPOINT6 - SETPOINT6
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT6_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK (0x80U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT (7U)
/*! SETPOINT7 - SETPOINT7
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT7_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK (0x100U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT (8U)
/*! SETPOINT8 - SETPOINT8
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT8_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK (0x200U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT (9U)
/*! SETPOINT9 - SETPOINT9
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT9_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK (0x400U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT (10U)
/*! SETPOINT10 - SETPOINT10
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT10_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK (0x800U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT (11U)
/*! SETPOINT11 - SETPOINT11
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT11_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK (0x1000U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT (12U)
/*! SETPOINT12 - SETPOINT12
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT12_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK (0x2000U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT (13U)
/*! SETPOINT13 - SETPOINT13
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT13_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK (0x4000U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT (14U)
/*! SETPOINT14 - SETPOINT14
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT14_MASK)
#define SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK (0x8000U)
#define SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT (15U)
/*! SETPOINT15 - SETPOINT15
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M4DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M4DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M4DEBUG_SETPOINT15_MASK)
/*! @} */
/*! @name DOMAIN_M4DEBUG - Slice Domain Config Register */
/*! @{ */
#define SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK (0x1U)
#define SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT (0U)
/*! CPU0_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU0 in RUN mode
* 0b1..Slice reset will be asserted when CPU0 in RUN mode
*/
#define SRC_DOMAIN_M4DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_RUN_MASK)
#define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK (0x2U)
#define SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT (1U)
/*! CPU0_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
* 0b1..Slice reset will be asserted when CPU0 in WAIT mode
*/
#define SRC_DOMAIN_M4DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_WAIT_MASK)
#define SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK (0x4U)
#define SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT (2U)
/*! CPU0_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU0 in STOP mode
* 0b1..Slice reset will be asserted when CPU0 in STOP mode
*/
#define SRC_DOMAIN_M4DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_STOP_MASK)
#define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK (0x8U)
#define SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT (3U)
/*! CPU0_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
*/
#define SRC_DOMAIN_M4DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU0_SUSP_MASK)
#define SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK (0x10U)
#define SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT (4U)
/*! CPU1_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU1 in RUN mode
* 0b1..Slice reset will be asserted when CPU1 in RUN mode
*/
#define SRC_DOMAIN_M4DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_RUN_MASK)
#define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK (0x20U)
#define SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT (5U)
/*! CPU1_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
* 0b1..Slice reset will be asserted when CPU1 in WAIT mode
*/
#define SRC_DOMAIN_M4DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_WAIT_MASK)
#define SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK (0x40U)
#define SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT (6U)
/*! CPU1_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU1 in STOP mode
* 0b1..Slice reset will be asserted when CPU1 in STOP mode
*/
#define SRC_DOMAIN_M4DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_STOP_MASK)
#define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK (0x80U)
#define SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT (7U)
/*! CPU1_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
*/
#define SRC_DOMAIN_M4DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M4DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M4DEBUG_CPU1_SUSP_MASK)
/*! @} */
/*! @name STAT_M4DEBUG - Slice Status Register */
/*! @{ */
#define SRC_STAT_M4DEBUG_UNDER_RST_MASK (0x1U)
#define SRC_STAT_M4DEBUG_UNDER_RST_SHIFT (0U)
/*! UNDER_RST
* 0b0..the reset is finished
* 0b1..the reset is in process
*/
#define SRC_STAT_M4DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M4DEBUG_UNDER_RST_MASK)
#define SRC_STAT_M4DEBUG_RST_BY_HW_MASK (0x4U)
#define SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT (2U)
/*! RST_BY_HW
* 0b0..the reset is not caused by the power mode transfer
* 0b1..the reset is caused by the power mode transfer
*/
#define SRC_STAT_M4DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_HW_MASK)
#define SRC_STAT_M4DEBUG_RST_BY_SW_MASK (0x8U)
#define SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT (3U)
/*! RST_BY_SW
* 0b0..the reset is not caused by software setting
* 0b1..the reset is caused by software setting
*/
#define SRC_STAT_M4DEBUG_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M4DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M4DEBUG_RST_BY_SW_MASK)
/*! @} */
/*! @name AUTHEN_M7DEBUG - Slice Authentication Register */
/*! @{ */
#define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK (0x1U)
#define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT (0U)
/*! DOMAIN_MODE
* 0b0..slice hardware reset will NOT be triggered by CPU power mode transition
* 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
*/
#define SRC_AUTHEN_M7DEBUG_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_DOMAIN_MODE_MASK)
#define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK (0x2U)
#define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT (1U)
/*! SETPOINT_MODE
* 0b0..slice hardware reset will NOT be triggered by Setpoint transition
* 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
*/
#define SRC_AUTHEN_M7DEBUG_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_SETPOINT_MODE_MASK)
#define SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK (0x80U)
#define SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT (7U)
/*! LOCK_MODE - Domain/Setpoint mode lock
*/
#define SRC_AUTHEN_M7DEBUG_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_MODE_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_MODE_MASK)
#define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK (0xF00U)
#define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT (8U)
#define SRC_AUTHEN_M7DEBUG_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_ASSIGN_LIST_MASK)
#define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK (0x8000U)
#define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT (15U)
/*! LOCK_ASSIGN - Assign list lock
*/
#define SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_ASSIGN_MASK)
#define SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK (0xF0000U)
#define SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT (16U)
/*! WHITE_LIST - Domain ID white list
*/
#define SRC_AUTHEN_M7DEBUG_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_WHITE_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_WHITE_LIST_MASK)
#define SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK (0x800000U)
#define SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT (23U)
/*! LOCK_LIST - White list lock
*/
#define SRC_AUTHEN_M7DEBUG_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_LIST_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_LIST_MASK)
#define SRC_AUTHEN_M7DEBUG_USER_MASK (0x1000000U)
#define SRC_AUTHEN_M7DEBUG_USER_SHIFT (24U)
/*! USER - Allow user mode access
*/
#define SRC_AUTHEN_M7DEBUG_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_USER_SHIFT)) & SRC_AUTHEN_M7DEBUG_USER_MASK)
#define SRC_AUTHEN_M7DEBUG_NONSECURE_MASK (0x2000000U)
#define SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT (25U)
/*! NONSECURE - Allow non-secure mode access
*/
#define SRC_AUTHEN_M7DEBUG_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_NONSECURE_SHIFT)) & SRC_AUTHEN_M7DEBUG_NONSECURE_MASK)
#define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK (0x80000000U)
#define SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT (31U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define SRC_AUTHEN_M7DEBUG_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_M7DEBUG_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_M7DEBUG_LOCK_SETTING_MASK)
/*! @} */
/*! @name CTRL_M7DEBUG - Slice Control Register */
/*! @{ */
#define SRC_CTRL_M7DEBUG_SW_RESET_MASK (0x1U)
#define SRC_CTRL_M7DEBUG_SW_RESET_SHIFT (0U)
/*! SW_RESET
* 0b0..do not assert slice software reset
* 0b1..assert slice software reset
*/
#define SRC_CTRL_M7DEBUG_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_M7DEBUG_SW_RESET_SHIFT)) & SRC_CTRL_M7DEBUG_SW_RESET_MASK)
/*! @} */
/*! @name SETPOINT_M7DEBUG - Slice Setpoint Config Register */
/*! @{ */
#define SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK (0x1U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT (0U)
/*! SETPOINT0 - SETPOINT0
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT0_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT0_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK (0x2U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT (1U)
/*! SETPOINT1 - SETPOINT1
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT1_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT1_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK (0x4U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT (2U)
/*! SETPOINT2 - SETPOINT2
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT2_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT2_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK (0x8U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT (3U)
/*! SETPOINT3 - SETPOINT3
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT3_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT3_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK (0x10U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT (4U)
/*! SETPOINT4 - SETPOINT4
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT4_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT4_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK (0x20U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT (5U)
/*! SETPOINT5 - SETPOINT5
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT5_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT5_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK (0x40U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT (6U)
/*! SETPOINT6 - SETPOINT6
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT6_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT6_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK (0x80U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT (7U)
/*! SETPOINT7 - SETPOINT7
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT7_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT7_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK (0x100U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT (8U)
/*! SETPOINT8 - SETPOINT8
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT8_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT8_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK (0x200U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT (9U)
/*! SETPOINT9 - SETPOINT9
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT9_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT9_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK (0x400U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT (10U)
/*! SETPOINT10 - SETPOINT10
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT10_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT10_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK (0x800U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT (11U)
/*! SETPOINT11 - SETPOINT11
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT11_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT11_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK (0x1000U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT (12U)
/*! SETPOINT12 - SETPOINT12
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT12_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT12_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK (0x2000U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT (13U)
/*! SETPOINT13 - SETPOINT13
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT13_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT13_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK (0x4000U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT (14U)
/*! SETPOINT14 - SETPOINT14
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT14_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT14_MASK)
#define SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK (0x8000U)
#define SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT (15U)
/*! SETPOINT15 - SETPOINT15
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_M7DEBUG_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_M7DEBUG_SETPOINT15_SHIFT)) & SRC_SETPOINT_M7DEBUG_SETPOINT15_MASK)
/*! @} */
/*! @name DOMAIN_M7DEBUG - Slice Domain Config Register */
/*! @{ */
#define SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK (0x1U)
#define SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT (0U)
/*! CPU0_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU0 in RUN mode
* 0b1..Slice reset will be asserted when CPU0 in RUN mode
*/
#define SRC_DOMAIN_M7DEBUG_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_RUN_MASK)
#define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK (0x2U)
#define SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT (1U)
/*! CPU0_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
* 0b1..Slice reset will be asserted when CPU0 in WAIT mode
*/
#define SRC_DOMAIN_M7DEBUG_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_WAIT_MASK)
#define SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK (0x4U)
#define SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT (2U)
/*! CPU0_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU0 in STOP mode
* 0b1..Slice reset will be asserted when CPU0 in STOP mode
*/
#define SRC_DOMAIN_M7DEBUG_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_STOP_MASK)
#define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK (0x8U)
#define SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT (3U)
/*! CPU0_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
*/
#define SRC_DOMAIN_M7DEBUG_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU0_SUSP_MASK)
#define SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK (0x10U)
#define SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT (4U)
/*! CPU1_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU1 in RUN mode
* 0b1..Slice reset will be asserted when CPU1 in RUN mode
*/
#define SRC_DOMAIN_M7DEBUG_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_RUN_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_RUN_MASK)
#define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK (0x20U)
#define SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT (5U)
/*! CPU1_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
* 0b1..Slice reset will be asserted when CPU1 in WAIT mode
*/
#define SRC_DOMAIN_M7DEBUG_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_WAIT_MASK)
#define SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK (0x40U)
#define SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT (6U)
/*! CPU1_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU1 in STOP mode
* 0b1..Slice reset will be asserted when CPU1 in STOP mode
*/
#define SRC_DOMAIN_M7DEBUG_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_STOP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_STOP_MASK)
#define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK (0x80U)
#define SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT (7U)
/*! CPU1_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
*/
#define SRC_DOMAIN_M7DEBUG_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_M7DEBUG_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_M7DEBUG_CPU1_SUSP_MASK)
/*! @} */
/*! @name STAT_M7DEBUG - Slice Status Register */
/*! @{ */
#define SRC_STAT_M7DEBUG_UNDER_RST_MASK (0x1U)
#define SRC_STAT_M7DEBUG_UNDER_RST_SHIFT (0U)
/*! UNDER_RST
* 0b0..the reset is finished
* 0b1..the reset is in process
*/
#define SRC_STAT_M7DEBUG_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_UNDER_RST_SHIFT)) & SRC_STAT_M7DEBUG_UNDER_RST_MASK)
#define SRC_STAT_M7DEBUG_RST_BY_HW_MASK (0x4U)
#define SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT (2U)
/*! RST_BY_HW
* 0b0..the reset is not caused by the power mode transfer
* 0b1..the reset is caused by the power mode transfer
*/
#define SRC_STAT_M7DEBUG_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_HW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_HW_MASK)
#define SRC_STAT_M7DEBUG_RST_BY_SW_MASK (0x8U)
#define SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT (3U)
/*! RST_BY_SW
* 0b0..the reset is not caused by software setting
* 0b1..the reset is caused by software setting
*/
#define SRC_STAT_M7DEBUG_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_M7DEBUG_RST_BY_SW_SHIFT)) & SRC_STAT_M7DEBUG_RST_BY_SW_MASK)
/*! @} */
/*! @name AUTHEN_USBPHY1 - Slice Authentication Register */
/*! @{ */
#define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK (0x1U)
#define SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT (0U)
/*! DOMAIN_MODE
* 0b0..slice hardware reset will NOT be triggered by CPU power mode transition
* 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
*/
#define SRC_AUTHEN_USBPHY1_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_DOMAIN_MODE_MASK)
#define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK (0x2U)
#define SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT (1U)
/*! SETPOINT_MODE
* 0b0..slice hardware reset will NOT be triggered by Setpoint transition
* 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
*/
#define SRC_AUTHEN_USBPHY1_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_SETPOINT_MODE_MASK)
#define SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK (0x80U)
#define SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT (7U)
/*! LOCK_MODE - Domain/Setpoint mode lock
*/
#define SRC_AUTHEN_USBPHY1_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_MODE_MASK)
#define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK (0xF00U)
#define SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT (8U)
#define SRC_AUTHEN_USBPHY1_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_ASSIGN_LIST_MASK)
#define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK (0x8000U)
#define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT (15U)
/*! LOCK_ASSIGN - Assign list lock
*/
#define SRC_AUTHEN_USBPHY1_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_ASSIGN_MASK)
#define SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK (0xF0000U)
#define SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT (16U)
/*! WHITE_LIST - Domain ID white list
*/
#define SRC_AUTHEN_USBPHY1_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_WHITE_LIST_MASK)
#define SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK (0x800000U)
#define SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT (23U)
/*! LOCK_LIST - White list lock
*/
#define SRC_AUTHEN_USBPHY1_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_LIST_MASK)
#define SRC_AUTHEN_USBPHY1_USER_MASK (0x1000000U)
#define SRC_AUTHEN_USBPHY1_USER_SHIFT (24U)
/*! USER - Allow user mode access
*/
#define SRC_AUTHEN_USBPHY1_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_USER_SHIFT)) & SRC_AUTHEN_USBPHY1_USER_MASK)
#define SRC_AUTHEN_USBPHY1_NONSECURE_MASK (0x2000000U)
#define SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT (25U)
/*! NONSECURE - Allow non-secure mode access
*/
#define SRC_AUTHEN_USBPHY1_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY1_NONSECURE_MASK)
#define SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK (0x80000000U)
#define SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT (31U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define SRC_AUTHEN_USBPHY1_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY1_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY1_LOCK_SETTING_MASK)
/*! @} */
/*! @name CTRL_USBPHY1 - Slice Control Register */
/*! @{ */
#define SRC_CTRL_USBPHY1_SW_RESET_MASK (0x1U)
#define SRC_CTRL_USBPHY1_SW_RESET_SHIFT (0U)
/*! SW_RESET
* 0b0..do not assert slice software reset
* 0b1..assert slice software reset
*/
#define SRC_CTRL_USBPHY1_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY1_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY1_SW_RESET_MASK)
/*! @} */
/*! @name SETPOINT_USBPHY1 - Slice Setpoint Config Register */
/*! @{ */
#define SRC_SETPOINT_USBPHY1_SETPOINT0_MASK (0x1U)
#define SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT (0U)
/*! SETPOINT0 - SETPOINT0
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT0_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT1_MASK (0x2U)
#define SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT (1U)
/*! SETPOINT1 - SETPOINT1
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT1_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT2_MASK (0x4U)
#define SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT (2U)
/*! SETPOINT2 - SETPOINT2
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT2_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT3_MASK (0x8U)
#define SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT (3U)
/*! SETPOINT3 - SETPOINT3
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT3_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT4_MASK (0x10U)
#define SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT (4U)
/*! SETPOINT4 - SETPOINT4
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT4_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT5_MASK (0x20U)
#define SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT (5U)
/*! SETPOINT5 - SETPOINT5
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT5_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT6_MASK (0x40U)
#define SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT (6U)
/*! SETPOINT6 - SETPOINT6
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT6_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT7_MASK (0x80U)
#define SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT (7U)
/*! SETPOINT7 - SETPOINT7
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT7_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT8_MASK (0x100U)
#define SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT (8U)
/*! SETPOINT8 - SETPOINT8
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT8_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT9_MASK (0x200U)
#define SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT (9U)
/*! SETPOINT9 - SETPOINT9
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT9_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT10_MASK (0x400U)
#define SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT (10U)
/*! SETPOINT10 - SETPOINT10
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT10_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT11_MASK (0x800U)
#define SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT (11U)
/*! SETPOINT11 - SETPOINT11
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT11_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT12_MASK (0x1000U)
#define SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT (12U)
/*! SETPOINT12 - SETPOINT12
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT12_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT13_MASK (0x2000U)
#define SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT (13U)
/*! SETPOINT13 - SETPOINT13
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT13_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT14_MASK (0x4000U)
#define SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT (14U)
/*! SETPOINT14 - SETPOINT14
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT14_MASK)
#define SRC_SETPOINT_USBPHY1_SETPOINT15_MASK (0x8000U)
#define SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT (15U)
/*! SETPOINT15 - SETPOINT15
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY1_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY1_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY1_SETPOINT15_MASK)
/*! @} */
/*! @name DOMAIN_USBPHY1 - Slice Domain Config Register */
/*! @{ */
#define SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK (0x1U)
#define SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT (0U)
/*! CPU0_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU0 in RUN mode
* 0b1..Slice reset will be asserted when CPU0 in RUN mode
*/
#define SRC_DOMAIN_USBPHY1_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_RUN_MASK)
#define SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK (0x2U)
#define SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT (1U)
/*! CPU0_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
* 0b1..Slice reset will be asserted when CPU0 in WAIT mode
*/
#define SRC_DOMAIN_USBPHY1_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_WAIT_MASK)
#define SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK (0x4U)
#define SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT (2U)
/*! CPU0_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU0 in STOP mode
* 0b1..Slice reset will be asserted when CPU0 in STOP mode
*/
#define SRC_DOMAIN_USBPHY1_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_STOP_MASK)
#define SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK (0x8U)
#define SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT (3U)
/*! CPU0_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
*/
#define SRC_DOMAIN_USBPHY1_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU0_SUSP_MASK)
#define SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK (0x10U)
#define SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT (4U)
/*! CPU1_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU1 in RUN mode
* 0b1..Slice reset will be asserted when CPU1 in RUN mode
*/
#define SRC_DOMAIN_USBPHY1_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_RUN_MASK)
#define SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK (0x20U)
#define SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT (5U)
/*! CPU1_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
* 0b1..Slice reset will be asserted when CPU1 in WAIT mode
*/
#define SRC_DOMAIN_USBPHY1_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_WAIT_MASK)
#define SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK (0x40U)
#define SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT (6U)
/*! CPU1_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU1 in STOP mode
* 0b1..Slice reset will be asserted when CPU1 in STOP mode
*/
#define SRC_DOMAIN_USBPHY1_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_STOP_MASK)
#define SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK (0x80U)
#define SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT (7U)
/*! CPU1_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
*/
#define SRC_DOMAIN_USBPHY1_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY1_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY1_CPU1_SUSP_MASK)
/*! @} */
/*! @name STAT_USBPHY1 - Slice Status Register */
/*! @{ */
#define SRC_STAT_USBPHY1_UNDER_RST_MASK (0x1U)
#define SRC_STAT_USBPHY1_UNDER_RST_SHIFT (0U)
/*! UNDER_RST
* 0b0..the reset is finished
* 0b1..the reset is in process
*/
#define SRC_STAT_USBPHY1_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY1_UNDER_RST_MASK)
#define SRC_STAT_USBPHY1_RST_BY_HW_MASK (0x4U)
#define SRC_STAT_USBPHY1_RST_BY_HW_SHIFT (2U)
/*! RST_BY_HW
* 0b0..the reset is not caused by the power mode transfer
* 0b1..the reset is caused by the power mode transfer
*/
#define SRC_STAT_USBPHY1_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_HW_MASK)
#define SRC_STAT_USBPHY1_RST_BY_SW_MASK (0x8U)
#define SRC_STAT_USBPHY1_RST_BY_SW_SHIFT (3U)
/*! RST_BY_SW
* 0b0..the reset is not caused by software setting
* 0b1..the reset is caused by software setting
*/
#define SRC_STAT_USBPHY1_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY1_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY1_RST_BY_SW_MASK)
/*! @} */
/*! @name AUTHEN_USBPHY2 - Slice Authentication Register */
/*! @{ */
#define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK (0x1U)
#define SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT (0U)
/*! DOMAIN_MODE
* 0b0..slice hardware reset will NOT be triggered by CPU power mode transition
* 0b1..slice hardware reset will be triggered by CPU power mode transition. Do not set this bit and SETPOINT_MODE at the same time.
*/
#define SRC_AUTHEN_USBPHY2_DOMAIN_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_DOMAIN_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_DOMAIN_MODE_MASK)
#define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK (0x2U)
#define SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT (1U)
/*! SETPOINT_MODE
* 0b0..slice hardware reset will NOT be triggered by Setpoint transition
* 0b1..slice hardware reset will be triggered by Setpoint transition. Do not set this bit and DOMAIN_MODE at the same time.
*/
#define SRC_AUTHEN_USBPHY2_SETPOINT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_SETPOINT_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_SETPOINT_MODE_MASK)
#define SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK (0x80U)
#define SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT (7U)
/*! LOCK_MODE - Domain/Setpoint mode lock
*/
#define SRC_AUTHEN_USBPHY2_LOCK_MODE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_MODE_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_MODE_MASK)
#define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK (0xF00U)
#define SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT (8U)
#define SRC_AUTHEN_USBPHY2_ASSIGN_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_ASSIGN_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_ASSIGN_LIST_MASK)
#define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK (0x8000U)
#define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT (15U)
/*! LOCK_ASSIGN - Assign list lock
*/
#define SRC_AUTHEN_USBPHY2_LOCK_ASSIGN(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_ASSIGN_MASK)
#define SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK (0xF0000U)
#define SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT (16U)
/*! WHITE_LIST - Domain ID white list
*/
#define SRC_AUTHEN_USBPHY2_WHITE_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_WHITE_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_WHITE_LIST_MASK)
#define SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK (0x800000U)
#define SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT (23U)
/*! LOCK_LIST - White list lock
*/
#define SRC_AUTHEN_USBPHY2_LOCK_LIST(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_LIST_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_LIST_MASK)
#define SRC_AUTHEN_USBPHY2_USER_MASK (0x1000000U)
#define SRC_AUTHEN_USBPHY2_USER_SHIFT (24U)
/*! USER - Allow user mode access
*/
#define SRC_AUTHEN_USBPHY2_USER(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_USER_SHIFT)) & SRC_AUTHEN_USBPHY2_USER_MASK)
#define SRC_AUTHEN_USBPHY2_NONSECURE_MASK (0x2000000U)
#define SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT (25U)
/*! NONSECURE - Allow non-secure mode access
*/
#define SRC_AUTHEN_USBPHY2_NONSECURE(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_NONSECURE_SHIFT)) & SRC_AUTHEN_USBPHY2_NONSECURE_MASK)
#define SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK (0x80000000U)
#define SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT (31U)
/*! LOCK_SETTING - Lock NONSECURE and USER
*/
#define SRC_AUTHEN_USBPHY2_LOCK_SETTING(x) (((uint32_t)(((uint32_t)(x)) << SRC_AUTHEN_USBPHY2_LOCK_SETTING_SHIFT)) & SRC_AUTHEN_USBPHY2_LOCK_SETTING_MASK)
/*! @} */
/*! @name CTRL_USBPHY2 - Slice Control Register */
/*! @{ */
#define SRC_CTRL_USBPHY2_SW_RESET_MASK (0x1U)
#define SRC_CTRL_USBPHY2_SW_RESET_SHIFT (0U)
/*! SW_RESET
* 0b0..do not assert slice software reset
* 0b1..assert slice software reset
*/
#define SRC_CTRL_USBPHY2_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SRC_CTRL_USBPHY2_SW_RESET_SHIFT)) & SRC_CTRL_USBPHY2_SW_RESET_MASK)
/*! @} */
/*! @name SETPOINT_USBPHY2 - Slice Setpoint Config Register */
/*! @{ */
#define SRC_SETPOINT_USBPHY2_SETPOINT0_MASK (0x1U)
#define SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT (0U)
/*! SETPOINT0 - SETPOINT0
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT0(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT0_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT0_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT1_MASK (0x2U)
#define SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT (1U)
/*! SETPOINT1 - SETPOINT1
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT1(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT1_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT1_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT2_MASK (0x4U)
#define SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT (2U)
/*! SETPOINT2 - SETPOINT2
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT2(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT2_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT2_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT3_MASK (0x8U)
#define SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT (3U)
/*! SETPOINT3 - SETPOINT3
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT3(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT3_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT3_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT4_MASK (0x10U)
#define SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT (4U)
/*! SETPOINT4 - SETPOINT4
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT4(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT4_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT4_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT5_MASK (0x20U)
#define SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT (5U)
/*! SETPOINT5 - SETPOINT5
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT5(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT5_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT5_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT6_MASK (0x40U)
#define SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT (6U)
/*! SETPOINT6 - SETPOINT6
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT6(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT6_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT6_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT7_MASK (0x80U)
#define SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT (7U)
/*! SETPOINT7 - SETPOINT7
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT7(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT7_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT7_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT8_MASK (0x100U)
#define SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT (8U)
/*! SETPOINT8 - SETPOINT8
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT8(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT8_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT8_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT9_MASK (0x200U)
#define SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT (9U)
/*! SETPOINT9 - SETPOINT9
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT9(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT9_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT9_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT10_MASK (0x400U)
#define SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT (10U)
/*! SETPOINT10 - SETPOINT10
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT10(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT10_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT10_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT11_MASK (0x800U)
#define SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT (11U)
/*! SETPOINT11 - SETPOINT11
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT11(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT11_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT11_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT12_MASK (0x1000U)
#define SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT (12U)
/*! SETPOINT12 - SETPOINT12
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT12(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT12_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT12_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT13_MASK (0x2000U)
#define SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT (13U)
/*! SETPOINT13 - SETPOINT13
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT13(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT13_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT13_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT14_MASK (0x4000U)
#define SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT (14U)
/*! SETPOINT14 - SETPOINT14
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT14(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT14_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT14_MASK)
#define SRC_SETPOINT_USBPHY2_SETPOINT15_MASK (0x8000U)
#define SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT (15U)
/*! SETPOINT15 - SETPOINT15
* 0b0..Slice reset will be de-asserted when system in Setpoint n
* 0b1..Slice reset will be asserted when system in Setpoint n
*/
#define SRC_SETPOINT_USBPHY2_SETPOINT15(x) (((uint32_t)(((uint32_t)(x)) << SRC_SETPOINT_USBPHY2_SETPOINT15_SHIFT)) & SRC_SETPOINT_USBPHY2_SETPOINT15_MASK)
/*! @} */
/*! @name DOMAIN_USBPHY2 - Slice Domain Config Register */
/*! @{ */
#define SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK (0x1U)
#define SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT (0U)
/*! CPU0_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU0 in RUN mode
* 0b1..Slice reset will be asserted when CPU0 in RUN mode
*/
#define SRC_DOMAIN_USBPHY2_CPU0_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_RUN_MASK)
#define SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK (0x2U)
#define SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT (1U)
/*! CPU0_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU0 in WAIT mode
* 0b1..Slice reset will be asserted when CPU0 in WAIT mode
*/
#define SRC_DOMAIN_USBPHY2_CPU0_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_WAIT_MASK)
#define SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK (0x4U)
#define SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT (2U)
/*! CPU0_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU0 in STOP mode
* 0b1..Slice reset will be asserted when CPU0 in STOP mode
*/
#define SRC_DOMAIN_USBPHY2_CPU0_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_STOP_MASK)
#define SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK (0x8U)
#define SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT (3U)
/*! CPU0_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU0 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU0 in SUSPEND mode
*/
#define SRC_DOMAIN_USBPHY2_CPU0_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU0_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU0_SUSP_MASK)
#define SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK (0x10U)
#define SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT (4U)
/*! CPU1_RUN - CPU mode setting for RUN
* 0b0..Slice reset will be de-asserted when CPU1 in RUN mode
* 0b1..Slice reset will be asserted when CPU1 in RUN mode
*/
#define SRC_DOMAIN_USBPHY2_CPU1_RUN(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_RUN_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_RUN_MASK)
#define SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK (0x20U)
#define SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT (5U)
/*! CPU1_WAIT - CPU mode setting for WAIT
* 0b0..Slice reset will be de-asserted when CPU1 in WAIT mode
* 0b1..Slice reset will be asserted when CPU1 in WAIT mode
*/
#define SRC_DOMAIN_USBPHY2_CPU1_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_WAIT_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_WAIT_MASK)
#define SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK (0x40U)
#define SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT (6U)
/*! CPU1_STOP - CPU mode setting for STOP
* 0b0..Slice reset will be de-asserted when CPU1 in STOP mode
* 0b1..Slice reset will be asserted when CPU1 in STOP mode
*/
#define SRC_DOMAIN_USBPHY2_CPU1_STOP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_STOP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_STOP_MASK)
#define SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK (0x80U)
#define SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT (7U)
/*! CPU1_SUSP - CPU mode setting for SUSPEND
* 0b0..Slice reset will be de-asserted when CPU1 in SUSPEND mode
* 0b1..Slice reset will be asserted when CPU1 in SUSPEND mode
*/
#define SRC_DOMAIN_USBPHY2_CPU1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << SRC_DOMAIN_USBPHY2_CPU1_SUSP_SHIFT)) & SRC_DOMAIN_USBPHY2_CPU1_SUSP_MASK)
/*! @} */
/*! @name STAT_USBPHY2 - Slice Status Register */
/*! @{ */
#define SRC_STAT_USBPHY2_UNDER_RST_MASK (0x1U)
#define SRC_STAT_USBPHY2_UNDER_RST_SHIFT (0U)
/*! UNDER_RST
* 0b0..the reset is finished
* 0b1..the reset is in process
*/
#define SRC_STAT_USBPHY2_UNDER_RST(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_UNDER_RST_SHIFT)) & SRC_STAT_USBPHY2_UNDER_RST_MASK)
#define SRC_STAT_USBPHY2_RST_BY_HW_MASK (0x4U)
#define SRC_STAT_USBPHY2_RST_BY_HW_SHIFT (2U)
/*! RST_BY_HW
* 0b0..the reset is not caused by the power mode transfer
* 0b1..the reset is caused by the power mode transfer
*/
#define SRC_STAT_USBPHY2_RST_BY_HW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_HW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_HW_MASK)
#define SRC_STAT_USBPHY2_RST_BY_SW_MASK (0x8U)
#define SRC_STAT_USBPHY2_RST_BY_SW_SHIFT (3U)
/*! RST_BY_SW
* 0b0..the reset is not caused by software setting
* 0b1..the reset is caused by software setting
*/
#define SRC_STAT_USBPHY2_RST_BY_SW(x) (((uint32_t)(((uint32_t)(x)) << SRC_STAT_USBPHY2_RST_BY_SW_SHIFT)) & SRC_STAT_USBPHY2_RST_BY_SW_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SRC_Register_Masks */
/* SRC - Peripheral instance base addresses */
/** Peripheral SRC base address */
#define SRC_BASE (0x40C04000u)
/** Peripheral SRC base pointer */
#define SRC ((SRC_Type *)SRC_BASE)
/** Array initializer of SRC peripheral base addresses */
#define SRC_BASE_ADDRS { SRC_BASE }
/** Array initializer of SRC peripheral base pointers */
#define SRC_BASE_PTRS { SRC }
/*!
* @}
*/ /* end of group SRC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SSARC_HP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SSARC_HP_Peripheral_Access_Layer SSARC_HP Peripheral Access Layer
* @{
*/
/** SSARC_HP - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x10 */
__IO uint32_t SRAM0; /**< Description Address Register, array offset: 0x0, array step: 0x10 */
__IO uint32_t SRAM1; /**< Description Data Register, array offset: 0x4, array step: 0x10 */
__IO uint32_t SRAM2; /**< Description Control Register, array offset: 0x8, array step: 0x10 */
uint8_t RESERVED_0[4];
} DESC[1024];
} SSARC_HP_Type;
/* ----------------------------------------------------------------------------
-- SSARC_HP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SSARC_HP_Register_Masks SSARC_HP Register Masks
* @{
*/
/*! @name SRAM0 - Description Address Register */
/*! @{ */
#define SSARC_HP_SRAM0_ADDR_MASK (0xFFFFFFFFU)
#define SSARC_HP_SRAM0_ADDR_SHIFT (0U)
/*! ADDR - Address field
*/
#define SSARC_HP_SRAM0_ADDR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM0_ADDR_SHIFT)) & SSARC_HP_SRAM0_ADDR_MASK)
/*! @} */
/* The count of SSARC_HP_SRAM0 */
#define SSARC_HP_SRAM0_COUNT (1024U)
/*! @name SRAM1 - Description Data Register */
/*! @{ */
#define SSARC_HP_SRAM1_DATA_MASK (0xFFFFFFFFU)
#define SSARC_HP_SRAM1_DATA_SHIFT (0U)
/*! DATA - Data field
*/
#define SSARC_HP_SRAM1_DATA(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM1_DATA_SHIFT)) & SSARC_HP_SRAM1_DATA_MASK)
/*! @} */
/* The count of SSARC_HP_SRAM1 */
#define SSARC_HP_SRAM1_COUNT (1024U)
/*! @name SRAM2 - Description Control Register */
/*! @{ */
#define SSARC_HP_SRAM2_TYPE_MASK (0x7U)
#define SSARC_HP_SRAM2_TYPE_SHIFT (0U)
/*! TYPE - Type field
* 0b000..SR
* 0b001..WO
* 0b010..RMW_OR
* 0b011..RMW_AND
* 0b100..DELAY
* 0b101..POLLING_0
* 0b110..POLLING_1
* 0b111..Reserved
*/
#define SSARC_HP_SRAM2_TYPE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_TYPE_SHIFT)) & SSARC_HP_SRAM2_TYPE_MASK)
#define SSARC_HP_SRAM2_SV_EN_MASK (0x10U)
#define SSARC_HP_SRAM2_SV_EN_SHIFT (4U)
/*! SV_EN - Save Enable
* 0b0..Do not use this descriptor in the save operation
* 0b1..Use this descriptor in the save operation
*/
#define SSARC_HP_SRAM2_SV_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SV_EN_SHIFT)) & SSARC_HP_SRAM2_SV_EN_MASK)
#define SSARC_HP_SRAM2_RT_EN_MASK (0x20U)
#define SSARC_HP_SRAM2_RT_EN_SHIFT (5U)
/*! RT_EN - Restore Enable
* 0b0..Do not use this descriptor for the restore operation
* 0b1..Use this descriptor for the restore operation
*/
#define SSARC_HP_SRAM2_RT_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_RT_EN_SHIFT)) & SSARC_HP_SRAM2_RT_EN_MASK)
#define SSARC_HP_SRAM2_SIZE_MASK (0xC0U)
#define SSARC_HP_SRAM2_SIZE_SHIFT (6U)
/*! SIZE - Size field
* 0b00..8-bit
* 0b01..16-bit
* 0b10..32-bit
* 0b11..Reserved
*/
#define SSARC_HP_SRAM2_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_HP_SRAM2_SIZE_SHIFT)) & SSARC_HP_SRAM2_SIZE_MASK)
/*! @} */
/* The count of SSARC_HP_SRAM2 */
#define SSARC_HP_SRAM2_COUNT (1024U)
/*!
* @}
*/ /* end of group SSARC_HP_Register_Masks */
/* SSARC_HP - Peripheral instance base addresses */
/** Peripheral SSARC_HP base address */
#define SSARC_HP_BASE (0x40CB4000u)
/** Peripheral SSARC_HP base pointer */
#define SSARC_HP ((SSARC_HP_Type *)SSARC_HP_BASE)
/** Array initializer of SSARC_HP peripheral base addresses */
#define SSARC_HP_BASE_ADDRS { SSARC_HP_BASE }
/** Array initializer of SSARC_HP peripheral base pointers */
#define SSARC_HP_BASE_PTRS { SSARC_HP }
/*!
* @}
*/ /* end of group SSARC_HP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- SSARC_LP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup SSARC_LP_Peripheral_Access_Layer SSARC_LP Peripheral Access Layer
* @{
*/
/** SSARC_LP - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x20 */
__IO uint32_t DESC_CTRL0; /**< Descriptor Control0 0 Register..Descriptor Control0 15 Register, array offset: 0x0, array step: 0x20 */
__IO uint32_t DESC_CTRL1; /**< Descriptor Control1 0 Register..Descriptor Control1 15 Register, array offset: 0x4, array step: 0x20 */
__IO uint32_t DESC_ADDR_UP; /**< Descriptor Address Up 0 Register..Descriptor Address Up 15 Register, array offset: 0x8, array step: 0x20 */
__IO uint32_t DESC_ADDR_DOWN; /**< Descriptor Address Down 0 Register..Descriptor Address Down 15 Register, array offset: 0xC, array step: 0x20 */
uint8_t RESERVED_0[16];
} GROUPS[16];
__IO uint32_t CTRL; /**< Control Register, offset: 0x200 */
__IO uint32_t INT_STATUS; /**< Interrupt Status Register, offset: 0x204 */
uint8_t RESERVED_0[4];
__IO uint32_t HP_TIMEOUT; /**< HP Timeout Register, offset: 0x20C */
uint8_t RESERVED_1[12];
__I uint32_t HW_GROUP_PENDING; /**< Hardware Request Pending Register, offset: 0x21C */
__I uint32_t SW_GROUP_PENDING; /**< Software Request Pending Register, offset: 0x220 */
} SSARC_LP_Type;
/* ----------------------------------------------------------------------------
-- SSARC_LP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup SSARC_LP_Register_Masks SSARC_LP Register Masks
* @{
*/
/*! @name DESC_CTRL0 - Descriptor Control0 0 Register..Descriptor Control0 15 Register */
/*! @{ */
#define SSARC_LP_DESC_CTRL0_START_MASK (0x3FFU)
#define SSARC_LP_DESC_CTRL0_START_SHIFT (0U)
/*! START - Start index
*/
#define SSARC_LP_DESC_CTRL0_START(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_START_SHIFT)) & SSARC_LP_DESC_CTRL0_START_MASK)
#define SSARC_LP_DESC_CTRL0_END_MASK (0xFFC00U)
#define SSARC_LP_DESC_CTRL0_END_SHIFT (10U)
/*! END - End index
*/
#define SSARC_LP_DESC_CTRL0_END(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_END_SHIFT)) & SSARC_LP_DESC_CTRL0_END_MASK)
#define SSARC_LP_DESC_CTRL0_SV_ORDER_MASK (0x100000U)
#define SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT (20U)
/*! SV_ORDER - Save Order
* 0b0..Descriptors within the group are processed from start to end
* 0b1..Descriptors within the group are processed from end to start
*/
#define SSARC_LP_DESC_CTRL0_SV_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_SV_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_SV_ORDER_MASK)
#define SSARC_LP_DESC_CTRL0_RT_ORDER_MASK (0x200000U)
#define SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT (21U)
/*! RT_ORDER - Restore order
* 0b0..Descriptors within the group are processed from start to end
* 0b1..Descriptors within the group are processed from end to start
*/
#define SSARC_LP_DESC_CTRL0_RT_ORDER(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL0_RT_ORDER_SHIFT)) & SSARC_LP_DESC_CTRL0_RT_ORDER_MASK)
/*! @} */
/* The count of SSARC_LP_DESC_CTRL0 */
#define SSARC_LP_DESC_CTRL0_COUNT (16U)
/*! @name DESC_CTRL1 - Descriptor Control1 0 Register..Descriptor Control1 15 Register */
/*! @{ */
#define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK (0x1U)
#define SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT (0U)
/*! SW_TRIG_SV - Software trigger save
* 0b1..Request a software save operation/software restore operation in progress
* 0b0..No software save request/software restore request complete
*/
#define SSARC_LP_DESC_CTRL1_SW_TRIG_SV(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_SV_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_SV_MASK)
#define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK (0x2U)
#define SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT (1U)
/*! SW_TRIG_RT - Software trigger restore
* 0b1..Request a software restore operation/software restore operation in progress
* 0b0..No software restore request/software restore request complete
*/
#define SSARC_LP_DESC_CTRL1_SW_TRIG_RT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SW_TRIG_RT_SHIFT)) & SSARC_LP_DESC_CTRL1_SW_TRIG_RT_MASK)
#define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK (0x70U)
#define SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT (4U)
/*! POWER_DOMAIN
* 0b000..PGMC_BPC0
* 0b001..PGMC_BPC1
* 0b010..PGMC_BPC2
* 0b011..PGMC_BPC3
* 0b100..PGMC_BPC4
* 0b101..PGMC_BPC5
* 0b110..PGMC_BPC6
* 0b111..PGMC_BPC7
*/
#define SSARC_LP_DESC_CTRL1_POWER_DOMAIN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_POWER_DOMAIN_SHIFT)) & SSARC_LP_DESC_CTRL1_POWER_DOMAIN_MASK)
#define SSARC_LP_DESC_CTRL1_GP_EN_MASK (0x80U)
#define SSARC_LP_DESC_CTRL1_GP_EN_SHIFT (7U)
/*! GP_EN - Group Enable
* 0b0..Group disabled
* 0b1..Group enabled
*/
#define SSARC_LP_DESC_CTRL1_GP_EN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_GP_EN_SHIFT)) & SSARC_LP_DESC_CTRL1_GP_EN_MASK)
#define SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK (0xF00U)
#define SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT (8U)
/*! SV_PRIORITY - Save Priority
*/
#define SSARC_LP_DESC_CTRL1_SV_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_SV_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_SV_PRIORITY_MASK)
#define SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK (0xF000U)
#define SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT (12U)
/*! RT_PRIORITY - Restore Priority
*/
#define SSARC_LP_DESC_CTRL1_RT_PRIORITY(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RT_PRIORITY_SHIFT)) & SSARC_LP_DESC_CTRL1_RT_PRIORITY_MASK)
#define SSARC_LP_DESC_CTRL1_CPUD_MASK (0x30000U)
#define SSARC_LP_DESC_CTRL1_CPUD_SHIFT (16U)
/*! CPUD - CPU Domain
*/
#define SSARC_LP_DESC_CTRL1_CPUD(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_CPUD_SHIFT)) & SSARC_LP_DESC_CTRL1_CPUD_MASK)
#define SSARC_LP_DESC_CTRL1_RL_MASK (0x40000U)
#define SSARC_LP_DESC_CTRL1_RL_SHIFT (18U)
/*! RL - Read Lock
* 0b1..Group is locked (read access not allowed)
* 0b0..Group is unlocked (read access allowed)
*/
#define SSARC_LP_DESC_CTRL1_RL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_RL_SHIFT)) & SSARC_LP_DESC_CTRL1_RL_MASK)
#define SSARC_LP_DESC_CTRL1_WL_MASK (0x80000U)
#define SSARC_LP_DESC_CTRL1_WL_SHIFT (19U)
/*! WL - Write Lock
* 0b1..Group is locked (write access not allowed)
* 0b0..Group is unlocked (write access allowed)
*/
#define SSARC_LP_DESC_CTRL1_WL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_WL_SHIFT)) & SSARC_LP_DESC_CTRL1_WL_MASK)
#define SSARC_LP_DESC_CTRL1_DL_MASK (0x100000U)
#define SSARC_LP_DESC_CTRL1_DL_SHIFT (20U)
/*! DL - Domain lock
* 0b1..Lock
* 0b0..Unlock
*/
#define SSARC_LP_DESC_CTRL1_DL(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_CTRL1_DL_SHIFT)) & SSARC_LP_DESC_CTRL1_DL_MASK)
/*! @} */
/* The count of SSARC_LP_DESC_CTRL1 */
#define SSARC_LP_DESC_CTRL1_COUNT (16U)
/*! @name DESC_ADDR_UP - Descriptor Address Up 0 Register..Descriptor Address Up 15 Register */
/*! @{ */
#define SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK (0xFFFFFFFFU)
#define SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT (0U)
/*! ADDR_UP - Address field (High)
*/
#define SSARC_LP_DESC_ADDR_UP_ADDR_UP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_UP_ADDR_UP_SHIFT)) & SSARC_LP_DESC_ADDR_UP_ADDR_UP_MASK)
/*! @} */
/* The count of SSARC_LP_DESC_ADDR_UP */
#define SSARC_LP_DESC_ADDR_UP_COUNT (16U)
/*! @name DESC_ADDR_DOWN - Descriptor Address Down 0 Register..Descriptor Address Down 15 Register */
/*! @{ */
#define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK (0xFFFFFFFFU)
#define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT (0U)
/*! ADDR_DOWN - Address field (Low)
*/
#define SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_SHIFT)) & SSARC_LP_DESC_ADDR_DOWN_ADDR_DOWN_MASK)
/*! @} */
/* The count of SSARC_LP_DESC_ADDR_DOWN */
#define SSARC_LP_DESC_ADDR_DOWN_COUNT (16U)
/*! @name CTRL - Control Register */
/*! @{ */
#define SSARC_LP_CTRL_DIS_HW_REQ_MASK (0x8000000U)
#define SSARC_LP_CTRL_DIS_HW_REQ_SHIFT (27U)
/*! DIS_HW_REQ - Save/Restore request disable
* 0b0..PGMC save/restore requests enabled
* 0b1..PGMC save/restore requests disabled
*/
#define SSARC_LP_CTRL_DIS_HW_REQ(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_DIS_HW_REQ_SHIFT)) & SSARC_LP_CTRL_DIS_HW_REQ_MASK)
#define SSARC_LP_CTRL_SW_RESET_MASK (0x80000000U)
#define SSARC_LP_CTRL_SW_RESET_SHIFT (31U)
/*! SW_RESET - Software reset
*/
#define SSARC_LP_CTRL_SW_RESET(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_CTRL_SW_RESET_SHIFT)) & SSARC_LP_CTRL_SW_RESET_MASK)
/*! @} */
/*! @name INT_STATUS - Interrupt Status Register */
/*! @{ */
#define SSARC_LP_INT_STATUS_ERR_INDEX_MASK (0x3FFU)
#define SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT (0U)
/*! ERR_INDEX - Error Index
*/
#define SSARC_LP_INT_STATUS_ERR_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ERR_INDEX_SHIFT)) & SSARC_LP_INT_STATUS_ERR_INDEX_MASK)
#define SSARC_LP_INT_STATUS_AHB_RESP_MASK (0xC00U)
#define SSARC_LP_INT_STATUS_AHB_RESP_SHIFT (10U)
/*! AHB_RESP - AHB Bus response field
*/
#define SSARC_LP_INT_STATUS_AHB_RESP(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_RESP_SHIFT)) & SSARC_LP_INT_STATUS_AHB_RESP_MASK)
#define SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK (0x8000000U)
#define SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT (27U)
/*! GROUP_CONFLICT - Group Conflict field
* 0b1..A group conflict error has occurred
* 0b0..No group conflict error
*/
#define SSARC_LP_INT_STATUS_GROUP_CONFLICT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_GROUP_CONFLICT_SHIFT)) & SSARC_LP_INT_STATUS_GROUP_CONFLICT_MASK)
#define SSARC_LP_INT_STATUS_TIMEOUT_MASK (0x10000000U)
#define SSARC_LP_INT_STATUS_TIMEOUT_SHIFT (28U)
/*! TIMEOUT - Timeout field
* 0b1..A timeout event has occurred
* 0b0..No timeout event
*/
#define SSARC_LP_INT_STATUS_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_TIMEOUT_SHIFT)) & SSARC_LP_INT_STATUS_TIMEOUT_MASK)
#define SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK (0x20000000U)
#define SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT (29U)
/*! SW_REQ_DONE - Software Request Done
* 0b1..Atleast one software triggered has been complete
* 0b0..No software triggered requests or software triggered request still in progress
*/
#define SSARC_LP_INT_STATUS_SW_REQ_DONE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_SW_REQ_DONE_SHIFT)) & SSARC_LP_INT_STATUS_SW_REQ_DONE_MASK)
#define SSARC_LP_INT_STATUS_AHB_ERR_MASK (0x40000000U)
#define SSARC_LP_INT_STATUS_AHB_ERR_SHIFT (30U)
/*! AHB_ERR - AHB Error field
* 0b1..An AHB error has occurred
* 0b0..No AHB error
*/
#define SSARC_LP_INT_STATUS_AHB_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_AHB_ERR_SHIFT)) & SSARC_LP_INT_STATUS_AHB_ERR_MASK)
#define SSARC_LP_INT_STATUS_ADDR_ERR_MASK (0x80000000U)
#define SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT (31U)
/*! ADDR_ERR - Address Error field
* 0b1..An address error has occurred
* 0b0..No address error
*/
#define SSARC_LP_INT_STATUS_ADDR_ERR(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_INT_STATUS_ADDR_ERR_SHIFT)) & SSARC_LP_INT_STATUS_ADDR_ERR_MASK)
/*! @} */
/*! @name HP_TIMEOUT - HP Timeout Register */
/*! @{ */
#define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK (0xFFFFFFFFU)
#define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT (0U)
/*! TIMEOUT_VALUE - Time out value
*/
#define SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_SHIFT)) & SSARC_LP_HP_TIMEOUT_TIMEOUT_VALUE_MASK)
/*! @} */
/*! @name HW_GROUP_PENDING - Hardware Request Pending Register */
/*! @{ */
#define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK (0xFFFFU)
#define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT (0U)
/*! HW_SAVE_PENDING - This field indicates which groups are pending for save from hardware request
*/
#define SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_SAVE_PENDING_MASK)
#define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK (0xFFFF0000U)
#define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT (16U)
/*! HW_RESTORE_PENDING - This field indicates which groups are pending for restore from hardware request
*/
#define SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_SHIFT)) & SSARC_LP_HW_GROUP_PENDING_HW_RESTORE_PENDING_MASK)
/*! @} */
/*! @name SW_GROUP_PENDING - Software Request Pending Register */
/*! @{ */
#define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK (0xFFFFU)
#define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT (0U)
/*! SW_SAVE_PENDING - This field indicates which groups are pending for save from software request
*/
#define SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_SAVE_PENDING_MASK)
#define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK (0xFFFF0000U)
#define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT (16U)
/*! SW_RESTORE_PENDING - This field indicates which groups are pending for restore from software request
*/
#define SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING(x) (((uint32_t)(((uint32_t)(x)) << SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_SHIFT)) & SSARC_LP_SW_GROUP_PENDING_SW_RESTORE_PENDING_MASK)
/*! @} */
/*!
* @}
*/ /* end of group SSARC_LP_Register_Masks */
/* SSARC_LP - Peripheral instance base addresses */
/** Peripheral SSARC_LP base address */
#define SSARC_LP_BASE (0x40CB8000u)
/** Peripheral SSARC_LP base pointer */
#define SSARC_LP ((SSARC_LP_Type *)SSARC_LP_BASE)
/** Array initializer of SSARC_LP peripheral base addresses */
#define SSARC_LP_BASE_ADDRS { SSARC_LP_BASE }
/** Array initializer of SSARC_LP peripheral base pointers */
#define SSARC_LP_BASE_PTRS { SSARC_LP }
/*!
* @}
*/ /* end of group SSARC_LP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TMPSNS Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TMPSNS_Peripheral_Access_Layer TMPSNS Peripheral Access Layer
* @{
*/
/** TMPSNS - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL0; /**< Temperature Sensor Control Register 0, offset: 0x0 */
__IO uint32_t CTRL0_SET; /**< Temperature Sensor Control Register 0, offset: 0x4 */
__IO uint32_t CTRL0_CLR; /**< Temperature Sensor Control Register 0, offset: 0x8 */
__IO uint32_t CTRL0_TOG; /**< Temperature Sensor Control Register 0, offset: 0xC */
__IO uint32_t CTRL1; /**< Temperature Sensor Control Register 1, offset: 0x10 */
__IO uint32_t CTRL1_SET; /**< Temperature Sensor Control Register 1, offset: 0x14 */
__IO uint32_t CTRL1_CLR; /**< Temperature Sensor Control Register 1, offset: 0x18 */
__IO uint32_t CTRL1_TOG; /**< Temperature Sensor Control Register 1, offset: 0x1C */
__IO uint32_t RANGE0; /**< Temperature Sensor Range Register 0, offset: 0x20 */
__IO uint32_t RANGE0_SET; /**< Temperature Sensor Range Register 0, offset: 0x24 */
__IO uint32_t RANGE0_CLR; /**< Temperature Sensor Range Register 0, offset: 0x28 */
__IO uint32_t RANGE0_TOG; /**< Temperature Sensor Range Register 0, offset: 0x2C */
__IO uint32_t RANGE1; /**< Temperature Sensor Range Register 1, offset: 0x30 */
__IO uint32_t RANGE1_SET; /**< Temperature Sensor Range Register 1, offset: 0x34 */
__IO uint32_t RANGE1_CLR; /**< Temperature Sensor Range Register 1, offset: 0x38 */
__IO uint32_t RANGE1_TOG; /**< Temperature Sensor Range Register 1, offset: 0x3C */
uint8_t RESERVED_0[16];
__IO uint32_t STATUS0; /**< Temperature Sensor Status Register 0, offset: 0x50 */
} TMPSNS_Type;
/* ----------------------------------------------------------------------------
-- TMPSNS Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TMPSNS_Register_Masks TMPSNS Register Masks
* @{
*/
/*! @name CTRL0 - Temperature Sensor Control Register 0 */
/*! @{ */
#define TMPSNS_CTRL0_SLOPE_CAL_MASK (0x3FU)
#define TMPSNS_CTRL0_SLOPE_CAL_SHIFT (0U)
/*! SLOPE_CAL - Ramp slope calibration control
*/
#define TMPSNS_CTRL0_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SLOPE_CAL_MASK)
#define TMPSNS_CTRL0_V_SEL_MASK (0x300U)
#define TMPSNS_CTRL0_V_SEL_SHIFT (8U)
/*! V_SEL - Voltage Select
* 0b00..Normal temperature measuring mode
* 0b01-0b10..Reserved
*/
#define TMPSNS_CTRL0_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_V_SEL_SHIFT)) & TMPSNS_CTRL0_V_SEL_MASK)
#define TMPSNS_CTRL0_IBIAS_TRIM_MASK (0xF000U)
#define TMPSNS_CTRL0_IBIAS_TRIM_SHIFT (12U)
/*! IBIAS_TRIM - Current bias trim value
*/
#define TMPSNS_CTRL0_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_IBIAS_TRIM_MASK)
/*! @} */
/*! @name CTRL0_SET - Temperature Sensor Control Register 0 */
/*! @{ */
#define TMPSNS_CTRL0_SET_SLOPE_CAL_MASK (0x3FU)
#define TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT (0U)
/*! SLOPE_CAL - Ramp slope calibration control
*/
#define TMPSNS_CTRL0_SET_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_SET_SLOPE_CAL_MASK)
#define TMPSNS_CTRL0_SET_V_SEL_MASK (0x300U)
#define TMPSNS_CTRL0_SET_V_SEL_SHIFT (8U)
/*! V_SEL - Voltage Select
*/
#define TMPSNS_CTRL0_SET_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_V_SEL_SHIFT)) & TMPSNS_CTRL0_SET_V_SEL_MASK)
#define TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK (0xF000U)
#define TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT (12U)
/*! IBIAS_TRIM - Current bias trim value
*/
#define TMPSNS_CTRL0_SET_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_SET_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_SET_IBIAS_TRIM_MASK)
/*! @} */
/*! @name CTRL0_CLR - Temperature Sensor Control Register 0 */
/*! @{ */
#define TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK (0x3FU)
#define TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT (0U)
/*! SLOPE_CAL - Ramp slope calibration control
*/
#define TMPSNS_CTRL0_CLR_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_CLR_SLOPE_CAL_MASK)
#define TMPSNS_CTRL0_CLR_V_SEL_MASK (0x300U)
#define TMPSNS_CTRL0_CLR_V_SEL_SHIFT (8U)
/*! V_SEL - Voltage Select
*/
#define TMPSNS_CTRL0_CLR_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_V_SEL_SHIFT)) & TMPSNS_CTRL0_CLR_V_SEL_MASK)
#define TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK (0xF000U)
#define TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT (12U)
/*! IBIAS_TRIM - Current bias trim value
*/
#define TMPSNS_CTRL0_CLR_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_CLR_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_CLR_IBIAS_TRIM_MASK)
/*! @} */
/*! @name CTRL0_TOG - Temperature Sensor Control Register 0 */
/*! @{ */
#define TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK (0x3FU)
#define TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT (0U)
/*! SLOPE_CAL - Ramp slope calibration control
*/
#define TMPSNS_CTRL0_TOG_SLOPE_CAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_SLOPE_CAL_SHIFT)) & TMPSNS_CTRL0_TOG_SLOPE_CAL_MASK)
#define TMPSNS_CTRL0_TOG_V_SEL_MASK (0x300U)
#define TMPSNS_CTRL0_TOG_V_SEL_SHIFT (8U)
/*! V_SEL - Voltage Select
*/
#define TMPSNS_CTRL0_TOG_V_SEL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_V_SEL_SHIFT)) & TMPSNS_CTRL0_TOG_V_SEL_MASK)
#define TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK (0xF000U)
#define TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT (12U)
/*! IBIAS_TRIM - Current bias trim value
*/
#define TMPSNS_CTRL0_TOG_IBIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL0_TOG_IBIAS_TRIM_SHIFT)) & TMPSNS_CTRL0_TOG_IBIAS_TRIM_MASK)
/*! @} */
/*! @name CTRL1 - Temperature Sensor Control Register 1 */
/*! @{ */
#define TMPSNS_CTRL1_FREQ_MASK (0xFFFFU)
#define TMPSNS_CTRL1_FREQ_SHIFT (0U)
/*! FREQ - Temperature Measurement Frequency
* 0b0000000000000000..Single Reading Mode. New reading available every time CTRL1[START] bit is set to 1 from 0.
* 0b0000000000000001-0b1111111111111111..Continuous Reading Mode. Next temperature reading taken after programmed number of cycles after current reading is complete.
*/
#define TMPSNS_CTRL1_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FREQ_SHIFT)) & TMPSNS_CTRL1_FREQ_MASK)
#define TMPSNS_CTRL1_FINISH_IE_MASK (0x10000U)
#define TMPSNS_CTRL1_FINISH_IE_SHIFT (16U)
/*! FINISH_IE - Measurement finished interrupt enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define TMPSNS_CTRL1_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_FINISH_IE_MASK)
#define TMPSNS_CTRL1_LOW_TEMP_IE_MASK (0x20000U)
#define TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT (17U)
/*! LOW_TEMP_IE - Low temperature interrupt enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define TMPSNS_CTRL1_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_LOW_TEMP_IE_MASK)
#define TMPSNS_CTRL1_HIGH_TEMP_IE_MASK (0x40000U)
#define TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT (18U)
/*! HIGH_TEMP_IE - High temperature interrupt enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define TMPSNS_CTRL1_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_HIGH_TEMP_IE_MASK)
#define TMPSNS_CTRL1_PANIC_TEMP_IE_MASK (0x80000U)
#define TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT (19U)
/*! PANIC_TEMP_IE - Panic temperature interrupt enable
* 0b0..Interrupt is disabled
* 0b1..Interrupt is enabled
*/
#define TMPSNS_CTRL1_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_PANIC_TEMP_IE_MASK)
#define TMPSNS_CTRL1_START_MASK (0x400000U)
#define TMPSNS_CTRL1_START_SHIFT (22U)
/*! START - Start Temperature Measurement
* 0b0..No new temperature reading taken
* 0b1..Initiate a new temperature reading
*/
#define TMPSNS_CTRL1_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_START_SHIFT)) & TMPSNS_CTRL1_START_MASK)
#define TMPSNS_CTRL1_PWD_MASK (0x800000U)
#define TMPSNS_CTRL1_PWD_SHIFT (23U)
/*! PWD - Temperature Sensor Power Down
* 0b0..Sensor is active
* 0b1..Sensor is powered down
*/
#define TMPSNS_CTRL1_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_SHIFT)) & TMPSNS_CTRL1_PWD_MASK)
#define TMPSNS_CTRL1_RFU_MASK (0x7F000000U)
#define TMPSNS_CTRL1_RFU_SHIFT (24U)
/*! RFU - Read/Writeable field. Reserved for future use
*/
#define TMPSNS_CTRL1_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_RFU_SHIFT)) & TMPSNS_CTRL1_RFU_MASK)
#define TMPSNS_CTRL1_PWD_FULL_MASK (0x80000000U)
#define TMPSNS_CTRL1_PWD_FULL_SHIFT (31U)
/*! PWD_FULL - Temperature Sensor Full Power Down
* 0b0..Sensor is active
* 0b1..Sensor is powered down
*/
#define TMPSNS_CTRL1_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_PWD_FULL_MASK)
/*! @} */
/*! @name CTRL1_SET - Temperature Sensor Control Register 1 */
/*! @{ */
#define TMPSNS_CTRL1_SET_FREQ_MASK (0xFFFFU)
#define TMPSNS_CTRL1_SET_FREQ_SHIFT (0U)
/*! FREQ - Temperature Measurement Frequency
*/
#define TMPSNS_CTRL1_SET_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FREQ_SHIFT)) & TMPSNS_CTRL1_SET_FREQ_MASK)
#define TMPSNS_CTRL1_SET_FINISH_IE_MASK (0x10000U)
#define TMPSNS_CTRL1_SET_FINISH_IE_SHIFT (16U)
/*! FINISH_IE - Measurement finished interrupt enable
*/
#define TMPSNS_CTRL1_SET_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_SET_FINISH_IE_MASK)
#define TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK (0x20000U)
#define TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT (17U)
/*! LOW_TEMP_IE - Low temperature interrupt enable
*/
#define TMPSNS_CTRL1_SET_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_LOW_TEMP_IE_MASK)
#define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK (0x40000U)
#define TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT (18U)
/*! HIGH_TEMP_IE - High temperature interrupt enable
*/
#define TMPSNS_CTRL1_SET_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_HIGH_TEMP_IE_MASK)
#define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK (0x80000U)
#define TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT (19U)
/*! PANIC_TEMP_IE - Panic temperature interrupt enable
*/
#define TMPSNS_CTRL1_SET_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_SET_PANIC_TEMP_IE_MASK)
#define TMPSNS_CTRL1_SET_START_MASK (0x400000U)
#define TMPSNS_CTRL1_SET_START_SHIFT (22U)
/*! START - Start Temperature Measurement
*/
#define TMPSNS_CTRL1_SET_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_START_SHIFT)) & TMPSNS_CTRL1_SET_START_MASK)
#define TMPSNS_CTRL1_SET_PWD_MASK (0x800000U)
#define TMPSNS_CTRL1_SET_PWD_SHIFT (23U)
/*! PWD - Temperature Sensor Power Down
*/
#define TMPSNS_CTRL1_SET_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_SHIFT)) & TMPSNS_CTRL1_SET_PWD_MASK)
#define TMPSNS_CTRL1_SET_RFU_MASK (0x7F000000U)
#define TMPSNS_CTRL1_SET_RFU_SHIFT (24U)
/*! RFU - Read/Writeable field. Reserved for future use
*/
#define TMPSNS_CTRL1_SET_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_RFU_SHIFT)) & TMPSNS_CTRL1_SET_RFU_MASK)
#define TMPSNS_CTRL1_SET_PWD_FULL_MASK (0x80000000U)
#define TMPSNS_CTRL1_SET_PWD_FULL_SHIFT (31U)
/*! PWD_FULL - Temperature Sensor Full Power Down
*/
#define TMPSNS_CTRL1_SET_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_SET_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_SET_PWD_FULL_MASK)
/*! @} */
/*! @name CTRL1_CLR - Temperature Sensor Control Register 1 */
/*! @{ */
#define TMPSNS_CTRL1_CLR_FREQ_MASK (0xFFFFU)
#define TMPSNS_CTRL1_CLR_FREQ_SHIFT (0U)
/*! FREQ - Temperature Measurement Frequency
*/
#define TMPSNS_CTRL1_CLR_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FREQ_SHIFT)) & TMPSNS_CTRL1_CLR_FREQ_MASK)
#define TMPSNS_CTRL1_CLR_FINISH_IE_MASK (0x10000U)
#define TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT (16U)
/*! FINISH_IE - Measurement finished interrupt enable
*/
#define TMPSNS_CTRL1_CLR_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_CLR_FINISH_IE_MASK)
#define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK (0x20000U)
#define TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT (17U)
/*! LOW_TEMP_IE - Low temperature interrupt enable
*/
#define TMPSNS_CTRL1_CLR_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_LOW_TEMP_IE_MASK)
#define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK (0x40000U)
#define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT (18U)
/*! HIGH_TEMP_IE - High temperature interrupt enable
*/
#define TMPSNS_CTRL1_CLR_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_HIGH_TEMP_IE_MASK)
#define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK (0x80000U)
#define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT (19U)
/*! PANIC_TEMP_IE - Panic temperature interrupt enable
*/
#define TMPSNS_CTRL1_CLR_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_CLR_PANIC_TEMP_IE_MASK)
#define TMPSNS_CTRL1_CLR_START_MASK (0x400000U)
#define TMPSNS_CTRL1_CLR_START_SHIFT (22U)
/*! START - Start Temperature Measurement
*/
#define TMPSNS_CTRL1_CLR_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_START_SHIFT)) & TMPSNS_CTRL1_CLR_START_MASK)
#define TMPSNS_CTRL1_CLR_PWD_MASK (0x800000U)
#define TMPSNS_CTRL1_CLR_PWD_SHIFT (23U)
/*! PWD - Temperature Sensor Power Down
*/
#define TMPSNS_CTRL1_CLR_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_MASK)
#define TMPSNS_CTRL1_CLR_RFU_MASK (0x7F000000U)
#define TMPSNS_CTRL1_CLR_RFU_SHIFT (24U)
/*! RFU - Read/Writeable field. Reserved for future use
*/
#define TMPSNS_CTRL1_CLR_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_RFU_SHIFT)) & TMPSNS_CTRL1_CLR_RFU_MASK)
#define TMPSNS_CTRL1_CLR_PWD_FULL_MASK (0x80000000U)
#define TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT (31U)
/*! PWD_FULL - Temperature Sensor Full Power Down
*/
#define TMPSNS_CTRL1_CLR_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_CLR_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_CLR_PWD_FULL_MASK)
/*! @} */
/*! @name CTRL1_TOG - Temperature Sensor Control Register 1 */
/*! @{ */
#define TMPSNS_CTRL1_TOG_FREQ_MASK (0xFFFFU)
#define TMPSNS_CTRL1_TOG_FREQ_SHIFT (0U)
/*! FREQ - Temperature Measurement Frequency
*/
#define TMPSNS_CTRL1_TOG_FREQ(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FREQ_SHIFT)) & TMPSNS_CTRL1_TOG_FREQ_MASK)
#define TMPSNS_CTRL1_TOG_FINISH_IE_MASK (0x10000U)
#define TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT (16U)
/*! FINISH_IE - Measurement finished interrupt enable
*/
#define TMPSNS_CTRL1_TOG_FINISH_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_FINISH_IE_SHIFT)) & TMPSNS_CTRL1_TOG_FINISH_IE_MASK)
#define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK (0x20000U)
#define TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT (17U)
/*! LOW_TEMP_IE - Low temperature interrupt enable
*/
#define TMPSNS_CTRL1_TOG_LOW_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_LOW_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_LOW_TEMP_IE_MASK)
#define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK (0x40000U)
#define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT (18U)
/*! HIGH_TEMP_IE - High temperature interrupt enable
*/
#define TMPSNS_CTRL1_TOG_HIGH_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_HIGH_TEMP_IE_MASK)
#define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK (0x80000U)
#define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT (19U)
/*! PANIC_TEMP_IE - Panic temperature interrupt enable
*/
#define TMPSNS_CTRL1_TOG_PANIC_TEMP_IE(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_SHIFT)) & TMPSNS_CTRL1_TOG_PANIC_TEMP_IE_MASK)
#define TMPSNS_CTRL1_TOG_START_MASK (0x400000U)
#define TMPSNS_CTRL1_TOG_START_SHIFT (22U)
/*! START - Start Temperature Measurement
*/
#define TMPSNS_CTRL1_TOG_START(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_START_SHIFT)) & TMPSNS_CTRL1_TOG_START_MASK)
#define TMPSNS_CTRL1_TOG_PWD_MASK (0x800000U)
#define TMPSNS_CTRL1_TOG_PWD_SHIFT (23U)
/*! PWD - Temperature Sensor Power Down
*/
#define TMPSNS_CTRL1_TOG_PWD(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_MASK)
#define TMPSNS_CTRL1_TOG_RFU_MASK (0x7F000000U)
#define TMPSNS_CTRL1_TOG_RFU_SHIFT (24U)
/*! RFU - Read/Writeable field. Reserved for future use
*/
#define TMPSNS_CTRL1_TOG_RFU(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_RFU_SHIFT)) & TMPSNS_CTRL1_TOG_RFU_MASK)
#define TMPSNS_CTRL1_TOG_PWD_FULL_MASK (0x80000000U)
#define TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT (31U)
/*! PWD_FULL - Temperature Sensor Full Power Down
*/
#define TMPSNS_CTRL1_TOG_PWD_FULL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_CTRL1_TOG_PWD_FULL_SHIFT)) & TMPSNS_CTRL1_TOG_PWD_FULL_MASK)
/*! @} */
/*! @name RANGE0 - Temperature Sensor Range Register 0 */
/*! @{ */
#define TMPSNS_RANGE0_LOW_TEMP_VAL_MASK (0xFFFU)
#define TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT (0U)
/*! LOW_TEMP_VAL - Low temperature threshold value
*/
#define TMPSNS_RANGE0_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_LOW_TEMP_VAL_MASK)
#define TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK (0xFFF0000U)
#define TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT (16U)
/*! HIGH_TEMP_VAL - High temperature threshold value
*/
#define TMPSNS_RANGE0_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_HIGH_TEMP_VAL_MASK)
/*! @} */
/*! @name RANGE0_SET - Temperature Sensor Range Register 0 */
/*! @{ */
#define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK (0xFFFU)
#define TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT (0U)
/*! LOW_TEMP_VAL - Low temperature threshold value
*/
#define TMPSNS_RANGE0_SET_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_LOW_TEMP_VAL_MASK)
#define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK (0xFFF0000U)
#define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT (16U)
/*! HIGH_TEMP_VAL - High temperature threshold value
*/
#define TMPSNS_RANGE0_SET_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_SET_HIGH_TEMP_VAL_MASK)
/*! @} */
/*! @name RANGE0_CLR - Temperature Sensor Range Register 0 */
/*! @{ */
#define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK (0xFFFU)
#define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT (0U)
/*! LOW_TEMP_VAL - Low temperature threshold value
*/
#define TMPSNS_RANGE0_CLR_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_LOW_TEMP_VAL_MASK)
#define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK (0xFFF0000U)
#define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT (16U)
/*! HIGH_TEMP_VAL - High temperature threshold value
*/
#define TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_CLR_HIGH_TEMP_VAL_MASK)
/*! @} */
/*! @name RANGE0_TOG - Temperature Sensor Range Register 0 */
/*! @{ */
#define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK (0xFFFU)
#define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT (0U)
/*! LOW_TEMP_VAL - Low temperature threshold value
*/
#define TMPSNS_RANGE0_TOG_LOW_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_LOW_TEMP_VAL_MASK)
#define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK (0xFFF0000U)
#define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT (16U)
/*! HIGH_TEMP_VAL - High temperature threshold value
*/
#define TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_SHIFT)) & TMPSNS_RANGE0_TOG_HIGH_TEMP_VAL_MASK)
/*! @} */
/*! @name RANGE1 - Temperature Sensor Range Register 1 */
/*! @{ */
#define TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK (0xFFFU)
#define TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT (0U)
/*! PANIC_TEMP_VAL - Panic temperature threshold value
*/
#define TMPSNS_RANGE1_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_PANIC_TEMP_VAL_MASK)
/*! @} */
/*! @name RANGE1_SET - Temperature Sensor Range Register 1 */
/*! @{ */
#define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK (0xFFFU)
#define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT (0U)
/*! PANIC_TEMP_VAL - Panic temperature threshold value
*/
#define TMPSNS_RANGE1_SET_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_SET_PANIC_TEMP_VAL_MASK)
/*! @} */
/*! @name RANGE1_CLR - Temperature Sensor Range Register 1 */
/*! @{ */
#define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK (0xFFFU)
#define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT (0U)
/*! PANIC_TEMP_VAL - Panic temperature threshold value
*/
#define TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_CLR_PANIC_TEMP_VAL_MASK)
/*! @} */
/*! @name RANGE1_TOG - Temperature Sensor Range Register 1 */
/*! @{ */
#define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK (0xFFFU)
#define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT (0U)
/*! PANIC_TEMP_VAL - Panic temperature threshold value
*/
#define TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_SHIFT)) & TMPSNS_RANGE1_TOG_PANIC_TEMP_VAL_MASK)
/*! @} */
/*! @name STATUS0 - Temperature Sensor Status Register 0 */
/*! @{ */
#define TMPSNS_STATUS0_TEMP_VAL_MASK (0xFFFU)
#define TMPSNS_STATUS0_TEMP_VAL_SHIFT (0U)
/*! TEMP_VAL - Measured temperature value
*/
#define TMPSNS_STATUS0_TEMP_VAL(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_TEMP_VAL_SHIFT)) & TMPSNS_STATUS0_TEMP_VAL_MASK)
#define TMPSNS_STATUS0_FINISH_MASK (0x10000U)
#define TMPSNS_STATUS0_FINISH_SHIFT (16U)
/*! FINISH - Temperature measurement complete
* 0b0..Temperature sensor is busy (if CTRL1[START] = 1)or no new reading has been initiated (if CTRL1[START] = 0)
* 0b1..Temperature reading is complete and new temperature value available for reading
*/
#define TMPSNS_STATUS0_FINISH(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_FINISH_SHIFT)) & TMPSNS_STATUS0_FINISH_MASK)
#define TMPSNS_STATUS0_LOW_TEMP_MASK (0x20000U)
#define TMPSNS_STATUS0_LOW_TEMP_SHIFT (17U)
/*! LOW_TEMP - Low temperature alarm bit
* 0b0..No Low temperature alert
* 0b1..Low temperature alert
*/
#define TMPSNS_STATUS0_LOW_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_LOW_TEMP_SHIFT)) & TMPSNS_STATUS0_LOW_TEMP_MASK)
#define TMPSNS_STATUS0_HIGH_TEMP_MASK (0x40000U)
#define TMPSNS_STATUS0_HIGH_TEMP_SHIFT (18U)
/*! HIGH_TEMP - High temperature alarm bit
* 0b0..No High temperature alert
* 0b1..High temperature alert
*/
#define TMPSNS_STATUS0_HIGH_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_HIGH_TEMP_SHIFT)) & TMPSNS_STATUS0_HIGH_TEMP_MASK)
#define TMPSNS_STATUS0_PANIC_TEMP_MASK (0x80000U)
#define TMPSNS_STATUS0_PANIC_TEMP_SHIFT (19U)
/*! PANIC_TEMP - Panic temperature alarm bit
* 0b0..No Panic temperature alert
* 0b1..Panic temperature alert
*/
#define TMPSNS_STATUS0_PANIC_TEMP(x) (((uint32_t)(((uint32_t)(x)) << TMPSNS_STATUS0_PANIC_TEMP_SHIFT)) & TMPSNS_STATUS0_PANIC_TEMP_MASK)
/*! @} */
/*!
* @}
*/ /* end of group TMPSNS_Register_Masks */
/* TMPSNS - Peripheral instance base addresses */
/** Peripheral TMPSNS base address */
#define TMPSNS_BASE (0u)
/** Peripheral TMPSNS base pointer */
#define TMPSNS ((TMPSNS_Type *)TMPSNS_BASE)
/** Array initializer of TMPSNS peripheral base addresses */
#define TMPSNS_BASE_ADDRS { TMPSNS_BASE }
/** Array initializer of TMPSNS peripheral base pointers */
#define TMPSNS_BASE_PTRS { TMPSNS }
/*!
* @}
*/ /* end of group TMPSNS_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- TMR Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup TMR_Peripheral_Access_Layer TMR Peripheral Access Layer
* @{
*/
/** TMR - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0, array step: 0x20 */
__IO uint16_t COMP1; /**< Timer Channel Compare Register 1, array offset: 0x0, array step: 0x20 */
__IO uint16_t COMP2; /**< Timer Channel Compare Register 2, array offset: 0x2, array step: 0x20 */
__IO uint16_t CAPT; /**< Timer Channel Capture Register, array offset: 0x4, array step: 0x20 */
__IO uint16_t LOAD; /**< Timer Channel Load Register, array offset: 0x6, array step: 0x20 */
__IO uint16_t HOLD; /**< Timer Channel Hold Register, array offset: 0x8, array step: 0x20 */
__IO uint16_t CNTR; /**< Timer Channel Counter Register, array offset: 0xA, array step: 0x20 */
__IO uint16_t CTRL; /**< Timer Channel Control Register, array offset: 0xC, array step: 0x20 */
__IO uint16_t SCTRL; /**< Timer Channel Status and Control Register, array offset: 0xE, array step: 0x20 */
__IO uint16_t CMPLD1; /**< Timer Channel Comparator Load Register 1, array offset: 0x10, array step: 0x20 */
__IO uint16_t CMPLD2; /**< Timer Channel Comparator Load Register 2, array offset: 0x12, array step: 0x20 */
__IO uint16_t CSCTRL; /**< Timer Channel Comparator Status and Control Register, array offset: 0x14, array step: 0x20 */
__IO uint16_t FILT; /**< Timer Channel Input Filter Register, array offset: 0x16, array step: 0x20 */
__IO uint16_t DMA; /**< Timer Channel DMA Enable Register, array offset: 0x18, array step: 0x20 */
uint8_t RESERVED_0[4];
__IO uint16_t ENBL; /**< Timer Channel Enable Register, array offset: 0x1E, array step: 0x20, this item is not available for all array instances */
} CHANNEL[4];
} TMR_Type;
/* ----------------------------------------------------------------------------
-- TMR Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup TMR_Register_Masks TMR Register Masks
* @{
*/
/*! @name COMP1 - Timer Channel Compare Register 1 */
/*! @{ */
#define TMR_COMP1_COMPARISON_1_MASK (0xFFFFU)
#define TMR_COMP1_COMPARISON_1_SHIFT (0U)
/*! COMPARISON_1 - Comparison Value 1
*/
#define TMR_COMP1_COMPARISON_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP1_COMPARISON_1_SHIFT)) & TMR_COMP1_COMPARISON_1_MASK)
/*! @} */
/* The count of TMR_COMP1 */
#define TMR_COMP1_COUNT (4U)
/*! @name COMP2 - Timer Channel Compare Register 2 */
/*! @{ */
#define TMR_COMP2_COMPARISON_2_MASK (0xFFFFU)
#define TMR_COMP2_COMPARISON_2_SHIFT (0U)
/*! COMPARISON_2 - Comparison Value 2
*/
#define TMR_COMP2_COMPARISON_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_COMP2_COMPARISON_2_SHIFT)) & TMR_COMP2_COMPARISON_2_MASK)
/*! @} */
/* The count of TMR_COMP2 */
#define TMR_COMP2_COUNT (4U)
/*! @name CAPT - Timer Channel Capture Register */
/*! @{ */
#define TMR_CAPT_CAPTURE_MASK (0xFFFFU)
#define TMR_CAPT_CAPTURE_SHIFT (0U)
/*! CAPTURE - Capture Value
*/
#define TMR_CAPT_CAPTURE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CAPT_CAPTURE_SHIFT)) & TMR_CAPT_CAPTURE_MASK)
/*! @} */
/* The count of TMR_CAPT */
#define TMR_CAPT_COUNT (4U)
/*! @name LOAD - Timer Channel Load Register */
/*! @{ */
#define TMR_LOAD_LOAD_MASK (0xFFFFU)
#define TMR_LOAD_LOAD_SHIFT (0U)
/*! LOAD - Timer Load Register
*/
#define TMR_LOAD_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_LOAD_LOAD_SHIFT)) & TMR_LOAD_LOAD_MASK)
/*! @} */
/* The count of TMR_LOAD */
#define TMR_LOAD_COUNT (4U)
/*! @name HOLD - Timer Channel Hold Register */
/*! @{ */
#define TMR_HOLD_HOLD_MASK (0xFFFFU)
#define TMR_HOLD_HOLD_SHIFT (0U)
/*! HOLD - HOLD
*/
#define TMR_HOLD_HOLD(x) (((uint16_t)(((uint16_t)(x)) << TMR_HOLD_HOLD_SHIFT)) & TMR_HOLD_HOLD_MASK)
/*! @} */
/* The count of TMR_HOLD */
#define TMR_HOLD_COUNT (4U)
/*! @name CNTR - Timer Channel Counter Register */
/*! @{ */
#define TMR_CNTR_COUNTER_MASK (0xFFFFU)
#define TMR_CNTR_COUNTER_SHIFT (0U)
/*! COUNTER - COUNTER
*/
#define TMR_CNTR_COUNTER(x) (((uint16_t)(((uint16_t)(x)) << TMR_CNTR_COUNTER_SHIFT)) & TMR_CNTR_COUNTER_MASK)
/*! @} */
/* The count of TMR_CNTR */
#define TMR_CNTR_COUNT (4U)
/*! @name CTRL - Timer Channel Control Register */
/*! @{ */
#define TMR_CTRL_OUTMODE_MASK (0x7U)
#define TMR_CTRL_OUTMODE_SHIFT (0U)
/*! OUTMODE - Output Mode
* 0b000..Asserted while counter is active
* 0b001..Clear OFLAG output on successful compare
* 0b010..Set OFLAG output on successful compare
* 0b011..Toggle OFLAG output on successful compare
* 0b100..Toggle OFLAG output using alternating compare registers
* 0b101..Set on compare, cleared on secondary source input edge
* 0b110..Set on compare, cleared on counter rollover
* 0b111..Enable gated clock output while counter is active
*/
#define TMR_CTRL_OUTMODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_OUTMODE_SHIFT)) & TMR_CTRL_OUTMODE_MASK)
#define TMR_CTRL_COINIT_MASK (0x8U)
#define TMR_CTRL_COINIT_SHIFT (3U)
/*! COINIT - Co-Channel Initialization
* 0b0..Co-channel counter/timers cannot force a re-initialization of this counter/timer
* 0b1..Co-channel counter/timers may force a re-initialization of this counter/timer
*/
#define TMR_CTRL_COINIT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_COINIT_SHIFT)) & TMR_CTRL_COINIT_MASK)
#define TMR_CTRL_DIR_MASK (0x10U)
#define TMR_CTRL_DIR_SHIFT (4U)
/*! DIR - Count Direction
* 0b0..Count up.
* 0b1..Count down.
*/
#define TMR_CTRL_DIR(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_DIR_SHIFT)) & TMR_CTRL_DIR_MASK)
#define TMR_CTRL_LENGTH_MASK (0x20U)
#define TMR_CTRL_LENGTH_SHIFT (5U)
/*! LENGTH - Count Length
* 0b0..Count until roll over at $FFFF and continue from $0000.
* 0b1..Count until compare, then re-initialize. If counting up, a successful compare occurs when the counter
* reaches a COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value.
* When output mode $4 is used, alternating values of COMP1 and COMP2 are used to generate successful
* comparisons. For example, the counter counts until a COMP1 value is reached, re-initializes, counts until COMP2
* value is reached, re-initializes, counts until COMP1 value is reached, and so on.
*/
#define TMR_CTRL_LENGTH(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_LENGTH_SHIFT)) & TMR_CTRL_LENGTH_MASK)
#define TMR_CTRL_ONCE_MASK (0x40U)
#define TMR_CTRL_ONCE_SHIFT (6U)
/*! ONCE - Count Once
* 0b0..Count repeatedly.
* 0b1..Count until compare and then stop. If counting up, a successful compare occurs when the counter reaches a
* COMP1 value. If counting down, a successful compare occurs when the counter reaches a COMP2 value. When
* output mode $4 is used, the counter re-initializes after reaching the COMP1 value, continues to count to
* the COMP2 value, and then stops.
*/
#define TMR_CTRL_ONCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_ONCE_SHIFT)) & TMR_CTRL_ONCE_MASK)
#define TMR_CTRL_SCS_MASK (0x180U)
#define TMR_CTRL_SCS_SHIFT (7U)
/*! SCS - Secondary Count Source
* 0b00..Counter 0 input pin
* 0b01..Counter 1 input pin
* 0b10..Counter 2 input pin
* 0b11..Counter 3 input pin
*/
#define TMR_CTRL_SCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_SCS_SHIFT)) & TMR_CTRL_SCS_MASK)
#define TMR_CTRL_PCS_MASK (0x1E00U)
#define TMR_CTRL_PCS_SHIFT (9U)
/*! PCS - Primary Count Source
* 0b0000..Counter 0 input pin
* 0b0001..Counter 1 input pin
* 0b0010..Counter 2 input pin
* 0b0011..Counter 3 input pin
* 0b0100..Counter 0 output
* 0b0101..Counter 1 output
* 0b0110..Counter 2 output
* 0b0111..Counter 3 output
* 0b1000..IP bus clock divide by 1 prescaler
* 0b1001..IP bus clock divide by 2 prescaler
* 0b1010..IP bus clock divide by 4 prescaler
* 0b1011..IP bus clock divide by 8 prescaler
* 0b1100..IP bus clock divide by 16 prescaler
* 0b1101..IP bus clock divide by 32 prescaler
* 0b1110..IP bus clock divide by 64 prescaler
* 0b1111..IP bus clock divide by 128 prescaler
*/
#define TMR_CTRL_PCS(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_PCS_SHIFT)) & TMR_CTRL_PCS_MASK)
#define TMR_CTRL_CM_MASK (0xE000U)
#define TMR_CTRL_CM_SHIFT (13U)
/*! CM - Count Mode
* 0b000..No operation
* 0b001..Count rising edges of primary sourceRising edges are counted only when SCTRL[IPS] = 0. Falling edges
* are counted when SCTRL[IPS] = 1. If the primary count source is IP bus clock divide by 1, only rising
* edges are counted regardless of the value of SCTRL[IPS].
* 0b010..Count rising and falling edges of primary sourceIP bus clock divide by 1 cannot be used as a primary count source in edge count mode.
* 0b011..Count rising edges of primary source while secondary input high active
* 0b100..Quadrature count mode, uses primary and secondary sources
* 0b101..Count rising edges of primary source; secondary source specifies directionRising edges are counted only
* when SCTRL[IPS] = 0. Falling edges are counted when SCTRL[IPS] = 1.
* 0b110..Edge of secondary source triggers primary count until compare
* 0b111..Cascaded counter mode (up/down)The primary count source must be set to one of the counter outputs.
*/
#define TMR_CTRL_CM(x) (((uint16_t)(((uint16_t)(x)) << TMR_CTRL_CM_SHIFT)) & TMR_CTRL_CM_MASK)
/*! @} */
/* The count of TMR_CTRL */
#define TMR_CTRL_COUNT (4U)
/*! @name SCTRL - Timer Channel Status and Control Register */
/*! @{ */
#define TMR_SCTRL_OEN_MASK (0x1U)
#define TMR_SCTRL_OEN_SHIFT (0U)
/*! OEN - Output Enable
* 0b0..The external pin is configured as an input.
* 0b1..The OFLAG output signal is driven on the external pin. Other timer groups using this external pin as
* their input see the driven value. The polarity of the signal is determined by OPS.
*/
#define TMR_SCTRL_OEN(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OEN_SHIFT)) & TMR_SCTRL_OEN_MASK)
#define TMR_SCTRL_OPS_MASK (0x2U)
#define TMR_SCTRL_OPS_SHIFT (1U)
/*! OPS - Output Polarity Select
* 0b0..True polarity.
* 0b1..Inverted polarity.
*/
#define TMR_SCTRL_OPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_OPS_SHIFT)) & TMR_SCTRL_OPS_MASK)
#define TMR_SCTRL_FORCE_MASK (0x4U)
#define TMR_SCTRL_FORCE_SHIFT (2U)
/*! FORCE - Force OFLAG Output
*/
#define TMR_SCTRL_FORCE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_FORCE_SHIFT)) & TMR_SCTRL_FORCE_MASK)
#define TMR_SCTRL_VAL_MASK (0x8U)
#define TMR_SCTRL_VAL_SHIFT (3U)
/*! VAL - Forced OFLAG Value
*/
#define TMR_SCTRL_VAL(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_VAL_SHIFT)) & TMR_SCTRL_VAL_MASK)
#define TMR_SCTRL_EEOF_MASK (0x10U)
#define TMR_SCTRL_EEOF_SHIFT (4U)
/*! EEOF - Enable External OFLAG Force
*/
#define TMR_SCTRL_EEOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_EEOF_SHIFT)) & TMR_SCTRL_EEOF_MASK)
#define TMR_SCTRL_MSTR_MASK (0x20U)
#define TMR_SCTRL_MSTR_SHIFT (5U)
/*! MSTR - Master Mode
*/
#define TMR_SCTRL_MSTR(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_MSTR_SHIFT)) & TMR_SCTRL_MSTR_MASK)
#define TMR_SCTRL_CAPTURE_MODE_MASK (0xC0U)
#define TMR_SCTRL_CAPTURE_MODE_SHIFT (6U)
/*! CAPTURE_MODE - Input Capture Mode
* 0b00..Capture function is disabled
* 0b01..Load capture register on rising edge (when IPS=0) or falling edge (when IPS=1) of input
* 0b10..Load capture register on falling edge (when IPS=0) or rising edge (when IPS=1) of input
* 0b11..Load capture register on both edges of input
*/
#define TMR_SCTRL_CAPTURE_MODE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_CAPTURE_MODE_SHIFT)) & TMR_SCTRL_CAPTURE_MODE_MASK)
#define TMR_SCTRL_INPUT_MASK (0x100U)
#define TMR_SCTRL_INPUT_SHIFT (8U)
/*! INPUT - External Input Signal
*/
#define TMR_SCTRL_INPUT(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_INPUT_SHIFT)) & TMR_SCTRL_INPUT_MASK)
#define TMR_SCTRL_IPS_MASK (0x200U)
#define TMR_SCTRL_IPS_SHIFT (9U)
/*! IPS - Input Polarity Select
*/
#define TMR_SCTRL_IPS(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IPS_SHIFT)) & TMR_SCTRL_IPS_MASK)
#define TMR_SCTRL_IEFIE_MASK (0x400U)
#define TMR_SCTRL_IEFIE_SHIFT (10U)
/*! IEFIE - Input Edge Flag Interrupt Enable
*/
#define TMR_SCTRL_IEFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEFIE_SHIFT)) & TMR_SCTRL_IEFIE_MASK)
#define TMR_SCTRL_IEF_MASK (0x800U)
#define TMR_SCTRL_IEF_SHIFT (11U)
/*! IEF - Input Edge Flag
*/
#define TMR_SCTRL_IEF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_IEF_SHIFT)) & TMR_SCTRL_IEF_MASK)
#define TMR_SCTRL_TOFIE_MASK (0x1000U)
#define TMR_SCTRL_TOFIE_SHIFT (12U)
/*! TOFIE - Timer Overflow Flag Interrupt Enable
*/
#define TMR_SCTRL_TOFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOFIE_SHIFT)) & TMR_SCTRL_TOFIE_MASK)
#define TMR_SCTRL_TOF_MASK (0x2000U)
#define TMR_SCTRL_TOF_SHIFT (13U)
/*! TOF - Timer Overflow Flag
*/
#define TMR_SCTRL_TOF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TOF_SHIFT)) & TMR_SCTRL_TOF_MASK)
#define TMR_SCTRL_TCFIE_MASK (0x4000U)
#define TMR_SCTRL_TCFIE_SHIFT (14U)
/*! TCFIE - Timer Compare Flag Interrupt Enable
*/
#define TMR_SCTRL_TCFIE(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCFIE_SHIFT)) & TMR_SCTRL_TCFIE_MASK)
#define TMR_SCTRL_TCF_MASK (0x8000U)
#define TMR_SCTRL_TCF_SHIFT (15U)
/*! TCF - Timer Compare Flag
*/
#define TMR_SCTRL_TCF(x) (((uint16_t)(((uint16_t)(x)) << TMR_SCTRL_TCF_SHIFT)) & TMR_SCTRL_TCF_MASK)
/*! @} */
/* The count of TMR_SCTRL */
#define TMR_SCTRL_COUNT (4U)
/*! @name CMPLD1 - Timer Channel Comparator Load Register 1 */
/*! @{ */
#define TMR_CMPLD1_COMPARATOR_LOAD_1_MASK (0xFFFFU)
#define TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT (0U)
/*! COMPARATOR_LOAD_1 - COMPARATOR_LOAD_1
*/
#define TMR_CMPLD1_COMPARATOR_LOAD_1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD1_COMPARATOR_LOAD_1_SHIFT)) & TMR_CMPLD1_COMPARATOR_LOAD_1_MASK)
/*! @} */
/* The count of TMR_CMPLD1 */
#define TMR_CMPLD1_COUNT (4U)
/*! @name CMPLD2 - Timer Channel Comparator Load Register 2 */
/*! @{ */
#define TMR_CMPLD2_COMPARATOR_LOAD_2_MASK (0xFFFFU)
#define TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT (0U)
/*! COMPARATOR_LOAD_2 - COMPARATOR_LOAD_2
*/
#define TMR_CMPLD2_COMPARATOR_LOAD_2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CMPLD2_COMPARATOR_LOAD_2_SHIFT)) & TMR_CMPLD2_COMPARATOR_LOAD_2_MASK)
/*! @} */
/* The count of TMR_CMPLD2 */
#define TMR_CMPLD2_COUNT (4U)
/*! @name CSCTRL - Timer Channel Comparator Status and Control Register */
/*! @{ */
#define TMR_CSCTRL_CL1_MASK (0x3U)
#define TMR_CSCTRL_CL1_SHIFT (0U)
/*! CL1 - Compare Load Control 1
* 0b00..Never preload
* 0b01..Load upon successful compare with the value in COMP1
* 0b10..Load upon successful compare with the value in COMP2
* 0b11..Reserved
*/
#define TMR_CSCTRL_CL1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL1_SHIFT)) & TMR_CSCTRL_CL1_MASK)
#define TMR_CSCTRL_CL2_MASK (0xCU)
#define TMR_CSCTRL_CL2_SHIFT (2U)
/*! CL2 - Compare Load Control 2
* 0b00..Never preload
* 0b01..Load upon successful compare with the value in COMP1
* 0b10..Load upon successful compare with the value in COMP2
* 0b11..Reserved
*/
#define TMR_CSCTRL_CL2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_CL2_SHIFT)) & TMR_CSCTRL_CL2_MASK)
#define TMR_CSCTRL_TCF1_MASK (0x10U)
#define TMR_CSCTRL_TCF1_SHIFT (4U)
/*! TCF1 - Timer Compare 1 Interrupt Flag
*/
#define TMR_CSCTRL_TCF1(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1_SHIFT)) & TMR_CSCTRL_TCF1_MASK)
#define TMR_CSCTRL_TCF2_MASK (0x20U)
#define TMR_CSCTRL_TCF2_SHIFT (5U)
/*! TCF2 - Timer Compare 2 Interrupt Flag
*/
#define TMR_CSCTRL_TCF2(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2_SHIFT)) & TMR_CSCTRL_TCF2_MASK)
#define TMR_CSCTRL_TCF1EN_MASK (0x40U)
#define TMR_CSCTRL_TCF1EN_SHIFT (6U)
/*! TCF1EN - Timer Compare 1 Interrupt Enable
*/
#define TMR_CSCTRL_TCF1EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF1EN_SHIFT)) & TMR_CSCTRL_TCF1EN_MASK)
#define TMR_CSCTRL_TCF2EN_MASK (0x80U)
#define TMR_CSCTRL_TCF2EN_SHIFT (7U)
/*! TCF2EN - Timer Compare 2 Interrupt Enable
*/
#define TMR_CSCTRL_TCF2EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCF2EN_SHIFT)) & TMR_CSCTRL_TCF2EN_MASK)
#define TMR_CSCTRL_UP_MASK (0x200U)
#define TMR_CSCTRL_UP_SHIFT (9U)
/*! UP - Counting Direction Indicator
* 0b0..The last count was in the DOWN direction.
* 0b1..The last count was in the UP direction.
*/
#define TMR_CSCTRL_UP(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_UP_SHIFT)) & TMR_CSCTRL_UP_MASK)
#define TMR_CSCTRL_TCI_MASK (0x400U)
#define TMR_CSCTRL_TCI_SHIFT (10U)
/*! TCI - Triggered Count Initialization Control
* 0b0..Stop counter upon receiving a second trigger event while still counting from the first trigger event.
* 0b1..Reload the counter upon receiving a second trigger event while still counting from the first trigger event.
*/
#define TMR_CSCTRL_TCI(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_TCI_SHIFT)) & TMR_CSCTRL_TCI_MASK)
#define TMR_CSCTRL_ROC_MASK (0x800U)
#define TMR_CSCTRL_ROC_SHIFT (11U)
/*! ROC - Reload on Capture
* 0b0..Do not reload the counter on a capture event.
* 0b1..Reload the counter on a capture event.
*/
#define TMR_CSCTRL_ROC(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ROC_SHIFT)) & TMR_CSCTRL_ROC_MASK)
#define TMR_CSCTRL_ALT_LOAD_MASK (0x1000U)
#define TMR_CSCTRL_ALT_LOAD_SHIFT (12U)
/*! ALT_LOAD - Alternative Load Enable
* 0b0..Counter can be re-initialized only with the LOAD register.
* 0b1..Counter can be re-initialized with the LOAD or CMPLD2 registers depending on count direction.
*/
#define TMR_CSCTRL_ALT_LOAD(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_ALT_LOAD_SHIFT)) & TMR_CSCTRL_ALT_LOAD_MASK)
#define TMR_CSCTRL_FAULT_MASK (0x2000U)
#define TMR_CSCTRL_FAULT_SHIFT (13U)
/*! FAULT - Fault Enable
* 0b0..Fault function disabled.
* 0b1..Fault function enabled.
*/
#define TMR_CSCTRL_FAULT(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_FAULT_SHIFT)) & TMR_CSCTRL_FAULT_MASK)
#define TMR_CSCTRL_DBG_EN_MASK (0xC000U)
#define TMR_CSCTRL_DBG_EN_SHIFT (14U)
/*! DBG_EN - Debug Actions Enable
* 0b00..Continue with normal operation during debug mode. (default)
* 0b01..Halt TMR counter during debug mode.
* 0b10..Force TMR output to logic 0 (prior to consideration of SCTRL[OPS]).
* 0b11..Both halt counter and force output to 0 during debug mode.
*/
#define TMR_CSCTRL_DBG_EN(x) (((uint16_t)(((uint16_t)(x)) << TMR_CSCTRL_DBG_EN_SHIFT)) & TMR_CSCTRL_DBG_EN_MASK)
/*! @} */
/* The count of TMR_CSCTRL */
#define TMR_CSCTRL_COUNT (4U)
/*! @name FILT - Timer Channel Input Filter Register */
/*! @{ */
#define TMR_FILT_FILT_PER_MASK (0xFFU)
#define TMR_FILT_FILT_PER_SHIFT (0U)
/*! FILT_PER - Input Filter Sample Period
*/
#define TMR_FILT_FILT_PER(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_PER_SHIFT)) & TMR_FILT_FILT_PER_MASK)
#define TMR_FILT_FILT_CNT_MASK (0x700U)
#define TMR_FILT_FILT_CNT_SHIFT (8U)
/*! FILT_CNT - Input Filter Sample Count
*/
#define TMR_FILT_FILT_CNT(x) (((uint16_t)(((uint16_t)(x)) << TMR_FILT_FILT_CNT_SHIFT)) & TMR_FILT_FILT_CNT_MASK)
/*! @} */
/* The count of TMR_FILT */
#define TMR_FILT_COUNT (4U)
/*! @name DMA - Timer Channel DMA Enable Register */
/*! @{ */
#define TMR_DMA_IEFDE_MASK (0x1U)
#define TMR_DMA_IEFDE_SHIFT (0U)
/*! IEFDE - Input Edge Flag DMA Enable
*/
#define TMR_DMA_IEFDE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_IEFDE_SHIFT)) & TMR_DMA_IEFDE_MASK)
#define TMR_DMA_CMPLD1DE_MASK (0x2U)
#define TMR_DMA_CMPLD1DE_SHIFT (1U)
/*! CMPLD1DE - Comparator Preload Register 1 DMA Enable
*/
#define TMR_DMA_CMPLD1DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD1DE_SHIFT)) & TMR_DMA_CMPLD1DE_MASK)
#define TMR_DMA_CMPLD2DE_MASK (0x4U)
#define TMR_DMA_CMPLD2DE_SHIFT (2U)
/*! CMPLD2DE - Comparator Preload Register 2 DMA Enable
*/
#define TMR_DMA_CMPLD2DE(x) (((uint16_t)(((uint16_t)(x)) << TMR_DMA_CMPLD2DE_SHIFT)) & TMR_DMA_CMPLD2DE_MASK)
/*! @} */
/* The count of TMR_DMA */
#define TMR_DMA_COUNT (4U)
/*! @name ENBL - Timer Channel Enable Register */
/*! @{ */
#define TMR_ENBL_ENBL_MASK (0xFU)
#define TMR_ENBL_ENBL_SHIFT (0U)
/*! ENBL - Timer Channel Enable
* 0b0000..Timer channel is disabled.
* 0b0001..Timer channel is enabled. (default)
*/
#define TMR_ENBL_ENBL(x) (((uint16_t)(((uint16_t)(x)) << TMR_ENBL_ENBL_SHIFT)) & TMR_ENBL_ENBL_MASK)
/*! @} */
/* The count of TMR_ENBL */
#define TMR_ENBL_COUNT (4U)
/*!
* @}
*/ /* end of group TMR_Register_Masks */
/* TMR - Peripheral instance base addresses */
/** Peripheral TMR1 base address */
#define TMR1_BASE (0x4015C000u)
/** Peripheral TMR1 base pointer */
#define TMR1 ((TMR_Type *)TMR1_BASE)
/** Peripheral TMR2 base address */
#define TMR2_BASE (0x40160000u)
/** Peripheral TMR2 base pointer */
#define TMR2 ((TMR_Type *)TMR2_BASE)
/** Peripheral TMR3 base address */
#define TMR3_BASE (0x40164000u)
/** Peripheral TMR3 base pointer */
#define TMR3 ((TMR_Type *)TMR3_BASE)
/** Peripheral TMR4 base address */
#define TMR4_BASE (0x40168000u)
/** Peripheral TMR4 base pointer */
#define TMR4 ((TMR_Type *)TMR4_BASE)
/** Array initializer of TMR peripheral base addresses */
#define TMR_BASE_ADDRS { 0u, TMR1_BASE, TMR2_BASE, TMR3_BASE, TMR4_BASE }
/** Array initializer of TMR peripheral base pointers */
#define TMR_BASE_PTRS { (TMR_Type *)0u, TMR1, TMR2, TMR3, TMR4 }
/** Interrupt vectors for the TMR peripheral type */
#define TMR_IRQS { NotAvail_IRQn, TMR1_IRQn, TMR2_IRQn, TMR3_IRQn, TMR4_IRQn }
/*!
* @}
*/ /* end of group TMR_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
* @{
*/
/** USB - Register Layout Typedef */
typedef struct {
__I uint32_t ID; /**< Identification register, offset: 0x0 */
__I uint32_t HWGENERAL; /**< Hardware General, offset: 0x4 */
__I uint32_t HWHOST; /**< Host Hardware Parameters, offset: 0x8 */
__I uint32_t HWDEVICE; /**< Device Hardware Parameters, offset: 0xC */
__I uint32_t HWTXBUF; /**< TX Buffer Hardware Parameters, offset: 0x10 */
__I uint32_t HWRXBUF; /**< RX Buffer Hardware Parameters, offset: 0x14 */
uint8_t RESERVED_0[104];
__IO uint32_t GPTIMER0LD; /**< General Purpose Timer #0 Load, offset: 0x80 */
__IO uint32_t GPTIMER0CTRL; /**< General Purpose Timer #0 Controller, offset: 0x84 */
__IO uint32_t GPTIMER1LD; /**< General Purpose Timer #1 Load, offset: 0x88 */
__IO uint32_t GPTIMER1CTRL; /**< General Purpose Timer #1 Controller, offset: 0x8C */
__IO uint32_t SBUSCFG; /**< System Bus Config, offset: 0x90 */
uint8_t RESERVED_1[108];
__I uint8_t CAPLENGTH; /**< Capability Registers Length, offset: 0x100 */
uint8_t RESERVED_2[1];
__I uint16_t HCIVERSION; /**< Host Controller Interface Version, offset: 0x102 */
__I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x104 */
__I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x108 */
uint8_t RESERVED_3[20];
__I uint16_t DCIVERSION; /**< Device Controller Interface Version, offset: 0x120 */
uint8_t RESERVED_4[2];
__I uint32_t DCCPARAMS; /**< Device Controller Capability Parameters, offset: 0x124 */
uint8_t RESERVED_5[24];
__IO uint32_t USBCMD; /**< USB Command Register, offset: 0x140 */
__IO uint32_t USBSTS; /**< USB Status Register, offset: 0x144 */
__IO uint32_t USBINTR; /**< Interrupt Enable Register, offset: 0x148 */
__IO uint32_t FRINDEX; /**< USB Frame Index, offset: 0x14C */
uint8_t RESERVED_6[4];
union { /* offset: 0x154 */
__IO uint32_t DEVICEADDR; /**< Device Address, offset: 0x154 */
__IO uint32_t PERIODICLISTBASE; /**< Frame List Base Address, offset: 0x154 */
};
union { /* offset: 0x158 */
__IO uint32_t ASYNCLISTADDR; /**< Next Asynch. Address, offset: 0x158 */
__IO uint32_t ENDPTLISTADDR; /**< Endpoint List Address, offset: 0x158 */
};
uint8_t RESERVED_7[4];
__IO uint32_t BURSTSIZE; /**< Programmable Burst Size, offset: 0x160 */
__IO uint32_t TXFILLTUNING; /**< TX FIFO Fill Tuning, offset: 0x164 */
uint8_t RESERVED_8[16];
__IO uint32_t ENDPTNAK; /**< Endpoint NAK, offset: 0x178 */
__IO uint32_t ENDPTNAKEN; /**< Endpoint NAK Enable, offset: 0x17C */
__I uint32_t CONFIGFLAG; /**< Configure Flag Register, offset: 0x180 */
__IO uint32_t PORTSC1; /**< Port Status & Control, offset: 0x184 */
uint8_t RESERVED_9[28];
__IO uint32_t OTGSC; /**< On-The-Go Status & control, offset: 0x1A4 */
__IO uint32_t USBMODE; /**< USB Device Mode, offset: 0x1A8 */
__IO uint32_t ENDPTSETUPSTAT; /**< Endpoint Setup Status, offset: 0x1AC */
__IO uint32_t ENDPTPRIME; /**< Endpoint Prime, offset: 0x1B0 */
__IO uint32_t ENDPTFLUSH; /**< Endpoint Flush, offset: 0x1B4 */
__I uint32_t ENDPTSTAT; /**< Endpoint Status, offset: 0x1B8 */
__IO uint32_t ENDPTCOMPLETE; /**< Endpoint Complete, offset: 0x1BC */
__IO uint32_t ENDPTCTRL0; /**< Endpoint Control0, offset: 0x1C0 */
__IO uint32_t ENDPTCTRL[7]; /**< Endpoint Control 1..Endpoint Control 7, array offset: 0x1C4, array step: 0x4 */
} USB_Type;
/* ----------------------------------------------------------------------------
-- USB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USB_Register_Masks USB Register Masks
* @{
*/
/*! @name ID - Identification register */
/*! @{ */
#define USB_ID_ID_MASK (0x3FU)
#define USB_ID_ID_SHIFT (0U)
/*! ID - ID
*/
#define USB_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_ID_SHIFT)) & USB_ID_ID_MASK)
#define USB_ID_NID_MASK (0x3F00U)
#define USB_ID_NID_SHIFT (8U)
/*! NID - NID
*/
#define USB_ID_NID(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_NID_SHIFT)) & USB_ID_NID_MASK)
#define USB_ID_REVISION_MASK (0xFF0000U)
#define USB_ID_REVISION_SHIFT (16U)
/*! REVISION - REVISION
*/
#define USB_ID_REVISION(x) (((uint32_t)(((uint32_t)(x)) << USB_ID_REVISION_SHIFT)) & USB_ID_REVISION_MASK)
/*! @} */
/*! @name HWGENERAL - Hardware General */
/*! @{ */
#define USB_HWGENERAL_PHYW_MASK (0x30U)
#define USB_HWGENERAL_PHYW_SHIFT (4U)
/*! PHYW - PHYW
* 0b00..8 bit wide data bus (Software non-programmable)
* 0b01..16 bit wide data bus (Software non-programmable)
* 0b10..Reset to 8 bit wide data bus (Software programmable)
* 0b11..Reset to 16 bit wide data bus (Software programmable)
*/
#define USB_HWGENERAL_PHYW(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYW_SHIFT)) & USB_HWGENERAL_PHYW_MASK)
#define USB_HWGENERAL_PHYM_MASK (0x1C0U)
#define USB_HWGENERAL_PHYM_SHIFT (6U)
/*! PHYM - PHYM
* 0b000..UTMI/UMTI+
* 0b001..ULPI DDR
* 0b010..ULPI
* 0b011..Serial Only
* 0b100..Software programmable - reset to UTMI/UTMI+
* 0b101..Software programmable - reset to ULPI DDR
* 0b110..Software programmable - reset to ULPI
* 0b111..Software programmable - reset to Serial
*/
#define USB_HWGENERAL_PHYM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_PHYM_SHIFT)) & USB_HWGENERAL_PHYM_MASK)
#define USB_HWGENERAL_SM_MASK (0x600U)
#define USB_HWGENERAL_SM_SHIFT (9U)
/*! SM - SM
* 0b00..No Serial Engine, always use parallel signalling.
* 0b01..Serial Engine present, always use serial signalling for FS/LS.
* 0b10..Software programmable - Reset to use parallel signalling for FS/LS
* 0b11..Software programmable - Reset to use serial signalling for FS/LS
*/
#define USB_HWGENERAL_SM(x) (((uint32_t)(((uint32_t)(x)) << USB_HWGENERAL_SM_SHIFT)) & USB_HWGENERAL_SM_MASK)
/*! @} */
/*! @name HWHOST - Host Hardware Parameters */
/*! @{ */
#define USB_HWHOST_HC_MASK (0x1U)
#define USB_HWHOST_HC_SHIFT (0U)
/*! HC - HC
* 0b1..Supported
* 0b0..Not supported
*/
#define USB_HWHOST_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_HC_SHIFT)) & USB_HWHOST_HC_MASK)
#define USB_HWHOST_NPORT_MASK (0xEU)
#define USB_HWHOST_NPORT_SHIFT (1U)
/*! NPORT - NPORT
*/
#define USB_HWHOST_NPORT(x) (((uint32_t)(((uint32_t)(x)) << USB_HWHOST_NPORT_SHIFT)) & USB_HWHOST_NPORT_MASK)
/*! @} */
/*! @name HWDEVICE - Device Hardware Parameters */
/*! @{ */
#define USB_HWDEVICE_DC_MASK (0x1U)
#define USB_HWDEVICE_DC_SHIFT (0U)
/*! DC - DC
* 0b1..Supported
* 0b0..Not supported
*/
#define USB_HWDEVICE_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DC_SHIFT)) & USB_HWDEVICE_DC_MASK)
#define USB_HWDEVICE_DEVEP_MASK (0x3EU)
#define USB_HWDEVICE_DEVEP_SHIFT (1U)
/*! DEVEP - DEVEP
*/
#define USB_HWDEVICE_DEVEP(x) (((uint32_t)(((uint32_t)(x)) << USB_HWDEVICE_DEVEP_SHIFT)) & USB_HWDEVICE_DEVEP_MASK)
/*! @} */
/*! @name HWTXBUF - TX Buffer Hardware Parameters */
/*! @{ */
#define USB_HWTXBUF_TXBURST_MASK (0xFFU)
#define USB_HWTXBUF_TXBURST_SHIFT (0U)
/*! TXBURST - TXBURST
*/
#define USB_HWTXBUF_TXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXBURST_SHIFT)) & USB_HWTXBUF_TXBURST_MASK)
#define USB_HWTXBUF_TXCHANADD_MASK (0xFF0000U)
#define USB_HWTXBUF_TXCHANADD_SHIFT (16U)
/*! TXCHANADD - TXCHANADD
*/
#define USB_HWTXBUF_TXCHANADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWTXBUF_TXCHANADD_SHIFT)) & USB_HWTXBUF_TXCHANADD_MASK)
/*! @} */
/*! @name HWRXBUF - RX Buffer Hardware Parameters */
/*! @{ */
#define USB_HWRXBUF_RXBURST_MASK (0xFFU)
#define USB_HWRXBUF_RXBURST_SHIFT (0U)
/*! RXBURST - RXBURST
*/
#define USB_HWRXBUF_RXBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXBURST_SHIFT)) & USB_HWRXBUF_RXBURST_MASK)
#define USB_HWRXBUF_RXADD_MASK (0xFF00U)
#define USB_HWRXBUF_RXADD_SHIFT (8U)
/*! RXADD - RXADD
*/
#define USB_HWRXBUF_RXADD(x) (((uint32_t)(((uint32_t)(x)) << USB_HWRXBUF_RXADD_SHIFT)) & USB_HWRXBUF_RXADD_MASK)
/*! @} */
/*! @name GPTIMER0LD - General Purpose Timer #0 Load */
/*! @{ */
#define USB_GPTIMER0LD_GPTLD_MASK (0xFFFFFFU)
#define USB_GPTIMER0LD_GPTLD_SHIFT (0U)
/*! GPTLD - GPTLD
*/
#define USB_GPTIMER0LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0LD_GPTLD_SHIFT)) & USB_GPTIMER0LD_GPTLD_MASK)
/*! @} */
/*! @name GPTIMER0CTRL - General Purpose Timer #0 Controller */
/*! @{ */
#define USB_GPTIMER0CTRL_GPTCNT_MASK (0xFFFFFFU)
#define USB_GPTIMER0CTRL_GPTCNT_SHIFT (0U)
/*! GPTCNT - GPTCNT
*/
#define USB_GPTIMER0CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTCNT_SHIFT)) & USB_GPTIMER0CTRL_GPTCNT_MASK)
#define USB_GPTIMER0CTRL_GPTMODE_MASK (0x1000000U)
#define USB_GPTIMER0CTRL_GPTMODE_SHIFT (24U)
/*! GPTMODE - GPTMODE
* 0b0..One Shot Mode
* 0b1..Repeat Mode
*/
#define USB_GPTIMER0CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTMODE_SHIFT)) & USB_GPTIMER0CTRL_GPTMODE_MASK)
#define USB_GPTIMER0CTRL_GPTRST_MASK (0x40000000U)
#define USB_GPTIMER0CTRL_GPTRST_SHIFT (30U)
/*! GPTRST - GPTRST
* 0b0..No action
* 0b1..Load counter value from GPTLD bits in n_GPTIMER0LD
*/
#define USB_GPTIMER0CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRST_SHIFT)) & USB_GPTIMER0CTRL_GPTRST_MASK)
#define USB_GPTIMER0CTRL_GPTRUN_MASK (0x80000000U)
#define USB_GPTIMER0CTRL_GPTRUN_SHIFT (31U)
/*! GPTRUN - GPTRUN
* 0b0..Stop counting
* 0b1..Run
*/
#define USB_GPTIMER0CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER0CTRL_GPTRUN_SHIFT)) & USB_GPTIMER0CTRL_GPTRUN_MASK)
/*! @} */
/*! @name GPTIMER1LD - General Purpose Timer #1 Load */
/*! @{ */
#define USB_GPTIMER1LD_GPTLD_MASK (0xFFFFFFU)
#define USB_GPTIMER1LD_GPTLD_SHIFT (0U)
/*! GPTLD - GPTLD
*/
#define USB_GPTIMER1LD_GPTLD(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1LD_GPTLD_SHIFT)) & USB_GPTIMER1LD_GPTLD_MASK)
/*! @} */
/*! @name GPTIMER1CTRL - General Purpose Timer #1 Controller */
/*! @{ */
#define USB_GPTIMER1CTRL_GPTCNT_MASK (0xFFFFFFU)
#define USB_GPTIMER1CTRL_GPTCNT_SHIFT (0U)
/*! GPTCNT - GPTCNT
*/
#define USB_GPTIMER1CTRL_GPTCNT(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTCNT_SHIFT)) & USB_GPTIMER1CTRL_GPTCNT_MASK)
#define USB_GPTIMER1CTRL_GPTMODE_MASK (0x1000000U)
#define USB_GPTIMER1CTRL_GPTMODE_SHIFT (24U)
/*! GPTMODE - GPTMODE
* 0b0..One Shot Mode
* 0b1..Repeat Mode
*/
#define USB_GPTIMER1CTRL_GPTMODE(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTMODE_SHIFT)) & USB_GPTIMER1CTRL_GPTMODE_MASK)
#define USB_GPTIMER1CTRL_GPTRST_MASK (0x40000000U)
#define USB_GPTIMER1CTRL_GPTRST_SHIFT (30U)
/*! GPTRST - GPTRST
* 0b0..No action
* 0b1..Load counter value from GPTLD bits in USB_n_GPTIMER0LD
*/
#define USB_GPTIMER1CTRL_GPTRST(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRST_SHIFT)) & USB_GPTIMER1CTRL_GPTRST_MASK)
#define USB_GPTIMER1CTRL_GPTRUN_MASK (0x80000000U)
#define USB_GPTIMER1CTRL_GPTRUN_SHIFT (31U)
/*! GPTRUN - GPTRUN
* 0b0..Stop counting
* 0b1..Run
*/
#define USB_GPTIMER1CTRL_GPTRUN(x) (((uint32_t)(((uint32_t)(x)) << USB_GPTIMER1CTRL_GPTRUN_SHIFT)) & USB_GPTIMER1CTRL_GPTRUN_MASK)
/*! @} */
/*! @name SBUSCFG - System Bus Config */
/*! @{ */
#define USB_SBUSCFG_AHBBRST_MASK (0x7U)
#define USB_SBUSCFG_AHBBRST_SHIFT (0U)
/*! AHBBRST - AHBBRST
* 0b000..Incremental burst of unspecified length only
* 0b001..INCR4 burst, then single transfer
* 0b010..INCR8 burst, INCR4 burst, then single transfer
* 0b011..INCR16 burst, INCR8 burst, INCR4 burst, then single transfer
* 0b100..Reserved, don't use
* 0b101..INCR4 burst, then incremental burst of unspecified length
* 0b110..INCR8 burst, INCR4 burst, then incremental burst of unspecified length
* 0b111..INCR16 burst, INCR8 burst, INCR4 burst, then incremental burst of unspecified length
*/
#define USB_SBUSCFG_AHBBRST(x) (((uint32_t)(((uint32_t)(x)) << USB_SBUSCFG_AHBBRST_SHIFT)) & USB_SBUSCFG_AHBBRST_MASK)
/*! @} */
/*! @name CAPLENGTH - Capability Registers Length */
/*! @{ */
#define USB_CAPLENGTH_CAPLENGTH_MASK (0xFFU)
#define USB_CAPLENGTH_CAPLENGTH_SHIFT (0U)
/*! CAPLENGTH - CAPLENGTH
*/
#define USB_CAPLENGTH_CAPLENGTH(x) (((uint8_t)(((uint8_t)(x)) << USB_CAPLENGTH_CAPLENGTH_SHIFT)) & USB_CAPLENGTH_CAPLENGTH_MASK)
/*! @} */
/*! @name HCIVERSION - Host Controller Interface Version */
/*! @{ */
#define USB_HCIVERSION_HCIVERSION_MASK (0xFFFFU)
#define USB_HCIVERSION_HCIVERSION_SHIFT (0U)
/*! HCIVERSION - HCIVERSION
*/
#define USB_HCIVERSION_HCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_HCIVERSION_HCIVERSION_SHIFT)) & USB_HCIVERSION_HCIVERSION_MASK)
/*! @} */
/*! @name HCSPARAMS - Host Controller Structural Parameters */
/*! @{ */
#define USB_HCSPARAMS_N_PORTS_MASK (0xFU)
#define USB_HCSPARAMS_N_PORTS_SHIFT (0U)
/*! N_PORTS - N_PORTS
*/
#define USB_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PORTS_SHIFT)) & USB_HCSPARAMS_N_PORTS_MASK)
#define USB_HCSPARAMS_PPC_MASK (0x10U)
#define USB_HCSPARAMS_PPC_SHIFT (4U)
/*! PPC - PPC
*/
#define USB_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PPC_SHIFT)) & USB_HCSPARAMS_PPC_MASK)
#define USB_HCSPARAMS_N_PCC_MASK (0xF00U)
#define USB_HCSPARAMS_N_PCC_SHIFT (8U)
/*! N_PCC - N_PCC
*/
#define USB_HCSPARAMS_N_PCC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PCC_SHIFT)) & USB_HCSPARAMS_N_PCC_MASK)
#define USB_HCSPARAMS_N_CC_MASK (0xF000U)
#define USB_HCSPARAMS_N_CC_SHIFT (12U)
/*! N_CC - N_CC
* 0b0000..There is no internal Companion Controller and port-ownership hand-off is not supported.
* 0b0001..There are internal companion controller(s) and port-ownership hand-offs is supported.
*/
#define USB_HCSPARAMS_N_CC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_CC_SHIFT)) & USB_HCSPARAMS_N_CC_MASK)
#define USB_HCSPARAMS_PI_MASK (0x10000U)
#define USB_HCSPARAMS_PI_SHIFT (16U)
/*! PI - PI
*/
#define USB_HCSPARAMS_PI(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_PI_SHIFT)) & USB_HCSPARAMS_PI_MASK)
#define USB_HCSPARAMS_N_PTT_MASK (0xF00000U)
#define USB_HCSPARAMS_N_PTT_SHIFT (20U)
/*! N_PTT - N_PTT
*/
#define USB_HCSPARAMS_N_PTT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_PTT_SHIFT)) & USB_HCSPARAMS_N_PTT_MASK)
#define USB_HCSPARAMS_N_TT_MASK (0xF000000U)
#define USB_HCSPARAMS_N_TT_SHIFT (24U)
/*! N_TT - N_TT
*/
#define USB_HCSPARAMS_N_TT(x) (((uint32_t)(((uint32_t)(x)) << USB_HCSPARAMS_N_TT_SHIFT)) & USB_HCSPARAMS_N_TT_MASK)
/*! @} */
/*! @name HCCPARAMS - Host Controller Capability Parameters */
/*! @{ */
#define USB_HCCPARAMS_ADC_MASK (0x1U)
#define USB_HCCPARAMS_ADC_SHIFT (0U)
/*! ADC - ADC
*/
#define USB_HCCPARAMS_ADC(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ADC_SHIFT)) & USB_HCCPARAMS_ADC_MASK)
#define USB_HCCPARAMS_PFL_MASK (0x2U)
#define USB_HCCPARAMS_PFL_SHIFT (1U)
/*! PFL - PFL
*/
#define USB_HCCPARAMS_PFL(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_PFL_SHIFT)) & USB_HCCPARAMS_PFL_MASK)
#define USB_HCCPARAMS_ASP_MASK (0x4U)
#define USB_HCCPARAMS_ASP_SHIFT (2U)
/*! ASP - ASP
*/
#define USB_HCCPARAMS_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_ASP_SHIFT)) & USB_HCCPARAMS_ASP_MASK)
#define USB_HCCPARAMS_IST_MASK (0xF0U)
#define USB_HCCPARAMS_IST_SHIFT (4U)
/*! IST - IST
*/
#define USB_HCCPARAMS_IST(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_IST_SHIFT)) & USB_HCCPARAMS_IST_MASK)
#define USB_HCCPARAMS_EECP_MASK (0xFF00U)
#define USB_HCCPARAMS_EECP_SHIFT (8U)
/*! EECP - EECP
*/
#define USB_HCCPARAMS_EECP(x) (((uint32_t)(((uint32_t)(x)) << USB_HCCPARAMS_EECP_SHIFT)) & USB_HCCPARAMS_EECP_MASK)
/*! @} */
/*! @name DCIVERSION - Device Controller Interface Version */
/*! @{ */
#define USB_DCIVERSION_DCIVERSION_MASK (0xFFFFU)
#define USB_DCIVERSION_DCIVERSION_SHIFT (0U)
/*! DCIVERSION - DCIVERSION
*/
#define USB_DCIVERSION_DCIVERSION(x) (((uint16_t)(((uint16_t)(x)) << USB_DCIVERSION_DCIVERSION_SHIFT)) & USB_DCIVERSION_DCIVERSION_MASK)
/*! @} */
/*! @name DCCPARAMS - Device Controller Capability Parameters */
/*! @{ */
#define USB_DCCPARAMS_DEN_MASK (0x1FU)
#define USB_DCCPARAMS_DEN_SHIFT (0U)
/*! DEN - DEN
*/
#define USB_DCCPARAMS_DEN(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DEN_SHIFT)) & USB_DCCPARAMS_DEN_MASK)
#define USB_DCCPARAMS_DC_MASK (0x80U)
#define USB_DCCPARAMS_DC_SHIFT (7U)
/*! DC - DC
*/
#define USB_DCCPARAMS_DC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_DC_SHIFT)) & USB_DCCPARAMS_DC_MASK)
#define USB_DCCPARAMS_HC_MASK (0x100U)
#define USB_DCCPARAMS_HC_SHIFT (8U)
/*! HC - HC
*/
#define USB_DCCPARAMS_HC(x) (((uint32_t)(((uint32_t)(x)) << USB_DCCPARAMS_HC_SHIFT)) & USB_DCCPARAMS_HC_MASK)
/*! @} */
/*! @name USBCMD - USB Command Register */
/*! @{ */
#define USB_USBCMD_RS_MASK (0x1U)
#define USB_USBCMD_RS_SHIFT (0U)
/*! RS - RS
*/
#define USB_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RS_SHIFT)) & USB_USBCMD_RS_MASK)
#define USB_USBCMD_RST_MASK (0x2U)
#define USB_USBCMD_RST_SHIFT (1U)
/*! RST - RST
*/
#define USB_USBCMD_RST(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_RST_SHIFT)) & USB_USBCMD_RST_MASK)
#define USB_USBCMD_FS_1_MASK (0xCU)
#define USB_USBCMD_FS_1_SHIFT (2U)
/*! FS_1 - FS_1
*/
#define USB_USBCMD_FS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_1_SHIFT)) & USB_USBCMD_FS_1_MASK)
#define USB_USBCMD_PSE_MASK (0x10U)
#define USB_USBCMD_PSE_SHIFT (4U)
/*! PSE - PSE
* 0b0..Do not process the Periodic Schedule
* 0b1..Use the PERIODICLISTBASE register to access the Periodic Schedule.
*/
#define USB_USBCMD_PSE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_PSE_SHIFT)) & USB_USBCMD_PSE_MASK)
#define USB_USBCMD_ASE_MASK (0x20U)
#define USB_USBCMD_ASE_SHIFT (5U)
/*! ASE - ASE
* 0b0..Do not process the Asynchronous Schedule.
* 0b1..Use the ASYNCLISTADDR register to access the Asynchronous Schedule.
*/
#define USB_USBCMD_ASE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASE_SHIFT)) & USB_USBCMD_ASE_MASK)
#define USB_USBCMD_IAA_MASK (0x40U)
#define USB_USBCMD_IAA_SHIFT (6U)
/*! IAA - IAA
*/
#define USB_USBCMD_IAA(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_IAA_SHIFT)) & USB_USBCMD_IAA_MASK)
#define USB_USBCMD_ASP_MASK (0x300U)
#define USB_USBCMD_ASP_SHIFT (8U)
/*! ASP - ASP
*/
#define USB_USBCMD_ASP(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASP_SHIFT)) & USB_USBCMD_ASP_MASK)
#define USB_USBCMD_ASPE_MASK (0x800U)
#define USB_USBCMD_ASPE_SHIFT (11U)
/*! ASPE - ASPE
*/
#define USB_USBCMD_ASPE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ASPE_SHIFT)) & USB_USBCMD_ASPE_MASK)
#define USB_USBCMD_SUTW_MASK (0x2000U)
#define USB_USBCMD_SUTW_SHIFT (13U)
/*! SUTW - SUTW
*/
#define USB_USBCMD_SUTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_SUTW_SHIFT)) & USB_USBCMD_SUTW_MASK)
#define USB_USBCMD_ATDTW_MASK (0x4000U)
#define USB_USBCMD_ATDTW_SHIFT (14U)
/*! ATDTW - ATDTW
*/
#define USB_USBCMD_ATDTW(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ATDTW_SHIFT)) & USB_USBCMD_ATDTW_MASK)
#define USB_USBCMD_FS_2_MASK (0x8000U)
#define USB_USBCMD_FS_2_SHIFT (15U)
/*! FS_2 - FS_2
*/
#define USB_USBCMD_FS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_FS_2_SHIFT)) & USB_USBCMD_FS_2_MASK)
#define USB_USBCMD_ITC_MASK (0xFF0000U)
#define USB_USBCMD_ITC_SHIFT (16U)
/*! ITC - ITC
* 0b00000000..Immediate (no threshold)
* 0b00000001..1 micro-frame
* 0b00000010..2 micro-frames
* 0b00000100..4 micro-frames
* 0b00001000..8 micro-frames
* 0b00010000..16 micro-frames
* 0b00100000..32 micro-frames
* 0b01000000..64 micro-frames
*/
#define USB_USBCMD_ITC(x) (((uint32_t)(((uint32_t)(x)) << USB_USBCMD_ITC_SHIFT)) & USB_USBCMD_ITC_MASK)
/*! @} */
/*! @name USBSTS - USB Status Register */
/*! @{ */
#define USB_USBSTS_UI_MASK (0x1U)
#define USB_USBSTS_UI_SHIFT (0U)
/*! UI - UI
*/
#define USB_USBSTS_UI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UI_SHIFT)) & USB_USBSTS_UI_MASK)
#define USB_USBSTS_UEI_MASK (0x2U)
#define USB_USBSTS_UEI_SHIFT (1U)
/*! UEI - UEI
*/
#define USB_USBSTS_UEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_UEI_SHIFT)) & USB_USBSTS_UEI_MASK)
#define USB_USBSTS_PCI_MASK (0x4U)
#define USB_USBSTS_PCI_SHIFT (2U)
/*! PCI - PCI
*/
#define USB_USBSTS_PCI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PCI_SHIFT)) & USB_USBSTS_PCI_MASK)
#define USB_USBSTS_FRI_MASK (0x8U)
#define USB_USBSTS_FRI_SHIFT (3U)
/*! FRI - FRI
*/
#define USB_USBSTS_FRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_FRI_SHIFT)) & USB_USBSTS_FRI_MASK)
#define USB_USBSTS_SEI_MASK (0x10U)
#define USB_USBSTS_SEI_SHIFT (4U)
/*! SEI - SEI
*/
#define USB_USBSTS_SEI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SEI_SHIFT)) & USB_USBSTS_SEI_MASK)
#define USB_USBSTS_AAI_MASK (0x20U)
#define USB_USBSTS_AAI_SHIFT (5U)
/*! AAI - AAI
*/
#define USB_USBSTS_AAI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AAI_SHIFT)) & USB_USBSTS_AAI_MASK)
#define USB_USBSTS_URI_MASK (0x40U)
#define USB_USBSTS_URI_SHIFT (6U)
/*! URI - URI
*/
#define USB_USBSTS_URI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_URI_SHIFT)) & USB_USBSTS_URI_MASK)
#define USB_USBSTS_SRI_MASK (0x80U)
#define USB_USBSTS_SRI_SHIFT (7U)
/*! SRI - SRI
*/
#define USB_USBSTS_SRI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SRI_SHIFT)) & USB_USBSTS_SRI_MASK)
#define USB_USBSTS_SLI_MASK (0x100U)
#define USB_USBSTS_SLI_SHIFT (8U)
/*! SLI - SLI
*/
#define USB_USBSTS_SLI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_SLI_SHIFT)) & USB_USBSTS_SLI_MASK)
#define USB_USBSTS_ULPII_MASK (0x400U)
#define USB_USBSTS_ULPII_SHIFT (10U)
/*! ULPII - ULPII
*/
#define USB_USBSTS_ULPII(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_ULPII_SHIFT)) & USB_USBSTS_ULPII_MASK)
#define USB_USBSTS_HCH_MASK (0x1000U)
#define USB_USBSTS_HCH_SHIFT (12U)
/*! HCH - HCH
*/
#define USB_USBSTS_HCH(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_HCH_SHIFT)) & USB_USBSTS_HCH_MASK)
#define USB_USBSTS_RCL_MASK (0x2000U)
#define USB_USBSTS_RCL_SHIFT (13U)
/*! RCL - RCL
*/
#define USB_USBSTS_RCL(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_RCL_SHIFT)) & USB_USBSTS_RCL_MASK)
#define USB_USBSTS_PS_MASK (0x4000U)
#define USB_USBSTS_PS_SHIFT (14U)
/*! PS - PS
*/
#define USB_USBSTS_PS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_PS_SHIFT)) & USB_USBSTS_PS_MASK)
#define USB_USBSTS_AS_MASK (0x8000U)
#define USB_USBSTS_AS_SHIFT (15U)
/*! AS - AS
*/
#define USB_USBSTS_AS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_AS_SHIFT)) & USB_USBSTS_AS_MASK)
#define USB_USBSTS_NAKI_MASK (0x10000U)
#define USB_USBSTS_NAKI_SHIFT (16U)
/*! NAKI - NAKI
*/
#define USB_USBSTS_NAKI(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_NAKI_SHIFT)) & USB_USBSTS_NAKI_MASK)
#define USB_USBSTS_TI0_MASK (0x1000000U)
#define USB_USBSTS_TI0_SHIFT (24U)
/*! TI0 - TI0
*/
#define USB_USBSTS_TI0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI0_SHIFT)) & USB_USBSTS_TI0_MASK)
#define USB_USBSTS_TI1_MASK (0x2000000U)
#define USB_USBSTS_TI1_SHIFT (25U)
/*! TI1 - TI1
*/
#define USB_USBSTS_TI1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBSTS_TI1_SHIFT)) & USB_USBSTS_TI1_MASK)
/*! @} */
/*! @name USBINTR - Interrupt Enable Register */
/*! @{ */
#define USB_USBINTR_UE_MASK (0x1U)
#define USB_USBINTR_UE_SHIFT (0U)
/*! UE - UE
*/
#define USB_USBINTR_UE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UE_SHIFT)) & USB_USBINTR_UE_MASK)
#define USB_USBINTR_UEE_MASK (0x2U)
#define USB_USBINTR_UEE_SHIFT (1U)
/*! UEE - UEE
*/
#define USB_USBINTR_UEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UEE_SHIFT)) & USB_USBINTR_UEE_MASK)
#define USB_USBINTR_PCE_MASK (0x4U)
#define USB_USBINTR_PCE_SHIFT (2U)
/*! PCE - PCE
*/
#define USB_USBINTR_PCE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_PCE_SHIFT)) & USB_USBINTR_PCE_MASK)
#define USB_USBINTR_FRE_MASK (0x8U)
#define USB_USBINTR_FRE_SHIFT (3U)
/*! FRE - FRE
*/
#define USB_USBINTR_FRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_FRE_SHIFT)) & USB_USBINTR_FRE_MASK)
#define USB_USBINTR_SEE_MASK (0x10U)
#define USB_USBINTR_SEE_SHIFT (4U)
/*! SEE - SEE
*/
#define USB_USBINTR_SEE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SEE_SHIFT)) & USB_USBINTR_SEE_MASK)
#define USB_USBINTR_AAE_MASK (0x20U)
#define USB_USBINTR_AAE_SHIFT (5U)
/*! AAE - AAE
*/
#define USB_USBINTR_AAE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_AAE_SHIFT)) & USB_USBINTR_AAE_MASK)
#define USB_USBINTR_URE_MASK (0x40U)
#define USB_USBINTR_URE_SHIFT (6U)
/*! URE - URE
*/
#define USB_USBINTR_URE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_URE_SHIFT)) & USB_USBINTR_URE_MASK)
#define USB_USBINTR_SRE_MASK (0x80U)
#define USB_USBINTR_SRE_SHIFT (7U)
/*! SRE - SRE
*/
#define USB_USBINTR_SRE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SRE_SHIFT)) & USB_USBINTR_SRE_MASK)
#define USB_USBINTR_SLE_MASK (0x100U)
#define USB_USBINTR_SLE_SHIFT (8U)
/*! SLE - SLE
*/
#define USB_USBINTR_SLE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_SLE_SHIFT)) & USB_USBINTR_SLE_MASK)
#define USB_USBINTR_ULPIE_MASK (0x400U)
#define USB_USBINTR_ULPIE_SHIFT (10U)
/*! ULPIE - ULPIE
*/
#define USB_USBINTR_ULPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_ULPIE_SHIFT)) & USB_USBINTR_ULPIE_MASK)
#define USB_USBINTR_NAKE_MASK (0x10000U)
#define USB_USBINTR_NAKE_SHIFT (16U)
/*! NAKE - NAKE
*/
#define USB_USBINTR_NAKE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_NAKE_SHIFT)) & USB_USBINTR_NAKE_MASK)
#define USB_USBINTR_UAIE_MASK (0x40000U)
#define USB_USBINTR_UAIE_SHIFT (18U)
/*! UAIE - UAIE
*/
#define USB_USBINTR_UAIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UAIE_SHIFT)) & USB_USBINTR_UAIE_MASK)
#define USB_USBINTR_UPIE_MASK (0x80000U)
#define USB_USBINTR_UPIE_SHIFT (19U)
/*! UPIE - UPIE
*/
#define USB_USBINTR_UPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_UPIE_SHIFT)) & USB_USBINTR_UPIE_MASK)
#define USB_USBINTR_TIE0_MASK (0x1000000U)
#define USB_USBINTR_TIE0_SHIFT (24U)
/*! TIE0 - TIE0
*/
#define USB_USBINTR_TIE0(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE0_SHIFT)) & USB_USBINTR_TIE0_MASK)
#define USB_USBINTR_TIE1_MASK (0x2000000U)
#define USB_USBINTR_TIE1_SHIFT (25U)
/*! TIE1 - TIE1
*/
#define USB_USBINTR_TIE1(x) (((uint32_t)(((uint32_t)(x)) << USB_USBINTR_TIE1_SHIFT)) & USB_USBINTR_TIE1_MASK)
/*! @} */
/*! @name FRINDEX - USB Frame Index */
/*! @{ */
#define USB_FRINDEX_FRINDEX_MASK (0x3FFFU)
#define USB_FRINDEX_FRINDEX_SHIFT (0U)
/*! FRINDEX - FRINDEX
* 0b00000000000000..(1024) 12
* 0b00000000000001..(512) 11
* 0b00000000000010..(256) 10
* 0b00000000000011..(128) 9
* 0b00000000000100..(64) 8
* 0b00000000000101..(32) 7
* 0b00000000000110..(16) 6
* 0b00000000000111..(8) 5
*/
#define USB_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USB_FRINDEX_FRINDEX_SHIFT)) & USB_FRINDEX_FRINDEX_MASK)
/*! @} */
/*! @name DEVICEADDR - Device Address */
/*! @{ */
#define USB_DEVICEADDR_USBADRA_MASK (0x1000000U)
#define USB_DEVICEADDR_USBADRA_SHIFT (24U)
/*! USBADRA - USBADRA
*/
#define USB_DEVICEADDR_USBADRA(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADRA_SHIFT)) & USB_DEVICEADDR_USBADRA_MASK)
#define USB_DEVICEADDR_USBADR_MASK (0xFE000000U)
#define USB_DEVICEADDR_USBADR_SHIFT (25U)
/*! USBADR - USBADR
*/
#define USB_DEVICEADDR_USBADR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVICEADDR_USBADR_SHIFT)) & USB_DEVICEADDR_USBADR_MASK)
/*! @} */
/*! @name PERIODICLISTBASE - Frame List Base Address */
/*! @{ */
#define USB_PERIODICLISTBASE_BASEADR_MASK (0xFFFFF000U)
#define USB_PERIODICLISTBASE_BASEADR_SHIFT (12U)
/*! BASEADR - BASEADR
*/
#define USB_PERIODICLISTBASE_BASEADR(x) (((uint32_t)(((uint32_t)(x)) << USB_PERIODICLISTBASE_BASEADR_SHIFT)) & USB_PERIODICLISTBASE_BASEADR_MASK)
/*! @} */
/*! @name ASYNCLISTADDR - Next Asynch. Address */
/*! @{ */
#define USB_ASYNCLISTADDR_ASYBASE_MASK (0xFFFFFFE0U)
#define USB_ASYNCLISTADDR_ASYBASE_SHIFT (5U)
/*! ASYBASE - ASYBASE
*/
#define USB_ASYNCLISTADDR_ASYBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ASYNCLISTADDR_ASYBASE_SHIFT)) & USB_ASYNCLISTADDR_ASYBASE_MASK)
/*! @} */
/*! @name ENDPTLISTADDR - Endpoint List Address */
/*! @{ */
#define USB_ENDPTLISTADDR_EPBASE_MASK (0xFFFFF800U)
#define USB_ENDPTLISTADDR_EPBASE_SHIFT (11U)
/*! EPBASE - EPBASE
*/
#define USB_ENDPTLISTADDR_EPBASE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTLISTADDR_EPBASE_SHIFT)) & USB_ENDPTLISTADDR_EPBASE_MASK)
/*! @} */
/*! @name BURSTSIZE - Programmable Burst Size */
/*! @{ */
#define USB_BURSTSIZE_RXPBURST_MASK (0xFFU)
#define USB_BURSTSIZE_RXPBURST_SHIFT (0U)
/*! RXPBURST - RXPBURST
*/
#define USB_BURSTSIZE_RXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_RXPBURST_SHIFT)) & USB_BURSTSIZE_RXPBURST_MASK)
#define USB_BURSTSIZE_TXPBURST_MASK (0x1FF00U)
#define USB_BURSTSIZE_TXPBURST_SHIFT (8U)
/*! TXPBURST - TXPBURST
*/
#define USB_BURSTSIZE_TXPBURST(x) (((uint32_t)(((uint32_t)(x)) << USB_BURSTSIZE_TXPBURST_SHIFT)) & USB_BURSTSIZE_TXPBURST_MASK)
/*! @} */
/*! @name TXFILLTUNING - TX FIFO Fill Tuning */
/*! @{ */
#define USB_TXFILLTUNING_TXSCHOH_MASK (0xFFU)
#define USB_TXFILLTUNING_TXSCHOH_SHIFT (0U)
/*! TXSCHOH - TXSCHOH
*/
#define USB_TXFILLTUNING_TXSCHOH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHOH_SHIFT)) & USB_TXFILLTUNING_TXSCHOH_MASK)
#define USB_TXFILLTUNING_TXSCHHEALTH_MASK (0x1F00U)
#define USB_TXFILLTUNING_TXSCHHEALTH_SHIFT (8U)
/*! TXSCHHEALTH - TXSCHHEALTH
*/
#define USB_TXFILLTUNING_TXSCHHEALTH(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXSCHHEALTH_SHIFT)) & USB_TXFILLTUNING_TXSCHHEALTH_MASK)
#define USB_TXFILLTUNING_TXFIFOTHRES_MASK (0x3F0000U)
#define USB_TXFILLTUNING_TXFIFOTHRES_SHIFT (16U)
/*! TXFIFOTHRES - TXFIFOTHRES
*/
#define USB_TXFILLTUNING_TXFIFOTHRES(x) (((uint32_t)(((uint32_t)(x)) << USB_TXFILLTUNING_TXFIFOTHRES_SHIFT)) & USB_TXFILLTUNING_TXFIFOTHRES_MASK)
/*! @} */
/*! @name ENDPTNAK - Endpoint NAK */
/*! @{ */
#define USB_ENDPTNAK_EPRN_MASK (0xFFU)
#define USB_ENDPTNAK_EPRN_SHIFT (0U)
/*! EPRN - EPRN
*/
#define USB_ENDPTNAK_EPRN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPRN_SHIFT)) & USB_ENDPTNAK_EPRN_MASK)
#define USB_ENDPTNAK_EPTN_MASK (0xFF0000U)
#define USB_ENDPTNAK_EPTN_SHIFT (16U)
/*! EPTN - EPTN
*/
#define USB_ENDPTNAK_EPTN(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAK_EPTN_SHIFT)) & USB_ENDPTNAK_EPTN_MASK)
/*! @} */
/*! @name ENDPTNAKEN - Endpoint NAK Enable */
/*! @{ */
#define USB_ENDPTNAKEN_EPRNE_MASK (0xFFU)
#define USB_ENDPTNAKEN_EPRNE_SHIFT (0U)
/*! EPRNE - EPRNE
*/
#define USB_ENDPTNAKEN_EPRNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPRNE_SHIFT)) & USB_ENDPTNAKEN_EPRNE_MASK)
#define USB_ENDPTNAKEN_EPTNE_MASK (0xFF0000U)
#define USB_ENDPTNAKEN_EPTNE_SHIFT (16U)
/*! EPTNE - EPTNE
*/
#define USB_ENDPTNAKEN_EPTNE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTNAKEN_EPTNE_SHIFT)) & USB_ENDPTNAKEN_EPTNE_MASK)
/*! @} */
/*! @name CONFIGFLAG - Configure Flag Register */
/*! @{ */
#define USB_CONFIGFLAG_CF_MASK (0x1U)
#define USB_CONFIGFLAG_CF_SHIFT (0U)
/*! CF - CF
* 0b0..Port routing control logic default-routes each port to an implementation dependent classic host controller.
* 0b1..Port routing control logic default-routes all ports to this host controller.
*/
#define USB_CONFIGFLAG_CF(x) (((uint32_t)(((uint32_t)(x)) << USB_CONFIGFLAG_CF_SHIFT)) & USB_CONFIGFLAG_CF_MASK)
/*! @} */
/*! @name PORTSC1 - Port Status & Control */
/*! @{ */
#define USB_PORTSC1_CCS_MASK (0x1U)
#define USB_PORTSC1_CCS_SHIFT (0U)
/*! CCS - CCS
*/
#define USB_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CCS_SHIFT)) & USB_PORTSC1_CCS_MASK)
#define USB_PORTSC1_CSC_MASK (0x2U)
#define USB_PORTSC1_CSC_SHIFT (1U)
/*! CSC - CSC
*/
#define USB_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_CSC_SHIFT)) & USB_PORTSC1_CSC_MASK)
#define USB_PORTSC1_PE_MASK (0x4U)
#define USB_PORTSC1_PE_SHIFT (2U)
/*! PE - PE
*/
#define USB_PORTSC1_PE(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PE_SHIFT)) & USB_PORTSC1_PE_MASK)
#define USB_PORTSC1_PEC_MASK (0x8U)
#define USB_PORTSC1_PEC_SHIFT (3U)
/*! PEC - PEC
*/
#define USB_PORTSC1_PEC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PEC_SHIFT)) & USB_PORTSC1_PEC_MASK)
#define USB_PORTSC1_OCA_MASK (0x10U)
#define USB_PORTSC1_OCA_SHIFT (4U)
/*! OCA - OCA
* 0b1..This port currently has an over-current condition
* 0b0..This port does not have an over-current condition.
*/
#define USB_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCA_SHIFT)) & USB_PORTSC1_OCA_MASK)
#define USB_PORTSC1_OCC_MASK (0x20U)
#define USB_PORTSC1_OCC_SHIFT (5U)
/*! OCC - OCC
*/
#define USB_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_OCC_SHIFT)) & USB_PORTSC1_OCC_MASK)
#define USB_PORTSC1_FPR_MASK (0x40U)
#define USB_PORTSC1_FPR_SHIFT (6U)
/*! FPR - FPR
*/
#define USB_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_FPR_SHIFT)) & USB_PORTSC1_FPR_MASK)
#define USB_PORTSC1_SUSP_MASK (0x80U)
#define USB_PORTSC1_SUSP_SHIFT (7U)
/*! SUSP - SUSP
*/
#define USB_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_SUSP_SHIFT)) & USB_PORTSC1_SUSP_MASK)
#define USB_PORTSC1_PR_MASK (0x100U)
#define USB_PORTSC1_PR_SHIFT (8U)
/*! PR - PR
*/
#define USB_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PR_SHIFT)) & USB_PORTSC1_PR_MASK)
#define USB_PORTSC1_HSP_MASK (0x200U)
#define USB_PORTSC1_HSP_SHIFT (9U)
/*! HSP - HSP
*/
#define USB_PORTSC1_HSP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_HSP_SHIFT)) & USB_PORTSC1_HSP_MASK)
#define USB_PORTSC1_LS_MASK (0xC00U)
#define USB_PORTSC1_LS_SHIFT (10U)
/*! LS - LS
* 0b00..SE0
* 0b10..J-state
* 0b01..K-state
* 0b11..Undefined
*/
#define USB_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_LS_SHIFT)) & USB_PORTSC1_LS_MASK)
#define USB_PORTSC1_PP_MASK (0x1000U)
#define USB_PORTSC1_PP_SHIFT (12U)
/*! PP - PP
*/
#define USB_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PP_SHIFT)) & USB_PORTSC1_PP_MASK)
#define USB_PORTSC1_PO_MASK (0x2000U)
#define USB_PORTSC1_PO_SHIFT (13U)
/*! PO - PO
*/
#define USB_PORTSC1_PO(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PO_SHIFT)) & USB_PORTSC1_PO_MASK)
#define USB_PORTSC1_PIC_MASK (0xC000U)
#define USB_PORTSC1_PIC_SHIFT (14U)
/*! PIC - PIC
* 0b00..Port indicators are off
* 0b01..Amber
* 0b10..Green
* 0b11..Undefined
*/
#define USB_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PIC_SHIFT)) & USB_PORTSC1_PIC_MASK)
#define USB_PORTSC1_PTC_MASK (0xF0000U)
#define USB_PORTSC1_PTC_SHIFT (16U)
/*! PTC - PTC
* 0b0000..TEST_MODE_DISABLE
* 0b0001..J_STATE
* 0b0010..K_STATE
* 0b0011..SE0 (host) / NAK (device)
* 0b0100..Packet
* 0b0101..FORCE_ENABLE_HS
* 0b0110..FORCE_ENABLE_FS
* 0b0111..FORCE_ENABLE_LS
* 0b1000-0b1111..Reserved
*/
#define USB_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTC_SHIFT)) & USB_PORTSC1_PTC_MASK)
#define USB_PORTSC1_WKCN_MASK (0x100000U)
#define USB_PORTSC1_WKCN_SHIFT (20U)
/*! WKCN - WKCN
*/
#define USB_PORTSC1_WKCN(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKCN_SHIFT)) & USB_PORTSC1_WKCN_MASK)
#define USB_PORTSC1_WKDC_MASK (0x200000U)
#define USB_PORTSC1_WKDC_SHIFT (21U)
/*! WKDC - WKDC
*/
#define USB_PORTSC1_WKDC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKDC_SHIFT)) & USB_PORTSC1_WKDC_MASK)
#define USB_PORTSC1_WKOC_MASK (0x400000U)
#define USB_PORTSC1_WKOC_SHIFT (22U)
/*! WKOC - WKOC
*/
#define USB_PORTSC1_WKOC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_WKOC_SHIFT)) & USB_PORTSC1_WKOC_MASK)
#define USB_PORTSC1_PHCD_MASK (0x800000U)
#define USB_PORTSC1_PHCD_SHIFT (23U)
/*! PHCD - PHCD
* 0b1..Disable PHY clock
* 0b0..Enable PHY clock
*/
#define USB_PORTSC1_PHCD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PHCD_SHIFT)) & USB_PORTSC1_PHCD_MASK)
#define USB_PORTSC1_PFSC_MASK (0x1000000U)
#define USB_PORTSC1_PFSC_SHIFT (24U)
/*! PFSC - PFSC
* 0b1..Forced to full speed
* 0b0..Normal operation
*/
#define USB_PORTSC1_PFSC(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PFSC_SHIFT)) & USB_PORTSC1_PFSC_MASK)
#define USB_PORTSC1_PTS_2_MASK (0x2000000U)
#define USB_PORTSC1_PTS_2_SHIFT (25U)
/*! PTS_2 - PTS_2
*/
#define USB_PORTSC1_PTS_2(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_2_SHIFT)) & USB_PORTSC1_PTS_2_MASK)
#define USB_PORTSC1_PSPD_MASK (0xC000000U)
#define USB_PORTSC1_PSPD_SHIFT (26U)
/*! PSPD - PSPD
* 0b00..Full Speed
* 0b01..Low Speed
* 0b10..High Speed
* 0b11..Undefined
*/
#define USB_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PSPD_SHIFT)) & USB_PORTSC1_PSPD_MASK)
#define USB_PORTSC1_PTW_MASK (0x10000000U)
#define USB_PORTSC1_PTW_SHIFT (28U)
/*! PTW - PTW
* 0b0..Select the 8-bit UTMI interface [60MHz]
* 0b1..Select the 16-bit UTMI interface [30MHz]
*/
#define USB_PORTSC1_PTW(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTW_SHIFT)) & USB_PORTSC1_PTW_MASK)
#define USB_PORTSC1_STS_MASK (0x20000000U)
#define USB_PORTSC1_STS_SHIFT (29U)
/*! STS - STS
*/
#define USB_PORTSC1_STS(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_STS_SHIFT)) & USB_PORTSC1_STS_MASK)
#define USB_PORTSC1_PTS_1_MASK (0xC0000000U)
#define USB_PORTSC1_PTS_1_SHIFT (30U)
/*! PTS_1 - PTS_1
*/
#define USB_PORTSC1_PTS_1(x) (((uint32_t)(((uint32_t)(x)) << USB_PORTSC1_PTS_1_SHIFT)) & USB_PORTSC1_PTS_1_MASK)
/*! @} */
/*! @name OTGSC - On-The-Go Status & control */
/*! @{ */
#define USB_OTGSC_VD_MASK (0x1U)
#define USB_OTGSC_VD_SHIFT (0U)
/*! VD - VD
*/
#define USB_OTGSC_VD(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VD_SHIFT)) & USB_OTGSC_VD_MASK)
#define USB_OTGSC_VC_MASK (0x2U)
#define USB_OTGSC_VC_SHIFT (1U)
/*! VC - VC
*/
#define USB_OTGSC_VC(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_VC_SHIFT)) & USB_OTGSC_VC_MASK)
#define USB_OTGSC_OT_MASK (0x8U)
#define USB_OTGSC_OT_SHIFT (3U)
/*! OT - OT
*/
#define USB_OTGSC_OT(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_OT_SHIFT)) & USB_OTGSC_OT_MASK)
#define USB_OTGSC_DP_MASK (0x10U)
#define USB_OTGSC_DP_SHIFT (4U)
/*! DP - DP
*/
#define USB_OTGSC_DP(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DP_SHIFT)) & USB_OTGSC_DP_MASK)
#define USB_OTGSC_IDPU_MASK (0x20U)
#define USB_OTGSC_IDPU_SHIFT (5U)
/*! IDPU - IDPU
*/
#define USB_OTGSC_IDPU(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDPU_SHIFT)) & USB_OTGSC_IDPU_MASK)
#define USB_OTGSC_ID_MASK (0x100U)
#define USB_OTGSC_ID_SHIFT (8U)
/*! ID - ID
*/
#define USB_OTGSC_ID(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ID_SHIFT)) & USB_OTGSC_ID_MASK)
#define USB_OTGSC_AVV_MASK (0x200U)
#define USB_OTGSC_AVV_SHIFT (9U)
/*! AVV - AVV
*/
#define USB_OTGSC_AVV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVV_SHIFT)) & USB_OTGSC_AVV_MASK)
#define USB_OTGSC_ASV_MASK (0x400U)
#define USB_OTGSC_ASV_SHIFT (10U)
/*! ASV - ASV
*/
#define USB_OTGSC_ASV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASV_SHIFT)) & USB_OTGSC_ASV_MASK)
#define USB_OTGSC_BSV_MASK (0x800U)
#define USB_OTGSC_BSV_SHIFT (11U)
/*! BSV - BSV
*/
#define USB_OTGSC_BSV(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSV_SHIFT)) & USB_OTGSC_BSV_MASK)
#define USB_OTGSC_BSE_MASK (0x1000U)
#define USB_OTGSC_BSE_SHIFT (12U)
/*! BSE - BSE
*/
#define USB_OTGSC_BSE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSE_SHIFT)) & USB_OTGSC_BSE_MASK)
#define USB_OTGSC_TOG_1MS_MASK (0x2000U)
#define USB_OTGSC_TOG_1MS_SHIFT (13U)
/*! TOG_1MS - TOG_1MS
*/
#define USB_OTGSC_TOG_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_TOG_1MS_SHIFT)) & USB_OTGSC_TOG_1MS_MASK)
#define USB_OTGSC_DPS_MASK (0x4000U)
#define USB_OTGSC_DPS_SHIFT (14U)
/*! DPS - DPS
*/
#define USB_OTGSC_DPS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPS_SHIFT)) & USB_OTGSC_DPS_MASK)
#define USB_OTGSC_IDIS_MASK (0x10000U)
#define USB_OTGSC_IDIS_SHIFT (16U)
/*! IDIS - IDIS
*/
#define USB_OTGSC_IDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIS_SHIFT)) & USB_OTGSC_IDIS_MASK)
#define USB_OTGSC_AVVIS_MASK (0x20000U)
#define USB_OTGSC_AVVIS_SHIFT (17U)
/*! AVVIS - AVVIS
*/
#define USB_OTGSC_AVVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIS_SHIFT)) & USB_OTGSC_AVVIS_MASK)
#define USB_OTGSC_ASVIS_MASK (0x40000U)
#define USB_OTGSC_ASVIS_SHIFT (18U)
/*! ASVIS - ASVIS
*/
#define USB_OTGSC_ASVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIS_SHIFT)) & USB_OTGSC_ASVIS_MASK)
#define USB_OTGSC_BSVIS_MASK (0x80000U)
#define USB_OTGSC_BSVIS_SHIFT (19U)
/*! BSVIS - BSVIS
*/
#define USB_OTGSC_BSVIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIS_SHIFT)) & USB_OTGSC_BSVIS_MASK)
#define USB_OTGSC_BSEIS_MASK (0x100000U)
#define USB_OTGSC_BSEIS_SHIFT (20U)
/*! BSEIS - BSEIS
*/
#define USB_OTGSC_BSEIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIS_SHIFT)) & USB_OTGSC_BSEIS_MASK)
#define USB_OTGSC_STATUS_1MS_MASK (0x200000U)
#define USB_OTGSC_STATUS_1MS_SHIFT (21U)
/*! STATUS_1MS - STATUS_1MS
*/
#define USB_OTGSC_STATUS_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_STATUS_1MS_SHIFT)) & USB_OTGSC_STATUS_1MS_MASK)
#define USB_OTGSC_DPIS_MASK (0x400000U)
#define USB_OTGSC_DPIS_SHIFT (22U)
/*! DPIS - DPIS
*/
#define USB_OTGSC_DPIS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIS_SHIFT)) & USB_OTGSC_DPIS_MASK)
#define USB_OTGSC_IDIE_MASK (0x1000000U)
#define USB_OTGSC_IDIE_SHIFT (24U)
/*! IDIE - IDIE
*/
#define USB_OTGSC_IDIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_IDIE_SHIFT)) & USB_OTGSC_IDIE_MASK)
#define USB_OTGSC_AVVIE_MASK (0x2000000U)
#define USB_OTGSC_AVVIE_SHIFT (25U)
/*! AVVIE - AVVIE
*/
#define USB_OTGSC_AVVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_AVVIE_SHIFT)) & USB_OTGSC_AVVIE_MASK)
#define USB_OTGSC_ASVIE_MASK (0x4000000U)
#define USB_OTGSC_ASVIE_SHIFT (26U)
/*! ASVIE - ASVIE
*/
#define USB_OTGSC_ASVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_ASVIE_SHIFT)) & USB_OTGSC_ASVIE_MASK)
#define USB_OTGSC_BSVIE_MASK (0x8000000U)
#define USB_OTGSC_BSVIE_SHIFT (27U)
/*! BSVIE - BSVIE
*/
#define USB_OTGSC_BSVIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSVIE_SHIFT)) & USB_OTGSC_BSVIE_MASK)
#define USB_OTGSC_BSEIE_MASK (0x10000000U)
#define USB_OTGSC_BSEIE_SHIFT (28U)
/*! BSEIE - BSEIE
*/
#define USB_OTGSC_BSEIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_BSEIE_SHIFT)) & USB_OTGSC_BSEIE_MASK)
#define USB_OTGSC_EN_1MS_MASK (0x20000000U)
#define USB_OTGSC_EN_1MS_SHIFT (29U)
/*! EN_1MS - EN_1MS
*/
#define USB_OTGSC_EN_1MS(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_EN_1MS_SHIFT)) & USB_OTGSC_EN_1MS_MASK)
#define USB_OTGSC_DPIE_MASK (0x40000000U)
#define USB_OTGSC_DPIE_SHIFT (30U)
/*! DPIE - DPIE
*/
#define USB_OTGSC_DPIE(x) (((uint32_t)(((uint32_t)(x)) << USB_OTGSC_DPIE_SHIFT)) & USB_OTGSC_DPIE_MASK)
/*! @} */
/*! @name USBMODE - USB Device Mode */
/*! @{ */
#define USB_USBMODE_CM_MASK (0x3U)
#define USB_USBMODE_CM_SHIFT (0U)
/*! CM - CM
* 0b00..Idle [Default for combination host/device]
* 0b01..Reserved
* 0b10..Device Controller [Default for device only controller]
* 0b11..Host Controller [Default for host only controller]
*/
#define USB_USBMODE_CM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_CM_SHIFT)) & USB_USBMODE_CM_MASK)
#define USB_USBMODE_ES_MASK (0x4U)
#define USB_USBMODE_ES_SHIFT (2U)
/*! ES - ES
* 0b0..Little Endian [Default]
* 0b1..Big Endian
*/
#define USB_USBMODE_ES(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_ES_SHIFT)) & USB_USBMODE_ES_MASK)
#define USB_USBMODE_SLOM_MASK (0x8U)
#define USB_USBMODE_SLOM_SHIFT (3U)
/*! SLOM - SLOM
* 0b0..Setup Lockouts On (default);
* 0b1..Setup Lockouts Off
*/
#define USB_USBMODE_SLOM(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SLOM_SHIFT)) & USB_USBMODE_SLOM_MASK)
#define USB_USBMODE_SDIS_MASK (0x10U)
#define USB_USBMODE_SDIS_SHIFT (4U)
/*! SDIS - SDIS
*/
#define USB_USBMODE_SDIS(x) (((uint32_t)(((uint32_t)(x)) << USB_USBMODE_SDIS_SHIFT)) & USB_USBMODE_SDIS_MASK)
/*! @} */
/*! @name ENDPTSETUPSTAT - Endpoint Setup Status */
/*! @{ */
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK (0xFFFFU)
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT (0U)
/*! ENDPTSETUPSTAT - ENDPTSETUPSTAT
*/
#define USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT)) & USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK)
/*! @} */
/*! @name ENDPTPRIME - Endpoint Prime */
/*! @{ */
#define USB_ENDPTPRIME_PERB_MASK (0xFFU)
#define USB_ENDPTPRIME_PERB_SHIFT (0U)
/*! PERB - PERB
*/
#define USB_ENDPTPRIME_PERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PERB_SHIFT)) & USB_ENDPTPRIME_PERB_MASK)
#define USB_ENDPTPRIME_PETB_MASK (0xFF0000U)
#define USB_ENDPTPRIME_PETB_SHIFT (16U)
/*! PETB - PETB
*/
#define USB_ENDPTPRIME_PETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTPRIME_PETB_SHIFT)) & USB_ENDPTPRIME_PETB_MASK)
/*! @} */
/*! @name ENDPTFLUSH - Endpoint Flush */
/*! @{ */
#define USB_ENDPTFLUSH_FERB_MASK (0xFFU)
#define USB_ENDPTFLUSH_FERB_SHIFT (0U)
/*! FERB - FERB
*/
#define USB_ENDPTFLUSH_FERB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FERB_SHIFT)) & USB_ENDPTFLUSH_FERB_MASK)
#define USB_ENDPTFLUSH_FETB_MASK (0xFF0000U)
#define USB_ENDPTFLUSH_FETB_SHIFT (16U)
/*! FETB - FETB
*/
#define USB_ENDPTFLUSH_FETB(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTFLUSH_FETB_SHIFT)) & USB_ENDPTFLUSH_FETB_MASK)
/*! @} */
/*! @name ENDPTSTAT - Endpoint Status */
/*! @{ */
#define USB_ENDPTSTAT_ERBR_MASK (0xFFU)
#define USB_ENDPTSTAT_ERBR_SHIFT (0U)
/*! ERBR - ERBR
*/
#define USB_ENDPTSTAT_ERBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ERBR_SHIFT)) & USB_ENDPTSTAT_ERBR_MASK)
#define USB_ENDPTSTAT_ETBR_MASK (0xFF0000U)
#define USB_ENDPTSTAT_ETBR_SHIFT (16U)
/*! ETBR - ETBR
*/
#define USB_ENDPTSTAT_ETBR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTSTAT_ETBR_SHIFT)) & USB_ENDPTSTAT_ETBR_MASK)
/*! @} */
/*! @name ENDPTCOMPLETE - Endpoint Complete */
/*! @{ */
#define USB_ENDPTCOMPLETE_ERCE_MASK (0xFFU)
#define USB_ENDPTCOMPLETE_ERCE_SHIFT (0U)
/*! ERCE - ERCE
*/
#define USB_ENDPTCOMPLETE_ERCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ERCE_SHIFT)) & USB_ENDPTCOMPLETE_ERCE_MASK)
#define USB_ENDPTCOMPLETE_ETCE_MASK (0xFF0000U)
#define USB_ENDPTCOMPLETE_ETCE_SHIFT (16U)
/*! ETCE - ETCE
*/
#define USB_ENDPTCOMPLETE_ETCE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCOMPLETE_ETCE_SHIFT)) & USB_ENDPTCOMPLETE_ETCE_MASK)
/*! @} */
/*! @name ENDPTCTRL0 - Endpoint Control0 */
/*! @{ */
#define USB_ENDPTCTRL0_RXS_MASK (0x1U)
#define USB_ENDPTCTRL0_RXS_SHIFT (0U)
/*! RXS - RXS
*/
#define USB_ENDPTCTRL0_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXS_SHIFT)) & USB_ENDPTCTRL0_RXS_MASK)
#define USB_ENDPTCTRL0_RXT_MASK (0xCU)
#define USB_ENDPTCTRL0_RXT_SHIFT (2U)
/*! RXT - RXT
*/
#define USB_ENDPTCTRL0_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXT_SHIFT)) & USB_ENDPTCTRL0_RXT_MASK)
#define USB_ENDPTCTRL0_RXE_MASK (0x80U)
#define USB_ENDPTCTRL0_RXE_SHIFT (7U)
/*! RXE - RXE
*/
#define USB_ENDPTCTRL0_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_RXE_SHIFT)) & USB_ENDPTCTRL0_RXE_MASK)
#define USB_ENDPTCTRL0_TXS_MASK (0x10000U)
#define USB_ENDPTCTRL0_TXS_SHIFT (16U)
/*! TXS - TXS
*/
#define USB_ENDPTCTRL0_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXS_SHIFT)) & USB_ENDPTCTRL0_TXS_MASK)
#define USB_ENDPTCTRL0_TXT_MASK (0xC0000U)
#define USB_ENDPTCTRL0_TXT_SHIFT (18U)
/*! TXT - TXT
*/
#define USB_ENDPTCTRL0_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXT_SHIFT)) & USB_ENDPTCTRL0_TXT_MASK)
#define USB_ENDPTCTRL0_TXE_MASK (0x800000U)
#define USB_ENDPTCTRL0_TXE_SHIFT (23U)
/*! TXE - TXE
*/
#define USB_ENDPTCTRL0_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL0_TXE_SHIFT)) & USB_ENDPTCTRL0_TXE_MASK)
/*! @} */
/*! @name ENDPTCTRL - Endpoint Control 1..Endpoint Control 7 */
/*! @{ */
#define USB_ENDPTCTRL_RXS_MASK (0x1U)
#define USB_ENDPTCTRL_RXS_SHIFT (0U)
/*! RXS - RXS
*/
#define USB_ENDPTCTRL_RXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXS_SHIFT)) & USB_ENDPTCTRL_RXS_MASK)
#define USB_ENDPTCTRL_RXD_MASK (0x2U)
#define USB_ENDPTCTRL_RXD_SHIFT (1U)
/*! RXD - RXD
*/
#define USB_ENDPTCTRL_RXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXD_SHIFT)) & USB_ENDPTCTRL_RXD_MASK)
#define USB_ENDPTCTRL_RXT_MASK (0xCU)
#define USB_ENDPTCTRL_RXT_SHIFT (2U)
/*! RXT - RXT
*/
#define USB_ENDPTCTRL_RXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXT_SHIFT)) & USB_ENDPTCTRL_RXT_MASK)
#define USB_ENDPTCTRL_RXI_MASK (0x20U)
#define USB_ENDPTCTRL_RXI_SHIFT (5U)
/*! RXI - RXI
*/
#define USB_ENDPTCTRL_RXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXI_SHIFT)) & USB_ENDPTCTRL_RXI_MASK)
#define USB_ENDPTCTRL_RXR_MASK (0x40U)
#define USB_ENDPTCTRL_RXR_SHIFT (6U)
/*! RXR - RXR
*/
#define USB_ENDPTCTRL_RXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXR_SHIFT)) & USB_ENDPTCTRL_RXR_MASK)
#define USB_ENDPTCTRL_RXE_MASK (0x80U)
#define USB_ENDPTCTRL_RXE_SHIFT (7U)
/*! RXE - RXE
*/
#define USB_ENDPTCTRL_RXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_RXE_SHIFT)) & USB_ENDPTCTRL_RXE_MASK)
#define USB_ENDPTCTRL_TXS_MASK (0x10000U)
#define USB_ENDPTCTRL_TXS_SHIFT (16U)
/*! TXS - TXS
*/
#define USB_ENDPTCTRL_TXS(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXS_SHIFT)) & USB_ENDPTCTRL_TXS_MASK)
#define USB_ENDPTCTRL_TXD_MASK (0x20000U)
#define USB_ENDPTCTRL_TXD_SHIFT (17U)
/*! TXD - TXD
*/
#define USB_ENDPTCTRL_TXD(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXD_SHIFT)) & USB_ENDPTCTRL_TXD_MASK)
#define USB_ENDPTCTRL_TXT_MASK (0xC0000U)
#define USB_ENDPTCTRL_TXT_SHIFT (18U)
/*! TXT - TXT
*/
#define USB_ENDPTCTRL_TXT(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXT_SHIFT)) & USB_ENDPTCTRL_TXT_MASK)
#define USB_ENDPTCTRL_TXI_MASK (0x200000U)
#define USB_ENDPTCTRL_TXI_SHIFT (21U)
/*! TXI - TXI
*/
#define USB_ENDPTCTRL_TXI(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXI_SHIFT)) & USB_ENDPTCTRL_TXI_MASK)
#define USB_ENDPTCTRL_TXR_MASK (0x400000U)
#define USB_ENDPTCTRL_TXR_SHIFT (22U)
/*! TXR - TXR
*/
#define USB_ENDPTCTRL_TXR(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXR_SHIFT)) & USB_ENDPTCTRL_TXR_MASK)
#define USB_ENDPTCTRL_TXE_MASK (0x800000U)
#define USB_ENDPTCTRL_TXE_SHIFT (23U)
/*! TXE - TXE
*/
#define USB_ENDPTCTRL_TXE(x) (((uint32_t)(((uint32_t)(x)) << USB_ENDPTCTRL_TXE_SHIFT)) & USB_ENDPTCTRL_TXE_MASK)
/*! @} */
/* The count of USB_ENDPTCTRL */
#define USB_ENDPTCTRL_COUNT (7U)
/*!
* @}
*/ /* end of group USB_Register_Masks */
/* USB - Peripheral instance base addresses */
/** Peripheral USB_OTG1 base address */
#define USB_OTG1_BASE (0x40430000u)
/** Peripheral USB_OTG1 base pointer */
#define USB_OTG1 ((USB_Type *)USB_OTG1_BASE)
/** Peripheral USB_OTG2 base address */
#define USB_OTG2_BASE (0x4042C000u)
/** Peripheral USB_OTG2 base pointer */
#define USB_OTG2 ((USB_Type *)USB_OTG2_BASE)
/** Array initializer of USB peripheral base addresses */
#define USB_BASE_ADDRS { 0u, USB_OTG1_BASE, USB_OTG2_BASE }
/** Array initializer of USB peripheral base pointers */
#define USB_BASE_PTRS { (USB_Type *)0u, USB_OTG1, USB_OTG2 }
/** Interrupt vectors for the USB peripheral type */
#define USB_IRQS { NotAvail_IRQn, USB_OTG1_IRQn, USB_OTG2_IRQn }
/* Backward compatibility */
#define GPTIMER0CTL GPTIMER0CTRL
#define GPTIMER1CTL GPTIMER1CTRL
#define USB_SBUSCFG SBUSCFG
#define EPLISTADDR ENDPTLISTADDR
#define EPSETUPSR ENDPTSETUPSTAT
#define EPPRIME ENDPTPRIME
#define EPFLUSH ENDPTFLUSH
#define EPSR ENDPTSTAT
#define EPCOMPLETE ENDPTCOMPLETE
#define EPCR ENDPTCTRL
#define EPCR0 ENDPTCTRL0
#define USBHS_ID_ID_MASK USB_ID_ID_MASK
#define USBHS_ID_ID_SHIFT USB_ID_ID_SHIFT
#define USBHS_ID_ID(x) USB_ID_ID(x)
#define USBHS_ID_NID_MASK USB_ID_NID_MASK
#define USBHS_ID_NID_SHIFT USB_ID_NID_SHIFT
#define USBHS_ID_NID(x) USB_ID_NID(x)
#define USBHS_ID_REVISION_MASK USB_ID_REVISION_MASK
#define USBHS_ID_REVISION_SHIFT USB_ID_REVISION_SHIFT
#define USBHS_ID_REVISION(x) USB_ID_REVISION(x)
#define USBHS_HWGENERAL_PHYW_MASK USB_HWGENERAL_PHYW_MASK
#define USBHS_HWGENERAL_PHYW_SHIFT USB_HWGENERAL_PHYW_SHIFT
#define USBHS_HWGENERAL_PHYW(x) USB_HWGENERAL_PHYW(x)
#define USBHS_HWGENERAL_PHYM_MASK USB_HWGENERAL_PHYM_MASK
#define USBHS_HWGENERAL_PHYM_SHIFT USB_HWGENERAL_PHYM_SHIFT
#define USBHS_HWGENERAL_PHYM(x) USB_HWGENERAL_PHYM(x)
#define USBHS_HWGENERAL_SM_MASK USB_HWGENERAL_SM_MASK
#define USBHS_HWGENERAL_SM_SHIFT USB_HWGENERAL_SM_SHIFT
#define USBHS_HWGENERAL_SM(x) USB_HWGENERAL_SM(x)
#define USBHS_HWHOST_HC_MASK USB_HWHOST_HC_MASK
#define USBHS_HWHOST_HC_SHIFT USB_HWHOST_HC_SHIFT
#define USBHS_HWHOST_HC(x) USB_HWHOST_HC(x)
#define USBHS_HWHOST_NPORT_MASK USB_HWHOST_NPORT_MASK
#define USBHS_HWHOST_NPORT_SHIFT USB_HWHOST_NPORT_SHIFT
#define USBHS_HWHOST_NPORT(x) USB_HWHOST_NPORT(x)
#define USBHS_HWDEVICE_DC_MASK USB_HWDEVICE_DC_MASK
#define USBHS_HWDEVICE_DC_SHIFT USB_HWDEVICE_DC_SHIFT
#define USBHS_HWDEVICE_DC(x) USB_HWDEVICE_DC(x)
#define USBHS_HWDEVICE_DEVEP_MASK USB_HWDEVICE_DEVEP_MASK
#define USBHS_HWDEVICE_DEVEP_SHIFT USB_HWDEVICE_DEVEP_SHIFT
#define USBHS_HWDEVICE_DEVEP(x) USB_HWDEVICE_DEVEP(x)
#define USBHS_HWTXBUF_TXBURST_MASK USB_HWTXBUF_TXBURST_MASK
#define USBHS_HWTXBUF_TXBURST_SHIFT USB_HWTXBUF_TXBURST_SHIFT
#define USBHS_HWTXBUF_TXBURST(x) USB_HWTXBUF_TXBURST(x)
#define USBHS_HWTXBUF_TXCHANADD_MASK USB_HWTXBUF_TXCHANADD_MASK
#define USBHS_HWTXBUF_TXCHANADD_SHIFT USB_HWTXBUF_TXCHANADD_SHIFT
#define USBHS_HWTXBUF_TXCHANADD(x) USB_HWTXBUF_TXCHANADD(x)
#define USBHS_HWRXBUF_RXBURST_MASK USB_HWRXBUF_RXBURST_MASK
#define USBHS_HWRXBUF_RXBURST_SHIFT USB_HWRXBUF_RXBURST_SHIFT
#define USBHS_HWRXBUF_RXBURST(x) USB_HWRXBUF_RXBURST(x)
#define USBHS_HWRXBUF_RXADD_MASK USB_HWRXBUF_RXADD_MASK
#define USBHS_HWRXBUF_RXADD_SHIFT USB_HWRXBUF_RXADD_SHIFT
#define USBHS_HWRXBUF_RXADD(x) USB_HWRXBUF_RXADD(x)
#define USBHS_GPTIMER0LD_GPTLD_MASK USB_GPTIMER0LD_GPTLD_MASK
#define USBHS_GPTIMER0LD_GPTLD_SHIFT USB_GPTIMER0LD_GPTLD_SHIFT
#define USBHS_GPTIMER0LD_GPTLD(x) USB_GPTIMER0LD_GPTLD(x)
#define USBHS_GPTIMER0CTL_GPTCNT_MASK USB_GPTIMER0CTRL_GPTCNT_MASK
#define USBHS_GPTIMER0CTL_GPTCNT_SHIFT USB_GPTIMER0CTRL_GPTCNT_SHIFT
#define USBHS_GPTIMER0CTL_GPTCNT(x) USB_GPTIMER0CTRL_GPTCNT(x)
#define USBHS_GPTIMER0CTL_MODE_MASK USB_GPTIMER0CTRL_GPTMODE_MASK
#define USBHS_GPTIMER0CTL_MODE_SHIFT USB_GPTIMER0CTRL_GPTMODE_SHIFT
#define USBHS_GPTIMER0CTL_MODE(x) USB_GPTIMER0CTRL_GPTMODE(x)
#define USBHS_GPTIMER0CTL_RST_MASK USB_GPTIMER0CTRL_GPTRST_MASK
#define USBHS_GPTIMER0CTL_RST_SHIFT USB_GPTIMER0CTRL_GPTRST_SHIFT
#define USBHS_GPTIMER0CTL_RST(x) USB_GPTIMER0CTRL_GPTRST(x)
#define USBHS_GPTIMER0CTL_RUN_MASK USB_GPTIMER0CTRL_GPTRUN_MASK
#define USBHS_GPTIMER0CTL_RUN_SHIFT USB_GPTIMER0CTRL_GPTRUN_SHIFT
#define USBHS_GPTIMER0CTL_RUN(x) USB_GPTIMER0CTRL_GPTRUN(x)
#define USBHS_GPTIMER1LD_GPTLD_MASK USB_GPTIMER1LD_GPTLD_MASK
#define USBHS_GPTIMER1LD_GPTLD_SHIFT USB_GPTIMER1LD_GPTLD_SHIFT
#define USBHS_GPTIMER1LD_GPTLD(x) USB_GPTIMER1LD_GPTLD(x)
#define USBHS_GPTIMER1CTL_GPTCNT_MASK USB_GPTIMER1CTRL_GPTCNT_MASK
#define USBHS_GPTIMER1CTL_GPTCNT_SHIFT USB_GPTIMER1CTRL_GPTCNT_SHIFT
#define USBHS_GPTIMER1CTL_GPTCNT(x) USB_GPTIMER1CTRL_GPTCNT(x)
#define USBHS_GPTIMER1CTL_MODE_MASK USB_GPTIMER1CTRL_GPTMODE_MASK
#define USBHS_GPTIMER1CTL_MODE_SHIFT USB_GPTIMER1CTRL_GPTMODE_SHIFT
#define USBHS_GPTIMER1CTL_MODE(x) USB_GPTIMER1CTRL_GPTMODE(x)
#define USBHS_GPTIMER1CTL_RST_MASK USB_GPTIMER1CTRL_GPTRST_MASK
#define USBHS_GPTIMER1CTL_RST_SHIFT USB_GPTIMER1CTRL_GPTRST_SHIFT
#define USBHS_GPTIMER1CTL_RST(x) USB_GPTIMER1CTRL_GPTRST(x)
#define USBHS_GPTIMER1CTL_RUN_MASK USB_GPTIMER1CTRL_GPTRUN_MASK
#define USBHS_GPTIMER1CTL_RUN_SHIFT USB_GPTIMER1CTRL_GPTRUN_SHIFT
#define USBHS_GPTIMER1CTL_RUN(x) USB_GPTIMER1CTRL_GPTRUN(x)
#define USBHS_USB_SBUSCFG_BURSTMODE_MASK USB_SBUSCFG_AHBBRST_MASK
#define USBHS_USB_SBUSCFG_BURSTMODE_SHIFT USB_SBUSCFG_AHBBRST_SHIFT
#define USBHS_USB_SBUSCFG_BURSTMODE(x) USB_SBUSCFG_AHBBRST(x)
#define USBHS_HCIVERSION_CAPLENGTH(x) USB_HCIVERSION_CAPLENGTH(x)
#define USBHS_HCIVERSION_HCIVERSION_MASK USB_HCIVERSION_HCIVERSION_MASK
#define USBHS_HCIVERSION_HCIVERSION_SHIFT USB_HCIVERSION_HCIVERSION_SHIFT
#define USBHS_HCIVERSION_HCIVERSION(x) USB_HCIVERSION_HCIVERSION(x)
#define USBHS_HCSPARAMS_N_PORTS_MASK USB_HCSPARAMS_N_PORTS_MASK
#define USBHS_HCSPARAMS_N_PORTS_SHIFT USB_HCSPARAMS_N_PORTS_SHIFT
#define USBHS_HCSPARAMS_N_PORTS(x) USB_HCSPARAMS_N_PORTS(x)
#define USBHS_HCSPARAMS_PPC_MASK USB_HCSPARAMS_PPC_MASK
#define USBHS_HCSPARAMS_PPC_SHIFT USB_HCSPARAMS_PPC_SHIFT
#define USBHS_HCSPARAMS_PPC(x) USB_HCSPARAMS_PPC(x)
#define USBHS_HCSPARAMS_N_PCC_MASK USB_HCSPARAMS_N_PCC_MASK
#define USBHS_HCSPARAMS_N_PCC_SHIFT USB_HCSPARAMS_N_PCC_SHIFT
#define USBHS_HCSPARAMS_N_PCC(x) USB_HCSPARAMS_N_PCC(x)
#define USBHS_HCSPARAMS_N_CC_MASK USB_HCSPARAMS_N_CC_MASK
#define USBHS_HCSPARAMS_N_CC_SHIFT USB_HCSPARAMS_N_CC_SHIFT
#define USBHS_HCSPARAMS_N_CC(x) USB_HCSPARAMS_N_CC(x)
#define USBHS_HCSPARAMS_PI_MASK USB_HCSPARAMS_PI_MASK
#define USBHS_HCSPARAMS_PI_SHIFT USB_HCSPARAMS_PI_SHIFT
#define USBHS_HCSPARAMS_PI(x) USB_HCSPARAMS_PI(x)
#define USBHS_HCSPARAMS_N_PTT_MASK USB_HCSPARAMS_N_PTT_MASK
#define USBHS_HCSPARAMS_N_PTT_SHIFT USB_HCSPARAMS_N_PTT_SHIFT
#define USBHS_HCSPARAMS_N_PTT(x) USB_HCSPARAMS_N_PTT(x)
#define USBHS_HCSPARAMS_N_TT_MASK USB_HCSPARAMS_N_TT_MASK
#define USBHS_HCSPARAMS_N_TT_SHIFT USB_HCSPARAMS_N_TT_SHIFT
#define USBHS_HCSPARAMS_N_TT(x) USB_HCSPARAMS_N_TT(x)
#define USBHS_HCCPARAMS_ADC_MASK USB_HCCPARAMS_ADC_MASK
#define USBHS_HCCPARAMS_ADC_SHIFT USB_HCCPARAMS_ADC_SHIFT
#define USBHS_HCCPARAMS_ADC(x) USB_HCCPARAMS_ADC(x)
#define USBHS_HCCPARAMS_PFL_MASK USB_HCCPARAMS_PFL_MASK
#define USBHS_HCCPARAMS_PFL_SHIFT USB_HCCPARAMS_PFL_SHIFT
#define USBHS_HCCPARAMS_PFL(x) USB_HCCPARAMS_PFL(x)
#define USBHS_HCCPARAMS_ASP_MASK USB_HCCPARAMS_ASP_MASK
#define USBHS_HCCPARAMS_ASP_SHIFT USB_HCCPARAMS_ASP_SHIFT
#define USBHS_HCCPARAMS_ASP(x) USB_HCCPARAMS_ASP(x)
#define USBHS_HCCPARAMS_IST_MASK USB_HCCPARAMS_IST_MASK
#define USBHS_HCCPARAMS_IST_SHIFT USB_HCCPARAMS_IST_SHIFT
#define USBHS_HCCPARAMS_IST(x) USB_HCCPARAMS_IST(x)
#define USBHS_HCCPARAMS_EECP_MASK USB_HCCPARAMS_EECP_MASK
#define USBHS_HCCPARAMS_EECP_SHIFT USB_HCCPARAMS_EECP_SHIFT
#define USBHS_HCCPARAMS_EECP(x) USB_HCCPARAMS_EECP(x)
#define USBHS_DCIVERSION_DCIVERSION_MASK USB_DCIVERSION_DCIVERSION_MASK
#define USBHS_DCIVERSION_DCIVERSION_SHIFT USB_DCIVERSION_DCIVERSION_SHIFT
#define USBHS_DCIVERSION_DCIVERSION(x) USB_DCIVERSION_DCIVERSION(x)
#define USBHS_DCCPARAMS_DEN_MASK USB_DCCPARAMS_DEN_MASK
#define USBHS_DCCPARAMS_DEN_SHIFT USB_DCCPARAMS_DEN_SHIFT
#define USBHS_DCCPARAMS_DEN(x) USB_DCCPARAMS_DEN(x)
#define USBHS_DCCPARAMS_DC_MASK USB_DCCPARAMS_DC_MASK
#define USBHS_DCCPARAMS_DC_SHIFT USB_DCCPARAMS_DC_SHIFT
#define USBHS_DCCPARAMS_DC(x) USB_DCCPARAMS_DC(x)
#define USBHS_DCCPARAMS_HC_MASK USB_DCCPARAMS_HC_MASK
#define USBHS_DCCPARAMS_HC_SHIFT USB_DCCPARAMS_HC_SHIFT
#define USBHS_DCCPARAMS_HC(x) USB_DCCPARAMS_HC(x)
#define USBHS_USBCMD_RS_MASK USB_USBCMD_RS_MASK
#define USBHS_USBCMD_RS_SHIFT USB_USBCMD_RS_SHIFT
#define USBHS_USBCMD_RS(x) USB_USBCMD_RS(x)
#define USBHS_USBCMD_RST_MASK USB_USBCMD_RST_MASK
#define USBHS_USBCMD_RST_SHIFT USB_USBCMD_RST_SHIFT
#define USBHS_USBCMD_RST(x) USB_USBCMD_RST(x)
#define USBHS_USBCMD_FS_MASK USB_USBCMD_FS_1_MASK
#define USBHS_USBCMD_FS_SHIFT USB_USBCMD_FS_1_SHIFT
#define USBHS_USBCMD_FS(x) USB_USBCMD_FS_1(x)
#define USBHS_USBCMD_PSE_MASK USB_USBCMD_PSE_MASK
#define USBHS_USBCMD_PSE_SHIFT USB_USBCMD_PSE_SHIFT
#define USBHS_USBCMD_PSE(x) USB_USBCMD_PSE(x)
#define USBHS_USBCMD_ASE_MASK USB_USBCMD_ASE_MASK
#define USBHS_USBCMD_ASE_SHIFT USB_USBCMD_ASE_SHIFT
#define USBHS_USBCMD_ASE(x) USB_USBCMD_ASE(x)
#define USBHS_USBCMD_IAA_MASK USB_USBCMD_IAA_MASK
#define USBHS_USBCMD_IAA_SHIFT USB_USBCMD_IAA_SHIFT
#define USBHS_USBCMD_IAA(x) USB_USBCMD_IAA(x)
#define USBHS_USBCMD_ASP_MASK USB_USBCMD_ASP_MASK
#define USBHS_USBCMD_ASP_SHIFT USB_USBCMD_ASP_SHIFT
#define USBHS_USBCMD_ASP(x) USB_USBCMD_ASP(x)
#define USBHS_USBCMD_ASPE_MASK USB_USBCMD_ASPE_MASK
#define USBHS_USBCMD_ASPE_SHIFT USB_USBCMD_ASPE_SHIFT
#define USBHS_USBCMD_ASPE(x) USB_USBCMD_ASPE(x)
#define USBHS_USBCMD_ATDTW_MASK USB_USBCMD_ATDTW_MASK
#define USBHS_USBCMD_ATDTW_SHIFT USB_USBCMD_ATDTW_SHIFT
#define USBHS_USBCMD_ATDTW(x) USB_USBCMD_ATDTW(x)
#define USBHS_USBCMD_SUTW_MASK USB_USBCMD_SUTW_MASK
#define USBHS_USBCMD_SUTW_SHIFT USB_USBCMD_SUTW_SHIFT
#define USBHS_USBCMD_SUTW(x) USB_USBCMD_SUTW(x)
#define USBHS_USBCMD_FS2_MASK USB_USBCMD_FS_2_MASK
#define USBHS_USBCMD_FS2_SHIFT USB_USBCMD_FS_2_SHIFT
#define USBHS_USBCMD_FS2(x) USB_USBCMD_FS_2(x)
#define USBHS_USBCMD_ITC_MASK USB_USBCMD_ITC_MASK
#define USBHS_USBCMD_ITC_SHIFT USB_USBCMD_ITC_SHIFT
#define USBHS_USBCMD_ITC(x) USB_USBCMD_ITC(x)
#define USBHS_USBSTS_UI_MASK USB_USBSTS_UI_MASK
#define USBHS_USBSTS_UI_SHIFT USB_USBSTS_UI_SHIFT
#define USBHS_USBSTS_UI(x) USB_USBSTS_UI(x)
#define USBHS_USBSTS_UEI_MASK USB_USBSTS_UEI_MASK
#define USBHS_USBSTS_UEI_SHIFT USB_USBSTS_UEI_SHIFT
#define USBHS_USBSTS_UEI(x) USB_USBSTS_UEI(x)
#define USBHS_USBSTS_PCI_MASK USB_USBSTS_PCI_MASK
#define USBHS_USBSTS_PCI_SHIFT USB_USBSTS_PCI_SHIFT
#define USBHS_USBSTS_PCI(x) USB_USBSTS_PCI(x)
#define USBHS_USBSTS_FRI_MASK USB_USBSTS_FRI_MASK
#define USBHS_USBSTS_FRI_SHIFT USB_USBSTS_FRI_SHIFT
#define USBHS_USBSTS_FRI(x) USB_USBSTS_FRI(x)
#define USBHS_USBSTS_SEI_MASK USB_USBSTS_SEI_MASK
#define USBHS_USBSTS_SEI_SHIFT USB_USBSTS_SEI_SHIFT
#define USBHS_USBSTS_SEI(x) USB_USBSTS_SEI(x)
#define USBHS_USBSTS_AAI_MASK USB_USBSTS_AAI_MASK
#define USBHS_USBSTS_AAI_SHIFT USB_USBSTS_AAI_SHIFT
#define USBHS_USBSTS_AAI(x) USB_USBSTS_AAI(x)
#define USBHS_USBSTS_URI_MASK USB_USBSTS_URI_MASK
#define USBHS_USBSTS_URI_SHIFT USB_USBSTS_URI_SHIFT
#define USBHS_USBSTS_URI(x) USB_USBSTS_URI(x)
#define USBHS_USBSTS_SRI_MASK USB_USBSTS_SRI_MASK
#define USBHS_USBSTS_SRI_SHIFT USB_USBSTS_SRI_SHIFT
#define USBHS_USBSTS_SRI(x) USB_USBSTS_SRI(x)
#define USBHS_USBSTS_SLI_MASK USB_USBSTS_SLI_MASK
#define USBHS_USBSTS_SLI_SHIFT USB_USBSTS_SLI_SHIFT
#define USBHS_USBSTS_SLI(x) USB_USBSTS_SLI(x)
#define USBHS_USBSTS_ULPII_MASK USB_USBSTS_ULPII_MASK
#define USBHS_USBSTS_ULPII_SHIFT USB_USBSTS_ULPII_SHIFT
#define USBHS_USBSTS_ULPII(x) USB_USBSTS_ULPII(x)
#define USBHS_USBSTS_HCH_MASK USB_USBSTS_HCH_MASK
#define USBHS_USBSTS_HCH_SHIFT USB_USBSTS_HCH_SHIFT
#define USBHS_USBSTS_HCH(x) USB_USBSTS_HCH(x)
#define USBHS_USBSTS_RCL_MASK USB_USBSTS_RCL_MASK
#define USBHS_USBSTS_RCL_SHIFT USB_USBSTS_RCL_SHIFT
#define USBHS_USBSTS_RCL(x) USB_USBSTS_RCL(x)
#define USBHS_USBSTS_PS_MASK USB_USBSTS_PS_MASK
#define USBHS_USBSTS_PS_SHIFT USB_USBSTS_PS_SHIFT
#define USBHS_USBSTS_PS(x) USB_USBSTS_PS(x)
#define USBHS_USBSTS_AS_MASK USB_USBSTS_AS_MASK
#define USBHS_USBSTS_AS_SHIFT USB_USBSTS_AS_SHIFT
#define USBHS_USBSTS_AS(x) USB_USBSTS_AS(x)
#define USBHS_USBSTS_NAKI_MASK USB_USBSTS_NAKI_MASK
#define USBHS_USBSTS_NAKI_SHIFT USB_USBSTS_NAKI_SHIFT
#define USBHS_USBSTS_NAKI(x) USB_USBSTS_NAKI(x)
#define USBHS_USBSTS_TI0_MASK USB_USBSTS_TI0_MASK
#define USBHS_USBSTS_TI0_SHIFT USB_USBSTS_TI0_SHIFT
#define USBHS_USBSTS_TI0(x) USB_USBSTS_TI0(x)
#define USBHS_USBSTS_TI1_MASK USB_USBSTS_TI1_MASK
#define USBHS_USBSTS_TI1_SHIFT USB_USBSTS_TI1_SHIFT
#define USBHS_USBSTS_TI1(x) USB_USBSTS_TI1(x)
#define USBHS_USBINTR_UE_MASK USB_USBINTR_UE_MASK
#define USBHS_USBINTR_UE_SHIFT USB_USBINTR_UE_SHIFT
#define USBHS_USBINTR_UE(x) USB_USBINTR_UE(x)
#define USBHS_USBINTR_UEE_MASK USB_USBINTR_UEE_MASK
#define USBHS_USBINTR_UEE_SHIFT USB_USBINTR_UEE_SHIFT
#define USBHS_USBINTR_UEE(x) USB_USBINTR_UEE(x)
#define USBHS_USBINTR_PCE_MASK USB_USBINTR_PCE_MASK
#define USBHS_USBINTR_PCE_SHIFT USB_USBINTR_PCE_SHIFT
#define USBHS_USBINTR_PCE(x) USB_USBINTR_PCE(x)
#define USBHS_USBINTR_FRE_MASK USB_USBINTR_FRE_MASK
#define USBHS_USBINTR_FRE_SHIFT USB_USBINTR_FRE_SHIFT
#define USBHS_USBINTR_FRE(x) USB_USBINTR_FRE(x)
#define USBHS_USBINTR_SEE_MASK USB_USBINTR_SEE_MASK
#define USBHS_USBINTR_SEE_SHIFT USB_USBINTR_SEE_SHIFT
#define USBHS_USBINTR_SEE(x) USB_USBINTR_SEE(x)
#define USBHS_USBINTR_AAE_MASK USB_USBINTR_AAE_MASK
#define USBHS_USBINTR_AAE_SHIFT USB_USBINTR_AAE_SHIFT
#define USBHS_USBINTR_AAE(x) USB_USBINTR_AAE(x)
#define USBHS_USBINTR_URE_MASK USB_USBINTR_URE_MASK
#define USBHS_USBINTR_URE_SHIFT USB_USBINTR_URE_SHIFT
#define USBHS_USBINTR_URE(x) USB_USBINTR_URE(x)
#define USBHS_USBINTR_SRE_MASK USB_USBINTR_SRE_MASK
#define USBHS_USBINTR_SRE_SHIFT USB_USBINTR_SRE_SHIFT
#define USBHS_USBINTR_SRE(x) USB_USBINTR_SRE(x)
#define USBHS_USBINTR_SLE_MASK USB_USBINTR_SLE_MASK
#define USBHS_USBINTR_SLE_SHIFT USB_USBINTR_SLE_SHIFT
#define USBHS_USBINTR_SLE(x) USB_USBINTR_SLE(x)
#define USBHS_USBINTR_ULPIE_MASK USB_USBINTR_ULPIE_MASK
#define USBHS_USBINTR_ULPIE_SHIFT USB_USBINTR_ULPIE_SHIFT
#define USBHS_USBINTR_ULPIE(x) USB_USBINTR_ULPIE(x)
#define USBHS_USBINTR_NAKE_MASK USB_USBINTR_NAKE_MASK
#define USBHS_USBINTR_NAKE_SHIFT USB_USBINTR_NAKE_SHIFT
#define USBHS_USBINTR_NAKE(x) USB_USBINTR_NAKE(x)
#define USBHS_USBINTR_UAIE_MASK USB_USBINTR_UAIE_MASK
#define USBHS_USBINTR_UAIE_SHIFT USB_USBINTR_UAIE_SHIFT
#define USBHS_USBINTR_UAIE(x) USB_USBINTR_UAIE(x)
#define USBHS_USBINTR_UPIE_MASK USB_USBINTR_UPIE_MASK
#define USBHS_USBINTR_UPIE_SHIFT USB_USBINTR_UPIE_SHIFT
#define USBHS_USBINTR_UPIE(x) USB_USBINTR_UPIE(x)
#define USBHS_USBINTR_TIE0_MASK USB_USBINTR_TIE0_MASK
#define USBHS_USBINTR_TIE0_SHIFT USB_USBINTR_TIE0_SHIFT
#define USBHS_USBINTR_TIE0(x) USB_USBINTR_TIE0(x)
#define USBHS_USBINTR_TIE1_MASK USB_USBINTR_TIE1_MASK
#define USBHS_USBINTR_TIE1_SHIFT USB_USBINTR_TIE1_SHIFT
#define USBHS_USBINTR_TIE1(x) USB_USBINTR_TIE1(x)
#define USBHS_FRINDEX_FRINDEX_MASK USB_FRINDEX_FRINDEX_MASK
#define USBHS_FRINDEX_FRINDEX_SHIFT USB_FRINDEX_FRINDEX_SHIFT
#define USBHS_FRINDEX_FRINDEX(x) USB_FRINDEX_FRINDEX(x)
#define USBHS_DEVICEADDR_USBADRA_MASK USB_DEVICEADDR_USBADRA_MASK
#define USBHS_DEVICEADDR_USBADRA_SHIFT USB_DEVICEADDR_USBADRA_SHIFT
#define USBHS_DEVICEADDR_USBADRA(x) USB_DEVICEADDR_USBADRA(x)
#define USBHS_DEVICEADDR_USBADR_MASK USB_DEVICEADDR_USBADR_MASK
#define USBHS_DEVICEADDR_USBADR_SHIFT USB_DEVICEADDR_USBADR_SHIFT
#define USBHS_DEVICEADDR_USBADR(x) USB_DEVICEADDR_USBADR(x)
#define USBHS_PERIODICLISTBASE_PERBASE_MASK USB_PERIODICLISTBASE_BASEADR_MASK
#define USBHS_PERIODICLISTBASE_PERBASE_SHIFT USB_PERIODICLISTBASE_BASEADR_SHIFT
#define USBHS_PERIODICLISTBASE_PERBASE(x) USB_PERIODICLISTBASE_BASEADR(x)
#define USBHS_ASYNCLISTADDR_ASYBASE_MASK USB_ASYNCLISTADDR_ASYBASE_MASK
#define USBHS_ASYNCLISTADDR_ASYBASE_SHIFT USB_ASYNCLISTADDR_ASYBASE_SHIFT
#define USBHS_ASYNCLISTADDR_ASYBASE(x) USB_ASYNCLISTADDR_ASYBASE(x)
#define USBHS_EPLISTADDR_EPBASE_MASK USB_ENDPTLISTADDR_EPBASE_MASK
#define USBHS_EPLISTADDR_EPBASE_SHIFT USB_ENDPTLISTADDR_EPBASE_SHIFT
#define USBHS_EPLISTADDR_EPBASE(x) USB_ENDPTLISTADDR_EPBASE(x)
#define USBHS_BURSTSIZE_RXPBURST_MASK USB_BURSTSIZE_RXPBURST_MASK
#define USBHS_BURSTSIZE_RXPBURST_SHIFT USB_BURSTSIZE_RXPBURST_SHIFT
#define USBHS_BURSTSIZE_RXPBURST(x) USB_BURSTSIZE_RXPBURST(x)
#define USBHS_BURSTSIZE_TXPBURST_MASK USB_BURSTSIZE_TXPBURST_MASK
#define USBHS_BURSTSIZE_TXPBURST_SHIFT USB_BURSTSIZE_TXPBURST_SHIFT
#define USBHS_BURSTSIZE_TXPBURST(x) USB_BURSTSIZE_TXPBURST(x)
#define USBHS_TXFILLTUNING_TXSCHOH_MASK USB_TXFILLTUNING_TXSCHOH_MASK
#define USBHS_TXFILLTUNING_TXSCHOH_SHIFT USB_TXFILLTUNING_TXSCHOH_SHIFT
#define USBHS_TXFILLTUNING_TXSCHOH(x) USB_TXFILLTUNING_TXSCHOH(x)
#define USBHS_TXFILLTUNING_TXSCHHEALTH_MASK USB_TXFILLTUNING_TXSCHHEALTH_MASK
#define USBHS_TXFILLTUNING_TXSCHHEALTH_SHIFT USB_TXFILLTUNING_TXSCHHEALTH_SHIFT
#define USBHS_TXFILLTUNING_TXSCHHEALTH(x) USB_TXFILLTUNING_TXSCHHEALTH(x)
#define USBHS_TXFILLTUNING_TXFIFOTHRES_MASK USB_TXFILLTUNING_TXFIFOTHRES_MASK
#define USBHS_TXFILLTUNING_TXFIFOTHRES_SHIFT USB_TXFILLTUNING_TXFIFOTHRES_SHIFT
#define USBHS_TXFILLTUNING_TXFIFOTHRES(x) USB_TXFILLTUNING_TXFIFOTHRES(x)
#define USBHS_ENDPTNAK_EPRN_MASK USB_ENDPTNAK_EPRN_MASK
#define USBHS_ENDPTNAK_EPRN_SHIFT USB_ENDPTNAK_EPRN_SHIFT
#define USBHS_ENDPTNAK_EPRN(x) USB_ENDPTNAK_EPRN(x)
#define USBHS_ENDPTNAK_EPTN_MASK USB_ENDPTNAK_EPTN_MASK
#define USBHS_ENDPTNAK_EPTN_SHIFT USB_ENDPTNAK_EPTN_SHIFT
#define USBHS_ENDPTNAK_EPTN(x) USB_ENDPTNAK_EPTN(x)
#define USBHS_ENDPTNAKEN_EPRNE_MASK USB_ENDPTNAKEN_EPRNE_MASK
#define USBHS_ENDPTNAKEN_EPRNE_SHIFT USB_ENDPTNAKEN_EPRNE_SHIFT
#define USBHS_ENDPTNAKEN_EPRNE(x) USB_ENDPTNAKEN_EPRNE(x)
#define USBHS_ENDPTNAKEN_EPTNE_MASK USB_ENDPTNAKEN_EPTNE_MASK
#define USBHS_ENDPTNAKEN_EPTNE_SHIFT USB_ENDPTNAKEN_EPTNE_SHIFT
#define USBHS_ENDPTNAKEN_EPTNE(x) USB_ENDPTNAKEN_EPTNE(x)
#define USBHS_CONFIGFLAG_CF_MASK USB_CONFIGFLAG_CF_MASK
#define USBHS_CONFIGFLAG_CF_SHIFT USB_CONFIGFLAG_CF_SHIFT
#define USBHS_CONFIGFLAG_CF(x) USB_CONFIGFLAG_CF(x)
#define USBHS_PORTSC1_CCS_MASK USB_PORTSC1_CCS_MASK
#define USBHS_PORTSC1_CCS_SHIFT USB_PORTSC1_CCS_SHIFT
#define USBHS_PORTSC1_CCS(x) USB_PORTSC1_CCS(x)
#define USBHS_PORTSC1_CSC_MASK USB_PORTSC1_CSC_MASK
#define USBHS_PORTSC1_CSC_SHIFT USB_PORTSC1_CSC_SHIFT
#define USBHS_PORTSC1_CSC(x) USB_PORTSC1_CSC(x)
#define USBHS_PORTSC1_PE_MASK USB_PORTSC1_PE_MASK
#define USBHS_PORTSC1_PE_SHIFT USB_PORTSC1_PE_SHIFT
#define USBHS_PORTSC1_PE(x) USB_PORTSC1_PE(x)
#define USBHS_PORTSC1_PEC_MASK USB_PORTSC1_PEC_MASK
#define USBHS_PORTSC1_PEC_SHIFT USB_PORTSC1_PEC_SHIFT
#define USBHS_PORTSC1_PEC(x) USB_PORTSC1_PEC(x)
#define USBHS_PORTSC1_OCA_MASK USB_PORTSC1_OCA_MASK
#define USBHS_PORTSC1_OCA_SHIFT USB_PORTSC1_OCA_SHIFT
#define USBHS_PORTSC1_OCA(x) USB_PORTSC1_OCA(x)
#define USBHS_PORTSC1_OCC_MASK USB_PORTSC1_OCC_MASK
#define USBHS_PORTSC1_OCC_SHIFT USB_PORTSC1_OCC_SHIFT
#define USBHS_PORTSC1_OCC(x) USB_PORTSC1_OCC(x)
#define USBHS_PORTSC1_FPR_MASK USB_PORTSC1_FPR_MASK
#define USBHS_PORTSC1_FPR_SHIFT USB_PORTSC1_FPR_SHIFT
#define USBHS_PORTSC1_FPR(x) USB_PORTSC1_FPR(x)
#define USBHS_PORTSC1_SUSP_MASK USB_PORTSC1_SUSP_MASK
#define USBHS_PORTSC1_SUSP_SHIFT USB_PORTSC1_SUSP_SHIFT
#define USBHS_PORTSC1_SUSP(x) USB_PORTSC1_SUSP(x)
#define USBHS_PORTSC1_PR_MASK USB_PORTSC1_PR_MASK
#define USBHS_PORTSC1_PR_SHIFT USB_PORTSC1_PR_SHIFT
#define USBHS_PORTSC1_PR(x) USB_PORTSC1_PR(x)
#define USBHS_PORTSC1_HSP_MASK USB_PORTSC1_HSP_MASK
#define USBHS_PORTSC1_HSP_SHIFT USB_PORTSC1_HSP_SHIFT
#define USBHS_PORTSC1_HSP(x) USB_PORTSC1_HSP(x)
#define USBHS_PORTSC1_LS_MASK USB_PORTSC1_LS_MASK
#define USBHS_PORTSC1_LS_SHIFT USB_PORTSC1_LS_SHIFT
#define USBHS_PORTSC1_LS(x) USB_PORTSC1_LS(x)
#define USBHS_PORTSC1_PP_MASK USB_PORTSC1_PP_MASK
#define USBHS_PORTSC1_PP_SHIFT USB_PORTSC1_PP_SHIFT
#define USBHS_PORTSC1_PP(x) USB_PORTSC1_PP(x)
#define USBHS_PORTSC1_PO_MASK USB_PORTSC1_PO_MASK
#define USBHS_PORTSC1_PO_SHIFT USB_PORTSC1_PO_SHIFT
#define USBHS_PORTSC1_PO(x) USB_PORTSC1_PO(x)
#define USBHS_PORTSC1_PIC_MASK USB_PORTSC1_PIC_MASK
#define USBHS_PORTSC1_PIC_SHIFT USB_PORTSC1_PIC_SHIFT
#define USBHS_PORTSC1_PIC(x) USB_PORTSC1_PIC(x)
#define USBHS_PORTSC1_PTC_MASK USB_PORTSC1_PTC_MASK
#define USBHS_PORTSC1_PTC_SHIFT USB_PORTSC1_PTC_SHIFT
#define USBHS_PORTSC1_PTC(x) USB_PORTSC1_PTC(x)
#define USBHS_PORTSC1_WKCN_MASK USB_PORTSC1_WKCN_MASK
#define USBHS_PORTSC1_WKCN_SHIFT USB_PORTSC1_WKCN_SHIFT
#define USBHS_PORTSC1_WKCN(x) USB_PORTSC1_WKCN(x)
#define USBHS_PORTSC1_WKDS_MASK USB_PORTSC1_WKDC_MASK
#define USBHS_PORTSC1_WKDS_SHIFT USB_PORTSC1_WKDC_SHIFT
#define USBHS_PORTSC1_WKDS(x) USB_PORTSC1_WKDC(x)
#define USBHS_PORTSC1_WKOC_MASK USB_PORTSC1_WKOC_MASK
#define USBHS_PORTSC1_WKOC_SHIFT USB_PORTSC1_WKOC_SHIFT
#define USBHS_PORTSC1_WKOC(x) USB_PORTSC1_WKOC(x)
#define USBHS_PORTSC1_PHCD_MASK USB_PORTSC1_PHCD_MASK
#define USBHS_PORTSC1_PHCD_SHIFT USB_PORTSC1_PHCD_SHIFT
#define USBHS_PORTSC1_PHCD(x) USB_PORTSC1_PHCD(x)
#define USBHS_PORTSC1_PFSC_MASK USB_PORTSC1_PFSC_MASK
#define USBHS_PORTSC1_PFSC_SHIFT USB_PORTSC1_PFSC_SHIFT
#define USBHS_PORTSC1_PFSC(x) USB_PORTSC1_PFSC(x)
#define USBHS_PORTSC1_PTS2_MASK USB_PORTSC1_PTS_2_MASK
#define USBHS_PORTSC1_PTS2_SHIFT USB_PORTSC1_PTS_2_SHIFT
#define USBHS_PORTSC1_PTS2(x) USB_PORTSC1_PTS_2(x)
#define USBHS_PORTSC1_PSPD_MASK USB_PORTSC1_PSPD_MASK
#define USBHS_PORTSC1_PSPD_SHIFT USB_PORTSC1_PSPD_SHIFT
#define USBHS_PORTSC1_PSPD(x) USB_PORTSC1_PSPD(x)
#define USBHS_PORTSC1_PTW_MASK USB_PORTSC1_PTW_MASK
#define USBHS_PORTSC1_PTW_SHIFT USB_PORTSC1_PTW_SHIFT
#define USBHS_PORTSC1_PTW(x) USB_PORTSC1_PTW(x)
#define USBHS_PORTSC1_STS_MASK USB_PORTSC1_STS_MASK
#define USBHS_PORTSC1_STS_SHIFT USB_PORTSC1_STS_SHIFT
#define USBHS_PORTSC1_STS(x) USB_PORTSC1_STS(x)
#define USBHS_PORTSC1_PTS_MASK USB_PORTSC1_PTS_1_MASK
#define USBHS_PORTSC1_PTS_SHIFT USB_PORTSC1_PTS_1_SHIFT
#define USBHS_PORTSC1_PTS(x) USB_PORTSC1_PTS_1(x)
#define USBHS_OTGSC_VD_MASK USB_OTGSC_VD_MASK
#define USBHS_OTGSC_VD_SHIFT USB_OTGSC_VD_SHIFT
#define USBHS_OTGSC_VD(x) USB_OTGSC_VD(x)
#define USBHS_OTGSC_VC_MASK USB_OTGSC_VC_MASK
#define USBHS_OTGSC_VC_SHIFT USB_OTGSC_VC_SHIFT
#define USBHS_OTGSC_VC(x) USB_OTGSC_VC(x)
#define USBHS_OTGSC_OT_MASK USB_OTGSC_OT_MASK
#define USBHS_OTGSC_OT_SHIFT USB_OTGSC_OT_SHIFT
#define USBHS_OTGSC_OT(x) USB_OTGSC_OT(x)
#define USBHS_OTGSC_DP_MASK USB_OTGSC_DP_MASK
#define USBHS_OTGSC_DP_SHIFT USB_OTGSC_DP_SHIFT
#define USBHS_OTGSC_DP(x) USB_OTGSC_DP(x)
#define USBHS_OTGSC_IDPU_MASK USB_OTGSC_IDPU_MASK
#define USBHS_OTGSC_IDPU_SHIFT USB_OTGSC_IDPU_SHIFT
#define USBHS_OTGSC_IDPU(x) USB_OTGSC_IDPU(x)
#define USBHS_OTGSC_ID_MASK USB_OTGSC_ID_MASK
#define USBHS_OTGSC_ID_SHIFT USB_OTGSC_ID_SHIFT
#define USBHS_OTGSC_ID(x) USB_OTGSC_ID(x)
#define USBHS_OTGSC_AVV_MASK USB_OTGSC_AVV_MASK
#define USBHS_OTGSC_AVV_SHIFT USB_OTGSC_AVV_SHIFT
#define USBHS_OTGSC_AVV(x) USB_OTGSC_AVV(x)
#define USBHS_OTGSC_ASV_MASK USB_OTGSC_ASV_MASK
#define USBHS_OTGSC_ASV_SHIFT USB_OTGSC_ASV_SHIFT
#define USBHS_OTGSC_ASV(x) USB_OTGSC_ASV(x)
#define USBHS_OTGSC_BSV_MASK USB_OTGSC_BSV_MASK
#define USBHS_OTGSC_BSV_SHIFT USB_OTGSC_BSV_SHIFT
#define USBHS_OTGSC_BSV(x) USB_OTGSC_BSV(x)
#define USBHS_OTGSC_BSE_MASK USB_OTGSC_BSE_MASK
#define USBHS_OTGSC_BSE_SHIFT USB_OTGSC_BSE_SHIFT
#define USBHS_OTGSC_BSE(x) USB_OTGSC_BSE(x)
#define USBHS_OTGSC_MST_MASK USB_OTGSC_TOG_1MS_MASK
#define USBHS_OTGSC_MST_SHIFT USB_OTGSC_TOG_1MS_SHIFT
#define USBHS_OTGSC_MST(x) USB_OTGSC_TOG_1MS(x)
#define USBHS_OTGSC_DPS_MASK USB_OTGSC_DPS_MASK
#define USBHS_OTGSC_DPS_SHIFT USB_OTGSC_DPS_SHIFT
#define USBHS_OTGSC_DPS(x) USB_OTGSC_DPS(x)
#define USBHS_OTGSC_IDIS_MASK USB_OTGSC_IDIS_MASK
#define USBHS_OTGSC_IDIS_SHIFT USB_OTGSC_IDIS_SHIFT
#define USBHS_OTGSC_IDIS(x) USB_OTGSC_IDIS(x)
#define USBHS_OTGSC_AVVIS_MASK USB_OTGSC_AVVIS_MASK
#define USBHS_OTGSC_AVVIS_SHIFT USB_OTGSC_AVVIS_SHIFT
#define USBHS_OTGSC_AVVIS(x) USB_OTGSC_AVVIS(x)
#define USBHS_OTGSC_ASVIS_MASK USB_OTGSC_ASVIS_MASK
#define USBHS_OTGSC_ASVIS_SHIFT USB_OTGSC_ASVIS_SHIFT
#define USBHS_OTGSC_ASVIS(x) USB_OTGSC_ASVIS(x)
#define USBHS_OTGSC_BSVIS_MASK USB_OTGSC_BSVIS_MASK
#define USBHS_OTGSC_BSVIS_SHIFT USB_OTGSC_BSVIS_SHIFT
#define USBHS_OTGSC_BSVIS(x) USB_OTGSC_BSVIS(x)
#define USBHS_OTGSC_BSEIS_MASK USB_OTGSC_BSEIS_MASK
#define USBHS_OTGSC_BSEIS_SHIFT USB_OTGSC_BSEIS_SHIFT
#define USBHS_OTGSC_BSEIS(x) USB_OTGSC_BSEIS(x)
#define USBHS_OTGSC_MSS_MASK USB_OTGSC_STATUS_1MS_MASK
#define USBHS_OTGSC_MSS_SHIFT USB_OTGSC_STATUS_1MS_SHIFT
#define USBHS_OTGSC_MSS(x) USB_OTGSC_STATUS_1MS(x)
#define USBHS_OTGSC_DPIS_MASK USB_OTGSC_DPIS_MASK
#define USBHS_OTGSC_DPIS_SHIFT USB_OTGSC_DPIS_SHIFT
#define USBHS_OTGSC_DPIS(x) USB_OTGSC_DPIS(x)
#define USBHS_OTGSC_IDIE_MASK USB_OTGSC_IDIE_MASK
#define USBHS_OTGSC_IDIE_SHIFT USB_OTGSC_IDIE_SHIFT
#define USBHS_OTGSC_IDIE(x) USB_OTGSC_IDIE(x)
#define USBHS_OTGSC_AVVIE_MASK USB_OTGSC_AVVIE_MASK
#define USBHS_OTGSC_AVVIE_SHIFT USB_OTGSC_AVVIE_SHIFT
#define USBHS_OTGSC_AVVIE(x) USB_OTGSC_AVVIE(x)
#define USBHS_OTGSC_ASVIE_MASK USB_OTGSC_ASVIE_MASK
#define USBHS_OTGSC_ASVIE_SHIFT USB_OTGSC_ASVIE_SHIFT
#define USBHS_OTGSC_ASVIE(x) USB_OTGSC_ASVIE(x)
#define USBHS_OTGSC_BSVIE_MASK USB_OTGSC_BSVIE_MASK
#define USBHS_OTGSC_BSVIE_SHIFT USB_OTGSC_BSVIE_SHIFT
#define USBHS_OTGSC_BSVIE(x) USB_OTGSC_BSVIE(x)
#define USBHS_OTGSC_BSEIE_MASK USB_OTGSC_BSEIE_MASK
#define USBHS_OTGSC_BSEIE_SHIFT USB_OTGSC_BSEIE_SHIFT
#define USBHS_OTGSC_BSEIE(x) USB_OTGSC_BSEIE(x)
#define USBHS_OTGSC_MSE_MASK USB_OTGSC_EN_1MS_MASK
#define USBHS_OTGSC_MSE_SHIFT USB_OTGSC_EN_1MS_SHIFT
#define USBHS_OTGSC_MSE(x) USB_OTGSC_EN_1MS(x)
#define USBHS_OTGSC_DPIE_MASK USB_OTGSC_DPIE_MASK
#define USBHS_OTGSC_DPIE_SHIFT USB_OTGSC_DPIE_SHIFT
#define USBHS_OTGSC_DPIE(x) USB_OTGSC_DPIE(x)
#define USBHS_USBMODE_CM_MASK USB_USBMODE_CM_MASK
#define USBHS_USBMODE_CM_SHIFT USB_USBMODE_CM_SHIFT
#define USBHS_USBMODE_CM(x) USB_USBMODE_CM(x)
#define USBHS_USBMODE_ES_MASK USB_USBMODE_ES_MASK
#define USBHS_USBMODE_ES_SHIFT USB_USBMODE_ES_SHIFT
#define USBHS_USBMODE_ES(x) USB_USBMODE_ES(x)
#define USBHS_USBMODE_SLOM_MASK USB_USBMODE_SLOM_MASK
#define USBHS_USBMODE_SLOM_SHIFT USB_USBMODE_SLOM_SHIFT
#define USBHS_USBMODE_SLOM(x) USB_USBMODE_SLOM(x)
#define USBHS_USBMODE_SDIS_MASK USB_USBMODE_SDIS_MASK
#define USBHS_USBMODE_SDIS_SHIFT USB_USBMODE_SDIS_SHIFT
#define USBHS_USBMODE_SDIS(x) USB_USBMODE_SDIS(x)
#define USBHS_EPSETUPSR_EPSETUPSTAT_MASK USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_MASK
#define USBHS_EPSETUPSR_EPSETUPSTAT_SHIFT USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT_SHIFT
#define USBHS_EPSETUPSR_EPSETUPSTAT(x) USB_ENDPTSETUPSTAT_ENDPTSETUPSTAT(x)
#define USBHS_EPPRIME_PERB_MASK USB_ENDPTPRIME_PERB_MASK
#define USBHS_EPPRIME_PERB_SHIFT USB_ENDPTPRIME_PERB_SHIFT
#define USBHS_EPPRIME_PERB(x) USB_ENDPTPRIME_PERB(x)
#define USBHS_EPPRIME_PETB_MASK USB_ENDPTPRIME_PETB_MASK
#define USBHS_EPPRIME_PETB_SHIFT USB_ENDPTPRIME_PETB_SHIFT
#define USBHS_EPPRIME_PETB(x) USB_ENDPTPRIME_PETB(x)
#define USBHS_EPFLUSH_FERB_MASK USB_ENDPTFLUSH_FERB_MASK
#define USBHS_EPFLUSH_FERB_SHIFT USB_ENDPTFLUSH_FERB_SHIFT
#define USBHS_EPFLUSH_FERB(x) USB_ENDPTFLUSH_FERB(x)
#define USBHS_EPFLUSH_FETB_MASK USB_ENDPTFLUSH_FETB_MASK
#define USBHS_EPFLUSH_FETB_SHIFT USB_ENDPTFLUSH_FETB_SHIFT
#define USBHS_EPFLUSH_FETB(x) USB_ENDPTFLUSH_FETB(x)
#define USBHS_EPSR_ERBR_MASK USB_ENDPTSTAT_ERBR_MASK
#define USBHS_EPSR_ERBR_SHIFT USB_ENDPTSTAT_ERBR_SHIFT
#define USBHS_EPSR_ERBR(x) USB_ENDPTSTAT_ERBR(x)
#define USBHS_EPSR_ETBR_MASK USB_ENDPTSTAT_ETBR_MASK
#define USBHS_EPSR_ETBR_SHIFT USB_ENDPTSTAT_ETBR_SHIFT
#define USBHS_EPSR_ETBR(x) USB_ENDPTSTAT_ETBR(x)
#define USBHS_EPCOMPLETE_ERCE_MASK USB_ENDPTCOMPLETE_ERCE_MASK
#define USBHS_EPCOMPLETE_ERCE_SHIFT USB_ENDPTCOMPLETE_ERCE_SHIFT
#define USBHS_EPCOMPLETE_ERCE(x) USB_ENDPTCOMPLETE_ERCE(x)
#define USBHS_EPCOMPLETE_ETCE_MASK USB_ENDPTCOMPLETE_ETCE_MASK
#define USBHS_EPCOMPLETE_ETCE_SHIFT USB_ENDPTCOMPLETE_ETCE_SHIFT
#define USBHS_EPCOMPLETE_ETCE(x) USB_ENDPTCOMPLETE_ETCE(x)
#define USBHS_EPCR0_RXS_MASK USB_ENDPTCTRL0_RXS_MASK
#define USBHS_EPCR0_RXS_SHIFT USB_ENDPTCTRL0_RXS_SHIFT
#define USBHS_EPCR0_RXS(x) USB_ENDPTCTRL0_RXS(x)
#define USBHS_EPCR0_RXT_MASK USB_ENDPTCTRL0_RXT_MASK
#define USBHS_EPCR0_RXT_SHIFT USB_ENDPTCTRL0_RXT_SHIFT
#define USBHS_EPCR0_RXT(x) USB_ENDPTCTRL0_RXT(x)
#define USBHS_EPCR0_RXE_MASK USB_ENDPTCTRL0_RXE_MASK
#define USBHS_EPCR0_RXE_SHIFT USB_ENDPTCTRL0_RXE_SHIFT
#define USBHS_EPCR0_RXE(x) USB_ENDPTCTRL0_RXE(x)
#define USBHS_EPCR0_TXS_MASK USB_ENDPTCTRL0_TXS_MASK
#define USBHS_EPCR0_TXS_SHIFT USB_ENDPTCTRL0_TXS_SHIFT
#define USBHS_EPCR0_TXS(x) USB_ENDPTCTRL0_TXS(x)
#define USBHS_EPCR0_TXT_MASK USB_ENDPTCTRL0_TXT_MASK
#define USBHS_EPCR0_TXT_SHIFT USB_ENDPTCTRL0_TXT_SHIFT
#define USBHS_EPCR0_TXT(x) USB_ENDPTCTRL0_TXT(x)
#define USBHS_EPCR0_TXE_MASK USB_ENDPTCTRL0_TXE_MASK
#define USBHS_EPCR0_TXE_SHIFT USB_ENDPTCTRL0_TXE_SHIFT
#define USBHS_EPCR0_TXE(x) USB_ENDPTCTRL0_TXE(x)
#define USBHS_EPCR_RXS_MASK USB_ENDPTCTRL_RXS_MASK
#define USBHS_EPCR_RXS_SHIFT USB_ENDPTCTRL_RXS_SHIFT
#define USBHS_EPCR_RXS(x) USB_ENDPTCTRL_RXS(x)
#define USBHS_EPCR_RXD_MASK USB_ENDPTCTRL_RXD_MASK
#define USBHS_EPCR_RXD_SHIFT USB_ENDPTCTRL_RXD_SHIFT
#define USBHS_EPCR_RXD(x) USB_ENDPTCTRL_RXD(x)
#define USBHS_EPCR_RXT_MASK USB_ENDPTCTRL_RXT_MASK
#define USBHS_EPCR_RXT_SHIFT USB_ENDPTCTRL_RXT_SHIFT
#define USBHS_EPCR_RXT(x) USB_ENDPTCTRL_RXT(x)
#define USBHS_EPCR_RXI_MASK USB_ENDPTCTRL_RXI_MASK
#define USBHS_EPCR_RXI_SHIFT USB_ENDPTCTRL_RXI_SHIFT
#define USBHS_EPCR_RXI(x) USB_ENDPTCTRL_RXI(x)
#define USBHS_EPCR_RXR_MASK USB_ENDPTCTRL_RXR_MASK
#define USBHS_EPCR_RXR_SHIFT USB_ENDPTCTRL_RXR_SHIFT
#define USBHS_EPCR_RXR(x) USB_ENDPTCTRL_RXR(x)
#define USBHS_EPCR_RXE_MASK USB_ENDPTCTRL_RXE_MASK
#define USBHS_EPCR_RXE_SHIFT USB_ENDPTCTRL_RXE_SHIFT
#define USBHS_EPCR_RXE(x) USB_ENDPTCTRL_RXE(x)
#define USBHS_EPCR_TXS_MASK USB_ENDPTCTRL_TXS_MASK
#define USBHS_EPCR_TXS_SHIFT USB_ENDPTCTRL_TXS_SHIFT
#define USBHS_EPCR_TXS(x) USB_ENDPTCTRL_TXS(x)
#define USBHS_EPCR_TXD_MASK USB_ENDPTCTRL_TXD_MASK
#define USBHS_EPCR_TXD_SHIFT USB_ENDPTCTRL_TXD_SHIFT
#define USBHS_EPCR_TXD(x) USB_ENDPTCTRL_TXD(x)
#define USBHS_EPCR_TXT_MASK USB_ENDPTCTRL_TXT_MASK
#define USBHS_EPCR_TXT_SHIFT USB_ENDPTCTRL_TXT_SHIFT
#define USBHS_EPCR_TXT(x) USB_ENDPTCTRL_TXT(x)
#define USBHS_EPCR_TXI_MASK USB_ENDPTCTRL_TXI_MASK
#define USBHS_EPCR_TXI_SHIFT USB_ENDPTCTRL_TXI_SHIFT
#define USBHS_EPCR_TXI(x) USB_ENDPTCTRL_TXI(x)
#define USBHS_EPCR_TXR_MASK USB_ENDPTCTRL_TXR_MASK
#define USBHS_EPCR_TXR_SHIFT USB_ENDPTCTRL_TXR_SHIFT
#define USBHS_EPCR_TXR(x) USB_ENDPTCTRL_TXR(x)
#define USBHS_EPCR_TXE_MASK USB_ENDPTCTRL_TXE_MASK
#define USBHS_EPCR_TXE_SHIFT USB_ENDPTCTRL_TXE_SHIFT
#define USBHS_EPCR_TXE(x) USB_ENDPTCTRL_TXE(x)
#define USBHS_EPCR_COUNT USB_ENDPTCTRL_COUNT
#define USBHS_Type USB_Type
#define USBHS_BASE_ADDRS { USB_OTG1_BASE, USB_OTG2_BASE }
#define USBHS_IRQS { USB_OTG1_IRQn, USB_OTG2_IRQn }
#define USBHS_IRQHandler USB_OTG1_IRQHandler
/*!
* @}
*/ /* end of group USB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USBHSDCD Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USBHSDCD_Peripheral_Access_Layer USBHSDCD Peripheral Access Layer
* @{
*/
/** USBHSDCD - Register Layout Typedef */
typedef struct {
__IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
__IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
__I uint32_t STATUS; /**< Status register, offset: 0x8 */
__IO uint32_t SIGNAL_OVERRIDE; /**< Signal Override Register, offset: 0xC */
__IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
__IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
union { /* offset: 0x18 */
__IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
__IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
};
} USBHSDCD_Type;
/* ----------------------------------------------------------------------------
-- USBHSDCD Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USBHSDCD_Register_Masks USBHSDCD Register Masks
* @{
*/
/*! @name CONTROL - Control register */
/*! @{ */
#define USBHSDCD_CONTROL_IACK_MASK (0x1U)
#define USBHSDCD_CONTROL_IACK_SHIFT (0U)
/*! IACK - Interrupt Acknowledge
* 0b0..Do not clear the interrupt.
* 0b1..Clear the IF bit (interrupt flag).
*/
#define USBHSDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IACK_SHIFT)) & USBHSDCD_CONTROL_IACK_MASK)
#define USBHSDCD_CONTROL_IF_MASK (0x100U)
#define USBHSDCD_CONTROL_IF_SHIFT (8U)
/*! IF - Interrupt Flag
* 0b0..No interrupt is pending.
* 0b1..An interrupt is pending.
*/
#define USBHSDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IF_SHIFT)) & USBHSDCD_CONTROL_IF_MASK)
#define USBHSDCD_CONTROL_IE_MASK (0x10000U)
#define USBHSDCD_CONTROL_IE_SHIFT (16U)
/*! IE - Interrupt Enable
* 0b0..Disable interrupts to the system.
* 0b1..Enable interrupts to the system.
*/
#define USBHSDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_IE_SHIFT)) & USBHSDCD_CONTROL_IE_MASK)
#define USBHSDCD_CONTROL_BC12_MASK (0x20000U)
#define USBHSDCD_CONTROL_BC12_SHIFT (17U)
/*! BC12 - BC12
* 0b0..Compatible with BC1.1 (default)
* 0b1..Compatible with BC1.2
*/
#define USBHSDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_BC12_SHIFT)) & USBHSDCD_CONTROL_BC12_MASK)
#define USBHSDCD_CONTROL_START_MASK (0x1000000U)
#define USBHSDCD_CONTROL_START_SHIFT (24U)
/*! START - Start Change Detection Sequence
* 0b0..Do not start the sequence. Writes of this value have no effect.
* 0b1..Initiate the charger detection sequence. If the sequence is already running, writes of this value have no effect.
*/
#define USBHSDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_START_SHIFT)) & USBHSDCD_CONTROL_START_MASK)
#define USBHSDCD_CONTROL_SR_MASK (0x2000000U)
#define USBHSDCD_CONTROL_SR_SHIFT (25U)
/*! SR - Software Reset
* 0b0..Do not perform a software reset.
* 0b1..Perform a software reset.
*/
#define USBHSDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CONTROL_SR_SHIFT)) & USBHSDCD_CONTROL_SR_MASK)
/*! @} */
/*! @name CLOCK - Clock register */
/*! @{ */
#define USBHSDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
#define USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
/*! CLOCK_UNIT - Unit of Measurement Encoding for Clock Speed
* 0b0..kHz Speed (between 1 kHz and 1023 kHz)
* 0b1..MHz Speed (between 1 MHz and 1023 MHz)
*/
#define USBHSDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBHSDCD_CLOCK_CLOCK_UNIT_MASK)
#define USBHSDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
#define USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
/*! CLOCK_SPEED - Numerical Value of Clock Speed in Binary
*/
#define USBHSDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBHSDCD_CLOCK_CLOCK_SPEED_MASK)
/*! @} */
/*! @name STATUS - Status register */
/*! @{ */
#define USBHSDCD_STATUS_SEQ_RES_MASK (0x30000U)
#define USBHSDCD_STATUS_SEQ_RES_SHIFT (16U)
/*! SEQ_RES - Charger Detection Sequence Results
* 0b00..No results to report.
* 0b01..Attached to an SDP. Must comply with USB 2.0 by drawing only 2.5 mA (max) until connected.
* 0b10..Attached to a charging port. The exact meaning depends on bit 18 (value 0: Attached to either a CDP or a
* DCP. The charger type detection has not completed. value 1: Attached to a CDP. The charger type
* detection has completed.)
* 0b11..Attached to a DCP.
*/
#define USBHSDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_RES_SHIFT)) & USBHSDCD_STATUS_SEQ_RES_MASK)
#define USBHSDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
#define USBHSDCD_STATUS_SEQ_STAT_SHIFT (18U)
/*! SEQ_STAT - Charger Detection Sequence Status
* 0b00..The module is either not enabled, or the module is enabled but the data pins have not yet been detected.
* 0b01..Data pin contact detection is complete.
* 0b10..Charging port detection is complete.
* 0b11..Charger type detection is complete.
*/
#define USBHSDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_SEQ_STAT_SHIFT)) & USBHSDCD_STATUS_SEQ_STAT_MASK)
#define USBHSDCD_STATUS_ERR_MASK (0x100000U)
#define USBHSDCD_STATUS_ERR_SHIFT (20U)
/*! ERR - Error Flag
* 0b0..No sequence errors.
* 0b1..Error in the detection sequence. See the SEQ_STAT field to determine the phase in which the error occurred.
*/
#define USBHSDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ERR_SHIFT)) & USBHSDCD_STATUS_ERR_MASK)
#define USBHSDCD_STATUS_TO_MASK (0x200000U)
#define USBHSDCD_STATUS_TO_SHIFT (21U)
/*! TO - Timeout Flag
* 0b0..The detection sequence has not been running for over 1s.
* 0b1..It has been over 1 s since the data pin contact was detected and debounced.
*/
#define USBHSDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_TO_SHIFT)) & USBHSDCD_STATUS_TO_MASK)
#define USBHSDCD_STATUS_ACTIVE_MASK (0x400000U)
#define USBHSDCD_STATUS_ACTIVE_SHIFT (22U)
/*! ACTIVE - Active Status Indicator
* 0b0..The sequence is not running.
* 0b1..The sequence is running.
*/
#define USBHSDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_STATUS_ACTIVE_SHIFT)) & USBHSDCD_STATUS_ACTIVE_MASK)
/*! @} */
/*! @name SIGNAL_OVERRIDE - Signal Override Register */
/*! @{ */
#define USBHSDCD_SIGNAL_OVERRIDE_PS_MASK (0x3U)
#define USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT (0U)
/*! PS - Phase Selection
* 0b00..No overrides. Bit field must remain at this value during normal USB data communication to prevent
* unexpected conditions on USB_DP and USB_DM pins. (Default)
* 0b01..Reserved, not for customer use.
* 0b10..Enables VDP_SRC voltage source for the USB_DP pin and IDM_SINK current source for the USB_DM pin.
* 0b11..Reserved, not for customer use.
*/
#define USBHSDCD_SIGNAL_OVERRIDE_PS(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_SIGNAL_OVERRIDE_PS_SHIFT)) & USBHSDCD_SIGNAL_OVERRIDE_PS_MASK)
/*! @} */
/*! @name TIMER0 - TIMER0 register */
/*! @{ */
#define USBHSDCD_TIMER0_TUNITCON_MASK (0xFFFU)
#define USBHSDCD_TIMER0_TUNITCON_SHIFT (0U)
/*! TUNITCON - Unit Connection Timer Elapse (in ms)
*/
#define USBHSDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TUNITCON_SHIFT)) & USBHSDCD_TIMER0_TUNITCON_MASK)
#define USBHSDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
#define USBHSDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
/*! TSEQ_INIT - Sequence Initiation Time
* 0b0000000000-0b1111111111..0ms - 1023ms
*/
#define USBHSDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBHSDCD_TIMER0_TSEQ_INIT_MASK)
/*! @} */
/*! @name TIMER1 - TIMER1 register */
/*! @{ */
#define USBHSDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
#define USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
/*! TVDPSRC_ON - Time Period Comparator Enabled
* 0b0000000001-0b1111111111..1ms - 1023ms
*/
#define USBHSDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBHSDCD_TIMER1_TVDPSRC_ON_MASK)
#define USBHSDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
#define USBHSDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
/*! TDCD_DBNC - Time Period to Debounce D+ Signal
* 0b0000000001-0b1111111111..1ms - 1023ms
*/
#define USBHSDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBHSDCD_TIMER1_TDCD_DBNC_MASK)
/*! @} */
/*! @name TIMER2_BC11 - TIMER2_BC11 register */
/*! @{ */
#define USBHSDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
#define USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
/*! CHECK_DM - Time Before Check of D- Line
* 0b0001-0b1111..1ms - 15ms
*/
#define USBHSDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBHSDCD_TIMER2_BC11_CHECK_DM_MASK)
#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
/*! TVDPSRC_CON - Time Period Before Enabling D+ Pullup
* 0b0000000001-0b1111111111..1ms - 1023ms
*/
#define USBHSDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBHSDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
/*! @} */
/*! @name TIMER2_BC12 - TIMER2_BC12 register */
/*! @{ */
#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
/*! TVDMSRC_ON - TVDMSRC_ON
* 0b0000000000-0b0000101000..0ms - 40ms
*/
#define USBHSDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBHSDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
/*! TWAIT_AFTER_PRD - TWAIT_AFTER_PRD
* 0b0000000001-0b1111111111..1ms - 1023ms
*/
#define USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBHSDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
/*! @} */
/*!
* @}
*/ /* end of group USBHSDCD_Register_Masks */
/* USBHSDCD - Peripheral instance base addresses */
/** Peripheral USBHSDCD1 base address */
#define USBHSDCD1_BASE (0x40434800u)
/** Peripheral USBHSDCD1 base pointer */
#define USBHSDCD1 ((USBHSDCD_Type *)USBHSDCD1_BASE)
/** Peripheral USBHSDCD2 base address */
#define USBHSDCD2_BASE (0x40438800u)
/** Peripheral USBHSDCD2 base pointer */
#define USBHSDCD2 ((USBHSDCD_Type *)USBHSDCD2_BASE)
/** Array initializer of USBHSDCD peripheral base addresses */
#define USBHSDCD_BASE_ADDRS { 0u, USBHSDCD1_BASE, USBHSDCD2_BASE }
/** Array initializer of USBHSDCD peripheral base pointers */
#define USBHSDCD_BASE_PTRS { (USBHSDCD_Type *)0u, USBHSDCD1, USBHSDCD2 }
/*!
* @}
*/ /* end of group USBHSDCD_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USBNC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USBNC_Peripheral_Access_Layer USBNC Peripheral Access Layer
* @{
*/
/** USBNC - Register Layout Typedef */
typedef struct {
__IO uint32_t CTRL1; /**< USB OTG Control 1 Register, offset: 0x0 */
__IO uint32_t CTRL2; /**< USB OTG Control 2 Register, offset: 0x4 */
uint8_t RESERVED_0[8];
__IO uint32_t HSIC_CTRL; /**< USB Host HSIC Control Register, offset: 0x10 */
} USBNC_Type;
/* ----------------------------------------------------------------------------
-- USBNC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USBNC_Register_Masks USBNC Register Masks
* @{
*/
/*! @name CTRL1 - USB OTG Control 1 Register */
/*! @{ */
#define USBNC_CTRL1_OVER_CUR_DIS_MASK (0x80U)
#define USBNC_CTRL1_OVER_CUR_DIS_SHIFT (7U)
/*! OVER_CUR_DIS - OVER_CUR_DIS
* 0b1..Disables overcurrent detection
* 0b0..Enables overcurrent detection
*/
#define USBNC_CTRL1_OVER_CUR_DIS(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_DIS_SHIFT)) & USBNC_CTRL1_OVER_CUR_DIS_MASK)
#define USBNC_CTRL1_OVER_CUR_POL_MASK (0x100U)
#define USBNC_CTRL1_OVER_CUR_POL_SHIFT (8U)
/*! OVER_CUR_POL - OVER_CUR_POL
* 0b1..Low active (low on this signal represents an overcurrent condition)
* 0b0..High active (high on this signal represents an overcurrent condition)
*/
#define USBNC_CTRL1_OVER_CUR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_OVER_CUR_POL_SHIFT)) & USBNC_CTRL1_OVER_CUR_POL_MASK)
#define USBNC_CTRL1_PWR_POL_MASK (0x200U)
#define USBNC_CTRL1_PWR_POL_SHIFT (9U)
/*! PWR_POL - PWR_POL
* 0b1..PMIC Power Pin is High active.
* 0b0..PMIC Power Pin is Low active.
*/
#define USBNC_CTRL1_PWR_POL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_PWR_POL_SHIFT)) & USBNC_CTRL1_PWR_POL_MASK)
#define USBNC_CTRL1_WIE_MASK (0x400U)
#define USBNC_CTRL1_WIE_SHIFT (10U)
/*! WIE - WIE
* 0b1..Interrupt Enabled
* 0b0..Interrupt Disabled
*/
#define USBNC_CTRL1_WIE(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIE_SHIFT)) & USBNC_CTRL1_WIE_MASK)
#define USBNC_CTRL1_WKUP_SW_EN_MASK (0x4000U)
#define USBNC_CTRL1_WKUP_SW_EN_SHIFT (14U)
/*! WKUP_SW_EN - WKUP_SW_EN
* 0b1..Enable
* 0b0..Disable
*/
#define USBNC_CTRL1_WKUP_SW_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_EN_SHIFT)) & USBNC_CTRL1_WKUP_SW_EN_MASK)
#define USBNC_CTRL1_WKUP_SW_MASK (0x8000U)
#define USBNC_CTRL1_WKUP_SW_SHIFT (15U)
/*! WKUP_SW - WKUP_SW
* 0b1..Force wake-up
* 0b0..Inactive
*/
#define USBNC_CTRL1_WKUP_SW(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_SW_SHIFT)) & USBNC_CTRL1_WKUP_SW_MASK)
#define USBNC_CTRL1_WKUP_ID_EN_MASK (0x10000U)
#define USBNC_CTRL1_WKUP_ID_EN_SHIFT (16U)
/*! WKUP_ID_EN - WKUP_ID_EN
* 0b1..Enable
* 0b0..Disable
*/
#define USBNC_CTRL1_WKUP_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_ID_EN_SHIFT)) & USBNC_CTRL1_WKUP_ID_EN_MASK)
#define USBNC_CTRL1_WKUP_VBUS_EN_MASK (0x20000U)
#define USBNC_CTRL1_WKUP_VBUS_EN_SHIFT (17U)
/*! WKUP_VBUS_EN - WKUP_VBUS_EN
* 0b1..Enable
* 0b0..Disable
*/
#define USBNC_CTRL1_WKUP_VBUS_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_VBUS_EN_SHIFT)) & USBNC_CTRL1_WKUP_VBUS_EN_MASK)
#define USBNC_CTRL1_WKUP_DPDM_EN_MASK (0x20000000U)
#define USBNC_CTRL1_WKUP_DPDM_EN_SHIFT (29U)
/*! WKUP_DPDM_EN - Wake-up on DPDM change enable
* 0b1..(Default) DPDM changes wake-up to be enabled, it is for device only.
* 0b0..DPDM changes wake-up to be disabled only when VBUS is 0.
*/
#define USBNC_CTRL1_WKUP_DPDM_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WKUP_DPDM_EN_SHIFT)) & USBNC_CTRL1_WKUP_DPDM_EN_MASK)
#define USBNC_CTRL1_WIR_MASK (0x80000000U)
#define USBNC_CTRL1_WIR_SHIFT (31U)
/*! WIR - WIR
* 0b1..Wake-up Interrupt Request received
* 0b0..No wake-up interrupt request received
*/
#define USBNC_CTRL1_WIR(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL1_WIR_SHIFT)) & USBNC_CTRL1_WIR_MASK)
/*! @} */
/*! @name CTRL2 - USB OTG Control 2 Register */
/*! @{ */
#define USBNC_CTRL2_VBUS_SOURCE_SEL_MASK (0x3U)
#define USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT (0U)
/*! VBUS_SOURCE_SEL - VBUS_SOURCE_SEL
* 0b00..vbus_valid
* 0b01..sess_valid
* 0b10..sess_valid
* 0b11..sess_valid
*/
#define USBNC_CTRL2_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_VBUS_SOURCE_SEL_SHIFT)) & USBNC_CTRL2_VBUS_SOURCE_SEL_MASK)
#define USBNC_CTRL2_AUTURESUME_EN_MASK (0x4U)
#define USBNC_CTRL2_AUTURESUME_EN_SHIFT (2U)
/*! AUTURESUME_EN - Auto Resume Enable
* 0b0..Default
*/
#define USBNC_CTRL2_AUTURESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_AUTURESUME_EN_SHIFT)) & USBNC_CTRL2_AUTURESUME_EN_MASK)
#define USBNC_CTRL2_LOWSPEED_EN_MASK (0x8U)
#define USBNC_CTRL2_LOWSPEED_EN_SHIFT (3U)
/*! LOWSPEED_EN - LOWSPEED_EN
* 0b0..Default
*/
#define USBNC_CTRL2_LOWSPEED_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_LOWSPEED_EN_SHIFT)) & USBNC_CTRL2_LOWSPEED_EN_MASK)
#define USBNC_CTRL2_UTMI_CLK_VLD_MASK (0x80000000U)
#define USBNC_CTRL2_UTMI_CLK_VLD_SHIFT (31U)
/*! UTMI_CLK_VLD - UTMI_CLK_VLD
* 0b0..Default
*/
#define USBNC_CTRL2_UTMI_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_CTRL2_UTMI_CLK_VLD_SHIFT)) & USBNC_CTRL2_UTMI_CLK_VLD_MASK)
/*! @} */
/*! @name HSIC_CTRL - USB Host HSIC Control Register */
/*! @{ */
#define USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK (0x800U)
#define USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT (11U)
/*! HSIC_CLK_ON - HSIC_CLK_ON
* 0b1..Active
* 0b0..Inactive
*/
#define USBNC_HSIC_CTRL_HSIC_CLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_CLK_ON_SHIFT)) & USBNC_HSIC_CTRL_HSIC_CLK_ON_MASK)
#define USBNC_HSIC_CTRL_HSIC_EN_MASK (0x1000U)
#define USBNC_HSIC_CTRL_HSIC_EN_SHIFT (12U)
/*! HSIC_EN - HSIC_EN
* 0b1..Enabled
* 0b0..Disabled
*/
#define USBNC_HSIC_CTRL_HSIC_EN(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_HSIC_EN_SHIFT)) & USBNC_HSIC_CTRL_HSIC_EN_MASK)
#define USBNC_HSIC_CTRL_CLK_VLD_MASK (0x80000000U)
#define USBNC_HSIC_CTRL_CLK_VLD_SHIFT (31U)
/*! CLK_VLD - CLK_VLD
* 0b1..Valid
* 0b0..Invalid
*/
#define USBNC_HSIC_CTRL_CLK_VLD(x) (((uint32_t)(((uint32_t)(x)) << USBNC_HSIC_CTRL_CLK_VLD_SHIFT)) & USBNC_HSIC_CTRL_CLK_VLD_MASK)
/*! @} */
/*!
* @}
*/ /* end of group USBNC_Register_Masks */
/* USBNC - Peripheral instance base addresses */
/** Peripheral USBNC_OTG1 base address */
#define USBNC_OTG1_BASE (0x40430200u)
/** Peripheral USBNC_OTG1 base pointer */
#define USBNC_OTG1 ((USBNC_Type *)USBNC_OTG1_BASE)
/** Peripheral USBNC_OTG2 base address */
#define USBNC_OTG2_BASE (0x4042C200u)
/** Peripheral USBNC_OTG2 base pointer */
#define USBNC_OTG2 ((USBNC_Type *)USBNC_OTG2_BASE)
/** Array initializer of USBNC peripheral base addresses */
#define USBNC_BASE_ADDRS { 0u, USBNC_OTG1_BASE, USBNC_OTG2_BASE }
/** Array initializer of USBNC peripheral base pointers */
#define USBNC_BASE_PTRS { (USBNC_Type *)0u, USBNC_OTG1, USBNC_OTG2 }
/* Backward compatibility */
#define USB_OTGn_CTRL CTRL1
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_MASK USBNC_CTRL1_OVER_CUR_DIS_MASK
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS_SHIFT USBNC_CTRL1_OVER_CUR_DIS_SHIFT
#define USBNC_USB_OTGn_CTRL_OVER_CUR_DIS(x) USBNC_CTRL1_OVER_CUR_DIS(x)
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_MASK USBNC_CTRL1_OVER_CUR_POL_MASK
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL_SHIFT USBNC_CTRL1_OVER_CUR_POL_SHIFT
#define USBNC_USB_OTGn_CTRL_OVER_CUR_POL(x) USBNC_CTRL1_OVER_CUR_POL(x)
#define USBNC_USB_OTGn_CTRL_PWR_POL_MASK USBNC_CTRL1_PWR_POL_MASK
#define USBNC_USB_OTGn_CTRL_PWR_POL_SHIFT USBNC_CTRL1_PWR_POL_SHIFT
#define USBNC_USB_OTGn_CTRL_PWR_POL(x) USBNC_CTRL1_PWR_POL(x)
#define USBNC_USB_OTGn_CTRL_WIE_MASK USBNC_CTRL1_WIE_MASK
#define USBNC_USB_OTGn_CTRL_WIE_SHIFT USBNC_CTRL1_WIE_SHIFT
#define USBNC_USB_OTGn_CTRL_WIE(x) USBNC_CTRL1_WIE(x)
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_MASK USBNC_CTRL1_WKUP_SW_EN_MASK
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN_SHIFT USBNC_CTRL1_WKUP_SW_EN_SHIFT
#define USBNC_USB_OTGn_CTRL_WKUP_SW_EN(x) USBNC_CTRL1_WKUP_SW_EN(x)
#define USBNC_USB_OTGn_CTRL_WKUP_SW_MASK USBNC_CTRL1_WKUP_SW_MASK
#define USBNC_USB_OTGn_CTRL_WKUP_SW_SHIFT USBNC_CTRL1_WKUP_SW_SHIFT
#define USBNC_USB_OTGn_CTRL_WKUP_SW(x) USBNC_CTRL1_WKUP_SW(x)
#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_MASK USBNC_CTRL1_WKUP_ID_EN_MASK
#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN_SHIFT USBNC_CTRL1_WKUP_ID_EN_SHIFT
#define USBNC_USB_OTGn_CTRL_WKUP_ID_EN(x) USBNC_CTRL1_WKUP_ID_EN(x)
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_MASK USBNC_CTRL1_WKUP_VBUS_EN_MASK
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN_SHIFT USBNC_CTRL1_WKUP_VBUS_EN_SHIFT
#define USBNC_USB_OTGn_CTRL_WKUP_VBUS_EN(x) USBNC_CTRL1_WKUP_VBUS_EN(x)
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_MASK USBNC_CTRL1_WKUP_DPDM_EN_MASK
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN_SHIFT USBNC_CTRL1_WKUP_DPDM_EN_SHIFT
#define USBNC_USB_OTGn_CTRL_WKUP_DPDM_EN(x) USBNC_CTRL1_WKUP_DPDM_EN(x)
#define USBNC_USB_OTGn_CTRL_WIR_MASK USBNC_CTRL1_WIR_MASK
#define USBNC_USB_OTGn_CTRL_WIR_SHIFT USBNC_CTRL1_WIR_SHIFT
#define USBNC_USB_OTGn_CTRL_WIR(x) USBNC_CTRL1_WIR(x)
/*!
* @}
*/ /* end of group USBNC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USBPHY Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USBPHY_Peripheral_Access_Layer USBPHY Peripheral Access Layer
* @{
*/
/** USBPHY - Register Layout Typedef */
typedef struct {
__IO uint32_t PWD; /**< USB PHY Power-Down Register, offset: 0x0 */
__IO uint32_t PWD_SET; /**< USB PHY Power-Down Register, offset: 0x4 */
__IO uint32_t PWD_CLR; /**< USB PHY Power-Down Register, offset: 0x8 */
__IO uint32_t PWD_TOG; /**< USB PHY Power-Down Register, offset: 0xC */
__IO uint32_t TX; /**< USB PHY Transmitter Control Register, offset: 0x10 */
__IO uint32_t TX_SET; /**< USB PHY Transmitter Control Register, offset: 0x14 */
__IO uint32_t TX_CLR; /**< USB PHY Transmitter Control Register, offset: 0x18 */
__IO uint32_t TX_TOG; /**< USB PHY Transmitter Control Register, offset: 0x1C */
__IO uint32_t RX; /**< USB PHY Receiver Control Register, offset: 0x20 */
__IO uint32_t RX_SET; /**< USB PHY Receiver Control Register, offset: 0x24 */
__IO uint32_t RX_CLR; /**< USB PHY Receiver Control Register, offset: 0x28 */
__IO uint32_t RX_TOG; /**< USB PHY Receiver Control Register, offset: 0x2C */
__IO uint32_t CTRL; /**< USB PHY General Control Register, offset: 0x30 */
__IO uint32_t CTRL_SET; /**< USB PHY General Control Register, offset: 0x34 */
__IO uint32_t CTRL_CLR; /**< USB PHY General Control Register, offset: 0x38 */
__IO uint32_t CTRL_TOG; /**< USB PHY General Control Register, offset: 0x3C */
__IO uint32_t STATUS; /**< USB PHY Status Register, offset: 0x40 */
uint8_t RESERVED_0[12];
__IO uint32_t DEBUGr; /**< USB PHY Debug Register, offset: 0x50 */
__IO uint32_t DEBUG_SET; /**< USB PHY Debug Register, offset: 0x54 */
__IO uint32_t DEBUG_CLR; /**< USB PHY Debug Register, offset: 0x58 */
__IO uint32_t DEBUG_TOG; /**< USB PHY Debug Register, offset: 0x5C */
__I uint32_t DEBUG0_STATUS; /**< UTMI Debug Status Register 0, offset: 0x60 */
uint8_t RESERVED_1[12];
__IO uint32_t DEBUG1; /**< UTMI Debug Status Register 1, offset: 0x70 */
__IO uint32_t DEBUG1_SET; /**< UTMI Debug Status Register 1, offset: 0x74 */
__IO uint32_t DEBUG1_CLR; /**< UTMI Debug Status Register 1, offset: 0x78 */
__IO uint32_t DEBUG1_TOG; /**< UTMI Debug Status Register 1, offset: 0x7C */
__I uint32_t VERSION; /**< UTMI RTL Version, offset: 0x80 */
uint8_t RESERVED_2[28];
__IO uint32_t PLL_SIC; /**< USB PHY PLL Control/Status Register, offset: 0xA0 */
__IO uint32_t PLL_SIC_SET; /**< USB PHY PLL Control/Status Register, offset: 0xA4 */
__IO uint32_t PLL_SIC_CLR; /**< USB PHY PLL Control/Status Register, offset: 0xA8 */
__IO uint32_t PLL_SIC_TOG; /**< USB PHY PLL Control/Status Register, offset: 0xAC */
uint8_t RESERVED_3[16];
__IO uint32_t USB1_VBUS_DETECT; /**< USB PHY VBUS Detect Control Register, offset: 0xC0 */
__IO uint32_t USB1_VBUS_DETECT_SET; /**< USB PHY VBUS Detect Control Register, offset: 0xC4 */
__IO uint32_t USB1_VBUS_DETECT_CLR; /**< USB PHY VBUS Detect Control Register, offset: 0xC8 */
__IO uint32_t USB1_VBUS_DETECT_TOG; /**< USB PHY VBUS Detect Control Register, offset: 0xCC */
__I uint32_t USB1_VBUS_DET_STAT; /**< USB PHY VBUS Detector Status Register, offset: 0xD0 */
uint8_t RESERVED_4[12];
__IO uint32_t USB1_CHRG_DETECT; /**< USB PHY Charger Detect Control Register, offset: 0xE0 */
__IO uint32_t USB1_CHRG_DETECT_SET; /**< USB PHY Charger Detect Control Register, offset: 0xE4 */
__IO uint32_t USB1_CHRG_DETECT_CLR; /**< USB PHY Charger Detect Control Register, offset: 0xE8 */
__IO uint32_t USB1_CHRG_DETECT_TOG; /**< USB PHY Charger Detect Control Register, offset: 0xEC */
__I uint32_t USB1_CHRG_DET_STAT; /**< USB PHY Charger Detect Status Register, offset: 0xF0 */
uint8_t RESERVED_5[12];
__IO uint32_t ANACTRL; /**< USB PHY Analog Control Register, offset: 0x100 */
__IO uint32_t ANACTRL_SET; /**< USB PHY Analog Control Register, offset: 0x104 */
__IO uint32_t ANACTRL_CLR; /**< USB PHY Analog Control Register, offset: 0x108 */
__IO uint32_t ANACTRL_TOG; /**< USB PHY Analog Control Register, offset: 0x10C */
__IO uint32_t USB1_LOOPBACK; /**< USB PHY Loopback Control/Status Register, offset: 0x110 */
__IO uint32_t USB1_LOOPBACK_SET; /**< USB PHY Loopback Control/Status Register, offset: 0x114 */
__IO uint32_t USB1_LOOPBACK_CLR; /**< USB PHY Loopback Control/Status Register, offset: 0x118 */
__IO uint32_t USB1_LOOPBACK_TOG; /**< USB PHY Loopback Control/Status Register, offset: 0x11C */
__IO uint32_t USB1_LOOPBACK_HSFSCNT; /**< USB PHY Loopback Packet Number Select Register, offset: 0x120 */
__IO uint32_t USB1_LOOPBACK_HSFSCNT_SET; /**< USB PHY Loopback Packet Number Select Register, offset: 0x124 */
__IO uint32_t USB1_LOOPBACK_HSFSCNT_CLR; /**< USB PHY Loopback Packet Number Select Register, offset: 0x128 */
__IO uint32_t USB1_LOOPBACK_HSFSCNT_TOG; /**< USB PHY Loopback Packet Number Select Register, offset: 0x12C */
__IO uint32_t TRIM_OVERRIDE_EN; /**< USB PHY Trim Override Enable Register, offset: 0x130 */
__IO uint32_t TRIM_OVERRIDE_EN_SET; /**< USB PHY Trim Override Enable Register, offset: 0x134 */
__IO uint32_t TRIM_OVERRIDE_EN_CLR; /**< USB PHY Trim Override Enable Register, offset: 0x138 */
__IO uint32_t TRIM_OVERRIDE_EN_TOG; /**< USB PHY Trim Override Enable Register, offset: 0x13C */
} USBPHY_Type;
/* ----------------------------------------------------------------------------
-- USBPHY Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USBPHY_Register_Masks USBPHY Register Masks
* @{
*/
/*! @name PWD - USB PHY Power-Down Register */
/*! @{ */
#define USBPHY_PWD_TXPWDFS_MASK (0x400U)
#define USBPHY_PWD_TXPWDFS_SHIFT (10U)
/*! TXPWDFS - TXPWDFS
* 0b0..Normal operation.
* 0b1..Power-down the USB full-speed drivers. This turns off the current starvation sources and puts the drivers into high-impedance output
*/
#define USBPHY_PWD_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDFS_SHIFT)) & USBPHY_PWD_TXPWDFS_MASK)
#define USBPHY_PWD_TXPWDIBIAS_MASK (0x800U)
#define USBPHY_PWD_TXPWDIBIAS_SHIFT (11U)
/*! TXPWDIBIAS - TXPWDIBIAS
* 0b0..Normal operation
* 0b1..Power-down the USB PHY current bias block for the transmitter. This bit should be set only when the USB
* is in suspend mode. This effectively powers down the entire USB transmit path
*/
#define USBPHY_PWD_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TXPWDIBIAS_MASK)
#define USBPHY_PWD_TXPWDV2I_MASK (0x1000U)
#define USBPHY_PWD_TXPWDV2I_SHIFT (12U)
/*! TXPWDV2I - TXPWDV2I
* 0b0..Normal operation.
* 0b1..Power-down the USB PHY transmit V-to-I converter and the current mirror
*/
#define USBPHY_PWD_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TXPWDV2I_SHIFT)) & USBPHY_PWD_TXPWDV2I_MASK)
#define USBPHY_PWD_RXPWDENV_MASK (0x20000U)
#define USBPHY_PWD_RXPWDENV_SHIFT (17U)
/*! RXPWDENV - RXPWDENV
* 0b0..Normal operation.
* 0b1..Power-down the USB high-speed receiver envelope detector (squelch signal)
*/
#define USBPHY_PWD_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDENV_SHIFT)) & USBPHY_PWD_RXPWDENV_MASK)
#define USBPHY_PWD_RXPWD1PT1_MASK (0x40000U)
#define USBPHY_PWD_RXPWD1PT1_SHIFT (18U)
/*! RXPWD1PT1 - RXPWD1PT1
* 0b0..Normal operation
* 0b1..Power-down the USB full-speed differential receiver.
*/
#define USBPHY_PWD_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWD1PT1_SHIFT)) & USBPHY_PWD_RXPWD1PT1_MASK)
#define USBPHY_PWD_RXPWDDIFF_MASK (0x80000U)
#define USBPHY_PWD_RXPWDDIFF_SHIFT (19U)
/*! RXPWDDIFF - RXPWDDIFF
* 0b0..Normal operation.
* 0b1..Power-down the USB high-speed differential receiver
*/
#define USBPHY_PWD_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDDIFF_SHIFT)) & USBPHY_PWD_RXPWDDIFF_MASK)
#define USBPHY_PWD_RXPWDRX_MASK (0x100000U)
#define USBPHY_PWD_RXPWDRX_SHIFT (20U)
/*! RXPWDRX - RXPWDRX
* 0b0..Normal operation
* 0b1..Power-down the entire USB PHY receiver block except for the full-speed differential receiver
*/
#define USBPHY_PWD_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_RXPWDRX_SHIFT)) & USBPHY_PWD_RXPWDRX_MASK)
/*! @} */
/*! @name PWD_SET - USB PHY Power-Down Register */
/*! @{ */
#define USBPHY_PWD_SET_TXPWDFS_MASK (0x400U)
#define USBPHY_PWD_SET_TXPWDFS_SHIFT (10U)
/*! TXPWDFS - TXPWDFS
*/
#define USBPHY_PWD_SET_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDFS_SHIFT)) & USBPHY_PWD_SET_TXPWDFS_MASK)
#define USBPHY_PWD_SET_TXPWDIBIAS_MASK (0x800U)
#define USBPHY_PWD_SET_TXPWDIBIAS_SHIFT (11U)
/*! TXPWDIBIAS - TXPWDIBIAS
*/
#define USBPHY_PWD_SET_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_SET_TXPWDIBIAS_MASK)
#define USBPHY_PWD_SET_TXPWDV2I_MASK (0x1000U)
#define USBPHY_PWD_SET_TXPWDV2I_SHIFT (12U)
/*! TXPWDV2I - TXPWDV2I
*/
#define USBPHY_PWD_SET_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_TXPWDV2I_SHIFT)) & USBPHY_PWD_SET_TXPWDV2I_MASK)
#define USBPHY_PWD_SET_RXPWDENV_MASK (0x20000U)
#define USBPHY_PWD_SET_RXPWDENV_SHIFT (17U)
/*! RXPWDENV - RXPWDENV
*/
#define USBPHY_PWD_SET_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDENV_SHIFT)) & USBPHY_PWD_SET_RXPWDENV_MASK)
#define USBPHY_PWD_SET_RXPWD1PT1_MASK (0x40000U)
#define USBPHY_PWD_SET_RXPWD1PT1_SHIFT (18U)
/*! RXPWD1PT1 - RXPWD1PT1
*/
#define USBPHY_PWD_SET_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWD1PT1_SHIFT)) & USBPHY_PWD_SET_RXPWD1PT1_MASK)
#define USBPHY_PWD_SET_RXPWDDIFF_MASK (0x80000U)
#define USBPHY_PWD_SET_RXPWDDIFF_SHIFT (19U)
/*! RXPWDDIFF - RXPWDDIFF
*/
#define USBPHY_PWD_SET_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDDIFF_SHIFT)) & USBPHY_PWD_SET_RXPWDDIFF_MASK)
#define USBPHY_PWD_SET_RXPWDRX_MASK (0x100000U)
#define USBPHY_PWD_SET_RXPWDRX_SHIFT (20U)
/*! RXPWDRX - RXPWDRX
*/
#define USBPHY_PWD_SET_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_SET_RXPWDRX_SHIFT)) & USBPHY_PWD_SET_RXPWDRX_MASK)
/*! @} */
/*! @name PWD_CLR - USB PHY Power-Down Register */
/*! @{ */
#define USBPHY_PWD_CLR_TXPWDFS_MASK (0x400U)
#define USBPHY_PWD_CLR_TXPWDFS_SHIFT (10U)
/*! TXPWDFS - TXPWDFS
*/
#define USBPHY_PWD_CLR_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDFS_SHIFT)) & USBPHY_PWD_CLR_TXPWDFS_MASK)
#define USBPHY_PWD_CLR_TXPWDIBIAS_MASK (0x800U)
#define USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT (11U)
/*! TXPWDIBIAS - TXPWDIBIAS
*/
#define USBPHY_PWD_CLR_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_CLR_TXPWDIBIAS_MASK)
#define USBPHY_PWD_CLR_TXPWDV2I_MASK (0x1000U)
#define USBPHY_PWD_CLR_TXPWDV2I_SHIFT (12U)
/*! TXPWDV2I - TXPWDV2I
*/
#define USBPHY_PWD_CLR_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_TXPWDV2I_SHIFT)) & USBPHY_PWD_CLR_TXPWDV2I_MASK)
#define USBPHY_PWD_CLR_RXPWDENV_MASK (0x20000U)
#define USBPHY_PWD_CLR_RXPWDENV_SHIFT (17U)
/*! RXPWDENV - RXPWDENV
*/
#define USBPHY_PWD_CLR_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDENV_SHIFT)) & USBPHY_PWD_CLR_RXPWDENV_MASK)
#define USBPHY_PWD_CLR_RXPWD1PT1_MASK (0x40000U)
#define USBPHY_PWD_CLR_RXPWD1PT1_SHIFT (18U)
/*! RXPWD1PT1 - RXPWD1PT1
*/
#define USBPHY_PWD_CLR_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWD1PT1_SHIFT)) & USBPHY_PWD_CLR_RXPWD1PT1_MASK)
#define USBPHY_PWD_CLR_RXPWDDIFF_MASK (0x80000U)
#define USBPHY_PWD_CLR_RXPWDDIFF_SHIFT (19U)
/*! RXPWDDIFF - RXPWDDIFF
*/
#define USBPHY_PWD_CLR_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDDIFF_SHIFT)) & USBPHY_PWD_CLR_RXPWDDIFF_MASK)
#define USBPHY_PWD_CLR_RXPWDRX_MASK (0x100000U)
#define USBPHY_PWD_CLR_RXPWDRX_SHIFT (20U)
/*! RXPWDRX - RXPWDRX
*/
#define USBPHY_PWD_CLR_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_CLR_RXPWDRX_SHIFT)) & USBPHY_PWD_CLR_RXPWDRX_MASK)
/*! @} */
/*! @name PWD_TOG - USB PHY Power-Down Register */
/*! @{ */
#define USBPHY_PWD_TOG_TXPWDFS_MASK (0x400U)
#define USBPHY_PWD_TOG_TXPWDFS_SHIFT (10U)
/*! TXPWDFS - TXPWDFS
*/
#define USBPHY_PWD_TOG_TXPWDFS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDFS_SHIFT)) & USBPHY_PWD_TOG_TXPWDFS_MASK)
#define USBPHY_PWD_TOG_TXPWDIBIAS_MASK (0x800U)
#define USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT (11U)
/*! TXPWDIBIAS - TXPWDIBIAS
*/
#define USBPHY_PWD_TOG_TXPWDIBIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDIBIAS_SHIFT)) & USBPHY_PWD_TOG_TXPWDIBIAS_MASK)
#define USBPHY_PWD_TOG_TXPWDV2I_MASK (0x1000U)
#define USBPHY_PWD_TOG_TXPWDV2I_SHIFT (12U)
/*! TXPWDV2I - TXPWDV2I
*/
#define USBPHY_PWD_TOG_TXPWDV2I(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_TXPWDV2I_SHIFT)) & USBPHY_PWD_TOG_TXPWDV2I_MASK)
#define USBPHY_PWD_TOG_RXPWDENV_MASK (0x20000U)
#define USBPHY_PWD_TOG_RXPWDENV_SHIFT (17U)
/*! RXPWDENV - RXPWDENV
*/
#define USBPHY_PWD_TOG_RXPWDENV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDENV_SHIFT)) & USBPHY_PWD_TOG_RXPWDENV_MASK)
#define USBPHY_PWD_TOG_RXPWD1PT1_MASK (0x40000U)
#define USBPHY_PWD_TOG_RXPWD1PT1_SHIFT (18U)
/*! RXPWD1PT1 - RXPWD1PT1
*/
#define USBPHY_PWD_TOG_RXPWD1PT1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWD1PT1_SHIFT)) & USBPHY_PWD_TOG_RXPWD1PT1_MASK)
#define USBPHY_PWD_TOG_RXPWDDIFF_MASK (0x80000U)
#define USBPHY_PWD_TOG_RXPWDDIFF_SHIFT (19U)
/*! RXPWDDIFF - RXPWDDIFF
*/
#define USBPHY_PWD_TOG_RXPWDDIFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDDIFF_SHIFT)) & USBPHY_PWD_TOG_RXPWDDIFF_MASK)
#define USBPHY_PWD_TOG_RXPWDRX_MASK (0x100000U)
#define USBPHY_PWD_TOG_RXPWDRX_SHIFT (20U)
/*! RXPWDRX - RXPWDRX
*/
#define USBPHY_PWD_TOG_RXPWDRX(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PWD_TOG_RXPWDRX_SHIFT)) & USBPHY_PWD_TOG_RXPWDRX_MASK)
/*! @} */
/*! @name TX - USB PHY Transmitter Control Register */
/*! @{ */
#define USBPHY_TX_D_CAL_MASK (0xFU)
#define USBPHY_TX_D_CAL_SHIFT (0U)
/*! D_CAL - D_CAL
* 0b0000..Maximum current, approximately 19% above nominal.
* 0b0111..Nominal
* 0b1111..Minimum current, approximately 19% below nominal.
*/
#define USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TX_D_CAL_MASK)
#define USBPHY_TX_TXCAL45DN_MASK (0xF00U)
#define USBPHY_TX_TXCAL45DN_SHIFT (8U)
/*! TXCAL45DN - TXCAL45DN
*/
#define USBPHY_TX_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DN_SHIFT)) & USBPHY_TX_TXCAL45DN_MASK)
#define USBPHY_TX_TXCAL45DP_MASK (0xF0000U)
#define USBPHY_TX_TXCAL45DP_SHIFT (16U)
/*! TXCAL45DP - TXCAL45DP
*/
#define USBPHY_TX_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TXCAL45DP_SHIFT)) & USBPHY_TX_TXCAL45DP_MASK)
/*! @} */
/*! @name TX_SET - USB PHY Transmitter Control Register */
/*! @{ */
#define USBPHY_TX_SET_D_CAL_MASK (0xFU)
#define USBPHY_TX_SET_D_CAL_SHIFT (0U)
/*! D_CAL - D_CAL
*/
#define USBPHY_TX_SET_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_D_CAL_SHIFT)) & USBPHY_TX_SET_D_CAL_MASK)
#define USBPHY_TX_SET_TXCAL45DN_MASK (0xF00U)
#define USBPHY_TX_SET_TXCAL45DN_SHIFT (8U)
/*! TXCAL45DN - TXCAL45DN
*/
#define USBPHY_TX_SET_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DN_SHIFT)) & USBPHY_TX_SET_TXCAL45DN_MASK)
#define USBPHY_TX_SET_TXCAL45DP_MASK (0xF0000U)
#define USBPHY_TX_SET_TXCAL45DP_SHIFT (16U)
/*! TXCAL45DP - TXCAL45DP
*/
#define USBPHY_TX_SET_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_SET_TXCAL45DP_SHIFT)) & USBPHY_TX_SET_TXCAL45DP_MASK)
/*! @} */
/*! @name TX_CLR - USB PHY Transmitter Control Register */
/*! @{ */
#define USBPHY_TX_CLR_D_CAL_MASK (0xFU)
#define USBPHY_TX_CLR_D_CAL_SHIFT (0U)
/*! D_CAL - D_CAL
*/
#define USBPHY_TX_CLR_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_D_CAL_SHIFT)) & USBPHY_TX_CLR_D_CAL_MASK)
#define USBPHY_TX_CLR_TXCAL45DN_MASK (0xF00U)
#define USBPHY_TX_CLR_TXCAL45DN_SHIFT (8U)
/*! TXCAL45DN - TXCAL45DN
*/
#define USBPHY_TX_CLR_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DN_SHIFT)) & USBPHY_TX_CLR_TXCAL45DN_MASK)
#define USBPHY_TX_CLR_TXCAL45DP_MASK (0xF0000U)
#define USBPHY_TX_CLR_TXCAL45DP_SHIFT (16U)
/*! TXCAL45DP - TXCAL45DP
*/
#define USBPHY_TX_CLR_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_CLR_TXCAL45DP_SHIFT)) & USBPHY_TX_CLR_TXCAL45DP_MASK)
/*! @} */
/*! @name TX_TOG - USB PHY Transmitter Control Register */
/*! @{ */
#define USBPHY_TX_TOG_D_CAL_MASK (0xFU)
#define USBPHY_TX_TOG_D_CAL_SHIFT (0U)
/*! D_CAL - D_CAL
*/
#define USBPHY_TX_TOG_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_D_CAL_SHIFT)) & USBPHY_TX_TOG_D_CAL_MASK)
#define USBPHY_TX_TOG_TXCAL45DN_MASK (0xF00U)
#define USBPHY_TX_TOG_TXCAL45DN_SHIFT (8U)
/*! TXCAL45DN - TXCAL45DN
*/
#define USBPHY_TX_TOG_TXCAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DN_SHIFT)) & USBPHY_TX_TOG_TXCAL45DN_MASK)
#define USBPHY_TX_TOG_TXCAL45DP_MASK (0xF0000U)
#define USBPHY_TX_TOG_TXCAL45DP_SHIFT (16U)
/*! TXCAL45DP - TXCAL45DP
*/
#define USBPHY_TX_TOG_TXCAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TX_TOG_TXCAL45DP_SHIFT)) & USBPHY_TX_TOG_TXCAL45DP_MASK)
/*! @} */
/*! @name RX - USB PHY Receiver Control Register */
/*! @{ */
#define USBPHY_RX_ENVADJ_MASK (0x7U)
#define USBPHY_RX_ENVADJ_SHIFT (0U)
/*! ENVADJ - ENVADJ
* 0b000..Trip-Level Voltage is 0.1000 V
* 0b001..Trip-Level Voltage is 0.1125 V
* 0b010..Trip-Level Voltage is 0.1250 V
* 0b011..Trip-Level Voltage is 0.0875 V
* 0b1xx..Reserved
*/
#define USBPHY_RX_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_ENVADJ_SHIFT)) & USBPHY_RX_ENVADJ_MASK)
#define USBPHY_RX_DISCONADJ_MASK (0x70U)
#define USBPHY_RX_DISCONADJ_SHIFT (4U)
/*! DISCONADJ - DISCONADJ
* 0b000..Trip-Level Voltage is 0.56875 V
* 0b001..Trip-Level Voltage is 0.55000 V
* 0b010..Trip-Level Voltage is 0.58125 V
* 0b011..Trip-Level Voltage is 0.60000 V
* 0b1xx..Reserved
*/
#define USBPHY_RX_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_DISCONADJ_SHIFT)) & USBPHY_RX_DISCONADJ_MASK)
#define USBPHY_RX_RXDBYPASS_MASK (0x400000U)
#define USBPHY_RX_RXDBYPASS_SHIFT (22U)
/*! RXDBYPASS - RXDBYPASS
* 0b0..Normal operation.
* 0b1..Use the output of the USB_DP single-ended receiver in place of the full-speed differential receiver
*/
#define USBPHY_RX_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_RXDBYPASS_SHIFT)) & USBPHY_RX_RXDBYPASS_MASK)
/*! @} */
/*! @name RX_SET - USB PHY Receiver Control Register */
/*! @{ */
#define USBPHY_RX_SET_ENVADJ_MASK (0x7U)
#define USBPHY_RX_SET_ENVADJ_SHIFT (0U)
/*! ENVADJ - ENVADJ
*/
#define USBPHY_RX_SET_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_ENVADJ_SHIFT)) & USBPHY_RX_SET_ENVADJ_MASK)
#define USBPHY_RX_SET_DISCONADJ_MASK (0x70U)
#define USBPHY_RX_SET_DISCONADJ_SHIFT (4U)
/*! DISCONADJ - DISCONADJ
*/
#define USBPHY_RX_SET_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_DISCONADJ_SHIFT)) & USBPHY_RX_SET_DISCONADJ_MASK)
#define USBPHY_RX_SET_RXDBYPASS_MASK (0x400000U)
#define USBPHY_RX_SET_RXDBYPASS_SHIFT (22U)
/*! RXDBYPASS - RXDBYPASS
*/
#define USBPHY_RX_SET_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_SET_RXDBYPASS_SHIFT)) & USBPHY_RX_SET_RXDBYPASS_MASK)
/*! @} */
/*! @name RX_CLR - USB PHY Receiver Control Register */
/*! @{ */
#define USBPHY_RX_CLR_ENVADJ_MASK (0x7U)
#define USBPHY_RX_CLR_ENVADJ_SHIFT (0U)
/*! ENVADJ - ENVADJ
*/
#define USBPHY_RX_CLR_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_ENVADJ_SHIFT)) & USBPHY_RX_CLR_ENVADJ_MASK)
#define USBPHY_RX_CLR_DISCONADJ_MASK (0x70U)
#define USBPHY_RX_CLR_DISCONADJ_SHIFT (4U)
/*! DISCONADJ - DISCONADJ
*/
#define USBPHY_RX_CLR_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_DISCONADJ_SHIFT)) & USBPHY_RX_CLR_DISCONADJ_MASK)
#define USBPHY_RX_CLR_RXDBYPASS_MASK (0x400000U)
#define USBPHY_RX_CLR_RXDBYPASS_SHIFT (22U)
/*! RXDBYPASS - RXDBYPASS
*/
#define USBPHY_RX_CLR_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_CLR_RXDBYPASS_SHIFT)) & USBPHY_RX_CLR_RXDBYPASS_MASK)
/*! @} */
/*! @name RX_TOG - USB PHY Receiver Control Register */
/*! @{ */
#define USBPHY_RX_TOG_ENVADJ_MASK (0x7U)
#define USBPHY_RX_TOG_ENVADJ_SHIFT (0U)
/*! ENVADJ - ENVADJ
*/
#define USBPHY_RX_TOG_ENVADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_ENVADJ_SHIFT)) & USBPHY_RX_TOG_ENVADJ_MASK)
#define USBPHY_RX_TOG_DISCONADJ_MASK (0x70U)
#define USBPHY_RX_TOG_DISCONADJ_SHIFT (4U)
/*! DISCONADJ - DISCONADJ
*/
#define USBPHY_RX_TOG_DISCONADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_DISCONADJ_SHIFT)) & USBPHY_RX_TOG_DISCONADJ_MASK)
#define USBPHY_RX_TOG_RXDBYPASS_MASK (0x400000U)
#define USBPHY_RX_TOG_RXDBYPASS_SHIFT (22U)
/*! RXDBYPASS - RXDBYPASS
*/
#define USBPHY_RX_TOG_RXDBYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_RX_TOG_RXDBYPASS_SHIFT)) & USBPHY_RX_TOG_RXDBYPASS_MASK)
/*! @} */
/*! @name CTRL - USB PHY General Control Register */
/*! @{ */
#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT (0U)
/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
*/
#define USBPHY_CTRL_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_ENOTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT (1U)
/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
*/
#define USBPHY_CTRL_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_ENHOSTDISCONDETECT_MASK)
#define USBPHY_CTRL_ENIRQHOSTDISCON_MASK (0x4U)
#define USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT (2U)
/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
*/
#define USBPHY_CTRL_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_ENIRQHOSTDISCON_MASK)
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT (3U)
/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
*/
#define USBPHY_CTRL_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_HOSTDISCONDETECT_IRQ_MASK)
#define USBPHY_CTRL_ENDEVPLUGINDETECT_MASK (0x10U)
#define USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT (4U)
/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
* 0b0..Disables 200kohm pullup resistors on DP and DN pins
* 0b1..Enables 200kohm pullup resistors on DP and DN pins
*/
#define USBPHY_CTRL_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_ENDEVPLUGINDETECT_MASK)
#define USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT (5U)
/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
*/
#define USBPHY_CTRL_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_POLARITY_MASK)
#define USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK (0x40U)
#define USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT (6U)
/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
*/
#define USBPHY_CTRL_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_OTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_ENOTGIDDETECT_MASK (0x80U)
#define USBPHY_CTRL_ENOTGIDDETECT_SHIFT (7U)
/*! ENOTGIDDETECT - ENOTGIDDETECT
*/
#define USBPHY_CTRL_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_ENOTGIDDETECT_MASK)
#define USBPHY_CTRL_RESUMEIRQSTICKY_MASK (0x100U)
#define USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT (8U)
/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
*/
#define USBPHY_CTRL_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_RESUMEIRQSTICKY_MASK)
#define USBPHY_CTRL_ENIRQRESUMEDETECT_MASK (0x200U)
#define USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT (9U)
/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
*/
#define USBPHY_CTRL_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_ENIRQRESUMEDETECT_MASK)
#define USBPHY_CTRL_RESUME_IRQ_MASK (0x400U)
#define USBPHY_CTRL_RESUME_IRQ_SHIFT (10U)
/*! RESUME_IRQ - RESUME_IRQ
*/
#define USBPHY_CTRL_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_RESUME_IRQ_MASK)
#define USBPHY_CTRL_ENIRQDEVPLUGIN_MASK (0x800U)
#define USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT (11U)
/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
*/
#define USBPHY_CTRL_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_ENIRQDEVPLUGIN_MASK)
#define USBPHY_CTRL_DEVPLUGIN_IRQ_MASK (0x1000U)
#define USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT (12U)
/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
*/
#define USBPHY_CTRL_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_DEVPLUGIN_IRQ_MASK)
#define USBPHY_CTRL_ENUTMILEVEL2_MASK (0x4000U)
#define USBPHY_CTRL_ENUTMILEVEL2_SHIFT (14U)
/*! ENUTMILEVEL2 - ENUTMILEVEL2
*/
#define USBPHY_CTRL_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL2_MASK)
#define USBPHY_CTRL_ENUTMILEVEL3_MASK (0x8000U)
#define USBPHY_CTRL_ENUTMILEVEL3_SHIFT (15U)
/*! ENUTMILEVEL3 - ENUTMILEVEL3
*/
#define USBPHY_CTRL_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_ENUTMILEVEL3_MASK)
#define USBPHY_CTRL_ENIRQWAKEUP_MASK (0x10000U)
#define USBPHY_CTRL_ENIRQWAKEUP_SHIFT (16U)
/*! ENIRQWAKEUP - ENIRQWAKEUP
*/
#define USBPHY_CTRL_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_ENIRQWAKEUP_MASK)
#define USBPHY_CTRL_WAKEUP_IRQ_MASK (0x20000U)
#define USBPHY_CTRL_WAKEUP_IRQ_SHIFT (17U)
/*! WAKEUP_IRQ - WAKEUP_IRQ
*/
#define USBPHY_CTRL_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_WAKEUP_IRQ_MASK)
#define USBPHY_CTRL_AUTORESUME_EN_MASK (0x40000U)
#define USBPHY_CTRL_AUTORESUME_EN_SHIFT (18U)
/*! AUTORESUME_EN - AUTORESUME_EN
*/
#define USBPHY_CTRL_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_AUTORESUME_EN_MASK)
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT (19U)
/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
*/
#define USBPHY_CTRL_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_CLKGATE_MASK)
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT (20U)
/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
*/
#define USBPHY_CTRL_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_ENAUTOCLR_PHY_PWD_MASK)
#define USBPHY_CTRL_ENDPDMCHG_WKUP_MASK (0x200000U)
#define USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT (21U)
/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
*/
#define USBPHY_CTRL_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENDPDMCHG_WKUP_MASK)
#define USBPHY_CTRL_ENIDCHG_WKUP_MASK (0x400000U)
#define USBPHY_CTRL_ENIDCHG_WKUP_SHIFT (22U)
/*! ENIDCHG_WKUP - ENIDCHG_WKUP
*/
#define USBPHY_CTRL_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENIDCHG_WKUP_MASK)
#define USBPHY_CTRL_ENVBUSCHG_WKUP_MASK (0x800000U)
#define USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT (23U)
/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
*/
#define USBPHY_CTRL_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_ENVBUSCHG_WKUP_MASK)
#define USBPHY_CTRL_FSDLL_RST_EN_MASK (0x1000000U)
#define USBPHY_CTRL_FSDLL_RST_EN_SHIFT (24U)
/*! FSDLL_RST_EN - FSDLL_RST_EN
*/
#define USBPHY_CTRL_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_FSDLL_RST_EN_MASK)
#define USBPHY_CTRL_OTG_ID_VALUE_MASK (0x8000000U)
#define USBPHY_CTRL_OTG_ID_VALUE_SHIFT (27U)
/*! OTG_ID_VALUE - OTG_ID_VALUE
*/
#define USBPHY_CTRL_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_OTG_ID_VALUE_MASK)
#define USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT (28U)
/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
*/
#define USBPHY_CTRL_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_HOST_FORCE_LS_SE0_MASK)
#define USBPHY_CTRL_UTMI_SUSPENDM_MASK (0x20000000U)
#define USBPHY_CTRL_UTMI_SUSPENDM_SHIFT (29U)
/*! UTMI_SUSPENDM - UTMI_SUSPENDM
*/
#define USBPHY_CTRL_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_UTMI_SUSPENDM_MASK)
#define USBPHY_CTRL_CLKGATE_MASK (0x40000000U)
#define USBPHY_CTRL_CLKGATE_SHIFT (30U)
/*! CLKGATE - CLKGATE
*/
#define USBPHY_CTRL_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLKGATE_SHIFT)) & USBPHY_CTRL_CLKGATE_MASK)
#define USBPHY_CTRL_SFTRST_MASK (0x80000000U)
#define USBPHY_CTRL_SFTRST_SHIFT (31U)
/*! SFTRST - SFTRST
*/
#define USBPHY_CTRL_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SFTRST_SHIFT)) & USBPHY_CTRL_SFTRST_MASK)
/*! @} */
/*! @name CTRL_SET - USB PHY General Control Register */
/*! @{ */
#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT (0U)
/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
*/
#define USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_ENOTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT (1U)
/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
*/
#define USBPHY_CTRL_SET_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_SET_ENHOSTDISCONDETECT_MASK)
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK (0x4U)
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT (2U)
/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
*/
#define USBPHY_CTRL_SET_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_SET_ENIRQHOSTDISCON_MASK)
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT (3U)
/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
*/
#define USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_SET_HOSTDISCONDETECT_IRQ_MASK)
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK (0x10U)
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT (4U)
/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
*/
#define USBPHY_CTRL_SET_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_SET_ENDEVPLUGINDETECT_MASK)
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT (5U)
/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
*/
#define USBPHY_CTRL_SET_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_POLARITY_MASK)
#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK (0x40U)
#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT (6U)
/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
*/
#define USBPHY_CTRL_SET_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_SET_ENOTGIDDETECT_MASK (0x80U)
#define USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT (7U)
/*! ENOTGIDDETECT - ENOTGIDDETECT
*/
#define USBPHY_CTRL_SET_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_SET_ENOTGIDDETECT_MASK)
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK (0x100U)
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT (8U)
/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
*/
#define USBPHY_CTRL_SET_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_SET_RESUMEIRQSTICKY_MASK)
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK (0x200U)
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT (9U)
/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
*/
#define USBPHY_CTRL_SET_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_SET_ENIRQRESUMEDETECT_MASK)
#define USBPHY_CTRL_SET_RESUME_IRQ_MASK (0x400U)
#define USBPHY_CTRL_SET_RESUME_IRQ_SHIFT (10U)
/*! RESUME_IRQ - RESUME_IRQ
*/
#define USBPHY_CTRL_SET_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_SET_RESUME_IRQ_MASK)
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK (0x800U)
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT (11U)
/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
*/
#define USBPHY_CTRL_SET_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_SET_ENIRQDEVPLUGIN_MASK)
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK (0x1000U)
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT (12U)
/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
*/
#define USBPHY_CTRL_SET_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_SET_DEVPLUGIN_IRQ_MASK)
#define USBPHY_CTRL_SET_ENUTMILEVEL2_MASK (0x4000U)
#define USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT (14U)
/*! ENUTMILEVEL2 - ENUTMILEVEL2
*/
#define USBPHY_CTRL_SET_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL2_MASK)
#define USBPHY_CTRL_SET_ENUTMILEVEL3_MASK (0x8000U)
#define USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT (15U)
/*! ENUTMILEVEL3 - ENUTMILEVEL3
*/
#define USBPHY_CTRL_SET_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_SET_ENUTMILEVEL3_MASK)
#define USBPHY_CTRL_SET_ENIRQWAKEUP_MASK (0x10000U)
#define USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT (16U)
/*! ENIRQWAKEUP - ENIRQWAKEUP
*/
#define USBPHY_CTRL_SET_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_SET_ENIRQWAKEUP_MASK)
#define USBPHY_CTRL_SET_WAKEUP_IRQ_MASK (0x20000U)
#define USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT (17U)
/*! WAKEUP_IRQ - WAKEUP_IRQ
*/
#define USBPHY_CTRL_SET_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_SET_WAKEUP_IRQ_MASK)
#define USBPHY_CTRL_SET_AUTORESUME_EN_MASK (0x40000U)
#define USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT (18U)
/*! AUTORESUME_EN - AUTORESUME_EN
*/
#define USBPHY_CTRL_SET_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_SET_AUTORESUME_EN_MASK)
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT (19U)
/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
*/
#define USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_CLKGATE_MASK)
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT (20U)
/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
*/
#define USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_SET_ENAUTOCLR_PHY_PWD_MASK)
#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK (0x200000U)
#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT (21U)
/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
*/
#define USBPHY_CTRL_SET_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENDPDMCHG_WKUP_MASK)
#define USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK (0x400000U)
#define USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT (22U)
/*! ENIDCHG_WKUP - ENIDCHG_WKUP
*/
#define USBPHY_CTRL_SET_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENIDCHG_WKUP_MASK)
#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK (0x800000U)
#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT (23U)
/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
*/
#define USBPHY_CTRL_SET_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_SET_ENVBUSCHG_WKUP_MASK)
#define USBPHY_CTRL_SET_FSDLL_RST_EN_MASK (0x1000000U)
#define USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT (24U)
/*! FSDLL_RST_EN - FSDLL_RST_EN
*/
#define USBPHY_CTRL_SET_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_SET_FSDLL_RST_EN_MASK)
#define USBPHY_CTRL_SET_OTG_ID_VALUE_MASK (0x8000000U)
#define USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT (27U)
/*! OTG_ID_VALUE - OTG_ID_VALUE
*/
#define USBPHY_CTRL_SET_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_SET_OTG_ID_VALUE_MASK)
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT (28U)
/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
*/
#define USBPHY_CTRL_SET_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_SET_HOST_FORCE_LS_SE0_MASK)
#define USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK (0x20000000U)
#define USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT (29U)
/*! UTMI_SUSPENDM - UTMI_SUSPENDM
*/
#define USBPHY_CTRL_SET_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_SET_UTMI_SUSPENDM_MASK)
#define USBPHY_CTRL_SET_CLKGATE_MASK (0x40000000U)
#define USBPHY_CTRL_SET_CLKGATE_SHIFT (30U)
/*! CLKGATE - CLKGATE
*/
#define USBPHY_CTRL_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_CLKGATE_SHIFT)) & USBPHY_CTRL_SET_CLKGATE_MASK)
#define USBPHY_CTRL_SET_SFTRST_MASK (0x80000000U)
#define USBPHY_CTRL_SET_SFTRST_SHIFT (31U)
/*! SFTRST - SFTRST
*/
#define USBPHY_CTRL_SET_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_SET_SFTRST_SHIFT)) & USBPHY_CTRL_SET_SFTRST_MASK)
/*! @} */
/*! @name CTRL_CLR - USB PHY General Control Register */
/*! @{ */
#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT (0U)
/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
*/
#define USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_ENOTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT (1U)
/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
*/
#define USBPHY_CTRL_CLR_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENHOSTDISCONDETECT_MASK)
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK (0x4U)
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT (2U)
/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
*/
#define USBPHY_CTRL_CLR_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_CLR_ENIRQHOSTDISCON_MASK)
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT (3U)
/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
*/
#define USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_CLR_HOSTDISCONDETECT_IRQ_MASK)
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK (0x10U)
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT (4U)
/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
*/
#define USBPHY_CTRL_CLR_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENDEVPLUGINDETECT_MASK)
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT (5U)
/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
*/
#define USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_POLARITY_MASK)
#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK (0x40U)
#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT (6U)
/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
*/
#define USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK (0x80U)
#define USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT (7U)
/*! ENOTGIDDETECT - ENOTGIDDETECT
*/
#define USBPHY_CTRL_CLR_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENOTGIDDETECT_MASK)
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK (0x100U)
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT (8U)
/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
*/
#define USBPHY_CTRL_CLR_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_CLR_RESUMEIRQSTICKY_MASK)
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK (0x200U)
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT (9U)
/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
*/
#define USBPHY_CTRL_CLR_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_CLR_ENIRQRESUMEDETECT_MASK)
#define USBPHY_CTRL_CLR_RESUME_IRQ_MASK (0x400U)
#define USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT (10U)
/*! RESUME_IRQ - RESUME_IRQ
*/
#define USBPHY_CTRL_CLR_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_CLR_RESUME_IRQ_MASK)
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK (0x800U)
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT (11U)
/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
*/
#define USBPHY_CTRL_CLR_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_CLR_ENIRQDEVPLUGIN_MASK)
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK (0x1000U)
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT (12U)
/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
*/
#define USBPHY_CTRL_CLR_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_CLR_DEVPLUGIN_IRQ_MASK)
#define USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK (0x4000U)
#define USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT (14U)
/*! ENUTMILEVEL2 - ENUTMILEVEL2
*/
#define USBPHY_CTRL_CLR_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL2_MASK)
#define USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK (0x8000U)
#define USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT (15U)
/*! ENUTMILEVEL3 - ENUTMILEVEL3
*/
#define USBPHY_CTRL_CLR_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_CLR_ENUTMILEVEL3_MASK)
#define USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK (0x10000U)
#define USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT (16U)
/*! ENIRQWAKEUP - ENIRQWAKEUP
*/
#define USBPHY_CTRL_CLR_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_CLR_ENIRQWAKEUP_MASK)
#define USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK (0x20000U)
#define USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT (17U)
/*! WAKEUP_IRQ - WAKEUP_IRQ
*/
#define USBPHY_CTRL_CLR_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_CLR_WAKEUP_IRQ_MASK)
#define USBPHY_CTRL_CLR_AUTORESUME_EN_MASK (0x40000U)
#define USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT (18U)
/*! AUTORESUME_EN - AUTORESUME_EN
*/
#define USBPHY_CTRL_CLR_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_CLR_AUTORESUME_EN_MASK)
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT (19U)
/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
*/
#define USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_CLKGATE_MASK)
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT (20U)
/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
*/
#define USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_CLR_ENAUTOCLR_PHY_PWD_MASK)
#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK (0x200000U)
#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT (21U)
/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
*/
#define USBPHY_CTRL_CLR_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENDPDMCHG_WKUP_MASK)
#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK (0x400000U)
#define USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT (22U)
/*! ENIDCHG_WKUP - ENIDCHG_WKUP
*/
#define USBPHY_CTRL_CLR_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENIDCHG_WKUP_MASK)
#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK (0x800000U)
#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT (23U)
/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
*/
#define USBPHY_CTRL_CLR_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_CLR_ENVBUSCHG_WKUP_MASK)
#define USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK (0x1000000U)
#define USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT (24U)
/*! FSDLL_RST_EN - FSDLL_RST_EN
*/
#define USBPHY_CTRL_CLR_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_CLR_FSDLL_RST_EN_MASK)
#define USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK (0x8000000U)
#define USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT (27U)
/*! OTG_ID_VALUE - OTG_ID_VALUE
*/
#define USBPHY_CTRL_CLR_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_CLR_OTG_ID_VALUE_MASK)
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT (28U)
/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
*/
#define USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_CLR_HOST_FORCE_LS_SE0_MASK)
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK (0x20000000U)
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT (29U)
/*! UTMI_SUSPENDM - UTMI_SUSPENDM
*/
#define USBPHY_CTRL_CLR_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_CLR_UTMI_SUSPENDM_MASK)
#define USBPHY_CTRL_CLR_CLKGATE_MASK (0x40000000U)
#define USBPHY_CTRL_CLR_CLKGATE_SHIFT (30U)
/*! CLKGATE - CLKGATE
*/
#define USBPHY_CTRL_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_CLKGATE_SHIFT)) & USBPHY_CTRL_CLR_CLKGATE_MASK)
#define USBPHY_CTRL_CLR_SFTRST_MASK (0x80000000U)
#define USBPHY_CTRL_CLR_SFTRST_SHIFT (31U)
/*! SFTRST - SFTRST
*/
#define USBPHY_CTRL_CLR_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_CLR_SFTRST_SHIFT)) & USBPHY_CTRL_CLR_SFTRST_MASK)
/*! @} */
/*! @name CTRL_TOG - USB PHY General Control Register */
/*! @{ */
#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK (0x1U)
#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT (0U)
/*! ENOTG_ID_CHG_IRQ - ENOTG_ID_CHG_IRQ
*/
#define USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_ENOTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK (0x2U)
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT (1U)
/*! ENHOSTDISCONDETECT - ENHOSTDISCONDETECT
*/
#define USBPHY_CTRL_TOG_ENHOSTDISCONDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENHOSTDISCONDETECT_MASK)
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK (0x4U)
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT (2U)
/*! ENIRQHOSTDISCON - ENIRQHOSTDISCON
*/
#define USBPHY_CTRL_TOG_ENIRQHOSTDISCON(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQHOSTDISCON_SHIFT)) & USBPHY_CTRL_TOG_ENIRQHOSTDISCON_MASK)
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK (0x8U)
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT (3U)
/*! HOSTDISCONDETECT_IRQ - HOSTDISCONDETECT_IRQ
*/
#define USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_SHIFT)) & USBPHY_CTRL_TOG_HOSTDISCONDETECT_IRQ_MASK)
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK (0x10U)
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT (4U)
/*! ENDEVPLUGINDETECT - Enables non-standard resistive plugged-in detection
*/
#define USBPHY_CTRL_TOG_ENDEVPLUGINDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENDEVPLUGINDETECT_MASK)
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK (0x20U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT (5U)
/*! DEVPLUGIN_POLARITY - DEVPLUGIN_POLARITY
*/
#define USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_POLARITY_MASK)
#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK (0x40U)
#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT (6U)
/*! OTG_ID_CHG_IRQ - OTG_ID_CHG_IRQ
*/
#define USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_CHG_IRQ_MASK)
#define USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK (0x80U)
#define USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT (7U)
/*! ENOTGIDDETECT - ENOTGIDDETECT
*/
#define USBPHY_CTRL_TOG_ENOTGIDDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENOTGIDDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENOTGIDDETECT_MASK)
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK (0x100U)
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT (8U)
/*! RESUMEIRQSTICKY - RESUMEIRQSTICKY
*/
#define USBPHY_CTRL_TOG_RESUMEIRQSTICKY(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUMEIRQSTICKY_SHIFT)) & USBPHY_CTRL_TOG_RESUMEIRQSTICKY_MASK)
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK (0x200U)
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT (9U)
/*! ENIRQRESUMEDETECT - ENIRQRESUMEDETECT
*/
#define USBPHY_CTRL_TOG_ENIRQRESUMEDETECT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_SHIFT)) & USBPHY_CTRL_TOG_ENIRQRESUMEDETECT_MASK)
#define USBPHY_CTRL_TOG_RESUME_IRQ_MASK (0x400U)
#define USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT (10U)
/*! RESUME_IRQ - RESUME_IRQ
*/
#define USBPHY_CTRL_TOG_RESUME_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_RESUME_IRQ_SHIFT)) & USBPHY_CTRL_TOG_RESUME_IRQ_MASK)
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK (0x800U)
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT (11U)
/*! ENIRQDEVPLUGIN - ENIRQDEVPLUGIN
*/
#define USBPHY_CTRL_TOG_ENIRQDEVPLUGIN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_SHIFT)) & USBPHY_CTRL_TOG_ENIRQDEVPLUGIN_MASK)
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK (0x1000U)
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT (12U)
/*! DEVPLUGIN_IRQ - DEVPLUGIN_IRQ
*/
#define USBPHY_CTRL_TOG_DEVPLUGIN_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_SHIFT)) & USBPHY_CTRL_TOG_DEVPLUGIN_IRQ_MASK)
#define USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK (0x4000U)
#define USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT (14U)
/*! ENUTMILEVEL2 - ENUTMILEVEL2
*/
#define USBPHY_CTRL_TOG_ENUTMILEVEL2(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL2_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL2_MASK)
#define USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK (0x8000U)
#define USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT (15U)
/*! ENUTMILEVEL3 - ENUTMILEVEL3
*/
#define USBPHY_CTRL_TOG_ENUTMILEVEL3(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENUTMILEVEL3_SHIFT)) & USBPHY_CTRL_TOG_ENUTMILEVEL3_MASK)
#define USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK (0x10000U)
#define USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT (16U)
/*! ENIRQWAKEUP - ENIRQWAKEUP
*/
#define USBPHY_CTRL_TOG_ENIRQWAKEUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIRQWAKEUP_SHIFT)) & USBPHY_CTRL_TOG_ENIRQWAKEUP_MASK)
#define USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK (0x20000U)
#define USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT (17U)
/*! WAKEUP_IRQ - WAKEUP_IRQ
*/
#define USBPHY_CTRL_TOG_WAKEUP_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_WAKEUP_IRQ_SHIFT)) & USBPHY_CTRL_TOG_WAKEUP_IRQ_MASK)
#define USBPHY_CTRL_TOG_AUTORESUME_EN_MASK (0x40000U)
#define USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT (18U)
/*! AUTORESUME_EN - AUTORESUME_EN
*/
#define USBPHY_CTRL_TOG_AUTORESUME_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_AUTORESUME_EN_SHIFT)) & USBPHY_CTRL_TOG_AUTORESUME_EN_MASK)
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK (0x80000U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT (19U)
/*! ENAUTOCLR_CLKGATE - ENAUTOCLR_CLKGATE
*/
#define USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_CLKGATE_MASK)
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK (0x100000U)
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT (20U)
/*! ENAUTOCLR_PHY_PWD - ENAUTOCLR_PHY_PWD
*/
#define USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_SHIFT)) & USBPHY_CTRL_TOG_ENAUTOCLR_PHY_PWD_MASK)
#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK (0x200000U)
#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT (21U)
/*! ENDPDMCHG_WKUP - ENDPDMCHG_WKUP
*/
#define USBPHY_CTRL_TOG_ENDPDMCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENDPDMCHG_WKUP_MASK)
#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK (0x400000U)
#define USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT (22U)
/*! ENIDCHG_WKUP - ENIDCHG_WKUP
*/
#define USBPHY_CTRL_TOG_ENIDCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENIDCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENIDCHG_WKUP_MASK)
#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK (0x800000U)
#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT (23U)
/*! ENVBUSCHG_WKUP - ENVBUSCHG_WKUP
*/
#define USBPHY_CTRL_TOG_ENVBUSCHG_WKUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_SHIFT)) & USBPHY_CTRL_TOG_ENVBUSCHG_WKUP_MASK)
#define USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK (0x1000000U)
#define USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT (24U)
/*! FSDLL_RST_EN - FSDLL_RST_EN
*/
#define USBPHY_CTRL_TOG_FSDLL_RST_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_FSDLL_RST_EN_SHIFT)) & USBPHY_CTRL_TOG_FSDLL_RST_EN_MASK)
#define USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK (0x8000000U)
#define USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT (27U)
/*! OTG_ID_VALUE - OTG_ID_VALUE
*/
#define USBPHY_CTRL_TOG_OTG_ID_VALUE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_OTG_ID_VALUE_SHIFT)) & USBPHY_CTRL_TOG_OTG_ID_VALUE_MASK)
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK (0x10000000U)
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT (28U)
/*! HOST_FORCE_LS_SE0 - HOST_FORCE_LS_SE0
*/
#define USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_SHIFT)) & USBPHY_CTRL_TOG_HOST_FORCE_LS_SE0_MASK)
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK (0x20000000U)
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT (29U)
/*! UTMI_SUSPENDM - UTMI_SUSPENDM
*/
#define USBPHY_CTRL_TOG_UTMI_SUSPENDM(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_UTMI_SUSPENDM_SHIFT)) & USBPHY_CTRL_TOG_UTMI_SUSPENDM_MASK)
#define USBPHY_CTRL_TOG_CLKGATE_MASK (0x40000000U)
#define USBPHY_CTRL_TOG_CLKGATE_SHIFT (30U)
/*! CLKGATE - CLKGATE
*/
#define USBPHY_CTRL_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_CLKGATE_SHIFT)) & USBPHY_CTRL_TOG_CLKGATE_MASK)
#define USBPHY_CTRL_TOG_SFTRST_MASK (0x80000000U)
#define USBPHY_CTRL_TOG_SFTRST_SHIFT (31U)
/*! SFTRST - SFTRST
*/
#define USBPHY_CTRL_TOG_SFTRST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_CTRL_TOG_SFTRST_SHIFT)) & USBPHY_CTRL_TOG_SFTRST_MASK)
/*! @} */
/*! @name STATUS - USB PHY Status Register */
/*! @{ */
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK (0x8U)
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT (3U)
/*! HOSTDISCONDETECT_STATUS - HOSTDISCONDETECT_STATUS
* 0b0..USB cable disconnect has not been detected at the local host
* 0b1..USB cable disconnect has been detected at the local host
*/
#define USBPHY_STATUS_HOSTDISCONDETECT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_HOSTDISCONDETECT_STATUS_SHIFT)) & USBPHY_STATUS_HOSTDISCONDETECT_STATUS_MASK)
#define USBPHY_STATUS_DEVPLUGIN_STATUS_MASK (0x40U)
#define USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT (6U)
/*! DEVPLUGIN_STATUS - Status indicator for non-standard resistive plugged-in detection
* 0b0..No attachment to a USB host is detected
* 0b1..Cable attachment to a USB host is detected
*/
#define USBPHY_STATUS_DEVPLUGIN_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_DEVPLUGIN_STATUS_SHIFT)) & USBPHY_STATUS_DEVPLUGIN_STATUS_MASK)
#define USBPHY_STATUS_OTGID_STATUS_MASK (0x100U)
#define USBPHY_STATUS_OTGID_STATUS_SHIFT (8U)
/*! OTGID_STATUS - OTGID_STATUS
*/
#define USBPHY_STATUS_OTGID_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_OTGID_STATUS_SHIFT)) & USBPHY_STATUS_OTGID_STATUS_MASK)
#define USBPHY_STATUS_RESUME_STATUS_MASK (0x400U)
#define USBPHY_STATUS_RESUME_STATUS_SHIFT (10U)
/*! RESUME_STATUS - RESUME_STATUS
*/
#define USBPHY_STATUS_RESUME_STATUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_STATUS_RESUME_STATUS_SHIFT)) & USBPHY_STATUS_RESUME_STATUS_MASK)
/*! @} */
/*! @name DEBUG - USB PHY Debug Register */
/*! @{ */
#define USBPHY_DEBUG_OTGIDPIOLOCK_MASK (0x1U)
#define USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT (0U)
/*! OTGIDPIOLOCK - OTGIDPIOLOCK
*/
#define USBPHY_DEBUG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_OTGIDPIOLOCK_MASK)
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
*/
#define USBPHY_DEBUG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_DEBUG_INTERFACE_HOLD_MASK)
#define USBPHY_DEBUG_HSTPULLDOWN_MASK (0xCU)
#define USBPHY_DEBUG_HSTPULLDOWN_SHIFT (2U)
/*! HSTPULLDOWN - HSTPULLDOWN
*/
#define USBPHY_DEBUG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_ENHSTPULLDOWN_MASK (0x30U)
#define USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT (4U)
/*! ENHSTPULLDOWN - ENHSTPULLDOWN
*/
#define USBPHY_DEBUG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_TX2RXCOUNT_MASK (0xF00U)
#define USBPHY_DEBUG_TX2RXCOUNT_SHIFT (8U)
/*! TX2RXCOUNT - TX2RXCOUNT
*/
#define USBPHY_DEBUG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_ENTX2RXCOUNT_MASK (0x1000U)
#define USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT (12U)
/*! ENTX2RXCOUNT - ENTX2RXCOUNT
*/
#define USBPHY_DEBUG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_ENTX2RXCOUNT_MASK)
#define USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT (16U)
/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
*/
#define USBPHY_DEBUG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_ENSQUELCHRESET_MASK (0x1000000U)
#define USBPHY_DEBUG_ENSQUELCHRESET_SHIFT (24U)
/*! ENSQUELCHRESET - ENSQUELCHRESET
*/
#define USBPHY_DEBUG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_ENSQUELCHRESET_MASK)
#define USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT (25U)
/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
*/
#define USBPHY_DEBUG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT (29U)
/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
*/
#define USBPHY_DEBUG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_HOST_RESUME_DEBUG_MASK)
#define USBPHY_DEBUG_CLKGATE_MASK (0x40000000U)
#define USBPHY_DEBUG_CLKGATE_SHIFT (30U)
/*! CLKGATE - CLKGATE
*/
#define USBPHY_DEBUG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLKGATE_MASK)
/*! @} */
/*! @name DEBUG_SET - USB PHY Debug Register */
/*! @{ */
#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK (0x1U)
#define USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT (0U)
/*! OTGIDPIOLOCK - OTGIDPIOLOCK
*/
#define USBPHY_DEBUG_SET_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_SET_OTGIDPIOLOCK_MASK)
#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT (1U)
/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
*/
#define USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_SET_DEBUG_INTERFACE_HOLD_MASK)
#define USBPHY_DEBUG_SET_HSTPULLDOWN_MASK (0xCU)
#define USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT (2U)
/*! HSTPULLDOWN - HSTPULLDOWN
*/
#define USBPHY_DEBUG_SET_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK (0x30U)
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT (4U)
/*! ENHSTPULLDOWN - ENHSTPULLDOWN
*/
#define USBPHY_DEBUG_SET_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_SET_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_SET_TX2RXCOUNT_MASK (0xF00U)
#define USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT (8U)
/*! TX2RXCOUNT - TX2RXCOUNT
*/
#define USBPHY_DEBUG_SET_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK (0x1000U)
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT (12U)
/*! ENTX2RXCOUNT - ENTX2RXCOUNT
*/
#define USBPHY_DEBUG_SET_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_SET_ENTX2RXCOUNT_MASK)
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT (16U)
/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
*/
#define USBPHY_DEBUG_SET_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK (0x1000000U)
#define USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT (24U)
/*! ENSQUELCHRESET - ENSQUELCHRESET
*/
#define USBPHY_DEBUG_SET_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_SET_ENSQUELCHRESET_MASK)
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT (25U)
/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
*/
#define USBPHY_DEBUG_SET_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_SET_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT (29U)
/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
*/
#define USBPHY_DEBUG_SET_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_SET_HOST_RESUME_DEBUG_MASK)
#define USBPHY_DEBUG_SET_CLKGATE_MASK (0x40000000U)
#define USBPHY_DEBUG_SET_CLKGATE_SHIFT (30U)
/*! CLKGATE - CLKGATE
*/
#define USBPHY_DEBUG_SET_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_SET_CLKGATE_SHIFT)) & USBPHY_DEBUG_SET_CLKGATE_MASK)
/*! @} */
/*! @name DEBUG_CLR - USB PHY Debug Register */
/*! @{ */
#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK (0x1U)
#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT (0U)
/*! OTGIDPIOLOCK - OTGIDPIOLOCK
*/
#define USBPHY_DEBUG_CLR_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_CLR_OTGIDPIOLOCK_MASK)
#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT (1U)
/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
*/
#define USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_CLR_DEBUG_INTERFACE_HOLD_MASK)
#define USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK (0xCU)
#define USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT (2U)
/*! HSTPULLDOWN - HSTPULLDOWN
*/
#define USBPHY_DEBUG_CLR_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK (0x30U)
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT (4U)
/*! ENHSTPULLDOWN - ENHSTPULLDOWN
*/
#define USBPHY_DEBUG_CLR_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_CLR_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK (0xF00U)
#define USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT (8U)
/*! TX2RXCOUNT - TX2RXCOUNT
*/
#define USBPHY_DEBUG_CLR_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK (0x1000U)
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT (12U)
/*! ENTX2RXCOUNT - ENTX2RXCOUNT
*/
#define USBPHY_DEBUG_CLR_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_ENTX2RXCOUNT_MASK)
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT (16U)
/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
*/
#define USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK (0x1000000U)
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT (24U)
/*! ENSQUELCHRESET - ENSQUELCHRESET
*/
#define USBPHY_DEBUG_CLR_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_CLR_ENSQUELCHRESET_MASK)
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT (25U)
/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
*/
#define USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_CLR_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT (29U)
/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
*/
#define USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_CLR_HOST_RESUME_DEBUG_MASK)
#define USBPHY_DEBUG_CLR_CLKGATE_MASK (0x40000000U)
#define USBPHY_DEBUG_CLR_CLKGATE_SHIFT (30U)
/*! CLKGATE - CLKGATE
*/
#define USBPHY_DEBUG_CLR_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_CLR_CLKGATE_SHIFT)) & USBPHY_DEBUG_CLR_CLKGATE_MASK)
/*! @} */
/*! @name DEBUG_TOG - USB PHY Debug Register */
/*! @{ */
#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK (0x1U)
#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT (0U)
/*! OTGIDPIOLOCK - OTGIDPIOLOCK
*/
#define USBPHY_DEBUG_TOG_OTGIDPIOLOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_OTGIDPIOLOCK_SHIFT)) & USBPHY_DEBUG_TOG_OTGIDPIOLOCK_MASK)
#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK (0x2U)
#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT (1U)
/*! DEBUG_INTERFACE_HOLD - DEBUG_INTERFACE_HOLD
*/
#define USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_SHIFT)) & USBPHY_DEBUG_TOG_DEBUG_INTERFACE_HOLD_MASK)
#define USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK (0xCU)
#define USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT (2U)
/*! HSTPULLDOWN - HSTPULLDOWN
*/
#define USBPHY_DEBUG_TOG_HSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_HSTPULLDOWN_MASK)
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK (0x30U)
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT (4U)
/*! ENHSTPULLDOWN - ENHSTPULLDOWN
*/
#define USBPHY_DEBUG_TOG_ENHSTPULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENHSTPULLDOWN_SHIFT)) & USBPHY_DEBUG_TOG_ENHSTPULLDOWN_MASK)
#define USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK (0xF00U)
#define USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT (8U)
/*! TX2RXCOUNT - TX2RXCOUNT
*/
#define USBPHY_DEBUG_TOG_TX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_TX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_TX2RXCOUNT_MASK)
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK (0x1000U)
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT (12U)
/*! ENTX2RXCOUNT - ENTX2RXCOUNT
*/
#define USBPHY_DEBUG_TOG_ENTX2RXCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENTX2RXCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_ENTX2RXCOUNT_MASK)
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK (0x1F0000U)
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT (16U)
/*! SQUELCHRESETCOUNT - SQUELCHRESETCOUNT
*/
#define USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETCOUNT_MASK)
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK (0x1000000U)
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT (24U)
/*! ENSQUELCHRESET - ENSQUELCHRESET
*/
#define USBPHY_DEBUG_TOG_ENSQUELCHRESET(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_ENSQUELCHRESET_SHIFT)) & USBPHY_DEBUG_TOG_ENSQUELCHRESET_MASK)
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK (0x1E000000U)
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT (25U)
/*! SQUELCHRESETLENGTH - SQUELCHRESETLENGTH
*/
#define USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_SHIFT)) & USBPHY_DEBUG_TOG_SQUELCHRESETLENGTH_MASK)
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK (0x20000000U)
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT (29U)
/*! HOST_RESUME_DEBUG - HOST_RESUME_DEBUG
*/
#define USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_SHIFT)) & USBPHY_DEBUG_TOG_HOST_RESUME_DEBUG_MASK)
#define USBPHY_DEBUG_TOG_CLKGATE_MASK (0x40000000U)
#define USBPHY_DEBUG_TOG_CLKGATE_SHIFT (30U)
/*! CLKGATE - CLKGATE
*/
#define USBPHY_DEBUG_TOG_CLKGATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG_TOG_CLKGATE_SHIFT)) & USBPHY_DEBUG_TOG_CLKGATE_MASK)
/*! @} */
/*! @name DEBUG0_STATUS - UTMI Debug Status Register 0 */
/*! @{ */
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK (0xFFFFU)
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT (0U)
/*! LOOP_BACK_FAIL_COUNT - LOOP_BACK_FAIL_COUNT
*/
#define USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_LOOP_BACK_FAIL_COUNT_MASK)
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK (0x3FF0000U)
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT (16U)
/*! UTMI_RXERROR_FAIL_COUNT - UTMI_RXERROR_FAIL_COUNT
*/
#define USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_UTMI_RXERROR_FAIL_COUNT_MASK)
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK (0xFC000000U)
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT (26U)
/*! SQUELCH_COUNT - SQUELCH_COUNT
*/
#define USBPHY_DEBUG0_STATUS_SQUELCH_COUNT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_SHIFT)) & USBPHY_DEBUG0_STATUS_SQUELCH_COUNT_MASK)
/*! @} */
/*! @name DEBUG1 - UTMI Debug Status Register 1 */
/*! @{ */
#define USBPHY_DEBUG1_ENTAILADJVD_MASK (0x6000U)
#define USBPHY_DEBUG1_ENTAILADJVD_SHIFT (13U)
/*! ENTAILADJVD - ENTAILADJVD
* 0b00..Delay is nominal
* 0b01..Delay is +20%
* 0b10..Delay is -20%
* 0b11..Delay is -40%
*/
#define USBPHY_DEBUG1_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
*/
#define USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_SELFBIASOFF_MASK)
#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
*/
#define USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_PWDVBGUP_MASK)
#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT (17U)
/*! USB2_REFBIAS_LOWPWR - to be added
*/
#define USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_LOWPWR_MASK)
#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT (18U)
/*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
*/
#define USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_VBGADJ_MASK)
#define USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK (0x600000U)
#define USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT (21U)
/*! USB2_REFBIAS_TST - Bias current control for usb2_phy
*/
#define USBPHY_DEBUG1_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_USB2_REFBIAS_TST_MASK)
/*! @} */
/*! @name DEBUG1_SET - UTMI Debug Status Register 1 */
/*! @{ */
#define USBPHY_DEBUG1_SET_ENTAILADJVD_MASK (0x6000U)
#define USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT (13U)
/*! ENTAILADJVD - ENTAILADJVD
*/
#define USBPHY_DEBUG1_SET_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_SET_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
*/
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_SELFBIASOFF_MASK)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
*/
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_PWDVBGUP_MASK)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT (17U)
/*! USB2_REFBIAS_LOWPWR - to be added
*/
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_LOWPWR_MASK)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT (18U)
/*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
*/
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_VBGADJ_MASK)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK (0x600000U)
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT (21U)
/*! USB2_REFBIAS_TST - Bias current control for usb2_phy
*/
#define USBPHY_DEBUG1_SET_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_SET_USB2_REFBIAS_TST_MASK)
/*! @} */
/*! @name DEBUG1_CLR - UTMI Debug Status Register 1 */
/*! @{ */
#define USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK (0x6000U)
#define USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT (13U)
/*! ENTAILADJVD - ENTAILADJVD
*/
#define USBPHY_DEBUG1_CLR_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_CLR_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
*/
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_SELFBIASOFF_MASK)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
*/
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_PWDVBGUP_MASK)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT (17U)
/*! USB2_REFBIAS_LOWPWR - to be added
*/
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_LOWPWR_MASK)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT (18U)
/*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
*/
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_VBGADJ_MASK)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK (0x600000U)
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT (21U)
/*! USB2_REFBIAS_TST - Bias current control for usb2_phy
*/
#define USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_CLR_USB2_REFBIAS_TST_MASK)
/*! @} */
/*! @name DEBUG1_TOG - UTMI Debug Status Register 1 */
/*! @{ */
#define USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK (0x6000U)
#define USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT (13U)
/*! ENTAILADJVD - ENTAILADJVD
*/
#define USBPHY_DEBUG1_TOG_ENTAILADJVD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_ENTAILADJVD_SHIFT)) & USBPHY_DEBUG1_TOG_ENTAILADJVD_MASK)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK (0x8000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT (15U)
/*! USB2_REFBIAS_SELFBIASOFF - Set to 1 to disable self bias, 100 us after power up refbias(usb2_refbias_pwd).This can reduce noise on power.
*/
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_SELFBIASOFF_MASK)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK (0x10000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT (16U)
/*! USB2_REFBIAS_PWDVBGUP - Powers down the bandgap detect logic, will affect vbgup on misc1 register.
*/
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_PWDVBGUP_MASK)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK (0x20000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT (17U)
/*! USB2_REFBIAS_LOWPWR - to be added
*/
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_LOWPWR_MASK)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK (0x1C0000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT (18U)
/*! USB2_REFBIAS_VBGADJ - Adjustment bits on bandgap
*/
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_VBGADJ_MASK)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK (0x600000U)
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT (21U)
/*! USB2_REFBIAS_TST - Bias current control for usb2_phy
*/
#define USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_SHIFT)) & USBPHY_DEBUG1_TOG_USB2_REFBIAS_TST_MASK)
/*! @} */
/*! @name VERSION - UTMI RTL Version */
/*! @{ */
#define USBPHY_VERSION_STEP_MASK (0xFFFFU)
#define USBPHY_VERSION_STEP_SHIFT (0U)
/*! STEP - STEP
*/
#define USBPHY_VERSION_STEP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_STEP_SHIFT)) & USBPHY_VERSION_STEP_MASK)
#define USBPHY_VERSION_MINOR_MASK (0xFF0000U)
#define USBPHY_VERSION_MINOR_SHIFT (16U)
/*! MINOR - MINOR
*/
#define USBPHY_VERSION_MINOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MINOR_SHIFT)) & USBPHY_VERSION_MINOR_MASK)
#define USBPHY_VERSION_MAJOR_MASK (0xFF000000U)
#define USBPHY_VERSION_MAJOR_SHIFT (24U)
/*! MAJOR - MAJOR
*/
#define USBPHY_VERSION_MAJOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_VERSION_MAJOR_SHIFT)) & USBPHY_VERSION_MAJOR_MASK)
/*! @} */
/*! @name PLL_SIC - USB PHY PLL Control/Status Register */
/*! @{ */
#define USBPHY_PLL_SIC_PLL_POSTDIV_MASK (0x1CU)
#define USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT (2U)
/*! PLL_POSTDIV - PLL_POSTDIV
*/
#define USBPHY_PLL_SIC_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_PLL_POSTDIV_MASK)
#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK (0x40U)
#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT (6U)
/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
*/
#define USBPHY_PLL_SIC_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_PLL_EN_USB_CLKS_MASK)
#define USBPHY_PLL_SIC_PLL_POWER_MASK (0x1000U)
#define USBPHY_PLL_SIC_PLL_POWER_SHIFT (12U)
/*! PLL_POWER - PLL_POWER
*/
#define USBPHY_PLL_SIC_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_PLL_POWER_MASK)
#define USBPHY_PLL_SIC_PLL_ENABLE_MASK (0x2000U)
#define USBPHY_PLL_SIC_PLL_ENABLE_SHIFT (13U)
/*! PLL_ENABLE - PLL_ENABLE
*/
#define USBPHY_PLL_SIC_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_ENABLE_MASK)
#define USBPHY_PLL_SIC_PLL_BYPASS_MASK (0x10000U)
#define USBPHY_PLL_SIC_PLL_BYPASS_SHIFT (16U)
/*! PLL_BYPASS - PLL_BYPASS
*/
#define USBPHY_PLL_SIC_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_PLL_BYPASS_MASK)
#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK (0x80000U)
#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
* 0b0..Selects PLL_POWER to control the reference bias
* 0b1..Selects REFBIAS_PWD to control the reference bias.
*/
#define USBPHY_PLL_SIC_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_SEL_MASK)
#define USBPHY_PLL_SIC_REFBIAS_PWD_MASK (0x100000U)
#define USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT (20U)
/*! REFBIAS_PWD - Power down the reference bias
*/
#define USBPHY_PLL_SIC_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_REFBIAS_PWD_MASK)
#define USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK (0x200000U)
#define USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT (21U)
/*! PLL_REG_ENABLE - PLL_REG_ENABLE
*/
#define USBPHY_PLL_SIC_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_PLL_REG_ENABLE_MASK)
#define USBPHY_PLL_SIC_PLL_DIV_SEL_MASK (0x1C00000U)
#define USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT (22U)
/*! PLL_DIV_SEL - PLL_DIV_SEL
* 0b000..Divide by 13
* 0b001..Divide by 15
* 0b010..Divide by 16
* 0b011..Divide by 20
* 0b100..Divide by 22
* 0b101..Divide by 25
* 0b110..Divide by 30
* 0b111..Divide by 240
*/
#define USBPHY_PLL_SIC_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_PLL_DIV_SEL_MASK)
#define USBPHY_PLL_SIC_PLL_LOCK_MASK (0x80000000U)
#define USBPHY_PLL_SIC_PLL_LOCK_SHIFT (31U)
/*! PLL_LOCK - PLL_LOCK
* 0b0..PLL is not currently locked
* 0b1..PLL is currently locked
*/
#define USBPHY_PLL_SIC_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_PLL_LOCK_MASK)
/*! @} */
/*! @name PLL_SIC_SET - USB PHY PLL Control/Status Register */
/*! @{ */
#define USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK (0x1CU)
#define USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT (2U)
/*! PLL_POSTDIV - PLL_POSTDIV
*/
#define USBPHY_PLL_SIC_SET_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POSTDIV_MASK)
#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK (0x40U)
#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT (6U)
/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
*/
#define USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_EN_USB_CLKS_MASK)
#define USBPHY_PLL_SIC_SET_PLL_POWER_MASK (0x1000U)
#define USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT (12U)
/*! PLL_POWER - PLL_POWER
*/
#define USBPHY_PLL_SIC_SET_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_POWER_MASK)
#define USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK (0x2000U)
#define USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT (13U)
/*! PLL_ENABLE - PLL_ENABLE
*/
#define USBPHY_PLL_SIC_SET_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_ENABLE_MASK)
#define USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK (0x10000U)
#define USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT (16U)
/*! PLL_BYPASS - PLL_BYPASS
*/
#define USBPHY_PLL_SIC_SET_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_BYPASS_MASK)
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK (0x80000U)
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
*/
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_SEL_MASK)
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK (0x100000U)
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT (20U)
/*! REFBIAS_PWD - Power down the reference bias
*/
#define USBPHY_PLL_SIC_SET_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_SET_REFBIAS_PWD_MASK)
#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK (0x200000U)
#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT (21U)
/*! PLL_REG_ENABLE - PLL_REG_ENABLE
*/
#define USBPHY_PLL_SIC_SET_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_REG_ENABLE_MASK)
#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK (0x1C00000U)
#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT (22U)
/*! PLL_DIV_SEL - PLL_DIV_SEL
*/
#define USBPHY_PLL_SIC_SET_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_DIV_SEL_MASK)
#define USBPHY_PLL_SIC_SET_PLL_LOCK_MASK (0x80000000U)
#define USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT (31U)
/*! PLL_LOCK - PLL_LOCK
*/
#define USBPHY_PLL_SIC_SET_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_SET_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_SET_PLL_LOCK_MASK)
/*! @} */
/*! @name PLL_SIC_CLR - USB PHY PLL Control/Status Register */
/*! @{ */
#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK (0x1CU)
#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT (2U)
/*! PLL_POSTDIV - PLL_POSTDIV
*/
#define USBPHY_PLL_SIC_CLR_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POSTDIV_MASK)
#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK (0x40U)
#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT (6U)
/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
*/
#define USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_EN_USB_CLKS_MASK)
#define USBPHY_PLL_SIC_CLR_PLL_POWER_MASK (0x1000U)
#define USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT (12U)
/*! PLL_POWER - PLL_POWER
*/
#define USBPHY_PLL_SIC_CLR_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_POWER_MASK)
#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK (0x2000U)
#define USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT (13U)
/*! PLL_ENABLE - PLL_ENABLE
*/
#define USBPHY_PLL_SIC_CLR_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_ENABLE_MASK)
#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK (0x10000U)
#define USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT (16U)
/*! PLL_BYPASS - PLL_BYPASS
*/
#define USBPHY_PLL_SIC_CLR_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_BYPASS_MASK)
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK (0x80000U)
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
*/
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SEL_MASK)
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK (0x100000U)
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT (20U)
/*! REFBIAS_PWD - Power down the reference bias
*/
#define USBPHY_PLL_SIC_CLR_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_CLR_REFBIAS_PWD_MASK)
#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK (0x200000U)
#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT (21U)
/*! PLL_REG_ENABLE - PLL_REG_ENABLE
*/
#define USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_REG_ENABLE_MASK)
#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK (0x1C00000U)
#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT (22U)
/*! PLL_DIV_SEL - PLL_DIV_SEL
*/
#define USBPHY_PLL_SIC_CLR_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_DIV_SEL_MASK)
#define USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK (0x80000000U)
#define USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT (31U)
/*! PLL_LOCK - PLL_LOCK
*/
#define USBPHY_PLL_SIC_CLR_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_CLR_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_CLR_PLL_LOCK_MASK)
/*! @} */
/*! @name PLL_SIC_TOG - USB PHY PLL Control/Status Register */
/*! @{ */
#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK (0x1CU)
#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT (2U)
/*! PLL_POSTDIV - PLL_POSTDIV
*/
#define USBPHY_PLL_SIC_TOG_PLL_POSTDIV(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POSTDIV_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POSTDIV_MASK)
#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK (0x40U)
#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT (6U)
/*! PLL_EN_USB_CLKS - PLL_EN_USB_CLKS
*/
#define USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_EN_USB_CLKS_MASK)
#define USBPHY_PLL_SIC_TOG_PLL_POWER_MASK (0x1000U)
#define USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT (12U)
/*! PLL_POWER - PLL_POWER
*/
#define USBPHY_PLL_SIC_TOG_PLL_POWER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_POWER_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_POWER_MASK)
#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK (0x2000U)
#define USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT (13U)
/*! PLL_ENABLE - PLL_ENABLE
*/
#define USBPHY_PLL_SIC_TOG_PLL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_ENABLE_MASK)
#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK (0x10000U)
#define USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT (16U)
/*! PLL_BYPASS - PLL_BYPASS
*/
#define USBPHY_PLL_SIC_TOG_PLL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_BYPASS_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_BYPASS_MASK)
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK (0x80000U)
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT (19U)
/*! REFBIAS_PWD_SEL - REFBIAS_PWD_SEL
*/
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SEL_MASK)
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK (0x100000U)
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT (20U)
/*! REFBIAS_PWD - Power down the reference bias
*/
#define USBPHY_PLL_SIC_TOG_REFBIAS_PWD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_REFBIAS_PWD_SHIFT)) & USBPHY_PLL_SIC_TOG_REFBIAS_PWD_MASK)
#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK (0x200000U)
#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT (21U)
/*! PLL_REG_ENABLE - PLL_REG_ENABLE
*/
#define USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_REG_ENABLE_MASK)
#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK (0x1C00000U)
#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT (22U)
/*! PLL_DIV_SEL - PLL_DIV_SEL
*/
#define USBPHY_PLL_SIC_TOG_PLL_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_DIV_SEL_MASK)
#define USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK (0x80000000U)
#define USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT (31U)
/*! PLL_LOCK - PLL_LOCK
*/
#define USBPHY_PLL_SIC_TOG_PLL_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_PLL_SIC_TOG_PLL_LOCK_SHIFT)) & USBPHY_PLL_SIC_TOG_PLL_LOCK_MASK)
/*! @} */
/*! @name USB1_VBUS_DETECT - USB PHY VBUS Detect Control Register */
/*! @{ */
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID_THRESH
* 0b000..4.0 V
* 0b001..4.1 V
* 0b010..4.2 V
* 0b011..4.3 V
* 0b100..4.4 V (Default)
* 0b101..4.5 V
* 0b110..4.6 V
* 0b111..4.7 V
*/
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_THRESH_MASK)
#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
* 0b0..Use the results of the internal VBUS_VALID and Session Valid comparators for VBUS_VALID, AVALID, BVALID, and SESSEND (Default)
* 0b1..Use the override values for VBUS_VALID, AVALID, BVALID, and SESSEND
*/
#define USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_OVERRIDE_EN_MASK)
#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override value for SESSEND
*/
#define USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SESSEND_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override value for B-Device Session Valid
*/
#define USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_BVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override value for A-Device Session Valid
*/
#define USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_AVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
* 0b0..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
* 0b1..Use the VBUS_VALID_3V detector results for signal reported to the USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_SEL_MASK)
#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
* 0b00..Use the VBUS_VALID comparator results for signal reported to the USB controller (Default)
* 0b01..Use the Session Valid comparator results for signal reported to the USB controller
* 0b10..Use the Session Valid comparator results for signal reported to the USB controller
* 0b11..Reserved, do not use
*/
#define USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUS_SOURCE_SEL_MASK)
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT (11U)
/*! ID_OVERRIDE_EN - TBA
*/
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_EN_MASK)
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT (12U)
/*! ID_OVERRIDE - TBA
*/
#define USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_ID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
* 0b0..Use the VBUS_VALID comparator for VBUS_VALID results
* 0b1..Use the Session End comparator for VBUS_VALID results. The Session End threshold is >0.8V and <4.0V.
*/
#define USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_VBUSVALID_TO_SESSVALID_MASK)
#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
* 0b000..Powers down the VBUS_VALID comparator
* 0b001..Enables the SESS_VALID comparator (default)
* 0b010..Enables the 3Vdetect (default)
*/
#define USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_PWRUP_CMPS_MASK)
#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
* 0b0..VBUS discharge resistor is disabled (Default)
* 0b1..VBUS discharge resistor is enabled
*/
#define USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_DISCHARGE_VBUS_MASK)
#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
* 0b0..Disable resistive charger detection resistors on DP and DP
* 0b1..Enable resistive charger detection resistors on DP and DP
*/
#define USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_EN_CHARGER_RESISTOR_MASK)
/*! @} */
/*! @name USB1_VBUS_DETECT_SET - USB PHY VBUS Detect Control Register */
/*! @{ */
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID_THRESH
*/
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_THRESH_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
*/
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_OVERRIDE_EN_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override value for SESSEND
*/
#define USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_SESSEND_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override value for B-Device Session Valid
*/
#define USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_BVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override value for A-Device Session Valid
*/
#define USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_AVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_SEL_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUS_SOURCE_SEL_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT (11U)
/*! ID_OVERRIDE_EN - TBA
*/
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_EN_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT (12U)
/*! ID_OVERRIDE - TBA
*/
#define USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_ID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
*/
#define USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_VBUSVALID_TO_SESSVALID_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
*/
#define USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_PWRUP_CMPS_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
*/
#define USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_DISCHARGE_VBUS_MASK)
#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
*/
#define USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_SET_EN_CHARGER_RESISTOR_MASK)
/*! @} */
/*! @name USB1_VBUS_DETECT_CLR - USB PHY VBUS Detect Control Register */
/*! @{ */
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID_THRESH
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_THRESH_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_OVERRIDE_EN_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override value for SESSEND
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_SESSEND_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override value for B-Device Session Valid
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_BVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override value for A-Device Session Valid
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_AVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_SEL_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUS_SOURCE_SEL_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT (11U)
/*! ID_OVERRIDE_EN - TBA
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_EN_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT (12U)
/*! ID_OVERRIDE - TBA
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_ID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_VBUSVALID_TO_SESSVALID_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_PWRUP_CMPS_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_DISCHARGE_VBUS_MASK)
#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
*/
#define USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_CLR_EN_CHARGER_RESISTOR_MASK)
/*! @} */
/*! @name USB1_VBUS_DETECT_TOG - USB PHY VBUS Detect Control Register */
/*! @{ */
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK (0x7U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT (0U)
/*! VBUSVALID_THRESH - VBUSVALID_THRESH
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_THRESH_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK (0x8U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT (3U)
/*! VBUS_OVERRIDE_EN - VBUS detect signal override enable
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_OVERRIDE_EN_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK (0x10U)
#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT (4U)
/*! SESSEND_OVERRIDE - Override value for SESSEND
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_SESSEND_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK (0x20U)
#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT (5U)
/*! BVALID_OVERRIDE - Override value for B-Device Session Valid
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_BVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK (0x40U)
#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT (6U)
/*! AVALID_OVERRIDE - Override value for A-Device Session Valid
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_AVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK (0x80U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT (7U)
/*! VBUSVALID_OVERRIDE - Override value for VBUS_VALID signal sent to USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK (0x100U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT (8U)
/*! VBUSVALID_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_SEL_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK (0x600U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT (9U)
/*! VBUS_SOURCE_SEL - Selects the source of the VBUS_VALID signal reported to the USB controller
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUS_SOURCE_SEL_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK (0x800U)
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT (11U)
/*! ID_OVERRIDE_EN - TBA
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_EN_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK (0x1000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT (12U)
/*! ID_OVERRIDE - TBA
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_ID_OVERRIDE_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK (0x40000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT (18U)
/*! VBUSVALID_TO_SESSVALID - Selects the comparator used for VBUS_VALID
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_VBUSVALID_TO_SESSVALID_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK (0x700000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT (20U)
/*! PWRUP_CMPS - Enables the VBUS_VALID comparator
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_PWRUP_CMPS_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK (0x4000000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT (26U)
/*! DISCHARGE_VBUS - Controls VBUS discharge resistor
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_DISCHARGE_VBUS_MASK)
#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK (0x80000000U)
#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT (31U)
/*! EN_CHARGER_RESISTOR - Enables resistors used for an older method of resistive battery charger detection
*/
#define USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_SHIFT)) & USBPHY_USB1_VBUS_DETECT_TOG_EN_CHARGER_RESISTOR_MASK)
/*! @} */
/*! @name USB1_VBUS_DET_STAT - USB PHY VBUS Detector Status Register */
/*! @{ */
#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK (0x1U)
#define USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT (0U)
/*! SESSEND - Session End indicator
* 0b0..The VBUS voltage is above the Session Valid threshold
* 0b1..The VBUS voltage is below the Session Valid threshold
*/
#define USBPHY_USB1_VBUS_DET_STAT_SESSEND(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_SESSEND_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_SESSEND_MASK)
#define USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK (0x2U)
#define USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT (1U)
/*! BVALID - B-Device Session Valid status
* 0b0..The VBUS voltage is below the Session Valid threshold
* 0b1..The VBUS voltage is above the Session Valid threshold
*/
#define USBPHY_USB1_VBUS_DET_STAT_BVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_BVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_BVALID_MASK)
#define USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK (0x4U)
#define USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT (2U)
/*! AVALID - A-Device Session Valid status
* 0b0..The VBUS voltage is below the Session Valid threshold
* 0b1..The VBUS voltage is above the Session Valid threshold
*/
#define USBPHY_USB1_VBUS_DET_STAT_AVALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_AVALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_AVALID_MASK)
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK (0x8U)
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT (3U)
/*! VBUS_VALID - VBUS voltage status
* 0b0..VBUS is below the comparator threshold
* 0b1..VBUS is above the comparator threshold
*/
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_MASK)
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK (0x10U)
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT (4U)
/*! VBUS_VALID_3V - VBUS_VALID_3V detector status
* 0b0..VBUS voltage is below VBUS_VALID_3V threshold
* 0b1..VBUS voltage is above VBUS_VALID_3V threshold
*/
#define USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_SHIFT)) & USBPHY_USB1_VBUS_DET_STAT_VBUS_VALID_3V_MASK)
/*! @} */
/*! @name USB1_CHRG_DETECT - USB PHY Charger Detect Control Register */
/*! @{ */
#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK (0x4U)
#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT (2U)
/*! PULLUP_DP - PULLUP_DP
*/
#define USBPHY_USB1_CHRG_DETECT_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_PULLUP_DP_MASK)
#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT (23U)
/*! BGR_BIAS - BGR_BIAS
* 0b0..Use local bias powered from USB1_VBUS for 10uA reference (Default)
* 0b1..Use bandgap bias powered from VREGIN0/VREGIN1 for 10uA reference
*/
#define USBPHY_USB1_CHRG_DETECT_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_BGR_BIAS_MASK)
/*! @} */
/*! @name USB1_CHRG_DETECT_SET - USB PHY Charger Detect Control Register */
/*! @{ */
#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK (0x4U)
#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT (2U)
/*! PULLUP_DP - PULLUP_DP
*/
#define USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_PULLUP_DP_MASK)
#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT (23U)
/*! BGR_BIAS - BGR_BIAS
*/
#define USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_SET_BGR_BIAS_MASK)
/*! @} */
/*! @name USB1_CHRG_DETECT_CLR - USB PHY Charger Detect Control Register */
/*! @{ */
#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK (0x4U)
#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT (2U)
/*! PULLUP_DP - PULLUP_DP
*/
#define USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_PULLUP_DP_MASK)
#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT (23U)
/*! BGR_BIAS - BGR_BIAS
*/
#define USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_CLR_BGR_BIAS_MASK)
/*! @} */
/*! @name USB1_CHRG_DETECT_TOG - USB PHY Charger Detect Control Register */
/*! @{ */
#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK (0x4U)
#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT (2U)
/*! PULLUP_DP - PULLUP_DP
*/
#define USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_PULLUP_DP_MASK)
#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK (0x800000U)
#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT (23U)
/*! BGR_BIAS - BGR_BIAS
*/
#define USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_SHIFT)) & USBPHY_USB1_CHRG_DETECT_TOG_BGR_BIAS_MASK)
/*! @} */
/*! @name USB1_CHRG_DET_STAT - USB PHY Charger Detect Status Register */
/*! @{ */
#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK (0x1U)
#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT (0U)
/*! PLUG_CONTACT - Battery Charging Data Contact Detection phase output
* 0b0..No USB cable attachment has been detected
* 0b1..A USB cable attachment between the device and host has been detected
*/
#define USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_PLUG_CONTACT_MASK)
#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK (0x2U)
#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT (1U)
/*! CHRG_DETECTED - Battery Charging Primary Detection phase output
* 0b0..Standard Downstream Port (SDP) has been detected
* 0b1..Charging Port has been detected
*/
#define USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_CHRG_DETECTED_MASK)
#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK (0x4U)
#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT (2U)
/*! DN_STATE - DN_STATE
* 0b0..DN pin voltage is < 0.8V
* 0b1..DN pin voltage is > 2.0V
*/
#define USBPHY_USB1_CHRG_DET_STAT_DN_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DN_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DN_STATE_MASK)
#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK (0x8U)
#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT (3U)
/*! DP_STATE - DP_STATE
* 0b0..DP pin voltage is < 0.8V
* 0b1..DP pin voltage is > 2.0V
*/
#define USBPHY_USB1_CHRG_DET_STAT_DP_STATE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_DP_STATE_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_DP_STATE_MASK)
#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK (0x10U)
#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT (4U)
/*! SECDET_DCP - Battery Charging Secondary Detection phase output
* 0b0..Charging Downstream Port (CDP) has been detected
* 0b1..Downstream Charging Port (DCP) has been detected
*/
#define USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_SHIFT)) & USBPHY_USB1_CHRG_DET_STAT_SECDET_DCP_MASK)
/*! @} */
/*! @name ANACTRL - USB PHY Analog Control Register */
/*! @{ */
#define USBPHY_ANACTRL_DEV_PULLDOWN_MASK (0x400U)
#define USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT (10U)
/*! DEV_PULLDOWN - DEV_PULLDOWN
* 0b0..The 15kohm nominal pulldowns on the DP and DN pinsare disabled in device mode.
* 0b1..The 15kohm nominal pulldowns on the DP and DN pinsare enabled in device mode.
*/
#define USBPHY_ANACTRL_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_DEV_PULLDOWN_MASK)
/*! @} */
/*! @name ANACTRL_SET - USB PHY Analog Control Register */
/*! @{ */
#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK (0x400U)
#define USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT (10U)
/*! DEV_PULLDOWN - DEV_PULLDOWN
*/
#define USBPHY_ANACTRL_SET_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_SET_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_SET_DEV_PULLDOWN_MASK)
/*! @} */
/*! @name ANACTRL_CLR - USB PHY Analog Control Register */
/*! @{ */
#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK (0x400U)
#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT (10U)
/*! DEV_PULLDOWN - DEV_PULLDOWN
*/
#define USBPHY_ANACTRL_CLR_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_CLR_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_CLR_DEV_PULLDOWN_MASK)
/*! @} */
/*! @name ANACTRL_TOG - USB PHY Analog Control Register */
/*! @{ */
#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK (0x400U)
#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT (10U)
/*! DEV_PULLDOWN - DEV_PULLDOWN
*/
#define USBPHY_ANACTRL_TOG_DEV_PULLDOWN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_ANACTRL_TOG_DEV_PULLDOWN_SHIFT)) & USBPHY_ANACTRL_TOG_DEV_PULLDOWN_MASK)
/*! @} */
/*! @name USB1_LOOPBACK - USB PHY Loopback Control/Status Register */
/*! @{ */
#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI_TESTSTART
*/
#define USBPHY_USB1_LOOPBACK_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_TESTSTART_MASK)
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK (0x2U)
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI_DIG_TST0
*/
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST0_MASK)
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK (0x4U)
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI_DIG_TST1
*/
#define USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMI_DIG_TST1_MASK)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
*/
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HS_MODE_MASK)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
*/
#define USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_LS_MODE_MASK)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK (0x20U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT (5U)
/*! TSTI_TX_EN - TSTI_TX_EN
*/
#define USBPHY_USB1_LOOPBACK_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_EN_MASK)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK (0x40U)
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT (6U)
/*! TSTI_TX_HIZ - TSTI_TX_HIZ
*/
#define USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_TX_HIZ_MASK)
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK (0x80U)
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO_DIG_TST0
*/
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST0_MASK)
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK (0x100U)
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO_DIG_TST1
*/
#define USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_UTMO_DIG_TST1_MASK)
#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
*/
#define USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTI_HSFS_MODE_EN_MASK)
#define USBPHY_USB1_LOOPBACK_TSTPKT_MASK (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT (16U)
/*! TSTPKT - TSTPKT
*/
#define USBPHY_USB1_LOOPBACK_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TSTPKT_MASK)
/*! @} */
/*! @name USB1_LOOPBACK_SET - USB PHY Loopback Control/Status Register */
/*! @{ */
#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI_TESTSTART
*/
#define USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_TESTSTART_MASK)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK (0x2U)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI_DIG_TST0
*/
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST0_MASK)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK (0x4U)
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI_DIG_TST1
*/
#define USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMI_DIG_TST1_MASK)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
*/
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HS_MODE_MASK)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
*/
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_LS_MODE_MASK)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK (0x20U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT (5U)
/*! TSTI_TX_EN - TSTI_TX_EN
*/
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_EN_MASK)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK (0x40U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT (6U)
/*! TSTI_TX_HIZ - TSTI_TX_HIZ
*/
#define USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_TX_HIZ_MASK)
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK (0x80U)
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO_DIG_TST0
*/
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST0_MASK)
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK (0x100U)
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO_DIG_TST1
*/
#define USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_UTMO_DIG_TST1_MASK)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
*/
#define USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTI_HSFS_MODE_EN_MASK)
#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT (16U)
/*! TSTPKT - TSTPKT
*/
#define USBPHY_USB1_LOOPBACK_SET_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_SET_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_SET_TSTPKT_MASK)
/*! @} */
/*! @name USB1_LOOPBACK_CLR - USB PHY Loopback Control/Status Register */
/*! @{ */
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI_TESTSTART
*/
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_TESTSTART_MASK)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK (0x2U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI_DIG_TST0
*/
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST0_MASK)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK (0x4U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI_DIG_TST1
*/
#define USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMI_DIG_TST1_MASK)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
*/
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HS_MODE_MASK)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
*/
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_LS_MODE_MASK)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK (0x20U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT (5U)
/*! TSTI_TX_EN - TSTI_TX_EN
*/
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_EN_MASK)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK (0x40U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT (6U)
/*! TSTI_TX_HIZ - TSTI_TX_HIZ
*/
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_TX_HIZ_MASK)
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK (0x80U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO_DIG_TST0
*/
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST0_MASK)
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK (0x100U)
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO_DIG_TST1
*/
#define USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_UTMO_DIG_TST1_MASK)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
*/
#define USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTI_HSFS_MODE_EN_MASK)
#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT (16U)
/*! TSTPKT - TSTPKT
*/
#define USBPHY_USB1_LOOPBACK_CLR_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_CLR_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_CLR_TSTPKT_MASK)
/*! @} */
/*! @name USB1_LOOPBACK_TOG - USB PHY Loopback Control/Status Register */
/*! @{ */
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK (0x1U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT (0U)
/*! UTMI_TESTSTART - UTMI_TESTSTART
*/
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_TESTSTART_MASK)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK (0x2U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT (1U)
/*! UTMI_DIG_TST0 - UTMI_DIG_TST0
*/
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST0_MASK)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK (0x4U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT (2U)
/*! UTMI_DIG_TST1 - UTMI_DIG_TST1
*/
#define USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMI_DIG_TST1_MASK)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK (0x8U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT (3U)
/*! TSTI_TX_HS_MODE - TSTI_TX_HS_MODE
*/
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HS_MODE_MASK)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK (0x10U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT (4U)
/*! TSTI_TX_LS_MODE - TSTI_TX_LS_MODE
*/
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_LS_MODE_MASK)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK (0x20U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT (5U)
/*! TSTI_TX_EN - TSTI_TX_EN
*/
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_EN_MASK)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK (0x40U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT (6U)
/*! TSTI_TX_HIZ - TSTI_TX_HIZ
*/
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_TX_HIZ_MASK)
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK (0x80U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT (7U)
/*! UTMO_DIG_TST0 - UTMO_DIG_TST0
*/
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST0_MASK)
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK (0x100U)
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT (8U)
/*! UTMO_DIG_TST1 - UTMO_DIG_TST1
*/
#define USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_UTMO_DIG_TST1_MASK)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK (0x8000U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT (15U)
/*! TSTI_HSFS_MODE_EN - TSTI_HSFS_MODE_EN
*/
#define USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTI_HSFS_MODE_EN_MASK)
#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK (0xFF0000U)
#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT (16U)
/*! TSTPKT - TSTPKT
*/
#define USBPHY_USB1_LOOPBACK_TOG_TSTPKT(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_TOG_TSTPKT_SHIFT)) & USBPHY_USB1_LOOPBACK_TOG_TSTPKT_MASK)
/*! @} */
/*! @name USB1_LOOPBACK_HSFSCNT - USB PHY Loopback Packet Number Select Register */
/*! @{ */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
*/
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_HS_NUMBER_MASK)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
*/
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TSTI_FS_NUMBER_MASK)
/*! @} */
/*! @name USB1_LOOPBACK_HSFSCNT_SET - USB PHY Loopback Packet Number Select Register */
/*! @{ */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
*/
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_HS_NUMBER_MASK)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
*/
#define USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_SET_TSTI_FS_NUMBER_MASK)
/*! @} */
/*! @name USB1_LOOPBACK_HSFSCNT_CLR - USB PHY Loopback Packet Number Select Register */
/*! @{ */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
*/
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_HS_NUMBER_MASK)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
*/
#define USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_CLR_TSTI_FS_NUMBER_MASK)
/*! @} */
/*! @name USB1_LOOPBACK_HSFSCNT_TOG - USB PHY Loopback Packet Number Select Register */
/*! @{ */
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK (0xFFFFU)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT (0U)
/*! TSTI_HS_NUMBER - TSTI_HS_NUMBER
*/
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_HS_NUMBER_MASK)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK (0xFFFF0000U)
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT (16U)
/*! TSTI_FS_NUMBER - TSTI_FS_NUMBER
*/
#define USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_SHIFT)) & USBPHY_USB1_LOOPBACK_HSFSCNT_TOG_TSTI_FS_NUMBER_MASK)
/*! @} */
/*! @name TRIM_OVERRIDE_EN - USB PHY Trim Override Enable Register */
/*! @{ */
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_DIV_SEL_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_D_CAL_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DP_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_TX_CAL45DN_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_REFBIAS_TST_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_VBGADJ_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB2_REFBIAS_TST_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_PLL_CTRL0_DIV_SEL_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_D_CAL_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DP_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
*/
#define USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */
/*! @name TRIM_OVERRIDE_EN_SET - USB PHY Trim Override Enable Register */
/*! @{ */
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_DIV_SEL_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_D_CAL_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DP_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_TX_CAL45DN_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_REFBIAS_TST_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_VBGADJ_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB2_REFBIAS_TST_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_PLL_CTRL0_DIV_SEL_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_D_CAL_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DP_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
*/
#define USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_SET_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */
/*! @name TRIM_OVERRIDE_EN_CLR - USB PHY Trim Override Enable Register */
/*! @{ */
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_DIV_SEL_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_D_CAL_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DP_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_TX_CAL45DN_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_REFBIAS_TST_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_VBGADJ_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB2_REFBIAS_TST_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_PLL_CTRL0_DIV_SEL_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_D_CAL_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DP_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
*/
#define USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_CLR_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */
/*! @name TRIM_OVERRIDE_EN_TOG - USB PHY Trim Override Enable Register */
/*! @{ */
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK (0x1U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT (0U)
/*! TRIM_DIV_SEL_OVERRIDE - TRIM_DIV_SEL_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_DIV_SEL_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK (0x2U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT (1U)
/*! TRIM_ENV_TAIL_ADJ_VD_OVERRIDE - TRIM_ENV_TAIL_ADJ_VD_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_ENV_TAIL_ADJ_VD_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK (0x4U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT (2U)
/*! TRIM_TX_D_CAL_OVERRIDE - TRIM_TX_D_CAL_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_D_CAL_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK (0x8U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT (3U)
/*! TRIM_TX_CAL45DP_OVERRIDE - TRIM_TX_CAL45DP_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DP_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK (0x10U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT (4U)
/*! TRIM_TX_CAL45DN_OVERRIDE - TRIM_TX_CAL45DN_OVERRIDE
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_TX_CAL45DN_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK (0x20U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT (5U)
/*! TRIM_REFBIAS_VBGADJ_OVERRIDE - Override enable for bandgap adjustment.
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_VBGADJ_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK (0x40U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT (6U)
/*! TRIM_REFBIAS_TST_OVERRIDE - Override enable for bias current control
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_REFBIAS_TST_OVERRIDE_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK (0x1C00U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT (10U)
/*! TRIM_USB2_REFBIAS_VBGADJ - TRIM_USB2_REFBIAS_VBGADJ
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_VBGADJ_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK (0x6000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT (13U)
/*! TRIM_USB2_REFBIAS_TST - TRIM_USB2_REFBIAS_TST
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB2_REFBIAS_TST_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK (0x38000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT (15U)
/*! TRIM_PLL_CTRL0_DIV_SEL - TRIM_PLL_CTRL0_DIV_SEL
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_PLL_CTRL0_DIV_SEL_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK (0xC0000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT (18U)
/*! TRIM_USB_REG_ENV_TAIL_ADJ_VD - TRIM_USB_REG_ENV_TAIL_ADJ_VD
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USB_REG_ENV_TAIL_ADJ_VD_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK (0xF00000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT (20U)
/*! TRIM_USBPHY_TX_D_CAL - TRIM_USBPHY_TX_D_CAL
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_D_CAL_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK (0xF000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT (24U)
/*! TRIM_USBPHY_TX_CAL45DP - TRIM_USBPHY_TX_CAL45DP
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DP_MASK)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK (0xF0000000U)
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT (28U)
/*! TRIM_USBPHY_TX_CAL45DN - TRIM_USBPHY_TX_CAL45DN
*/
#define USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN(x) (((uint32_t)(((uint32_t)(x)) << USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_SHIFT)) & USBPHY_TRIM_OVERRIDE_EN_TOG_TRIM_USBPHY_TX_CAL45DN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group USBPHY_Register_Masks */
/* USBPHY - Peripheral instance base addresses */
/** Peripheral USBPHY1 base address */
#define USBPHY1_BASE (0x40434000u)
/** Peripheral USBPHY1 base pointer */
#define USBPHY1 ((USBPHY_Type *)USBPHY1_BASE)
/** Peripheral USBPHY2 base address */
#define USBPHY2_BASE (0x40438000u)
/** Peripheral USBPHY2 base pointer */
#define USBPHY2 ((USBPHY_Type *)USBPHY2_BASE)
/** Array initializer of USBPHY peripheral base addresses */
#define USBPHY_BASE_ADDRS { 0u, USBPHY1_BASE, USBPHY2_BASE }
/** Array initializer of USBPHY peripheral base pointers */
#define USBPHY_BASE_PTRS { (USBPHY_Type *)0u, USBPHY1, USBPHY2 }
/** Interrupt vectors for the USBPHY peripheral type */
#define USBPHY_IRQS { NotAvail_IRQn, USBPHY1_IRQn, USBPHY2_IRQn }
/* Backward compatibility */
#define USBPHY_CTRL_ENDEVPLUGINDET_MASK USBPHY_CTRL_ENDEVPLUGINDETECT_MASK
#define USBPHY_CTRL_ENDEVPLUGINDET_SHIFT USBPHY_CTRL_ENDEVPLUGINDETECT_SHIFT
#define USBPHY_CTRL_ENDEVPLUGINDET(x) USBPHY_CTRL_ENDEVPLUGINDETECT(x)
#define USBPHY_TX_TXCAL45DM_MASK USBPHY_TX_TXCAL45DN_MASK
#define USBPHY_TX_TXCAL45DM_SHIFT USBPHY_TX_TXCAL45DN_SHIFT
#define USBPHY_TX_TXCAL45DM(x) USBPHY_TX_TXCAL45DN(x)
/*!
* @}
*/ /* end of group USBPHY_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- USDHC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup USDHC_Peripheral_Access_Layer USDHC Peripheral Access Layer
* @{
*/
/** USDHC - Register Layout Typedef */
typedef struct {
__IO uint32_t DS_ADDR; /**< DMA System Address, offset: 0x0 */
__IO uint32_t BLK_ATT; /**< Block Attributes, offset: 0x4 */
__IO uint32_t CMD_ARG; /**< Command Argument, offset: 0x8 */
__IO uint32_t CMD_XFR_TYP; /**< Command Transfer Type, offset: 0xC */
__I uint32_t CMD_RSP0; /**< Command Response0, offset: 0x10 */
__I uint32_t CMD_RSP1; /**< Command Response1, offset: 0x14 */
__I uint32_t CMD_RSP2; /**< Command Response2, offset: 0x18 */
__I uint32_t CMD_RSP3; /**< Command Response3, offset: 0x1C */
__IO uint32_t DATA_BUFF_ACC_PORT; /**< Data Buffer Access Port, offset: 0x20 */
__I uint32_t PRES_STATE; /**< Present State, offset: 0x24 */
__IO uint32_t PROT_CTRL; /**< Protocol Control, offset: 0x28 */
__IO uint32_t SYS_CTRL; /**< System Control, offset: 0x2C */
__IO uint32_t INT_STATUS; /**< Interrupt Status, offset: 0x30 */
__IO uint32_t INT_STATUS_EN; /**< Interrupt Status Enable, offset: 0x34 */
__IO uint32_t INT_SIGNAL_EN; /**< Interrupt Signal Enable, offset: 0x38 */
__IO uint32_t AUTOCMD12_ERR_STATUS; /**< Auto CMD12 Error Status, offset: 0x3C */
__IO uint32_t HOST_CTRL_CAP; /**< Host Controller Capabilities, offset: 0x40 */
__IO uint32_t WTMK_LVL; /**< Watermark Level, offset: 0x44 */
__IO uint32_t MIX_CTRL; /**< Mixer Control, offset: 0x48 */
uint8_t RESERVED_0[4];
__O uint32_t FORCE_EVENT; /**< Force Event, offset: 0x50 */
__I uint32_t ADMA_ERR_STATUS; /**< ADMA Error Status, offset: 0x54 */
__IO uint32_t ADMA_SYS_ADDR; /**< ADMA System Address, offset: 0x58 */
uint8_t RESERVED_1[4];
__IO uint32_t DLL_CTRL; /**< DLL (Delay Line) Control, offset: 0x60 */
__I uint32_t DLL_STATUS; /**< DLL Status, offset: 0x64 */
__IO uint32_t CLK_TUNE_CTRL_STATUS; /**< CLK Tuning Control and Status, offset: 0x68 */
uint8_t RESERVED_2[4];
__IO uint32_t STROBE_DLL_CTRL; /**< Strobe DLL control, offset: 0x70 */
__I uint32_t STROBE_DLL_STATUS; /**< Strobe DLL status, offset: 0x74 */
uint8_t RESERVED_3[72];
__IO uint32_t VEND_SPEC; /**< Vendor Specific Register, offset: 0xC0 */
__IO uint32_t MMC_BOOT; /**< MMC Boot, offset: 0xC4 */
__IO uint32_t VEND_SPEC2; /**< Vendor Specific 2 Register, offset: 0xC8 */
__IO uint32_t TUNING_CTRL; /**< Tuning Control, offset: 0xCC */
} USDHC_Type;
/* ----------------------------------------------------------------------------
-- USDHC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup USDHC_Register_Masks USDHC Register Masks
* @{
*/
/*! @name DS_ADDR - DMA System Address */
/*! @{ */
#define USDHC_DS_ADDR_DS_ADDR_MASK (0xFFFFFFFFU)
#define USDHC_DS_ADDR_DS_ADDR_SHIFT (0U)
/*! DS_ADDR - System address
*/
#define USDHC_DS_ADDR_DS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DS_ADDR_DS_ADDR_SHIFT)) & USDHC_DS_ADDR_DS_ADDR_MASK)
/*! @} */
/*! @name BLK_ATT - Block Attributes */
/*! @{ */
#define USDHC_BLK_ATT_BLKSIZE_MASK (0x1FFFU)
#define USDHC_BLK_ATT_BLKSIZE_SHIFT (0U)
/*! BLKSIZE - Transfer block size
* 0b1000000000000..4096 bytes
* 0b0100000000000..2048 bytes
* 0b0001000000000..512 bytes
* 0b0000111111111..511 bytes
* 0b0000000000100..4 bytes
* 0b0000000000011..3 bytes
* 0b0000000000010..2 bytes
* 0b0000000000001..1 byte
* 0b0000000000000..No data transfer
*/
#define USDHC_BLK_ATT_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKSIZE_SHIFT)) & USDHC_BLK_ATT_BLKSIZE_MASK)
#define USDHC_BLK_ATT_BLKCNT_MASK (0xFFFF0000U)
#define USDHC_BLK_ATT_BLKCNT_SHIFT (16U)
/*! BLKCNT - Blocks count for current transfer
* 0b1111111111111111..65535 blocks
* 0b0000000000000010..2 blocks
* 0b0000000000000001..1 block
* 0b0000000000000000..Stop count
*/
#define USDHC_BLK_ATT_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_BLK_ATT_BLKCNT_SHIFT)) & USDHC_BLK_ATT_BLKCNT_MASK)
/*! @} */
/*! @name CMD_ARG - Command Argument */
/*! @{ */
#define USDHC_CMD_ARG_CMDARG_MASK (0xFFFFFFFFU)
#define USDHC_CMD_ARG_CMDARG_SHIFT (0U)
/*! CMDARG - Command argument
*/
#define USDHC_CMD_ARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_ARG_CMDARG_SHIFT)) & USDHC_CMD_ARG_CMDARG_MASK)
/*! @} */
/*! @name CMD_XFR_TYP - Command Transfer Type */
/*! @{ */
#define USDHC_CMD_XFR_TYP_RSPTYP_MASK (0x30000U)
#define USDHC_CMD_XFR_TYP_RSPTYP_SHIFT (16U)
/*! RSPTYP - Response type select
* 0b00..No response
* 0b01..Response length 136
* 0b10..Response length 48
* 0b11..Response length 48, check busy after response
*/
#define USDHC_CMD_XFR_TYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_RSPTYP_SHIFT)) & USDHC_CMD_XFR_TYP_RSPTYP_MASK)
#define USDHC_CMD_XFR_TYP_CCCEN_MASK (0x80000U)
#define USDHC_CMD_XFR_TYP_CCCEN_SHIFT (19U)
/*! CCCEN - Command CRC check enable
* 0b1..Enables command CRC check
* 0b0..Disables command CRC check
*/
#define USDHC_CMD_XFR_TYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CCCEN_SHIFT)) & USDHC_CMD_XFR_TYP_CCCEN_MASK)
#define USDHC_CMD_XFR_TYP_CICEN_MASK (0x100000U)
#define USDHC_CMD_XFR_TYP_CICEN_SHIFT (20U)
/*! CICEN - Command index check enable
* 0b1..Enables command index check
* 0b0..Disable command index check
*/
#define USDHC_CMD_XFR_TYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CICEN_SHIFT)) & USDHC_CMD_XFR_TYP_CICEN_MASK)
#define USDHC_CMD_XFR_TYP_DPSEL_MASK (0x200000U)
#define USDHC_CMD_XFR_TYP_DPSEL_SHIFT (21U)
/*! DPSEL - Data present select
* 0b1..Data present
* 0b0..No data present
*/
#define USDHC_CMD_XFR_TYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_DPSEL_SHIFT)) & USDHC_CMD_XFR_TYP_DPSEL_MASK)
#define USDHC_CMD_XFR_TYP_CMDTYP_MASK (0xC00000U)
#define USDHC_CMD_XFR_TYP_CMDTYP_SHIFT (22U)
/*! CMDTYP - Command type
* 0b11..Abort CMD12, CMD52 for writing I/O Abort in CCCR
* 0b10..Resume CMD52 for writing function select in CCCR
* 0b01..Suspend CMD52 for writing bus suspend in CCCR
* 0b00..Normal other commands
*/
#define USDHC_CMD_XFR_TYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDTYP_SHIFT)) & USDHC_CMD_XFR_TYP_CMDTYP_MASK)
#define USDHC_CMD_XFR_TYP_CMDINX_MASK (0x3F000000U)
#define USDHC_CMD_XFR_TYP_CMDINX_SHIFT (24U)
/*! CMDINX - Command index
*/
#define USDHC_CMD_XFR_TYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_XFR_TYP_CMDINX_SHIFT)) & USDHC_CMD_XFR_TYP_CMDINX_MASK)
/*! @} */
/*! @name CMD_RSP0 - Command Response0 */
/*! @{ */
#define USDHC_CMD_RSP0_CMDRSP0_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP0_CMDRSP0_SHIFT (0U)
/*! CMDRSP0 - Command response 0
*/
#define USDHC_CMD_RSP0_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP0_CMDRSP0_SHIFT)) & USDHC_CMD_RSP0_CMDRSP0_MASK)
/*! @} */
/*! @name CMD_RSP1 - Command Response1 */
/*! @{ */
#define USDHC_CMD_RSP1_CMDRSP1_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP1_CMDRSP1_SHIFT (0U)
/*! CMDRSP1 - Command response 1
*/
#define USDHC_CMD_RSP1_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP1_CMDRSP1_SHIFT)) & USDHC_CMD_RSP1_CMDRSP1_MASK)
/*! @} */
/*! @name CMD_RSP2 - Command Response2 */
/*! @{ */
#define USDHC_CMD_RSP2_CMDRSP2_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP2_CMDRSP2_SHIFT (0U)
/*! CMDRSP2 - Command response 2
*/
#define USDHC_CMD_RSP2_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP2_CMDRSP2_SHIFT)) & USDHC_CMD_RSP2_CMDRSP2_MASK)
/*! @} */
/*! @name CMD_RSP3 - Command Response3 */
/*! @{ */
#define USDHC_CMD_RSP3_CMDRSP3_MASK (0xFFFFFFFFU)
#define USDHC_CMD_RSP3_CMDRSP3_SHIFT (0U)
/*! CMDRSP3 - Command response 3
*/
#define USDHC_CMD_RSP3_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CMD_RSP3_CMDRSP3_SHIFT)) & USDHC_CMD_RSP3_CMDRSP3_MASK)
/*! @} */
/*! @name DATA_BUFF_ACC_PORT - Data Buffer Access Port */
/*! @{ */
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK (0xFFFFFFFFU)
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT (0U)
/*! DATCONT - Data content
*/
#define USDHC_DATA_BUFF_ACC_PORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DATA_BUFF_ACC_PORT_DATCONT_SHIFT)) & USDHC_DATA_BUFF_ACC_PORT_DATCONT_MASK)
/*! @} */
/*! @name PRES_STATE - Present State */
/*! @{ */
#define USDHC_PRES_STATE_CIHB_MASK (0x1U)
#define USDHC_PRES_STATE_CIHB_SHIFT (0U)
/*! CIHB - Command inhibit (CMD)
* 0b1..Cannot issue command
* 0b0..Can issue command using only CMD line
*/
#define USDHC_PRES_STATE_CIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CIHB_SHIFT)) & USDHC_PRES_STATE_CIHB_MASK)
#define USDHC_PRES_STATE_CDIHB_MASK (0x2U)
#define USDHC_PRES_STATE_CDIHB_SHIFT (1U)
/*! CDIHB - Command Inhibit Data (DATA)
* 0b1..Cannot issue command that uses the DATA line
* 0b0..Can issue command that uses the DATA line
*/
#define USDHC_PRES_STATE_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDIHB_SHIFT)) & USDHC_PRES_STATE_CDIHB_MASK)
#define USDHC_PRES_STATE_DLA_MASK (0x4U)
#define USDHC_PRES_STATE_DLA_SHIFT (2U)
/*! DLA - Data line active
* 0b1..DATA line active
* 0b0..DATA line inactive
*/
#define USDHC_PRES_STATE_DLA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLA_SHIFT)) & USDHC_PRES_STATE_DLA_MASK)
#define USDHC_PRES_STATE_SDSTB_MASK (0x8U)
#define USDHC_PRES_STATE_SDSTB_SHIFT (3U)
/*! SDSTB - SD clock stable
* 0b1..Clock is stable.
* 0b0..Clock is changing frequency and not stable.
*/
#define USDHC_PRES_STATE_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDSTB_SHIFT)) & USDHC_PRES_STATE_SDSTB_MASK)
#define USDHC_PRES_STATE_IPGOFF_MASK (0x10U)
#define USDHC_PRES_STATE_IPGOFF_SHIFT (4U)
/*! IPGOFF - Peripheral clock gated off internally
* 0b1..Peripheral clock is gated off.
* 0b0..Peripheral clock is active.
*/
#define USDHC_PRES_STATE_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_IPGOFF_SHIFT)) & USDHC_PRES_STATE_IPGOFF_MASK)
#define USDHC_PRES_STATE_HCKOFF_MASK (0x20U)
#define USDHC_PRES_STATE_HCKOFF_SHIFT (5U)
/*! HCKOFF - HCLK gated off internally
* 0b1..HCLK is gated off.
* 0b0..HCLK is active.
*/
#define USDHC_PRES_STATE_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_HCKOFF_SHIFT)) & USDHC_PRES_STATE_HCKOFF_MASK)
#define USDHC_PRES_STATE_PEROFF_MASK (0x40U)
#define USDHC_PRES_STATE_PEROFF_SHIFT (6U)
/*! PEROFF - IPG_PERCLK gated off internally
* 0b1..IPG_PERCLK is gated off.
* 0b0..IPG_PERCLK is active.
*/
#define USDHC_PRES_STATE_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_PEROFF_SHIFT)) & USDHC_PRES_STATE_PEROFF_MASK)
#define USDHC_PRES_STATE_SDOFF_MASK (0x80U)
#define USDHC_PRES_STATE_SDOFF_SHIFT (7U)
/*! SDOFF - SD clock gated off internally
* 0b1..SD clock is gated off.
* 0b0..SD clock is active.
*/
#define USDHC_PRES_STATE_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_SDOFF_SHIFT)) & USDHC_PRES_STATE_SDOFF_MASK)
#define USDHC_PRES_STATE_WTA_MASK (0x100U)
#define USDHC_PRES_STATE_WTA_SHIFT (8U)
/*! WTA - Write transfer active
* 0b1..Transferring data
* 0b0..No valid data
*/
#define USDHC_PRES_STATE_WTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WTA_SHIFT)) & USDHC_PRES_STATE_WTA_MASK)
#define USDHC_PRES_STATE_RTA_MASK (0x200U)
#define USDHC_PRES_STATE_RTA_SHIFT (9U)
/*! RTA - Read transfer active
* 0b1..Transferring data
* 0b0..No valid data
*/
#define USDHC_PRES_STATE_RTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTA_SHIFT)) & USDHC_PRES_STATE_RTA_MASK)
#define USDHC_PRES_STATE_BWEN_MASK (0x400U)
#define USDHC_PRES_STATE_BWEN_SHIFT (10U)
/*! BWEN - Buffer write enable
* 0b1..Write enable
* 0b0..Write disable
*/
#define USDHC_PRES_STATE_BWEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BWEN_SHIFT)) & USDHC_PRES_STATE_BWEN_MASK)
#define USDHC_PRES_STATE_BREN_MASK (0x800U)
#define USDHC_PRES_STATE_BREN_SHIFT (11U)
/*! BREN - Buffer read enable
* 0b1..Read enable
* 0b0..Read disable
*/
#define USDHC_PRES_STATE_BREN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_BREN_SHIFT)) & USDHC_PRES_STATE_BREN_MASK)
#define USDHC_PRES_STATE_RTR_MASK (0x1000U)
#define USDHC_PRES_STATE_RTR_SHIFT (12U)
/*! RTR - Re-Tuning Request (only for SD3.0 SDR104 mode,and EMMC HS200 mode)
* 0b1..Sampling clock needs re-tuning
* 0b0..Fixed or well tuned sampling clock
*/
#define USDHC_PRES_STATE_RTR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_RTR_SHIFT)) & USDHC_PRES_STATE_RTR_MASK)
#define USDHC_PRES_STATE_TSCD_MASK (0x8000U)
#define USDHC_PRES_STATE_TSCD_SHIFT (15U)
/*! TSCD - Tap select change done
* 0b1..Delay cell select change is finished.
* 0b0..Delay cell select change is not finished.
*/
#define USDHC_PRES_STATE_TSCD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_TSCD_SHIFT)) & USDHC_PRES_STATE_TSCD_MASK)
#define USDHC_PRES_STATE_CINST_MASK (0x10000U)
#define USDHC_PRES_STATE_CINST_SHIFT (16U)
/*! CINST - Card inserted
* 0b1..Card inserted
* 0b0..Power on reset or no card
*/
#define USDHC_PRES_STATE_CINST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CINST_SHIFT)) & USDHC_PRES_STATE_CINST_MASK)
#define USDHC_PRES_STATE_CDPL_MASK (0x40000U)
#define USDHC_PRES_STATE_CDPL_SHIFT (18U)
/*! CDPL - Card detect pin level
* 0b1..Card present (CD_B = 0)
* 0b0..No card present (CD_B = 1)
*/
#define USDHC_PRES_STATE_CDPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CDPL_SHIFT)) & USDHC_PRES_STATE_CDPL_MASK)
#define USDHC_PRES_STATE_WPSPL_MASK (0x80000U)
#define USDHC_PRES_STATE_WPSPL_SHIFT (19U)
/*! WPSPL - Write protect switch pin level
* 0b1..Write enabled (WP = 0)
* 0b0..Write protected (WP = 1)
*/
#define USDHC_PRES_STATE_WPSPL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_WPSPL_SHIFT)) & USDHC_PRES_STATE_WPSPL_MASK)
#define USDHC_PRES_STATE_CLSL_MASK (0x800000U)
#define USDHC_PRES_STATE_CLSL_SHIFT (23U)
/*! CLSL - CMD line signal level
*/
#define USDHC_PRES_STATE_CLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_CLSL_SHIFT)) & USDHC_PRES_STATE_CLSL_MASK)
#define USDHC_PRES_STATE_DLSL_MASK (0xFF000000U)
#define USDHC_PRES_STATE_DLSL_SHIFT (24U)
/*! DLSL - DATA[7:0] line signal level
* 0b00000111..Data 7 line signal level
* 0b00000110..Data 6 line signal level
* 0b00000101..Data 5 line signal level
* 0b00000100..Data 4 line signal level
* 0b00000011..Data 3 line signal level
* 0b00000010..Data 2 line signal level
* 0b00000001..Data 1 line signal level
* 0b00000000..Data 0 line signal level
*/
#define USDHC_PRES_STATE_DLSL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PRES_STATE_DLSL_SHIFT)) & USDHC_PRES_STATE_DLSL_MASK)
/*! @} */
/*! @name PROT_CTRL - Protocol Control */
/*! @{ */
#define USDHC_PROT_CTRL_DTW_MASK (0x6U)
#define USDHC_PROT_CTRL_DTW_SHIFT (1U)
/*! DTW - Data transfer width
* 0b10..8-bit mode
* 0b01..4-bit mode
* 0b00..1-bit mode
* 0b11..Reserved
*/
#define USDHC_PROT_CTRL_DTW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DTW_SHIFT)) & USDHC_PROT_CTRL_DTW_MASK)
#define USDHC_PROT_CTRL_D3CD_MASK (0x8U)
#define USDHC_PROT_CTRL_D3CD_SHIFT (3U)
/*! D3CD - DATA3 as card detection pin
* 0b1..DATA3 as card detection pin
* 0b0..DATA3 does not monitor card insertion
*/
#define USDHC_PROT_CTRL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_D3CD_SHIFT)) & USDHC_PROT_CTRL_D3CD_MASK)
#define USDHC_PROT_CTRL_EMODE_MASK (0x30U)
#define USDHC_PROT_CTRL_EMODE_SHIFT (4U)
/*! EMODE - Endian mode
* 0b00..Big endian mode
* 0b01..Half word big endian mode
* 0b10..Little endian mode
* 0b11..Reserved
*/
#define USDHC_PROT_CTRL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_EMODE_SHIFT)) & USDHC_PROT_CTRL_EMODE_MASK)
#define USDHC_PROT_CTRL_CDTL_MASK (0x40U)
#define USDHC_PROT_CTRL_CDTL_SHIFT (6U)
/*! CDTL - Card detect test level
* 0b1..Card detect test level is 1, card inserted
* 0b0..Card detect test level is 0, no card inserted
*/
#define USDHC_PROT_CTRL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDTL_SHIFT)) & USDHC_PROT_CTRL_CDTL_MASK)
#define USDHC_PROT_CTRL_CDSS_MASK (0x80U)
#define USDHC_PROT_CTRL_CDSS_SHIFT (7U)
/*! CDSS - Card detect signal selection
* 0b1..Card detection test level is selected (for test purpose).
* 0b0..Card detection level is selected (for normal purpose).
*/
#define USDHC_PROT_CTRL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CDSS_SHIFT)) & USDHC_PROT_CTRL_CDSS_MASK)
#define USDHC_PROT_CTRL_DMASEL_MASK (0x300U)
#define USDHC_PROT_CTRL_DMASEL_SHIFT (8U)
/*! DMASEL - DMA select
* 0b00..No DMA or simple DMA is selected.
* 0b01..ADMA1 is selected.
* 0b10..ADMA2 is selected.
* 0b11..Reserved
*/
#define USDHC_PROT_CTRL_DMASEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_DMASEL_SHIFT)) & USDHC_PROT_CTRL_DMASEL_MASK)
#define USDHC_PROT_CTRL_SABGREQ_MASK (0x10000U)
#define USDHC_PROT_CTRL_SABGREQ_SHIFT (16U)
/*! SABGREQ - Stop at block gap request
* 0b1..Stop
* 0b0..Transfer
*/
#define USDHC_PROT_CTRL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_SABGREQ_SHIFT)) & USDHC_PROT_CTRL_SABGREQ_MASK)
#define USDHC_PROT_CTRL_CREQ_MASK (0x20000U)
#define USDHC_PROT_CTRL_CREQ_SHIFT (17U)
/*! CREQ - Continue request
* 0b1..Restart
* 0b0..No effect
*/
#define USDHC_PROT_CTRL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_CREQ_SHIFT)) & USDHC_PROT_CTRL_CREQ_MASK)
#define USDHC_PROT_CTRL_RWCTL_MASK (0x40000U)
#define USDHC_PROT_CTRL_RWCTL_SHIFT (18U)
/*! RWCTL - Read wait control
* 0b1..Enables read wait control and assert read wait without stopping SD clock at block gap when SABGREQ field is set
* 0b0..Disables read wait control and stop SD clock at block gap when SABGREQ field is set
*/
#define USDHC_PROT_CTRL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RWCTL_SHIFT)) & USDHC_PROT_CTRL_RWCTL_MASK)
#define USDHC_PROT_CTRL_IABG_MASK (0x80000U)
#define USDHC_PROT_CTRL_IABG_SHIFT (19U)
/*! IABG - Interrupt at block gap
* 0b1..Enables interrupt at block gap
* 0b0..Disables interrupt at block gap
*/
#define USDHC_PROT_CTRL_IABG(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_IABG_SHIFT)) & USDHC_PROT_CTRL_IABG_MASK)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK (0x100000U)
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT (20U)
/*! RD_DONE_NO_8CLK - Read performed number 8 clock
*/
#define USDHC_PROT_CTRL_RD_DONE_NO_8CLK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_RD_DONE_NO_8CLK_SHIFT)) & USDHC_PROT_CTRL_RD_DONE_NO_8CLK_MASK)
#define USDHC_PROT_CTRL_WECINT_MASK (0x1000000U)
#define USDHC_PROT_CTRL_WECINT_SHIFT (24U)
/*! WECINT - Wakeup event enable on card interrupt
* 0b1..Enables wakeup event enable on card interrupt
* 0b0..Disables wakeup event enable on card interrupt
*/
#define USDHC_PROT_CTRL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINT_SHIFT)) & USDHC_PROT_CTRL_WECINT_MASK)
#define USDHC_PROT_CTRL_WECINS_MASK (0x2000000U)
#define USDHC_PROT_CTRL_WECINS_SHIFT (25U)
/*! WECINS - Wakeup event enable on SD card insertion
* 0b1..Enable wakeup event enable on SD card insertion
* 0b0..Disable wakeup event enable on SD card insertion
*/
#define USDHC_PROT_CTRL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECINS_SHIFT)) & USDHC_PROT_CTRL_WECINS_MASK)
#define USDHC_PROT_CTRL_WECRM_MASK (0x4000000U)
#define USDHC_PROT_CTRL_WECRM_SHIFT (26U)
/*! WECRM - Wakeup event enable on SD card removal
* 0b1..Enables wakeup event enable on SD card removal
* 0b0..Disables wakeup event enable on SD card removal
*/
#define USDHC_PROT_CTRL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_WECRM_SHIFT)) & USDHC_PROT_CTRL_WECRM_MASK)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK (0x40000000U)
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT (30U)
/*! NON_EXACT_BLK_RD - Non-exact block read
* 0b1..The block read is non-exact block read. Host driver needs to issue abort command to terminate this multi-block read.
* 0b0..The block read is exact block read. Host driver does not need to issue abort command to terminate this multi-block read.
*/
#define USDHC_PROT_CTRL_NON_EXACT_BLK_RD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_PROT_CTRL_NON_EXACT_BLK_RD_SHIFT)) & USDHC_PROT_CTRL_NON_EXACT_BLK_RD_MASK)
/*! @} */
/*! @name SYS_CTRL - System Control */
/*! @{ */
#define USDHC_SYS_CTRL_DVS_MASK (0xF0U)
#define USDHC_SYS_CTRL_DVS_SHIFT (4U)
/*! DVS - Divisor
* 0b0000..Divide-by-1
* 0b0001..Divide-by-2
* 0b1110..Divide-by-15
* 0b1111..Divide-by-16
*/
#define USDHC_SYS_CTRL_DVS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DVS_SHIFT)) & USDHC_SYS_CTRL_DVS_MASK)
#define USDHC_SYS_CTRL_SDCLKFS_MASK (0xFF00U)
#define USDHC_SYS_CTRL_SDCLKFS_SHIFT (8U)
/*! SDCLKFS - SDCLK frequency select
*/
#define USDHC_SYS_CTRL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_SDCLKFS_SHIFT)) & USDHC_SYS_CTRL_SDCLKFS_MASK)
#define USDHC_SYS_CTRL_DTOCV_MASK (0xF0000U)
#define USDHC_SYS_CTRL_DTOCV_SHIFT (16U)
/*! DTOCV - Data timeout counter value
* 0b1111..SDCLK x 2 29
* 0b1110..SDCLK x 2 28
* 0b1101..SDCLK x 2 27
* 0b1100..SDCLK x 2 26
* 0b1011..SDCLK x 2 25
* 0b1010..SDCLK x 2 24
* 0b1001..SDCLK x 2 23
* 0b1000..SDCLK x 2 22
* 0b0111..SDCLK x 2 21
* 0b0110..SDCLK x 2 20
* 0b0101..SDCLK x 2 19
* 0b0100..SDCLK x 2 18
* 0b0011..SDCLK x 2 17
* 0b0010..SDCLK x 2 16
* 0b0001..SDCLK x 2 15
* 0b0000..SDCLK x 2 14
*/
#define USDHC_SYS_CTRL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_DTOCV_SHIFT)) & USDHC_SYS_CTRL_DTOCV_MASK)
#define USDHC_SYS_CTRL_IPP_RST_N_MASK (0x800000U)
#define USDHC_SYS_CTRL_IPP_RST_N_SHIFT (23U)
/*! IPP_RST_N - Hardware reset
*/
#define USDHC_SYS_CTRL_IPP_RST_N(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_IPP_RST_N_SHIFT)) & USDHC_SYS_CTRL_IPP_RST_N_MASK)
#define USDHC_SYS_CTRL_RSTA_MASK (0x1000000U)
#define USDHC_SYS_CTRL_RSTA_SHIFT (24U)
/*! RSTA - Software reset for all
* 0b1..Reset
* 0b0..No reset
*/
#define USDHC_SYS_CTRL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTA_SHIFT)) & USDHC_SYS_CTRL_RSTA_MASK)
#define USDHC_SYS_CTRL_RSTC_MASK (0x2000000U)
#define USDHC_SYS_CTRL_RSTC_SHIFT (25U)
/*! RSTC - Software reset for CMD line
* 0b1..Reset
* 0b0..No reset
*/
#define USDHC_SYS_CTRL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTC_SHIFT)) & USDHC_SYS_CTRL_RSTC_MASK)
#define USDHC_SYS_CTRL_RSTD_MASK (0x4000000U)
#define USDHC_SYS_CTRL_RSTD_SHIFT (26U)
/*! RSTD - Software reset for data line
* 0b1..Reset
* 0b0..No reset
*/
#define USDHC_SYS_CTRL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTD_SHIFT)) & USDHC_SYS_CTRL_RSTD_MASK)
#define USDHC_SYS_CTRL_INITA_MASK (0x8000000U)
#define USDHC_SYS_CTRL_INITA_SHIFT (27U)
/*! INITA - Initialization active
*/
#define USDHC_SYS_CTRL_INITA(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_INITA_SHIFT)) & USDHC_SYS_CTRL_INITA_MASK)
#define USDHC_SYS_CTRL_RSTT_MASK (0x10000000U)
#define USDHC_SYS_CTRL_RSTT_SHIFT (28U)
/*! RSTT - Reset tuning
*/
#define USDHC_SYS_CTRL_RSTT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_SYS_CTRL_RSTT_SHIFT)) & USDHC_SYS_CTRL_RSTT_MASK)
/*! @} */
/*! @name INT_STATUS - Interrupt Status */
/*! @{ */
#define USDHC_INT_STATUS_CC_MASK (0x1U)
#define USDHC_INT_STATUS_CC_SHIFT (0U)
/*! CC - Command complete
* 0b1..Command complete
* 0b0..Command not complete
*/
#define USDHC_INT_STATUS_CC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CC_SHIFT)) & USDHC_INT_STATUS_CC_MASK)
#define USDHC_INT_STATUS_TC_MASK (0x2U)
#define USDHC_INT_STATUS_TC_SHIFT (1U)
/*! TC - Transfer complete
* 0b1..Transfer complete
* 0b0..Transfer does not complete
*/
#define USDHC_INT_STATUS_TC(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TC_SHIFT)) & USDHC_INT_STATUS_TC_MASK)
#define USDHC_INT_STATUS_BGE_MASK (0x4U)
#define USDHC_INT_STATUS_BGE_SHIFT (2U)
/*! BGE - Block gap event
* 0b1..Transaction stopped at block gap
* 0b0..No block gap event
*/
#define USDHC_INT_STATUS_BGE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BGE_SHIFT)) & USDHC_INT_STATUS_BGE_MASK)
#define USDHC_INT_STATUS_DINT_MASK (0x8U)
#define USDHC_INT_STATUS_DINT_SHIFT (3U)
/*! DINT - DMA interrupt
* 0b1..DMA interrupt is generated.
* 0b0..No DMA interrupt
*/
#define USDHC_INT_STATUS_DINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DINT_SHIFT)) & USDHC_INT_STATUS_DINT_MASK)
#define USDHC_INT_STATUS_BWR_MASK (0x10U)
#define USDHC_INT_STATUS_BWR_SHIFT (4U)
/*! BWR - Buffer write ready
* 0b1..Ready to write buffer
* 0b0..Not ready to write buffer
*/
#define USDHC_INT_STATUS_BWR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BWR_SHIFT)) & USDHC_INT_STATUS_BWR_MASK)
#define USDHC_INT_STATUS_BRR_MASK (0x20U)
#define USDHC_INT_STATUS_BRR_SHIFT (5U)
/*! BRR - Buffer read ready
* 0b1..Ready to read buffer
* 0b0..Not ready to read buffer
*/
#define USDHC_INT_STATUS_BRR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_BRR_SHIFT)) & USDHC_INT_STATUS_BRR_MASK)
#define USDHC_INT_STATUS_CINS_MASK (0x40U)
#define USDHC_INT_STATUS_CINS_SHIFT (6U)
/*! CINS - Card insertion
* 0b1..Card inserted
* 0b0..Card state unstable or removed
*/
#define USDHC_INT_STATUS_CINS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINS_SHIFT)) & USDHC_INT_STATUS_CINS_MASK)
#define USDHC_INT_STATUS_CRM_MASK (0x80U)
#define USDHC_INT_STATUS_CRM_SHIFT (7U)
/*! CRM - Card removal
* 0b1..Card removed
* 0b0..Card state unstable or inserted
*/
#define USDHC_INT_STATUS_CRM(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CRM_SHIFT)) & USDHC_INT_STATUS_CRM_MASK)
#define USDHC_INT_STATUS_CINT_MASK (0x100U)
#define USDHC_INT_STATUS_CINT_SHIFT (8U)
/*! CINT - Card interrupt
* 0b1..Generate card interrupt
* 0b0..No card interrupt
*/
#define USDHC_INT_STATUS_CINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CINT_SHIFT)) & USDHC_INT_STATUS_CINT_MASK)
#define USDHC_INT_STATUS_RTE_MASK (0x1000U)
#define USDHC_INT_STATUS_RTE_SHIFT (12U)
/*! RTE - Re-tuning event: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
* 0b1..Re-tuning should be performed.
* 0b0..Re-tuning is not required.
*/
#define USDHC_INT_STATUS_RTE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_RTE_SHIFT)) & USDHC_INT_STATUS_RTE_MASK)
#define USDHC_INT_STATUS_TP_MASK (0x4000U)
#define USDHC_INT_STATUS_TP_SHIFT (14U)
/*! TP - Tuning pass:(only for SD3.0 SDR104 mode and EMMC HS200 mode)
*/
#define USDHC_INT_STATUS_TP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TP_SHIFT)) & USDHC_INT_STATUS_TP_MASK)
#define USDHC_INT_STATUS_CTOE_MASK (0x10000U)
#define USDHC_INT_STATUS_CTOE_SHIFT (16U)
/*! CTOE - Command timeout error
* 0b1..Time out
* 0b0..No error
*/
#define USDHC_INT_STATUS_CTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CTOE_SHIFT)) & USDHC_INT_STATUS_CTOE_MASK)
#define USDHC_INT_STATUS_CCE_MASK (0x20000U)
#define USDHC_INT_STATUS_CCE_SHIFT (17U)
/*! CCE - Command CRC error
* 0b1..CRC error generated
* 0b0..No error
*/
#define USDHC_INT_STATUS_CCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CCE_SHIFT)) & USDHC_INT_STATUS_CCE_MASK)
#define USDHC_INT_STATUS_CEBE_MASK (0x40000U)
#define USDHC_INT_STATUS_CEBE_SHIFT (18U)
/*! CEBE - Command end bit error
* 0b1..End bit error generated
* 0b0..No error
*/
#define USDHC_INT_STATUS_CEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CEBE_SHIFT)) & USDHC_INT_STATUS_CEBE_MASK)
#define USDHC_INT_STATUS_CIE_MASK (0x80000U)
#define USDHC_INT_STATUS_CIE_SHIFT (19U)
/*! CIE - Command index error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_INT_STATUS_CIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_CIE_SHIFT)) & USDHC_INT_STATUS_CIE_MASK)
#define USDHC_INT_STATUS_DTOE_MASK (0x100000U)
#define USDHC_INT_STATUS_DTOE_SHIFT (20U)
/*! DTOE - Data timeout error
* 0b1..Time out
* 0b0..No error
*/
#define USDHC_INT_STATUS_DTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DTOE_SHIFT)) & USDHC_INT_STATUS_DTOE_MASK)
#define USDHC_INT_STATUS_DCE_MASK (0x200000U)
#define USDHC_INT_STATUS_DCE_SHIFT (21U)
/*! DCE - Data CRC error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_INT_STATUS_DCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DCE_SHIFT)) & USDHC_INT_STATUS_DCE_MASK)
#define USDHC_INT_STATUS_DEBE_MASK (0x400000U)
#define USDHC_INT_STATUS_DEBE_SHIFT (22U)
/*! DEBE - Data end bit error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_INT_STATUS_DEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DEBE_SHIFT)) & USDHC_INT_STATUS_DEBE_MASK)
#define USDHC_INT_STATUS_AC12E_MASK (0x1000000U)
#define USDHC_INT_STATUS_AC12E_SHIFT (24U)
/*! AC12E - Auto CMD12 error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_INT_STATUS_AC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_AC12E_SHIFT)) & USDHC_INT_STATUS_AC12E_MASK)
#define USDHC_INT_STATUS_TNE_MASK (0x4000000U)
#define USDHC_INT_STATUS_TNE_SHIFT (26U)
/*! TNE - Tuning error: (only for SD3.0 SDR104 mode and EMMC HS200 mode)
*/
#define USDHC_INT_STATUS_TNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_TNE_SHIFT)) & USDHC_INT_STATUS_TNE_MASK)
#define USDHC_INT_STATUS_DMAE_MASK (0x10000000U)
#define USDHC_INT_STATUS_DMAE_SHIFT (28U)
/*! DMAE - DMA error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_INT_STATUS_DMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_DMAE_SHIFT)) & USDHC_INT_STATUS_DMAE_MASK)
/*! @} */
/*! @name INT_STATUS_EN - Interrupt Status Enable */
/*! @{ */
#define USDHC_INT_STATUS_EN_CCSEN_MASK (0x1U)
#define USDHC_INT_STATUS_EN_CCSEN_SHIFT (0U)
/*! CCSEN - Command complete status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCSEN_SHIFT)) & USDHC_INT_STATUS_EN_CCSEN_MASK)
#define USDHC_INT_STATUS_EN_TCSEN_MASK (0x2U)
#define USDHC_INT_STATUS_EN_TCSEN_SHIFT (1U)
/*! TCSEN - Transfer complete status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TCSEN_SHIFT)) & USDHC_INT_STATUS_EN_TCSEN_MASK)
#define USDHC_INT_STATUS_EN_BGESEN_MASK (0x4U)
#define USDHC_INT_STATUS_EN_BGESEN_SHIFT (2U)
/*! BGESEN - Block gap event status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BGESEN_SHIFT)) & USDHC_INT_STATUS_EN_BGESEN_MASK)
#define USDHC_INT_STATUS_EN_DINTSEN_MASK (0x8U)
#define USDHC_INT_STATUS_EN_DINTSEN_SHIFT (3U)
/*! DINTSEN - DMA interrupt status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_DINTSEN_MASK)
#define USDHC_INT_STATUS_EN_BWRSEN_MASK (0x10U)
#define USDHC_INT_STATUS_EN_BWRSEN_SHIFT (4U)
/*! BWRSEN - Buffer write ready status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BWRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BWRSEN_MASK)
#define USDHC_INT_STATUS_EN_BRRSEN_MASK (0x20U)
#define USDHC_INT_STATUS_EN_BRRSEN_SHIFT (5U)
/*! BRRSEN - Buffer read ready status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_BRRSEN_SHIFT)) & USDHC_INT_STATUS_EN_BRRSEN_MASK)
#define USDHC_INT_STATUS_EN_CINSSEN_MASK (0x40U)
#define USDHC_INT_STATUS_EN_CINSSEN_SHIFT (6U)
/*! CINSSEN - Card insertion status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CINSSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINSSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINSSEN_MASK)
#define USDHC_INT_STATUS_EN_CRMSEN_MASK (0x80U)
#define USDHC_INT_STATUS_EN_CRMSEN_SHIFT (7U)
/*! CRMSEN - Card removal status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CRMSEN_SHIFT)) & USDHC_INT_STATUS_EN_CRMSEN_MASK)
#define USDHC_INT_STATUS_EN_CINTSEN_MASK (0x100U)
#define USDHC_INT_STATUS_EN_CINTSEN_SHIFT (8U)
/*! CINTSEN - Card interrupt status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CINTSEN_SHIFT)) & USDHC_INT_STATUS_EN_CINTSEN_MASK)
#define USDHC_INT_STATUS_EN_RTESEN_MASK (0x1000U)
#define USDHC_INT_STATUS_EN_RTESEN_SHIFT (12U)
/*! RTESEN - Re-tuning event status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_RTESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_RTESEN_SHIFT)) & USDHC_INT_STATUS_EN_RTESEN_MASK)
#define USDHC_INT_STATUS_EN_TPSEN_MASK (0x4000U)
#define USDHC_INT_STATUS_EN_TPSEN_SHIFT (14U)
/*! TPSEN - Tuning pass status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_TPSEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TPSEN_SHIFT)) & USDHC_INT_STATUS_EN_TPSEN_MASK)
#define USDHC_INT_STATUS_EN_CTOESEN_MASK (0x10000U)
#define USDHC_INT_STATUS_EN_CTOESEN_SHIFT (16U)
/*! CTOESEN - Command timeout error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_CTOESEN_MASK)
#define USDHC_INT_STATUS_EN_CCESEN_MASK (0x20000U)
#define USDHC_INT_STATUS_EN_CCESEN_SHIFT (17U)
/*! CCESEN - Command CRC error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CCESEN_SHIFT)) & USDHC_INT_STATUS_EN_CCESEN_MASK)
#define USDHC_INT_STATUS_EN_CEBESEN_MASK (0x40000U)
#define USDHC_INT_STATUS_EN_CEBESEN_SHIFT (18U)
/*! CEBESEN - Command end bit error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_CEBESEN_MASK)
#define USDHC_INT_STATUS_EN_CIESEN_MASK (0x80000U)
#define USDHC_INT_STATUS_EN_CIESEN_SHIFT (19U)
/*! CIESEN - Command index error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_CIESEN_SHIFT)) & USDHC_INT_STATUS_EN_CIESEN_MASK)
#define USDHC_INT_STATUS_EN_DTOESEN_MASK (0x100000U)
#define USDHC_INT_STATUS_EN_DTOESEN_SHIFT (20U)
/*! DTOESEN - Data timeout error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DTOESEN_SHIFT)) & USDHC_INT_STATUS_EN_DTOESEN_MASK)
#define USDHC_INT_STATUS_EN_DCESEN_MASK (0x200000U)
#define USDHC_INT_STATUS_EN_DCESEN_SHIFT (21U)
/*! DCESEN - Data CRC error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DCESEN_SHIFT)) & USDHC_INT_STATUS_EN_DCESEN_MASK)
#define USDHC_INT_STATUS_EN_DEBESEN_MASK (0x400000U)
#define USDHC_INT_STATUS_EN_DEBESEN_SHIFT (22U)
/*! DEBESEN - Data end bit error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DEBESEN_SHIFT)) & USDHC_INT_STATUS_EN_DEBESEN_MASK)
#define USDHC_INT_STATUS_EN_AC12ESEN_MASK (0x1000000U)
#define USDHC_INT_STATUS_EN_AC12ESEN_SHIFT (24U)
/*! AC12ESEN - Auto CMD12 error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_AC12ESEN_SHIFT)) & USDHC_INT_STATUS_EN_AC12ESEN_MASK)
#define USDHC_INT_STATUS_EN_TNESEN_MASK (0x4000000U)
#define USDHC_INT_STATUS_EN_TNESEN_SHIFT (26U)
/*! TNESEN - Tuning error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_TNESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_TNESEN_SHIFT)) & USDHC_INT_STATUS_EN_TNESEN_MASK)
#define USDHC_INT_STATUS_EN_DMAESEN_MASK (0x10000000U)
#define USDHC_INT_STATUS_EN_DMAESEN_SHIFT (28U)
/*! DMAESEN - DMA error status enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_STATUS_EN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_STATUS_EN_DMAESEN_SHIFT)) & USDHC_INT_STATUS_EN_DMAESEN_MASK)
/*! @} */
/*! @name INT_SIGNAL_EN - Interrupt Signal Enable */
/*! @{ */
#define USDHC_INT_SIGNAL_EN_CCIEN_MASK (0x1U)
#define USDHC_INT_SIGNAL_EN_CCIEN_SHIFT (0U)
/*! CCIEN - Command complete interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TCIEN_MASK (0x2U)
#define USDHC_INT_SIGNAL_EN_TCIEN_SHIFT (1U)
/*! TCIEN - Transfer complete interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TCIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TCIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BGEIEN_MASK (0x4U)
#define USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT (2U)
/*! BGEIEN - Block gap event interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BGEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BGEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DINTIEN_MASK (0x8U)
#define USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT (3U)
/*! DINTIEN - DMA interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DINTIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BWRIEN_MASK (0x10U)
#define USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT (4U)
/*! BWRIEN - Buffer write ready interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BWRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BWRIEN_MASK)
#define USDHC_INT_SIGNAL_EN_BRRIEN_MASK (0x20U)
#define USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT (5U)
/*! BRRIEN - Buffer read ready interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_BRRIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_BRRIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CINSIEN_MASK (0x40U)
#define USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT (6U)
/*! CINSIEN - Card insertion interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINSIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINSIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CRMIEN_MASK (0x80U)
#define USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT (7U)
/*! CRMIEN - Card removal interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CRMIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CRMIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CINTIEN_MASK (0x100U)
#define USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT (8U)
/*! CINTIEN - Card interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CINTIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CINTIEN_MASK)
#define USDHC_INT_SIGNAL_EN_RTEIEN_MASK (0x1000U)
#define USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT (12U)
/*! RTEIEN - Re-tuning event interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_RTEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_RTEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_RTEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TPIEN_MASK (0x4000U)
#define USDHC_INT_SIGNAL_EN_TPIEN_SHIFT (14U)
/*! TPIEN - Tuning Pass interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_TPIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TPIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TPIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_MASK (0x10000U)
#define USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT (16U)
/*! CTOEIEN - Command timeout error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CTOEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CCEIEN_MASK (0x20000U)
#define USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT (17U)
/*! CCEIEN - Command CRC error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CCEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_MASK (0x40000U)
#define USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT (18U)
/*! CEBEIEN - Command end bit error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CEBEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_CIEIEN_MASK (0x80000U)
#define USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT (19U)
/*! CIEIEN - Command index error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_CIEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_CIEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_MASK (0x100000U)
#define USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT (20U)
/*! DTOEIEN - Data timeout error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DTOEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DTOEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DCEIEN_MASK (0x200000U)
#define USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT (21U)
/*! DCEIEN - Data CRC error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DCEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DCEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_MASK (0x400000U)
#define USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT (22U)
/*! DEBEIEN - Data end bit error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DEBEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DEBEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_MASK (0x1000000U)
#define USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT (24U)
/*! AC12EIEN - Auto CMD12 error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_AC12EIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_AC12EIEN_MASK)
#define USDHC_INT_SIGNAL_EN_TNEIEN_MASK (0x4000000U)
#define USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT (26U)
/*! TNEIEN - Tuning error interrupt enable
* 0b1..Enabled
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_TNEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_TNEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_TNEIEN_MASK)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_MASK (0x10000000U)
#define USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT (28U)
/*! DMAEIEN - DMA error interrupt enable
* 0b1..Enable
* 0b0..Masked
*/
#define USDHC_INT_SIGNAL_EN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_INT_SIGNAL_EN_DMAEIEN_SHIFT)) & USDHC_INT_SIGNAL_EN_DMAEIEN_MASK)
/*! @} */
/*! @name AUTOCMD12_ERR_STATUS - Auto CMD12 Error Status */
/*! @{ */
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK (0x1U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT (0U)
/*! AC12NE - Auto CMD12 not executed
* 0b1..Not executed
* 0b0..Executed
*/
#define USDHC_AUTOCMD12_ERR_STATUS_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12NE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12NE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK (0x2U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT (1U)
/*! AC12TOE - Auto CMD12 / 23 timeout error
* 0b1..Time out
* 0b0..No error
*/
#define USDHC_AUTOCMD12_ERR_STATUS_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12TOE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK (0x4U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT (2U)
/*! AC12EBE - Auto CMD12 / 23 end bit error
* 0b1..End bit error generated
* 0b0..No error
*/
#define USDHC_AUTOCMD12_ERR_STATUS_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12EBE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK (0x8U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT (3U)
/*! AC12CE - Auto CMD12 / 23 CRC error
* 0b1..CRC error met in Auto CMD12/23 response
* 0b0..No CRC error
*/
#define USDHC_AUTOCMD12_ERR_STATUS_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12CE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12CE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK (0x10U)
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT (4U)
/*! AC12IE - Auto CMD12 / 23 index error
* 0b1..Error, the CMD index in response is not CMD12/23
* 0b0..No error
*/
#define USDHC_AUTOCMD12_ERR_STATUS_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_AC12IE_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_AC12IE_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK (0x80U)
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT (7U)
/*! CNIBAC12E - Command not issued by Auto CMD12 error
* 0b1..Not issued
* 0b0..No error
*/
#define USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_CNIBAC12E_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK (0x400000U)
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT (22U)
/*! EXECUTE_TUNING - Execute tuning
* 0b1..Start tuning procedure
* 0b0..Tuning procedure is aborted
*/
#define USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_EXECUTE_TUNING_MASK)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK (0x800000U)
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT (23U)
/*! SMP_CLK_SEL - Sample clock select
* 0b1..Tuned clock is used to sample data
* 0b0..Fixed clock is used to sample data
*/
#define USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_SHIFT)) & USDHC_AUTOCMD12_ERR_STATUS_SMP_CLK_SEL_MASK)
/*! @} */
/*! @name HOST_CTRL_CAP - Host Controller Capabilities */
/*! @{ */
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK (0x1U)
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT (0U)
/*! SDR50_SUPPORT - SDR50 support
*/
#define USDHC_HOST_CTRL_CAP_SDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR50_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK (0x2U)
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT (1U)
/*! SDR104_SUPPORT - SDR104 support
*/
#define USDHC_HOST_CTRL_CAP_SDR104_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_SDR104_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK (0x4U)
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT (2U)
/*! DDR50_SUPPORT - DDR50 support
*/
#define USDHC_HOST_CTRL_CAP_DDR50_SUPPORT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_SHIFT)) & USDHC_HOST_CTRL_CAP_DDR50_SUPPORT_MASK)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK (0x2000U)
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT (13U)
/*! USE_TUNING_SDR50 - Use Tuning for SDR50
* 0b1..SDR50 supports tuning
* 0b0..SDR50 does not support tuning
*/
#define USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_SHIFT)) & USDHC_HOST_CTRL_CAP_USE_TUNING_SDR50_MASK)
#define USDHC_HOST_CTRL_CAP_MBL_MASK (0x70000U)
#define USDHC_HOST_CTRL_CAP_MBL_SHIFT (16U)
/*! MBL - Max block length
* 0b000..512 bytes
* 0b001..1024 bytes
* 0b010..2048 bytes
* 0b011..4096 bytes
*/
#define USDHC_HOST_CTRL_CAP_MBL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_MBL_SHIFT)) & USDHC_HOST_CTRL_CAP_MBL_MASK)
#define USDHC_HOST_CTRL_CAP_ADMAS_MASK (0x100000U)
#define USDHC_HOST_CTRL_CAP_ADMAS_SHIFT (20U)
/*! ADMAS - ADMA support
* 0b1..Advanced DMA supported
* 0b0..Advanced DMA not supported
*/
#define USDHC_HOST_CTRL_CAP_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_ADMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_ADMAS_MASK)
#define USDHC_HOST_CTRL_CAP_HSS_MASK (0x200000U)
#define USDHC_HOST_CTRL_CAP_HSS_SHIFT (21U)
/*! HSS - High speed support
* 0b1..High speed supported
* 0b0..High speed not supported
*/
#define USDHC_HOST_CTRL_CAP_HSS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_HSS_SHIFT)) & USDHC_HOST_CTRL_CAP_HSS_MASK)
#define USDHC_HOST_CTRL_CAP_DMAS_MASK (0x400000U)
#define USDHC_HOST_CTRL_CAP_DMAS_SHIFT (22U)
/*! DMAS - DMA support
* 0b1..DMA supported
* 0b0..DMA not supported
*/
#define USDHC_HOST_CTRL_CAP_DMAS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_DMAS_SHIFT)) & USDHC_HOST_CTRL_CAP_DMAS_MASK)
#define USDHC_HOST_CTRL_CAP_SRS_MASK (0x800000U)
#define USDHC_HOST_CTRL_CAP_SRS_SHIFT (23U)
/*! SRS - Suspend / resume support
* 0b1..Supported
* 0b0..Not supported
*/
#define USDHC_HOST_CTRL_CAP_SRS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_SRS_SHIFT)) & USDHC_HOST_CTRL_CAP_SRS_MASK)
#define USDHC_HOST_CTRL_CAP_VS33_MASK (0x1000000U)
#define USDHC_HOST_CTRL_CAP_VS33_SHIFT (24U)
/*! VS33 - Voltage support 3.3 V
* 0b1..3.3 V supported
* 0b0..3.3 V not supported
*/
#define USDHC_HOST_CTRL_CAP_VS33(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS33_SHIFT)) & USDHC_HOST_CTRL_CAP_VS33_MASK)
#define USDHC_HOST_CTRL_CAP_VS30_MASK (0x2000000U)
#define USDHC_HOST_CTRL_CAP_VS30_SHIFT (25U)
/*! VS30 - Voltage support 3.0 V
* 0b1..3.0 V supported
* 0b0..3.0 V not supported
*/
#define USDHC_HOST_CTRL_CAP_VS30(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS30_SHIFT)) & USDHC_HOST_CTRL_CAP_VS30_MASK)
#define USDHC_HOST_CTRL_CAP_VS18_MASK (0x4000000U)
#define USDHC_HOST_CTRL_CAP_VS18_SHIFT (26U)
/*! VS18 - Voltage support 1.8 V
* 0b1..1.8 V supported
* 0b0..1.8 V not supported
*/
#define USDHC_HOST_CTRL_CAP_VS18(x) (((uint32_t)(((uint32_t)(x)) << USDHC_HOST_CTRL_CAP_VS18_SHIFT)) & USDHC_HOST_CTRL_CAP_VS18_MASK)
/*! @} */
/*! @name WTMK_LVL - Watermark Level */
/*! @{ */
#define USDHC_WTMK_LVL_RD_WML_MASK (0xFFU)
#define USDHC_WTMK_LVL_RD_WML_SHIFT (0U)
/*! RD_WML - Read watermark level
*/
#define USDHC_WTMK_LVL_RD_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_RD_WML_SHIFT)) & USDHC_WTMK_LVL_RD_WML_MASK)
#define USDHC_WTMK_LVL_WR_WML_MASK (0xFF0000U)
#define USDHC_WTMK_LVL_WR_WML_SHIFT (16U)
/*! WR_WML - Write watermark level
*/
#define USDHC_WTMK_LVL_WR_WML(x) (((uint32_t)(((uint32_t)(x)) << USDHC_WTMK_LVL_WR_WML_SHIFT)) & USDHC_WTMK_LVL_WR_WML_MASK)
/*! @} */
/*! @name MIX_CTRL - Mixer Control */
/*! @{ */
#define USDHC_MIX_CTRL_DMAEN_MASK (0x1U)
#define USDHC_MIX_CTRL_DMAEN_SHIFT (0U)
/*! DMAEN - DMA enable
* 0b1..Enable
* 0b0..Disable
*/
#define USDHC_MIX_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DMAEN_SHIFT)) & USDHC_MIX_CTRL_DMAEN_MASK)
#define USDHC_MIX_CTRL_BCEN_MASK (0x2U)
#define USDHC_MIX_CTRL_BCEN_SHIFT (1U)
/*! BCEN - Block count enable
* 0b1..Enable
* 0b0..Disable
*/
#define USDHC_MIX_CTRL_BCEN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_BCEN_SHIFT)) & USDHC_MIX_CTRL_BCEN_MASK)
#define USDHC_MIX_CTRL_AC12EN_MASK (0x4U)
#define USDHC_MIX_CTRL_AC12EN_SHIFT (2U)
/*! AC12EN - Auto CMD12 enable
* 0b1..Enable
* 0b0..Disable
*/
#define USDHC_MIX_CTRL_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC12EN_SHIFT)) & USDHC_MIX_CTRL_AC12EN_MASK)
#define USDHC_MIX_CTRL_DDR_EN_MASK (0x8U)
#define USDHC_MIX_CTRL_DDR_EN_SHIFT (3U)
/*! DDR_EN - Dual data rate mode selection
*/
#define USDHC_MIX_CTRL_DDR_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DDR_EN_SHIFT)) & USDHC_MIX_CTRL_DDR_EN_MASK)
#define USDHC_MIX_CTRL_DTDSEL_MASK (0x10U)
#define USDHC_MIX_CTRL_DTDSEL_SHIFT (4U)
/*! DTDSEL - Data transfer direction select
* 0b1..Read (Card to host)
* 0b0..Write (Host to card)
*/
#define USDHC_MIX_CTRL_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_DTDSEL_SHIFT)) & USDHC_MIX_CTRL_DTDSEL_MASK)
#define USDHC_MIX_CTRL_MSBSEL_MASK (0x20U)
#define USDHC_MIX_CTRL_MSBSEL_SHIFT (5U)
/*! MSBSEL - Multi / Single block select
* 0b1..Multiple blocks
* 0b0..Single block
*/
#define USDHC_MIX_CTRL_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_MSBSEL_SHIFT)) & USDHC_MIX_CTRL_MSBSEL_MASK)
#define USDHC_MIX_CTRL_NIBBLE_POS_MASK (0x40U)
#define USDHC_MIX_CTRL_NIBBLE_POS_SHIFT (6U)
/*! NIBBLE_POS - Nibble position indication
*/
#define USDHC_MIX_CTRL_NIBBLE_POS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_NIBBLE_POS_SHIFT)) & USDHC_MIX_CTRL_NIBBLE_POS_MASK)
#define USDHC_MIX_CTRL_AC23EN_MASK (0x80U)
#define USDHC_MIX_CTRL_AC23EN_SHIFT (7U)
/*! AC23EN - Auto CMD23 enable
*/
#define USDHC_MIX_CTRL_AC23EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AC23EN_SHIFT)) & USDHC_MIX_CTRL_AC23EN_MASK)
#define USDHC_MIX_CTRL_EXE_TUNE_MASK (0x400000U)
#define USDHC_MIX_CTRL_EXE_TUNE_SHIFT (22U)
/*! EXE_TUNE - Execute tuning: (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
* 0b1..Execute tuning
* 0b0..Not tuned or tuning completed
*/
#define USDHC_MIX_CTRL_EXE_TUNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_EXE_TUNE_SHIFT)) & USDHC_MIX_CTRL_EXE_TUNE_MASK)
#define USDHC_MIX_CTRL_SMP_CLK_SEL_MASK (0x800000U)
#define USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT (23U)
/*! SMP_CLK_SEL - Clock selection
* 0b1..Tuned clock is used to sample data / cmd
* 0b0..Fixed clock is used to sample data / cmd
*/
#define USDHC_MIX_CTRL_SMP_CLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_SMP_CLK_SEL_SHIFT)) & USDHC_MIX_CTRL_SMP_CLK_SEL_MASK)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK (0x1000000U)
#define USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT (24U)
/*! AUTO_TUNE_EN - Auto tuning enable (Only used for SD3.0, SDR104 mode and and EMMC HS200 mode)
* 0b1..Enable auto tuning
* 0b0..Disable auto tuning
*/
#define USDHC_MIX_CTRL_AUTO_TUNE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_AUTO_TUNE_EN_SHIFT)) & USDHC_MIX_CTRL_AUTO_TUNE_EN_MASK)
#define USDHC_MIX_CTRL_FBCLK_SEL_MASK (0x2000000U)
#define USDHC_MIX_CTRL_FBCLK_SEL_SHIFT (25U)
/*! FBCLK_SEL - Feedback clock source selection (Only used for SD3.0, SDR104 mode and EMMC HS200 mode)
* 0b1..Feedback clock comes from the ipp_card_clk_out
* 0b0..Feedback clock comes from the loopback CLK
*/
#define USDHC_MIX_CTRL_FBCLK_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_FBCLK_SEL_SHIFT)) & USDHC_MIX_CTRL_FBCLK_SEL_MASK)
#define USDHC_MIX_CTRL_HS400_MODE_MASK (0x4000000U)
#define USDHC_MIX_CTRL_HS400_MODE_SHIFT (26U)
/*! HS400_MODE - Enable HS400 mode
*/
#define USDHC_MIX_CTRL_HS400_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MIX_CTRL_HS400_MODE_SHIFT)) & USDHC_MIX_CTRL_HS400_MODE_MASK)
/*! @} */
/*! @name FORCE_EVENT - Force Event */
/*! @{ */
#define USDHC_FORCE_EVENT_FEVTAC12NE_MASK (0x1U)
#define USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT (0U)
/*! FEVTAC12NE - Force event auto command 12 not executed
*/
#define USDHC_FORCE_EVENT_FEVTAC12NE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12NE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12NE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_MASK (0x2U)
#define USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT (1U)
/*! FEVTAC12TOE - Force event auto command 12 time out error
*/
#define USDHC_FORCE_EVENT_FEVTAC12TOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12TOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12TOE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12CE_MASK (0x4U)
#define USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT (2U)
/*! FEVTAC12CE - Force event auto command 12 CRC error
*/
#define USDHC_FORCE_EVENT_FEVTAC12CE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12CE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12CE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_MASK (0x8U)
#define USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT (3U)
/*! FEVTAC12EBE - Force event Auto Command 12 end bit error
*/
#define USDHC_FORCE_EVENT_FEVTAC12EBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12EBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12EBE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12IE_MASK (0x10U)
#define USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT (4U)
/*! FEVTAC12IE - Force event Auto Command 12 index error
*/
#define USDHC_FORCE_EVENT_FEVTAC12IE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12IE_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12IE_MASK)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK (0x80U)
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT (7U)
/*! FEVTCNIBAC12E - Force event command not executed by Auto Command 12 error
*/
#define USDHC_FORCE_EVENT_FEVTCNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCNIBAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTCNIBAC12E_MASK)
#define USDHC_FORCE_EVENT_FEVTCTOE_MASK (0x10000U)
#define USDHC_FORCE_EVENT_FEVTCTOE_SHIFT (16U)
/*! FEVTCTOE - Force event command time out error
*/
#define USDHC_FORCE_EVENT_FEVTCTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCTOE_MASK)
#define USDHC_FORCE_EVENT_FEVTCCE_MASK (0x20000U)
#define USDHC_FORCE_EVENT_FEVTCCE_SHIFT (17U)
/*! FEVTCCE - Force event command CRC error
*/
#define USDHC_FORCE_EVENT_FEVTCCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCCE_MASK)
#define USDHC_FORCE_EVENT_FEVTCEBE_MASK (0x40000U)
#define USDHC_FORCE_EVENT_FEVTCEBE_SHIFT (18U)
/*! FEVTCEBE - Force event command end bit error
*/
#define USDHC_FORCE_EVENT_FEVTCEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCEBE_MASK)
#define USDHC_FORCE_EVENT_FEVTCIE_MASK (0x80000U)
#define USDHC_FORCE_EVENT_FEVTCIE_SHIFT (19U)
/*! FEVTCIE - Force event command index error
*/
#define USDHC_FORCE_EVENT_FEVTCIE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCIE_SHIFT)) & USDHC_FORCE_EVENT_FEVTCIE_MASK)
#define USDHC_FORCE_EVENT_FEVTDTOE_MASK (0x100000U)
#define USDHC_FORCE_EVENT_FEVTDTOE_SHIFT (20U)
/*! FEVTDTOE - Force event data time out error
*/
#define USDHC_FORCE_EVENT_FEVTDTOE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDTOE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDTOE_MASK)
#define USDHC_FORCE_EVENT_FEVTDCE_MASK (0x200000U)
#define USDHC_FORCE_EVENT_FEVTDCE_SHIFT (21U)
/*! FEVTDCE - Force event data CRC error
*/
#define USDHC_FORCE_EVENT_FEVTDCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDCE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDCE_MASK)
#define USDHC_FORCE_EVENT_FEVTDEBE_MASK (0x400000U)
#define USDHC_FORCE_EVENT_FEVTDEBE_SHIFT (22U)
/*! FEVTDEBE - Force event data end bit error
*/
#define USDHC_FORCE_EVENT_FEVTDEBE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDEBE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDEBE_MASK)
#define USDHC_FORCE_EVENT_FEVTAC12E_MASK (0x1000000U)
#define USDHC_FORCE_EVENT_FEVTAC12E_SHIFT (24U)
/*! FEVTAC12E - Force event Auto Command 12 error
*/
#define USDHC_FORCE_EVENT_FEVTAC12E(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTAC12E_SHIFT)) & USDHC_FORCE_EVENT_FEVTAC12E_MASK)
#define USDHC_FORCE_EVENT_FEVTTNE_MASK (0x4000000U)
#define USDHC_FORCE_EVENT_FEVTTNE_SHIFT (26U)
/*! FEVTTNE - Force tuning error
*/
#define USDHC_FORCE_EVENT_FEVTTNE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTTNE_SHIFT)) & USDHC_FORCE_EVENT_FEVTTNE_MASK)
#define USDHC_FORCE_EVENT_FEVTDMAE_MASK (0x10000000U)
#define USDHC_FORCE_EVENT_FEVTDMAE_SHIFT (28U)
/*! FEVTDMAE - Force event DMA error
*/
#define USDHC_FORCE_EVENT_FEVTDMAE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTDMAE_SHIFT)) & USDHC_FORCE_EVENT_FEVTDMAE_MASK)
#define USDHC_FORCE_EVENT_FEVTCINT_MASK (0x80000000U)
#define USDHC_FORCE_EVENT_FEVTCINT_SHIFT (31U)
/*! FEVTCINT - Force event card interrupt
*/
#define USDHC_FORCE_EVENT_FEVTCINT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_FORCE_EVENT_FEVTCINT_SHIFT)) & USDHC_FORCE_EVENT_FEVTCINT_MASK)
/*! @} */
/*! @name ADMA_ERR_STATUS - ADMA Error Status */
/*! @{ */
#define USDHC_ADMA_ERR_STATUS_ADMAES_MASK (0x3U)
#define USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT (0U)
/*! ADMAES - ADMA error state (when ADMA error is occurred)
*/
#define USDHC_ADMA_ERR_STATUS_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMAES_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMAES_MASK)
#define USDHC_ADMA_ERR_STATUS_ADMALME_MASK (0x4U)
#define USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT (2U)
/*! ADMALME - ADMA length mismatch error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_ADMA_ERR_STATUS_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMALME_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMALME_MASK)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_MASK (0x8U)
#define USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT (3U)
/*! ADMADCE - ADMA descriptor error
* 0b1..Error
* 0b0..No error
*/
#define USDHC_ADMA_ERR_STATUS_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_ERR_STATUS_ADMADCE_SHIFT)) & USDHC_ADMA_ERR_STATUS_ADMADCE_MASK)
/*! @} */
/*! @name ADMA_SYS_ADDR - ADMA System Address */
/*! @{ */
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK (0xFFFFFFFCU)
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT (2U)
/*! ADS_ADDR - ADMA system address
*/
#define USDHC_ADMA_SYS_ADDR_ADS_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_ADMA_SYS_ADDR_ADS_ADDR_SHIFT)) & USDHC_ADMA_SYS_ADDR_ADS_ADDR_MASK)
/*! @} */
/*! @name DLL_CTRL - DLL (Delay Line) Control */
/*! @{ */
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK (0x1U)
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT (0U)
/*! DLL_CTRL_ENABLE - DLL and delay chain
*/
#define USDHC_DLL_CTRL_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_ENABLE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_ENABLE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK (0x2U)
#define USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT (1U)
/*! DLL_CTRL_RESET - DLL reset
*/
#define USDHC_DLL_CTRL_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_RESET_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_RESET_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
/*! DLL_CTRL_SLV_FORCE_UPD - DLL slave delay line
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK (0x78U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT (3U)
/*! DLL_CTRL_SLV_DLY_TARGET0 - DLL slave delay target0
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET0_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
/*! DLL_CTRL_GATE_UPDATE - DLL gate update
*/
#define USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_GATE_UPDATE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
/*! DLL_CTRL_SLV_OVERRIDE - DLL slave override
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
/*! DLL_CTRL_SLV_OVERRIDE_VAL - DLL slave override val
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK (0x70000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT (16U)
/*! DLL_CTRL_SLV_DLY_TARGET1 - DLL slave delay target1
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_DLY_TARGET1_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
/*! DLL_CTRL_SLV_UPDATE_INT - Slave delay line update interval
*/
#define USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
/*! DLL_CTRL_REF_UPDATE_INT - DLL control loop update interval
*/
#define USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_DLL_CTRL_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */
/*! @name DLL_STATUS - DLL Status */
/*! @{ */
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK (0x1U)
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT (0U)
/*! DLL_STS_SLV_LOCK - Slave delay-line lock status
*/
#define USDHC_DLL_STATUS_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_LOCK_MASK)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK (0x2U)
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT (1U)
/*! DLL_STS_REF_LOCK - Reference DLL lock status
*/
#define USDHC_DLL_STATUS_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_LOCK_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_LOCK_MASK)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT (2U)
/*! DLL_STS_SLV_SEL - Slave delay line select status
*/
#define USDHC_DLL_STATUS_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_SLV_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_SLV_SEL_MASK)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK (0xFE00U)
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT (9U)
/*! DLL_STS_REF_SEL - Reference delay line select taps
*/
#define USDHC_DLL_STATUS_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_DLL_STATUS_DLL_STS_REF_SEL_SHIFT)) & USDHC_DLL_STATUS_DLL_STS_REF_SEL_MASK)
/*! @} */
/*! @name CLK_TUNE_CTRL_STATUS - CLK Tuning Control and Status */
/*! @{ */
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK (0xFU)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT (0U)
/*! DLY_CELL_SET_POST - Delay cells on the feedback clock between CLK_OUT and CLK_POST
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_POST_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK (0xF0U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT (4U)
/*! DLY_CELL_SET_OUT - Delay cells on the feedback clock between CLK_PRE and CLK_OUT
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_OUT_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK (0x7F00U)
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT (8U)
/*! DLY_CELL_SET_PRE - delay cells on the feedback clock between the feedback clock and CLK_PRE
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_DLY_CELL_SET_PRE_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK (0x8000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT (15U)
/*! NXT_ERR - NXT error
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_NXT_ERR_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK (0xF0000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT (16U)
/*! TAP_SEL_POST - Delay cells added on the feedback clock between CLK_OUT and CLK_POST
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_POST_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK (0xF00000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT (20U)
/*! TAP_SEL_OUT - Delay cells added on the feedback clock between CLK_PRE and CLK_OUT
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_OUT_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK (0x7F000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT (24U)
/*! TAP_SEL_PRE - TAP_SEL_PRE
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_TAP_SEL_PRE_MASK)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK (0x80000000U)
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT (31U)
/*! PRE_ERR - PRE error
*/
#define USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR(x) (((uint32_t)(((uint32_t)(x)) << USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_SHIFT)) & USDHC_CLK_TUNE_CTRL_STATUS_PRE_ERR_MASK)
/*! @} */
/*! @name STROBE_DLL_CTRL - Strobe DLL control */
/*! @{ */
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK (0x1U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT (0U)
/*! STROBE_DLL_CTRL_ENABLE - Strobe DLL control enable
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_ENABLE_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK (0x2U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT (1U)
/*! STROBE_DLL_CTRL_RESET - Strobe DLL control reset
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_RESET_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK (0x4U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT (2U)
/*! STROBE_DLL_CTRL_SLV_FORCE_UPD - Strobe DLL control slave force updated
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_FORCE_UPD_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK (0x78U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT (3U)
/*! STROBE_DLL_CTRL_SLV_DLY_TARGET - Strobe DLL Control Slave Delay Target
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_DLY_TARGET_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK (0x80U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT (7U)
/*! STROBE_DLL_CTRL_GATE_UPDATE - Strobe DLL control gate update
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_GATE_UPDATE_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK (0x100U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT (8U)
/*! STROBE_DLL_CTRL_SLV_OVERRIDE - Strobe DLL control slave override
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT (9U)
/*! STROBE_DLL_CTRL_SLV_OVERRIDE_VAL - Strobe DLL control slave Override value
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_OVERRIDE_VAL_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK (0xFF00000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT (20U)
/*! STROBE_DLL_CTRL_SLV_UPDATE_INT - Strobe DLL control slave update interval
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_SLV_UPDATE_INT_MASK)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK (0xF0000000U)
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT (28U)
/*! STROBE_DLL_CTRL_REF_UPDATE_INT - Strobe DLL control reference update interval
*/
#define USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_SHIFT)) & USDHC_STROBE_DLL_CTRL_STROBE_DLL_CTRL_REF_UPDATE_INT_MASK)
/*! @} */
/*! @name STROBE_DLL_STATUS - Strobe DLL status */
/*! @{ */
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK (0x1U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT (0U)
/*! STROBE_DLL_STS_SLV_LOCK - Strobe DLL status slave lock
*/
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_LOCK_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK (0x2U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT (1U)
/*! STROBE_DLL_STS_REF_LOCK - Strobe DLL status reference lock
*/
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_LOCK_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK (0x1FCU)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT (2U)
/*! STROBE_DLL_STS_SLV_SEL - Strobe DLL status slave select
*/
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_SLV_SEL_MASK)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK (0xFE00U)
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT (9U)
/*! STROBE_DLL_STS_REF_SEL - Strobe DLL status reference select
*/
#define USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL(x) (((uint32_t)(((uint32_t)(x)) << USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_SHIFT)) & USDHC_STROBE_DLL_STATUS_STROBE_DLL_STS_REF_SEL_MASK)
/*! @} */
/*! @name VEND_SPEC - Vendor Specific Register */
/*! @{ */
#define USDHC_VEND_SPEC_VSELECT_MASK (0x2U)
#define USDHC_VEND_SPEC_VSELECT_SHIFT (1U)
/*! VSELECT - Voltage selection
* 0b1..Change the voltage to low voltage range, around 1.8 V
* 0b0..Change the voltage to high voltage range, around 3.0 V
*/
#define USDHC_VEND_SPEC_VSELECT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_VSELECT_SHIFT)) & USDHC_VEND_SPEC_VSELECT_MASK)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK (0x4U)
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT (2U)
/*! CONFLICT_CHK_EN - Conflict check enable
* 0b0..Conflict check disable
* 0b1..Conflict check enable
*/
#define USDHC_VEND_SPEC_CONFLICT_CHK_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CONFLICT_CHK_EN_SHIFT)) & USDHC_VEND_SPEC_CONFLICT_CHK_EN_MASK)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK (0x8U)
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT (3U)
/*! AC12_WR_CHKBUSY_EN - Check busy enable
* 0b0..Do not check busy after auto CMD12 for write data packet
* 0b1..Check busy after auto CMD12 for write data packet
*/
#define USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_SHIFT)) & USDHC_VEND_SPEC_AC12_WR_CHKBUSY_EN_MASK)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK (0x100U)
#define USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT (8U)
/*! FRC_SDCLK_ON - Force CLK
* 0b0..CLK active or inactive is fully controlled by the hardware.
* 0b1..Force CLK active
*/
#define USDHC_VEND_SPEC_FRC_SDCLK_ON(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_FRC_SDCLK_ON_SHIFT)) & USDHC_VEND_SPEC_FRC_SDCLK_ON_MASK)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_MASK (0x8000U)
#define USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT (15U)
/*! CRC_CHK_DIS - CRC Check Disable
* 0b0..Check CRC16 for every read data packet and check CRC fields for every write data packet
* 0b1..Ignore CRC16 check for every read data packet and ignore CRC fields check for every write data packet
*/
#define USDHC_VEND_SPEC_CRC_CHK_DIS(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CRC_CHK_DIS_SHIFT)) & USDHC_VEND_SPEC_CRC_CHK_DIS_MASK)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_MASK (0x80000000U)
#define USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT (31U)
/*! CMD_BYTE_EN - Byte access
* 0b0..Disable
* 0b1..Enable
*/
#define USDHC_VEND_SPEC_CMD_BYTE_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC_CMD_BYTE_EN_SHIFT)) & USDHC_VEND_SPEC_CMD_BYTE_EN_MASK)
/*! @} */
/*! @name MMC_BOOT - MMC Boot */
/*! @{ */
#define USDHC_MMC_BOOT_DTOCV_ACK_MASK (0xFU)
#define USDHC_MMC_BOOT_DTOCV_ACK_SHIFT (0U)
/*! DTOCV_ACK - Boot ACK time out
* 0b0000..SDCLK x 2^14
* 0b0001..SDCLK x 2^15
* 0b0010..SDCLK x 2^16
* 0b0011..SDCLK x 2^17
* 0b0100..SDCLK x 2^18
* 0b0101..SDCLK x 2^19
* 0b0110..SDCLK x 2^20
* 0b0111..SDCLK x 2^21
* 0b1110..SDCLK x 2^28
* 0b1111..SDCLK x 2^29
*/
#define USDHC_MMC_BOOT_DTOCV_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DTOCV_ACK_SHIFT)) & USDHC_MMC_BOOT_DTOCV_ACK_MASK)
#define USDHC_MMC_BOOT_BOOT_ACK_MASK (0x10U)
#define USDHC_MMC_BOOT_BOOT_ACK_SHIFT (4U)
/*! BOOT_ACK - BOOT ACK
* 0b0..No ack
* 0b1..Ack
*/
#define USDHC_MMC_BOOT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_ACK_SHIFT)) & USDHC_MMC_BOOT_BOOT_ACK_MASK)
#define USDHC_MMC_BOOT_BOOT_MODE_MASK (0x20U)
#define USDHC_MMC_BOOT_BOOT_MODE_SHIFT (5U)
/*! BOOT_MODE - Boot mode
* 0b0..Normal boot
* 0b1..Alternative boot
*/
#define USDHC_MMC_BOOT_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_MODE_SHIFT)) & USDHC_MMC_BOOT_BOOT_MODE_MASK)
#define USDHC_MMC_BOOT_BOOT_EN_MASK (0x40U)
#define USDHC_MMC_BOOT_BOOT_EN_SHIFT (6U)
/*! BOOT_EN - Boot enable
* 0b0..Fast boot disable
* 0b1..Fast boot enable
*/
#define USDHC_MMC_BOOT_BOOT_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_EN_SHIFT)) & USDHC_MMC_BOOT_BOOT_EN_MASK)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_MASK (0x80U)
#define USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT (7U)
/*! AUTO_SABG_EN - Auto stop at block gap
*/
#define USDHC_MMC_BOOT_AUTO_SABG_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_AUTO_SABG_EN_SHIFT)) & USDHC_MMC_BOOT_AUTO_SABG_EN_MASK)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK (0x100U)
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT (8U)
/*! DISABLE_TIME_OUT - Time out
* 0b0..Enable time out
* 0b1..Disable time out
*/
#define USDHC_MMC_BOOT_DISABLE_TIME_OUT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_DISABLE_TIME_OUT_SHIFT)) & USDHC_MMC_BOOT_DISABLE_TIME_OUT_MASK)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK (0xFFFF0000U)
#define USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT (16U)
/*! BOOT_BLK_CNT - Stop At Block Gap value of automatic mode
*/
#define USDHC_MMC_BOOT_BOOT_BLK_CNT(x) (((uint32_t)(((uint32_t)(x)) << USDHC_MMC_BOOT_BOOT_BLK_CNT_SHIFT)) & USDHC_MMC_BOOT_BOOT_BLK_CNT_MASK)
/*! @} */
/*! @name VEND_SPEC2 - Vendor Specific 2 Register */
/*! @{ */
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK (0x8U)
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT (3U)
/*! CARD_INT_D3_TEST - Card interrupt detection test
* 0b0..Check the card interrupt only when DATA3 is high.
* 0b1..Check the card interrupt by ignoring the status of DATA3.
*/
#define USDHC_VEND_SPEC2_CARD_INT_D3_TEST(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_CARD_INT_D3_TEST_SHIFT)) & USDHC_VEND_SPEC2_CARD_INT_D3_TEST_MASK)
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK (0x10U)
#define USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT (4U)
/*! TUNING_8bit_EN - Tuning 8bit enable
*/
#define USDHC_VEND_SPEC2_TUNING_8bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_8bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_8bit_EN_MASK)
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK (0x20U)
#define USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT (5U)
/*! TUNING_1bit_EN - Tuning 1bit enable
*/
#define USDHC_VEND_SPEC2_TUNING_1bit_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_1bit_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_1bit_EN_MASK)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK (0x40U)
#define USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT (6U)
/*! TUNING_CMD_EN - Tuning command enable
* 0b0..Auto tuning circuit does not check the CMD line.
* 0b1..Auto tuning circuit checks the CMD line.
*/
#define USDHC_VEND_SPEC2_TUNING_CMD_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_TUNING_CMD_EN_SHIFT)) & USDHC_VEND_SPEC2_TUNING_CMD_EN_MASK)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK (0x400U)
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT (10U)
/*! HS400_WR_CLK_STOP_EN - HS400 write clock stop enable
*/
#define USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_WR_CLK_STOP_EN_MASK)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK (0x800U)
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT (11U)
/*! HS400_RD_CLK_STOP_EN - HS400 read clock stop enable
*/
#define USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_SHIFT)) & USDHC_VEND_SPEC2_HS400_RD_CLK_STOP_EN_MASK)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK (0x1000U)
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT (12U)
/*! ACMD23_ARGU2_EN - Argument2 register enable for ACMD23
* 0b1..Argument2 register enable for ACMD23 sharing with SDMA system address register. Default is enabled.
* 0b0..Disable
*/
#define USDHC_VEND_SPEC2_ACMD23_ARGU2_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_SHIFT)) & USDHC_VEND_SPEC2_ACMD23_ARGU2_EN_MASK)
/*! @} */
/*! @name TUNING_CTRL - Tuning Control */
/*! @{ */
#define USDHC_TUNING_CTRL_TUNING_START_TAP_MASK (0x7FU)
#define USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT (0U)
/*! TUNING_START_TAP - Tuning start
*/
#define USDHC_TUNING_CTRL_TUNING_START_TAP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_START_TAP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_START_TAP_MASK)
#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK (0x80U)
#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT (7U)
/*! DIS_CMD_CHK_FOR_STD_TUNING - Disable command check for standard tuning
*/
#define USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_SHIFT)) & USDHC_TUNING_CTRL_DIS_CMD_CHK_FOR_STD_TUNING_MASK)
#define USDHC_TUNING_CTRL_TUNING_COUNTER_MASK (0xFF00U)
#define USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT (8U)
/*! TUNING_COUNTER - Tuning counter
*/
#define USDHC_TUNING_CTRL_TUNING_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_COUNTER_SHIFT)) & USDHC_TUNING_CTRL_TUNING_COUNTER_MASK)
#define USDHC_TUNING_CTRL_TUNING_STEP_MASK (0x70000U)
#define USDHC_TUNING_CTRL_TUNING_STEP_SHIFT (16U)
/*! TUNING_STEP - TUNING_STEP
*/
#define USDHC_TUNING_CTRL_TUNING_STEP(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_STEP_SHIFT)) & USDHC_TUNING_CTRL_TUNING_STEP_MASK)
#define USDHC_TUNING_CTRL_TUNING_WINDOW_MASK (0x700000U)
#define USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT (20U)
/*! TUNING_WINDOW - Data window
*/
#define USDHC_TUNING_CTRL_TUNING_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_TUNING_WINDOW_SHIFT)) & USDHC_TUNING_CTRL_TUNING_WINDOW_MASK)
#define USDHC_TUNING_CTRL_STD_TUNING_EN_MASK (0x1000000U)
#define USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT (24U)
/*! STD_TUNING_EN - Standard tuning circuit and procedure enable
*/
#define USDHC_TUNING_CTRL_STD_TUNING_EN(x) (((uint32_t)(((uint32_t)(x)) << USDHC_TUNING_CTRL_STD_TUNING_EN_SHIFT)) & USDHC_TUNING_CTRL_STD_TUNING_EN_MASK)
/*! @} */
/*!
* @}
*/ /* end of group USDHC_Register_Masks */
/* USDHC - Peripheral instance base addresses */
/** Peripheral USDHC1 base address */
#define USDHC1_BASE (0x40418000u)
/** Peripheral USDHC1 base pointer */
#define USDHC1 ((USDHC_Type *)USDHC1_BASE)
/** Peripheral USDHC2 base address */
#define USDHC2_BASE (0x4041C000u)
/** Peripheral USDHC2 base pointer */
#define USDHC2 ((USDHC_Type *)USDHC2_BASE)
/** Array initializer of USDHC peripheral base addresses */
#define USDHC_BASE_ADDRS { 0u, USDHC1_BASE, USDHC2_BASE }
/** Array initializer of USDHC peripheral base pointers */
#define USDHC_BASE_PTRS { (USDHC_Type *)0u, USDHC1, USDHC2 }
/** Interrupt vectors for the USDHC peripheral type */
#define USDHC_IRQS { NotAvail_IRQn, USDHC1_IRQn, USDHC2_IRQn }
/*!
* @}
*/ /* end of group USDHC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VIDEO_MUX Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VIDEO_MUX_Peripheral_Access_Layer VIDEO_MUX Peripheral Access Layer
* @{
*/
/** VIDEO_MUX - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0 */
__IO uint32_t RW; /**< Video mux Control Register, offset: 0x0 */
__IO uint32_t SET; /**< Video mux Control Register, offset: 0x4 */
__IO uint32_t CLR; /**< Video mux Control Register, offset: 0x8 */
__IO uint32_t TOG; /**< Video mux Control Register, offset: 0xC */
} VID_MUX_CTRL;
uint8_t RESERVED_0[16];
struct { /* offset: 0x20 */
__IO uint32_t RW; /**< Pixel Link Master(PLM) Control Register, offset: 0x20 */
__IO uint32_t SET; /**< Pixel Link Master(PLM) Control Register, offset: 0x24 */
__IO uint32_t CLR; /**< Pixel Link Master(PLM) Control Register, offset: 0x28 */
__IO uint32_t TOG; /**< Pixel Link Master(PLM) Control Register, offset: 0x2C */
} PLM_CTRL;
struct { /* offset: 0x30 */
__IO uint32_t RW; /**< YUV420 Control Register, offset: 0x30 */
__IO uint32_t SET; /**< YUV420 Control Register, offset: 0x34 */
__IO uint32_t CLR; /**< YUV420 Control Register, offset: 0x38 */
__IO uint32_t TOG; /**< YUV420 Control Register, offset: 0x3C */
} YUV420_CTRL;
uint8_t RESERVED_1[16];
struct { /* offset: 0x50 */
__IO uint32_t RW; /**< Data Disable Register, offset: 0x50 */
__IO uint32_t SET; /**< Data Disable Register, offset: 0x54 */
__IO uint32_t CLR; /**< Data Disable Register, offset: 0x58 */
__IO uint32_t TOG; /**< Data Disable Register, offset: 0x5C */
} CFG_DT_DISABLE;
uint8_t RESERVED_2[16];
struct { /* offset: 0x70 */
__IO uint32_t RW; /**< MIPI DSI Control Register, offset: 0x70 */
__IO uint32_t SET; /**< MIPI DSI Control Register, offset: 0x74 */
__IO uint32_t CLR; /**< MIPI DSI Control Register, offset: 0x78 */
__IO uint32_t TOG; /**< MIPI DSI Control Register, offset: 0x7C */
} MIPI_DSI_CTRL;
} VIDEO_MUX_Type;
/* ----------------------------------------------------------------------------
-- VIDEO_MUX Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VIDEO_MUX_Register_Masks VIDEO_MUX Register Masks
* @{
*/
/*! @name VID_MUX_CTRL - Video mux Control Register */
/*! @{ */
#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK (0x1U)
#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT (0U)
/*! CSI_SEL - CSI sensor data input mux selector
* 0b0..CSI sensor data is from Parallel CSI
* 0b1..CSI sensor data is from MIPI CSI
*/
#define VIDEO_MUX_VID_MUX_CTRL_CSI_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_CSI_SEL_MASK)
#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK (0x2U)
#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT (1U)
/*! LCDIF2_SEL - LCDIF2 sensor data input mux selector
* 0b0..LCDIFv2 sensor data is from Parallel CSI
* 0b1..LCDIFv2 sensor data is from MIPI CSI
*/
#define VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_LCDIF2_SEL_MASK)
#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK (0x4U)
#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT (2U)
/*! MIPI_DSI_SEL - MIPI DSI video data input mux selector
* 0b0..MIPI DSI video data is from eLCDIF
* 0b1..MIPI DSI video data is from LCDIFv2
*/
#define VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_MIPI_DSI_SEL_MASK)
#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK (0x8U)
#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT (3U)
/*! PARA_LCD_SEL - Parallel LCDIF video data input mux selector
* 0b0..Parallel LCDIF video data is from eLCDIF
* 0b1..Parallel LCDIF video data is from LCDIFv2
*/
#define VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_SHIFT)) & VIDEO_MUX_VID_MUX_CTRL_PARA_LCD_SEL_MASK)
/*! @} */
/*! @name PLM_CTRL - Pixel Link Master(PLM) Control Register */
/*! @{ */
#define VIDEO_MUX_PLM_CTRL_ENABLE_MASK (0x1U)
#define VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT (0U)
/*! ENABLE - Enable the output of HYSNC and VSYNC
* 0b0..No active HSYNC and VSYNC output
* 0b1..Active HSYNC and VSYNC output
*/
#define VIDEO_MUX_PLM_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_ENABLE_SHIFT)) & VIDEO_MUX_PLM_CTRL_ENABLE_MASK)
#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK (0x2U)
#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT (1U)
/*! VSYNC_OVERRIDE - VSYNC override
* 0b1..VSYNC is asserted
* 0b0..VSYNC is not asserted
*/
#define VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VSYNC_OVERRIDE_MASK)
#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK (0x4U)
#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT (2U)
/*! HSYNC_OVERRIDE - HSYNC override
* 0b1..HSYNC is asserted
* 0b0..HSYNC is not asserted
*/
#define VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_HSYNC_OVERRIDE_MASK)
#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK (0x8U)
#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT (3U)
/*! VALID_OVERRIDE - Valid override
* 0b0..HSYNC and VSYNC is asserted
* 0b1..HSYNC and VSYNC is not asserted
*/
#define VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_SHIFT)) & VIDEO_MUX_PLM_CTRL_VALID_OVERRIDE_MASK)
#define VIDEO_MUX_PLM_CTRL_POLARITY_MASK (0x10U)
#define VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT (4U)
/*! POLARITY - Polarity of HYSNC/VSYNC
* 0b0..Keep the current polarity of HSYNC and VSYNC
* 0b1..Invert the polarity of HSYNC and VSYNC
*/
#define VIDEO_MUX_PLM_CTRL_POLARITY(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_PLM_CTRL_POLARITY_SHIFT)) & VIDEO_MUX_PLM_CTRL_POLARITY_MASK)
/*! @} */
/*! @name YUV420_CTRL - YUV420 Control Register */
/*! @{ */
#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK (0x1U)
#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT (0U)
/*! FST_LN_DATA_TYPE - Data type of First Line
* 0b0..Odd (default)
* 0b1..Even
*/
#define VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_SHIFT)) & VIDEO_MUX_YUV420_CTRL_FST_LN_DATA_TYPE_MASK)
/*! @} */
/*! @name CFG_DT_DISABLE - Data Disable Register */
/*! @{ */
#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK (0xFFFFFFU)
#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT (0U)
/*! CFG_DT_DISABLE - Data Type Disable
*/
#define VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_SHIFT)) & VIDEO_MUX_CFG_DT_DISABLE_CFG_DT_DISABLE_MASK)
/*! @} */
/*! @name MIPI_DSI_CTRL - MIPI DSI Control Register */
/*! @{ */
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK (0x1U)
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT (0U)
/*! DPI_SD - Shut Down - Control to shutdown display (type 4 only)
* 0b0..No effect
* 0b1..Send shutdown command
*/
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_SD_MASK)
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK (0x2U)
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT (1U)
/*! DPI_CM - Color Mode control
* 0b0..Normal Mode
* 0b1..Low-color mode
*/
#define VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_SHIFT)) & VIDEO_MUX_MIPI_DSI_CTRL_DPI_CM_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VIDEO_MUX_Register_Masks */
/* VIDEO_MUX - Peripheral instance base addresses */
/** Peripheral VIDEO_MUX base address */
#define VIDEO_MUX_BASE (0x40818000u)
/** Peripheral VIDEO_MUX base pointer */
#define VIDEO_MUX ((VIDEO_MUX_Type *)VIDEO_MUX_BASE)
/** Array initializer of VIDEO_MUX peripheral base addresses */
#define VIDEO_MUX_BASE_ADDRS { VIDEO_MUX_BASE }
/** Array initializer of VIDEO_MUX peripheral base pointers */
#define VIDEO_MUX_BASE_PTRS { VIDEO_MUX }
/*!
* @}
*/ /* end of group VIDEO_MUX_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VIDEO_PLL Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VIDEO_PLL_Peripheral_Access_Layer VIDEO_PLL Peripheral Access Layer
* @{
*/
/** VIDEO_PLL - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0 */
__IO uint32_t RW; /**< Fractional PLL Control Register, offset: 0x0 */
__IO uint32_t SET; /**< Fractional PLL Control Register, offset: 0x4 */
__IO uint32_t CLR; /**< Fractional PLL Control Register, offset: 0x8 */
__IO uint32_t TOG; /**< Fractional PLL Control Register, offset: 0xC */
} CTRL0;
struct { /* offset: 0x10 */
__IO uint32_t RW; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x10 */
__IO uint32_t SET; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x14 */
__IO uint32_t CLR; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x18 */
__IO uint32_t TOG; /**< Fractional PLL Spread Spectrum Control Register, offset: 0x1C */
} SPREAD_SPECTRUM;
struct { /* offset: 0x20 */
__IO uint32_t RW; /**< Fractional PLL Numerator Control Register, offset: 0x20 */
__IO uint32_t SET; /**< Fractional PLL Numerator Control Register, offset: 0x24 */
__IO uint32_t CLR; /**< Fractional PLL Numerator Control Register, offset: 0x28 */
__IO uint32_t TOG; /**< Fractional PLL Numerator Control Register, offset: 0x2C */
} NUMERATOR;
struct { /* offset: 0x30 */
__IO uint32_t RW; /**< Fractional PLL Denominator Control Register, offset: 0x30 */
__IO uint32_t SET; /**< Fractional PLL Denominator Control Register, offset: 0x34 */
__IO uint32_t CLR; /**< Fractional PLL Denominator Control Register, offset: 0x38 */
__IO uint32_t TOG; /**< Fractional PLL Denominator Control Register, offset: 0x3C */
} DENOMINATOR;
} VIDEO_PLL_Type;
/* ----------------------------------------------------------------------------
-- VIDEO_PLL Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VIDEO_PLL_Register_Masks VIDEO_PLL Register Masks
* @{
*/
/*! @name CTRL0 - Fractional PLL Control Register */
/*! @{ */
#define VIDEO_PLL_CTRL0_DIV_SELECT_MASK (0x7FU)
#define VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT (0U)
/*! DIV_SELECT - DIV_SELECT
*/
#define VIDEO_PLL_CTRL0_DIV_SELECT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DIV_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_DIV_SELECT_MASK)
#define VIDEO_PLL_CTRL0_ENABLE_ALT_MASK (0x100U)
#define VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT (8U)
/*! ENABLE_ALT - ENABLE_ALT
* 0b0..Disable the alternate clock output
* 0b1..Enable the alternate clock output which is the output of the post_divider, and cannot be bypassed
*/
#define VIDEO_PLL_CTRL0_ENABLE_ALT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_ALT_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_ALT_MASK)
#define VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK (0x2000U)
#define VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT (13U)
/*! HOLD_RING_OFF - PLL Start up initialization
* 0b0..Normal operation
* 0b1..Initialize PLL start up
*/
#define VIDEO_PLL_CTRL0_HOLD_RING_OFF(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_HOLD_RING_OFF_SHIFT)) & VIDEO_PLL_CTRL0_HOLD_RING_OFF_MASK)
#define VIDEO_PLL_CTRL0_POWERUP_MASK (0x4000U)
#define VIDEO_PLL_CTRL0_POWERUP_SHIFT (14U)
/*! POWERUP - POWERUP
* 0b1..Power Up the PLL
* 0b0..Power down the PLL
*/
#define VIDEO_PLL_CTRL0_POWERUP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POWERUP_SHIFT)) & VIDEO_PLL_CTRL0_POWERUP_MASK)
#define VIDEO_PLL_CTRL0_ENABLE_MASK (0x8000U)
#define VIDEO_PLL_CTRL0_ENABLE_SHIFT (15U)
/*! ENABLE - ENABLE
* 0b1..Enable the clock output
* 0b0..Disable the clock output
*/
#define VIDEO_PLL_CTRL0_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_ENABLE_SHIFT)) & VIDEO_PLL_CTRL0_ENABLE_MASK)
#define VIDEO_PLL_CTRL0_BYPASS_MASK (0x10000U)
#define VIDEO_PLL_CTRL0_BYPASS_SHIFT (16U)
/*! BYPASS - BYPASS
* 0b1..Bypass the PLL
* 0b0..No Bypass
*/
#define VIDEO_PLL_CTRL0_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BYPASS_SHIFT)) & VIDEO_PLL_CTRL0_BYPASS_MASK)
#define VIDEO_PLL_CTRL0_DITHER_EN_MASK (0x20000U)
#define VIDEO_PLL_CTRL0_DITHER_EN_SHIFT (17U)
/*! DITHER_EN - DITHER_EN
* 0b0..Disable Dither
* 0b1..Enable Dither
*/
#define VIDEO_PLL_CTRL0_DITHER_EN(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_DITHER_EN_SHIFT)) & VIDEO_PLL_CTRL0_DITHER_EN_MASK)
#define VIDEO_PLL_CTRL0_BIAS_TRIM_MASK (0x380000U)
#define VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT (19U)
/*! BIAS_TRIM - BIAS_TRIM
*/
#define VIDEO_PLL_CTRL0_BIAS_TRIM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_TRIM_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_TRIM_MASK)
#define VIDEO_PLL_CTRL0_PLL_REG_EN_MASK (0x400000U)
#define VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT (22U)
/*! PLL_REG_EN - PLL_REG_EN
*/
#define VIDEO_PLL_CTRL0_PLL_REG_EN(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_PLL_REG_EN_SHIFT)) & VIDEO_PLL_CTRL0_PLL_REG_EN_MASK)
#define VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK (0xE000000U)
#define VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT (25U)
/*! POST_DIV_SEL - Post Divide Select
* 0b000..Divide by 1
* 0b001..Divide by 2
* 0b010..Divide by 4
* 0b011..Divide by 8
* 0b100..Divide by 16
* 0b101..Divide by 32
*/
#define VIDEO_PLL_CTRL0_POST_DIV_SEL(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_POST_DIV_SEL_SHIFT)) & VIDEO_PLL_CTRL0_POST_DIV_SEL_MASK)
#define VIDEO_PLL_CTRL0_BIAS_SELECT_MASK (0x20000000U)
#define VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT (29U)
/*! BIAS_SELECT - BIAS_SELECT
* 0b0..Used in SoCs with a bias current of 10uA
* 0b1..Used in SoCs with a bias current of 2uA
*/
#define VIDEO_PLL_CTRL0_BIAS_SELECT(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_CTRL0_BIAS_SELECT_SHIFT)) & VIDEO_PLL_CTRL0_BIAS_SELECT_MASK)
/*! @} */
/*! @name SPREAD_SPECTRUM - Fractional PLL Spread Spectrum Control Register */
/*! @{ */
#define VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK (0x7FFFU)
#define VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT (0U)
/*! STEP - Step
*/
#define VIDEO_PLL_SPREAD_SPECTRUM_STEP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STEP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STEP_MASK)
#define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK (0x8000U)
#define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT (15U)
/*! ENABLE - Enable
*/
#define VIDEO_PLL_SPREAD_SPECTRUM_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_ENABLE_MASK)
#define VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK (0xFFFF0000U)
#define VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT (16U)
/*! STOP - Stop
*/
#define VIDEO_PLL_SPREAD_SPECTRUM_STOP(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_SPREAD_SPECTRUM_STOP_SHIFT)) & VIDEO_PLL_SPREAD_SPECTRUM_STOP_MASK)
/*! @} */
/*! @name NUMERATOR - Fractional PLL Numerator Control Register */
/*! @{ */
#define VIDEO_PLL_NUMERATOR_NUM_MASK (0x3FFFFFFFU)
#define VIDEO_PLL_NUMERATOR_NUM_SHIFT (0U)
/*! NUM - Numerator
*/
#define VIDEO_PLL_NUMERATOR_NUM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_NUMERATOR_NUM_SHIFT)) & VIDEO_PLL_NUMERATOR_NUM_MASK)
/*! @} */
/*! @name DENOMINATOR - Fractional PLL Denominator Control Register */
/*! @{ */
#define VIDEO_PLL_DENOMINATOR_DENOM_MASK (0x3FFFFFFFU)
#define VIDEO_PLL_DENOMINATOR_DENOM_SHIFT (0U)
/*! DENOM - Denominator
*/
#define VIDEO_PLL_DENOMINATOR_DENOM(x) (((uint32_t)(((uint32_t)(x)) << VIDEO_PLL_DENOMINATOR_DENOM_SHIFT)) & VIDEO_PLL_DENOMINATOR_DENOM_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VIDEO_PLL_Register_Masks */
/* VIDEO_PLL - Peripheral instance base addresses */
/** Peripheral VIDEO_PLL base address */
#define VIDEO_PLL_BASE (0u)
/** Peripheral VIDEO_PLL base pointer */
#define VIDEO_PLL ((VIDEO_PLL_Type *)VIDEO_PLL_BASE)
/** Array initializer of VIDEO_PLL peripheral base addresses */
#define VIDEO_PLL_BASE_ADDRS { VIDEO_PLL_BASE }
/** Array initializer of VIDEO_PLL peripheral base pointers */
#define VIDEO_PLL_BASE_PTRS { VIDEO_PLL }
/*!
* @}
*/ /* end of group VIDEO_PLL_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- VMBANDGAP Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup VMBANDGAP_Peripheral_Access_Layer VMBANDGAP Peripheral Access Layer
* @{
*/
/** VMBANDGAP - Register Layout Typedef */
typedef struct {
struct { /* offset: 0x0 */
__IO uint32_t RW; /**< Analog Control Register CTRL0, offset: 0x0 */
__IO uint32_t SET; /**< Analog Control Register CTRL0, offset: 0x4 */
__IO uint32_t CLR; /**< Analog Control Register CTRL0, offset: 0x8 */
__IO uint32_t TOG; /**< Analog Control Register CTRL0, offset: 0xC */
} CTRL0;
uint8_t RESERVED_0[64];
struct { /* offset: 0x50 */
__I uint32_t RW; /**< Analog Status Register STAT0, offset: 0x50 */
__I uint32_t SET; /**< Analog Status Register STAT0, offset: 0x54 */
__I uint32_t CLR; /**< Analog Status Register STAT0, offset: 0x58 */
__I uint32_t TOG; /**< Analog Status Register STAT0, offset: 0x5C */
} STAT0;
} VMBANDGAP_Type;
/* ----------------------------------------------------------------------------
-- VMBANDGAP Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup VMBANDGAP_Register_Masks VMBANDGAP Register Masks
* @{
*/
/*! @name CTRL0 - Analog Control Register CTRL0 */
/*! @{ */
#define VMBANDGAP_CTRL0_REFTOP_PWD_MASK (0x1U)
#define VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT (0U)
/*! REFTOP_PWD - Master power-down for bandgap module
*/
#define VMBANDGAP_CTRL0_REFTOP_PWD(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWD_MASK)
#define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK (0x2U)
#define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT (1U)
/*! REFTOP_LINREGREF_PWD - Power-down for bandgap voltage-reference buffer
*/
#define VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LINREGREF_PWD_MASK)
#define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK (0x4U)
#define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT (2U)
/*! REFTOP_PWDVBGUP - Power-down VBGUP detector in bandgap
*/
#define VMBANDGAP_CTRL0_REFTOP_PWDVBGUP(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_PWDVBGUP_MASK)
#define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK (0x8U)
#define VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT (3U)
/*! REFTOP_LOWPOWER - Low-power control bit
*/
#define VMBANDGAP_CTRL0_REFTOP_LOWPOWER(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_LOWPOWER_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_LOWPOWER_MASK)
#define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK (0x10U)
#define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT (4U)
/*! REFTOP_SELFBIASOFF - bandgap self-bias control bit
*/
#define VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_SHIFT)) & VMBANDGAP_CTRL0_REFTOP_SELFBIASOFF_MASK)
/*! @} */
/*! @name STAT0 - Analog Status Register STAT0 */
/*! @{ */
#define VMBANDGAP_STAT0_REFTOP_VBGUP_MASK (0x1U)
#define VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT (0U)
/*! REFTOP_VBGUP - Brief description here
*/
#define VMBANDGAP_STAT0_REFTOP_VBGUP(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_REFTOP_VBGUP_SHIFT)) & VMBANDGAP_STAT0_REFTOP_VBGUP_MASK)
#define VMBANDGAP_STAT0_VDD1_PORB_MASK (0x2U)
#define VMBANDGAP_STAT0_VDD1_PORB_SHIFT (1U)
/*! VDD1_PORB - Brief description here
*/
#define VMBANDGAP_STAT0_VDD1_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD1_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD1_PORB_MASK)
#define VMBANDGAP_STAT0_VDD2_PORB_MASK (0x4U)
#define VMBANDGAP_STAT0_VDD2_PORB_SHIFT (2U)
/*! VDD2_PORB - Brief description here
*/
#define VMBANDGAP_STAT0_VDD2_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD2_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD2_PORB_MASK)
#define VMBANDGAP_STAT0_VDD3_PORB_MASK (0x8U)
#define VMBANDGAP_STAT0_VDD3_PORB_SHIFT (3U)
/*! VDD3_PORB - Brief description here
*/
#define VMBANDGAP_STAT0_VDD3_PORB(x) (((uint32_t)(((uint32_t)(x)) << VMBANDGAP_STAT0_VDD3_PORB_SHIFT)) & VMBANDGAP_STAT0_VDD3_PORB_MASK)
/*! @} */
/*!
* @}
*/ /* end of group VMBANDGAP_Register_Masks */
/* VMBANDGAP - Peripheral instance base addresses */
/** Peripheral VMBANDGAP base address */
#define VMBANDGAP_BASE (0u)
/** Peripheral VMBANDGAP base pointer */
#define VMBANDGAP ((VMBANDGAP_Type *)VMBANDGAP_BASE)
/** Array initializer of VMBANDGAP peripheral base addresses */
#define VMBANDGAP_BASE_ADDRS { VMBANDGAP_BASE }
/** Array initializer of VMBANDGAP peripheral base pointers */
#define VMBANDGAP_BASE_PTRS { VMBANDGAP }
/*!
* @}
*/ /* end of group VMBANDGAP_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- WDOG Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
* @{
*/
/** WDOG - Register Layout Typedef */
typedef struct {
__IO uint16_t WCR; /**< Watchdog Control Register, offset: 0x0 */
__IO uint16_t WSR; /**< Watchdog Service Register, offset: 0x2 */
__I uint16_t WRSR; /**< Watchdog Reset Status Register, offset: 0x4 */
__IO uint16_t WICR; /**< Watchdog Interrupt Control Register, offset: 0x6 */
__IO uint16_t WMCR; /**< Watchdog Miscellaneous Control Register, offset: 0x8 */
} WDOG_Type;
/* ----------------------------------------------------------------------------
-- WDOG Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup WDOG_Register_Masks WDOG Register Masks
* @{
*/
/*! @name WCR - Watchdog Control Register */
/*! @{ */
#define WDOG_WCR_WDZST_MASK (0x1U)
#define WDOG_WCR_WDZST_SHIFT (0U)
/*! WDZST - WDZST
* 0b0..Continue timer operation (Default).
* 0b1..Suspend the watchdog timer.
*/
#define WDOG_WCR_WDZST(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDZST_SHIFT)) & WDOG_WCR_WDZST_MASK)
#define WDOG_WCR_WDBG_MASK (0x2U)
#define WDOG_WCR_WDBG_SHIFT (1U)
/*! WDBG - WDBG
* 0b0..Continue WDOG timer operation (Default).
* 0b1..Suspend the watchdog timer.
*/
#define WDOG_WCR_WDBG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDBG_SHIFT)) & WDOG_WCR_WDBG_MASK)
#define WDOG_WCR_WDE_MASK (0x4U)
#define WDOG_WCR_WDE_SHIFT (2U)
/*! WDE - WDE
* 0b0..Disable the Watchdog (Default).
* 0b1..Enable the Watchdog.
*/
#define WDOG_WCR_WDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDE_SHIFT)) & WDOG_WCR_WDE_MASK)
#define WDOG_WCR_WDT_MASK (0x8U)
#define WDOG_WCR_WDT_SHIFT (3U)
/*! WDT - WDT
* 0b0..No effect on WDOG_B (Default).
* 0b1..Assert WDOG_B upon a Watchdog Time-out event.
*/
#define WDOG_WCR_WDT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDT_SHIFT)) & WDOG_WCR_WDT_MASK)
#define WDOG_WCR_SRS_MASK (0x10U)
#define WDOG_WCR_SRS_SHIFT (4U)
/*! SRS - SRS
* 0b0..Assert system reset signal.
* 0b1..No effect on the system (Default).
*/
#define WDOG_WCR_SRS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRS_SHIFT)) & WDOG_WCR_SRS_MASK)
#define WDOG_WCR_WDA_MASK (0x20U)
#define WDOG_WCR_WDA_SHIFT (5U)
/*! WDA - WDA
* 0b0..Assert WDOG_B output.
* 0b1..No effect on system (Default).
*/
#define WDOG_WCR_WDA(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDA_SHIFT)) & WDOG_WCR_WDA_MASK)
#define WDOG_WCR_SRE_MASK (0x40U)
#define WDOG_WCR_SRE_SHIFT (6U)
/*! SRE - Software Reset Extension, an optional way to generate software reset
* 0b0..using original way to generate software reset (default)
* 0b1..using new way to generate software reset.
*/
#define WDOG_WCR_SRE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_SRE_SHIFT)) & WDOG_WCR_SRE_MASK)
#define WDOG_WCR_WDW_MASK (0x80U)
#define WDOG_WCR_WDW_SHIFT (7U)
/*! WDW - WDW
* 0b0..Continue WDOG timer operation (Default).
* 0b1..Suspend WDOG timer operation.
*/
#define WDOG_WCR_WDW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WDW_SHIFT)) & WDOG_WCR_WDW_MASK)
#define WDOG_WCR_WT_MASK (0xFF00U)
#define WDOG_WCR_WT_SHIFT (8U)
/*! WT - WT
* 0b00000000..- 0.5 Seconds (Default).
* 0b00000001..- 1.0 Seconds.
* 0b00000010..- 1.5 Seconds.
* 0b00000011..- 2.0 Seconds.
* 0b11111111..- 128 Seconds.
*/
#define WDOG_WCR_WT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WCR_WT_SHIFT)) & WDOG_WCR_WT_MASK)
/*! @} */
/*! @name WSR - Watchdog Service Register */
/*! @{ */
#define WDOG_WSR_WSR_MASK (0xFFFFU)
#define WDOG_WSR_WSR_SHIFT (0U)
/*! WSR - WSR
* 0b0101010101010101..Write to the Watchdog Service Register (WDOG_WSR).
* 0b1010101010101010..Write to the Watchdog Service Register (WDOG_WSR).
*/
#define WDOG_WSR_WSR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WSR_WSR_SHIFT)) & WDOG_WSR_WSR_MASK)
/*! @} */
/*! @name WRSR - Watchdog Reset Status Register */
/*! @{ */
#define WDOG_WRSR_SFTW_MASK (0x1U)
#define WDOG_WRSR_SFTW_SHIFT (0U)
/*! SFTW - SFTW
* 0b0..Reset is not the result of a software reset.
* 0b1..Reset is the result of a software reset.
*/
#define WDOG_WRSR_SFTW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_SFTW_SHIFT)) & WDOG_WRSR_SFTW_MASK)
#define WDOG_WRSR_TOUT_MASK (0x2U)
#define WDOG_WRSR_TOUT_SHIFT (1U)
/*! TOUT - TOUT
* 0b0..Reset is not the result of a WDOG timeout.
* 0b1..Reset is the result of a WDOG timeout.
*/
#define WDOG_WRSR_TOUT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_TOUT_SHIFT)) & WDOG_WRSR_TOUT_MASK)
#define WDOG_WRSR_POR_MASK (0x10U)
#define WDOG_WRSR_POR_SHIFT (4U)
/*! POR - POR
* 0b0..Reset is not the result of a power on reset.
* 0b1..Reset is the result of a power on reset.
*/
#define WDOG_WRSR_POR(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WRSR_POR_SHIFT)) & WDOG_WRSR_POR_MASK)
/*! @} */
/*! @name WICR - Watchdog Interrupt Control Register */
/*! @{ */
#define WDOG_WICR_WICT_MASK (0xFFU)
#define WDOG_WICR_WICT_SHIFT (0U)
/*! WICT - WICT
* 0b00000000..WICT[7:0] = Time duration between interrupt and time-out is 0 seconds.
* 0b00000001..WICT[7:0] = Time duration between interrupt and time-out is 0.5 seconds.
* 0b00000100..WICT[7:0] = Time duration between interrupt and time-out is 2 seconds (Default).
* 0b11111111..WICT[7:0] = Time duration between interrupt and time-out is 127.5 seconds.
*/
#define WDOG_WICR_WICT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WICT_SHIFT)) & WDOG_WICR_WICT_MASK)
#define WDOG_WICR_WTIS_MASK (0x4000U)
#define WDOG_WICR_WTIS_SHIFT (14U)
/*! WTIS - WTIS
* 0b0..No interrupt has occurred (Default).
* 0b1..Interrupt has occurred
*/
#define WDOG_WICR_WTIS(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WTIS_SHIFT)) & WDOG_WICR_WTIS_MASK)
#define WDOG_WICR_WIE_MASK (0x8000U)
#define WDOG_WICR_WIE_SHIFT (15U)
/*! WIE - WIE
* 0b0..Disable Interrupt (Default).
* 0b1..Enable Interrupt.
*/
#define WDOG_WICR_WIE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WICR_WIE_SHIFT)) & WDOG_WICR_WIE_MASK)
/*! @} */
/*! @name WMCR - Watchdog Miscellaneous Control Register */
/*! @{ */
#define WDOG_WMCR_PDE_MASK (0x1U)
#define WDOG_WMCR_PDE_SHIFT (0U)
/*! PDE - PDE
* 0b0..Power Down Counter of WDOG is disabled.
* 0b1..Power Down Counter of WDOG is enabled (Default).
*/
#define WDOG_WMCR_PDE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WMCR_PDE_SHIFT)) & WDOG_WMCR_PDE_MASK)
/*! @} */
/*!
* @}
*/ /* end of group WDOG_Register_Masks */
/* WDOG - Peripheral instance base addresses */
/** Peripheral WDOG1 base address */
#define WDOG1_BASE (0x40030000u)
/** Peripheral WDOG1 base pointer */
#define WDOG1 ((WDOG_Type *)WDOG1_BASE)
/** Peripheral WDOG2 base address */
#define WDOG2_BASE (0x40034000u)
/** Peripheral WDOG2 base pointer */
#define WDOG2 ((WDOG_Type *)WDOG2_BASE)
/** Array initializer of WDOG peripheral base addresses */
#define WDOG_BASE_ADDRS { 0u, WDOG1_BASE, WDOG2_BASE }
/** Array initializer of WDOG peripheral base pointers */
#define WDOG_BASE_PTRS { (WDOG_Type *)0u, WDOG1, WDOG2 }
/** Interrupt vectors for the WDOG peripheral type */
#define WDOG_IRQS { NotAvail_IRQn, WDOG1_IRQn, WDOG2_IRQn }
/*!
* @}
*/ /* end of group WDOG_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- XBARA Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup XBARA_Peripheral_Access_Layer XBARA Peripheral Access Layer
* @{
*/
/** XBARA - Register Layout Typedef */
typedef struct {
__IO uint16_t SEL0; /**< Crossbar A Select Register 0, offset: 0x0 */
__IO uint16_t SEL1; /**< Crossbar A Select Register 1, offset: 0x2 */
__IO uint16_t SEL2; /**< Crossbar A Select Register 2, offset: 0x4 */
__IO uint16_t SEL3; /**< Crossbar A Select Register 3, offset: 0x6 */
__IO uint16_t SEL4; /**< Crossbar A Select Register 4, offset: 0x8 */
__IO uint16_t SEL5; /**< Crossbar A Select Register 5, offset: 0xA */
__IO uint16_t SEL6; /**< Crossbar A Select Register 6, offset: 0xC */
__IO uint16_t SEL7; /**< Crossbar A Select Register 7, offset: 0xE */
__IO uint16_t SEL8; /**< Crossbar A Select Register 8, offset: 0x10 */
__IO uint16_t SEL9; /**< Crossbar A Select Register 9, offset: 0x12 */
__IO uint16_t SEL10; /**< Crossbar A Select Register 10, offset: 0x14 */
__IO uint16_t SEL11; /**< Crossbar A Select Register 11, offset: 0x16 */
__IO uint16_t SEL12; /**< Crossbar A Select Register 12, offset: 0x18 */
__IO uint16_t SEL13; /**< Crossbar A Select Register 13, offset: 0x1A */
__IO uint16_t SEL14; /**< Crossbar A Select Register 14, offset: 0x1C */
__IO uint16_t SEL15; /**< Crossbar A Select Register 15, offset: 0x1E */
__IO uint16_t SEL16; /**< Crossbar A Select Register 16, offset: 0x20 */
__IO uint16_t SEL17; /**< Crossbar A Select Register 17, offset: 0x22 */
__IO uint16_t SEL18; /**< Crossbar A Select Register 18, offset: 0x24 */
__IO uint16_t SEL19; /**< Crossbar A Select Register 19, offset: 0x26 */
__IO uint16_t SEL20; /**< Crossbar A Select Register 20, offset: 0x28 */
__IO uint16_t SEL21; /**< Crossbar A Select Register 21, offset: 0x2A */
__IO uint16_t SEL22; /**< Crossbar A Select Register 22, offset: 0x2C */
__IO uint16_t SEL23; /**< Crossbar A Select Register 23, offset: 0x2E */
__IO uint16_t SEL24; /**< Crossbar A Select Register 24, offset: 0x30 */
__IO uint16_t SEL25; /**< Crossbar A Select Register 25, offset: 0x32 */
__IO uint16_t SEL26; /**< Crossbar A Select Register 26, offset: 0x34 */
__IO uint16_t SEL27; /**< Crossbar A Select Register 27, offset: 0x36 */
__IO uint16_t SEL28; /**< Crossbar A Select Register 28, offset: 0x38 */
__IO uint16_t SEL29; /**< Crossbar A Select Register 29, offset: 0x3A */
__IO uint16_t SEL30; /**< Crossbar A Select Register 30, offset: 0x3C */
__IO uint16_t SEL31; /**< Crossbar A Select Register 31, offset: 0x3E */
__IO uint16_t SEL32; /**< Crossbar A Select Register 32, offset: 0x40 */
__IO uint16_t SEL33; /**< Crossbar A Select Register 33, offset: 0x42 */
__IO uint16_t SEL34; /**< Crossbar A Select Register 34, offset: 0x44 */
__IO uint16_t SEL35; /**< Crossbar A Select Register 35, offset: 0x46 */
__IO uint16_t SEL36; /**< Crossbar A Select Register 36, offset: 0x48 */
__IO uint16_t SEL37; /**< Crossbar A Select Register 37, offset: 0x4A */
__IO uint16_t SEL38; /**< Crossbar A Select Register 38, offset: 0x4C */
__IO uint16_t SEL39; /**< Crossbar A Select Register 39, offset: 0x4E */
__IO uint16_t SEL40; /**< Crossbar A Select Register 40, offset: 0x50 */
__IO uint16_t SEL41; /**< Crossbar A Select Register 41, offset: 0x52 */
__IO uint16_t SEL42; /**< Crossbar A Select Register 42, offset: 0x54 */
__IO uint16_t SEL43; /**< Crossbar A Select Register 43, offset: 0x56 */
__IO uint16_t SEL44; /**< Crossbar A Select Register 44, offset: 0x58 */
__IO uint16_t SEL45; /**< Crossbar A Select Register 45, offset: 0x5A */
__IO uint16_t SEL46; /**< Crossbar A Select Register 46, offset: 0x5C */
__IO uint16_t SEL47; /**< Crossbar A Select Register 47, offset: 0x5E */
__IO uint16_t SEL48; /**< Crossbar A Select Register 48, offset: 0x60 */
__IO uint16_t SEL49; /**< Crossbar A Select Register 49, offset: 0x62 */
__IO uint16_t SEL50; /**< Crossbar A Select Register 50, offset: 0x64 */
__IO uint16_t SEL51; /**< Crossbar A Select Register 51, offset: 0x66 */
__IO uint16_t SEL52; /**< Crossbar A Select Register 52, offset: 0x68 */
__IO uint16_t SEL53; /**< Crossbar A Select Register 53, offset: 0x6A */
__IO uint16_t SEL54; /**< Crossbar A Select Register 54, offset: 0x6C */
__IO uint16_t SEL55; /**< Crossbar A Select Register 55, offset: 0x6E */
__IO uint16_t SEL56; /**< Crossbar A Select Register 56, offset: 0x70 */
__IO uint16_t SEL57; /**< Crossbar A Select Register 57, offset: 0x72 */
__IO uint16_t SEL58; /**< Crossbar A Select Register 58, offset: 0x74 */
__IO uint16_t SEL59; /**< Crossbar A Select Register 59, offset: 0x76 */
__IO uint16_t SEL60; /**< Crossbar A Select Register 60, offset: 0x78 */
__IO uint16_t SEL61; /**< Crossbar A Select Register 61, offset: 0x7A */
__IO uint16_t SEL62; /**< Crossbar A Select Register 62, offset: 0x7C */
__IO uint16_t SEL63; /**< Crossbar A Select Register 63, offset: 0x7E */
__IO uint16_t SEL64; /**< Crossbar A Select Register 64, offset: 0x80 */
__IO uint16_t SEL65; /**< Crossbar A Select Register 65, offset: 0x82 */
__IO uint16_t SEL66; /**< Crossbar A Select Register 66, offset: 0x84 */
__IO uint16_t SEL67; /**< Crossbar A Select Register 67, offset: 0x86 */
__IO uint16_t SEL68; /**< Crossbar A Select Register 68, offset: 0x88 */
__IO uint16_t SEL69; /**< Crossbar A Select Register 69, offset: 0x8A */
__IO uint16_t SEL70; /**< Crossbar A Select Register 70, offset: 0x8C */
__IO uint16_t SEL71; /**< Crossbar A Select Register 71, offset: 0x8E */
__IO uint16_t SEL72; /**< Crossbar A Select Register 72, offset: 0x90 */
__IO uint16_t SEL73; /**< Crossbar A Select Register 73, offset: 0x92 */
__IO uint16_t SEL74; /**< Crossbar A Select Register 74, offset: 0x94 */
__IO uint16_t SEL75; /**< Crossbar A Select Register 75, offset: 0x96 */
__IO uint16_t SEL76; /**< Crossbar A Select Register 76, offset: 0x98 */
__IO uint16_t SEL77; /**< Crossbar A Select Register 77, offset: 0x9A */
__IO uint16_t SEL78; /**< Crossbar A Select Register 78, offset: 0x9C */
__IO uint16_t SEL79; /**< Crossbar A Select Register 79, offset: 0x9E */
__IO uint16_t SEL80; /**< Crossbar A Select Register 80, offset: 0xA0 */
__IO uint16_t SEL81; /**< Crossbar A Select Register 81, offset: 0xA2 */
__IO uint16_t SEL82; /**< Crossbar A Select Register 82, offset: 0xA4 */
__IO uint16_t SEL83; /**< Crossbar A Select Register 83, offset: 0xA6 */
__IO uint16_t SEL84; /**< Crossbar A Select Register 84, offset: 0xA8 */
__IO uint16_t SEL85; /**< Crossbar A Select Register 85, offset: 0xAA */
__IO uint16_t SEL86; /**< Crossbar A Select Register 86, offset: 0xAC */
__IO uint16_t SEL87; /**< Crossbar A Select Register 87, offset: 0xAE */
__IO uint16_t CTRL0; /**< Crossbar A Control Register 0, offset: 0xB0 */
__IO uint16_t CTRL1; /**< Crossbar A Control Register 1, offset: 0xB2 */
} XBARA_Type;
/* ----------------------------------------------------------------------------
-- XBARA Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup XBARA_Register_Masks XBARA Register Masks
* @{
*/
/*! @name SEL0 - Crossbar A Select Register 0 */
/*! @{ */
#define XBARA_SEL0_SEL0_MASK (0xFFU)
#define XBARA_SEL0_SEL0_SHIFT (0U)
#define XBARA_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL0_SHIFT)) & XBARA_SEL0_SEL0_MASK)
#define XBARA_SEL0_SEL1_MASK (0xFF00U)
#define XBARA_SEL0_SEL1_SHIFT (8U)
#define XBARA_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL0_SEL1_SHIFT)) & XBARA_SEL0_SEL1_MASK)
/*! @} */
/*! @name SEL1 - Crossbar A Select Register 1 */
/*! @{ */
#define XBARA_SEL1_SEL2_MASK (0xFFU)
#define XBARA_SEL1_SEL2_SHIFT (0U)
#define XBARA_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL2_SHIFT)) & XBARA_SEL1_SEL2_MASK)
#define XBARA_SEL1_SEL3_MASK (0xFF00U)
#define XBARA_SEL1_SEL3_SHIFT (8U)
#define XBARA_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL1_SEL3_SHIFT)) & XBARA_SEL1_SEL3_MASK)
/*! @} */
/*! @name SEL2 - Crossbar A Select Register 2 */
/*! @{ */
#define XBARA_SEL2_SEL4_MASK (0xFFU)
#define XBARA_SEL2_SEL4_SHIFT (0U)
#define XBARA_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL4_SHIFT)) & XBARA_SEL2_SEL4_MASK)
#define XBARA_SEL2_SEL5_MASK (0xFF00U)
#define XBARA_SEL2_SEL5_SHIFT (8U)
#define XBARA_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL2_SEL5_SHIFT)) & XBARA_SEL2_SEL5_MASK)
/*! @} */
/*! @name SEL3 - Crossbar A Select Register 3 */
/*! @{ */
#define XBARA_SEL3_SEL6_MASK (0xFFU)
#define XBARA_SEL3_SEL6_SHIFT (0U)
#define XBARA_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL6_SHIFT)) & XBARA_SEL3_SEL6_MASK)
#define XBARA_SEL3_SEL7_MASK (0xFF00U)
#define XBARA_SEL3_SEL7_SHIFT (8U)
#define XBARA_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL3_SEL7_SHIFT)) & XBARA_SEL3_SEL7_MASK)
/*! @} */
/*! @name SEL4 - Crossbar A Select Register 4 */
/*! @{ */
#define XBARA_SEL4_SEL8_MASK (0xFFU)
#define XBARA_SEL4_SEL8_SHIFT (0U)
#define XBARA_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL8_SHIFT)) & XBARA_SEL4_SEL8_MASK)
#define XBARA_SEL4_SEL9_MASK (0xFF00U)
#define XBARA_SEL4_SEL9_SHIFT (8U)
#define XBARA_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL4_SEL9_SHIFT)) & XBARA_SEL4_SEL9_MASK)
/*! @} */
/*! @name SEL5 - Crossbar A Select Register 5 */
/*! @{ */
#define XBARA_SEL5_SEL10_MASK (0xFFU)
#define XBARA_SEL5_SEL10_SHIFT (0U)
#define XBARA_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL10_SHIFT)) & XBARA_SEL5_SEL10_MASK)
#define XBARA_SEL5_SEL11_MASK (0xFF00U)
#define XBARA_SEL5_SEL11_SHIFT (8U)
#define XBARA_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL5_SEL11_SHIFT)) & XBARA_SEL5_SEL11_MASK)
/*! @} */
/*! @name SEL6 - Crossbar A Select Register 6 */
/*! @{ */
#define XBARA_SEL6_SEL12_MASK (0xFFU)
#define XBARA_SEL6_SEL12_SHIFT (0U)
#define XBARA_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL12_SHIFT)) & XBARA_SEL6_SEL12_MASK)
#define XBARA_SEL6_SEL13_MASK (0xFF00U)
#define XBARA_SEL6_SEL13_SHIFT (8U)
#define XBARA_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL6_SEL13_SHIFT)) & XBARA_SEL6_SEL13_MASK)
/*! @} */
/*! @name SEL7 - Crossbar A Select Register 7 */
/*! @{ */
#define XBARA_SEL7_SEL14_MASK (0xFFU)
#define XBARA_SEL7_SEL14_SHIFT (0U)
#define XBARA_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL14_SHIFT)) & XBARA_SEL7_SEL14_MASK)
#define XBARA_SEL7_SEL15_MASK (0xFF00U)
#define XBARA_SEL7_SEL15_SHIFT (8U)
#define XBARA_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL7_SEL15_SHIFT)) & XBARA_SEL7_SEL15_MASK)
/*! @} */
/*! @name SEL8 - Crossbar A Select Register 8 */
/*! @{ */
#define XBARA_SEL8_SEL16_MASK (0xFFU)
#define XBARA_SEL8_SEL16_SHIFT (0U)
#define XBARA_SEL8_SEL16(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL16_SHIFT)) & XBARA_SEL8_SEL16_MASK)
#define XBARA_SEL8_SEL17_MASK (0xFF00U)
#define XBARA_SEL8_SEL17_SHIFT (8U)
#define XBARA_SEL8_SEL17(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL8_SEL17_SHIFT)) & XBARA_SEL8_SEL17_MASK)
/*! @} */
/*! @name SEL9 - Crossbar A Select Register 9 */
/*! @{ */
#define XBARA_SEL9_SEL18_MASK (0xFFU)
#define XBARA_SEL9_SEL18_SHIFT (0U)
#define XBARA_SEL9_SEL18(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL18_SHIFT)) & XBARA_SEL9_SEL18_MASK)
#define XBARA_SEL9_SEL19_MASK (0xFF00U)
#define XBARA_SEL9_SEL19_SHIFT (8U)
#define XBARA_SEL9_SEL19(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL9_SEL19_SHIFT)) & XBARA_SEL9_SEL19_MASK)
/*! @} */
/*! @name SEL10 - Crossbar A Select Register 10 */
/*! @{ */
#define XBARA_SEL10_SEL20_MASK (0xFFU)
#define XBARA_SEL10_SEL20_SHIFT (0U)
#define XBARA_SEL10_SEL20(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL20_SHIFT)) & XBARA_SEL10_SEL20_MASK)
#define XBARA_SEL10_SEL21_MASK (0xFF00U)
#define XBARA_SEL10_SEL21_SHIFT (8U)
#define XBARA_SEL10_SEL21(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL10_SEL21_SHIFT)) & XBARA_SEL10_SEL21_MASK)
/*! @} */
/*! @name SEL11 - Crossbar A Select Register 11 */
/*! @{ */
#define XBARA_SEL11_SEL22_MASK (0xFFU)
#define XBARA_SEL11_SEL22_SHIFT (0U)
#define XBARA_SEL11_SEL22(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL22_SHIFT)) & XBARA_SEL11_SEL22_MASK)
#define XBARA_SEL11_SEL23_MASK (0xFF00U)
#define XBARA_SEL11_SEL23_SHIFT (8U)
#define XBARA_SEL11_SEL23(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL11_SEL23_SHIFT)) & XBARA_SEL11_SEL23_MASK)
/*! @} */
/*! @name SEL12 - Crossbar A Select Register 12 */
/*! @{ */
#define XBARA_SEL12_SEL24_MASK (0xFFU)
#define XBARA_SEL12_SEL24_SHIFT (0U)
#define XBARA_SEL12_SEL24(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL24_SHIFT)) & XBARA_SEL12_SEL24_MASK)
#define XBARA_SEL12_SEL25_MASK (0xFF00U)
#define XBARA_SEL12_SEL25_SHIFT (8U)
#define XBARA_SEL12_SEL25(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL12_SEL25_SHIFT)) & XBARA_SEL12_SEL25_MASK)
/*! @} */
/*! @name SEL13 - Crossbar A Select Register 13 */
/*! @{ */
#define XBARA_SEL13_SEL26_MASK (0xFFU)
#define XBARA_SEL13_SEL26_SHIFT (0U)
#define XBARA_SEL13_SEL26(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL26_SHIFT)) & XBARA_SEL13_SEL26_MASK)
#define XBARA_SEL13_SEL27_MASK (0xFF00U)
#define XBARA_SEL13_SEL27_SHIFT (8U)
#define XBARA_SEL13_SEL27(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL13_SEL27_SHIFT)) & XBARA_SEL13_SEL27_MASK)
/*! @} */
/*! @name SEL14 - Crossbar A Select Register 14 */
/*! @{ */
#define XBARA_SEL14_SEL28_MASK (0xFFU)
#define XBARA_SEL14_SEL28_SHIFT (0U)
#define XBARA_SEL14_SEL28(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL28_SHIFT)) & XBARA_SEL14_SEL28_MASK)
#define XBARA_SEL14_SEL29_MASK (0xFF00U)
#define XBARA_SEL14_SEL29_SHIFT (8U)
#define XBARA_SEL14_SEL29(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL14_SEL29_SHIFT)) & XBARA_SEL14_SEL29_MASK)
/*! @} */
/*! @name SEL15 - Crossbar A Select Register 15 */
/*! @{ */
#define XBARA_SEL15_SEL30_MASK (0xFFU)
#define XBARA_SEL15_SEL30_SHIFT (0U)
#define XBARA_SEL15_SEL30(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL30_SHIFT)) & XBARA_SEL15_SEL30_MASK)
#define XBARA_SEL15_SEL31_MASK (0xFF00U)
#define XBARA_SEL15_SEL31_SHIFT (8U)
#define XBARA_SEL15_SEL31(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL15_SEL31_SHIFT)) & XBARA_SEL15_SEL31_MASK)
/*! @} */
/*! @name SEL16 - Crossbar A Select Register 16 */
/*! @{ */
#define XBARA_SEL16_SEL32_MASK (0xFFU)
#define XBARA_SEL16_SEL32_SHIFT (0U)
#define XBARA_SEL16_SEL32(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL32_SHIFT)) & XBARA_SEL16_SEL32_MASK)
#define XBARA_SEL16_SEL33_MASK (0xFF00U)
#define XBARA_SEL16_SEL33_SHIFT (8U)
#define XBARA_SEL16_SEL33(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL16_SEL33_SHIFT)) & XBARA_SEL16_SEL33_MASK)
/*! @} */
/*! @name SEL17 - Crossbar A Select Register 17 */
/*! @{ */
#define XBARA_SEL17_SEL34_MASK (0xFFU)
#define XBARA_SEL17_SEL34_SHIFT (0U)
#define XBARA_SEL17_SEL34(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL34_SHIFT)) & XBARA_SEL17_SEL34_MASK)
#define XBARA_SEL17_SEL35_MASK (0xFF00U)
#define XBARA_SEL17_SEL35_SHIFT (8U)
#define XBARA_SEL17_SEL35(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL17_SEL35_SHIFT)) & XBARA_SEL17_SEL35_MASK)
/*! @} */
/*! @name SEL18 - Crossbar A Select Register 18 */
/*! @{ */
#define XBARA_SEL18_SEL36_MASK (0xFFU)
#define XBARA_SEL18_SEL36_SHIFT (0U)
#define XBARA_SEL18_SEL36(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL36_SHIFT)) & XBARA_SEL18_SEL36_MASK)
#define XBARA_SEL18_SEL37_MASK (0xFF00U)
#define XBARA_SEL18_SEL37_SHIFT (8U)
#define XBARA_SEL18_SEL37(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL18_SEL37_SHIFT)) & XBARA_SEL18_SEL37_MASK)
/*! @} */
/*! @name SEL19 - Crossbar A Select Register 19 */
/*! @{ */
#define XBARA_SEL19_SEL38_MASK (0xFFU)
#define XBARA_SEL19_SEL38_SHIFT (0U)
#define XBARA_SEL19_SEL38(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL38_SHIFT)) & XBARA_SEL19_SEL38_MASK)
#define XBARA_SEL19_SEL39_MASK (0xFF00U)
#define XBARA_SEL19_SEL39_SHIFT (8U)
#define XBARA_SEL19_SEL39(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL19_SEL39_SHIFT)) & XBARA_SEL19_SEL39_MASK)
/*! @} */
/*! @name SEL20 - Crossbar A Select Register 20 */
/*! @{ */
#define XBARA_SEL20_SEL40_MASK (0xFFU)
#define XBARA_SEL20_SEL40_SHIFT (0U)
#define XBARA_SEL20_SEL40(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL40_SHIFT)) & XBARA_SEL20_SEL40_MASK)
#define XBARA_SEL20_SEL41_MASK (0xFF00U)
#define XBARA_SEL20_SEL41_SHIFT (8U)
#define XBARA_SEL20_SEL41(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL20_SEL41_SHIFT)) & XBARA_SEL20_SEL41_MASK)
/*! @} */
/*! @name SEL21 - Crossbar A Select Register 21 */
/*! @{ */
#define XBARA_SEL21_SEL42_MASK (0xFFU)
#define XBARA_SEL21_SEL42_SHIFT (0U)
#define XBARA_SEL21_SEL42(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL42_SHIFT)) & XBARA_SEL21_SEL42_MASK)
#define XBARA_SEL21_SEL43_MASK (0xFF00U)
#define XBARA_SEL21_SEL43_SHIFT (8U)
#define XBARA_SEL21_SEL43(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL21_SEL43_SHIFT)) & XBARA_SEL21_SEL43_MASK)
/*! @} */
/*! @name SEL22 - Crossbar A Select Register 22 */
/*! @{ */
#define XBARA_SEL22_SEL44_MASK (0xFFU)
#define XBARA_SEL22_SEL44_SHIFT (0U)
#define XBARA_SEL22_SEL44(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL44_SHIFT)) & XBARA_SEL22_SEL44_MASK)
#define XBARA_SEL22_SEL45_MASK (0xFF00U)
#define XBARA_SEL22_SEL45_SHIFT (8U)
#define XBARA_SEL22_SEL45(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL22_SEL45_SHIFT)) & XBARA_SEL22_SEL45_MASK)
/*! @} */
/*! @name SEL23 - Crossbar A Select Register 23 */
/*! @{ */
#define XBARA_SEL23_SEL46_MASK (0xFFU)
#define XBARA_SEL23_SEL46_SHIFT (0U)
#define XBARA_SEL23_SEL46(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL46_SHIFT)) & XBARA_SEL23_SEL46_MASK)
#define XBARA_SEL23_SEL47_MASK (0xFF00U)
#define XBARA_SEL23_SEL47_SHIFT (8U)
#define XBARA_SEL23_SEL47(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL23_SEL47_SHIFT)) & XBARA_SEL23_SEL47_MASK)
/*! @} */
/*! @name SEL24 - Crossbar A Select Register 24 */
/*! @{ */
#define XBARA_SEL24_SEL48_MASK (0xFFU)
#define XBARA_SEL24_SEL48_SHIFT (0U)
#define XBARA_SEL24_SEL48(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL48_SHIFT)) & XBARA_SEL24_SEL48_MASK)
#define XBARA_SEL24_SEL49_MASK (0xFF00U)
#define XBARA_SEL24_SEL49_SHIFT (8U)
#define XBARA_SEL24_SEL49(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL24_SEL49_SHIFT)) & XBARA_SEL24_SEL49_MASK)
/*! @} */
/*! @name SEL25 - Crossbar A Select Register 25 */
/*! @{ */
#define XBARA_SEL25_SEL50_MASK (0xFFU)
#define XBARA_SEL25_SEL50_SHIFT (0U)
#define XBARA_SEL25_SEL50(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL50_SHIFT)) & XBARA_SEL25_SEL50_MASK)
#define XBARA_SEL25_SEL51_MASK (0xFF00U)
#define XBARA_SEL25_SEL51_SHIFT (8U)
#define XBARA_SEL25_SEL51(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL25_SEL51_SHIFT)) & XBARA_SEL25_SEL51_MASK)
/*! @} */
/*! @name SEL26 - Crossbar A Select Register 26 */
/*! @{ */
#define XBARA_SEL26_SEL52_MASK (0xFFU)
#define XBARA_SEL26_SEL52_SHIFT (0U)
#define XBARA_SEL26_SEL52(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL52_SHIFT)) & XBARA_SEL26_SEL52_MASK)
#define XBARA_SEL26_SEL53_MASK (0xFF00U)
#define XBARA_SEL26_SEL53_SHIFT (8U)
#define XBARA_SEL26_SEL53(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL26_SEL53_SHIFT)) & XBARA_SEL26_SEL53_MASK)
/*! @} */
/*! @name SEL27 - Crossbar A Select Register 27 */
/*! @{ */
#define XBARA_SEL27_SEL54_MASK (0xFFU)
#define XBARA_SEL27_SEL54_SHIFT (0U)
#define XBARA_SEL27_SEL54(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL54_SHIFT)) & XBARA_SEL27_SEL54_MASK)
#define XBARA_SEL27_SEL55_MASK (0xFF00U)
#define XBARA_SEL27_SEL55_SHIFT (8U)
#define XBARA_SEL27_SEL55(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL27_SEL55_SHIFT)) & XBARA_SEL27_SEL55_MASK)
/*! @} */
/*! @name SEL28 - Crossbar A Select Register 28 */
/*! @{ */
#define XBARA_SEL28_SEL56_MASK (0xFFU)
#define XBARA_SEL28_SEL56_SHIFT (0U)
#define XBARA_SEL28_SEL56(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL56_SHIFT)) & XBARA_SEL28_SEL56_MASK)
#define XBARA_SEL28_SEL57_MASK (0xFF00U)
#define XBARA_SEL28_SEL57_SHIFT (8U)
#define XBARA_SEL28_SEL57(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL28_SEL57_SHIFT)) & XBARA_SEL28_SEL57_MASK)
/*! @} */
/*! @name SEL29 - Crossbar A Select Register 29 */
/*! @{ */
#define XBARA_SEL29_SEL58_MASK (0xFFU)
#define XBARA_SEL29_SEL58_SHIFT (0U)
#define XBARA_SEL29_SEL58(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL58_SHIFT)) & XBARA_SEL29_SEL58_MASK)
#define XBARA_SEL29_SEL59_MASK (0xFF00U)
#define XBARA_SEL29_SEL59_SHIFT (8U)
#define XBARA_SEL29_SEL59(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL29_SEL59_SHIFT)) & XBARA_SEL29_SEL59_MASK)
/*! @} */
/*! @name SEL30 - Crossbar A Select Register 30 */
/*! @{ */
#define XBARA_SEL30_SEL60_MASK (0xFFU)
#define XBARA_SEL30_SEL60_SHIFT (0U)
#define XBARA_SEL30_SEL60(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL60_SHIFT)) & XBARA_SEL30_SEL60_MASK)
#define XBARA_SEL30_SEL61_MASK (0xFF00U)
#define XBARA_SEL30_SEL61_SHIFT (8U)
#define XBARA_SEL30_SEL61(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL30_SEL61_SHIFT)) & XBARA_SEL30_SEL61_MASK)
/*! @} */
/*! @name SEL31 - Crossbar A Select Register 31 */
/*! @{ */
#define XBARA_SEL31_SEL62_MASK (0xFFU)
#define XBARA_SEL31_SEL62_SHIFT (0U)
#define XBARA_SEL31_SEL62(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL62_SHIFT)) & XBARA_SEL31_SEL62_MASK)
#define XBARA_SEL31_SEL63_MASK (0xFF00U)
#define XBARA_SEL31_SEL63_SHIFT (8U)
#define XBARA_SEL31_SEL63(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL31_SEL63_SHIFT)) & XBARA_SEL31_SEL63_MASK)
/*! @} */
/*! @name SEL32 - Crossbar A Select Register 32 */
/*! @{ */
#define XBARA_SEL32_SEL64_MASK (0xFFU)
#define XBARA_SEL32_SEL64_SHIFT (0U)
#define XBARA_SEL32_SEL64(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL64_SHIFT)) & XBARA_SEL32_SEL64_MASK)
#define XBARA_SEL32_SEL65_MASK (0xFF00U)
#define XBARA_SEL32_SEL65_SHIFT (8U)
#define XBARA_SEL32_SEL65(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL32_SEL65_SHIFT)) & XBARA_SEL32_SEL65_MASK)
/*! @} */
/*! @name SEL33 - Crossbar A Select Register 33 */
/*! @{ */
#define XBARA_SEL33_SEL66_MASK (0xFFU)
#define XBARA_SEL33_SEL66_SHIFT (0U)
#define XBARA_SEL33_SEL66(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL66_SHIFT)) & XBARA_SEL33_SEL66_MASK)
#define XBARA_SEL33_SEL67_MASK (0xFF00U)
#define XBARA_SEL33_SEL67_SHIFT (8U)
#define XBARA_SEL33_SEL67(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL33_SEL67_SHIFT)) & XBARA_SEL33_SEL67_MASK)
/*! @} */
/*! @name SEL34 - Crossbar A Select Register 34 */
/*! @{ */
#define XBARA_SEL34_SEL68_MASK (0xFFU)
#define XBARA_SEL34_SEL68_SHIFT (0U)
#define XBARA_SEL34_SEL68(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL68_SHIFT)) & XBARA_SEL34_SEL68_MASK)
#define XBARA_SEL34_SEL69_MASK (0xFF00U)
#define XBARA_SEL34_SEL69_SHIFT (8U)
#define XBARA_SEL34_SEL69(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL34_SEL69_SHIFT)) & XBARA_SEL34_SEL69_MASK)
/*! @} */
/*! @name SEL35 - Crossbar A Select Register 35 */
/*! @{ */
#define XBARA_SEL35_SEL70_MASK (0xFFU)
#define XBARA_SEL35_SEL70_SHIFT (0U)
#define XBARA_SEL35_SEL70(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL70_SHIFT)) & XBARA_SEL35_SEL70_MASK)
#define XBARA_SEL35_SEL71_MASK (0xFF00U)
#define XBARA_SEL35_SEL71_SHIFT (8U)
#define XBARA_SEL35_SEL71(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL35_SEL71_SHIFT)) & XBARA_SEL35_SEL71_MASK)
/*! @} */
/*! @name SEL36 - Crossbar A Select Register 36 */
/*! @{ */
#define XBARA_SEL36_SEL72_MASK (0xFFU)
#define XBARA_SEL36_SEL72_SHIFT (0U)
#define XBARA_SEL36_SEL72(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL72_SHIFT)) & XBARA_SEL36_SEL72_MASK)
#define XBARA_SEL36_SEL73_MASK (0xFF00U)
#define XBARA_SEL36_SEL73_SHIFT (8U)
#define XBARA_SEL36_SEL73(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL36_SEL73_SHIFT)) & XBARA_SEL36_SEL73_MASK)
/*! @} */
/*! @name SEL37 - Crossbar A Select Register 37 */
/*! @{ */
#define XBARA_SEL37_SEL74_MASK (0xFFU)
#define XBARA_SEL37_SEL74_SHIFT (0U)
#define XBARA_SEL37_SEL74(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL74_SHIFT)) & XBARA_SEL37_SEL74_MASK)
#define XBARA_SEL37_SEL75_MASK (0xFF00U)
#define XBARA_SEL37_SEL75_SHIFT (8U)
#define XBARA_SEL37_SEL75(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL37_SEL75_SHIFT)) & XBARA_SEL37_SEL75_MASK)
/*! @} */
/*! @name SEL38 - Crossbar A Select Register 38 */
/*! @{ */
#define XBARA_SEL38_SEL76_MASK (0xFFU)
#define XBARA_SEL38_SEL76_SHIFT (0U)
#define XBARA_SEL38_SEL76(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL76_SHIFT)) & XBARA_SEL38_SEL76_MASK)
#define XBARA_SEL38_SEL77_MASK (0xFF00U)
#define XBARA_SEL38_SEL77_SHIFT (8U)
#define XBARA_SEL38_SEL77(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL38_SEL77_SHIFT)) & XBARA_SEL38_SEL77_MASK)
/*! @} */
/*! @name SEL39 - Crossbar A Select Register 39 */
/*! @{ */
#define XBARA_SEL39_SEL78_MASK (0xFFU)
#define XBARA_SEL39_SEL78_SHIFT (0U)
#define XBARA_SEL39_SEL78(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL78_SHIFT)) & XBARA_SEL39_SEL78_MASK)
#define XBARA_SEL39_SEL79_MASK (0xFF00U)
#define XBARA_SEL39_SEL79_SHIFT (8U)
#define XBARA_SEL39_SEL79(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL39_SEL79_SHIFT)) & XBARA_SEL39_SEL79_MASK)
/*! @} */
/*! @name SEL40 - Crossbar A Select Register 40 */
/*! @{ */
#define XBARA_SEL40_SEL80_MASK (0xFFU)
#define XBARA_SEL40_SEL80_SHIFT (0U)
#define XBARA_SEL40_SEL80(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL80_SHIFT)) & XBARA_SEL40_SEL80_MASK)
#define XBARA_SEL40_SEL81_MASK (0xFF00U)
#define XBARA_SEL40_SEL81_SHIFT (8U)
#define XBARA_SEL40_SEL81(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL40_SEL81_SHIFT)) & XBARA_SEL40_SEL81_MASK)
/*! @} */
/*! @name SEL41 - Crossbar A Select Register 41 */
/*! @{ */
#define XBARA_SEL41_SEL82_MASK (0xFFU)
#define XBARA_SEL41_SEL82_SHIFT (0U)
#define XBARA_SEL41_SEL82(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL82_SHIFT)) & XBARA_SEL41_SEL82_MASK)
#define XBARA_SEL41_SEL83_MASK (0xFF00U)
#define XBARA_SEL41_SEL83_SHIFT (8U)
#define XBARA_SEL41_SEL83(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL41_SEL83_SHIFT)) & XBARA_SEL41_SEL83_MASK)
/*! @} */
/*! @name SEL42 - Crossbar A Select Register 42 */
/*! @{ */
#define XBARA_SEL42_SEL84_MASK (0xFFU)
#define XBARA_SEL42_SEL84_SHIFT (0U)
#define XBARA_SEL42_SEL84(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL84_SHIFT)) & XBARA_SEL42_SEL84_MASK)
#define XBARA_SEL42_SEL85_MASK (0xFF00U)
#define XBARA_SEL42_SEL85_SHIFT (8U)
#define XBARA_SEL42_SEL85(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL42_SEL85_SHIFT)) & XBARA_SEL42_SEL85_MASK)
/*! @} */
/*! @name SEL43 - Crossbar A Select Register 43 */
/*! @{ */
#define XBARA_SEL43_SEL86_MASK (0xFFU)
#define XBARA_SEL43_SEL86_SHIFT (0U)
#define XBARA_SEL43_SEL86(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL86_SHIFT)) & XBARA_SEL43_SEL86_MASK)
#define XBARA_SEL43_SEL87_MASK (0xFF00U)
#define XBARA_SEL43_SEL87_SHIFT (8U)
#define XBARA_SEL43_SEL87(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL43_SEL87_SHIFT)) & XBARA_SEL43_SEL87_MASK)
/*! @} */
/*! @name SEL44 - Crossbar A Select Register 44 */
/*! @{ */
#define XBARA_SEL44_SEL88_MASK (0xFFU)
#define XBARA_SEL44_SEL88_SHIFT (0U)
#define XBARA_SEL44_SEL88(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL88_SHIFT)) & XBARA_SEL44_SEL88_MASK)
#define XBARA_SEL44_SEL89_MASK (0xFF00U)
#define XBARA_SEL44_SEL89_SHIFT (8U)
#define XBARA_SEL44_SEL89(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL44_SEL89_SHIFT)) & XBARA_SEL44_SEL89_MASK)
/*! @} */
/*! @name SEL45 - Crossbar A Select Register 45 */
/*! @{ */
#define XBARA_SEL45_SEL90_MASK (0xFFU)
#define XBARA_SEL45_SEL90_SHIFT (0U)
#define XBARA_SEL45_SEL90(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL90_SHIFT)) & XBARA_SEL45_SEL90_MASK)
#define XBARA_SEL45_SEL91_MASK (0xFF00U)
#define XBARA_SEL45_SEL91_SHIFT (8U)
#define XBARA_SEL45_SEL91(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL45_SEL91_SHIFT)) & XBARA_SEL45_SEL91_MASK)
/*! @} */
/*! @name SEL46 - Crossbar A Select Register 46 */
/*! @{ */
#define XBARA_SEL46_SEL92_MASK (0xFFU)
#define XBARA_SEL46_SEL92_SHIFT (0U)
#define XBARA_SEL46_SEL92(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL92_SHIFT)) & XBARA_SEL46_SEL92_MASK)
#define XBARA_SEL46_SEL93_MASK (0xFF00U)
#define XBARA_SEL46_SEL93_SHIFT (8U)
#define XBARA_SEL46_SEL93(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL46_SEL93_SHIFT)) & XBARA_SEL46_SEL93_MASK)
/*! @} */
/*! @name SEL47 - Crossbar A Select Register 47 */
/*! @{ */
#define XBARA_SEL47_SEL94_MASK (0xFFU)
#define XBARA_SEL47_SEL94_SHIFT (0U)
#define XBARA_SEL47_SEL94(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL94_SHIFT)) & XBARA_SEL47_SEL94_MASK)
#define XBARA_SEL47_SEL95_MASK (0xFF00U)
#define XBARA_SEL47_SEL95_SHIFT (8U)
#define XBARA_SEL47_SEL95(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL47_SEL95_SHIFT)) & XBARA_SEL47_SEL95_MASK)
/*! @} */
/*! @name SEL48 - Crossbar A Select Register 48 */
/*! @{ */
#define XBARA_SEL48_SEL96_MASK (0xFFU)
#define XBARA_SEL48_SEL96_SHIFT (0U)
#define XBARA_SEL48_SEL96(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL96_SHIFT)) & XBARA_SEL48_SEL96_MASK)
#define XBARA_SEL48_SEL97_MASK (0xFF00U)
#define XBARA_SEL48_SEL97_SHIFT (8U)
#define XBARA_SEL48_SEL97(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL48_SEL97_SHIFT)) & XBARA_SEL48_SEL97_MASK)
/*! @} */
/*! @name SEL49 - Crossbar A Select Register 49 */
/*! @{ */
#define XBARA_SEL49_SEL98_MASK (0xFFU)
#define XBARA_SEL49_SEL98_SHIFT (0U)
#define XBARA_SEL49_SEL98(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL98_SHIFT)) & XBARA_SEL49_SEL98_MASK)
#define XBARA_SEL49_SEL99_MASK (0xFF00U)
#define XBARA_SEL49_SEL99_SHIFT (8U)
#define XBARA_SEL49_SEL99(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL49_SEL99_SHIFT)) & XBARA_SEL49_SEL99_MASK)
/*! @} */
/*! @name SEL50 - Crossbar A Select Register 50 */
/*! @{ */
#define XBARA_SEL50_SEL100_MASK (0xFFU)
#define XBARA_SEL50_SEL100_SHIFT (0U)
#define XBARA_SEL50_SEL100(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL100_SHIFT)) & XBARA_SEL50_SEL100_MASK)
#define XBARA_SEL50_SEL101_MASK (0xFF00U)
#define XBARA_SEL50_SEL101_SHIFT (8U)
#define XBARA_SEL50_SEL101(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL50_SEL101_SHIFT)) & XBARA_SEL50_SEL101_MASK)
/*! @} */
/*! @name SEL51 - Crossbar A Select Register 51 */
/*! @{ */
#define XBARA_SEL51_SEL102_MASK (0xFFU)
#define XBARA_SEL51_SEL102_SHIFT (0U)
#define XBARA_SEL51_SEL102(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL102_SHIFT)) & XBARA_SEL51_SEL102_MASK)
#define XBARA_SEL51_SEL103_MASK (0xFF00U)
#define XBARA_SEL51_SEL103_SHIFT (8U)
#define XBARA_SEL51_SEL103(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL51_SEL103_SHIFT)) & XBARA_SEL51_SEL103_MASK)
/*! @} */
/*! @name SEL52 - Crossbar A Select Register 52 */
/*! @{ */
#define XBARA_SEL52_SEL104_MASK (0xFFU)
#define XBARA_SEL52_SEL104_SHIFT (0U)
#define XBARA_SEL52_SEL104(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL104_SHIFT)) & XBARA_SEL52_SEL104_MASK)
#define XBARA_SEL52_SEL105_MASK (0xFF00U)
#define XBARA_SEL52_SEL105_SHIFT (8U)
#define XBARA_SEL52_SEL105(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL52_SEL105_SHIFT)) & XBARA_SEL52_SEL105_MASK)
/*! @} */
/*! @name SEL53 - Crossbar A Select Register 53 */
/*! @{ */
#define XBARA_SEL53_SEL106_MASK (0xFFU)
#define XBARA_SEL53_SEL106_SHIFT (0U)
#define XBARA_SEL53_SEL106(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL106_SHIFT)) & XBARA_SEL53_SEL106_MASK)
#define XBARA_SEL53_SEL107_MASK (0xFF00U)
#define XBARA_SEL53_SEL107_SHIFT (8U)
#define XBARA_SEL53_SEL107(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL53_SEL107_SHIFT)) & XBARA_SEL53_SEL107_MASK)
/*! @} */
/*! @name SEL54 - Crossbar A Select Register 54 */
/*! @{ */
#define XBARA_SEL54_SEL108_MASK (0xFFU)
#define XBARA_SEL54_SEL108_SHIFT (0U)
#define XBARA_SEL54_SEL108(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL108_SHIFT)) & XBARA_SEL54_SEL108_MASK)
#define XBARA_SEL54_SEL109_MASK (0xFF00U)
#define XBARA_SEL54_SEL109_SHIFT (8U)
#define XBARA_SEL54_SEL109(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL54_SEL109_SHIFT)) & XBARA_SEL54_SEL109_MASK)
/*! @} */
/*! @name SEL55 - Crossbar A Select Register 55 */
/*! @{ */
#define XBARA_SEL55_SEL110_MASK (0xFFU)
#define XBARA_SEL55_SEL110_SHIFT (0U)
#define XBARA_SEL55_SEL110(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL110_SHIFT)) & XBARA_SEL55_SEL110_MASK)
#define XBARA_SEL55_SEL111_MASK (0xFF00U)
#define XBARA_SEL55_SEL111_SHIFT (8U)
#define XBARA_SEL55_SEL111(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL55_SEL111_SHIFT)) & XBARA_SEL55_SEL111_MASK)
/*! @} */
/*! @name SEL56 - Crossbar A Select Register 56 */
/*! @{ */
#define XBARA_SEL56_SEL112_MASK (0xFFU)
#define XBARA_SEL56_SEL112_SHIFT (0U)
#define XBARA_SEL56_SEL112(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL112_SHIFT)) & XBARA_SEL56_SEL112_MASK)
#define XBARA_SEL56_SEL113_MASK (0xFF00U)
#define XBARA_SEL56_SEL113_SHIFT (8U)
#define XBARA_SEL56_SEL113(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL56_SEL113_SHIFT)) & XBARA_SEL56_SEL113_MASK)
/*! @} */
/*! @name SEL57 - Crossbar A Select Register 57 */
/*! @{ */
#define XBARA_SEL57_SEL114_MASK (0xFFU)
#define XBARA_SEL57_SEL114_SHIFT (0U)
#define XBARA_SEL57_SEL114(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL114_SHIFT)) & XBARA_SEL57_SEL114_MASK)
#define XBARA_SEL57_SEL115_MASK (0xFF00U)
#define XBARA_SEL57_SEL115_SHIFT (8U)
#define XBARA_SEL57_SEL115(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL57_SEL115_SHIFT)) & XBARA_SEL57_SEL115_MASK)
/*! @} */
/*! @name SEL58 - Crossbar A Select Register 58 */
/*! @{ */
#define XBARA_SEL58_SEL116_MASK (0xFFU)
#define XBARA_SEL58_SEL116_SHIFT (0U)
#define XBARA_SEL58_SEL116(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL116_SHIFT)) & XBARA_SEL58_SEL116_MASK)
#define XBARA_SEL58_SEL117_MASK (0xFF00U)
#define XBARA_SEL58_SEL117_SHIFT (8U)
#define XBARA_SEL58_SEL117(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL58_SEL117_SHIFT)) & XBARA_SEL58_SEL117_MASK)
/*! @} */
/*! @name SEL59 - Crossbar A Select Register 59 */
/*! @{ */
#define XBARA_SEL59_SEL118_MASK (0xFFU)
#define XBARA_SEL59_SEL118_SHIFT (0U)
#define XBARA_SEL59_SEL118(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL118_SHIFT)) & XBARA_SEL59_SEL118_MASK)
#define XBARA_SEL59_SEL119_MASK (0xFF00U)
#define XBARA_SEL59_SEL119_SHIFT (8U)
#define XBARA_SEL59_SEL119(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL59_SEL119_SHIFT)) & XBARA_SEL59_SEL119_MASK)
/*! @} */
/*! @name SEL60 - Crossbar A Select Register 60 */
/*! @{ */
#define XBARA_SEL60_SEL120_MASK (0xFFU)
#define XBARA_SEL60_SEL120_SHIFT (0U)
#define XBARA_SEL60_SEL120(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL120_SHIFT)) & XBARA_SEL60_SEL120_MASK)
#define XBARA_SEL60_SEL121_MASK (0xFF00U)
#define XBARA_SEL60_SEL121_SHIFT (8U)
#define XBARA_SEL60_SEL121(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL60_SEL121_SHIFT)) & XBARA_SEL60_SEL121_MASK)
/*! @} */
/*! @name SEL61 - Crossbar A Select Register 61 */
/*! @{ */
#define XBARA_SEL61_SEL122_MASK (0xFFU)
#define XBARA_SEL61_SEL122_SHIFT (0U)
#define XBARA_SEL61_SEL122(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL122_SHIFT)) & XBARA_SEL61_SEL122_MASK)
#define XBARA_SEL61_SEL123_MASK (0xFF00U)
#define XBARA_SEL61_SEL123_SHIFT (8U)
#define XBARA_SEL61_SEL123(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL61_SEL123_SHIFT)) & XBARA_SEL61_SEL123_MASK)
/*! @} */
/*! @name SEL62 - Crossbar A Select Register 62 */
/*! @{ */
#define XBARA_SEL62_SEL124_MASK (0xFFU)
#define XBARA_SEL62_SEL124_SHIFT (0U)
#define XBARA_SEL62_SEL124(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL124_SHIFT)) & XBARA_SEL62_SEL124_MASK)
#define XBARA_SEL62_SEL125_MASK (0xFF00U)
#define XBARA_SEL62_SEL125_SHIFT (8U)
#define XBARA_SEL62_SEL125(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL62_SEL125_SHIFT)) & XBARA_SEL62_SEL125_MASK)
/*! @} */
/*! @name SEL63 - Crossbar A Select Register 63 */
/*! @{ */
#define XBARA_SEL63_SEL126_MASK (0xFFU)
#define XBARA_SEL63_SEL126_SHIFT (0U)
#define XBARA_SEL63_SEL126(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL126_SHIFT)) & XBARA_SEL63_SEL126_MASK)
#define XBARA_SEL63_SEL127_MASK (0xFF00U)
#define XBARA_SEL63_SEL127_SHIFT (8U)
#define XBARA_SEL63_SEL127(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL63_SEL127_SHIFT)) & XBARA_SEL63_SEL127_MASK)
/*! @} */
/*! @name SEL64 - Crossbar A Select Register 64 */
/*! @{ */
#define XBARA_SEL64_SEL128_MASK (0xFFU)
#define XBARA_SEL64_SEL128_SHIFT (0U)
#define XBARA_SEL64_SEL128(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL128_SHIFT)) & XBARA_SEL64_SEL128_MASK)
#define XBARA_SEL64_SEL129_MASK (0xFF00U)
#define XBARA_SEL64_SEL129_SHIFT (8U)
#define XBARA_SEL64_SEL129(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL64_SEL129_SHIFT)) & XBARA_SEL64_SEL129_MASK)
/*! @} */
/*! @name SEL65 - Crossbar A Select Register 65 */
/*! @{ */
#define XBARA_SEL65_SEL130_MASK (0xFFU)
#define XBARA_SEL65_SEL130_SHIFT (0U)
#define XBARA_SEL65_SEL130(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL130_SHIFT)) & XBARA_SEL65_SEL130_MASK)
#define XBARA_SEL65_SEL131_MASK (0xFF00U)
#define XBARA_SEL65_SEL131_SHIFT (8U)
#define XBARA_SEL65_SEL131(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL65_SEL131_SHIFT)) & XBARA_SEL65_SEL131_MASK)
/*! @} */
/*! @name SEL66 - Crossbar A Select Register 66 */
/*! @{ */
#define XBARA_SEL66_SEL132_MASK (0xFFU)
#define XBARA_SEL66_SEL132_SHIFT (0U)
#define XBARA_SEL66_SEL132(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL132_SHIFT)) & XBARA_SEL66_SEL132_MASK)
#define XBARA_SEL66_SEL133_MASK (0xFF00U)
#define XBARA_SEL66_SEL133_SHIFT (8U)
#define XBARA_SEL66_SEL133(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL66_SEL133_SHIFT)) & XBARA_SEL66_SEL133_MASK)
/*! @} */
/*! @name SEL67 - Crossbar A Select Register 67 */
/*! @{ */
#define XBARA_SEL67_SEL134_MASK (0xFFU)
#define XBARA_SEL67_SEL134_SHIFT (0U)
#define XBARA_SEL67_SEL134(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL134_SHIFT)) & XBARA_SEL67_SEL134_MASK)
#define XBARA_SEL67_SEL135_MASK (0xFF00U)
#define XBARA_SEL67_SEL135_SHIFT (8U)
#define XBARA_SEL67_SEL135(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL67_SEL135_SHIFT)) & XBARA_SEL67_SEL135_MASK)
/*! @} */
/*! @name SEL68 - Crossbar A Select Register 68 */
/*! @{ */
#define XBARA_SEL68_SEL136_MASK (0xFFU)
#define XBARA_SEL68_SEL136_SHIFT (0U)
#define XBARA_SEL68_SEL136(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL136_SHIFT)) & XBARA_SEL68_SEL136_MASK)
#define XBARA_SEL68_SEL137_MASK (0xFF00U)
#define XBARA_SEL68_SEL137_SHIFT (8U)
#define XBARA_SEL68_SEL137(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL68_SEL137_SHIFT)) & XBARA_SEL68_SEL137_MASK)
/*! @} */
/*! @name SEL69 - Crossbar A Select Register 69 */
/*! @{ */
#define XBARA_SEL69_SEL138_MASK (0xFFU)
#define XBARA_SEL69_SEL138_SHIFT (0U)
#define XBARA_SEL69_SEL138(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL138_SHIFT)) & XBARA_SEL69_SEL138_MASK)
#define XBARA_SEL69_SEL139_MASK (0xFF00U)
#define XBARA_SEL69_SEL139_SHIFT (8U)
#define XBARA_SEL69_SEL139(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL69_SEL139_SHIFT)) & XBARA_SEL69_SEL139_MASK)
/*! @} */
/*! @name SEL70 - Crossbar A Select Register 70 */
/*! @{ */
#define XBARA_SEL70_SEL140_MASK (0xFFU)
#define XBARA_SEL70_SEL140_SHIFT (0U)
#define XBARA_SEL70_SEL140(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL140_SHIFT)) & XBARA_SEL70_SEL140_MASK)
#define XBARA_SEL70_SEL141_MASK (0xFF00U)
#define XBARA_SEL70_SEL141_SHIFT (8U)
#define XBARA_SEL70_SEL141(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL70_SEL141_SHIFT)) & XBARA_SEL70_SEL141_MASK)
/*! @} */
/*! @name SEL71 - Crossbar A Select Register 71 */
/*! @{ */
#define XBARA_SEL71_SEL142_MASK (0xFFU)
#define XBARA_SEL71_SEL142_SHIFT (0U)
#define XBARA_SEL71_SEL142(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL142_SHIFT)) & XBARA_SEL71_SEL142_MASK)
#define XBARA_SEL71_SEL143_MASK (0xFF00U)
#define XBARA_SEL71_SEL143_SHIFT (8U)
#define XBARA_SEL71_SEL143(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL71_SEL143_SHIFT)) & XBARA_SEL71_SEL143_MASK)
/*! @} */
/*! @name SEL72 - Crossbar A Select Register 72 */
/*! @{ */
#define XBARA_SEL72_SEL144_MASK (0xFFU)
#define XBARA_SEL72_SEL144_SHIFT (0U)
#define XBARA_SEL72_SEL144(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL144_SHIFT)) & XBARA_SEL72_SEL144_MASK)
#define XBARA_SEL72_SEL145_MASK (0xFF00U)
#define XBARA_SEL72_SEL145_SHIFT (8U)
#define XBARA_SEL72_SEL145(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL72_SEL145_SHIFT)) & XBARA_SEL72_SEL145_MASK)
/*! @} */
/*! @name SEL73 - Crossbar A Select Register 73 */
/*! @{ */
#define XBARA_SEL73_SEL146_MASK (0xFFU)
#define XBARA_SEL73_SEL146_SHIFT (0U)
#define XBARA_SEL73_SEL146(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL146_SHIFT)) & XBARA_SEL73_SEL146_MASK)
#define XBARA_SEL73_SEL147_MASK (0xFF00U)
#define XBARA_SEL73_SEL147_SHIFT (8U)
#define XBARA_SEL73_SEL147(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL73_SEL147_SHIFT)) & XBARA_SEL73_SEL147_MASK)
/*! @} */
/*! @name SEL74 - Crossbar A Select Register 74 */
/*! @{ */
#define XBARA_SEL74_SEL148_MASK (0xFFU)
#define XBARA_SEL74_SEL148_SHIFT (0U)
#define XBARA_SEL74_SEL148(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL148_SHIFT)) & XBARA_SEL74_SEL148_MASK)
#define XBARA_SEL74_SEL149_MASK (0xFF00U)
#define XBARA_SEL74_SEL149_SHIFT (8U)
#define XBARA_SEL74_SEL149(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL74_SEL149_SHIFT)) & XBARA_SEL74_SEL149_MASK)
/*! @} */
/*! @name SEL75 - Crossbar A Select Register 75 */
/*! @{ */
#define XBARA_SEL75_SEL150_MASK (0xFFU)
#define XBARA_SEL75_SEL150_SHIFT (0U)
#define XBARA_SEL75_SEL150(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL150_SHIFT)) & XBARA_SEL75_SEL150_MASK)
#define XBARA_SEL75_SEL151_MASK (0xFF00U)
#define XBARA_SEL75_SEL151_SHIFT (8U)
#define XBARA_SEL75_SEL151(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL75_SEL151_SHIFT)) & XBARA_SEL75_SEL151_MASK)
/*! @} */
/*! @name SEL76 - Crossbar A Select Register 76 */
/*! @{ */
#define XBARA_SEL76_SEL152_MASK (0xFFU)
#define XBARA_SEL76_SEL152_SHIFT (0U)
#define XBARA_SEL76_SEL152(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL152_SHIFT)) & XBARA_SEL76_SEL152_MASK)
#define XBARA_SEL76_SEL153_MASK (0xFF00U)
#define XBARA_SEL76_SEL153_SHIFT (8U)
#define XBARA_SEL76_SEL153(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL76_SEL153_SHIFT)) & XBARA_SEL76_SEL153_MASK)
/*! @} */
/*! @name SEL77 - Crossbar A Select Register 77 */
/*! @{ */
#define XBARA_SEL77_SEL154_MASK (0xFFU)
#define XBARA_SEL77_SEL154_SHIFT (0U)
#define XBARA_SEL77_SEL154(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL154_SHIFT)) & XBARA_SEL77_SEL154_MASK)
#define XBARA_SEL77_SEL155_MASK (0xFF00U)
#define XBARA_SEL77_SEL155_SHIFT (8U)
#define XBARA_SEL77_SEL155(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL77_SEL155_SHIFT)) & XBARA_SEL77_SEL155_MASK)
/*! @} */
/*! @name SEL78 - Crossbar A Select Register 78 */
/*! @{ */
#define XBARA_SEL78_SEL156_MASK (0xFFU)
#define XBARA_SEL78_SEL156_SHIFT (0U)
#define XBARA_SEL78_SEL156(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL156_SHIFT)) & XBARA_SEL78_SEL156_MASK)
#define XBARA_SEL78_SEL157_MASK (0xFF00U)
#define XBARA_SEL78_SEL157_SHIFT (8U)
#define XBARA_SEL78_SEL157(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL78_SEL157_SHIFT)) & XBARA_SEL78_SEL157_MASK)
/*! @} */
/*! @name SEL79 - Crossbar A Select Register 79 */
/*! @{ */
#define XBARA_SEL79_SEL158_MASK (0xFFU)
#define XBARA_SEL79_SEL158_SHIFT (0U)
#define XBARA_SEL79_SEL158(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL158_SHIFT)) & XBARA_SEL79_SEL158_MASK)
#define XBARA_SEL79_SEL159_MASK (0xFF00U)
#define XBARA_SEL79_SEL159_SHIFT (8U)
#define XBARA_SEL79_SEL159(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL79_SEL159_SHIFT)) & XBARA_SEL79_SEL159_MASK)
/*! @} */
/*! @name SEL80 - Crossbar A Select Register 80 */
/*! @{ */
#define XBARA_SEL80_SEL160_MASK (0xFFU)
#define XBARA_SEL80_SEL160_SHIFT (0U)
#define XBARA_SEL80_SEL160(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL160_SHIFT)) & XBARA_SEL80_SEL160_MASK)
#define XBARA_SEL80_SEL161_MASK (0xFF00U)
#define XBARA_SEL80_SEL161_SHIFT (8U)
#define XBARA_SEL80_SEL161(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL80_SEL161_SHIFT)) & XBARA_SEL80_SEL161_MASK)
/*! @} */
/*! @name SEL81 - Crossbar A Select Register 81 */
/*! @{ */
#define XBARA_SEL81_SEL162_MASK (0xFFU)
#define XBARA_SEL81_SEL162_SHIFT (0U)
#define XBARA_SEL81_SEL162(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL162_SHIFT)) & XBARA_SEL81_SEL162_MASK)
#define XBARA_SEL81_SEL163_MASK (0xFF00U)
#define XBARA_SEL81_SEL163_SHIFT (8U)
#define XBARA_SEL81_SEL163(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL81_SEL163_SHIFT)) & XBARA_SEL81_SEL163_MASK)
/*! @} */
/*! @name SEL82 - Crossbar A Select Register 82 */
/*! @{ */
#define XBARA_SEL82_SEL164_MASK (0xFFU)
#define XBARA_SEL82_SEL164_SHIFT (0U)
#define XBARA_SEL82_SEL164(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL164_SHIFT)) & XBARA_SEL82_SEL164_MASK)
#define XBARA_SEL82_SEL165_MASK (0xFF00U)
#define XBARA_SEL82_SEL165_SHIFT (8U)
#define XBARA_SEL82_SEL165(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL82_SEL165_SHIFT)) & XBARA_SEL82_SEL165_MASK)
/*! @} */
/*! @name SEL83 - Crossbar A Select Register 83 */
/*! @{ */
#define XBARA_SEL83_SEL166_MASK (0xFFU)
#define XBARA_SEL83_SEL166_SHIFT (0U)
#define XBARA_SEL83_SEL166(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL166_SHIFT)) & XBARA_SEL83_SEL166_MASK)
#define XBARA_SEL83_SEL167_MASK (0xFF00U)
#define XBARA_SEL83_SEL167_SHIFT (8U)
#define XBARA_SEL83_SEL167(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL83_SEL167_SHIFT)) & XBARA_SEL83_SEL167_MASK)
/*! @} */
/*! @name SEL84 - Crossbar A Select Register 84 */
/*! @{ */
#define XBARA_SEL84_SEL168_MASK (0xFFU)
#define XBARA_SEL84_SEL168_SHIFT (0U)
#define XBARA_SEL84_SEL168(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL168_SHIFT)) & XBARA_SEL84_SEL168_MASK)
#define XBARA_SEL84_SEL169_MASK (0xFF00U)
#define XBARA_SEL84_SEL169_SHIFT (8U)
#define XBARA_SEL84_SEL169(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL84_SEL169_SHIFT)) & XBARA_SEL84_SEL169_MASK)
/*! @} */
/*! @name SEL85 - Crossbar A Select Register 85 */
/*! @{ */
#define XBARA_SEL85_SEL170_MASK (0xFFU)
#define XBARA_SEL85_SEL170_SHIFT (0U)
#define XBARA_SEL85_SEL170(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL170_SHIFT)) & XBARA_SEL85_SEL170_MASK)
#define XBARA_SEL85_SEL171_MASK (0xFF00U)
#define XBARA_SEL85_SEL171_SHIFT (8U)
#define XBARA_SEL85_SEL171(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL85_SEL171_SHIFT)) & XBARA_SEL85_SEL171_MASK)
/*! @} */
/*! @name SEL86 - Crossbar A Select Register 86 */
/*! @{ */
#define XBARA_SEL86_SEL172_MASK (0xFFU)
#define XBARA_SEL86_SEL172_SHIFT (0U)
#define XBARA_SEL86_SEL172(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL172_SHIFT)) & XBARA_SEL86_SEL172_MASK)
#define XBARA_SEL86_SEL173_MASK (0xFF00U)
#define XBARA_SEL86_SEL173_SHIFT (8U)
#define XBARA_SEL86_SEL173(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL86_SEL173_SHIFT)) & XBARA_SEL86_SEL173_MASK)
/*! @} */
/*! @name SEL87 - Crossbar A Select Register 87 */
/*! @{ */
#define XBARA_SEL87_SEL174_MASK (0xFFU)
#define XBARA_SEL87_SEL174_SHIFT (0U)
#define XBARA_SEL87_SEL174(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL174_SHIFT)) & XBARA_SEL87_SEL174_MASK)
#define XBARA_SEL87_SEL175_MASK (0xFF00U)
#define XBARA_SEL87_SEL175_SHIFT (8U)
#define XBARA_SEL87_SEL175(x) (((uint16_t)(((uint16_t)(x)) << XBARA_SEL87_SEL175_SHIFT)) & XBARA_SEL87_SEL175_MASK)
/*! @} */
/*! @name CTRL0 - Crossbar A Control Register 0 */
/*! @{ */
#define XBARA_CTRL0_DEN0_MASK (0x1U)
#define XBARA_CTRL0_DEN0_SHIFT (0U)
/*! DEN0 - DMA Enable for XBAR_OUT0
* 0b0..DMA disabled
* 0b1..DMA enabled
*/
#define XBARA_CTRL0_DEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN0_SHIFT)) & XBARA_CTRL0_DEN0_MASK)
#define XBARA_CTRL0_IEN0_MASK (0x2U)
#define XBARA_CTRL0_IEN0_SHIFT (1U)
/*! IEN0 - Interrupt Enable for XBAR_OUT0
* 0b0..Interrupt disabled
* 0b1..Interrupt enabled
*/
#define XBARA_CTRL0_IEN0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN0_SHIFT)) & XBARA_CTRL0_IEN0_MASK)
#define XBARA_CTRL0_EDGE0_MASK (0xCU)
#define XBARA_CTRL0_EDGE0_SHIFT (2U)
/*! EDGE0 - Active edge for edge detection on XBAR_OUT0
* 0b00..STS0 never asserts
* 0b01..STS0 asserts on rising edges of XBAR_OUT0
* 0b10..STS0 asserts on falling edges of XBAR_OUT0
* 0b11..STS0 asserts on rising and falling edges of XBAR_OUT0
*/
#define XBARA_CTRL0_EDGE0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE0_SHIFT)) & XBARA_CTRL0_EDGE0_MASK)
#define XBARA_CTRL0_STS0_MASK (0x10U)
#define XBARA_CTRL0_STS0_SHIFT (4U)
/*! STS0 - Edge detection status for XBAR_OUT0
* 0b0..Active edge not yet detected on XBAR_OUT0
* 0b1..Active edge detected on XBAR_OUT0
*/
#define XBARA_CTRL0_STS0(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS0_SHIFT)) & XBARA_CTRL0_STS0_MASK)
#define XBARA_CTRL0_DEN1_MASK (0x100U)
#define XBARA_CTRL0_DEN1_SHIFT (8U)
/*! DEN1 - DMA Enable for XBAR_OUT1
* 0b0..DMA disabled
* 0b1..DMA enabled
*/
#define XBARA_CTRL0_DEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_DEN1_SHIFT)) & XBARA_CTRL0_DEN1_MASK)
#define XBARA_CTRL0_IEN1_MASK (0x200U)
#define XBARA_CTRL0_IEN1_SHIFT (9U)
/*! IEN1 - Interrupt Enable for XBAR_OUT1
* 0b0..Interrupt disabled
* 0b1..Interrupt enabled
*/
#define XBARA_CTRL0_IEN1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_IEN1_SHIFT)) & XBARA_CTRL0_IEN1_MASK)
#define XBARA_CTRL0_EDGE1_MASK (0xC00U)
#define XBARA_CTRL0_EDGE1_SHIFT (10U)
/*! EDGE1 - Active edge for edge detection on XBAR_OUT1
* 0b00..STS1 never asserts
* 0b01..STS1 asserts on rising edges of XBAR_OUT1
* 0b10..STS1 asserts on falling edges of XBAR_OUT1
* 0b11..STS1 asserts on rising and falling edges of XBAR_OUT1
*/
#define XBARA_CTRL0_EDGE1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_EDGE1_SHIFT)) & XBARA_CTRL0_EDGE1_MASK)
#define XBARA_CTRL0_STS1_MASK (0x1000U)
#define XBARA_CTRL0_STS1_SHIFT (12U)
/*! STS1 - Edge detection status for XBAR_OUT1
* 0b0..Active edge not yet detected on XBAR_OUT1
* 0b1..Active edge detected on XBAR_OUT1
*/
#define XBARA_CTRL0_STS1(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL0_STS1_SHIFT)) & XBARA_CTRL0_STS1_MASK)
/*! @} */
/*! @name CTRL1 - Crossbar A Control Register 1 */
/*! @{ */
#define XBARA_CTRL1_DEN2_MASK (0x1U)
#define XBARA_CTRL1_DEN2_SHIFT (0U)
/*! DEN2 - DMA Enable for XBAR_OUT2
* 0b0..DMA disabled
* 0b1..DMA enabled
*/
#define XBARA_CTRL1_DEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN2_SHIFT)) & XBARA_CTRL1_DEN2_MASK)
#define XBARA_CTRL1_IEN2_MASK (0x2U)
#define XBARA_CTRL1_IEN2_SHIFT (1U)
/*! IEN2 - Interrupt Enable for XBAR_OUT2
* 0b0..Interrupt disabled
* 0b1..Interrupt enabled
*/
#define XBARA_CTRL1_IEN2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN2_SHIFT)) & XBARA_CTRL1_IEN2_MASK)
#define XBARA_CTRL1_EDGE2_MASK (0xCU)
#define XBARA_CTRL1_EDGE2_SHIFT (2U)
/*! EDGE2 - Active edge for edge detection on XBAR_OUT2
* 0b00..STS2 never asserts
* 0b01..STS2 asserts on rising edges of XBAR_OUT2
* 0b10..STS2 asserts on falling edges of XBAR_OUT2
* 0b11..STS2 asserts on rising and falling edges of XBAR_OUT2
*/
#define XBARA_CTRL1_EDGE2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE2_SHIFT)) & XBARA_CTRL1_EDGE2_MASK)
#define XBARA_CTRL1_STS2_MASK (0x10U)
#define XBARA_CTRL1_STS2_SHIFT (4U)
/*! STS2 - Edge detection status for XBAR_OUT2
* 0b0..Active edge not yet detected on XBAR_OUT2
* 0b1..Active edge detected on XBAR_OUT2
*/
#define XBARA_CTRL1_STS2(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS2_SHIFT)) & XBARA_CTRL1_STS2_MASK)
#define XBARA_CTRL1_DEN3_MASK (0x100U)
#define XBARA_CTRL1_DEN3_SHIFT (8U)
/*! DEN3 - DMA Enable for XBAR_OUT3
* 0b0..DMA disabled
* 0b1..DMA enabled
*/
#define XBARA_CTRL1_DEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_DEN3_SHIFT)) & XBARA_CTRL1_DEN3_MASK)
#define XBARA_CTRL1_IEN3_MASK (0x200U)
#define XBARA_CTRL1_IEN3_SHIFT (9U)
/*! IEN3 - Interrupt Enable for XBAR_OUT3
* 0b0..Interrupt disabled
* 0b1..Interrupt enabled
*/
#define XBARA_CTRL1_IEN3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_IEN3_SHIFT)) & XBARA_CTRL1_IEN3_MASK)
#define XBARA_CTRL1_EDGE3_MASK (0xC00U)
#define XBARA_CTRL1_EDGE3_SHIFT (10U)
/*! EDGE3 - Active edge for edge detection on XBAR_OUT3
* 0b00..STS3 never asserts
* 0b01..STS3 asserts on rising edges of XBAR_OUT3
* 0b10..STS3 asserts on falling edges of XBAR_OUT3
* 0b11..STS3 asserts on rising and falling edges of XBAR_OUT3
*/
#define XBARA_CTRL1_EDGE3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_EDGE3_SHIFT)) & XBARA_CTRL1_EDGE3_MASK)
#define XBARA_CTRL1_STS3_MASK (0x1000U)
#define XBARA_CTRL1_STS3_SHIFT (12U)
/*! STS3 - Edge detection status for XBAR_OUT3
* 0b0..Active edge not yet detected on XBAR_OUT3
* 0b1..Active edge detected on XBAR_OUT3
*/
#define XBARA_CTRL1_STS3(x) (((uint16_t)(((uint16_t)(x)) << XBARA_CTRL1_STS3_SHIFT)) & XBARA_CTRL1_STS3_MASK)
/*! @} */
/*!
* @}
*/ /* end of group XBARA_Register_Masks */
/* XBARA - Peripheral instance base addresses */
/** Peripheral XBARA1 base address */
#define XBARA1_BASE (0x4003C000u)
/** Peripheral XBARA1 base pointer */
#define XBARA1 ((XBARA_Type *)XBARA1_BASE)
/** Array initializer of XBARA peripheral base addresses */
#define XBARA_BASE_ADDRS { 0u, XBARA1_BASE }
/** Array initializer of XBARA peripheral base pointers */
#define XBARA_BASE_PTRS { (XBARA_Type *)0u, XBARA1 }
/*!
* @}
*/ /* end of group XBARA_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- XBARB Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup XBARB_Peripheral_Access_Layer XBARB Peripheral Access Layer
* @{
*/
/** XBARB - Register Layout Typedef */
typedef struct {
__IO uint16_t SEL0; /**< Crossbar B Select Register 0, offset: 0x0 */
__IO uint16_t SEL1; /**< Crossbar B Select Register 1, offset: 0x2 */
__IO uint16_t SEL2; /**< Crossbar B Select Register 2, offset: 0x4 */
__IO uint16_t SEL3; /**< Crossbar B Select Register 3, offset: 0x6 */
__IO uint16_t SEL4; /**< Crossbar B Select Register 4, offset: 0x8 */
__IO uint16_t SEL5; /**< Crossbar B Select Register 5, offset: 0xA */
__IO uint16_t SEL6; /**< Crossbar B Select Register 6, offset: 0xC */
__IO uint16_t SEL7; /**< Crossbar B Select Register 7, offset: 0xE */
} XBARB_Type;
/* ----------------------------------------------------------------------------
-- XBARB Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup XBARB_Register_Masks XBARB Register Masks
* @{
*/
/*! @name SEL0 - Crossbar B Select Register 0 */
/*! @{ */
#define XBARB_SEL0_SEL0_MASK (0x7FU)
#define XBARB_SEL0_SEL0_SHIFT (0U)
#define XBARB_SEL0_SEL0(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL0_SHIFT)) & XBARB_SEL0_SEL0_MASK)
#define XBARB_SEL0_SEL1_MASK (0x7F00U)
#define XBARB_SEL0_SEL1_SHIFT (8U)
#define XBARB_SEL0_SEL1(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL0_SEL1_SHIFT)) & XBARB_SEL0_SEL1_MASK)
/*! @} */
/*! @name SEL1 - Crossbar B Select Register 1 */
/*! @{ */
#define XBARB_SEL1_SEL2_MASK (0x7FU)
#define XBARB_SEL1_SEL2_SHIFT (0U)
#define XBARB_SEL1_SEL2(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL2_SHIFT)) & XBARB_SEL1_SEL2_MASK)
#define XBARB_SEL1_SEL3_MASK (0x7F00U)
#define XBARB_SEL1_SEL3_SHIFT (8U)
#define XBARB_SEL1_SEL3(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL1_SEL3_SHIFT)) & XBARB_SEL1_SEL3_MASK)
/*! @} */
/*! @name SEL2 - Crossbar B Select Register 2 */
/*! @{ */
#define XBARB_SEL2_SEL4_MASK (0x7FU)
#define XBARB_SEL2_SEL4_SHIFT (0U)
#define XBARB_SEL2_SEL4(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL4_SHIFT)) & XBARB_SEL2_SEL4_MASK)
#define XBARB_SEL2_SEL5_MASK (0x7F00U)
#define XBARB_SEL2_SEL5_SHIFT (8U)
#define XBARB_SEL2_SEL5(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL2_SEL5_SHIFT)) & XBARB_SEL2_SEL5_MASK)
/*! @} */
/*! @name SEL3 - Crossbar B Select Register 3 */
/*! @{ */
#define XBARB_SEL3_SEL6_MASK (0x7FU)
#define XBARB_SEL3_SEL6_SHIFT (0U)
#define XBARB_SEL3_SEL6(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL6_SHIFT)) & XBARB_SEL3_SEL6_MASK)
#define XBARB_SEL3_SEL7_MASK (0x7F00U)
#define XBARB_SEL3_SEL7_SHIFT (8U)
#define XBARB_SEL3_SEL7(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL3_SEL7_SHIFT)) & XBARB_SEL3_SEL7_MASK)
/*! @} */
/*! @name SEL4 - Crossbar B Select Register 4 */
/*! @{ */
#define XBARB_SEL4_SEL8_MASK (0x7FU)
#define XBARB_SEL4_SEL8_SHIFT (0U)
#define XBARB_SEL4_SEL8(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL8_SHIFT)) & XBARB_SEL4_SEL8_MASK)
#define XBARB_SEL4_SEL9_MASK (0x7F00U)
#define XBARB_SEL4_SEL9_SHIFT (8U)
#define XBARB_SEL4_SEL9(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL4_SEL9_SHIFT)) & XBARB_SEL4_SEL9_MASK)
/*! @} */
/*! @name SEL5 - Crossbar B Select Register 5 */
/*! @{ */
#define XBARB_SEL5_SEL10_MASK (0x7FU)
#define XBARB_SEL5_SEL10_SHIFT (0U)
#define XBARB_SEL5_SEL10(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL10_SHIFT)) & XBARB_SEL5_SEL10_MASK)
#define XBARB_SEL5_SEL11_MASK (0x7F00U)
#define XBARB_SEL5_SEL11_SHIFT (8U)
#define XBARB_SEL5_SEL11(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL5_SEL11_SHIFT)) & XBARB_SEL5_SEL11_MASK)
/*! @} */
/*! @name SEL6 - Crossbar B Select Register 6 */
/*! @{ */
#define XBARB_SEL6_SEL12_MASK (0x7FU)
#define XBARB_SEL6_SEL12_SHIFT (0U)
#define XBARB_SEL6_SEL12(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL12_SHIFT)) & XBARB_SEL6_SEL12_MASK)
#define XBARB_SEL6_SEL13_MASK (0x7F00U)
#define XBARB_SEL6_SEL13_SHIFT (8U)
#define XBARB_SEL6_SEL13(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL6_SEL13_SHIFT)) & XBARB_SEL6_SEL13_MASK)
/*! @} */
/*! @name SEL7 - Crossbar B Select Register 7 */
/*! @{ */
#define XBARB_SEL7_SEL14_MASK (0x7FU)
#define XBARB_SEL7_SEL14_SHIFT (0U)
#define XBARB_SEL7_SEL14(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL14_SHIFT)) & XBARB_SEL7_SEL14_MASK)
#define XBARB_SEL7_SEL15_MASK (0x7F00U)
#define XBARB_SEL7_SEL15_SHIFT (8U)
#define XBARB_SEL7_SEL15(x) (((uint16_t)(((uint16_t)(x)) << XBARB_SEL7_SEL15_SHIFT)) & XBARB_SEL7_SEL15_MASK)
/*! @} */
/*!
* @}
*/ /* end of group XBARB_Register_Masks */
/* XBARB - Peripheral instance base addresses */
/** Peripheral XBARB2 base address */
#define XBARB2_BASE (0x40040000u)
/** Peripheral XBARB2 base pointer */
#define XBARB2 ((XBARB_Type *)XBARB2_BASE)
/** Peripheral XBARB3 base address */
#define XBARB3_BASE (0x40044000u)
/** Peripheral XBARB3 base pointer */
#define XBARB3 ((XBARB_Type *)XBARB3_BASE)
/** Array initializer of XBARB peripheral base addresses */
#define XBARB_BASE_ADDRS { 0u, 0u, XBARB2_BASE, XBARB3_BASE }
/** Array initializer of XBARB peripheral base pointers */
#define XBARB_BASE_PTRS { (XBARB_Type *)0u, (XBARB_Type *)0u, XBARB2, XBARB3 }
/*!
* @}
*/ /* end of group XBARB_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- XECC Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup XECC_Peripheral_Access_Layer XECC Peripheral Access Layer
* @{
*/
/** XECC - Register Layout Typedef */
typedef struct {
__IO uint32_t ECC_CTRL; /**< ECC Control Register, offset: 0x0 */
__IO uint32_t ERR_STATUS; /**< Error Interrupt Status Register, offset: 0x4 */
__IO uint32_t ERR_STAT_EN; /**< Error Interrupt Status Enable Register, offset: 0x8 */
__IO uint32_t ERR_SIG_EN; /**< Error Interrupt Enable Register, offset: 0xC */
__IO uint32_t ERR_DATA_INJ; /**< Error Injection On Write Data, offset: 0x10 */
__IO uint32_t ERR_ECC_INJ; /**< Error Injection On ECC Code of Write Data, offset: 0x14 */
__I uint32_t SINGLE_ERR_ADDR; /**< Single Error Address, offset: 0x18 */
__I uint32_t SINGLE_ERR_DATA; /**< Single Error Read Data, offset: 0x1C */
__I uint32_t SINGLE_ERR_ECC; /**< Single Error ECC Code, offset: 0x20 */
__I uint32_t SINGLE_ERR_POS; /**< Single Error Bit Position, offset: 0x24 */
__I uint32_t SINGLE_ERR_BIT_FIELD; /**< Single Error Bit Field, offset: 0x28 */
__I uint32_t MULTI_ERR_ADDR; /**< Multiple Error Address, offset: 0x2C */
__I uint32_t MULTI_ERR_DATA; /**< Multiple Error Read Data, offset: 0x30 */
__I uint32_t MULTI_ERR_ECC; /**< Multiple Error ECC code, offset: 0x34 */
__I uint32_t MULTI_ERR_BIT_FIELD; /**< Multiple Error Bit Field, offset: 0x38 */
__IO uint32_t ECC_BASE_ADDR0; /**< ECC Region 0 Base Address, offset: 0x3C */
__IO uint32_t ECC_END_ADDR0; /**< ECC Region 0 End Address, offset: 0x40 */
__IO uint32_t ECC_BASE_ADDR1; /**< ECC Region 1 Base Address, offset: 0x44 */
__IO uint32_t ECC_END_ADDR1; /**< ECC Region 1 End Address, offset: 0x48 */
__IO uint32_t ECC_BASE_ADDR2; /**< ECC Region 2 Base Address, offset: 0x4C */
__IO uint32_t ECC_END_ADDR2; /**< ECC Region 2 End Address, offset: 0x50 */
__IO uint32_t ECC_BASE_ADDR3; /**< ECC Region 3 Base Address, offset: 0x54 */
__IO uint32_t ECC_END_ADDR3; /**< ECC Region 3 End Address, offset: 0x58 */
} XECC_Type;
/* ----------------------------------------------------------------------------
-- XECC Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup XECC_Register_Masks XECC Register Masks
* @{
*/
/*! @name ECC_CTRL - ECC Control Register */
/*! @{ */
#define XECC_ECC_CTRL_ECC_EN_MASK (0x1U)
#define XECC_ECC_CTRL_ECC_EN_SHIFT (0U)
/*! ECC_EN - ECC Function Enable
* 0b0..Disable
* 0b1..Enable
*/
#define XECC_ECC_CTRL_ECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_ECC_EN_SHIFT)) & XECC_ECC_CTRL_ECC_EN_MASK)
#define XECC_ECC_CTRL_WECC_EN_MASK (0x2U)
#define XECC_ECC_CTRL_WECC_EN_SHIFT (1U)
/*! WECC_EN - Write ECC Encode Function Enable
* 0b0..Disable
* 0b1..Enable
*/
#define XECC_ECC_CTRL_WECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_WECC_EN_SHIFT)) & XECC_ECC_CTRL_WECC_EN_MASK)
#define XECC_ECC_CTRL_RECC_EN_MASK (0x4U)
#define XECC_ECC_CTRL_RECC_EN_SHIFT (2U)
/*! RECC_EN - Read ECC Function Enable
* 0b0..Disable
* 0b1..Enable
*/
#define XECC_ECC_CTRL_RECC_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_RECC_EN_SHIFT)) & XECC_ECC_CTRL_RECC_EN_MASK)
#define XECC_ECC_CTRL_SWAP_EN_MASK (0x8U)
#define XECC_ECC_CTRL_SWAP_EN_SHIFT (3U)
/*! SWAP_EN - Swap Data Enable
* 0b0..Disable
* 0b1..Enable
*/
#define XECC_ECC_CTRL_SWAP_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_CTRL_SWAP_EN_SHIFT)) & XECC_ECC_CTRL_SWAP_EN_MASK)
/*! @} */
/*! @name ERR_STATUS - Error Interrupt Status Register */
/*! @{ */
#define XECC_ERR_STATUS_SINGLE_ERR_MASK (0x1U)
#define XECC_ERR_STATUS_SINGLE_ERR_SHIFT (0U)
/*! SINGLE_ERR - Single Bit Error
* 0b0..Single bit error does not happen.
* 0b1..Single bit error happens.
*/
#define XECC_ERR_STATUS_SINGLE_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_SINGLE_ERR_SHIFT)) & XECC_ERR_STATUS_SINGLE_ERR_MASK)
#define XECC_ERR_STATUS_MULTI_ERR_MASK (0x2U)
#define XECC_ERR_STATUS_MULTI_ERR_SHIFT (1U)
/*! MULTI_ERR - Multiple Bits Error
* 0b0..Multiple bits error does not happen.
* 0b1..Multiple bits error happens.
*/
#define XECC_ERR_STATUS_MULTI_ERR(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_MULTI_ERR_SHIFT)) & XECC_ERR_STATUS_MULTI_ERR_MASK)
#define XECC_ERR_STATUS_Reserved1_MASK (0xFFFFFFFCU)
#define XECC_ERR_STATUS_Reserved1_SHIFT (2U)
/*! Reserved1 - Reserved
*/
#define XECC_ERR_STATUS_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STATUS_Reserved1_SHIFT)) & XECC_ERR_STATUS_Reserved1_MASK)
/*! @} */
/*! @name ERR_STAT_EN - Error Interrupt Status Enable Register */
/*! @{ */
#define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK (0x1U)
#define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT (0U)
/*! SINGLE_ERR_STAT_EN - Single Bit Error Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_SINGLE_ERR_STAT_EN_MASK)
#define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK (0x2U)
#define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT (1U)
/*! MULIT_ERR_STAT_EN - Multiple Bits Error Status Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_SHIFT)) & XECC_ERR_STAT_EN_MULIT_ERR_STAT_EN_MASK)
#define XECC_ERR_STAT_EN_Reserved1_MASK (0xFFFFFFFCU)
#define XECC_ERR_STAT_EN_Reserved1_SHIFT (2U)
/*! Reserved1 - Reserved
*/
#define XECC_ERR_STAT_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_STAT_EN_Reserved1_SHIFT)) & XECC_ERR_STAT_EN_Reserved1_MASK)
/*! @} */
/*! @name ERR_SIG_EN - Error Interrupt Enable Register */
/*! @{ */
#define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK (0x1U)
#define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT (0U)
/*! SINGLE_ERR_SIG_EN - Single Bit Error Interrupt Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_SINGLE_ERR_SIG_EN_MASK)
#define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK (0x2U)
#define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT (1U)
/*! MULTI_ERR_SIG_EN - Multiple Bits Error Interrupt Enable
* 0b0..Masked
* 0b1..Enabled
*/
#define XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_SHIFT)) & XECC_ERR_SIG_EN_MULTI_ERR_SIG_EN_MASK)
#define XECC_ERR_SIG_EN_Reserved1_MASK (0xFFFFFFFCU)
#define XECC_ERR_SIG_EN_Reserved1_SHIFT (2U)
/*! Reserved1 - Reserved
*/
#define XECC_ERR_SIG_EN_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_SIG_EN_Reserved1_SHIFT)) & XECC_ERR_SIG_EN_Reserved1_MASK)
/*! @} */
/*! @name ERR_DATA_INJ - Error Injection On Write Data */
/*! @{ */
#define XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK (0xFFFFFFFFU)
#define XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT (0U)
/*! ERR_DATA_INJ - Error Injection On Write Data
*/
#define XECC_ERR_DATA_INJ_ERR_DATA_INJ(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_DATA_INJ_ERR_DATA_INJ_SHIFT)) & XECC_ERR_DATA_INJ_ERR_DATA_INJ_MASK)
/*! @} */
/*! @name ERR_ECC_INJ - Error Injection On ECC Code of Write Data */
/*! @{ */
#define XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK (0xFFFFFFFFU)
#define XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT (0U)
/*! ERR_ECC_INJ - Error Injection On ECC Code of Write Data
*/
#define XECC_ERR_ECC_INJ_ERR_ECC_INJ(x) (((uint32_t)(((uint32_t)(x)) << XECC_ERR_ECC_INJ_ERR_ECC_INJ_SHIFT)) & XECC_ERR_ECC_INJ_ERR_ECC_INJ_MASK)
/*! @} */
/*! @name SINGLE_ERR_ADDR - Single Error Address */
/*! @{ */
#define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK (0xFFFFFFFFU)
#define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT (0U)
/*! SINGLE_ERR_ADDR - Single Error Address
*/
#define XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_SHIFT)) & XECC_SINGLE_ERR_ADDR_SINGLE_ERR_ADDR_MASK)
/*! @} */
/*! @name SINGLE_ERR_DATA - Single Error Read Data */
/*! @{ */
#define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK (0xFFFFFFFFU)
#define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT (0U)
/*! SINGLE_ERR_DATA - Single Error Read Data
*/
#define XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_SHIFT)) & XECC_SINGLE_ERR_DATA_SINGLE_ERR_DATA_MASK)
/*! @} */
/*! @name SINGLE_ERR_ECC - Single Error ECC Code */
/*! @{ */
#define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK (0xFFFFFFFFU)
#define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT (0U)
/*! SINGLE_ERR_ECC - Single Error ECC code
*/
#define XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_SHIFT)) & XECC_SINGLE_ERR_ECC_SINGLE_ERR_ECC_MASK)
/*! @} */
/*! @name SINGLE_ERR_POS - Single Error Bit Position */
/*! @{ */
#define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK (0xFFFFFFFFU)
#define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT (0U)
/*! SINGLE_ERR_POS - Single Error bit Position
*/
#define XECC_SINGLE_ERR_POS_SINGLE_ERR_POS(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_SHIFT)) & XECC_SINGLE_ERR_POS_SINGLE_ERR_POS_MASK)
/*! @} */
/*! @name SINGLE_ERR_BIT_FIELD - Single Error Bit Field */
/*! @{ */
#define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK (0xFFU)
#define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT (0U)
/*! SINGLE_ERR_BIT_FIELD - Single Error Bit Field
*/
#define XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_SINGLE_ERR_BIT_FIELD_MASK)
#define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U)
#define XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT (8U)
/*! Reserved1 - Reserved
*/
#define XECC_SINGLE_ERR_BIT_FIELD_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_SINGLE_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_SINGLE_ERR_BIT_FIELD_Reserved1_MASK)
/*! @} */
/*! @name MULTI_ERR_ADDR - Multiple Error Address */
/*! @{ */
#define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK (0xFFFFFFFFU)
#define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT (0U)
/*! MULTI_ERR_ADDR - Multiple Error Address
*/
#define XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_SHIFT)) & XECC_MULTI_ERR_ADDR_MULTI_ERR_ADDR_MASK)
/*! @} */
/*! @name MULTI_ERR_DATA - Multiple Error Read Data */
/*! @{ */
#define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK (0xFFFFFFFFU)
#define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT (0U)
/*! MULTI_ERR_DATA - Multiple Error Read Data
*/
#define XECC_MULTI_ERR_DATA_MULTI_ERR_DATA(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_SHIFT)) & XECC_MULTI_ERR_DATA_MULTI_ERR_DATA_MASK)
/*! @} */
/*! @name MULTI_ERR_ECC - Multiple Error ECC code */
/*! @{ */
#define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK (0xFFFFFFFFU)
#define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT (0U)
/*! MULTI_ERR_ECC - Multiple Error ECC code
*/
#define XECC_MULTI_ERR_ECC_MULTI_ERR_ECC(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_SHIFT)) & XECC_MULTI_ERR_ECC_MULTI_ERR_ECC_MASK)
/*! @} */
/*! @name MULTI_ERR_BIT_FIELD - Multiple Error Bit Field */
/*! @{ */
#define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK (0xFFU)
#define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT (0U)
/*! MULTI_ERR_BIT_FIELD - Multiple Error Bit Field
*/
#define XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_MULTI_ERR_BIT_FIELD_MASK)
#define XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK (0xFFFFFF00U)
#define XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT (8U)
/*! Reserved1 - Reserved
*/
#define XECC_MULTI_ERR_BIT_FIELD_Reserved1(x) (((uint32_t)(((uint32_t)(x)) << XECC_MULTI_ERR_BIT_FIELD_Reserved1_SHIFT)) & XECC_MULTI_ERR_BIT_FIELD_Reserved1_MASK)
/*! @} */
/*! @name ECC_BASE_ADDR0 - ECC Region 0 Base Address */
/*! @{ */
#define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK (0xFFFFFFFFU)
#define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT (0U)
/*! ECC_BASE_ADDR0 - ECC Region 0 Base Address
*/
#define XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_SHIFT)) & XECC_ECC_BASE_ADDR0_ECC_BASE_ADDR0_MASK)
/*! @} */
/*! @name ECC_END_ADDR0 - ECC Region 0 End Address */
/*! @{ */
#define XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK (0xFFFFFFFFU)
#define XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT (0U)
/*! ECC_END_ADDR0 - ECC Region 0 End Address
*/
#define XECC_ECC_END_ADDR0_ECC_END_ADDR0(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR0_ECC_END_ADDR0_SHIFT)) & XECC_ECC_END_ADDR0_ECC_END_ADDR0_MASK)
/*! @} */
/*! @name ECC_BASE_ADDR1 - ECC Region 1 Base Address */
/*! @{ */
#define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK (0xFFFFFFFFU)
#define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT (0U)
/*! ECC_BASE_ADDR1 - ECC Region 1 Base Address
*/
#define XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_SHIFT)) & XECC_ECC_BASE_ADDR1_ECC_BASE_ADDR1_MASK)
/*! @} */
/*! @name ECC_END_ADDR1 - ECC Region 1 End Address */
/*! @{ */
#define XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK (0xFFFFFFFFU)
#define XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT (0U)
/*! ECC_END_ADDR1 - ECC Region 1 End Address
*/
#define XECC_ECC_END_ADDR1_ECC_END_ADDR1(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR1_ECC_END_ADDR1_SHIFT)) & XECC_ECC_END_ADDR1_ECC_END_ADDR1_MASK)
/*! @} */
/*! @name ECC_BASE_ADDR2 - ECC Region 2 Base Address */
/*! @{ */
#define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK (0xFFFFFFFFU)
#define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT (0U)
/*! ECC_BASE_ADDR2 - ECC Region 2 Base Address
*/
#define XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_SHIFT)) & XECC_ECC_BASE_ADDR2_ECC_BASE_ADDR2_MASK)
/*! @} */
/*! @name ECC_END_ADDR2 - ECC Region 2 End Address */
/*! @{ */
#define XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK (0xFFFFFFFFU)
#define XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT (0U)
/*! ECC_END_ADDR2 - ECC Region 2 End Address
*/
#define XECC_ECC_END_ADDR2_ECC_END_ADDR2(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR2_ECC_END_ADDR2_SHIFT)) & XECC_ECC_END_ADDR2_ECC_END_ADDR2_MASK)
/*! @} */
/*! @name ECC_BASE_ADDR3 - ECC Region 3 Base Address */
/*! @{ */
#define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK (0xFFFFFFFFU)
#define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT (0U)
/*! ECC_BASE_ADDR3 - ECC Region 3 Base Address
*/
#define XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_SHIFT)) & XECC_ECC_BASE_ADDR3_ECC_BASE_ADDR3_MASK)
/*! @} */
/*! @name ECC_END_ADDR3 - ECC Region 3 End Address */
/*! @{ */
#define XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK (0xFFFFFFFFU)
#define XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT (0U)
/*! ECC_END_ADDR3 - ECC Region 3 End Address
*/
#define XECC_ECC_END_ADDR3_ECC_END_ADDR3(x) (((uint32_t)(((uint32_t)(x)) << XECC_ECC_END_ADDR3_ECC_END_ADDR3_SHIFT)) & XECC_ECC_END_ADDR3_ECC_END_ADDR3_MASK)
/*! @} */
/*!
* @}
*/ /* end of group XECC_Register_Masks */
/* XECC - Peripheral instance base addresses */
/** Peripheral XECC_FLEXSPI1 base address */
#define XECC_FLEXSPI1_BASE (0x4001C000u)
/** Peripheral XECC_FLEXSPI1 base pointer */
#define XECC_FLEXSPI1 ((XECC_Type *)XECC_FLEXSPI1_BASE)
/** Peripheral XECC_FLEXSPI2 base address */
#define XECC_FLEXSPI2_BASE (0x40020000u)
/** Peripheral XECC_FLEXSPI2 base pointer */
#define XECC_FLEXSPI2 ((XECC_Type *)XECC_FLEXSPI2_BASE)
/** Peripheral XECC_SEMC base address */
#define XECC_SEMC_BASE (0x40024000u)
/** Peripheral XECC_SEMC base pointer */
#define XECC_SEMC ((XECC_Type *)XECC_SEMC_BASE)
/** Array initializer of XECC peripheral base addresses */
#define XECC_BASE_ADDRS { 0u, XECC_FLEXSPI1_BASE, XECC_FLEXSPI2_BASE, XECC_SEMC_BASE }
/** Array initializer of XECC peripheral base pointers */
#define XECC_BASE_PTRS { (XECC_Type *)0u, XECC_FLEXSPI1, XECC_FLEXSPI2, XECC_SEMC }
/*!
* @}
*/ /* end of group XECC_Peripheral_Access_Layer */
/* ----------------------------------------------------------------------------
-- XRDC2 Peripheral Access Layer
---------------------------------------------------------------------------- */
/*!
* @addtogroup XRDC2_Peripheral_Access_Layer XRDC2 Peripheral Access Layer
* @{
*/
/** XRDC2 - Register Layout Typedef */
typedef struct {
__IO uint32_t MCR; /**< Module Control Register, offset: 0x0 */
__I uint32_t SR; /**< Status Register, offset: 0x4 */
uint8_t RESERVED_0[4088];
struct { /* offset: 0x1000, array step: 0x8 */
__IO uint32_t MSC_MSAC_W0; /**< Memory Slot Access Control, array offset: 0x1000, array step: 0x8 */
__IO uint32_t MSC_MSAC_W1; /**< Memory Slot Access Control, array offset: 0x1004, array step: 0x8 */
} MSCI_MSAC_WK[128];
uint8_t RESERVED_1[3072];
struct { /* offset: 0x2000, array step: index*0x100, index2*0x8 */
__IO uint32_t MDAC_MDA_W0; /**< Master Domain Assignment, array offset: 0x2000, array step: index*0x100, index2*0x8 */
__IO uint32_t MDAC_MDA_W1; /**< Master Domain Assignment, array offset: 0x2004, array step: index*0x100, index2*0x8 */
} MDACI_MDAJ[32][32];
struct { /* offset: 0x4000, array step: index*0x800, index2*0x8 */
__IO uint32_t PAC_PDAC_W0; /**< Peripheral Domain Access Control, array offset: 0x4000, array step: index*0x800, index2*0x8 */
__IO uint32_t PAC_PDAC_W1; /**< Peripheral Domain Access Control, array offset: 0x4004, array step: index*0x800, index2*0x8 */
} PACI_PDACJ[8][256];
struct { /* offset: 0x8000, array step: index*0x400, index2*0x20 */
__IO uint32_t MRC_MRGD_W0; /**< Memory Region Descriptor, array offset: 0x8000, array step: index*0x400, index2*0x20 */
__IO uint32_t MRC_MRGD_W1; /**< Memory Region Descriptor, array offset: 0x8004, array step: index*0x400, index2*0x20 */
__IO uint32_t MRC_MRGD_W2; /**< Memory Region Descriptor, array offset: 0x8008, array step: index*0x400, index2*0x20 */
__IO uint32_t MRC_MRGD_W3; /**< Memory Region Descriptor, array offset: 0x800C, array step: index*0x400, index2*0x20 */
uint8_t RESERVED_0[4];
__IO uint32_t MRC_MRGD_W5; /**< Memory Region Descriptor, array offset: 0x8014, array step: index*0x400, index2*0x20 */
__IO uint32_t MRC_MRGD_W6; /**< Memory Region Descriptor, array offset: 0x8018, array step: index*0x400, index2*0x20 */
uint8_t RESERVED_1[4];
} MRCI_MRGDJ[32][32];
} XRDC2_Type;
/* ----------------------------------------------------------------------------
-- XRDC2 Register Masks
---------------------------------------------------------------------------- */
/*!
* @addtogroup XRDC2_Register_Masks XRDC2 Register Masks
* @{
*/
/*! @name MCR - Module Control Register */
/*! @{ */
#define XRDC2_MCR_GVLDM_MASK (0x1U)
#define XRDC2_MCR_GVLDM_SHIFT (0U)
/*! GVLDM - Global Valid MDAC
* 0b0..MDACs are disabled.
* 0b1..MDACs are enabled.
*/
#define XRDC2_MCR_GVLDM(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDM_SHIFT)) & XRDC2_MCR_GVLDM_MASK)
#define XRDC2_MCR_GVLDC_MASK (0x2U)
#define XRDC2_MCR_GVLDC_SHIFT (1U)
/*! GVLDC - Global Valid Access Control
* 0b0..Access controls are disabled, XRDC2 allows all transactions.
* 0b1..Access controls are enabled.
*/
#define XRDC2_MCR_GVLDC(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GVLDC_SHIFT)) & XRDC2_MCR_GVLDC_MASK)
#define XRDC2_MCR_GCL_MASK (0x30U)
#define XRDC2_MCR_GCL_SHIFT (4U)
/*! GCL - Global Configuration Lock
* 0b00..Lock disabled, registers can be written by any domain.
* 0b01..Lock disabled until the next reset, registers can be written by any domain.
* 0b10..Lock enabled, only the global configuration lock owner (SR[GCLO]) can write to registers.
* 0b11..Lock enabled, all registers are read only until the next reset.
*/
#define XRDC2_MCR_GCL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MCR_GCL_SHIFT)) & XRDC2_MCR_GCL_MASK)
/*! @} */
/*! @name SR - Status Register */
/*! @{ */
#define XRDC2_SR_DIN_MASK (0xFU)
#define XRDC2_SR_DIN_SHIFT (0U)
/*! DIN - Domain Identifier Number
*/
#define XRDC2_SR_DIN(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_DIN_SHIFT)) & XRDC2_SR_DIN_MASK)
#define XRDC2_SR_HRL_MASK (0xF0U)
#define XRDC2_SR_HRL_SHIFT (4U)
/*! HRL - Hardware Revision Level
*/
#define XRDC2_SR_HRL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_HRL_SHIFT)) & XRDC2_SR_HRL_MASK)
#define XRDC2_SR_GCLO_MASK (0xF00U)
#define XRDC2_SR_GCLO_SHIFT (8U)
/*! GCLO - Global Configuration Lock Owner
*/
#define XRDC2_SR_GCLO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_SR_GCLO_SHIFT)) & XRDC2_SR_GCLO_MASK)
/*! @} */
/*! @name MSC_MSAC_W0 - Memory Slot Access Control */
/*! @{ */
#define XRDC2_MSC_MSAC_W0_D0ACP_MASK (0x7U)
#define XRDC2_MSC_MSAC_W0_D0ACP_SHIFT (0U)
/*! D0ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D0ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D0ACP_MASK)
#define XRDC2_MSC_MSAC_W0_D1ACP_MASK (0x38U)
#define XRDC2_MSC_MSAC_W0_D1ACP_SHIFT (3U)
/*! D1ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D1ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D1ACP_MASK)
#define XRDC2_MSC_MSAC_W0_D2ACP_MASK (0x1C0U)
#define XRDC2_MSC_MSAC_W0_D2ACP_SHIFT (6U)
/*! D2ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D2ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D2ACP_MASK)
#define XRDC2_MSC_MSAC_W0_D3ACP_MASK (0xE00U)
#define XRDC2_MSC_MSAC_W0_D3ACP_SHIFT (9U)
/*! D3ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D3ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D3ACP_MASK)
#define XRDC2_MSC_MSAC_W0_D4ACP_MASK (0x7000U)
#define XRDC2_MSC_MSAC_W0_D4ACP_SHIFT (12U)
/*! D4ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D4ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D4ACP_MASK)
#define XRDC2_MSC_MSAC_W0_D5ACP_MASK (0x38000U)
#define XRDC2_MSC_MSAC_W0_D5ACP_SHIFT (15U)
/*! D5ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D5ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D5ACP_MASK)
#define XRDC2_MSC_MSAC_W0_D6ACP_MASK (0x1C0000U)
#define XRDC2_MSC_MSAC_W0_D6ACP_SHIFT (18U)
/*! D6ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D6ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D6ACP_MASK)
#define XRDC2_MSC_MSAC_W0_D7ACP_MASK (0xE00000U)
#define XRDC2_MSC_MSAC_W0_D7ACP_SHIFT (21U)
/*! D7ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_D7ACP_SHIFT)) & XRDC2_MSC_MSAC_W0_D7ACP_MASK)
#define XRDC2_MSC_MSAC_W0_EALO_MASK (0xF000000U)
#define XRDC2_MSC_MSAC_W0_EALO_SHIFT (24U)
/*! EALO - Exclusive Access Lock Owner
*/
#define XRDC2_MSC_MSAC_W0_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W0_EALO_SHIFT)) & XRDC2_MSC_MSAC_W0_EALO_MASK)
/*! @} */
/* The count of XRDC2_MSC_MSAC_W0 */
#define XRDC2_MSC_MSAC_W0_COUNT (128U)
/*! @name MSC_MSAC_W1 - Memory Slot Access Control */
/*! @{ */
#define XRDC2_MSC_MSAC_W1_D8ACP_MASK (0x7U)
#define XRDC2_MSC_MSAC_W1_D8ACP_SHIFT (0U)
/*! D8ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D8ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D8ACP_MASK)
#define XRDC2_MSC_MSAC_W1_D9ACP_MASK (0x38U)
#define XRDC2_MSC_MSAC_W1_D9ACP_SHIFT (3U)
/*! D9ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D9ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D9ACP_MASK)
#define XRDC2_MSC_MSAC_W1_D10ACP_MASK (0x1C0U)
#define XRDC2_MSC_MSAC_W1_D10ACP_SHIFT (6U)
/*! D10ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D10ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D10ACP_MASK)
#define XRDC2_MSC_MSAC_W1_D11ACP_MASK (0xE00U)
#define XRDC2_MSC_MSAC_W1_D11ACP_SHIFT (9U)
/*! D11ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D11ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D11ACP_MASK)
#define XRDC2_MSC_MSAC_W1_D12ACP_MASK (0x7000U)
#define XRDC2_MSC_MSAC_W1_D12ACP_SHIFT (12U)
/*! D12ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D12ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D12ACP_MASK)
#define XRDC2_MSC_MSAC_W1_D13ACP_MASK (0x38000U)
#define XRDC2_MSC_MSAC_W1_D13ACP_SHIFT (15U)
/*! D13ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D13ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D13ACP_MASK)
#define XRDC2_MSC_MSAC_W1_D14ACP_MASK (0x1C0000U)
#define XRDC2_MSC_MSAC_W1_D14ACP_SHIFT (18U)
/*! D14ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D14ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D14ACP_MASK)
#define XRDC2_MSC_MSAC_W1_D15ACP_MASK (0xE00000U)
#define XRDC2_MSC_MSAC_W1_D15ACP_SHIFT (21U)
/*! D15ACP - Domain "x" access control policy
*/
#define XRDC2_MSC_MSAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_D15ACP_SHIFT)) & XRDC2_MSC_MSAC_W1_D15ACP_MASK)
#define XRDC2_MSC_MSAC_W1_EAL_MASK (0x3000000U)
#define XRDC2_MSC_MSAC_W1_EAL_SHIFT (24U)
/*! EAL - Exclusive Access Lock
* 0b00..Lock disabled.
* 0b01..Lock disabled until next reset.
* 0b10..Lock enabled, lock state = available.
* 0b11..Lock enabled, lock state = not available.
*/
#define XRDC2_MSC_MSAC_W1_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_EAL_SHIFT)) & XRDC2_MSC_MSAC_W1_EAL_MASK)
#define XRDC2_MSC_MSAC_W1_DL2_MASK (0x60000000U)
#define XRDC2_MSC_MSAC_W1_DL2_SHIFT (29U)
/*! DL2 - Descriptor Lock
* 0b00..Lock disabled, descriptor registers can be written.
* 0b01..Lock disabled until the next reset, descriptor registers can be written.
* 0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.
* 0b11..Lock enabled, descriptor registers are read-only until the next reset.
*/
#define XRDC2_MSC_MSAC_W1_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_DL2_SHIFT)) & XRDC2_MSC_MSAC_W1_DL2_MASK)
#define XRDC2_MSC_MSAC_W1_VLD_MASK (0x80000000U)
#define XRDC2_MSC_MSAC_W1_VLD_SHIFT (31U)
/*! VLD - Valid
* 0b0..The MSAC assignment is invalid.
* 0b1..The MSAC assignment is valid.
*/
#define XRDC2_MSC_MSAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MSC_MSAC_W1_VLD_SHIFT)) & XRDC2_MSC_MSAC_W1_VLD_MASK)
/*! @} */
/* The count of XRDC2_MSC_MSAC_W1 */
#define XRDC2_MSC_MSAC_W1_COUNT (128U)
/*! @name MDAC_MDA_W0 - Master Domain Assignment */
/*! @{ */
#define XRDC2_MDAC_MDA_W0_MASK_MASK (0xFFFFU)
#define XRDC2_MDAC_MDA_W0_MASK_SHIFT (0U)
/*! MASK - Mask
*/
#define XRDC2_MDAC_MDA_W0_MASK(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MASK_SHIFT)) & XRDC2_MDAC_MDA_W0_MASK_MASK)
#define XRDC2_MDAC_MDA_W0_MATCH_MASK (0xFFFF0000U)
#define XRDC2_MDAC_MDA_W0_MATCH_SHIFT (16U)
/*! MATCH - Match
*/
#define XRDC2_MDAC_MDA_W0_MATCH(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W0_MATCH_SHIFT)) & XRDC2_MDAC_MDA_W0_MATCH_MASK)
/*! @} */
/* The count of XRDC2_MDAC_MDA_W0 */
#define XRDC2_MDAC_MDA_W0_COUNT (32U)
/* The count of XRDC2_MDAC_MDA_W0 */
#define XRDC2_MDAC_MDA_W0_COUNT2 (32U)
/*! @name MDAC_MDA_W1 - Master Domain Assignment */
/*! @{ */
#define XRDC2_MDAC_MDA_W1_DID_MASK (0xF0000U)
#define XRDC2_MDAC_MDA_W1_DID_SHIFT (16U)
/*! DID - Domain Identifier
*/
#define XRDC2_MDAC_MDA_W1_DID(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DID_SHIFT)) & XRDC2_MDAC_MDA_W1_DID_MASK)
#define XRDC2_MDAC_MDA_W1_PA_MASK (0x3000000U)
#define XRDC2_MDAC_MDA_W1_PA_SHIFT (24U)
/*! PA - Privileged attribute
* 0b00..Use the bus master's privileged/user attribute directly.
* 0b01..Use the bus master's privileged/user attribute directly.
* 0b10..Force the bus attribute for this master to user.
* 0b11..Force the bus attribute for this master to privileged.
*/
#define XRDC2_MDAC_MDA_W1_PA(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_PA_SHIFT)) & XRDC2_MDAC_MDA_W1_PA_MASK)
#define XRDC2_MDAC_MDA_W1_SA_MASK (0xC000000U)
#define XRDC2_MDAC_MDA_W1_SA_SHIFT (26U)
/*! SA - Secure attribute
* 0b00..Use the bus master's secure/nonsecure attribute directly.
* 0b01..Use the bus master's secure/nonsecure attribute directly.
* 0b10..Force the bus attribute for this master to secure.
* 0b11..Force the bus attribute for this master to nonsecure.
*/
#define XRDC2_MDAC_MDA_W1_SA(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_SA_SHIFT)) & XRDC2_MDAC_MDA_W1_SA_MASK)
#define XRDC2_MDAC_MDA_W1_DL_MASK (0x40000000U)
#define XRDC2_MDAC_MDA_W1_DL_SHIFT (30U)
/*! DL - Descriptor Lock
* 0b0..Lock disabled, registers can be written.
* 0b1..Lock enabled, registers are read-only until the next reset.
*/
#define XRDC2_MDAC_MDA_W1_DL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_DL_SHIFT)) & XRDC2_MDAC_MDA_W1_DL_MASK)
#define XRDC2_MDAC_MDA_W1_VLD_MASK (0x80000000U)
#define XRDC2_MDAC_MDA_W1_VLD_SHIFT (31U)
/*! VLD - Valid
* 0b0..The MDA is invalid.
* 0b1..The MDA is valid.
*/
#define XRDC2_MDAC_MDA_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MDAC_MDA_W1_VLD_SHIFT)) & XRDC2_MDAC_MDA_W1_VLD_MASK)
/*! @} */
/* The count of XRDC2_MDAC_MDA_W1 */
#define XRDC2_MDAC_MDA_W1_COUNT (32U)
/* The count of XRDC2_MDAC_MDA_W1 */
#define XRDC2_MDAC_MDA_W1_COUNT2 (32U)
/*! @name PAC_PDAC_W0 - Peripheral Domain Access Control */
/*! @{ */
#define XRDC2_PAC_PDAC_W0_D0ACP_MASK (0x7U)
#define XRDC2_PAC_PDAC_W0_D0ACP_SHIFT (0U)
/*! D0ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W0_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D0ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D0ACP_MASK)
#define XRDC2_PAC_PDAC_W0_D1ACP_MASK (0x38U)
#define XRDC2_PAC_PDAC_W0_D1ACP_SHIFT (3U)
/*! D1ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W0_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D1ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D1ACP_MASK)
#define XRDC2_PAC_PDAC_W0_D2ACP_MASK (0x1C0U)
#define XRDC2_PAC_PDAC_W0_D2ACP_SHIFT (6U)
/*! D2ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W0_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D2ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D2ACP_MASK)
#define XRDC2_PAC_PDAC_W0_D3ACP_MASK (0xE00U)
#define XRDC2_PAC_PDAC_W0_D3ACP_SHIFT (9U)
/*! D3ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W0_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D3ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D3ACP_MASK)
#define XRDC2_PAC_PDAC_W0_D4ACP_MASK (0x7000U)
#define XRDC2_PAC_PDAC_W0_D4ACP_SHIFT (12U)
/*! D4ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W0_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D4ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D4ACP_MASK)
#define XRDC2_PAC_PDAC_W0_D5ACP_MASK (0x38000U)
#define XRDC2_PAC_PDAC_W0_D5ACP_SHIFT (15U)
/*! D5ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W0_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D5ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D5ACP_MASK)
#define XRDC2_PAC_PDAC_W0_D6ACP_MASK (0x1C0000U)
#define XRDC2_PAC_PDAC_W0_D6ACP_SHIFT (18U)
/*! D6ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W0_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D6ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D6ACP_MASK)
#define XRDC2_PAC_PDAC_W0_D7ACP_MASK (0xE00000U)
#define XRDC2_PAC_PDAC_W0_D7ACP_SHIFT (21U)
/*! D7ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W0_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_D7ACP_SHIFT)) & XRDC2_PAC_PDAC_W0_D7ACP_MASK)
#define XRDC2_PAC_PDAC_W0_EALO_MASK (0xF000000U)
#define XRDC2_PAC_PDAC_W0_EALO_SHIFT (24U)
/*! EALO - Exclusive Access Lock Owner
*/
#define XRDC2_PAC_PDAC_W0_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W0_EALO_SHIFT)) & XRDC2_PAC_PDAC_W0_EALO_MASK)
/*! @} */
/* The count of XRDC2_PAC_PDAC_W0 */
#define XRDC2_PAC_PDAC_W0_COUNT (8U)
/* The count of XRDC2_PAC_PDAC_W0 */
#define XRDC2_PAC_PDAC_W0_COUNT2 (256U)
/*! @name PAC_PDAC_W1 - Peripheral Domain Access Control */
/*! @{ */
#define XRDC2_PAC_PDAC_W1_D8ACP_MASK (0x7U)
#define XRDC2_PAC_PDAC_W1_D8ACP_SHIFT (0U)
/*! D8ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W1_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D8ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D8ACP_MASK)
#define XRDC2_PAC_PDAC_W1_D9ACP_MASK (0x38U)
#define XRDC2_PAC_PDAC_W1_D9ACP_SHIFT (3U)
/*! D9ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W1_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D9ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D9ACP_MASK)
#define XRDC2_PAC_PDAC_W1_D10ACP_MASK (0x1C0U)
#define XRDC2_PAC_PDAC_W1_D10ACP_SHIFT (6U)
/*! D10ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W1_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D10ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D10ACP_MASK)
#define XRDC2_PAC_PDAC_W1_D11ACP_MASK (0xE00U)
#define XRDC2_PAC_PDAC_W1_D11ACP_SHIFT (9U)
/*! D11ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W1_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D11ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D11ACP_MASK)
#define XRDC2_PAC_PDAC_W1_D12ACP_MASK (0x7000U)
#define XRDC2_PAC_PDAC_W1_D12ACP_SHIFT (12U)
/*! D12ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W1_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D12ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D12ACP_MASK)
#define XRDC2_PAC_PDAC_W1_D13ACP_MASK (0x38000U)
#define XRDC2_PAC_PDAC_W1_D13ACP_SHIFT (15U)
/*! D13ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W1_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D13ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D13ACP_MASK)
#define XRDC2_PAC_PDAC_W1_D14ACP_MASK (0x1C0000U)
#define XRDC2_PAC_PDAC_W1_D14ACP_SHIFT (18U)
/*! D14ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W1_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D14ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D14ACP_MASK)
#define XRDC2_PAC_PDAC_W1_D15ACP_MASK (0xE00000U)
#define XRDC2_PAC_PDAC_W1_D15ACP_SHIFT (21U)
/*! D15ACP - Domain "x" access control policy
*/
#define XRDC2_PAC_PDAC_W1_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_D15ACP_SHIFT)) & XRDC2_PAC_PDAC_W1_D15ACP_MASK)
#define XRDC2_PAC_PDAC_W1_EAL_MASK (0x3000000U)
#define XRDC2_PAC_PDAC_W1_EAL_SHIFT (24U)
/*! EAL - Exclusive Access Lock
* 0b00..Lock disabled.
* 0b01..Lock disabled until next reset.
* 0b10..Lock enabled, lock state = available.
* 0b11..Lock enabled, lock state = not available.
*/
#define XRDC2_PAC_PDAC_W1_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_EAL_SHIFT)) & XRDC2_PAC_PDAC_W1_EAL_MASK)
#define XRDC2_PAC_PDAC_W1_DL2_MASK (0x60000000U)
#define XRDC2_PAC_PDAC_W1_DL2_SHIFT (29U)
/*! DL2 - Descriptor Lock
* 0b00..Lock disabled, descriptor registers can be written..
* 0b01..Lock disabled until the next reset, descriptor registers can be written..
* 0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written..
* 0b11..Lock enabled, descriptor registers are read-only until the next reset.
*/
#define XRDC2_PAC_PDAC_W1_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_DL2_SHIFT)) & XRDC2_PAC_PDAC_W1_DL2_MASK)
#define XRDC2_PAC_PDAC_W1_VLD_MASK (0x80000000U)
#define XRDC2_PAC_PDAC_W1_VLD_SHIFT (31U)
/*! VLD - Valid
* 0b0..The PDAC assignment is invalid.
* 0b1..The PDAC assignment is valid.
*/
#define XRDC2_PAC_PDAC_W1_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_PAC_PDAC_W1_VLD_SHIFT)) & XRDC2_PAC_PDAC_W1_VLD_MASK)
/*! @} */
/* The count of XRDC2_PAC_PDAC_W1 */
#define XRDC2_PAC_PDAC_W1_COUNT (8U)
/* The count of XRDC2_PAC_PDAC_W1 */
#define XRDC2_PAC_PDAC_W1_COUNT2 (256U)
/*! @name MRC_MRGD_W0 - Memory Region Descriptor */
/*! @{ */
#define XRDC2_MRC_MRGD_W0_SRTADDR_MASK (0xFFFFF000U)
#define XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT (12U)
/*! SRTADDR - Start Address
*/
#define XRDC2_MRC_MRGD_W0_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W0_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W0_SRTADDR_MASK)
/*! @} */
/* The count of XRDC2_MRC_MRGD_W0 */
#define XRDC2_MRC_MRGD_W0_COUNT (32U)
/* The count of XRDC2_MRC_MRGD_W0 */
#define XRDC2_MRC_MRGD_W0_COUNT2 (32U)
/*! @name MRC_MRGD_W1 - Memory Region Descriptor */
/*! @{ */
#define XRDC2_MRC_MRGD_W1_SRTADDR_MASK (0xFU)
#define XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT (0U)
/*! SRTADDR - Start Address
*/
#define XRDC2_MRC_MRGD_W1_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W1_SRTADDR_SHIFT)) & XRDC2_MRC_MRGD_W1_SRTADDR_MASK)
/*! @} */
/* The count of XRDC2_MRC_MRGD_W1 */
#define XRDC2_MRC_MRGD_W1_COUNT (32U)
/* The count of XRDC2_MRC_MRGD_W1 */
#define XRDC2_MRC_MRGD_W1_COUNT2 (32U)
/*! @name MRC_MRGD_W2 - Memory Region Descriptor */
/*! @{ */
#define XRDC2_MRC_MRGD_W2_ENDADDR_MASK (0xFFFFF000U)
#define XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT (12U)
/*! ENDADDR - End Address
*/
#define XRDC2_MRC_MRGD_W2_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W2_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W2_ENDADDR_MASK)
/*! @} */
/* The count of XRDC2_MRC_MRGD_W2 */
#define XRDC2_MRC_MRGD_W2_COUNT (32U)
/* The count of XRDC2_MRC_MRGD_W2 */
#define XRDC2_MRC_MRGD_W2_COUNT2 (32U)
/*! @name MRC_MRGD_W3 - Memory Region Descriptor */
/*! @{ */
#define XRDC2_MRC_MRGD_W3_ENDADDR_MASK (0xFU)
#define XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT (0U)
/*! ENDADDR - End Address
*/
#define XRDC2_MRC_MRGD_W3_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W3_ENDADDR_SHIFT)) & XRDC2_MRC_MRGD_W3_ENDADDR_MASK)
/*! @} */
/* The count of XRDC2_MRC_MRGD_W3 */
#define XRDC2_MRC_MRGD_W3_COUNT (32U)
/* The count of XRDC2_MRC_MRGD_W3 */
#define XRDC2_MRC_MRGD_W3_COUNT2 (32U)
/*! @name MRC_MRGD_W5 - Memory Region Descriptor */
/*! @{ */
#define XRDC2_MRC_MRGD_W5_D0ACP_MASK (0x7U)
#define XRDC2_MRC_MRGD_W5_D0ACP_SHIFT (0U)
/*! D0ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W5_D0ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D0ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D0ACP_MASK)
#define XRDC2_MRC_MRGD_W5_D1ACP_MASK (0x38U)
#define XRDC2_MRC_MRGD_W5_D1ACP_SHIFT (3U)
/*! D1ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W5_D1ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D1ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D1ACP_MASK)
#define XRDC2_MRC_MRGD_W5_D2ACP_MASK (0x1C0U)
#define XRDC2_MRC_MRGD_W5_D2ACP_SHIFT (6U)
/*! D2ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W5_D2ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D2ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D2ACP_MASK)
#define XRDC2_MRC_MRGD_W5_D3ACP_MASK (0xE00U)
#define XRDC2_MRC_MRGD_W5_D3ACP_SHIFT (9U)
/*! D3ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W5_D3ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D3ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D3ACP_MASK)
#define XRDC2_MRC_MRGD_W5_D4ACP_MASK (0x7000U)
#define XRDC2_MRC_MRGD_W5_D4ACP_SHIFT (12U)
/*! D4ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W5_D4ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D4ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D4ACP_MASK)
#define XRDC2_MRC_MRGD_W5_D5ACP_MASK (0x38000U)
#define XRDC2_MRC_MRGD_W5_D5ACP_SHIFT (15U)
/*! D5ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W5_D5ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D5ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D5ACP_MASK)
#define XRDC2_MRC_MRGD_W5_D6ACP_MASK (0x1C0000U)
#define XRDC2_MRC_MRGD_W5_D6ACP_SHIFT (18U)
/*! D6ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W5_D6ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D6ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D6ACP_MASK)
#define XRDC2_MRC_MRGD_W5_D7ACP_MASK (0xE00000U)
#define XRDC2_MRC_MRGD_W5_D7ACP_SHIFT (21U)
/*! D7ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W5_D7ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_D7ACP_SHIFT)) & XRDC2_MRC_MRGD_W5_D7ACP_MASK)
#define XRDC2_MRC_MRGD_W5_EALO_MASK (0xF000000U)
#define XRDC2_MRC_MRGD_W5_EALO_SHIFT (24U)
/*! EALO - Exclusive Access Lock Owner
*/
#define XRDC2_MRC_MRGD_W5_EALO(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W5_EALO_SHIFT)) & XRDC2_MRC_MRGD_W5_EALO_MASK)
/*! @} */
/* The count of XRDC2_MRC_MRGD_W5 */
#define XRDC2_MRC_MRGD_W5_COUNT (32U)
/* The count of XRDC2_MRC_MRGD_W5 */
#define XRDC2_MRC_MRGD_W5_COUNT2 (32U)
/*! @name MRC_MRGD_W6 - Memory Region Descriptor */
/*! @{ */
#define XRDC2_MRC_MRGD_W6_D8ACP_MASK (0x7U)
#define XRDC2_MRC_MRGD_W6_D8ACP_SHIFT (0U)
/*! D8ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W6_D8ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D8ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D8ACP_MASK)
#define XRDC2_MRC_MRGD_W6_D9ACP_MASK (0x38U)
#define XRDC2_MRC_MRGD_W6_D9ACP_SHIFT (3U)
/*! D9ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W6_D9ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D9ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D9ACP_MASK)
#define XRDC2_MRC_MRGD_W6_D10ACP_MASK (0x1C0U)
#define XRDC2_MRC_MRGD_W6_D10ACP_SHIFT (6U)
/*! D10ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W6_D10ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D10ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D10ACP_MASK)
#define XRDC2_MRC_MRGD_W6_D11ACP_MASK (0xE00U)
#define XRDC2_MRC_MRGD_W6_D11ACP_SHIFT (9U)
/*! D11ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W6_D11ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D11ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D11ACP_MASK)
#define XRDC2_MRC_MRGD_W6_D12ACP_MASK (0x7000U)
#define XRDC2_MRC_MRGD_W6_D12ACP_SHIFT (12U)
/*! D12ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W6_D12ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D12ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D12ACP_MASK)
#define XRDC2_MRC_MRGD_W6_D13ACP_MASK (0x38000U)
#define XRDC2_MRC_MRGD_W6_D13ACP_SHIFT (15U)
/*! D13ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W6_D13ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D13ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D13ACP_MASK)
#define XRDC2_MRC_MRGD_W6_D14ACP_MASK (0x1C0000U)
#define XRDC2_MRC_MRGD_W6_D14ACP_SHIFT (18U)
/*! D14ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W6_D14ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D14ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D14ACP_MASK)
#define XRDC2_MRC_MRGD_W6_D15ACP_MASK (0xE00000U)
#define XRDC2_MRC_MRGD_W6_D15ACP_SHIFT (21U)
/*! D15ACP - Domain "x" access control policy
*/
#define XRDC2_MRC_MRGD_W6_D15ACP(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_D15ACP_SHIFT)) & XRDC2_MRC_MRGD_W6_D15ACP_MASK)
#define XRDC2_MRC_MRGD_W6_EAL_MASK (0x3000000U)
#define XRDC2_MRC_MRGD_W6_EAL_SHIFT (24U)
/*! EAL - Exclusive Access Lock
* 0b00..Lock disabled.
* 0b01..Lock disabled until next reset.
* 0b10..Lock enabled, lock state = available.
* 0b11..Lock enabled, lock state = not available.
*/
#define XRDC2_MRC_MRGD_W6_EAL(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_EAL_SHIFT)) & XRDC2_MRC_MRGD_W6_EAL_MASK)
#define XRDC2_MRC_MRGD_W6_DL2_MASK (0x60000000U)
#define XRDC2_MRC_MRGD_W6_DL2_SHIFT (29U)
/*! DL2 - Descriptor Lock
* 0b00..Lock disabled, descriptor registers can be written.
* 0b01..Lock disabled until the next reset, descriptor registers can be written.
* 0b10..Lock enabled, only domain "x" can only update the DxACP field; no other fields can be written.
* 0b11..Lock enabled, descriptor registers are read-only until the next reset.
*/
#define XRDC2_MRC_MRGD_W6_DL2(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_DL2_SHIFT)) & XRDC2_MRC_MRGD_W6_DL2_MASK)
#define XRDC2_MRC_MRGD_W6_VLD_MASK (0x80000000U)
#define XRDC2_MRC_MRGD_W6_VLD_SHIFT (31U)
/*! VLD - Valid
* 0b0..The MRGD is invalid.
* 0b1..The MRGD is valid.
*/
#define XRDC2_MRC_MRGD_W6_VLD(x) (((uint32_t)(((uint32_t)(x)) << XRDC2_MRC_MRGD_W6_VLD_SHIFT)) & XRDC2_MRC_MRGD_W6_VLD_MASK)
/*! @} */
/* The count of XRDC2_MRC_MRGD_W6 */
#define XRDC2_MRC_MRGD_W6_COUNT (32U)
/* The count of XRDC2_MRC_MRGD_W6 */
#define XRDC2_MRC_MRGD_W6_COUNT2 (32U)
/*!
* @}
*/ /* end of group XRDC2_Register_Masks */
/* XRDC2 - Peripheral instance base addresses */
/** Peripheral XRDC2_D0 base address */
#define XRDC2_D0_BASE (0x40CE0000u)
/** Peripheral XRDC2_D0 base pointer */
#define XRDC2_D0 ((XRDC2_Type *)XRDC2_D0_BASE)
/** Peripheral XRDC2_D1 base address */
#define XRDC2_D1_BASE (0x40CD0000u)
/** Peripheral XRDC2_D1 base pointer */
#define XRDC2_D1 ((XRDC2_Type *)XRDC2_D1_BASE)
/** Array initializer of XRDC2 peripheral base addresses */
#define XRDC2_BASE_ADDRS { XRDC2_D0_BASE, XRDC2_D1_BASE }
/** Array initializer of XRDC2 peripheral base pointers */
#define XRDC2_BASE_PTRS { XRDC2_D0, XRDC2_D1 }
/*!
* @}
*/ /* end of group XRDC2_Peripheral_Access_Layer */
/*
** End of section using anonymous unions
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang diagnostic pop
#else
#pragma pop
#endif
#elif defined(__CWCC__)
#pragma pop
#elif defined(__GNUC__)
/* leave anonymous unions enabled */
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma language=default
#else
#error Not supported compiler type
#endif
/*!
* @}
*/ /* end of group Peripheral_access_layer */
/* ----------------------------------------------------------------------------
-- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
---------------------------------------------------------------------------- */
/*!
* @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
* @{
*/
#if defined(__ARMCC_VERSION)
#if (__ARMCC_VERSION >= 6010050)
#pragma clang system_header
#endif
#elif defined(__IAR_SYSTEMS_ICC__)
#pragma system_include
#endif
/**
* @brief Mask and left-shift a bit field value for use in a register bit range.
* @param field Name of the register bit field.
* @param value Value of the bit field.
* @return Masked and shifted value.
*/
#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
/**
* @brief Mask and right-shift a register value to extract a bit field value.
* @param field Name of the register bit field.
* @param value Value of the register.
* @return Masked and shifted bit field value.
*/
#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
/*!
* @}
*/ /* end of group Bit_Field_Generic_Macros */
/* ----------------------------------------------------------------------------
-- SDK Compatibility
---------------------------------------------------------------------------- */
/*!
* @addtogroup SDK_Compatibility_Symbols SDK Compatibility
* @{
*/
/* No SDK compatibility issues. */
/*!
* @}
*/ /* end of group SDK_Compatibility_Symbols */
#endif /* _MIMXRT1176_CM7_H_ */
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