228 lines
6.7 KiB
C
228 lines
6.7 KiB
C
/*
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* Copyright (c) 2006-2018, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef __DRV_CODEC_H__
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#define __DRV_CODEC_H__
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#define SUNXI_DAC_DPC 0x00
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#define SUNXI_DAC_FIFOC 0x04
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#define SUNXI_DAC_FIFOS 0x08
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#define SUNXI_DAC_TXDATA 0x0c
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#define SUNXI_ADC_FIFOC 0x10
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#define SUNXI_ADC_FIFOS 0x14
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#define SUNXI_ADC_RXDATA 0x18
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#define DAC_MIXER_CTRL 0x20
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#define ADC_MIXER_CTRL 0x24
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#define ADDA_TUNE 0x28
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#define BIAS_DA16_CAL_CTRL0 0x2C
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#define BIAS_DA16_CAL_CTRL1 0x34
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#define SUNXI_DAC_CNT 0x40
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#define SUNXI_ADC_CNT 0x44
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#define SUNXI_DAC_DG 0x48
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#define SUNXI_ADC_DG 0x4c
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#define AC_PR_CFG 0x400
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/*AC_DAC_DPC:0x00*/
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#define EN_DAC 31
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#define MODQU 25
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#define DWA 24
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#define HPF_EN 18
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#define DVOL 12
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/*#define HUB_EN 0 */
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/*AC_DAC_FIFOC:0x04*/
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#define DAC_FS 29
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#define FIR_VER 28
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#define SEND_LASAT 26
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#define FIFO_MODE 24
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#define DAC_DRQ_CLR_CNT 21
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#define TX_TRIG_LEVEL 8
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#define ADDA_LOOP_EN 7
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#define DAC_MONO_EN 6
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#define TX_SAMPLE_BITS 5
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#define DAC_DRQ_EN 4
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#define DAC_IRQ_EN 3
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#define FIFO_UNDERRUN_IRQ_EN 2
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#define FIFO_OVERRUN_IRQ_EN 1
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#define FIFO_FLUSH 0
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/*AC_ADC_FIFOC:0x10*/
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#define ADFS 29
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#define EN_AD 28
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#define RX_FIFO_MODE 24
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#define ADCDFEN 16
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#define RX_FIFO_TRG_LEVEL 8
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#define ADC_MONO_EN 7
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#define RX_SAMPLE_BITS 6
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#define ADC_DRQ_EN 4
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#define ADC_IRQ_EN 3
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#define ADC_OVERRUN_IRQ_EN 1
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#define ADC_FIFO_FLUSH 0
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/*DAC_MIXER_CTRL: 0x20*/
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#define DAC_AG_R_EN 31 /* dac right enable bit */
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#define DAC_AG_L_EN 30 /* dac left enable bit */
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#define R_MIXER_EN 29 /* right output mixer */
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#define L_MIXER_EN 28 /* left output mixer */
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#define PH_R_MUTE 27 /* headphone right mute */
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#define PH_L_MUTE 26 /* headphone left mute */
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#define PH_R_PWR_SLT 25
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#define PH_L_PWR_SLT 24
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#define PH_COM_FC 22
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#define PH_COM_PROTEC 21
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#define R_MIXER_MUTE_MIC 20
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#define R_MIXER_MUTE_LINEIN 19
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#define R_MIXER_MUTE_FM 18
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#define R_MIXER_MUTE_R_DAC 17
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#define R_MIXER_MUTE_L_DAC 16
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#define R_MIXER_MUTE 16
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#define HP_POWER_EN 15
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#define L_MIXER_MUTE_MIC 12
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#define L_MIXER_MUTE_LINEIN 11
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#define L_MIXER_MUTE_FM 10
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#define L_MIXER_MUTE_R_DAC 9
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#define L_MIXER_MUTE_L_DAC 8
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#define L_MIXER_MUTE 8
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#define L_HP_TO_R_HP_MUTE 7
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#define R_HP_TO_L_HP_MUTE 6
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#define HP_VOL 0
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/*ADC_MIXER_CTRL: 0x24*/
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#define ADC_EN 31 /* adc enable bit */
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/* mic in boost stage to L or R output mixer gain control */
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#define MIC_GAIN_CTL 24
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#define LINEIN_VOL 21 /* right output mixer */
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#define ADC_IN_GAIN_CTL 16 /* adc input gain control */
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#define COS_SLOP_TM 14 /* COS slop time control for Anti-pop */
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#define ADC_MIX_MUTE_MIC 13
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#define ADC_MIX_MUTE_FML 12
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#define ADC_MIX_MUTE_FMR 11
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#define ADC_MIX_MUTE_LINEIN 10
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#define ADC_MIX_MUTE_L 9
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#define ADC_MIX_MUTE_R 8
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#define ADC_MIX_MUTE 8 /* ADC mixer mute control */
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#define PA_SPEED_SLT 7 /* PA speed select->0: normal 1: fast */
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#define FM_TO_MIX_GAIN 4 /* FMin to mixer gain control */
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#define MIC_BST_AMP_EN 3 /* MIC boost AMP enable */
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#define MIC_BOST_GAIN 0 /* MIC boast AMP gain control */
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/*AC_ADC_TXDATA:0x20*/
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#define TX_DATA 0
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/*AC_DAC_CNT:0x40*/
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#define TX_CNT 0
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/*AC_ADC_CNT:0x44*/
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#define RX_CNT 0
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/*AC_DAC_DG:0x48*/
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/*
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* DAC Modulator Debug
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* 0:DAC Modulator Normal Mode
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* 1:DAC Modulator Debug Mode
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*/
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#define DAC_MODU_SELECT 11
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/*
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* DAC Pattern Select
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* 00:Normal(Audio sample from TX fifo)
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* 01: -6 dB sin wave
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* 10: -60 dB sin wave
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* 11: silent wave
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*/
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#define DAC_PATTERN_SELECT 9
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/*
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* CODEC Clock Source Select
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* 0:codec clock from PLL
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* 1:codec clock from OSC(for debug)
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*/
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#define CODEC_CLK_SELECT 8
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/*
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* DAC output channel swap enable
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* 0:disable
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* 1:enable
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*/
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#define DA_SWP 6
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/*AC_ADC_DG:0x4c*/
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#define AD_SWP 24
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/*AC_PR_CFG:0x400*/
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#define AC_PR_RST 28
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#define AC_PR_RW 24
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#define AC_PR_ADDR 16
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#define ADDA_PR_WDAT 8
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#define ADDA_PR_RDAT 0
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#define R6_REG_CCU_BASE 0x01c20000
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#define R6_REG_PLL_AUDIO_CTRL (R6_REG_CCU_BASE + 0x008)
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#define R6_REG_BUS_CLK_GATING_0 (R6_REG_CCU_BASE + 0x060)
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#define R6_REG_BUS_CLK_GATING_1 (R6_REG_CCU_BASE + 0x064)
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#define R6_REG_BUS_CLK_GATING_2 (R6_REG_CCU_BASE + 0x068)
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#define R6_REG_AUDIO_CODEC_CLK (R6_REG_CCU_BASE + 0x140)
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#define R6_REG_BUS_SOFT_RST_0 (R6_REG_CCU_BASE + 0x02C0)
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#define R6_REG_BUS_SOFT_RST_1 (R6_REG_CCU_BASE + 0x02C4)
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#define R6_REG_BUS_SOFT_RST_2 (R6_REG_CCU_BASE + 0x02D0)
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#define R6_REG_PIO_BASE 0x01c20800
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#define R6_REG_PD_CFG0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X00))
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#define R6_REG_PD_CFG1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X04))
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#define R6_REG_PD_CFG2 (R6_REG_PIO_BASE + (3 * 0x24 + 0X08))
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#define R6_REG_PD_CFG3 (R6_REG_PIO_BASE + (3 * 0x24 + 0X0c))
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#define R6_REG_PD_DATA (R6_REG_PIO_BASE + (3 * 0x24 + 0X10))
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#define R6_REG_PD_DRV0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X14))
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#define R6_REG_PD_DRV1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X18))
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#define R6_REG_PD_PUL0 (R6_REG_PIO_BASE + (3 * 0x24 + 0X1c))
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#define R6_REG_PD_PUL1 (R6_REG_PIO_BASE + (3 * 0x24 + 0X20))
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#define R6_REG_AC_BASE 0x01c23c00
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#define R6_REG_AC_DAC_DPC (R6_REG_AC_BASE + 0x00)
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#define R6_REG_AC_DAC_FIFOC (R6_REG_AC_BASE + 0x04)
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#define R6_REG_AC_DAC_FIFOS (R6_REG_AC_BASE + 0x08)
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#define R6_REG_AC_DAC_TXDADA (R6_REG_AC_BASE + 0x0c)
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#define R6_REG_AC_ADC_FIFOC (R6_REG_AC_BASE + 0x10)
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#define R6_REG_AC_ADC_FIFOS (R6_REG_AC_BASE + 0x14)
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#define R6_REG_AC_ADC_RXDADA (R6_REG_AC_BASE + 0x18)
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#define R6_REG_DAC_MIXER_CTRL (R6_REG_AC_BASE + 0x20)
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#define R6_REG_ADC_MIXER_CTRL (R6_REG_AC_BASE + 0x24)
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#define R6_REG_AC_DAC_CNT (R6_REG_AC_BASE + 0x40)
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#define R6_REG_NDMA_0_BASE (0x01c02000 + 0x100 + 0 * 0x20)
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#define R6_REG_DMA_INT_CTRL (0x01c02000 + 0x00)
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#define R6_REG_DMA_INT_STA (0x01c02000 + 0x04)
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#define R6_REG_DMA_PTY_CFG (0x01c02000 + 0x08)
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#define REG_NDMA_CFG (0x0)
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#define REG_NDMA_SRC_ADR (0x4)
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#define REG_NDMA_DES_ADR (0x8)
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#define REG_NDMA_BYTE_CNT (0xc)
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#define NDMA_CFG_SRC_DRQ_IR_RX (0x00 << 0)
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#define NDMA_CFG_SRC_DRQ_NONE (0x01 << 0)
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#define NDMA_CFG_SRC_DRQ_SDRAM (0x11 << 0)
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#define NDMA_CFG_DST_LINEAR (0x00 << 21)
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#define NDMA_CFG_DST_DRQ_IR_RX (0x00 << 16)
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#define NDMA_CFG_DST_DRQ_NONE (0x01 << 16)
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#define NDMA_CFG_DST_DRQ_SRAM (0x10 << 16)
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#define NDMA_CFG_DST_DRQ_SDRAM (0x11 << 16)
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#define NDMA_CFG_SRC_DRQ_SRAM (0x10 << 0)
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#define NDMA_CFG_SRC_LINEAR (0x00 << 5)
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#define NDMA_CFG_SRC_BST4_WIDTH32 ((0x1 << 7) | (0x2 << 8))
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#define NDMA_CFG_DST_DRQ_CODEC (0x0c << 16)
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#define NDMA_CFG_DST_IO (0x1 << 21)
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#define NDMA_CFG_DST_BST4_WIDTH32 ((0x1 << 23) | (0x2 << 24))
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#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
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#endif
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