227 lines
7.4 KiB
C
227 lines
7.4 KiB
C
/*
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* ===========================================================================================
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*
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* Filename: sunxi_hal_spi.h
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*
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* Description: SPI HAL definition.
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*
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* Version: Melis3.0
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* Create: 2019-11-18 11:11:56
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* Revision: none
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* Compiler: GCC:version 9.2.1
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*
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* Author: bantao@allwinnertech.com
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* Organization: SWC-BPD
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* Last Modified: 2019-12-03 16:02:11
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*
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* ===========================================================================================
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*/
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#ifndef SUNXI_HAL_SPI_H
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#define SUNXI_HAL_SPI_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "sunxi_hal_common.h"
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#include <hal_gpio.h>
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#include <hal_dma.h>
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/* #include <sunxi_drv_spi.h> */
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#include <hal_sem.h>
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#include <hal_clk.h>
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#include <spi/platform_spi.h>
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#include <spi/common_spi.h>
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/*****************************************************************************
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* spi master
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*****************************************************************************/
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/** @brief This enum defines the SPI master port.
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* This chip total has 2 SPI master port
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*/
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typedef enum
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{
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HAL_SPI_MASTER_0 = 0, /**< spi master port 0 */
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HAL_SPI_MASTER_1 = 1, /**< spi master port 1 */
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HAL_SPI_MASTER_2 = 2, /**< spi master port 1 */
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HAL_SPI_MASTER_MAX = SPI_MAX_NUM, /**< spi master max port number\<invalid\> */
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} hal_spi_master_port_t;
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typedef struct
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{
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const uint8_t *tx_buf; /**< Data buffer to send, */
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uint32_t tx_len; /**< The total number of bytes to send. */
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uint32_t
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tx_single_len; /**< The number of bytes to send in single mode. */
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uint8_t *rx_buf; /**< Received data buffer, */
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uint32_t rx_len; /**< The valid number of bytes received. */
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uint8_t tx_nbits : 3; /**< Data buffer to send in nbits mode */
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uint8_t rx_nbits : 3; /**< Data buffer to received in nbits mode */
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uint8_t dummy_byte; /**< Flash send dummy byte, default 0*/
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#define SPI_NBITS_SINGLE 0x01 /* 1bit transfer */
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#define SPI_NBITS_DUAL 0x02 /* 2bit transfer */
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#define SPI_NBITS_QUAD 0x04 /* 4bit transfer */
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uint8_t bits_per_word; /**< transfer bit_per_word */
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} hal_spi_master_transfer_t;
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typedef enum spi_mode_type
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{
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SGLE_HALF_DUPLEX_RX, /* single mode, half duplex read */
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SGLE_HALF_DUPLEX_TX, /* single mode, half duplex write */
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DUAL_HALF_DUPLEX_RX, /* dual mode, half duplex read */
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DUAL_HALF_DUPLEX_TX, /* dual mode, half duplex write */
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QUAD_HALF_DUPLEX_RX, /* quad mode, half duplex read */
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QUAD_HALF_DUPLEX_TX, /* quad mode, half duplex write */
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FULL_DUPLEX_TX_RX, /* full duplex read and write */
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MODE_TYPE_NULL,
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} spi_mode_type_t;
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typedef struct spi_dma
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{
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struct dma_slave_config config;
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struct sunxi_dma_chan *chan;
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} spi_dma_t;
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typedef struct sunxi_spi
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{
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int8_t result : 2;
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#define SPI_XFER_READY 0
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#define SPI_XFER_OK 1
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#define SPI_XFER_FAILED -1
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bool sem;
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uint16_t irqnum;
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unsigned long base;
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spi_mode_type_t mode_type;
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hal_clk_t pclk; /* PLL clock */
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hal_clk_t bus_clk; /* BUS clock */
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hal_clk_t mclk; /* spi module clock */
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struct reset_control *reset;
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spi_dma_t dma_rx;
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spi_dma_t dma_tx;
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char *align_dma_buf;
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#define ALIGN_DMA_BUF_SIZE (4096 + 64)
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hal_sem_t xSemaphore_tx;
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hal_sem_t xSemaphore_rx;
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hal_spi_master_port_t port;
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hal_spi_master_transfer_t *transfer;
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} sunxi_spi_t;
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typedef enum
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{
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SPI_MASTER_ERROR = -6, /**< SPI master function error occurred. */
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SPI_MASTER_ERROR_NOMEM = -5, /**< SPI master request mem failed. */
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SPI_MASTER_ERROR_TIMEOUT = -4, /**< SPI master xfer timeout. */
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SPI_MASTER_ERROR_BUSY = -3, /**< SPI master is busy. */
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SPI_MASTER_ERROR_PORT = -2, /**< SPI master invalid port. */
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SPI_MASTER_INVALID_PARAMETER =
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-1, /**< SPI master invalid input parameter. */
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SPI_MASTER_OK = 0 /**< SPI master operation completed successfully. */
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} spi_master_status_t;
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/** @brief selection of spi slave device connected to which cs pin of spi master
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*/
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typedef enum
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{
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HAL_SPI_MASTER_SLAVE_0 =
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0, /**< spi slave device connect to spi master cs0 pin */
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HAL_SPI_MASTER_SLAVE_1 =
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1, /**< spi slave device connect to spi master cs1 pin */
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HAL_SPI_MASTER_SLAVE_MAX /**< spi master max cs pin number\<invalid\> */
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} hal_spi_master_slave_port_t;
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/** @brief SPI master clock polarity definition */
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typedef enum
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{
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HAL_SPI_MASTER_CLOCK_POLARITY0 = 0, /**< Clock polarity is 0 */
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HAL_SPI_MASTER_CLOCK_POLARITY1 = 2 /**< Clock polarity is 1 */
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} hal_spi_master_clock_polarity_t;
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/** @brief SPI master clock format definition */
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typedef enum
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{
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HAL_SPI_MASTER_CLOCK_PHASE0 = 0, /**< Clock format is 0 */
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HAL_SPI_MASTER_CLOCK_PHASE1 = 1 /**< Clock format is 1 */
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} hal_spi_master_clock_phase_t;
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/** @brief SPI master transaction bit order definition */
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typedef enum
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{
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HAL_SPI_MASTER_MSB_FIRST =
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0, /**< Both send and receive data transfer MSB first */
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HAL_SPI_MASTER_LSB_FIRST =
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1 /**< Both send and receive data transfer LSB first */
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} hal_spi_master_bit_order_t;
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/** @brief SPI master status. */
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typedef enum
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{
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HAL_SPI_MASTER_STATUS_ERROR =
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-6, /**< SPI master function error occurred. */
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HAL_SPI_MASTER_STATUS_ERROR_NOMEM =
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-5, /**< SPI master request mem failed. */
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HAL_SPI_MASTER_STATUS_ERROR_TIMEOUT =
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-4, /**< SPI master xfer timeout. */
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HAL_SPI_MASTER_STATUS_ERROR_BUSY = -3, /**< SPI master is busy. */
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HAL_SPI_MASTER_STATUS_ERROR_PORT = -2, /**< SPI master invalid port. */
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HAL_SPI_MASTER_STATUS_INVALID_PARAMETER =
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-1, /**< SPI master invalid input parameter. */
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HAL_SPI_MASTER_STATUS_OK =
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0 /**< SPI master operation completed successfully. */
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} hal_spi_master_status_t;
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/** @brief SPI master running status. */
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typedef enum
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{
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HAL_SPI_MASTER_BUSY = 0, /**< SPI master is busy. */
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HAL_SPI_MASTER_IDLE = 1 /**< SPI master is idle. */
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} hal_spi_master_running_status_t;
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typedef enum
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{
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HAL_SPI_MASTER_CS_AUTO = 0,
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HAL_SPI_MASTER_CS_SOFT = 1,
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} hal_spi_master_cs_mode_t;
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typedef struct
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{
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uint32_t clock_frequency; /**< SPI master clock frequency setting. */
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hal_spi_master_slave_port_t
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slave_port; /**< SPI slave device selection. */
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hal_spi_master_bit_order_t
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bit_order; /**< SPI master bit order setting. 0:MSB first 1:LSB
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first*/
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hal_spi_master_clock_polarity_t
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cpol; /**< SPI master clock polarity setting. 0:Active high
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polarity(0 = Idle) 1:Active low polarity(1 = Idle) */
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hal_spi_master_clock_phase_t
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cpha; /**< SPI master clock phase setting. 0: Phase 0(Leading edge
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for sample data) 1: Phase 1(Leading edge for setup data)
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*/
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hal_spi_master_cs_mode_t csmode;
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} hal_spi_master_config_t;
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typedef enum
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{
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SPI_WRITE_READ = 0, /**< SPI master is busy. */
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SPI_CONFIG = 1 /**< SPI master is idle. */
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} hal_spi_transfer_cmd_t;
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spi_master_status_t hal_spi_init(hal_spi_master_port_t port, hal_spi_master_config_t *cfg);
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spi_master_status_t hal_spi_write(hal_spi_master_port_t port, const void *buf, uint32_t size);
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spi_master_status_t hal_spi_deinit(hal_spi_master_port_t port);
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spi_master_status_t hal_spi_read(hal_spi_master_port_t port, void *buf, uint32_t size);
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spi_master_status_t hal_spi_xfer(hal_spi_master_port_t port, hal_spi_master_transfer_t *transfer);
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spi_master_status_t hal_spi_hw_config(hal_spi_master_port_t port, hal_spi_master_config_t *spi_config);
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void hal_spi_cs(hal_spi_master_port_t port, uint8_t on_off);
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#endif
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