196 lines
5.7 KiB
C
196 lines
5.7 KiB
C
/*
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* ===========================================================================================
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*
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* Filename: sunxi_hal_spi.h
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*
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* Description: SPI HAL definition.
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*
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* Version: Melis3.0
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* Create: 2020-04-08 11:11:56
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* Revision: none
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* Compiler: GCC:version 9.2.1
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*
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* Author: bantao@allwinnertech.com
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* Organization: SWC-BPD
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* Last Modified: 2020-04-08 16:02:11
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*
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* ===========================================================================================
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*/
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#ifndef _CIR_H_
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#define _CIR_H_
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#include "hal_clk.h"
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#include "hal_reset.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/* Registers */
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#define CIR_CTRL (0x00) /* IR Control */
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#define CIR_RXCTRL (0x10) /* Rx Config */
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#define CIR_RXFIFO (0x20) /* Rx Data */
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#define CIR_RXINT (0x2C) /* Rx Interrupt Enable */
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#define CIR_RXSTA (0x30) /* Rx Interrupt Status */
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#define CIR_CONFIG (0x34) /* IR Sample Config */
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/*CIR_CTRL*/
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#define GEN_OFFSET 0
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#define RXEN_OFFSET 1
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#define CIR_ENABLE_OFFSET 4
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#define CIR_MODE_OFFSET 6
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/*global enable*/
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#define GEN (0x01 << GEN_OFFSET)
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/*receiver block enable*/
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#define RXEN (0x01 << RXEN_OFFSET)
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/*cir enable*/
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#define CIR_ENABLE (0x03 << CIR_ENABLE_OFFSET)
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/*active pulse accept mode*/
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#define CIR_MODE (0x03 << CIR_MODE_OFFSET)
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/*CIR_RXCTRL*/
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#define RPPI_OFFSET 2
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#define RPPI (0x01 << RPPI_OFFSET) /*receiver pulse polarity invert*/
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/*CIR_RXINT*/
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#define ROI_EN_OFFSET 0
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#define PREI_EN_OFFSET 1
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#define RAI_EN_OFFSET 4
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#define DRQ_EN_OFFSET 5
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#define RAL_OFFSET 8
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/*receiver fifo overrun interrupt enable*/
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#define ROI_EN (0x01 << ROI_EN_OFFSET)
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/*receiver packet end interrupt enable*/
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#define PREI_EN (0x01 << PREI_EN_OFFSET)
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/*rx fifo available interrupt enable*/
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#define RAI_EN (0x01 << RAI_EN_OFFSET)
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/*rx fifo dma enable*/
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#define DRQ_EN (0x01 << DRQ_EN_OFFSET)
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/*rx fifo available received byte level*/
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#define RAL (0x3f << RAL_OFFSET)
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#define IRQ_MASK (0x3f)
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/*CIR_RXSTA*/
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#define ROI_OFFSET 0
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#define RPE_OFFSET 1
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#define RA_OFFSET 4
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#define STAT_OFFSET 7
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#define RAC_OFFSET 8
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#define ROI (0x01 << ROI_OFFSET) /*receiver fifo overrun*/
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#define RPE (0x01 << RPE_OFFSET) /*receiver packet end reg*/
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#define RA (0x01 << RA_OFFSET) /*rx fifo available*/
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#define STAT (0x01 << STAT_OFFSET) /*status of cir, 0:idle, 1:busy*/
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#define RAC (0x7f << RAC_OFFSET) /*rx fifo available counter*/
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/*CIR_CONFIG*/
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#define SCS_OFFSET 0
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#define NTHR_OFFSET 2
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#define ITHR_OFFSET 8
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#define ATHR_OFFSET 16
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#define ATHC_OFFSET 23
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#define SCS2_OFFSET 24
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#define SCS (0x03 << SCS_OFFSET) /*sample clk select for cir*/
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#define NTHR (0x3f << NTHR_OFFSET) /*noise threshold for cir*/
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#define ITHR (0xff << ITHR_OFFSET) /*idle threshold for cir*/
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#define ATHR (0x7f << ATHR_OFFSET) /*active threshold for cir*/
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#define ATHC (0x01 << ATHC_OFFSET) /*active threshold control for cir*/
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#define SCS2 (0x01 << SCS2_OFFSET) /*bit2 of sample clock select for cir*/
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#define CIR_NOISE_THR_NEC 32
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#define CIR_NOISE_THR_RC5 22
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typedef enum {
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CIR_MASTER_0 = 0,
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CIR_MASTER_NUM,
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} cir_port_t;
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typedef enum {
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CIR_BOTH_PULSE = 0x01, /*both positive and negative pulses*/
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CIR_LOW_PULSE = 0x02, /*only negative pulse*/
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CIR_HIGH_PULSE = 0x03, /*only positive pulse*/
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} cir_mode_t;
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typedef enum {
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CIR_PIN_ERR = -4,
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CIR_CLK_ERR = -3,
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CIR_IRQ_ERR = -2,
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CIR_PORT_ERR = -1,
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CIR_OK = 0,
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} cir_status_t;
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typedef enum {
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CIR_CLK_DIV64 = 0x0,
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CIR_CLK_DIV128 = 0x01,
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CIR_CLK_DIV256 = 0x02,
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CIR_CLK_DIV512 = 0x03,
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CIR_CLK = 0x04,
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} cir_sample_clock_t;
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typedef struct {
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uint32_t gpio;
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uint8_t enable_mux;
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uint8_t disable_mux;
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} cir_gpio_t;
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typedef struct {
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uint32_t bus_clk;
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uint32_t mclk;
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uint32_t pclk;
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} cir_clk_t;
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typedef int (*cir_callback_t)(cir_port_t port, uint32_t data_type, uint32_t data);
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typedef struct {
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cir_port_t port;
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unsigned long base;
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uint32_t irq;
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cir_clk_t *clk;
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cir_gpio_t *pin;
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cir_callback_t callback;
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uint8_t status;
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hal_clk_t bclk;
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hal_clk_t pclk;
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hal_clk_t mclk;
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hal_clk_t test_clk;
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hal_clk_id_t m_clk_id;
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hal_clk_id_t p_clk_id;
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hal_clk_id_t b_clk_id;
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hal_clk_id_t test_clk_id;
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hal_clk_type_t cir_clk_type_R;
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hal_clk_type_t cir_clk_type_FIXED;
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hal_clk_type_t test_clk_type;
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struct reset_control *cir_reset;
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} sunxi_cir_t;
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void sunxi_cir_callback_register(cir_port_t port, cir_callback_t callback);
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void sunxi_cir_mode_enable(cir_port_t port, uint8_t enable);
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void sunxi_cir_mode_config(cir_port_t port, cir_mode_t mode);
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void sunxi_cir_sample_clock_select(cir_port_t port, cir_sample_clock_t div);
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void sunxi_cir_sample_noise_threshold(cir_port_t port, int8_t threshold);
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void sunxi_cir_sample_idle_threshold(cir_port_t port, int8_t threshold);
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void sunxi_cir_sample_active_threshold(cir_port_t port, int8_t threshold);
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void sunxi_cir_sample_active_thrctrl(cir_port_t port, int8_t enable);
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void sunxi_cir_fifo_level(cir_port_t port, int8_t size);
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void sunxi_cir_irq_enable(cir_port_t port, int enable);
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void sunxi_cir_irq_disable(cir_port_t port);
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void sunxi_cir_signal_invert(cir_port_t port, uint8_t invert);
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void sunxi_cir_module_enable(cir_port_t port, int8_t enable);
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cir_status_t sunxi_cir_init(cir_port_t port);
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void sunxi_cir_deinit(cir_port_t port);
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#ifdef CONFIG_STANDBY
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void sunxi_cir_suspend(cir_port_t port);
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void sunxi_cir_resume(cir_port_t port);
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#endif
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#ifdef __cplusplus
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}
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#endif
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#endif
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