363 lines
13 KiB
C
363 lines
13 KiB
C
/**
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******************************************************************************
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* @file system_stm32u5xx.c
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* @author MCD Application Team
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* @brief CMSIS Cortex-M33 Device Peripheral Access Layer System Source File
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*
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* This file provides two functions and one global variable to be called from
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* user application:
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* - SystemInit(): This function is called at startup just after reset and
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* before branch to main program. This call is made inside
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* the "startup_stm32u5xx.s" file.
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*
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
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* by the user application to setup the SysTick
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* timer or configure other parameters.
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*
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
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* be called whenever the core clock is changed
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* during program execution.
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*
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* After each device reset the MSI (4 MHz) is used as system clock source.
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* Then SystemInit() function is called, in "startup_stm32u5xx.s" file, to
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* configure the system clock before to branch to main program.
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*
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* This file configures the system clock as follows:
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*=============================================================================
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*-----------------------------------------------------------------------------
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* System Clock source | MSI
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*-----------------------------------------------------------------------------
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* SYSCLK(Hz) | 4000000
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*-----------------------------------------------------------------------------
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* HCLK(Hz) | 4000000
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*-----------------------------------------------------------------------------
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* AHB Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB1 Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB2 Prescaler | 1
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*-----------------------------------------------------------------------------
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* APB3 Prescaler | 1
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*-----------------------------------------------------------------------------
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* PLL1_SRC | No clock
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*-----------------------------------------------------------------------------
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* PLL1_M | 1
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*-----------------------------------------------------------------------------
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* PLL1_N | 8
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*-----------------------------------------------------------------------------
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* PLL1_P | 7
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*-----------------------------------------------------------------------------
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* PLL1_Q | 2
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*-----------------------------------------------------------------------------
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* PLL1_R | 2
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*-----------------------------------------------------------------------------
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* PLL2_SRC | NA
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*-----------------------------------------------------------------------------
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* PLL2_M | NA
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*-----------------------------------------------------------------------------
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* PLL2_N | NA
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*-----------------------------------------------------------------------------
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* PLL2_P | NA
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*-----------------------------------------------------------------------------
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* PLL2_Q | NA
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*-----------------------------------------------------------------------------
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* PLL2_R | NA
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*-----------------------------------------------------------------------------
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* PLL3_SRC | NA
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*-----------------------------------------------------------------------------
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* PLL3_M | NA
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*-----------------------------------------------------------------------------
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* PLL3_N | NA
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*-----------------------------------------------------------------------------
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* PLL3_P | NA
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*-----------------------------------------------------------------------------
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* Require 48MHz for USB FS, | Disabled
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* SDIO and RNG clock |
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*-----------------------------------------------------------------------------
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*=============================================================================
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******************************************************************************
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* @attention
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*
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* Copyright (c) 2021 STMicroelectronics.
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* All rights reserved.
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*
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* This software is licensed under terms that can be found in the LICENSE file
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* in the root directory of this software component.
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* If no LICENSE file comes with this software, it is provided AS-IS.
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*
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******************************************************************************
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*/
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/** @addtogroup CMSIS
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* @{
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*/
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/** @addtogroup STM32U5xx_system
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* @{
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*/
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/** @addtogroup STM32U5xx_System_Private_Includes
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* @{
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*/
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#include "stm32u5xx.h"
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#include <math.h>
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/**
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* @}
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*/
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/** @addtogroup STM32U5xx_System_Private_TypesDefinitions
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32U5xx_System_Private_Defines
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* @{
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*/
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#if !defined (HSE_VALUE)
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#define HSE_VALUE 16000000U /*!< Value of the External oscillator in Hz */
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#endif /* HSE_VALUE */
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#if !defined (MSI_VALUE)
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#define MSI_VALUE 4000000U /*!< Value of the Internal oscillator in Hz*/
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#endif /* MSI_VALUE */
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#if !defined (HSI_VALUE)
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#define HSI_VALUE 16000000U /*!< Value of the Internal oscillator in Hz*/
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#endif /* HSI_VALUE */
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/************************* Miscellaneous Configuration ************************/
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/*!< Uncomment the following line if you need to relocate your vector Table in
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Internal SRAM. */
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/* #define VECT_TAB_SRAM */
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#define VECT_TAB_OFFSET 0x00000000UL /*!< Vector Table base offset field.
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This value must be a multiple of 0x200. */
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/******************************************************************************/
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/**
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* @}
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*/
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/** @addtogroup STM32U5xx_System_Private_Macros
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32U5xx_System_Private_Variables
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* @{
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*/
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/* The SystemCoreClock variable is updated in three ways:
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1) by calling CMSIS function SystemCoreClockUpdate()
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2) by calling HAL API function HAL_RCC_GetHCLKFreq()
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
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Note: If you use this function to configure the system clock; then there
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is no need to call the 2 first functions listed above, since SystemCoreClock
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variable is updated automatically.
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*/
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uint32_t SystemCoreClock = 4000000U;
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const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U};
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const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U};
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const uint32_t MSIRangeTable[16] = {48000000U,24000000U,16000000U,12000000U, 4000000U, 2000000U, 1500000U,\
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1000000U, 3072000U, 1536000U,1024000U, 768000U, 400000U, 200000U, 150000U, 100000U};
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/**
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* @}
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*/
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/** @addtogroup STM32U5xx_System_Private_FunctionPrototypes
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* @{
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*/
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/**
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* @}
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*/
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/** @addtogroup STM32U5xx_System_Private_Functions
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* @{
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*/
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/**
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* @brief Setup the microcontroller system.
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* @param None
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* @retval None
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*/
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void SystemInit(void)
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{
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/* FPU settings ------------------------------------------------------------*/
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#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
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SCB->CPACR |= ((3UL << 20U)|(3UL << 22U)); /* set CP10 and CP11 Full Access */
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#endif
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/* Reset the RCC clock configuration to the default reset state ------------*/
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/* Set MSION bit */
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RCC->CR = RCC_CR_MSISON;
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/* Reset CFGR register */
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RCC->CFGR1 = 0U;
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RCC->CFGR2 = 0U;
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RCC->CFGR3 = 0U;
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/* Reset HSEON, CSSON , HSION, PLLxON bits */
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RCC->CR &= ~(RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLL1ON | RCC_CR_PLL2ON | RCC_CR_PLL3ON);
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/* Reset PLLCFGR register */
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RCC->PLL1CFGR = 0U;
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/* Reset HSEBYP bit */
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RCC->CR &= ~(RCC_CR_HSEBYP);
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/* Disable all interrupts */
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RCC->CIER = 0U;
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/* Configure the Vector Table location add offset address ------------------*/
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#ifdef VECT_TAB_SRAM
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SCB->VTOR = SRAM1_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
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#else
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
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#endif
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}
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/**
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* @brief Update SystemCoreClock variable according to Clock Register Values.
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* The SystemCoreClock variable contains the core clock (HCLK), it can
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* be used by the user application to setup the SysTick timer or configure
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* other parameters.
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*
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* @note Each time the core clock (HCLK) changes, this function must be called
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* to update SystemCoreClock variable value. Otherwise, any configuration
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* based on this variable will be incorrect.
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*
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* @note - The system frequency computed by this function is not the real
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* frequency in the chip. It is calculated based on the predefined
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* constant and the selected clock source:
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*
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* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI_VALUE(*)
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*
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(**)
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*
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(***)
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*
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(***)
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* or HSI_VALUE(*) or MSI_VALUE(*) multiplied/divided by the PLL factors.
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*
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* (*) MSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
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* 4 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (**) HSI_VALUE is a constant defined in stm32u5xx_hal.h file (default value
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* 16 MHz) but the real value may vary depending on the variations
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* in voltage and temperature.
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*
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* (***) HSE_VALUE is a constant defined in stm32u5xx_hal.h file (default value
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real
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* frequency of the crystal used. Otherwise, this function may
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* have wrong result.
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*
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* - The result of this function could be not correct when using fractional
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* value for HSE crystal.
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*
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* @param None
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* @retval None
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*/
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void SystemCoreClockUpdate(void)
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{
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uint32_t pllr, pllsource, pllm , tmp, pllfracen, msirange;
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float_t fracn1, pllvco;
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/* Get MSI Range frequency--------------------------------------------------*/
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if(READ_BIT(RCC->ICSCR1, RCC_ICSCR1_MSIRGSEL) == 0U)
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{
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/* MSISRANGE from RCC_CSR applies */
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msirange = (RCC->CSR & RCC_CSR_MSISSRANGE) >> RCC_CSR_MSISSRANGE_Pos;
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}
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else
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{
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/* MSIRANGE from RCC_CR applies */
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msirange = (RCC->ICSCR1 & RCC_ICSCR1_MSISRANGE) >> RCC_ICSCR1_MSISRANGE_Pos;
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}
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/*MSI frequency range in HZ*/
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msirange = MSIRangeTable[msirange];
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/* Get SYSCLK source -------------------------------------------------------*/
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switch (RCC->CFGR1 & RCC_CFGR1_SWS)
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{
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case 0x00: /* MSI used as system clock source */
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SystemCoreClock = msirange;
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break;
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case 0x04: /* HSI used as system clock source */
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SystemCoreClock = HSI_VALUE;
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break;
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case 0x08: /* HSE used as system clock source */
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SystemCoreClock = HSE_VALUE;
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break;
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case 0x0C: /* PLL used as system clock source */
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/* PLL_VCO = (HSE_VALUE or HSI_VALUE or MSI_VALUE/ PLLM) * PLLN
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SYSCLK = PLL_VCO / PLLR
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*/
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pllsource = (RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1SRC);
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pllm = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1M)>> RCC_PLL1CFGR_PLL1M_Pos) + 1U;
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pllfracen = ((RCC->PLL1CFGR & RCC_PLL1CFGR_PLL1FRACEN)>>RCC_PLL1CFGR_PLL1FRACEN_Pos);
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fracn1 = (float_t)(uint32_t)(pllfracen* ((RCC->PLL1FRACR & RCC_PLL1FRACR_PLL1FRACN)>> RCC_PLL1FRACR_PLL1FRACN_Pos));
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switch (pllsource)
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{
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case 0x00: /* No clock sent to PLL*/
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pllvco = (float_t)0U;
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break;
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case 0x02: /* HSI used as PLL clock source */
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pllvco = ((float_t)HSI_VALUE / (float_t)pllm);
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break;
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case 0x03: /* HSE used as PLL clock source */
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pllvco = ((float_t)HSE_VALUE / (float_t)pllm);
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break;
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default: /* MSI used as PLL clock source */
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pllvco = ((float_t)msirange / (float_t)pllm);
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break;
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}
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pllvco = pllvco * ((float_t)(uint32_t)(RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1N) + (fracn1/(float_t)0x2000) + (float_t)1U);
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pllr = (((RCC->PLL1DIVR & RCC_PLL1DIVR_PLL1R) >> RCC_PLL1DIVR_PLL1R_Pos) + 1U );
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SystemCoreClock = (uint32_t)((uint32_t)pllvco/pllr);
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break;
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default:
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SystemCoreClock = msirange;
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break;
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}
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/* Compute HCLK clock frequency --------------------------------------------*/
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/* Get HCLK prescaler */
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tmp = AHBPrescTable[((RCC->CFGR2 & RCC_CFGR2_HPRE) >> RCC_CFGR2_HPRE_Pos)];
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/* HCLK clock frequency */
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SystemCoreClock >>= tmp;
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}
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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