817 lines
29 KiB
C
817 lines
29 KiB
C
/*
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* Copyright (c) 2015, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_flexio_i2c_master.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief FLEXIO I2C transfer state */
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enum _flexio_i2c_master_transfer_states
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{
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kFLEXIO_I2C_Idle = 0x0U, /*!< I2C bus idle */
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kFLEXIO_I2C_CheckAddress = 0x1U, /*!< 7-bit address check state */
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kFLEXIO_I2C_SendCommand = 0x2U, /*!< Send command byte phase */
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kFLEXIO_I2C_SendData = 0x3U, /*!< Send data transfer phase*/
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kFLEXIO_I2C_ReceiveDataBegin = 0x4U, /*!< Receive data begin transfer phase*/
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kFLEXIO_I2C_ReceiveData = 0x5U, /*!< Receive data transfer phase*/
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};
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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extern const clock_ip_name_t s_flexioClocks[];
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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extern FLEXIO_Type *const s_flexioBases[];
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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extern uint32_t FLEXIO_GetInstance(FLEXIO_Type *base);
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/*!
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* @brief Set up master transfer, send slave address and decide the initial
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* transfer state.
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*
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* @param base pointer to FLEXIO_I2C_Type structure
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* @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
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* @param transfer pointer to flexio_i2c_master_transfer_t structure
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*/
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static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
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flexio_i2c_master_handle_t *handle,
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flexio_i2c_master_transfer_t *xfer);
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/*!
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* @brief Master run transfer state machine to perform a byte of transfer.
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*
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* @param base pointer to FLEXIO_I2C_Type structure
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* @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
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* @param statusFlags flexio i2c hardware status
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* @retval kStatus_Success Successfully run state machine
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* @retval kStatus_FLEXIO_I2C_Nak Receive Nak during transfer
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*/
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static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
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flexio_i2c_master_handle_t *handle,
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uint32_t statusFlags);
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/*!
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* @brief Complete transfer, disable interrupt and call callback.
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*
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* @param base pointer to FLEXIO_I2C_Type structure
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* @param handle pointer to flexio_i2c_master_handle_t structure which stores the transfer state
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* @param status flexio transfer status
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*/
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static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
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flexio_i2c_master_handle_t *handle,
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status_t status);
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/*******************************************************************************
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* Codes
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******************************************************************************/
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uint32_t FLEXIO_I2C_GetInstance(FLEXIO_I2C_Type *base)
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{
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return FLEXIO_GetInstance(base->flexioBase);
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}
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static status_t FLEXIO_I2C_MasterTransferInitStateMachine(FLEXIO_I2C_Type *base,
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flexio_i2c_master_handle_t *handle,
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flexio_i2c_master_transfer_t *xfer)
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{
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bool needRestart;
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uint32_t byteCount;
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/* Init the handle member. */
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handle->transfer.slaveAddress = xfer->slaveAddress;
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handle->transfer.direction = xfer->direction;
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handle->transfer.subaddress = xfer->subaddress;
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handle->transfer.subaddressSize = xfer->subaddressSize;
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handle->transfer.data = xfer->data;
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handle->transfer.dataSize = xfer->dataSize;
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handle->transfer.flags = xfer->flags;
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handle->transferSize = xfer->dataSize;
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/* Initial state, i2c check address state. */
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handle->state = kFLEXIO_I2C_CheckAddress;
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/* Clear all status before transfer. */
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FLEXIO_I2C_MasterClearStatusFlags(base, kFLEXIO_I2C_ReceiveNakFlag);
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/* Calculate whether need to send re-start. */
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needRestart = (handle->transfer.subaddressSize != 0) && (handle->transfer.direction == kFLEXIO_I2C_Read);
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/* Calculate total byte count in a frame. */
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byteCount = 1;
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if (!needRestart)
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{
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byteCount += handle->transfer.dataSize;
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}
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if (handle->transfer.subaddressSize != 0)
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{
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byteCount += handle->transfer.subaddressSize;
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/* Next state, send command byte. */
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handle->state = kFLEXIO_I2C_SendCommand;
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}
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/* Configure data count. */
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if (FLEXIO_I2C_MasterSetTransferCount(base, byteCount) != kStatus_Success)
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{
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return kStatus_InvalidArgument;
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}
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while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
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{
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}
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/* Send address byte first. */
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if (needRestart)
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{
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FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Write);
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}
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else
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{
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FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, handle->transfer.direction);
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}
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return kStatus_Success;
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}
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static status_t FLEXIO_I2C_MasterTransferRunStateMachine(FLEXIO_I2C_Type *base,
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flexio_i2c_master_handle_t *handle,
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uint32_t statusFlags)
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{
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if (statusFlags & kFLEXIO_I2C_ReceiveNakFlag)
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{
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/* Clear receive nak flag. */
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FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
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if ((!((handle->state == kFLEXIO_I2C_SendData) && (handle->transfer.dataSize == 0U))) &&
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(!(((handle->state == kFLEXIO_I2C_ReceiveData) || (handle->state == kFLEXIO_I2C_ReceiveDataBegin)) &&
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(handle->transfer.dataSize == 1U))))
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{
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FLEXIO_I2C_MasterReadByte(base);
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FLEXIO_I2C_MasterAbortStop(base);
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handle->state = kFLEXIO_I2C_Idle;
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return kStatus_FLEXIO_I2C_Nak;
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}
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}
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if (handle->state == kFLEXIO_I2C_CheckAddress)
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{
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if (handle->transfer.direction == kFLEXIO_I2C_Write)
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{
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/* Next state, send data. */
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handle->state = kFLEXIO_I2C_SendData;
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}
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else
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{
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/* Next state, receive data begin. */
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handle->state = kFLEXIO_I2C_ReceiveDataBegin;
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}
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}
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if ((statusFlags & kFLEXIO_I2C_RxFullFlag) && (handle->state != kFLEXIO_I2C_ReceiveData))
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{
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FLEXIO_I2C_MasterReadByte(base);
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}
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switch (handle->state)
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{
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case kFLEXIO_I2C_SendCommand:
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if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
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{
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if (handle->transfer.subaddressSize > 0)
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{
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handle->transfer.subaddressSize--;
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FLEXIO_I2C_MasterWriteByte(
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base, ((handle->transfer.subaddress) >> (8 * handle->transfer.subaddressSize)));
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if (handle->transfer.subaddressSize == 0)
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{
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/* Load re-start in advance. */
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if (handle->transfer.direction == kFLEXIO_I2C_Read)
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{
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while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
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{
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}
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FLEXIO_I2C_MasterRepeatedStart(base);
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}
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}
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}
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else
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{
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if (handle->transfer.direction == kFLEXIO_I2C_Write)
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{
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/* Next state, send data. */
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handle->state = kFLEXIO_I2C_SendData;
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/* Send first byte of data. */
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if (handle->transfer.dataSize > 0)
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{
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FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
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handle->transfer.data++;
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handle->transfer.dataSize--;
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}
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}
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else
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{
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FLEXIO_I2C_MasterSetTransferCount(base, (handle->transfer.dataSize + 1));
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FLEXIO_I2C_MasterStart(base, handle->transfer.slaveAddress, kFLEXIO_I2C_Read);
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/* Next state, receive data begin. */
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handle->state = kFLEXIO_I2C_ReceiveDataBegin;
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}
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}
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}
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break;
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/* Send command byte. */
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case kFLEXIO_I2C_SendData:
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if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
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{
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/* Send one byte of data. */
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if (handle->transfer.dataSize > 0)
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{
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FLEXIO_I2C_MasterWriteByte(base, *handle->transfer.data);
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handle->transfer.data++;
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handle->transfer.dataSize--;
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}
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else
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{
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FLEXIO_I2C_MasterStop(base);
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while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag))
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{
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}
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FLEXIO_I2C_MasterReadByte(base);
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handle->state = kFLEXIO_I2C_Idle;
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}
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}
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break;
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case kFLEXIO_I2C_ReceiveDataBegin:
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if (statusFlags & kFLEXIO_I2C_RxFullFlag)
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{
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handle->state = kFLEXIO_I2C_ReceiveData;
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/* Send nak at the last receive byte. */
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if (handle->transfer.dataSize == 1)
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{
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FLEXIO_I2C_MasterEnableAck(base, false);
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while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
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{
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}
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FLEXIO_I2C_MasterStop(base);
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}
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else
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{
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FLEXIO_I2C_MasterEnableAck(base, true);
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}
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}
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else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
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{
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/* Read one byte of data. */
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FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
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}
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else
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{
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}
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break;
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case kFLEXIO_I2C_ReceiveData:
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if (statusFlags & kFLEXIO_I2C_RxFullFlag)
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{
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*handle->transfer.data = FLEXIO_I2C_MasterReadByte(base);
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handle->transfer.data++;
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if (handle->transfer.dataSize--)
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{
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if (handle->transfer.dataSize == 0)
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{
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FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_RxFullInterruptEnable);
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handle->state = kFLEXIO_I2C_Idle;
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}
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/* Send nak at the last receive byte. */
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if (handle->transfer.dataSize == 1)
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{
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FLEXIO_I2C_MasterEnableAck(base, false);
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while (!((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0]))))
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{
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}
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FLEXIO_I2C_MasterStop(base);
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}
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}
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}
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else if (statusFlags & kFLEXIO_I2C_TxEmptyFlag)
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{
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if (handle->transfer.dataSize > 1)
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{
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FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
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}
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}
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else
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{
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}
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break;
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default:
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break;
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}
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return kStatus_Success;
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}
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static void FLEXIO_I2C_MasterTransferComplete(FLEXIO_I2C_Type *base,
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flexio_i2c_master_handle_t *handle,
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status_t status)
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{
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FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
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if (handle->completionCallback)
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{
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handle->completionCallback(base, handle, status, handle->userData);
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}
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}
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status_t FLEXIO_I2C_MasterInit(FLEXIO_I2C_Type *base, flexio_i2c_master_config_t *masterConfig, uint32_t srcClock_Hz)
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{
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assert(base && masterConfig);
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flexio_shifter_config_t shifterConfig;
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flexio_timer_config_t timerConfig;
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uint32_t controlVal = 0;
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uint16_t timerDiv = 0;
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status_t result = kStatus_Success;
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memset(&shifterConfig, 0, sizeof(shifterConfig));
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memset(&timerConfig, 0, sizeof(timerConfig));
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Ungate flexio clock. */
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CLOCK_EnableClock(s_flexioClocks[FLEXIO_I2C_GetInstance(base)]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/* Do hardware configuration. */
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/* 1. Configure the shifter 0 for tx. */
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shifterConfig.timerSelect = base->timerIndex[1];
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnPositive;
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shifterConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
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shifterConfig.pinSelect = base->SDAPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveLow;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeTransmit;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitHigh;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitLow;
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[0], &shifterConfig);
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/* 2. Configure the shifter 1 for rx. */
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shifterConfig.timerSelect = base->timerIndex[1];
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shifterConfig.timerPolarity = kFLEXIO_ShifterTimerPolarityOnNegitive;
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shifterConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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shifterConfig.pinSelect = base->SDAPinIndex;
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shifterConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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shifterConfig.shifterMode = kFLEXIO_ShifterModeReceive;
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shifterConfig.inputSource = kFLEXIO_ShifterInputFromPin;
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shifterConfig.shifterStop = kFLEXIO_ShifterStopBitLow;
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shifterConfig.shifterStart = kFLEXIO_ShifterStartBitDisabledLoadDataOnEnable;
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FLEXIO_SetShifterConfig(base->flexioBase, base->shifterIndex[1], &shifterConfig);
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/*3. Configure the timer 0 for generating bit clock. */
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOpenDrainOrBidirection;
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timerConfig.pinSelect = base->SCLPinIndex;
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timerConfig.pinPolarity = kFLEXIO_PinActiveHigh;
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timerConfig.timerMode = kFLEXIO_TimerModeDual8BitBaudBit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputZeroNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnFlexIOClockShiftTimerOutput;
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timerConfig.timerReset = kFLEXIO_TimerResetOnTimerPinEqualToTimerOutput;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnTimerCompare;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnTriggerHigh;
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timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerDisable;
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timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
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/* Set TIMCMP[7:0] = (baud rate divider / 2) - 1. */
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timerDiv = (srcClock_Hz / masterConfig->baudRate_Bps) / 2 - 1;
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if (timerDiv > 0xFFU)
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{
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result = kStatus_InvalidArgument;
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return result;
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}
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timerConfig.timerCompare = timerDiv;
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FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[0], &timerConfig);
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/* 4. Configure the timer 1 for controlling shifters. */
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timerConfig.triggerSelect = FLEXIO_TIMER_TRIGGER_SEL_SHIFTnSTAT(base->shifterIndex[0]);
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timerConfig.triggerPolarity = kFLEXIO_TimerTriggerPolarityActiveLow;
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timerConfig.triggerSource = kFLEXIO_TimerTriggerSourceInternal;
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timerConfig.pinConfig = kFLEXIO_PinConfigOutputDisabled;
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timerConfig.pinSelect = base->SCLPinIndex;
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timerConfig.pinPolarity = kFLEXIO_PinActiveLow;
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timerConfig.timerMode = kFLEXIO_TimerModeSingle16Bit;
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timerConfig.timerOutput = kFLEXIO_TimerOutputOneNotAffectedByReset;
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timerConfig.timerDecrement = kFLEXIO_TimerDecSrcOnPinInputShiftPinInput;
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timerConfig.timerReset = kFLEXIO_TimerResetNever;
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timerConfig.timerDisable = kFLEXIO_TimerDisableOnPreTimerDisable;
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timerConfig.timerEnable = kFLEXIO_TimerEnableOnPrevTimerEnable;
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timerConfig.timerStop = kFLEXIO_TimerStopBitEnableOnTimerCompare;
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timerConfig.timerStart = kFLEXIO_TimerStartBitEnabled;
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/* Set TIMCMP[15:0] = (number of bits x 2) - 1. */
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timerConfig.timerCompare = 8 * 2 - 1;
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FLEXIO_SetTimerConfig(base->flexioBase, base->timerIndex[1], &timerConfig);
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/* Configure FLEXIO I2C Master. */
|
|
controlVal = base->flexioBase->CTRL;
|
|
controlVal &=
|
|
~(FLEXIO_CTRL_DOZEN_MASK | FLEXIO_CTRL_DBGE_MASK | FLEXIO_CTRL_FASTACC_MASK | FLEXIO_CTRL_FLEXEN_MASK);
|
|
controlVal |= (FLEXIO_CTRL_DBGE(masterConfig->enableInDebug) | FLEXIO_CTRL_FASTACC(masterConfig->enableFastAccess) |
|
|
FLEXIO_CTRL_FLEXEN(masterConfig->enableMaster));
|
|
if (!masterConfig->enableInDoze)
|
|
{
|
|
controlVal |= FLEXIO_CTRL_DOZEN_MASK;
|
|
}
|
|
|
|
base->flexioBase->CTRL = controlVal;
|
|
return result;
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterDeinit(FLEXIO_I2C_Type *base)
|
|
{
|
|
base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = 0;
|
|
base->flexioBase->SHIFTCTL[base->shifterIndex[0]] = 0;
|
|
base->flexioBase->SHIFTCFG[base->shifterIndex[1]] = 0;
|
|
base->flexioBase->SHIFTCTL[base->shifterIndex[1]] = 0;
|
|
base->flexioBase->TIMCFG[base->timerIndex[0]] = 0;
|
|
base->flexioBase->TIMCMP[base->timerIndex[0]] = 0;
|
|
base->flexioBase->TIMCTL[base->timerIndex[0]] = 0;
|
|
base->flexioBase->TIMCFG[base->timerIndex[1]] = 0;
|
|
base->flexioBase->TIMCMP[base->timerIndex[1]] = 0;
|
|
base->flexioBase->TIMCTL[base->timerIndex[1]] = 0;
|
|
/* Clear the shifter flag. */
|
|
base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[0]);
|
|
base->flexioBase->SHIFTSTAT = (1U << base->shifterIndex[1]);
|
|
/* Clear the timer flag. */
|
|
base->flexioBase->TIMSTAT = (1U << base->timerIndex[0]);
|
|
base->flexioBase->TIMSTAT = (1U << base->timerIndex[1]);
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterGetDefaultConfig(flexio_i2c_master_config_t *masterConfig)
|
|
{
|
|
assert(masterConfig);
|
|
|
|
masterConfig->enableMaster = true;
|
|
masterConfig->enableInDoze = false;
|
|
masterConfig->enableInDebug = true;
|
|
masterConfig->enableFastAccess = false;
|
|
|
|
/* Default baud rate at 100kbps. */
|
|
masterConfig->baudRate_Bps = 100000U;
|
|
}
|
|
|
|
uint32_t FLEXIO_I2C_MasterGetStatusFlags(FLEXIO_I2C_Type *base)
|
|
{
|
|
uint32_t status = 0;
|
|
|
|
status =
|
|
((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[0])) >> base->shifterIndex[0]);
|
|
status |=
|
|
(((FLEXIO_GetShifterStatusFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
|
|
<< 1U);
|
|
status |=
|
|
(((FLEXIO_GetShifterErrorFlags(base->flexioBase) & (1U << base->shifterIndex[1])) >> (base->shifterIndex[1]))
|
|
<< 2U);
|
|
|
|
return status;
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterClearStatusFlags(FLEXIO_I2C_Type *base, uint32_t mask)
|
|
{
|
|
if (mask & kFLEXIO_I2C_TxEmptyFlag)
|
|
{
|
|
FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[0]);
|
|
}
|
|
|
|
if (mask & kFLEXIO_I2C_RxFullFlag)
|
|
{
|
|
FLEXIO_ClearShifterStatusFlags(base->flexioBase, 1U << base->shifterIndex[1]);
|
|
}
|
|
|
|
if (mask & kFLEXIO_I2C_ReceiveNakFlag)
|
|
{
|
|
FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
|
|
}
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterEnableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
|
|
{
|
|
if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
|
|
{
|
|
FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
|
|
}
|
|
if (mask & kFLEXIO_I2C_RxFullInterruptEnable)
|
|
{
|
|
FLEXIO_EnableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
|
|
}
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterDisableInterrupts(FLEXIO_I2C_Type *base, uint32_t mask)
|
|
{
|
|
if (mask & kFLEXIO_I2C_TxEmptyInterruptEnable)
|
|
{
|
|
FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[0]);
|
|
}
|
|
if (mask & kFLEXIO_I2C_RxFullInterruptEnable)
|
|
{
|
|
FLEXIO_DisableShifterStatusInterrupts(base->flexioBase, 1U << base->shifterIndex[1]);
|
|
}
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterSetBaudRate(FLEXIO_I2C_Type *base, uint32_t baudRate_Bps, uint32_t srcClock_Hz)
|
|
{
|
|
uint16_t timerDiv = 0;
|
|
uint16_t timerCmp = 0;
|
|
FLEXIO_Type *flexioBase = base->flexioBase;
|
|
|
|
/* Set TIMCMP[7:0] = (baud rate divider / 2) - 1.*/
|
|
timerDiv = srcClock_Hz / baudRate_Bps;
|
|
timerDiv = timerDiv / 2 - 1U;
|
|
|
|
timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
|
|
timerCmp &= 0xFF00;
|
|
timerCmp |= timerDiv;
|
|
|
|
flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
|
|
}
|
|
|
|
status_t FLEXIO_I2C_MasterSetTransferCount(FLEXIO_I2C_Type *base, uint8_t count)
|
|
{
|
|
if (count > 14U)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
uint16_t timerCmp = 0;
|
|
uint32_t timerConfig = 0;
|
|
FLEXIO_Type *flexioBase = base->flexioBase;
|
|
|
|
timerCmp = flexioBase->TIMCMP[base->timerIndex[0]];
|
|
timerCmp &= 0x00FFU;
|
|
timerCmp |= (count * 18 + 1U) << 8U;
|
|
flexioBase->TIMCMP[base->timerIndex[0]] = timerCmp;
|
|
timerConfig = flexioBase->TIMCFG[base->timerIndex[0]];
|
|
timerConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
|
|
timerConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnTimerCompare);
|
|
flexioBase->TIMCFG[base->timerIndex[0]] = timerConfig;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterStart(FLEXIO_I2C_Type *base, uint8_t address, flexio_i2c_direction_t direction)
|
|
{
|
|
uint32_t data;
|
|
|
|
data = ((uint32_t)address) << 1U | ((direction == kFLEXIO_I2C_Read) ? 1U : 0U);
|
|
|
|
FLEXIO_I2C_MasterWriteByte(base, data);
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterRepeatedStart(FLEXIO_I2C_Type *base)
|
|
{
|
|
/* Prepare for RESTART condition, no stop.*/
|
|
FLEXIO_I2C_MasterWriteByte(base, 0xFFFFFFFFU);
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterStop(FLEXIO_I2C_Type *base)
|
|
{
|
|
/* Prepare normal stop. */
|
|
FLEXIO_I2C_MasterSetTransferCount(base, 0x0U);
|
|
FLEXIO_I2C_MasterWriteByte(base, 0x0U);
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterAbortStop(FLEXIO_I2C_Type *base)
|
|
{
|
|
uint32_t tmpConfig;
|
|
|
|
/* Prepare abort stop. */
|
|
tmpConfig = base->flexioBase->TIMCFG[base->timerIndex[0]];
|
|
tmpConfig &= ~FLEXIO_TIMCFG_TIMDIS_MASK;
|
|
tmpConfig |= FLEXIO_TIMCFG_TIMDIS(kFLEXIO_TimerDisableOnPinBothEdge);
|
|
base->flexioBase->TIMCFG[base->timerIndex[0]] = tmpConfig;
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterEnableAck(FLEXIO_I2C_Type *base, bool enable)
|
|
{
|
|
uint32_t tmpConfig = 0;
|
|
|
|
tmpConfig = base->flexioBase->SHIFTCFG[base->shifterIndex[0]];
|
|
tmpConfig &= ~FLEXIO_SHIFTCFG_SSTOP_MASK;
|
|
if (enable)
|
|
{
|
|
tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitLow);
|
|
}
|
|
else
|
|
{
|
|
tmpConfig |= FLEXIO_SHIFTCFG_SSTOP(kFLEXIO_ShifterStopBitHigh);
|
|
}
|
|
base->flexioBase->SHIFTCFG[base->shifterIndex[0]] = tmpConfig;
|
|
}
|
|
|
|
status_t FLEXIO_I2C_MasterWriteBlocking(FLEXIO_I2C_Type *base, const uint8_t *txBuff, uint8_t txSize)
|
|
{
|
|
assert(txBuff);
|
|
assert(txSize);
|
|
|
|
uint32_t status;
|
|
|
|
while (txSize--)
|
|
{
|
|
FLEXIO_I2C_MasterWriteByte(base, *txBuff++);
|
|
|
|
/* Wait until data transfer complete. */
|
|
while (!((status = FLEXIO_I2C_MasterGetStatusFlags(base)) & kFLEXIO_I2C_RxFullFlag))
|
|
{
|
|
}
|
|
|
|
if (status & kFLEXIO_I2C_ReceiveNakFlag)
|
|
{
|
|
FLEXIO_ClearShifterErrorFlags(base->flexioBase, 1U << base->shifterIndex[1]);
|
|
return kStatus_FLEXIO_I2C_Nak;
|
|
}
|
|
}
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterReadBlocking(FLEXIO_I2C_Type *base, uint8_t *rxBuff, uint8_t rxSize)
|
|
{
|
|
assert(rxBuff);
|
|
assert(rxSize);
|
|
|
|
while (rxSize--)
|
|
{
|
|
/* Wait until data transfer complete. */
|
|
while (!(FLEXIO_I2C_MasterGetStatusFlags(base) & kFLEXIO_I2C_RxFullFlag))
|
|
{
|
|
}
|
|
|
|
*rxBuff++ = FLEXIO_I2C_MasterReadByte(base);
|
|
}
|
|
}
|
|
|
|
status_t FLEXIO_I2C_MasterTransferBlocking(FLEXIO_I2C_Type *base, flexio_i2c_master_transfer_t *xfer)
|
|
{
|
|
assert(xfer);
|
|
|
|
flexio_i2c_master_handle_t tmpHandle;
|
|
uint32_t statusFlags;
|
|
uint32_t result = kStatus_Success;
|
|
|
|
/* Zero the handle. */
|
|
memset(&tmpHandle, 0, sizeof(tmpHandle));
|
|
|
|
/* Set up transfer machine. */
|
|
FLEXIO_I2C_MasterTransferInitStateMachine(base, &tmpHandle, xfer);
|
|
|
|
do
|
|
{
|
|
/* Wait either tx empty or rx full flag is asserted. */
|
|
while (!((statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base)) &
|
|
(kFLEXIO_I2C_TxEmptyFlag | kFLEXIO_I2C_RxFullFlag)))
|
|
{
|
|
}
|
|
|
|
result = FLEXIO_I2C_MasterTransferRunStateMachine(base, &tmpHandle, statusFlags);
|
|
|
|
} while ((tmpHandle.state != kFLEXIO_I2C_Idle) && (result == kStatus_Success));
|
|
|
|
return result;
|
|
}
|
|
|
|
status_t FLEXIO_I2C_MasterTransferCreateHandle(FLEXIO_I2C_Type *base,
|
|
flexio_i2c_master_handle_t *handle,
|
|
flexio_i2c_master_transfer_callback_t callback,
|
|
void *userData)
|
|
{
|
|
assert(handle);
|
|
|
|
IRQn_Type flexio_irqs[] = FLEXIO_IRQS;
|
|
|
|
/* Zero the handle. */
|
|
memset(handle, 0, sizeof(*handle));
|
|
|
|
/* Register callback and userData. */
|
|
handle->completionCallback = callback;
|
|
handle->userData = userData;
|
|
|
|
/* Enable interrupt in NVIC. */
|
|
EnableIRQ(flexio_irqs[FLEXIO_I2C_GetInstance(base)]);
|
|
|
|
/* Save the context in global variables to support the double weak mechanism. */
|
|
return FLEXIO_RegisterHandleIRQ(base, handle, FLEXIO_I2C_MasterTransferHandleIRQ);
|
|
}
|
|
|
|
status_t FLEXIO_I2C_MasterTransferNonBlocking(FLEXIO_I2C_Type *base,
|
|
flexio_i2c_master_handle_t *handle,
|
|
flexio_i2c_master_transfer_t *xfer)
|
|
{
|
|
assert(handle);
|
|
assert(xfer);
|
|
|
|
if (handle->state != kFLEXIO_I2C_Idle)
|
|
{
|
|
return kStatus_FLEXIO_I2C_Busy;
|
|
}
|
|
else
|
|
{
|
|
/* Set up transfer machine. */
|
|
FLEXIO_I2C_MasterTransferInitStateMachine(base, handle, xfer);
|
|
|
|
/* Enable both tx empty and rxfull interrupt. */
|
|
FLEXIO_I2C_MasterEnableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
|
|
|
|
return kStatus_Success;
|
|
}
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterTransferAbort(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle)
|
|
{
|
|
assert(handle);
|
|
|
|
/* Disable interrupts. */
|
|
FLEXIO_I2C_MasterDisableInterrupts(base, kFLEXIO_I2C_TxEmptyInterruptEnable | kFLEXIO_I2C_RxFullInterruptEnable);
|
|
|
|
/* Reset to idle state. */
|
|
handle->state = kFLEXIO_I2C_Idle;
|
|
}
|
|
|
|
status_t FLEXIO_I2C_MasterTransferGetCount(FLEXIO_I2C_Type *base, flexio_i2c_master_handle_t *handle, size_t *count)
|
|
{
|
|
if (!count)
|
|
{
|
|
return kStatus_InvalidArgument;
|
|
}
|
|
|
|
*count = handle->transferSize - handle->transfer.dataSize;
|
|
|
|
return kStatus_Success;
|
|
}
|
|
|
|
void FLEXIO_I2C_MasterTransferHandleIRQ(void *i2cType, void *i2cHandle)
|
|
{
|
|
FLEXIO_I2C_Type *base = (FLEXIO_I2C_Type *)i2cType;
|
|
flexio_i2c_master_handle_t *handle = (flexio_i2c_master_handle_t *)i2cHandle;
|
|
uint32_t statusFlags;
|
|
status_t result;
|
|
|
|
statusFlags = FLEXIO_I2C_MasterGetStatusFlags(base);
|
|
|
|
result = FLEXIO_I2C_MasterTransferRunStateMachine(base, handle, statusFlags);
|
|
|
|
if (handle->state == kFLEXIO_I2C_Idle)
|
|
{
|
|
FLEXIO_I2C_MasterTransferComplete(base, handle, result);
|
|
}
|
|
}
|