165 lines
7.5 KiB
C
165 lines
7.5 KiB
C
//*****************************************************************************
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//
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// am_reg_tpiu.h
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//! @file
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//!
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//! @brief Register macros for the TPIU module
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//
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//*****************************************************************************
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//*****************************************************************************
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//
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// Copyright (c) 2017, Ambiq Micro
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// All rights reserved.
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice,
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// this list of conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its
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// contributors may be used to endorse or promote products derived from this
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// software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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// AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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// IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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// ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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// LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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// CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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// SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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// INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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// CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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// ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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// POSSIBILITY OF SUCH DAMAGE.
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//
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// This is part of revision 1.2.9 of the AmbiqSuite Development Package.
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//
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//*****************************************************************************
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#ifndef AM_REG_TPIU_H
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#define AM_REG_TPIU_H
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//*****************************************************************************
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//
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// Instance finder. (1 instance(s) available)
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//
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//*****************************************************************************
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#define AM_REG_TPIU_NUM_MODULES 1
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#define AM_REG_TPIUn(n) \
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(REG_TPIU_BASEADDR + 0x00000000 * n)
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//*****************************************************************************
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//
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// Register offsets.
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//
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//*****************************************************************************
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#define AM_REG_TPIU_SSPSR_O 0xE0040000
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#define AM_REG_TPIU_CSPSR_O 0xE0040004
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#define AM_REG_TPIU_ACPR_O 0xE0040010
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#define AM_REG_TPIU_SPPR_O 0xE00400F0
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#define AM_REG_TPIU_FFCR_O 0xE0040304
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#define AM_REG_TPIU_ITCTRL_O 0xE0040F00
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#define AM_REG_TPIU_TYPE_O 0xE0040FC8
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//*****************************************************************************
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//
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// TPIU_SSPSR - Supported Parallel Port Sizes.
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//
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//*****************************************************************************
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// Parallel Port Width 1 supported
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#define AM_REG_TPIU_SSPSR_SWIDTH0_S 0
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#define AM_REG_TPIU_SSPSR_SWIDTH0_M 0x00000001
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#define AM_REG_TPIU_SSPSR_SWIDTH0(n) (((uint32_t)(n) << 0) & 0x00000001)
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//*****************************************************************************
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//
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// TPIU_CSPSR - Current Parallel Port Size.
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//
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//*****************************************************************************
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// One-hot representation of the current port width.
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#define AM_REG_TPIU_CSPSR_CWIDTH_S 0
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#define AM_REG_TPIU_CSPSR_CWIDTH_M 0xFFFFFFFF
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#define AM_REG_TPIU_CSPSR_CWIDTH(n) (((uint32_t)(n) << 0) & 0xFFFFFFFF)
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#define AM_REG_TPIU_CSPSR_CWIDTH_1BIT 0x00000001
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//*****************************************************************************
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//
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// TPIU_ACPR - Asynchronous Clock Prescaler.
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//
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//*****************************************************************************
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// Prescaler value for the baudrate of SWO.
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#define AM_REG_TPIU_ACPR_SWOSCALER_S 0
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#define AM_REG_TPIU_ACPR_SWOSCALER_M 0x0000FFFF
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#define AM_REG_TPIU_ACPR_SWOSCALER(n) (((uint32_t)(n) << 0) & 0x0000FFFF)
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#define AM_REG_TPIU_ACPR_SWOSCALER_115200 0x00000033
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//*****************************************************************************
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//
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// TPIU_SPPR - Selected Pin Protocol.
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//
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//*****************************************************************************
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// Selects the protocol used for trace output.
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#define AM_REG_TPIU_SPPR_TXMODE_S 0
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#define AM_REG_TPIU_SPPR_TXMODE_M 0x00000003
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#define AM_REG_TPIU_SPPR_TXMODE(n) (((uint32_t)(n) << 0) & 0x00000003)
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#define AM_REG_TPIU_SPPR_TXMODE_PARALLEL 0x00000000
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#define AM_REG_TPIU_SPPR_TXMODE_MANCHESTER 0x00000001
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#define AM_REG_TPIU_SPPR_TXMODE_NRZ 0x00000002
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#define AM_REG_TPIU_SPPR_TXMODE_UART 0x00000002
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//*****************************************************************************
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//
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// TPIU_FFCR - Formatter and Flush Control Register.
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//
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//*****************************************************************************
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// Enable continuous formatting.
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#define AM_REG_TPIU_FFCR_ENFCONT_S 1
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#define AM_REG_TPIU_FFCR_ENFCONT_M 0x00000002
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#define AM_REG_TPIU_FFCR_ENFCONT(n) (((uint32_t)(n) << 1) & 0x00000002)
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//*****************************************************************************
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//
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// TPIU_ITCTRL - Specifies normal or integration mode for the TPIU.
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//
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//*****************************************************************************
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// Specifies the current mode for the TPIU.
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#define AM_REG_TPIU_ITCTRL_MODE_S 0
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#define AM_REG_TPIU_ITCTRL_MODE_M 0x00000003
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#define AM_REG_TPIU_ITCTRL_MODE(n) (((uint32_t)(n) << 0) & 0x00000003)
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#define AM_REG_TPIU_ITCTRL_MODE_NORMAL 0x00000000
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#define AM_REG_TPIU_ITCTRL_MODE_TEST 0x00000001
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#define AM_REG_TPIU_ITCTRL_MODE_DATA_TEST 0x00000002
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//*****************************************************************************
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//
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// TPIU_TYPE - TPIU Type.
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//
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//*****************************************************************************
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// 1 Indicates UART/NRZ support.
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#define AM_REG_TPIU_TYPE_NRZVALID_S 11
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#define AM_REG_TPIU_TYPE_NRZVALID_M 0x00000800
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#define AM_REG_TPIU_TYPE_NRZVALID(n) (((uint32_t)(n) << 11) & 0x00000800)
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// 1 Indicates Manchester support.
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#define AM_REG_TPIU_TYPE_MANCVALID_S 10
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#define AM_REG_TPIU_TYPE_MANCVALID_M 0x00000400
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#define AM_REG_TPIU_TYPE_MANCVALID(n) (((uint32_t)(n) << 10) & 0x00000400)
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// 0 Indicates Parallel Trace support.
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#define AM_REG_TPIU_TYPE_PTINVALID_S 9
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#define AM_REG_TPIU_TYPE_PTINVALID_M 0x00000200
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#define AM_REG_TPIU_TYPE_PTINVALID(n) (((uint32_t)(n) << 9) & 0x00000200)
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// FIFO Size reported as a power of two. For instance, 0x3 indicates a FIFO size
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// of 8 bytes.
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#define AM_REG_TPIU_TYPE_FIFOSZ_S 6
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#define AM_REG_TPIU_TYPE_FIFOSZ_M 0x000001C0
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#define AM_REG_TPIU_TYPE_FIFOSZ(n) (((uint32_t)(n) << 6) & 0x000001C0)
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#endif // AM_REG_TPIU_H
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