266 lines
19 KiB
C
266 lines
19 KiB
C
/*!
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\file gd32f4xx.h
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\brief general definitions for GD32F4xx
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*/
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/*
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Copyright (C) 2016 GigaDevice
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2016-08-15, V1.0.0, firmware update for GD32F4xx
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*/
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#ifndef GD32F4XX_H
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#define GD32F4XX_H
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#ifdef cplusplus
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extern "C" {
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#endif
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/* define GD32F4xx */
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#if !defined (GD32F4xx)
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#define GD32F4xx
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#endif /* define GD32F4xx */
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#if !defined (GD32F4xx)
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#error "Please select the target GD32F4xx device used in your application (in gd32f4xx.h file)"
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#endif /* undefine GD32F4xx tip */
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/* define value of high speed crystal oscillator (HXTAL) in Hz */
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#if !defined (HXTAL_VALUE)
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#define HXTAL_VALUE ((uint32_t)25000000)
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#endif /* high speed crystal oscillator value */
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/* define startup timeout value of high speed crystal oscillator (HXTAL) */
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#if !defined (HXTAL_STARTUP_TIMEOUT)
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#define HXTAL_STARTUP_TIMEOUT ((uint16_t)0x0800)
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#endif /* high speed crystal oscillator startup timeout */
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/* define value of internal 16MHz RC oscillator (IRC16M) in Hz */
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#if !defined (IRC16M_VALUE)
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#define IRC16M_VALUE ((uint32_t)16000000)
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#endif /* internal 16MHz RC oscillator value */
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/* define startup timeout value of internal 16MHz RC oscillator (IRC16M) */
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#if !defined (IRC16M_STARTUP_TIMEOUT)
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#define IRC16M_STARTUP_TIMEOUT ((uint16_t)0x0500)
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#endif /* internal 16MHz RC oscillator startup timeout */
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/* define value of internal 32KHz RC oscillator(IRC32K) in Hz */
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#if !defined (IRC32K_VALUE)
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#define IRC32K_VALUE ((uint32_t)32000)
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#endif /* internal 32KHz RC oscillator value */
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/* define value of low speed crystal oscillator (LXTAL)in Hz */
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#if !defined (LXTAL_VALUE)
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#define LXTAL_VALUE ((uint32_t)32768)
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#endif /* low speed crystal oscillator value */
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/* I2S external clock in selection */
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//#define I2S_EXTERNAL_CLOCK_IN (uint32_t)12288000U
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/* GD32F4xx firmware library version number V1.0 */
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#define __GD32F4xx_STDPERIPH_VERSION_MAIN (0x03) /*!< [31:24] main version */
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#define __GD32F4xx_STDPERIPH_VERSION_SUB1 (0x00) /*!< [23:16] sub1 version */
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#define __GD32F4xx_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
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#define __GD32F4xx_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
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#define __GD32F4xx_STDPERIPH_VERSION ((__GD32F4xx_STDPERIPH_VERSION_MAIN << 24)\
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|(__GD32F4xx_STDPERIPH_VERSION_SUB1 << 16)\
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|(__GD32F4xx_STDPERIPH_VERSION_SUB2 << 8)\
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|(__GD32F4xx_STDPERIPH_VERSION_RC))
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/* configuration of the Cortex-M4 processor and core peripherals */
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#define __CM4_REV 0x0001 /*!< Core revision r0p1 */
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#define __MPU_PRESENT 1 /*!< GD32F4xx do not provide MPU */
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#define __NVIC_PRIO_BITS 4 /*!< GD32F4xx uses 4 bits for the priority levels */
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#define __VENDOR_SYSTICKCONFIG 0 /*!< set to 1 if different sysTick config is used */
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#define __FPU_PRESENT 1 /*!< FPU present */
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/* define interrupt number */
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typedef enum IRQn
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{
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/* Cortex-M4 processor exceptions numbers */
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NonMaskableInt_IRQn = -14, /*!< 2 non maskable interrupt */
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MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 memory management interrupt */
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BusFault_IRQn = -11, /*!< 5 Cortex-M4 bus fault interrupt */
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UsageFault_IRQn = -10, /*!< 6 Cortex-M4 usage fault interrupt */
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SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV call interrupt */
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DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 debug monitor interrupt */
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PendSV_IRQn = -2, /*!< 14 Cortex-M4 pend SV interrupt */
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SysTick_IRQn = -1, /*!< 15 Cortex-M4 system tick interrupt */
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/* interruput numbers */
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WWDGT_IRQn = 0, /*!< window watchDog timer interrupt */
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LVD_IRQn = 1, /*!< LVD through EXTI line detect interrupt */
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TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp through EXTI Line detect */
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RTC_WKUP_IRQn = 3, /*!< RTC Wakeup through EXTI line interrupt */
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FMC_IRQn = 4, /*!< FMC interrupt */
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RCU_CTC_IRQn = 5, /*!< RCU and CTC interrupt */
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EXTI0_IRQn = 6, /*!< EXTI line 0 interrupts */
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EXTI1_IRQn = 7, /*!< EXTI line 1 interrupts */
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EXTI2_IRQn = 8, /*!< EXTI line 2 interrupts */
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EXTI3_IRQn = 9, /*!< EXTI line 3 interrupts */
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EXTI4_IRQn = 10, /*!< EXTI line 4 interrupts */
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DMA0_Channel0_IRQn = 11, /*!< DMA0 Channel0 Interrupt */
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DMA0_Channel1_IRQn = 12, /*!< DMA0 Channel1 Interrupt */
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DMA0_Channel2_IRQn = 13, /*!< DMA0 Channel2 Interrupt */
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DMA0_Channel3_IRQn = 14, /*!< DMA0 Channel3 Interrupt */
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DMA0_Channel4_IRQn = 15, /*!< DMA0 Channel4 Interrupt */
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DMA0_Channel5_IRQn = 16, /*!< DMA0 Channel5 Interrupt */
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DMA0_Channel6_IRQn = 17, /*!< DMA0 Channel6 Interrupt */
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ADC_IRQn = 18, /*!< ADC interrupt */
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CAN0_TX_IRQn = 19, /*!< CAN0 TX interrupts */
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CAN0_RX0_IRQn = 20, /*!< CAN0 RX0 interrupts */
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CAN0_RX1_IRQn = 21, /*!< CAN0 RX1 interrupts */
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CAN0_EWMC_IRQn = 22, /*!< CAN0 EWMC interrupts */
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EXTI5_9_IRQn = 23, /*!< EXTI[9:5] interrupts */
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TIMER0_BRK_TIMER8_IRQn = 24, /*!< TIMER0 Break and TIMER8 interrupts */
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TIMER0_UP_TIMER9_IRQn = 25, /*!< TIMER0 Update and TIMER9 interrupts */
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TIMER0_TRG_CMT_TIMER10_IRQn = 26, /*!< TIMER0 Trigger and Commutation and TIMER10 interrupts */
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TIMER0_CC_IRQn = 27, /*!< TIMER0 Capture Compare interrupts */
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TIMER1_IRQn = 28, /*!< TIMER1 interrupt */
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TIMER2_IRQn = 29, /*!< TIMER2 interrupt */
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TIMER3_IRQn = 30, /*!< TIMER3 interrupts */
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I2C0_EV_IRQn = 31, /*!< I2C0 event interrupt */
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I2C0_ER_IRQn = 32, /*!< I2C0 error interrupt */
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I2C1_EV_IRQn = 33, /*!< I2C1 event interrupt */
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I2C1_ER_IRQn = 34, /*!< I2C1 error interrupt */
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SPI0_IRQn = 35, /*!< SPI0 interrupt */
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SPI1_IRQn = 36, /*!< SPI1 interrupt */
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USART0_IRQn = 37, /*!< USART0 interrupt */
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USART1_IRQn = 38, /*!< USART1 interrupt */
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USART2_IRQn = 39, /*!< USART2 interrupt */
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EXTI10_15_IRQn = 40, /*!< EXTI[15:10] interrupts */
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RTC_Alarm_IRQn = 41, /*!< RTC Alarm interrupt */
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USBFS_WKUP_IRQn = 42, /*!< USBFS Wakeup interrupt */
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TIMER7_BRK_TIMER11_IRQn = 43, /*!< TIMER7 Break and TIMER11 interrupts */
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TIMER7_UP_TIMER12_IRQn = 44, /*!< TIMER7 Update and TIMER12 interrupts */
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TIMER7_TRG_CMT_TIMER13_IRQn = 45, /*!< TIMER7 Trigger and Commutation and TIMER13 interrupts */
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TIMER7_CC_IRQn = 46, /*!< TIMER7 Capture Compare interrupts */
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DMA0_Channel7_IRQn = 47, /*!< DMA0 Channel7 Interrupt */
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EXMC_IRQn = 48, /*!< EXMC Interrupt */
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SDIO_IRQn = 49, /*!< SDIO Interrupt */
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TIMER4_IRQn = 50, /*!< TIMER4 Interrupt */
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SPI2_IRQn = 51, /*!< SPI2 Interrupt */
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UART3_IRQn = 52, /*!< UART3 Interrupt */
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UART4_IRQn = 53, /*!< UART4 Interrupt */
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TIMER5_DAC_IRQn = 54, /*!< TIMER5 and DAC0 DAC1 Underrun error Interrupt */
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TIMER6_IRQn = 55, /*!< TIMER6 Interrupt */
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DMA1_Channel0_IRQn = 56, /*!< DMA1 Channel0 Interrupt */
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DMA1_Channel1_IRQn = 57, /*!< DMA1 Channel1 Interrupt */
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DMA1_Channel2_IRQn = 58, /*!< DMA1 Channel2 Interrupt */
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DMA1_Channel3_IRQn = 59, /*!< DMA1 Channel3 Interrupt */
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DMA1_Channel4_IRQn = 60, /*!< DMA1 Channel4 Interrupt */
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ENET_IRQn = 61, /*!< Ethernet Interrupt */
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ENET_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI Line Interrupt */
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CAN1_TX_IRQn = 63, /*!< CAN1 TX Interrupt */
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CAN1_RX0_IRQn = 64, /*!< CAN1 RX0 Interrupt */
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CAN1_RX1_IRQn = 65, /*!< CAN1 RX1 Interrupt */
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CAN1_EWMC_IRQn = 66, /*!< CAN1 EWMC Interrupt */
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USBFS_IRQn = 67, /*!< USBFS Interrupt */
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DMA1_Channel5_IRQn = 68, /*!< DMA1 Channel5 Interrupt */
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DMA1_Channel6_IRQn = 69, /*!< DMA1 Channel6 Interrupt */
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DMA1_Channel7_IRQn = 70, /*!< DMA1 Channel7 Interrupt */
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USART5_IRQn = 71, /*!< USART5 Interrupt */
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I2C2_EV_IRQn = 72, /*!< I2C2 Event Interrupt */
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I2C2_ER_IRQn = 73, /*!< I2C2 Error Interrupt */
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USBHS_EP1_Out_IRQn = 74, /*!< USBHS Endpoint 1 Out Interrupt */
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USBHS_EP1_In_IRQn = 75, /*!< USBHS Endpoint 1 in Interrupt */
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USBHS_WKUP_IRQn = 76, /*!< USBHS Wakeup through EXTI Line Interrupt */
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USBHS_IRQn = 77, /*!< USBHS Interrupt */
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DCI_IRQn = 78, /*!< DCI Interrupt */
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TRNG_IRQn = 80, /*!< TRNG Interrupt */
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FPU_IRQn = 81, /*!< FPU Interrupt */
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UART6_IRQn = 82, /*!< UART6 Interrupt */
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UART7_IRQn = 83, /*!< UART7 Interrupt */
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SPI3_IRQn = 84, /*!< SPI3 Interrupt */
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SPI4_IRQn = 85, /*!< SPI4 Interrupt */
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SPI5_IRQn = 86, /*!< SPI5 Interrupt */
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TLI_IRQn = 88, /*!< TLI Interrupt */
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TLI_ER_IRQn = 89, /*!< TLI Error Interrupt */
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IPA_IRQn = 90, /*!< IPA Interrupt */
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} IRQn_Type;
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/* includes */
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#include "core_cm4.h"
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#include "system_gd32f4xx.h"
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#include <stdint.h>
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/* enum definitions */
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typedef enum {DISABLE = 0, ENABLE = !DISABLE} EventStatus, ControlStatus;
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typedef enum {FALSE = 0, TRUE = !FALSE} bool;
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typedef enum {RESET = 0, SET = !RESET} FlagStatus;
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typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrStatus;
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/* bit operations */
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#define REG32(addr) (*(volatile uint32_t *)(uint32_t)(addr))
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#define REG16(addr) (*(volatile uint16_t *)(uint32_t)(addr))
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#define REG8(addr) (*(volatile uint8_t *)(uint32_t)(addr))
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#define BIT(x) ((uint32_t)((uint32_t)0x01U<<(x)))
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#define BITS(start, end) ((0xFFFFFFFFUL << (start)) & (0xFFFFFFFFUL >> (31U - (uint32_t)(end))))
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#define GET_BITS(regval, start, end) (((regval) & BITS((start),(end))) >> (start))
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/* main flash and SRAM memory map */
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#define FLASH_BASE ((uint32_t)0x08000000U) /*!< main FLASH base address */
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#define TCMSRAM_BASE ((uint32_t)0x10000000U) /*!< TCMSRAM(64KB) base address */
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#define OPTION_BASE ((uint32_t)0x1FFEC000U) /*!< Option bytes base address */
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#define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM0 base address */
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/* peripheral memory map */
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#define APB1_BUS_BASE ((uint32_t)0x40000000U) /*!< apb1 base address */
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#define APB2_BUS_BASE ((uint32_t)0x40010000U) /*!< apb2 base address */
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#define AHB1_BUS_BASE ((uint32_t)0x40020000U) /*!< ahb1 base address */
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#define AHB2_BUS_BASE ((uint32_t)0x50000000U) /*!< ahb2 base address */
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/* EXMC memory map */
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#define EXMC_BASE ((uint32_t)0xA0000000U) /*!< EXMC register base address */
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/* advanced peripheral bus 1 memory map */
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#define TIMER_BASE (APB1_BUS_BASE + 0x00000000U) /*!< TIMER base address */
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#define RTC_BASE (APB1_BUS_BASE + 0x00002800U) /*!< RTC base address */
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#define WWDGT_BASE (APB1_BUS_BASE + 0x00002C00U) /*!< WWDGT base address */
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#define FWDGT_BASE (APB1_BUS_BASE + 0x00003000U) /*!< FWDGT base address */
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#define I2S_ADD_BASE (APB1_BUS_BASE + 0x00003400U) /*!< I2S1_add base address */
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#define SPI_BASE (APB1_BUS_BASE + 0x00003800U) /*!< SPI base address */
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#define USART_BASE (APB1_BUS_BASE + 0x00004400U) /*!< USART base address */
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#define I2C_BASE (APB1_BUS_BASE + 0x00005400U) /*!< I2C base address */
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#define CAN_BASE (APB1_BUS_BASE + 0x00006400U) /*!< CAN base address */
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#define CTC_BASE (APB1_BUS_BASE + 0x00006C00U) /*!< CTC base address */
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#define PMU_BASE (APB1_BUS_BASE + 0x00007000U) /*!< PMU base address */
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#define DAC_BASE (APB1_BUS_BASE + 0x00007400U) /*!< DAC base address */
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#define IREF_BASE (APB1_BUS_BASE + 0x0000C400U) /*!< IREF base address */
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/* advanced peripheral bus 2 memory map */
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#define TLI_BASE (APB2_BUS_BASE + 0x00006800U) /*!< TLI base address */
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#define SYSCFG_BASE (APB2_BUS_BASE + 0x00003800U) /*!< SYSCFG base address */
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#define EXTI_BASE (APB2_BUS_BASE + 0x00003C00U) /*!< EXTI base address */
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#define SDIO_BASE (APB2_BUS_BASE + 0x00002C00U) /*!< SDIO base address */
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#define ADC_BASE (APB2_BUS_BASE + 0x00002000U) /*!< ADC base address */
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/* advanced high performance bus 1 memory map */
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#define GPIO_BASE (AHB1_BUS_BASE + 0x00000000U) /*!< GPIO base address */
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#define CRC_BASE (AHB1_BUS_BASE + 0x00003000U) /*!< CRC base address */
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#define RCU_BASE (AHB1_BUS_BASE + 0x00003800U) /*!< RCU base address */
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#define FMC_BASE (AHB1_BUS_BASE + 0x00003C00U) /*!< FMC base address */
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#define BKPSRAM_BASE (AHB1_BUS_BASE + 0x00004000U) /*!< BKPSRAM base address */
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#define DMA_BASE (AHB1_BUS_BASE + 0x00006000U) /*!< DMA base address */
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#define ENET_BASE (AHB1_BUS_BASE + 0x00008000U) /*!< ENET base address */
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#define IPA_BASE (AHB1_BUS_BASE + 0x0000B000U) /*!< IPA base address */
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#define USBHS_BASE (AHB1_BUS_BASE + 0x00020000U) /*!< USBHS base address */
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/* advanced high performance bus 2 memory map */
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#define USBFS_BASE (AHB2_BUS_BASE + 0x00000000U) /*!< USBFS base address */
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#define DCI_BASE (AHB2_BUS_BASE + 0x00050000U) /*!< DCI base address */
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#define TRNG_BASE (AHB2_BUS_BASE + 0x00060800U) /*!< TRNG base address */
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/* option byte and debug memory map */
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#define OB_BASE ((uint32_t)0x1FFEC000U) /*!< OB base address */
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#define DBG_BASE ((uint32_t)0xE0042000U) /*!< DBG base address */
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/* define marco USE_STDPERIPH_DRIVER */
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#if !defined USE_STDPERIPH_DRIVER
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#define USE_STDPERIPH_DRIVER
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#endif
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#ifdef USE_STDPERIPH_DRIVER
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#include "gd32f4xx_libopt.h"
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#endif /* USE_STDPERIPH_DRIVER */
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#ifdef cplusplus
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}
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#endif
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#endif
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