244 lines
7.5 KiB
C
244 lines
7.5 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fxhci_cmd.c
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* Date: 2022-02-11 13:33:12
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* LastEditTime: 2022-02-18 09:11:23
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* Description: This files is for implementation of XHCI command
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 Zhugengyu 2022/2/7 init commit
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*/
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#include "fdebug.h"
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#include "fxhci_private.h"
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#define FUSB_DEBUG_TAG "FXHCI_CMD"
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#define FUSB_ERROR(format, ...) FT_DEBUG_PRINT_E(FUSB_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FUSB_WARN(format, ...) FT_DEBUG_PRINT_W(FUSB_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FUSB_INFO(format, ...) FT_DEBUG_PRINT_I(FUSB_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FUSB_DEBUG(format, ...) FT_DEBUG_PRINT_D(FUSB_DEBUG_TAG, format, ##__VA_ARGS__)
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FXhciTrb *FXhciNextCmdTrb(FXhci *const xhci)
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{
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FXhciClearTrb(xhci->cr.cur, xhci->cr.pcs);
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return xhci->cr.cur;
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}
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void FXhciPostCmd(FXhci *const xhci)
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{
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FUSB_INFO("Command %d (@%p) ", FXHCI_TRB_GET(TT, xhci->cr.cur), xhci->cr.cur);
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FXHCI_TRB_SET(C, xhci->cr.cur, xhci->cr.pcs); /* Cycle Bit */
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++xhci->cr.cur;
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/* pass command trb to hardware */
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WMB();
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/* Ring the doorbell */
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FXhciWriteDb32(&xhci->mmio, FXHCI_REG_DB_HOST_CONTROLLER, FXHCI_REG_DB_TARGET_HC_COMMAND);
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while (FXHCI_TRB_GET(TT, xhci->cr.cur) == FXHCI_TRB_LINK)
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{
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FUSB_DEBUG("Handling LINK pointer (@%p) ", xhci->cr.cur);
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const int tc = FXHCI_TRB_GET(TC, xhci->cr.cur); /* Completion Code */
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FXHCI_TRB_SET(C, xhci->cr.cur, xhci->cr.pcs); /* Cycle Bit */
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xhci->cr.cur = (void *)(uintptr)(xhci->cr.cur->ptr_low);
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if (tc)
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xhci->cr.pcs ^= 1;
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}
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}
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static FXhciTransCode FXhciWaitForCmd(FXhci *const xhci,
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const FXhciTrb *const cmd_trb,
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const int clear_event)
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{
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FXhciTransCode cc;
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u64 reg_val64;
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cc = FXhciWaitForCmdDone(xhci, cmd_trb, clear_event);
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if (cc != FXHCI_CC_TIMEOUT)
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return cc;
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/* Abort command on timeout */
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FUSB_ERROR("Aborting command (@%p), CRCR: 0x%x ", cmd_trb, FXhciReadOper64(&xhci->mmio, FXHCI_REG_OP_CRCR));
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/*
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* Ref. xHCI Specification Revision 1.2, May 2019.
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* Section 5.4.5, Table 5-24.
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*
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* Abort the command and stop the ring.
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*/
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reg_val64 = FXhciReadOper64(&xhci->mmio, FXHCI_REG_OP_CRCR);
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reg_val64 |= FXHCI_REG_OP_CRCR_CA;
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FXhciWriteOper64(&xhci->mmio, FXHCI_REG_OP_CRCR, reg_val64);
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cc = FXhciWaitForCmdAborted(xhci, cmd_trb);
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if ((FXhciReadOper64(&xhci->mmio, FXHCI_REG_OP_CRCR) & FXHCI_REG_OP_CRCR_CRR))
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FUSB_ERROR("xhci_wait_for_command: Command ring still running");
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return cc;
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}
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FXhciTransCode FXhciCmdNop(FXhci *const xhci)
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{
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FXhciTrb *const cmd = FXhciNextCmdTrb(xhci);
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FXHCI_TRB_SET(TT, cmd, FXHCI_TRB_CMD_NOOP); /* TRB Type */
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FXhciPostCmd(xhci);
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/* wait for result in event ring */
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FXhciTransCode cc = FXhciWaitForCmdDone(xhci, cmd, 1);
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FUSB_INFO("Command ring is %srunning: cc: %d",
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(FXhciReadOper64(&xhci->mmio, FXHCI_REG_OP_CRCR) & FXHCI_REG_OP_CRCR_CRR) ? "" : "not ", /* check if cmd ring is running */
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cc);
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if (cc != FXHCI_CC_SUCCESS)
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FUSB_ERROR("noop command failed. ");
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return cc;
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}
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/*
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* xhci_cmd_* return >= 0: xhci completion code (cc)
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* < 0: driver error code
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*/
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FXhciTransCode FXhciCmdEnableSlot(FXhci *const xhci, int *const slot_id)
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{
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FXhciTrb *const cmd = FXhciNextCmdTrb(xhci);
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FXHCI_TRB_SET(TT, cmd, FXHCI_TRB_CMD_ENABLE_SLOT); /* TRB Type */
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FXhciPostCmd(xhci);
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FXhciTransCode cc = FXhciWaitForCmd(xhci, cmd, 0);
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if (cc >= 0)
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{
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if (cc == FXHCI_CC_SUCCESS)
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{
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*slot_id = FXHCI_TRB_GET(ID, xhci->er.cur);
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if (*slot_id > xhci->max_slots_en)
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cc = FXHCI_CC_CONTROLLER_ERROR;
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}
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FXhciAdvanceEvtRing(xhci);
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FXhciHandleEvts(xhci);
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}
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return cc;
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}
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FXhciTransCode FXhciCmdDisableSlot(FXhci *const xhci, const int slot_id)
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{
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FXhciTrb *const cmd = FXhciNextCmdTrb(xhci);
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FXHCI_TRB_SET(TT, cmd, FXHCI_TRB_CMD_DISABLE_SLOT); /* TRB Type */
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FXHCI_TRB_SET(ID, cmd, slot_id); /* Slot ID */
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FXhciPostCmd(xhci);
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return FXhciWaitForCmd(xhci, cmd, 1);
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}
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FXhciTransCode FXhciCmdAddressDevice(FXhci *const xhci,
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const int slot_id,
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FXhciInputCtx *const ic)
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{
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FXhciTrb *const cmd = FXhciNextCmdTrb(xhci);
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FXHCI_TRB_SET(TT, cmd, FXHCI_TRB_CMD_ADDRESS_DEV); /* TRB Type */
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FXHCI_TRB_SET(ID, cmd, slot_id); /* Slot ID */
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cmd->ptr_low = (uintptr)(ic->raw);
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FXhciPostCmd(xhci);
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return FXhciWaitForCmd(xhci, cmd, 1);
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}
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FXhciTransCode FXhciCmdConfigureEp(FXhci *const xhci,
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const int slot_id,
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const int config_id,
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FXhciInputCtx *const ic)
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{
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FXhciTrb *const cmd = FXhciNextCmdTrb(xhci);
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FXHCI_TRB_SET(TT, cmd, FXHCI_TRB_CMD_CONFIGURE_EP); /* TRB Type */
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FXHCI_TRB_SET(ID, cmd, slot_id); /* Slot ID */
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cmd->ptr_low = (uintptr)(ic->raw);
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if (config_id == 0)
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FXHCI_TRB_SET(DC, cmd, 1); /* Deconfigure */
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FXhciPostCmd(xhci);
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return FXhciWaitForCmd(xhci, cmd, 1);
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}
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FXhciTransCode FXhciCmdEvaluateCtx(FXhci *const xhci,
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const int slot_id,
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FXhciInputCtx *const ic)
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{
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FXhciTrb *const cmd = FXhciNextCmdTrb(xhci);
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FXHCI_TRB_SET(TT, cmd, FXHCI_TRB_CMD_EVAL_CTX); /* TRB Type */
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FXHCI_TRB_SET(ID, cmd, slot_id); /* Slot ID */
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cmd->ptr_low = (uintptr)(ic->raw);
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FXhciPostCmd(xhci);
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return FXhciWaitForCmd(xhci, cmd, 1);
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}
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FXhciTransCode FXhciCmdResetEp(FXhci *const xhci, const int slot_id, const int ep)
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{
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FXhciTrb *const cmd = FXhciNextCmdTrb(xhci);
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FXHCI_TRB_SET(TT, cmd, FXHCI_TRB_CMD_RESET_EP); /* TRB Type */
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FXHCI_TRB_SET(ID, cmd, slot_id); /* Slot ID */
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FXHCI_TRB_SET(EP, cmd, ep); /* Endpoint ID */
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FXhciPostCmd(xhci);
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return FXhciWaitForCmd(xhci, cmd, 1);
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}
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FXhciTransCode FXhciCmdStopEp(FXhci *const xhci, const int slot_id, const int ep)
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{
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FXhciTrb *const cmd = FXhciNextCmdTrb(xhci);
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FXHCI_TRB_SET(TT, cmd, FXHCI_TRB_CMD_STOP_EP); /* TRB Type */
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FXHCI_TRB_SET(ID, cmd, slot_id); /* Slot ID */
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FXHCI_TRB_SET(EP, cmd, ep); /* Endpoint ID */
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FXhciPostCmd(xhci);
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return FXhciWaitForCmd(xhci, cmd, 1);
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}
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FXhciTransCode FXhciCmdSetTrDq(FXhci *const xhci, const int slot_id, const int ep,
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FXhciTrb *const dq_trb, const int dcs)
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{
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FXhciTrb *const cmd = FXhciNextCmdTrb(xhci);
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FXHCI_TRB_SET(TT, cmd, FXHCI_TRB_CMD_SET_TR_DQ); /* TRB Type */
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FXHCI_TRB_SET(ID, cmd, slot_id); /* Slot ID */
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FXHCI_TRB_SET(EP, cmd, ep); /* Endpoint ID */
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cmd->ptr_low = (uintptr)(dq_trb) | dcs;
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FXhciPostCmd(xhci);
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return FXhciWaitForCmd(xhci, cmd, 1);
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}
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