77 lines
2.6 KiB
C
77 lines
2.6 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fpcie_dma.h
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* Date: 2022-02-10 14:55:11
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* LastEditTime: 2022-02-18 08:57:51
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* Description: This files is for
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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*/
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#ifndef DRIVERS_FPCIE_DMA_H
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#define DRIVERS_FPCIE_DMA_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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#include "ftypes.h"
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/***************************** Include Files *********************************/
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/************************** Constant Definitions *****************************/
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/************************** Variable Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define DMA_XFER_START (0x01 << 0)
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#define DMA_READ (0x00 << 1)
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#define DMA_WRITE (0x01 << 1)
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#define DMA_CHANNEL_READ_DONE (0x01 << 0)
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#define DMA_CHANNEL_WRITE_DONE (0x01 << 1)
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#define DMA_CHANNEL_READ_ERROR (0x01 << 8)
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#define DMA_CHANNEL_WRITE_ERROR (0x01 << 9)
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#define DMA_CHANNEL_READ_DONE_ENABLE (0x01 << 0)
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#define DMA_CHANNEL_WRITE_DONE_ENABLE (0x01 << 1)
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#define DMA_CHANNEL_READ_ERROR_ENABLE (0x01 << 8)
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#define DMA_CHANNEL_WRITE_ERROR_ENABLE (0x01 << 9)
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/************************** Function Prototypes ******************************/
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/**************************** Type Definitions *******************************/
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struct FPcieDmaDescriptor
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{
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volatile u64 axi_base_address; /* 0x00 */
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volatile u32 axi_address_phase_controls; /* 0x08 */
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volatile u64 pcie_base_address; /* 0x12 */
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volatile u64 pcie_tlp_header_attributes; /* 0x20 */
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volatile u32 transfer_control; /* 0x28 */
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volatile u8 axi_bus_status; /* 0x32 */
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volatile u8 pcie_bus_status; /* 0x33 */
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volatile u8 channel_status; /* 0x34 */
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volatile u8 reserve; /* 0x35 */
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volatile u64 next_descriptor; /* 0x36 */
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} __attribute__((packed)) __attribute__((aligned(128)));
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#ifdef __cplusplus
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}
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#endif
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#endif // !
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