223 lines
8.6 KiB
C
223 lines
8.6 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fddma_hw.h
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 08:24:52
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* Description: This files is for register definition
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 Zhugengyu 2022/5/13 init commit
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*/
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#ifndef DRIVERS_FDDMA_HW_H
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#define DRIVERS_FDDMA_HW_H
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/***************************** Include Files *********************************/
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#include "fassert.h"
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#include "ftypes.h"
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#include "fio.h"
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#include "fkernel.h"
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/************************** Constant Definitions *****************************/
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/** @name Register Map
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*
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* Register offsets from the base address of an GPIO device.
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* @{
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*/
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#define FDDMA_CTL_OFFSET 0x0 /* 全局控制类寄存器 */
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#define FDDMA_CHAN_0_3_CFG_OFFSET 0x4 /* DMA通道0~3选择配置寄存器 */
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#define FDDMA_STA_OFFSET 0x8 /* 中断状态寄存器 */
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#define FDDMA_MASK_INTR_OFFSET 0xC /* 中断掩码寄存器 */
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/* AXI读写相关的配置硬件暂未开放 */
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#define FDDMA_UP_AXI_AW_CFG_OFFSET 0x10 /* 上行AXI写通道配置寄存器 */
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#define FDDMA_UP_AXI_AR_CFG_OFFSET 0x14 /* 上行AXI读通道配置寄存器 */
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#define FDDMA_DOWN_AXI_AW_CFG_OFFSET 0x18 /* 下行AXI写通道配置寄存器 */
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#define FDDMA_DOWN_AXI_AR_CFG_OFFSET 0x1C /* 下行AXI读通道配置寄存器 */
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#define FDDMA_CHAN_BIND_OFFSET 0x20 /* DMA通道绑定寄存器 */
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#define FDDMA_GCAP_OFFSET 0x24 /* DMA通道数寄存器（只读） */
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#define FDDMA_CHAN_4_7_CFG_OFFSET 0x28 /* DMA通道4~7选择配置寄存器 */
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#define FDDMA_CHAN_OFFSET(chan) (0x40 * (chan))
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#define FDDMA_CHAN_DDR_UP_ADDR_OFFSET(chan) (0x40 + FDDMA_CHAN_OFFSET(chan)) /* 内存中源/目的地址高32位 */
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#define FDDMA_CHAN_DDR_LOW_ADDR_OFFSET(chan) (0x44 + FDDMA_CHAN_OFFSET(chan)) /* 内存中源/目的地址低32位 */
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#define FDDMA_CHAN_DEV_ADDR_OFFSET(chan) (0x48 + FDDMA_CHAN_OFFSET(chan)) /* 设备中源/目的地址32位 */
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#define FDDMA_CHAN_TS_OFFSET(chan) (0x4C + FDDMA_CHAN_OFFSET(chan)) /* 需要传输的总数据字节数 */
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#define FDDMA_CHAN_CRT_UP_ADDR_OFFSET(chan) (0x50 + FDDMA_CHAN_OFFSET(chan)) /* 当前内存需要读写数据的高32位 */
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#define FDDMA_CHAN_CRT_LOW_ADDR_OFFSET(chan) (0x54 + FDDMA_CHAN_OFFSET(chan)) /* 当前内存需要读写数据的低32位 */
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#define FDDMA_CHAN_CTL_OFFSET(chan) (0x58 + FDDMA_CHAN_OFFSET(chan)) /* 通道控制寄存器 */
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#define FDDMA_CHAN_STS_OFFSET(chan) (0x5C + FDDMA_CHAN_OFFSET(chan)) /* 通道状态寄存器 */
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#define FDDMA_CHAN_TIMEOUT_CNT_OFFSET(chan) (0x60 + FDDMA_CHAN_OFFSET(chan)) /* 超时等待阈值 */
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/** @name FDDMA_CTL_OFFSET Register
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*/
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#define FDDMA_CTL_SRST BIT(1) /* 1: 全局软复位 */
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#define FDDMA_CTL_ENABLE BIT(0) /* 1: 全局使能控制 */
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/** @name FDDMA_CHAN_0_3_CFG_OFFSET Register
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*/
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#define FDDMA_CHAN_0_3_SEL_EN(chan) BIT((chan) * 8 + 7) /* 1: 通道chan信号源选择有效 */
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#define FDDMA_CHAN_0_3_SEL(chan, sel) ((sel) << ((chan) * 8)) /* 通道chan信号源选择sel项 */
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#define FDDMA_CHAN_0_3_SEL_MASK(chan) (GENMASK(7, 0) << ((chan) * 8))
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/** @name FDDMA_STA_OFFSET Register
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*/
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#define FDDMA_STA_CHAN_REQ_DONE(chan) BIT((chan) * 4) /* 通道chan的block请求完成时置1，写1后清0 */
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/** @name FDDMA_MASK_INTR_OFFSET Register
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*/
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#define FDDMA_MASK_EN_GLOBAL_INTR BIT(31) /* 全局中断使能输出控制位 */
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#define FDDMA_MASK_EN_CHAN_INTR(chan) BIT(chan) /* 通道chan的中断输出控制位 */
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/** @name FDDMA_CHAN_BIND_OFFSET Register
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*/
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#define FDDMA_CHAN_BIND(chan) BIT(chan) /* 1: 通道已绑定了外设DMA请求信号线 */
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/** @name FDDMA_CHAN_4_7_CFG_OFFSET Register
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*/
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#define FDDMA_CHAN_4_7_SEL_EN(chan) BIT(((chan) - 4) * 8 + 7) /* 1: 通道chan信号源选择有效 */
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#define FDDMA_CHAN_4_7_SEL(chan, sel) ((sel) << (((chan) - 4) * 8)) /* 通道chan信号源选择sel项 */
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#define FDDMA_CHAN_4_7_SEL_MASK(chan) (GENMASK(7, 0) << (((chan) - 4) * 8))
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/** @name FDDMA_CHAN_CTL_OFFSET Register
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*/
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#define FDDMA_CHAN_CTL_RX_MODE BIT(2) /* 1：接收外设 dma_rx_req, 0：接收外设 dma_tx_req */
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#define FDDMA_CHAN_CTL_SRST BIT(1) /* 1: 复位通道 */
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#define FDDMA_CHAN_CTL_EN BIT(0) /* 1: 使能通道 */
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/** @name FDDMA_CHAN_STS_OFFSET Register
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*/
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#define FDDMA_CHAN_STS_FIFO_EMPTY BIT(1) /* 1: FIFO空状态 */
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#define FDDMA_CHAN_STS_FIFO_FULL BIT(0) /* 1: FIFO满状态 */
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/** @name FDDMA_CHAN_TIMEOUT_CNT_OFFSET Register
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*/
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#define FDDMA_CHAN_TIMEOUT_EN BIT(32) /* 1: 使能超时机制 */
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#define FDDMA_CHAN_TIMEOUT_CNT_SET(cnt) SET_REG32_BITS((cnt), 27, 0) /* 超时阈值 */
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#define FDDMA_CHAN_TIMEOUT_CNT_MASK GENMASK(27, 0)
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/**************************** Type Definitions *******************************/
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/************************** Variable Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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/**
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* @name: FDdmaReadReg
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* @msg: 读DDMA寄存器
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* @return {u32} 获取的寄存器值
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* @param {uintptr} base_addr, DDMA寄存器基地址
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* @param {u32} reg_off, DDMA寄存器偏移量
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*/
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static inline u32 FDdmaReadReg(uintptr base_addr, u32 reg_off)
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{
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return FtIn32(base_addr + reg_off);
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}
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/**
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* @name: FDdmaWriteReg
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* @msg: 写DDMA寄存器
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* @return {无}
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* @param {uintptr} base_addr, DDMA寄存器基地址
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* @param {u32} reg_off, DDMA寄存器偏移量
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* @param {u32} reg_val, 设置的寄存器值
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*/
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static inline void FDdmaWriteReg(uintptr base_addr, u32 reg_off, u32 reg_val)
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{
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FtOut32(base_addr + reg_off, reg_val);
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return;
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}
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/**
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* @name: FDdmaReadStatus
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* @msg: 获取DDMA中断状态
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* @return {u32} 中断状态
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* @param {uintptr} base_addr, DDMA寄存器基地址
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*/
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static inline u32 FDdmaReadStatus(uintptr base_addr)
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{
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return FDdmaReadReg(base_addr, FDDMA_STA_OFFSET);
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}
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/**
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* @name: FDdmaReadChanStatus
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* @msg: 获取DDMA通道中断状态
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* @return {u32} 中断状态
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* @param {uintptr} base_addr, DDMA寄存器基地址
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* @param {u32} chan, DDMA通道号
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*/
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static inline u32 FDdmaReadChanStatus(uintptr base_addr, u32 chan)
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{
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return FDdmaReadReg(base_addr, FDDMA_CHAN_STS_OFFSET(chan));
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}
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/************************** Function Prototypes ******************************/
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/* 复位DDMA控制器 */
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void FDdmaSoftwareReset(uintptr base_addr);
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/* 去使能DDMA控制器 */
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void FDdmaDisable(uintptr base_addr);
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/* 使能DDMA控制器 */
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void FDdmaEnable(uintptr base_addr);
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/* 重置DDMA通道 */
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void FDdmaResetChan(uintptr base_addr, u32 chan);
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/* 去使能DDMA通道 */
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FError FDdmaDisableChan(uintptr base_addr, u32 chan);
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/* 使能DDMA通道 */
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void FDdmaEnableChan(uintptr base_addr, u32 chan);
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/* 关闭DDMA全局中断 */
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void FDdmaDisableGlobalIrq(uintptr base_addr);
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/* 打开DDMA全局中断 */
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void FDdmaEnableGlobalIrq(uintptr base_addr);
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/* 关闭DDMA通道中断 */
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void FDdmaDisableChanIrq(uintptr base_addr, u32 chan);
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/* 打开DDMA通道中断 */
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void FDdmaEnableChanIrq(uintptr base_addr, u32 chan);
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/* 清除DDMA通道中断状态 */
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void FDdmaClearChanIrq(uintptr base_addr, u32 chan);
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/* 检查通道是否在工作中 */
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boolean FDdmaIsChanRunning(uintptr base_addr, u32 chan);
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/* 将DDMA通道与外设绑定 */
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void FDdmaSetChanSelection(uintptr base_addr, u32 chan, u32 slave_id);
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/* 修改通道的绑定状态 */
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void FDdmaSetChanBind(uintptr base_addr, u32 chan, boolean bind);
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/* 设置通道的方向 */
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void FDdmaSetChanDirection(uintptr base_addr, u32 chan, boolean is_rx);
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/* 设置通道超时 */
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void FDdmaSetChanTimeout(uintptr base_addr, u32 chan, u32 timeout);
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#ifdef __cplusplus
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}
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#endif
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#endif |