841 lines
23 KiB
C
841 lines
23 KiB
C
/*
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* Copyright (c) 2019-2025 Allwinner Technology Co., Ltd. ALL rights reserved.
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*
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* Allwinner is a trademark of Allwinner Technology Co.,Ltd., registered in
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* the the people's Republic of China and other countries.
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* All Allwinner Technology Co.,Ltd. trademarks are used with permission.
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*
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* DISCLAIMER
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* THIRD PARTY LICENCES MAY BE REQUIRED TO IMPLEMENT THE SOLUTION/PRODUCT.
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* IF YOU NEED TO INTEGRATE THIRD PARTY’S TECHNOLOGY (SONY, DTS, DOLBY, AVS OR MPEGLA, ETC.)
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* IN ALLWINNERS’SDK OR PRODUCTS, YOU SHALL BE SOLELY RESPONSIBLE TO OBTAIN
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* ALL APPROPRIATELY REQUIRED THIRD PARTY LICENCES.
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* ALLWINNER SHALL HAVE NO WARRANTY, INDEMNITY OR OTHER OBLIGATIONS WITH RESPECT TO MATTERS
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* COVERED UNDER ANY REQUIRED THIRD PARTY LICENSE.
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* YOU ARE SOLELY RESPONSIBLE FOR YOUR USAGE OF THIRD PARTY’S TECHNOLOGY.
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*
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*
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* THIS SOFTWARE IS PROVIDED BY ALLWINNER"AS IS" AND TO THE MAXIMUM EXTENT
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* PERMITTED BY LAW, ALLWINNER EXPRESSLY DISCLAIMS ALL WARRANTIES OF ANY KIND,
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* WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING WITHOUT LIMITATION REGARDING
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* THE TITLE, NON-INFRINGEMENT, ACCURACY, CONDITION, COMPLETENESS, PERFORMANCE
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* OR MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
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* IN NO EVENT SHALL ALLWINNER BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS, OR BUSINESS INTERRUPTION)
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* HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
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* STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED
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* OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <string.h>
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#include <stdint.h>
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#include <stdlib.h>
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#include <stdio.h>
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#include <hal_reset.h>
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#include <hal_cache.h>
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#include <hal_mem.h>
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#include <hal_atomic.h>
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#include <hal_clk.h>
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#include <hal_interrupt.h>
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#include <interrupt.h>
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#include <sunxi_hal_common.h>
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#include <hal_dma.h>
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#define DMA_ERR(fmt, arg...) printf("%s()%d " fmt, __func__, __LINE__, ##arg)
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static struct sunxi_dma_chan dma_chan_source[NR_MAX_CHAN];
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static hal_spinlock_t dma_lock;
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/*
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* Fix sconfig's bus width according to at_dmac.
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* 1 byte -> 0, 2 bytes -> 1, 4 bytes -> 2, 8bytes -> 3
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*/
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static inline uint32_t convert_buswidth(enum dma_slave_buswidth addr_width)
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{
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if (addr_width > DMA_SLAVE_BUSWIDTH_8_BYTES)
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{
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return 0;
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}
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switch (addr_width)
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{
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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return 1;
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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return 2;
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case DMA_SLAVE_BUSWIDTH_8_BYTES:
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return 3;
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default:
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/* For 1 byte width or fallback */
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return 0;
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}
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}
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static inline void convert_burst(uint32_t *maxburst)
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{
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switch (*maxburst)
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{
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case 1:
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*maxburst = 0;
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break;
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case 4:
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*maxburst = 1;
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break;
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case 8:
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*maxburst = 2;
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break;
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case 16:
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*maxburst = 3;
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break;
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default:
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printf("unknown maxburst\n");
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*maxburst = 0;
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break;
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}
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}
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static inline void sunxi_cfg_lli(struct sunxi_dma_lli *lli, uint32_t src_addr,
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uint32_t dst_addr, uint32_t len,
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struct dma_slave_config *config)
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{
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uint32_t src_width = 0, dst_width = 0;
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if (NULL == lli && NULL == config)
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{
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return;
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}
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src_width = convert_buswidth(config->src_addr_width);
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dst_width = convert_buswidth(config->dst_addr_width);
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lli->cfg = SRC_BURST(config->src_maxburst) | \
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SRC_WIDTH(src_width) | \
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DST_BURST(config->dst_maxburst) | \
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DST_WIDTH(dst_width);
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lli->src = src_addr;
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lli->dst = dst_addr;
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lli->len = len;
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lli->para = NORMAL_WAIT;
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}
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static void sunxi_dump_lli(struct sunxi_dma_chan *chan, struct sunxi_dma_lli *lli)
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{
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#ifdef DMA_DEBUG
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printf("channum:%x\n"
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"\t\tdesc:desc - 0x%08x desc p - 0x%08x desc v - 0x%08x\n"
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"\t\tlli: v- 0x%08x v_lln - 0x%08x s - 0x%08x d - 0x%08x\n"
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"\t\tlen - 0x%08x para - 0x%08x p_lln - 0x%08x\n",
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chan->chan_count,
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(uint32_t)chan->desc, (uint32_t)chan->desc->p_lln, (uint32_t)chan->desc->vlln,
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(uint32_t)lli, (uint32_t)lli->vlln, (uint32_t)lli->src,
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(uint32_t)lli->dst, (uint32_t)lli->len, (uint32_t)lli->para, (uint32_t)lli->p_lln);
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#endif
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}
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static void sunxi_dump_com_regs(void)
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{
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#ifdef DMA_DEBUG
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printf("Common register:\n"
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"\tmask0: 0x%08x\n"
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"\tmask1: 0x%08x\n"
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"\tpend0: 0x%08x\n"
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"\tpend1: 0x%08x\n"
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#ifdef DMA_SECURE
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"\tsecur: 0x%08x\n"
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#endif
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#ifdef DMA_GATE
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"\t_gate: 0x%08x\n"
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#endif
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"\tstats: 0x%08x\n",
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(uint32_t)hal_readl(DMA_IRQ_EN(0)),
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(uint32_t)hal_readl(DMA_IRQ_EN(1)),
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(uint32_t)hal_readl(DMA_IRQ_STAT(0)),
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(uint32_t)hal_readl(DMA_IRQ_STAT(1)),
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#ifdef DMA_SECURE
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(uint32_t)hal_readl(DMA_SECURE),
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#endif
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#ifdef DMA_GATE
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(uint32_t)hal_readl(DMA_GATE),
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#endif
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(uint32_t)hal_readl(DMA_STAT));
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#endif
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}
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static inline void sunxi_dump_chan_regs(struct sunxi_dma_chan *ch)
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{
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#ifdef DMA_DEBUG
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u32 chan_num = ch->chan_count;
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printf("Chan %d reg:\n"
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"\t___en: \t0x%08x\n"
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"\tpause: \t0x%08x\n"
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"\tstart: \t0x%08x\n"
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"\t__cfg: \t0x%08x\n"
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"\t__src: \t0x%08x\n"
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"\t__dst: \t0x%08x\n"
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"\tcount: \t0x%08x\n"
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"\t_para: \t0x%08x\n\n",
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chan_num,
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(uint32_t)hal_readl(DMA_ENABLE(chan_num)),
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(uint32_t)hal_readl(DMA_PAUSE(chan_num)),
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(uint32_t)hal_readl(DMA_LLI_ADDR(chan_num)),
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(uint32_t)hal_readl(DMA_CFG(chan_num)),
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(uint32_t)hal_readl(DMA_CUR_SRC(chan_num)),
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(uint32_t)hal_readl(DMA_CUR_DST(chan_num)),
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(uint32_t)hal_readl(DMA_CNT(chan_num)),
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(uint32_t)hal_readl(DMA_PARA(chan_num)));
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#endif
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}
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static void *sunxi_lli_list(struct sunxi_dma_lli *prev, struct sunxi_dma_lli *next,
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struct sunxi_dma_chan *chan)
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{
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if ((!prev && !chan) || !next)
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{
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return NULL;
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}
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if (!prev)
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{
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chan->desc = next;
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chan->desc->p_lln = __va_to_pa((unsigned long)next);
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chan->desc->vlln = next;
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}
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else
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{
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prev->p_lln = __va_to_pa((unsigned long)next);
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prev->vlln = next;
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}
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next->p_lln = LINK_END;
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next->vlln = NULL;
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return next;
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}
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static irqreturn_t sunxi_dma_irq_handle(int irq, void *ptr)
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{
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uint32_t status_l = 0, status_h = 0;
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int i = 0;
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status_l = hal_readl(DMA_IRQ_STAT(0));
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#if NR_MAX_CHAN + START_CHAN_OFFSET > HIGH_CHAN
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status_h = hal_readl(DMA_IRQ_STAT(1));
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#endif
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hal_writel(status_l, DMA_IRQ_STAT(0));
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#if NR_MAX_CHAN + START_CHAN_OFFSET > HIGH_CHAN
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hal_writel(status_h, DMA_IRQ_STAT(1));
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#endif
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for (i = 0; i < NR_MAX_CHAN; i++)
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{
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uint32_t __cpsr;
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struct sunxi_dma_chan *chan = &dma_chan_source[i];
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__cpsr = hal_spin_lock_irqsave(&dma_lock);
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uint32_t chan_num = chan->chan_count;
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uint32_t status = 0;
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if (chan->used == 0)
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{
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hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
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continue;
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}
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status = (chan_num + START_CHAN_OFFSET >= HIGH_CHAN) \
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? (status_h >> ((chan_num + START_CHAN_OFFSET - HIGH_CHAN) << 2)) \
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: (status_l >> ((chan_num + START_CHAN_OFFSET) << 2));
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if (!(chan->irq_type & status))
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{
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goto unlock;
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}
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if (chan->cyclic)
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{
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dma_callback cb = NULL;
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void *cb_data = NULL;
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chan->periods_pos ++;
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if (chan->periods_pos * chan->desc->len >= chan->buf_len)
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{
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chan->periods_pos = 0;
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}
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cb = chan->callback;
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cb_data = chan->callback_param;
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hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
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if (cb)
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{
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cb(cb_data);
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}
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__cpsr = hal_spin_lock_irqsave(&dma_lock);
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}
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else
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{
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dma_callback cb = NULL;
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void *cb_data = NULL;
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cb = chan->callback;
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cb_data = chan->callback_param;
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hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
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if (cb)
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{
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cb(cb_data);
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}
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__cpsr = hal_spin_lock_irqsave(&dma_lock);
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}
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unlock:
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hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
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}
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return 0;
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}
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static int sunxi_dma_clk_init(bool enable)
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{
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hal_clk_status_t ret;
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hal_reset_type_t reset_type = HAL_SUNXI_RESET;
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u32 reset_id;
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hal_clk_type_t clk_type = HAL_SUNXI_CCU;
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hal_clk_id_t clk_id;
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hal_clk_t clk;
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struct reset_control *reset;
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clk_id = SUNXI_CLK_DMA;
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reset_id = SUNXI_RST_DMA;
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if (enable)
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{
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reset = hal_reset_control_get(reset_type, reset_id);
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hal_reset_control_deassert(reset);
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hal_reset_control_put(reset);
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hal_clock_enable(hal_clock_get(clk_type, SUNXI_CLK_MBUS_DMA));
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clk = hal_clock_get(clk_type, clk_id);
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ret = hal_clock_enable(clk);
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if (ret != HAL_CLK_STATUS_OK)
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DMA_ERR("DMA clock enable failed.\n");
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}
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else
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{
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clk = hal_clock_get(clk_type, clk_id);
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ret = hal_clock_disable(clk);
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if (ret != HAL_CLK_STATUS_OK)
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DMA_ERR("DMA clock disable failed.\n");
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hal_clock_disable(hal_clock_get(clk_type, SUNXI_CLK_MBUS_DMA));
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hal_clock_put(clk);
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}
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return ret;
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}
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void sunxi_dma_free_ill(struct sunxi_dma_chan *chan)
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{
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struct sunxi_dma_lli *li_adr = NULL, *next = NULL;
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if (NULL == chan)
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{
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DMA_ERR("[dma] chan is NULL\n");
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return ;
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}
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li_adr = chan->desc;
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chan->desc = NULL;
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while (li_adr)
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{
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next = li_adr->vlln;
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dma_free_coherent(li_adr);
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li_adr = next;
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}
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chan->callback = NULL;
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chan->callback_param = NULL;
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}
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hal_dma_chan_status_t hal_dma_chan_request(struct sunxi_dma_chan **dma_chan)
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{
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int i = 0;
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struct sunxi_dma_chan *chan;
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uint32_t __cpsr;
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for (i = 0; i < NR_MAX_CHAN; i++)
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{
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__cpsr = hal_spin_lock_irqsave(&dma_lock);
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chan = &dma_chan_source[i];
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if (chan->used == 0)
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{
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chan->used = 1;
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chan->chan_count = i;
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hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
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*dma_chan = &dma_chan_source[i];
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return HAL_DMA_CHAN_STATUS_FREE;
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}
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hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
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}
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return HAL_DMA_CHAN_STATUS_BUSY;
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}
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hal_dma_status_t hal_dma_prep_memcpy(struct sunxi_dma_chan *chan,
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uint32_t dest, uint32_t src, uint32_t len)
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{
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struct sunxi_dma_lli *l_item = NULL;
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struct dma_slave_config *config = NULL;
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uint32_t __cpsr;
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if ((NULL == chan) || (dest == 0 || src == 0))
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{
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DMA_ERR("[dma] chan is NULL\n");
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return HAL_DMA_STATUS_INVALID_PARAMETER;
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}
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__cpsr = hal_spin_lock_irqsave(&dma_lock);
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l_item = (struct sunxi_dma_lli *)dma_alloc_coherent(sizeof(struct sunxi_dma_lli));
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if (!l_item)
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{
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hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
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return HAL_DMA_STATUS_NO_MEM;
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}
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memset(l_item, 0, sizeof(struct sunxi_dma_lli));
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config = &chan->cfg;
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dest = __va_to_pa(dest);
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src = __va_to_pa(src);
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sunxi_cfg_lli(l_item, src, dest, len, config);
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l_item->cfg |= SRC_DRQ(DRQSRC_SDRAM) \
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| DST_DRQ(DRQDST_SDRAM) \
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| DST_LINEAR_MODE \
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| SRC_LINEAR_MODE;
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sunxi_lli_list(NULL, l_item, chan);
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sunxi_dump_lli(chan, l_item);
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hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
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return HAL_DMA_STATUS_OK;
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}
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hal_dma_status_t hal_dma_prep_device(struct sunxi_dma_chan *chan,
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uint32_t dest, uint32_t src,
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uint32_t len, enum dma_transfer_direction dir)
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{
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struct sunxi_dma_lli *l_item = NULL;
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struct dma_slave_config *config = NULL;
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uint32_t __cpsr;
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if ((NULL == chan) || (dest == 0 || src == 0))
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{
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DMA_ERR("[dma] chan is NULL\n");
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return HAL_DMA_STATUS_INVALID_PARAMETER;
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}
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l_item = (struct sunxi_dma_lli *)dma_alloc_coherent(sizeof(struct sunxi_dma_lli));
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if (!l_item)
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{
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return HAL_DMA_STATUS_NO_MEM;
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}
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memset(l_item, 0, sizeof(struct sunxi_dma_lli));
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__cpsr = hal_spin_lock_irqsave(&dma_lock);
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config = &chan->cfg;
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if (dir == DMA_MEM_TO_DEV)
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{
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src = __va_to_pa(src);
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sunxi_cfg_lli(l_item, src, dest, len, config);
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l_item->cfg |= GET_DST_DRQ(config->slave_id) \
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| SRC_LINEAR_MODE \
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| DST_IO_MODE \
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| SRC_DRQ(DRQSRC_SDRAM);
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}
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else if (dir == DMA_DEV_TO_MEM)
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{
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dest = __va_to_pa(dest);
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sunxi_cfg_lli(l_item, src, dest, len, config);
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l_item ->cfg |= GET_SRC_DRQ(config->slave_id) \
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| DST_LINEAR_MODE \
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| SRC_IO_MODE \
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| DST_DRQ(DRQSRC_SDRAM);
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}
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else if (dir == DMA_DEV_TO_DEV)
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{
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sunxi_cfg_lli(l_item, src, dest, len, config);
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l_item->cfg |= GET_SRC_DRQ(config->slave_id) \
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| DST_IO_MODE \
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| SRC_IO_MODE \
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| GET_DST_DRQ(config->slave_id);
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}
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sunxi_lli_list(NULL, l_item, chan);
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sunxi_dump_lli(chan, l_item);
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hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
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return HAL_DMA_STATUS_OK;
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}
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hal_dma_status_t hal_dma_prep_cyclic(struct sunxi_dma_chan *chan,
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uint32_t buf_addr, uint32_t buf_len,
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uint32_t period_len, enum dma_transfer_direction dir)
|
||
{
|
||
struct sunxi_dma_lli *l_item = NULL, *prev = NULL;
|
||
uint32_t periods = buf_len / period_len;
|
||
struct dma_slave_config *config = NULL;
|
||
uint32_t i = 0;
|
||
uint32_t __cpsr;
|
||
|
||
if ((NULL == chan && chan->cyclic) || (0 == buf_addr))
|
||
{
|
||
DMA_ERR("[dma] chan or buf_addr is NULL\n");
|
||
return HAL_DMA_STATUS_INVALID_PARAMETER;
|
||
}
|
||
|
||
__cpsr = hal_spin_lock_irqsave(&dma_lock);
|
||
|
||
if (chan->desc) {
|
||
struct sunxi_dma_lli *li_adr = NULL, *next = NULL;
|
||
|
||
li_adr = chan->desc;
|
||
chan->desc = NULL;
|
||
|
||
while (li_adr)
|
||
{
|
||
next = li_adr->vlln;
|
||
dma_free_coherent(li_adr);
|
||
li_adr = next;
|
||
}
|
||
}
|
||
|
||
config = &chan->cfg;
|
||
for (i = 0; i < periods; i++)
|
||
{
|
||
hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
|
||
l_item = (struct sunxi_dma_lli *)dma_alloc_coherent(sizeof(struct sunxi_dma_lli));
|
||
if (!l_item)
|
||
{
|
||
return HAL_DMA_STATUS_NO_MEM;
|
||
}
|
||
__cpsr = hal_spin_lock_irqsave(&dma_lock);
|
||
memset(l_item, 0, sizeof(struct sunxi_dma_lli));
|
||
if (dir == DMA_MEM_TO_DEV)
|
||
{
|
||
sunxi_cfg_lli(l_item, __va_to_pa(buf_addr + period_len * i),
|
||
config->dst_addr, period_len, config);
|
||
l_item->cfg |= GET_DST_DRQ(config->slave_id) \
|
||
| SRC_LINEAR_MODE \
|
||
| DST_IO_MODE \
|
||
| SRC_DRQ(DRQSRC_SDRAM);
|
||
}
|
||
else if (dir == DMA_DEV_TO_MEM)
|
||
{
|
||
sunxi_cfg_lli(l_item, config->src_addr, \
|
||
__va_to_pa(buf_addr + period_len * i), \
|
||
period_len, config);
|
||
l_item ->cfg |= GET_SRC_DRQ(config->slave_id) \
|
||
| DST_LINEAR_MODE \
|
||
| SRC_IO_MODE \
|
||
| DST_DRQ(DRQSRC_SDRAM);
|
||
}
|
||
else if (dir == DMA_DEV_TO_DEV)
|
||
{
|
||
sunxi_cfg_lli(l_item, config->src_addr, \
|
||
config->dst_addr, period_len, config);
|
||
l_item->cfg |= GET_SRC_DRQ(config->slave_id) \
|
||
| DST_IO_MODE \
|
||
| SRC_IO_MODE \
|
||
| GET_DST_DRQ(config->slave_id);
|
||
|
||
}
|
||
prev = sunxi_lli_list(prev, l_item, chan);
|
||
}
|
||
prev->p_lln = __va_to_pa((unsigned long)chan->desc);
|
||
chan->cyclic = true;
|
||
#ifdef DMA_DEBUG
|
||
for (prev = chan->desc; prev != NULL; prev = prev->vlln)
|
||
{
|
||
sunxi_dump_lli(chan, prev);
|
||
}
|
||
#endif
|
||
hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
|
||
|
||
return HAL_DMA_STATUS_OK;
|
||
}
|
||
|
||
hal_dma_status_t hal_dma_callback_install(struct sunxi_dma_chan *chan,
|
||
dma_callback callback,
|
||
void *callback_param)
|
||
{
|
||
if (NULL == chan)
|
||
{
|
||
DMA_ERR("[dma] chan is NULL\n");
|
||
return HAL_DMA_STATUS_INVALID_PARAMETER;
|
||
}
|
||
|
||
if (NULL == callback)
|
||
{
|
||
DMA_ERR("[dma] callback is NULL\n");
|
||
return HAL_DMA_STATUS_INVALID_PARAMETER;
|
||
}
|
||
|
||
if (NULL == callback_param)
|
||
{
|
||
DMA_ERR("[dma] callback_param is NULL\n");
|
||
return HAL_DMA_STATUS_INVALID_PARAMETER;
|
||
}
|
||
|
||
chan->callback = callback;
|
||
chan->callback_param = callback_param;
|
||
|
||
return HAL_DMA_STATUS_OK;
|
||
}
|
||
|
||
hal_dma_status_t hal_dma_slave_config(struct sunxi_dma_chan *chan,
|
||
struct dma_slave_config *config)
|
||
{
|
||
uint32_t __cpsr;
|
||
|
||
if (NULL == config || NULL == chan)
|
||
{
|
||
DMA_ERR("[dma] dma config is NULL\n");
|
||
return HAL_DMA_STATUS_INVALID_PARAMETER;
|
||
}
|
||
|
||
__cpsr = hal_spin_lock_irqsave(&dma_lock);
|
||
convert_burst(&config->src_maxburst);
|
||
convert_burst(&config->dst_maxburst);
|
||
memcpy((void *) & (chan->cfg), (void *)config, sizeof(struct dma_slave_config));
|
||
hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
|
||
|
||
return HAL_DMA_STATUS_OK;
|
||
}
|
||
|
||
enum dma_status hal_dma_tx_status(struct sunxi_dma_chan *chan, uint32_t *left_size)
|
||
{
|
||
uint32_t i = 0;
|
||
struct sunxi_dma_lli *l_item = NULL;
|
||
enum dma_status status = DMA_INVALID_PARAMETER;
|
||
uint32_t __cpsr;
|
||
|
||
if (NULL == chan || NULL == left_size)
|
||
{
|
||
DMA_ERR("[dma] chan or left_size is NULL\n");
|
||
return HAL_DMA_STATUS_INVALID_PARAMETER;
|
||
}
|
||
|
||
__cpsr = hal_spin_lock_irqsave(&dma_lock);
|
||
if (chan->cyclic)
|
||
{
|
||
for (i = 0, l_item = chan->desc; i <= chan->periods_pos; i++, l_item = l_item->vlln)
|
||
{
|
||
if (NULL == l_item)
|
||
{
|
||
*left_size = 0;
|
||
status = DMA_COMPLETE;
|
||
goto unlock;
|
||
}
|
||
}
|
||
if (NULL == l_item)
|
||
{
|
||
*left_size = 0;
|
||
status = DMA_COMPLETE;
|
||
}
|
||
else
|
||
{
|
||
uint32_t pos = 0;
|
||
bool count = false;
|
||
|
||
pos = hal_readl(DMA_LLI_ADDR(chan->chan_count));
|
||
*left_size = hal_readl(DMA_CNT(chan->chan_count));
|
||
if (pos == LINK_END)
|
||
{
|
||
status = DMA_COMPLETE;
|
||
goto unlock;
|
||
}
|
||
for (l_item = chan->desc; l_item != NULL; l_item = l_item->vlln)
|
||
{
|
||
if (l_item->p_lln == pos)
|
||
{
|
||
count = true;
|
||
continue;
|
||
}
|
||
if (count)
|
||
{
|
||
*left_size += l_item->len;
|
||
}
|
||
}
|
||
status = DMA_IN_PROGRESS;
|
||
}
|
||
}
|
||
else
|
||
{
|
||
*left_size = hal_readl(DMA_CNT(chan->chan_count));
|
||
|
||
if (*left_size == 0)
|
||
{
|
||
status = DMA_COMPLETE;
|
||
}
|
||
else
|
||
{
|
||
status = DMA_IN_PROGRESS;
|
||
}
|
||
}
|
||
|
||
unlock:
|
||
hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
|
||
|
||
return status;
|
||
}
|
||
|
||
hal_dma_status_t hal_dma_start(struct sunxi_dma_chan *chan)
|
||
{
|
||
uint32_t high = 0;
|
||
uint32_t irq_val = 0;
|
||
struct sunxi_dma_lli *prev = NULL;
|
||
uint32_t __cpsr;
|
||
|
||
if (NULL == chan)
|
||
{
|
||
DMA_ERR("[dma] chan is NULL\n");
|
||
return HAL_DMA_STATUS_INVALID_PARAMETER;
|
||
}
|
||
|
||
__cpsr = hal_spin_lock_irqsave(&dma_lock);
|
||
|
||
if (chan->cyclic)
|
||
chan->irq_type = IRQ_PKG;
|
||
else
|
||
chan->irq_type = IRQ_QUEUE;
|
||
|
||
high = (chan->chan_count + START_CHAN_OFFSET >= HIGH_CHAN) ? 1 : 0;
|
||
|
||
irq_val = hal_readl(DMA_IRQ_EN(high));
|
||
irq_val |= SHIFT_IRQ_MASK(chan->irq_type, chan->chan_count);
|
||
hal_writel(irq_val, DMA_IRQ_EN(high));
|
||
|
||
SET_OP_MODE(chan->chan_count, SRC_HS_MASK | DST_HS_MASK);
|
||
|
||
for (prev = chan->desc; prev != NULL; prev = prev->vlln)
|
||
{
|
||
hal_dcache_clean((unsigned long)prev, sizeof(*prev));
|
||
/* k_dcache_clean(prev, sizeof(*prev)); */
|
||
//k_dcache_clean(prev->src, prev->len);
|
||
//k_dcache_clean_invalidate(prev->dst, prev->len);
|
||
}
|
||
|
||
hal_writel(__va_to_pa((unsigned long)chan->desc), DMA_LLI_ADDR(chan->chan_count));
|
||
hal_writel(CHAN_START, DMA_ENABLE(chan->chan_count));
|
||
sunxi_dump_com_regs();
|
||
sunxi_dump_chan_regs(chan);
|
||
hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
|
||
return HAL_DMA_STATUS_OK;
|
||
}
|
||
|
||
hal_dma_status_t hal_dma_stop(struct sunxi_dma_chan *chan)
|
||
{
|
||
uint32_t __cpsr;
|
||
|
||
if (NULL == chan)
|
||
{
|
||
DMA_ERR("[dma] chan is NULL\n");
|
||
return HAL_DMA_STATUS_INVALID_PARAMETER;
|
||
}
|
||
|
||
__cpsr = hal_spin_lock_irqsave(&dma_lock);
|
||
/*We should entry PAUSE state first to avoid missing data
|
||
* count witch transferring on bus.
|
||
*/
|
||
hal_writel(CHAN_PAUSE, DMA_PAUSE(chan->chan_count));
|
||
hal_writel(CHAN_STOP, DMA_ENABLE(chan->chan_count));
|
||
hal_writel(CHAN_RESUME, DMA_PAUSE(chan->chan_count));
|
||
|
||
if (chan->cyclic)
|
||
{
|
||
chan->cyclic = false;
|
||
}
|
||
hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
|
||
|
||
return HAL_DMA_STATUS_OK;
|
||
}
|
||
|
||
hal_dma_status_t hal_dma_chan_free(struct sunxi_dma_chan *chan)
|
||
{
|
||
uint32_t high = 0;
|
||
unsigned long irq_val = 0;
|
||
uint32_t __cpsr;
|
||
|
||
if (NULL == chan)
|
||
{
|
||
DMA_ERR("[dma] chan is NULL\n");
|
||
return HAL_DMA_STATUS_INVALID_PARAMETER;
|
||
}
|
||
|
||
if (!chan->used)
|
||
{
|
||
return HAL_DMA_STATUS_INVALID_PARAMETER;
|
||
}
|
||
|
||
__cpsr = hal_spin_lock_irqsave(&dma_lock);
|
||
|
||
high = (chan->chan_count + START_CHAN_OFFSET >= HIGH_CHAN) ? 1 : 0;
|
||
|
||
irq_val = hal_readl(DMA_IRQ_EN(high));
|
||
irq_val &= ~(SHIFT_IRQ_MASK(chan->irq_type, chan->chan_count));
|
||
hal_writel(irq_val, DMA_IRQ_EN(high));
|
||
|
||
chan->used = 0;
|
||
hal_spin_unlock_irqrestore(&dma_lock, __cpsr);
|
||
|
||
sunxi_dma_free_ill(chan);
|
||
|
||
return HAL_DMA_STATUS_OK;
|
||
}
|
||
|
||
hal_dma_status_t hal_dma_chan_desc_free(struct sunxi_dma_chan *chan)
|
||
{
|
||
/* FIXME: Interrupt context cannot release memory in melis OS. */
|
||
if (hal_interrupt_get_nest() <= 0)
|
||
{
|
||
sunxi_dma_free_ill(chan);
|
||
return HAL_DMA_STATUS_OK;
|
||
}
|
||
/* Freeing memory in interrupt is not allowed */
|
||
return HAL_DMA_STATUS_ERR_PERM;
|
||
}
|
||
|
||
/* only need to be executed once */
|
||
void hal_dma_init(void)
|
||
{
|
||
uint32_t i = 0, high = 0;
|
||
|
||
memset((void *)dma_chan_source, 0, NR_MAX_CHAN * sizeof(struct sunxi_dma_chan));
|
||
|
||
for (i = 0; i < NR_MAX_CHAN; i++)
|
||
{
|
||
high = (i >= HIGH_CHAN) ? 1 : 0;
|
||
/*disable all dma irq*/
|
||
hal_writel(0, DMA_IRQ_EN(high));
|
||
/*clear all dma irq pending*/
|
||
hal_writel(0xffffffff, DMA_IRQ_STAT(high));
|
||
}
|
||
/* disable auto gating */
|
||
hal_writel(DMA_MCLK_GATE | DMA_COMMON_GATE | DMA_CHAN_GATE, DMA_GATE);
|
||
sunxi_dma_clk_init(true);
|
||
|
||
/*request dma irq*/
|
||
if (request_irq(DMA_IRQ_NUM, sunxi_dma_irq_handle, 0, "dma-ctl", NULL) < 0)
|
||
{
|
||
DMA_ERR("[dma] request irq error\n");
|
||
}
|
||
enable_irq(DMA_IRQ_NUM);
|
||
}
|
||
|