55 lines
2.6 KiB
C
55 lines
2.6 KiB
C
/*
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* Copyright (C) 2017 C-SKY Microsystems Co., Ltd. All rights reserved.
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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/******************************************************************************
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* @file dw_gpio.h
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* @brief header file for GPIO Driver
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* @version V1.0
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* @date 02. June 2017
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******************************************************************************/
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#ifndef _DW_GPIO_H_
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#define _DW_GPIO_H_
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#include "drv_gpio.h"
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#include "soc.h"
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typedef struct {
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__IOM uint32_t SWPORT_DR; /* Offset: 0x000 (W/R) PortA data register */
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__IOM uint32_t SWPORT_DDR; /* Offset: 0x004 (W/R) PortA data direction register */
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__IOM uint32_t PORT_CTL; /* Offset: 0x008 (W/R) PortA source register */
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} dw_gpio_reg_t;
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typedef struct {
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__IOM uint32_t INTEN; /* Offset: 0x000 (W/R) Interrupt enable register */
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__IOM uint32_t INTMASK; /* Offset: 0x004 (W/R) Interrupt mask register */
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__IOM uint32_t INTTYPE_LEVEL; /* Offset: 0x008 (W/R) Interrupt level register */
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__IOM uint32_t INT_POLARITY; /* Offset: 0x00c (W/R) Interrupt polarity register */
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__IM uint32_t INTSTATUS; /* Offset: 0x010 (R) Interrupt status of Port */
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__IM uint32_t RAWINTSTATUS; /* Offset: 0x014 (W/R) Raw interrupt status of Port */
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__IOM uint32_t revreg1; /* Offset: 0x018 (W/R) Reserve register */
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__OM uint32_t PORTA_EOI; /* Offset: 0x01c (W/R) Port clear interrupt register */
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__IM uint32_t EXT_PORTA; /* Offset: 0x020 (W/R) PortA external port register */
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__IM uint32_t EXT_PORTB; /* Offset: 0x024 (W/R) PortB external port register */
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__IOM uint32_t revreg2[2]; /* Offset: 0x028 (W/R) Reserve register */
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__IOM uint32_t LS_SYNC; /* Offset: 0x030 (W/R) Level-sensitive synchronization enable register */
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} dw_gpio_control_reg_t;
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#endif
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