453 lines
18 KiB
C
453 lines
18 KiB
C
/**
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*********************************************************************************
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*
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* @file ald_spi.c
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* @brief Header file of SPI module driver.
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*
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* @version V1.0
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* @date 23 Feb. 2023
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* @author AE Team
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* @note
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* Change Logs:
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* Date Author Notes
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* 23 Feb. 2023 Lisq The first version
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*
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* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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**********************************************************************************
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*/
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#ifndef __ALD_SPI_H__
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#define __ALD_SPI_H__
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#include "ald_dma.h"
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#include "ald_syscfg.h"
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/** @addtogroup ES32VF2264_ALD
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* @{
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*/
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/** @addtogroup SPI
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* @{
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*/
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/** @defgroup SPI_Public_Types SPI Public Types
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* @{
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*/
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/**
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* @brief clock phase
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*/
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typedef enum {
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ALD_SPI_CPHA_FIRST = 0U, /**< Transiting data in the first edge */
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ALD_SPI_CPHA_SECOND = 1U, /**< Transiting data in the seconde edge */
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} ald_spi_cpha_t;
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/**
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* @brief clock polarity
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*/
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typedef enum {
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ALD_SPI_CPOL_LOW = 0U, /**< Polarity hold low when spi-bus is idle */
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ALD_SPI_CPOL_HIGH = 1U, /**< Polarity hold high when spi-bus is idle */
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} ald_spi_cpol_t;
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/**
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* @brief master selection
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*/
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typedef enum {
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ALD_SPI_MODE_SLAVER = 0U, /**< Slave mode */
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ALD_SPI_MODE_MASTER = 1U, /**< Master mode */
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} ald_spi_mode_t;
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/**
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* @brief baud rate control
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*/
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typedef enum {
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ALD_SPI_BAUD_2 = 0U, /**< fpclk/2 */
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ALD_SPI_BAUD_4 = 1U, /**< fpclk/4 */
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ALD_SPI_BAUD_8 = 2U, /**< fpclk/8 */
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ALD_SPI_BAUD_16 = 3U, /**< fpclk/16 */
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ALD_SPI_BAUD_32 = 4U, /**< fpclk/32 */
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ALD_SPI_BAUD_64 = 5U, /**< fpclk/64 */
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ALD_SPI_BAUD_128 = 6U, /**< fpclk/128 */
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ALD_SPI_BAUD_256 = 7U, /**< fpclk/256 */
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} ald_spi_baud_t;
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/**
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* @brief frame format
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*/
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typedef enum {
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ALD_SPI_FIRSTBIT_MSB = 0U, /**< MSB transmitted first */
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ALD_SPI_FIRSTBIT_LSB = 1U, /**< LSB transmitted first */
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} ald_spi_firstbit_t;
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/**
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* @brief data frame format
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*/
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typedef enum {
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ALD_SPI_DATA_SIZE_8 = 0U, /**< 8-bit data frame format is selected for transmission/reception */
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ALD_SPI_DATA_SIZE_16 = 1U, /**< 16-bit data frame format is selected for transmission/reception */
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} ald_spi_datasize_t;
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/**
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* @brief SPI error status
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*/
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typedef enum {
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ALD_SPI_ERROR_NONE = 0U, /**< none */
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ALD_SPI_ERROR_MODF = 1U, /**< mode fault */
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ALD_SPI_ERROR_CRC = 2U, /**< crc error */
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ALD_SPI_ERROR_FRE = 4U, /**< frame error */
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ALD_SPI_ERROR_RXOV = 8U, /**< receive over error */
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ALD_SPI_ERROR_TXOV = 0x10U, /**< dma error */
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ALD_SPI_ERROR_FLAG = 0x20U, /**< interrupt flag error */
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} ald_spi_error_t;
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/**
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* @brief interrupt control
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*/
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typedef enum {
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ALD_SPI_IT_TXE = (1U << 0), /**< Transmit fifo empty interrupt */
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ALD_SPI_IT_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt */
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ALD_SPI_IT_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt */
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ALD_SPI_IT_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt */
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ALD_SPI_IT_RXNE = (1U << 8), /**< Receive fifo not empty interrupt */
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ALD_SPI_IT_RXF = (1U << 9), /**< Receive fifo full interrupt */
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ALD_SPI_IT_RXOV = (1U << 10), /**< Receive fifo overflow interrupt */
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ALD_SPI_IT_RXUD = (1U << 11), /**< Receive fifo underflow interrupt */
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ALD_SPI_IT_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt */
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ALD_SPI_IT_CRCERR = (1U << 16), /**< Crc error interrupt */
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ALD_SPI_IT_MODF = (1U << 17), /**< Mode error interrupt */
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ALD_SPI_IT_FRE = (1U << 18), /**< Frame error interrupt */
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} ald_spi_it_t;
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/**
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* @brief interrupt flag
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*/
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typedef enum {
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ALD_SPI_IF_TXE = (1U << 0), /**< Transmit fifo empty interrupt flag */
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ALD_SPI_IF_TXOV = (1U << 2), /**< Transmit fifo overflow interrupt flag */
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ALD_SPI_IF_TXUD = (1U << 3), /**< Transmit fifo underflow interrupt flag */
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ALD_SPI_IF_TXTH = (1U << 4), /**< Transmit fifo under threshold interrupt flag */
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ALD_SPI_IF_RXNE = (1U << 8), /**< Receive fifo not empty interrupt flag */
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ALD_SPI_IF_RXF = (1U << 9), /**< Receive fifo full interrupt flag */
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ALD_SPI_IF_RXOV = (1U << 10), /**< Receive fifo overflow interrupt flag */
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ALD_SPI_IF_RXUD = (1U << 11), /**< Receive fifo underflow interrupt flag */
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ALD_SPI_IF_RXTH = (1U << 12), /**< Receive fifo over threshold interrupt flag */
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ALD_SPI_IF_CRCERR = (1U << 16), /**< Crc error interrupt flag */
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ALD_SPI_IF_MODF = (1U << 17), /**< Mode error interrupt flag */
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ALD_SPI_IF_FRE = (1U << 18), /**< Frame error interrupt flag */
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} ald_spi_flag_t;
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/**
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* @brief SPI state structures definition
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*/
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typedef enum {
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ALD_SPI_STATE_RESET = 0x00U, /**< Peripheral is not initialized */
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ALD_SPI_STATE_READY = 0x01U, /**< Peripheral Initialized and ready for use */
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ALD_SPI_STATE_BUSY = 0x02U, /**< an internal process is ongoing */
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ALD_SPI_STATE_BUSY_TX = 0x11U, /**< transmit is ongoing */
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ALD_SPI_STATE_BUSY_RX = 0x21U, /**< receive is ongoing */
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ALD_SPI_STATE_BUSY_TX_RX = 0x31U, /**< transmit and receive are ongoing */
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ALD_SPI_STATE_TIMEOUT = 0x03U, /**< Timeout state */
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ALD_SPI_STATE_ERROR = 0x04U, /**< Error */
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} ald_spi_state_t;
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/**
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* @brief SPI direction definition
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*/
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typedef enum {
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ALD_SPI_DIRECTION_2LINES = 0U, /**< 2 lines */
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ALD_SPI_DIRECTION_2LINES_RXONLY = 1U, /**< 2 lines only rx */
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ALD_SPI_DIRECTION_1LINE = 2U, /**< 1 line */
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ALD_SPI_DIRECTION_1LINE_RX = 3U, /**< 1 line only rx */
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} ald_spi_direction_t;
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/**
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* @brief SPI dma request definition
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*/
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typedef enum {
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ALD_SPI_DMA_REQ_TX = 0U, /**< TX dma request */
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ALD_SPI_DMA_REQ_RX = 1U, /**< RX dma request */
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} ald_spi_dma_req_t;
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/**
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* @brief SPI crc length definition
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*/
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typedef enum {
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ALD_SPI_FRAME_MOTOROLA = 0U, /**< SPI motorola mode */
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ALD_SPI_FRAME_TI = 1U, /**< SPI TI mode */
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} ald_spi_frame_t;
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/**
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* @brief SPI status definition
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*/
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typedef enum {
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ALD_SPI_STATUS_TXE = (1U << 0), /**< Transmit fifo empty status */
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ALD_SPI_STATUS_TXF = (1U << 1), /**< Transmit fifo full status */
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ALD_SPI_STATUS_TXOV = (1U << 2), /**< Transmit fifo overflow status */
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ALD_SPI_STATUS_TXUD = (1U << 3), /**< Transmit fifo underflow status */
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ALD_SPI_STATUS_TXTH = (1U << 4), /**< Transmit fifo under threshold status */
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ALD_SPI_STATUS_RXNE = (1U << 8), /**< Receive fifo not empty status */
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ALD_SPI_STATUS_RXF = (1U << 9), /**< Receive fifo full status */
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ALD_SPI_STATUS_RXOV = (1U << 10), /**< Receive fifo overflow status */
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ALD_SPI_STATUS_RXUD = (1U << 11), /**< Receive fifo underflow status */
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ALD_SPI_STATUS_RXTH = (1U << 12), /**< Receive fifo under threshold status */
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ALD_SPI_STATUS_BUSY = (1U << 15), /**< BUSY status */
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} ald_spi_status_t;
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/**
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* @brief SPI TXE/RXNE status definition
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*/
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typedef enum {
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ALD_SPI_SR_TXE = 0U, /**< SR.TXE set */
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ALD_SPI_SR_RXNE = 1U, /**< SR.RXTH set */
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ALD_SPI_SR_TXE_RXNE = 2U, /**< SR.TXE and SR.RXNE set */
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} ald_spi_sr_status_t;
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/**
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* @brief SPI init structure definition
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*/
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typedef struct {
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ald_spi_mode_t mode; /**< SPI mode */
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ald_spi_direction_t dir; /**< SPI direction */
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ald_spi_datasize_t data_size; /**< SPI data size */
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ald_spi_baud_t baud; /**< SPI baudrate prescaler */
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ald_spi_cpha_t phase; /**< SPI clock phase */
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ald_spi_cpol_t polarity; /**< SPI clock polarity */
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ald_spi_firstbit_t first_bit; /**< SPI first bit */
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type_func_t ss_en; /**< SPI ssm enable or disable */
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type_func_t crc_calc; /**< SPI crc calculation */
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ald_spi_frame_t frame; /**< SPI frame format */
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uint16_t crc_poly; /**< SPI crc polynomial */
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} ald_spi_init_t;
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/**
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* @brief SPI handle structure definition
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*/
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typedef struct ald_spi_handle_s {
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SPI_I2S_TypeDef *perh; /**< SPI registers base address */
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ald_spi_init_t init; /**< SPI communication parameters */
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uint8_t *tx_buf; /**< Pointer to SPI Tx transfer buffer */
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uint16_t tx_size; /**< SPI Tx transfer size */
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uint16_t tx_count; /**< SPI Tx transfer counter */
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uint8_t *rx_buf; /**< Pointer to SPI Rx transfer buffer */
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uint16_t rx_size; /**< SPI Rx Transfer size */
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uint16_t rx_count; /**< SPI Rx Transfer Counter */
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ald_dma_handle_t hdmatx; /**< SPI Tx DMA handle parameters */
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ald_dma_handle_t hdmarx; /**< SPI Rx DMA handle parameters */
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lock_state_t lock; /**< Locking object */
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ald_spi_state_t state; /**< SPI communication state */
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uint32_t err_code; /**< SPI error code */
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void (*tx_cplt_cbk)(struct ald_spi_handle_s *arg); /**< Tx completed callback */
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void (*rx_cplt_cbk)(struct ald_spi_handle_s *arg); /**< Rx completed callback */
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void (*tx_rx_cplt_cbk)(struct ald_spi_handle_s *arg); /**< Tx & Rx completed callback */
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void (*err_cbk)(struct ald_spi_handle_s *arg); /**< error callback */
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} ald_spi_handle_t;
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/**
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* @}
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*/
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/** @defgroup SPI_Public_Macros SPI Public Macros
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* @{
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*/
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#define ALD_SPI_RESET_HANDLE_STATE(x) ((x)->state = ALD_SPI_STATE_RESET)
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#define ALD_SPI_ENABLE(x) ((x)->perh->CON1 |= (1 << SPI_CON1_SPIEN_POS))
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#define ALD_SPI_DISABLE(x) ((x)->perh->CON1 &= ~(1 << SPI_CON1_SPIEN_POS))
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#define ALD_SPI_CRC_RESET(x) \
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do { \
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CLEAR_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
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SET_BIT((x)->perh->CON1, SPI_CON1_CRCEN_MSK); \
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} while (0)
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#define ALD_SPI_CRCNEXT_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
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#define ALD_SPI_CRCNEXT_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_NXTCRC_MSK))
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#define ALD_SPI_RXONLY_ENABLE(x) (SET_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
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#define ALD_SPI_RXONLY_DISABLE(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_RXO_MSK))
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#define ALD_SPI_1LINE_TX(x) (SET_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
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#define ALD_SPI_1LINE_RX(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_BIDOEN_MSK))
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#define ALD_SPI_SSI_HIGH(x) (SET_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
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#define ALD_SPI_SSI_LOW(x) (CLEAR_BIT((x)->perh->CON1, SPI_CON1_SSOUT_MSK))
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#define ALD_SPI_SSOE_ENABLE(x) (SET_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
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#define ALD_SPI_SSOE_DISABLE(x) (CLEAR_BIT((x)->perh->CON2, SPI_CON2_NSSOE_MSK))
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/**
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* @}
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*/
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/** @defgroup SPI_Private_Macros SPI Private Macros
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* @{
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*/
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#define IS_SPI(x) (((x) == SPI0) || \
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((x) == SPI1))
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#define IS_SPI_CPHA(x) (((x) == ALD_SPI_CPHA_FIRST) || \
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((x) == ALD_SPI_CPHA_SECOND))
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#define IS_SPI_CPOL(x) (((x) == ALD_SPI_CPOL_LOW) || \
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((x) == ALD_SPI_CPOL_HIGH))
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#define IS_SPI_MODE(x) (((x) == ALD_SPI_MODE_SLAVER) || \
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((x) == ALD_SPI_MODE_MASTER))
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#define IS_SPI_FIRBIT(x) (((x) == ALD_SPI_FIRSTBIT_MSB) || \
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((x) == ALD_SPI_FIRSTBIT_LSB))
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#define IS_SPI_BAUD(x) (((x) == ALD_SPI_BAUD_2) || \
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((x) == ALD_SPI_BAUD_4) || \
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((x) == ALD_SPI_BAUD_8) || \
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((x) == ALD_SPI_BAUD_16) || \
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((x) == ALD_SPI_BAUD_32) || \
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((x) == ALD_SPI_BAUD_64) || \
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((x) == ALD_SPI_BAUD_128) || \
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((x) == ALD_SPI_BAUD_256))
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#define IS_SPI_DATASIZE(x) (((x) == ALD_SPI_DATA_SIZE_8) || \
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((x) == ALD_SPI_DATA_SIZE_16))
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#define IS_SPI_BIDOE(x) (((x) == ALD_SPI_BID_RX) || \
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((x) == ALD_SPI_BID_TX))
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#define IS_SPI_BIDMODE(x) (((x) == ALD_SPI_BIDMODE_DUAL) || \
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((x) == ALD_SPI_BIDMODE_SOLE))
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#define IS_SPI_DIRECTION(x) (((x) == ALD_SPI_DIRECTION_2LINES) || \
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((x) == ALD_SPI_DIRECTION_2LINES_RXONLY) || \
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((x) == ALD_SPI_DIRECTION_1LINE) || \
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((x) == ALD_SPI_DIRECTION_1LINE_RX))
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#define IS_SPI_DMA_REQ(x) (((x) == ALD_SPI_DMA_REQ_TX) || \
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((x) == ALD_SPI_DMA_REQ_RX))
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#define IS_SPI_STATUS(x) (((x) == ALD_SPI_STATUS_TXE) || \
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((x) == ALD_SPI_STATUS_TXF) || \
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((x) == ALD_SPI_STATUS_TXOV) || \
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((x) == ALD_SPI_STATUS_TXUD) || \
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((x) == ALD_SPI_STATUS_TXTH) || \
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((x) == ALD_SPI_STATUS_RXNE) || \
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((x) == ALD_SPI_STATUS_RXF) || \
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((x) == ALD_SPI_STATUS_RXOV) || \
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((x) == ALD_SPI_STATUS_RXUD) || \
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((x) == ALD_SPI_STATUS_RXTH) || \
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((x) == ALD_SPI_STATUS_BUSY))
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#define IS_SPI_IT(x) (((x) == ALD_SPI_IT_TXE) || \
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((x) == ALD_SPI_IT_TXOV) || \
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((x) == ALD_SPI_IT_TXUD) || \
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((x) == ALD_SPI_IT_TXTH) || \
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((x) == ALD_SPI_IT_RXNE) || \
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((x) == ALD_SPI_IT_RXF) || \
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((x) == ALD_SPI_IT_RXOV) || \
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((x) == ALD_SPI_IT_RXUD) || \
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((x) == ALD_SPI_IT_RXTH) || \
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((x) == ALD_SPI_IT_CRCERR) || \
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((x) == ALD_SPI_IT_MODF) || \
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((x) == ALD_SPI_IT_FRE))
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#define IS_SPI_IF(x) (((x) == ALD_SPI_IF_TXE) || \
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((x) == ALD_SPI_IF_TXOV) || \
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((x) == ALD_SPI_IF_TXUD) || \
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((x) == ALD_SPI_IF_TXTH) || \
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((x) == ALD_SPI_IF_RXNE) || \
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((x) == ALD_SPI_IF_RXF) || \
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((x) == ALD_SPI_IF_RXOV) || \
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((x) == ALD_SPI_IF_RXUD) || \
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((x) == ALD_SPI_IF_RXTH) || \
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((x) == ALD_SPI_IF_CRCERR) || \
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((x) == ALD_SPI_IF_MODF) || \
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((x) == ALD_SPI_IF_FRE))
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#define IS_SPI_FRAME(x) (((x) == ALD_SPI_FRAME_MOTOROLA) || \
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((x) == ALD_SPI_FRAME_TI) )
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/**
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* @}
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*/
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/** @addtogroup SPI_Public_Functions
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* @{
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*/
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/** @addtogroup SPI_Public_Functions_Group1
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* @{
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*/
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ald_status_t ald_spi_init(ald_spi_handle_t *hperh);
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void ald_spi_reset(ald_spi_handle_t *hperh);
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/**
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* @}
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*/
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/** @addtogroup SPI_Public_Functions_Group2
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* @{
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*/
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int32_t ald_spi_send_byte_fast(ald_spi_handle_t *hperh, uint8_t data);
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int32_t ald_spi_send_byte_fast_1line(ald_spi_handle_t *hperh, uint8_t data);
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uint8_t ald_spi_recv_byte_fast(ald_spi_handle_t *hperh, int *status);
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ald_status_t ald_spi_send_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
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ald_status_t ald_spi_master_recv_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size);
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ald_status_t ald_spi_slave_recv_bytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
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ald_status_t ald_spi_send_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
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ald_status_t ald_spi_master_recv_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size);
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ald_status_t ald_spi_slave_recv_dbytes_fast(ald_spi_handle_t *hperh, uint8_t *buf, uint32_t size, uint32_t timeout);
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/**
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* @}
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*/
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/** @addtogroup SPI_Public_Functions_Group3
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* @{
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*/
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ald_status_t ald_spi_send(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
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ald_status_t ald_spi_recv(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint32_t timeout);
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ald_status_t ald_spi_send_recv(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint32_t timeout);
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ald_status_t ald_spi_send_by_it(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size);
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ald_status_t ald_spi_recv_by_it(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size);
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ald_status_t ald_spi_send_recv_by_it(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size);
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ald_status_t ald_spi_send_by_dma(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
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ald_status_t ald_spi_recv_by_dma(ald_spi_handle_t *hperh, uint8_t *buf, uint16_t size, uint8_t channel);
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ald_status_t ald_spi_send_recv_by_dma(ald_spi_handle_t *hperh, uint8_t *tx_buf, uint8_t *rx_buf, uint16_t size, uint8_t tx_channel, uint8_t rx_channel);
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ald_status_t ald_spi_dma_pause(ald_spi_handle_t *hperh);
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ald_status_t ald_spi_dma_resume(ald_spi_handle_t *hperh);
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ald_status_t ald_spi_dma_stop(ald_spi_handle_t *hperh);
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/**
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* @}
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*/
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/** @addtogroup SPI_Public_Functions_Group4
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* @{
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*/
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void ald_spi_irq_handler(ald_spi_handle_t *hperh);
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void ald_spi_interrupt_config(ald_spi_handle_t *hperh, ald_spi_it_t it, type_func_t state);
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void ald_spi_speed_config(ald_spi_handle_t *hperh, ald_spi_baud_t speed);
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void ald_spi_dma_req_config(ald_spi_handle_t *hperh, ald_spi_dma_req_t req, type_func_t state);
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it_status_t ald_spi_get_it_status(ald_spi_handle_t *hperh, ald_spi_it_t it);
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flag_status_t spi_get_status(ald_spi_handle_t *hperh, ald_spi_status_t status);
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flag_status_t ald_spi_get_flag_status(ald_spi_handle_t *hperh, ald_spi_flag_t flag);
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void ald_spi_clear_flag_status(ald_spi_handle_t *hperh, ald_spi_flag_t flag);
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/**
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* @}
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*/
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/** @addtogroup SPI_Public_Functions_Group5
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* @{
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*/
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ald_spi_state_t ald_spi_get_state(ald_spi_handle_t *hperh);
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uint32_t ald_spi_get_error(ald_spi_handle_t *hperh);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /* __ALD_SPI_H__ */
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