343 lines
13 KiB
C
343 lines
13 KiB
C
/**
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*********************************************************************************
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*
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* @file ald_dma.h
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* @brief DMA module Library.
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*
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* @version V1.0
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* @date 16 Feb. 2023
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* @author AE Team
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* @note
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* Change Logs:
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* Date Author Notes
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* 16 Feb. 2023 AE Team The first version
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*
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* Copyright (C) Shanghai Eastsoft Microelectronics Co. Ltd. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed under the Apache License, Version 2.0 (the License); you may
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* not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an AS IS BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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**********************************************************************************
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*/
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#ifndef __ALD_DMA_H__
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#define __ALD_DMA_H__
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#ifdef __cplusplus
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extern "C" {
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#endif /* __cplusplus */
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#include "ald_utils.h"
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/** @addtogroup ES32VF2264_ALD
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* @{
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*/
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/** @addtogroup DMA
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* @{
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*/
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/**
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* @defgroup DMA_Public_Macros DMA Public Macros
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* @{
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*/
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#define ALD_DMA_CH_COUNT 7U
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/**
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* @}
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*/
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/**
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* @defgroup DMA_Public_Types DMA Public Types
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* @{
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*/
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/**
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* @brief Input source to DMA channel
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*/
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typedef enum {
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ALD_DMA_MSEL_NONE = 0x0U, /**< NONE */
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ALD_DMA_MSEL_GPIO = 0x1U, /**< GPIO */
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ALD_DMA_MSEL_ADC = 0x2U, /**< ADC */
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ALD_DMA_MSEL_CRC = 0x3U, /**< CRC */
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ALD_DMA_MSEL_EUART0 = 0x4U, /**< EUART0 */
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ALD_DMA_MSEL_EUART1 = 0x5U, /**< EUART1 */
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ALD_DMA_MSEL_CUART0 = 0x6U, /**< CUART0 */
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ALD_DMA_MSEL_CUART1 = 0x7U, /**< CUART1 */
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ALD_DMA_MSEL_CUART2 = 0x8U, /**< CUART2 */
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ALD_DMA_MSEL_SPI0 = 0x9U, /**< SPI0 */
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ALD_DMA_MSEL_SPI1 = 0xAU, /**< SPI1 */
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ALD_DMA_MSEL_I2C0 = 0xBU, /**< I2C0 */
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ALD_DMA_MSEL_I2C1 = 0xCU, /**< I2C1 */
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ALD_DMA_MSEL_AD16C4T = 0xDU, /**< AD16C4T */
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ALD_DMA_MSEL_GP16C4T0= 0xEU, /**< GP16C4T0 */
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ALD_DMA_MSEL_GP16C4T1= 0xFU, /**< GP16C4T1 */
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ALD_DMA_MSEL_GP16C4T2= 0x10U, /**< GP16C4T2 */
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ALD_DMA_MSEL_PIS = 0x11U, /**< PIS */
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ALD_DMA_MSEL_BS16T = 0x12U, /**< BS16T */
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} ald_dma_msel_t;
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/**
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* @brief Input signal to DMA channel
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*/
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typedef enum {
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ALD_DMA_MSIGSEL_NONE = 0x0U, /**< NONE */
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ALD_DMA_MSIGSEL_EXTI_0 = 0x0U, /**< External interrupt 0 */
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ALD_DMA_MSIGSEL_EXTI_1 = 0x1U, /**< External interrupt 1 */
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ALD_DMA_MSIGSEL_EXTI_2 = 0x2U, /**< External interrupt 2 */
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ALD_DMA_MSIGSEL_EXTI_3 = 0x3U, /**< External interrupt 3 */
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ALD_DMA_MSIGSEL_EXTI_4 = 0x4U, /**< External interrupt 4 */
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ALD_DMA_MSIGSEL_EXTI_5 = 0x5U, /**< External interrupt 5 */
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ALD_DMA_MSIGSEL_EXTI_6 = 0x6U, /**< External interrupt 6 */
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ALD_DMA_MSIGSEL_EXTI_7 = 0x7U, /**< External interrupt 7 */
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ALD_DMA_MSIGSEL_EXTI_8 = 0x8U, /**< External interrupt 8 */
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ALD_DMA_MSIGSEL_EXTI_9 = 0x9U, /**< External interrupt 9 */
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ALD_DMA_MSIGSEL_EXTI_10 = 0xAU, /**< External interrupt 10 */
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ALD_DMA_MSIGSEL_EXTI_11 = 0xBU, /**< External interrupt 11 */
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ALD_DMA_MSIGSEL_EXTI_12 = 0xCU, /**< External interrupt 12 */
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ALD_DMA_MSIGSEL_EXTI_13 = 0xDU, /**< External interrupt 13 */
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ALD_DMA_MSIGSEL_EXTI_14 = 0xEU, /**< External interrupt 14 */
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ALD_DMA_MSIGSEL_EXTI_15 = 0xFU, /**< External interrupt 15 */
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ALD_DMA_MSIGSEL_ADC = 0x0U, /**< ADC mode */
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ALD_DMA_MSIGSEL_CRC = 0x0U, /**< CRC */
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ALD_DMA_MSIGSEL_UART_RNR = 0x0U, /**< UART reveive */
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ALD_DMA_MSIGSEL_UART_TXEMPTY = 0x1U, /**< UART transmit */
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ALD_DMA_MSIGSEL_SPI_RNR = 0x0U, /**< SPI receive */
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ALD_DMA_MSIGSEL_SPI_TXEMPTY = 0x1U, /**< SPI transmit */
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ALD_DMA_MSIGSEL_I2C_RNR = 0x0U, /**< I2C receive */
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ALD_DMA_MSIGSEL_I2C_TXEMPTY = 0x1U, /**< I2C transmit */
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ALD_DMA_MSIGSEL_TIMER_CH1 = 0x0U, /**< TIM channal 1 */
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ALD_DMA_MSIGSEL_TIMER_CH2 = 0x1U, /**< TIM channal 2 */
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ALD_DMA_MSIGSEL_TIMER_CH3 = 0x2U, /**< TIM channal 3 */
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ALD_DMA_MSIGSEL_TIMER_CH4 = 0x3U, /**< TIM channal 4 */
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ALD_DMA_MSIGSEL_TIMER_TRI = 0x4U, /**< TIM trigger */
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ALD_DMA_MSIGSEL_TIMER_COMP = 0x5U, /**< TIM compare */
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ALD_DMA_MSIGSEL_TIMER_UPDATE = 0x6U, /**< TIM update */
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ALD_DMA_MSIGSEL_PIS_CH0 = 0x0U, /**< PIS channal 0 */
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ALD_DMA_MSIGSEL_PIS_CH1 = 0x1U, /**< PIS channal 1 */
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ALD_DMA_MSIGSEL_PIS_CH2 = 0x2U, /**< PIS channal 2 */
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ALD_DMA_MSIGSEL_PIS_CH3 = 0x3U, /**< PIS channal 3 */
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ALD_DMA_MSIGSEL_PIS_CH4 = 0x4U, /**< PIS channal 4 */
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ALD_DMA_MSIGSEL_PIS_CH5 = 0x5U, /**< PIS channal 5 */
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ALD_DMA_MSIGSEL_PIS_CH6 = 0x6U, /**< PIS channal 6 */
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ALD_DMA_MSIGSEL_PIS_CH7 = 0x7U, /**< PIS channal 7 */
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ALD_DMA_MSIGSEL_BSTIM = 0x0U, /**< BSTIM */
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} ald_dma_msigsel_t;
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/**
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* @brief Priority of DMA channel
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*/
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typedef enum
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{
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ALD_DMA_LOW_PRIORITY = 0,
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ALD_DMA_MEDIUM_PRIORITY = 1,
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ALD_DMA_HIGH_PRIORUTY = 2,
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ALD_DMA_HIGHEST_PRIORITY = 3
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} ald_dma_priority_t;
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/**
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* @brief data increment
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*/
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typedef enum
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{
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ALD_DMA_DATA_INC_DISABLE = 0x0U,
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ALD_DMA_DATA_INC_ENABLE = 0x1U,
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} ald_dma_data_inc_t;
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/**
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* @brief Data size
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*/
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typedef enum {
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ALD_DMA_DATA_SIZE_BYTE = 0x0U, /**< Byte */
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ALD_DMA_DATA_SIZE_HALFWORD = 0x1U, /**< Halfword */
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ALD_DMA_DATA_SIZE_WORD = 0x2U, /**< Word */
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} ald_dma_data_size_t;
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/**
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* @brief Interrupt flag trigger mode
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*/
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typedef enum
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{
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ALD_DMA_IT_FLAG_TC = 0x0U, /**< DMA transfer complete interrupt */
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ALD_DMA_IT_FLAG_HT = 0x1U, /**< DMA transfer half complete interrupt */
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} ald_dma_it_flag_t;
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/**
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* @brief Control how many DMA transfers can occur
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* before the controller re-arbitrates
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*/
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typedef enum {
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ALD_DMA_R_POWER_1 = 0x0U, /**< Arbitrates after each DMA transfer */
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ALD_DMA_R_POWER_2 = 0x1U, /**< Arbitrates after 2 DMA transfer */
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ALD_DMA_R_POWER_4 = 0x2U, /**< Arbitrates after 4 DMA transfer */
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ALD_DMA_R_POWER_8 = 0x3U, /**< Arbitrates after 8 DMA transfer */
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ALD_DMA_R_POWER_16 = 0x4U, /**< Arbitrates after 16 DMA transfer */
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ALD_DMA_R_POWER_32 = 0x5U, /**< Arbitrates after 32 DMA transfer */
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ALD_DMA_R_POWER_64 = 0x6U, /**< Arbitrates after 64 DMA transfer */
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ALD_DMA_R_POWER_128 = 0x7U, /**< Arbitrates after 128 DMA transfer */
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ALD_DMA_R_POWER_256 = 0x8U, /**< Arbitrates after 256 DMA transfer */
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ALD_DMA_R_POWER_512 = 0x9U, /**< Arbitrates after 512 DMA transfer */
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ALD_DMA_R_POWER_1024 = 0xAU, /**< Arbitrates after 1024 DMA transfer */
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} ald_dma_arbiter_config_t;
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/**
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* @brief Callback function pointer and param
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*/
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typedef struct {
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void (*cplt_tc_cbk)(void *arg); /**< DMA transfers complete callback */
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void (*cplt_ht_cbk)(void* arg); /**< DMA transfers half complete callback */
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void *cplt_tc_arg; /**< The parameter of cplt_tc_cbk() */
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void *cplt_ht_arg; /**< The parameter of cplt_ht_cbk() */
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} ald_dma_call_back_t;
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/**
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* @brief DMA channal configure structure
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*/
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typedef struct {
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void *src; /**< Source data begin pointer */
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void *dst; /**< Destination data begin pointer */
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uint16_t size; /**< The total number of DMA transfers that DMA cycle contains */
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ald_dma_data_size_t src_data_width; /**< Source data width */
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ald_dma_data_size_t dst_data_width; /**< Dest data width */
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ald_dma_data_inc_t src_inc; /**< Source increment type */
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ald_dma_data_inc_t dst_inc; /**< Destination increment type */
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ald_dma_arbiter_config_t R_power; /**< Control how many DMA transfers can occur before re-arbitrates */
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ald_dma_priority_t priority; /**< High priority or default priority */
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TypeFunc mem_to_mem; /**< Enable/disable memory to memory mode */
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TypeFunc circle_mode; /**< Enable/disable circular mode */
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ald_dma_msel_t msel; /**< Input source to DMA channel */
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ald_dma_msigsel_t msigsel; /**< Input signal to DMA channel */
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uint8_t channel; /**< Channel index */
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} ald_dma_config_t;
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/** @defgroup ALD_DMA_Public_Constants DMA Public Constants
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* @{
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*/
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/**
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* brief ALD_DMA_CHANNEL DMA channel
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*/
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#define ALD_DMA_CH_0 0x0U /**< Channel 0 */
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#define ALD_DMA_CH_1 0x1U /**< Channel 1 */
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#define ALD_DMA_CH_2 0x2U /**< Channel 2 */
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#define ALD_DMA_CH_3 0x3U /**< Channel 3 */
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#define ALD_DMA_CH_4 0x4U /**< Channel 4 */
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#define ALD_DMA_CH_5 0x5U /**< Channel 5 */
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#define ALD_DMA_CH_6 0x6U /**< Channel 6 */
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/**
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* @}
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*/
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/**
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* @brief DMA handle structure definition
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*/
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typedef struct {
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DMA_TypeDef *perh; /**< DMA registers base address */
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ald_dma_config_t config; /**< Channel configure structure. @ref dma_config_t */
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void (*cplt_tc_cbk)(void *arg); /**< DMA transfers complete callback */
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void (*cplt_ht_cbk)(void *arg); /**< DMA transfers half complete callback */
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void *cplt_tc_arg; /**< The parameter of cplt_tc_cbk() */
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void *cplt_ht_arg; /**< The parameter of cplt_ht_cbk() */
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} ald_dma_handle_t;
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/**
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* @}
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*/
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/**
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* @defgroup DMA_Private_Macros DMA Private Macros
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* @{
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*/
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#define IS_DMA_MSEL_TYPE(x) ((x) <= ALD_DMA_MSEL_BS16T)
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#define IS_DMA_MSIGSEL_TYPE(x) ((x) <= ALD_DMA_MSIGSEL_EXTI_15)
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#define IS_DMA_DATAINC_TYPE(x) (((x) == ALD_DMA_DATA_INC_DISABLE) || \
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((x) == ALD_DMA_DATA_INC_ENABLE))
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#define IS_DMA_DATASIZE_TYPE(x) (((x) == ALD_DMA_DATA_SIZE_BYTE) || \
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((x) == ALD_DMA_DATA_SIZE_HALFWORD) || \
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((x) == ALD_DMA_DATA_SIZE_WORD))
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#define IS_DMA_ARBITERCONFIG_TYPE(x) (((x) == ALD_DMA_R_POWER_1) || \
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((x) == ALD_DMA_R_POWER_2) || \
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((x) == ALD_DMA_R_POWER_4) || \
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((x) == ALD_DMA_R_POWER_8) || \
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((x) == ALD_DMA_R_POWER_16) || \
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((x) == ALD_DMA_R_POWER_32) || \
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((x) == ALD_DMA_R_POWER_64) || \
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((x) == ALD_DMA_R_POWER_128) || \
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((x) == ALD_DMA_R_POWER_256) || \
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((x) == ALD_DMA_R_POWER_512) || \
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((x) == ALD_DMA_R_POWER_1024))
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#define IS_DMA_PRIORITY_TYPE(x) (((x) == ALD_DMA_LOW_PRIORITY) || \
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((x) == ALD_DMA_MEDIUM_PRIORITY) || \
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((x) == ALD_DMA_HIGH_PRIORUTY) || \
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((x) == ALD_DMA_HIGHEST_PRIORITY))
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#define IS_DMA_IT_TYPE(x) (((x) == ALD_DMA_IT_FLAG_TC) || \
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((x) == ALD_DMA_IT_FLAG_HT))
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#define IS_DMA(x) ((x) == DMA)
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#define IS_DMA_CHANNEL(x) ((x) <= ALD_DMA_CH_6)
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#define IS_DMA_DATA_SIZE(x) ((x) <= 65535)
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/**
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* @}
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*/
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/**
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* @addtogroup DMA_Public_Functions
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* @{
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*/
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/** @addtogroup DMA_Public_Functions_Group1
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* @{
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*/
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/* Initialization functions */
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extern void ald_dma_config_base(ald_dma_config_t *config);
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extern void ald_dma_config_basic(ald_dma_handle_t *hperh);
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extern void ald_dma_config_basic_easy(void *src, void *dst, uint16_t size, ald_dma_msel_t msel,
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ald_dma_msigsel_t msigsel, uint8_t channel, void (*cbk)(void *arg));
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extern void ald_dma_irq_handler(void);
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extern void ald_dma_reset(void);
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extern void ald_dma_init(void);
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extern void ald_dma_config_struct(ald_dma_config_t *p);
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/**
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* @}
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*/
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/** @addtogroup DMA_Public_Functions_Group2
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* @{
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*/
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/* DMA control functions */
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extern void ald_dma_channel_config(uint8_t channel, type_func_t state);
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void ald_dma_interrupt_config(uint8_t channel, ald_dma_it_flag_t it, type_func_t state);
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extern it_status_t ald_dma_get_it_status(uint8_t channel, ald_dma_it_flag_t it);
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extern flag_status_t ald_dma_get_flag_status(uint8_t channel, ald_dma_it_flag_t it);
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extern void ald_dma_clear_flag_status(uint8_t channel, ald_dma_it_flag_t it);
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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/**
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* @}
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*/
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#ifdef __cplusplus
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}
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#endif /* __cplusplus */
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#endif /*__ALD_DMA_H__ */
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