267 lines
8.3 KiB
C
267 lines
8.3 KiB
C
/*
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* Copyright (c) 2016, Freescale Semiconductor, Inc.
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* Copyright 2016-2017 NXP
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*
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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*
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* o Redistributions of source code must retain the above copyright notice, this list
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* of conditions and the following disclaimer.
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*
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* o Redistributions in binary form must reproduce the above copyright notice, this
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* list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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*
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* o Neither the name of the copyright holder nor the names of its
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* contributors may be used to endorse or promote products derived from this
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* software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "fsl_phy.h"
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/*******************************************************************************
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* Definitions
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******************************************************************************/
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/*! @brief Defines the timeout macro. */
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#define PHY_TIMEOUT_COUNT 0xFFFFU
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/*******************************************************************************
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* Prototypes
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******************************************************************************/
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/*!
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* @brief Get the ENET instance from peripheral base address.
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*
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* @param base ENET peripheral base address.
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* @return ENET instance.
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*/
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extern uint32_t ENET_GetInstance(ENET_Type *base);
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/*******************************************************************************
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* Variables
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******************************************************************************/
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/*! @brief Pointers to enet clocks for each instance. */
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#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
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extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_ENET_COUNT];
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#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
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extern clock_ip_name_t s_enetClock[FSL_FEATURE_SOC_LPC_ENET_COUNT];
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#endif
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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/*******************************************************************************
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* Code
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******************************************************************************/
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status_t PHY_Init(ENET_Type *base, uint32_t phyAddr, uint32_t srcClock_Hz)
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{
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uint32_t reg;
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uint32_t idReg = 0;
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uint32_t delay = PHY_TIMEOUT_COUNT;
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uint32_t instance = ENET_GetInstance(base);
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#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
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/* Set SMI first. */
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CLOCK_EnableClock(s_enetClock[instance]);
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#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
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#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
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ENET_SetSMI(base, srcClock_Hz, false);
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#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
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ENET_SetSMI(base);
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#endif
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/* Initialization after PHY stars to work. */
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while ((idReg != PHY_CONTROL_ID1) && (delay != 0))
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{
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PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
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delay --;
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}
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if (!delay)
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{
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return kStatus_Fail;
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}
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delay = PHY_TIMEOUT_COUNT;
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/* Reset PHY and wait until completion. */
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PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, PHY_BCTL_RESET_MASK);
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do
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{
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PHY_Read(base, phyAddr, PHY_BASICCONTROL_REG, ®);
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} while (delay-- && reg & PHY_BCTL_RESET_MASK);
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if (!delay)
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{
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return kStatus_Fail;
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}
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/* Set the ability. */
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PHY_Write(base, phyAddr, PHY_AUTONEG_ADVERTISE_REG, (PHY_ALL_CAPABLE_MASK | 0x1U));
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/* Start Auto negotiation and wait until auto negotiation completion */
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PHY_Write(base, phyAddr, PHY_BASICCONTROL_REG, (PHY_BCTL_AUTONEG_MASK | PHY_BCTL_RESTART_AUTONEG_MASK));
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delay = PHY_TIMEOUT_COUNT;
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do
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{
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PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, ®);
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delay --;
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} while (delay && ((reg & PHY_SPECIALCTL_AUTONEGDONE_MASK) == 0));
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if (!delay)
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{
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return kStatus_Fail;
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}
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return kStatus_Success;
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}
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status_t PHY_Write(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t data)
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{
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#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
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uint32_t counter;
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/* Clear the SMI interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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/* Starts a SMI write command. */
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ENET_StartSMIWrite(base, phyAddr, phyReg, kENET_MiiWriteValidFrame, data);
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/* Wait for SMI complete. */
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for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
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{
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if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
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{
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break;
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}
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}
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/* Check for timeout. */
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if (!counter)
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{
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return kStatus_PHY_SMIVisitTimeout;
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}
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/* Clear MII interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
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ENET_StartSMIWrite(base, phyAddr, phyReg, data);
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while (ENET_IsSMIBusy(base))
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;
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#endif
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return kStatus_Success;
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}
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status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
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{
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#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
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assert(dataPtr);
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uint32_t counter;
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/* Clear the MII interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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/* Starts a SMI read command operation. */
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ENET_StartSMIRead(base, phyAddr, phyReg, kENET_MiiReadValidFrame);
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/* Wait for MII complete. */
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for (counter = PHY_TIMEOUT_COUNT; counter > 0; counter--)
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{
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if (ENET_GetInterruptStatus(base) & ENET_EIR_MII_MASK)
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{
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break;
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}
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}
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/* Check for timeout. */
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if (!counter)
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{
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return kStatus_PHY_SMIVisitTimeout;
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}
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/* Get data from MII register. */
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*dataPtr = ENET_ReadSMIData(base);
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/* Clear MII interrupt event. */
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ENET_ClearInterruptStatus(base, ENET_EIR_MII_MASK);
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#elif defined(FSL_FEATURE_SOC_LPC_ENET_COUNT) && (FSL_FEATURE_SOC_LPC_ENET_COUNT > 0)
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ENET_StartSMIRead(base, phyAddr, phyReg);
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while (ENET_IsSMIBusy(base))
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;
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*dataPtr = ENET_ReadSMIData(base);
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#endif
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return kStatus_Success;
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}
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status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
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{
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uint32_t reg;
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status_t result = kStatus_Success;
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/* Read the basic status register. */
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result = PHY_Read(base, phyAddr, PHY_BASICSTATUS_REG, ®);
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if (result == kStatus_Success)
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{
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if (reg & PHY_BSTATUS_LINKSTATUS_MASK)
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{
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/* link up. */
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*status = true;
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}
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else
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{
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*status = false;
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}
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}
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return result;
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}
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status_t PHY_GetLinkSpeedDuplex(ENET_Type *base, uint32_t phyAddr, phy_speed_t *speed, phy_duplex_t *duplex)
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{
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assert(duplex);
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assert(speed);
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uint32_t reg;
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status_t result = kStatus_Success;
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/* Read the control two register. */
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result = PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, ®);
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if (result == kStatus_Success)
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{
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if (reg & PHY_SPECIALCTL_DUPLEX_MASK)
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{
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/* Full duplex. */
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*duplex = kPHY_FullDuplex;
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}
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else
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{
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/* Half duplex. */
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*duplex = kPHY_HalfDuplex;
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}
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if (reg & PHY_SPECIALCTL_100SPEED_MASK)
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{
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/* 100M speed. */
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*speed = kPHY_Speed100M;
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}
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else
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{ /* 10M speed. */
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*speed = kPHY_Speed10M;
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}
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}
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return result;
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}
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