187 lines
6.8 KiB
C
187 lines
6.8 KiB
C
/* ------------------------------------------
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* Copyright (c) 2017, Synopsys, Inc. All rights reserved.
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* Redistribution and use in source and binary forms, with or without modification,
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* are permitted provided that the following conditions are met:
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* 1) Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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* 2) Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation and/or
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* other materials provided with the distribution.
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* 3) Neither the name of the Synopsys, Inc., nor the names of its contributors may
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* be used to endorse or promote products derived from this software without
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* specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
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* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* \version 2017.03
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* \date 2014-06-30
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* \author Huaqi Fang(Huaqi.Fang@synopsys.com)
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--------------------------------------------- */
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/**
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* \file
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* \ingroup DEVICE_DW_IIC
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* \brief DesignWare IIC driver hardware description related header file
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* \details detailed hardware related definitions of DesignWare IIC driver
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*/
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#ifndef _DEVICE_DW_IIC_HAL_H_
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#define _DEVICE_DW_IIC_HAL_H_
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#include "device/designware/iic/dw_iic_hal_cfg.h"
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/** Enable Designware IIC */
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#define DW_IIC_ENABLE (1)
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/** Disable Designware IIC */
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#define DW_IIC_DISABLE (0)
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/** Stop Condition issue after this byte */
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#define IC_DATA_CMD_STOP (1 << 9)
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/** Restart Condition issue after this byte */
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#define IC_DATA_CMD_RESTART (1 << 10)
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/** No Restart or stop condition after this byte */
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#define IC_DATA_CMD_NONE (0)
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/** Perform a write request */
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#define IC_DATA_CMD_WRITE_REQ (0)
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/** Perform a read request */
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#define IC_DATA_CMD_READ_REQ (1 << 8)
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/** Fields of IC_CON register */
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/* DW_APB I2C IP Config Dependencies. */
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#if DW_IIC_ALLOW_RESTART
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#define IC_CON_RESTART_EN (1 << 5)
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#else
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#define IC_CON_RESTART_EN (0x00)
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#endif
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/* Master Addressing Mode Config */
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#if DW_IIC_MST_10_BIT_ADDR_SUPPORT
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#define MST_10_BIT_ADDR_MODE (1 << 4)
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#define IC_10BITADDR_MASTER (1 << 12)
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#else
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#define MST_10_BIT_ADDR_MODE (0x00)
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#define IC_10BITADDR_MASTER (0x00)
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#endif
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/* Slave Addressing Mode Config */
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#if DW_IIC_SLV_10_BIT_ADDR_SUPPORT
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#define SLV_10_BIT_ADDR_MODE (1 << 3)
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#else
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#define SLV_10_BIT_ADDR_MODE (0x00)
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#endif
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#if DW_IIC_SPECIAL_START_BYTE
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#define IC_TAR_SPECIAL (1 << 11)
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#define IC_TAR_GC_OR_START (1 << 10)
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#else
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#define IC_TAR_SPECIAL (0x00)
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#define IC_TAR_GC_OR_START (0x00)
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#endif
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/** 7bit IIC address mask for target address register */
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#define IC_TAR_7BIT_ADDR_MASK (0x7F)
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/** 7bit IIC address mask for slave address register */
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#define IC_SAR_7BIT_ADDR_MASK (0x7F)
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/** 10bit IIC address mask for target address register */
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#define IC_TAR_10BIT_ADDR_MASK (0x3FF)
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/** 10bit IIC address mask for slave address register */
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#define IC_SAR_10BIT_ADDR_MASK (0x3FF)
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/** Speed modes of IC_CON */
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#define IC_CON_SPEED_MASK (0x6)
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#define IC_CON_SPEED_STANDARD (0x2)
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#define IC_CON_SPEED_FAST (0x4)
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#define IC_CON_SPEED_HIGH (0x6)
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/** Working mode of IC_CON */
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#define IC_CON_MST_SLV_MODE_MASK (0x41)
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#define IC_CON_ENA_MASTER_MODE (0x41)
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#define IC_CON_ENA_SLAVE_MODE (0)
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/* IIC interrupt control */
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#define IC_INT_DISABLE_ALL (0x0)
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#define IC_INT_ENABLE_ALL (0x7FF)
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/* Interrupt Register Fields */
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#define IC_INTR_STAT_GEN_CALL (1 << 11)
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#define IC_INTR_STAT_START_DET (1 << 10)
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#define IC_INTR_STAT_STOP_DET (1 << 9)
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#define IC_INTR_STAT_ACTIVITY (1 << 8)
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#define IC_INTR_STAT_RX_DONE (1 << 7)
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#define IC_INTR_STAT_TX_ABRT (1 << 6)
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#define IC_INTR_STAT_RD_REQ (1 << 5)
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#define IC_INTR_STAT_TX_EMPTY (1 << 4)
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#define IC_INTR_STAT_TX_OVER (1 << 3)
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#define IC_INTR_STAT_RX_FULL (1 << 2)
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#define IC_INTR_STAT_RX_OVER (1 << 1)
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#define IC_INTR_STAT_RX_UNDER (1 << 0)
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/* Interrupt enable mask as master */
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#define IC_INT_MST_TX_ENABLE (IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_TX_OVER|IC_INTR_STAT_TX_ABRT)
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#define IC_INT_MST_RX_ENABLE (IC_INTR_STAT_TX_EMPTY|IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER|IC_INTR_STAT_TX_ABRT)
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/* Interrupt enable mask as master */
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#define IC_INT_SLV_COMMON_ENABLE (IC_INTR_STAT_START_DET|IC_INTR_STAT_STOP_DET)
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#define IC_INT_SLV_TX_ENABLE (IC_INTR_STAT_RD_REQ|IC_INTR_STAT_TX_ABRT)
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#define IC_INT_SLV_RX_ENABLE (IC_INTR_STAT_RX_FULL|IC_INTR_STAT_RX_OVER|IC_INTR_STAT_RX_UNDER)
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/* IC_ENABLE_STATUS Bits */
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#define IC_ENABLE_STATUS_IC_EN (1 << 0)
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#define IC_ENABLE_STATUS_SLV_DIS (1 << 1)
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#define IC_ENABLE_STATUS_SLV_RX_LOST (1 << 2)
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/* IIC TX & RX threshold settings */
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#define IIC_TX_THRESHOLD (0)
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#define IIC_RX_THRESHOLD (0)
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/* DW_APB IIC (DW_IC_STATUS) Status Register Fields. */
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#define IC_STATUS_ACTIVITY (0x01)
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#define IC_STATUS_TFNF (0x02) /* (1 << 1) */
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#define IC_STATUS_TFE (0x04) /* (1 << 2) */
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#define IC_STATUS_RFNE (0x08) /* (1 << 3) */
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#define IC_STATUS_RFF (0x10) /* (1 << 4) */
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#define IC_STATUS_MASTER_ACT (0x20) /* (1 << 5) */
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#define IC_STATUS_SLAVE_ACT (0x40) /* (1 << 6) */
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/* IC_TX_ABRT_SOURCE Register Bit Fields */
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#define IC_TX_ABRT_7B_ADDR_NOACK (1 << 0)
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#define IC_TX_ABRT_10ADDR1_NOACK (1 << 1)
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#define IC_TX_ABRT_10ADDR2_NOACK (1 << 2)
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#define IC_TX_ABRT_TXDATA_NOACK (1 << 3)
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#define IC_TX_ABRT_GCALL_NOACK (1 << 4)
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#define IC_TX_ABRT_GCALL_READ (1 << 5)
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#define IC_TX_ABRT_HS_ACKDET (1 << 6)
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#define IC_TX_ABRT_SBYTE_ACKDET (1 << 7)
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#define IC_TX_ABRT_HS_NORSTRT (1 << 8)
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#define IC_TX_ABRT_SBYTE_NORSTRT (1 << 9)
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#define IC_TX_ABRT_10B_RD_NORSTRT (1 << 10)
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#define IC_TX_ABRT_MASTER_DIS (1 << 11)
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#define IC_TX_ABRT_ARB_LOST (1 << 12)
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#define IC_TX_ABRT_SLVFLUSH_TXFIFO (1 << 13)
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#define IC_TX_ABRT_SLV_ARBLOST (1 << 14)
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#define IC_TX_ABRT_SLVRD_INTX (1 << 15)
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/* Combined bits for iic abort source as master */
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#define IIC_MST_ABRT_ADDR_NOACK (IC_TX_ABRT_7B_ADDR_NOACK|IC_TX_ABRT_10ADDR1_NOACK|IC_TX_ABRT_10ADDR1_NOACK)
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#define IIC_MST_ABRT_LOST_BUS (IC_TX_ABRT_ARB_LOST)
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#define IIC_MST_ABRT_DATA_NOACK (IC_TX_ABRT_TXDATA_NOACK)
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/* Combined bits for iic abort source as slave */
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#define IIC_SLV_ABRT_LOST_BUS (IC_TX_ABRT_ARB_LOST|IC_TX_ABRT_SLV_ARBLOST)
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/** @} */
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#endif /* _DEVICE_DW_IIC_HAL_H_ */
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