375 lines
9.1 KiB
NASM
375 lines
9.1 KiB
NASM
;
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; Copyright (c) 2021, Shenzhen Academy of Aerospace Technology
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;
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; SPDX-License-Identifier: Apache-2.0
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;
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; Change Logs:
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; Date Author Notes
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; 2021-11-16 Dystopia the first version
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;
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;-----------------------------------------------------------
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; interrupt handler for C6678 DSP
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;-----------------------------------------------------------
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;-----------------------------------------------------------
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; macro definition
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;-----------------------------------------------------------
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DP .set B14
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SP .set B15
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;
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;-----------------------------------------------------------
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;
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;-----------------------------------------------------------
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; global function
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;-----------------------------------------------------------
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.global _nmi_handler
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.global _bad_handler
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.global _int4_handler
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.global _int5_handler
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.global _int6_handler
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.global _int7_handler
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.global _int8_handler
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.global _int9_handler
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.global _int10_handler
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.global _int11_handler
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.global _int12_handler
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.global _int13_handler
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.global _int14_handler
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.global _int15_handler
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;
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;-----------------------------------------------------------
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;
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;-----------------------------------------------------------
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; extern function
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;-----------------------------------------------------------
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.ref hw_nmi_handler
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.ref hw_bad_handler
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.ref hw_int4_handler
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.ref hw_int5_handler
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.ref hw_int6_handler
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.ref hw_int7_handler
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.ref hw_int8_handler
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.ref hw_int9_handler
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.ref hw_int10_handler
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.ref hw_int11_handler
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.ref hw_int12_handler
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.ref hw_int13_handler
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.ref hw_int14_handler
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.ref hw_int15_handler
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.ref rt_hw_process_exception
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.ref rt_interrupt_context_restore
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;
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;-----------------------------------------------------------
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;
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;
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;-----------------------------------------------------------
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;
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;-----------------------------------------------------------
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; macro definition
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;-----------------------------------------------------------
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SAVE_ALL .macro __rp, __tsr
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STDW .D2T2 SP:DP,*--SP[1]
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SUBAW .D2 SP,2,SP
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ADD .D1X SP,-8,A15
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|| STDW .D2T1 A15:A14,*SP--[16] ; save A15:A14
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STDW .D2T2 B13:B12,*SP--[1]
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|| STDW .D1T1 A13:A12,*A15--[1]
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|| MVC .S2 __rp,B13
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STDW .D2T2 B11:B10,*SP--[1]
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|| STDW .D1T1 A11:A10,*A15--[1]
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|| MVC .S2 CSR,B12
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STDW .D2T2 B9:B8,*SP--[1]
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|| STDW .D1T1 A9:A8,*A15--[1]
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|| MVC .S2 RILC,B11
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STDW .D2T2 B7:B6,*SP--[1]
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|| STDW .D1T1 A7:A6,*A15--[1]
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|| MVC .S2 ILC,B10
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STDW .D2T2 B5:B4,*SP--[1]
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|| STDW .D1T1 A5:A4,*A15--[1]
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STDW .D2T2 B3:B2,*SP--[1]
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|| STDW .D1T1 A3:A2,*A15--[1]
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|| MVC .S2 __tsr,B5
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STDW .D2T2 B1:B0,*SP--[1]
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|| STDW .D1T1 A1:A0,*A15--[1]
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|| MV .S1X B5,A5
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STDW .D2T2 B31:B30,*SP--[1]
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|| STDW .D1T1 A31:A30,*A15--[1]
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|| MVKL 1,A4
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STDW .D2T2 B29:B28,*SP--[1]
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|| STDW .D1T1 A29:A28,*A15--[1]
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STDW .D2T2 B27:B26,*SP--[1]
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|| STDW .D1T1 A27:A26,*A15--[1]
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STDW .D2T2 B25:B24,*SP--[1]
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|| STDW .D1T1 A25:A24,*A15--[1]
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STDW .D2T2 B23:B22,*SP--[1]
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|| STDW .D1T1 A23:A22,*A15--[1]
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STDW .D2T2 B21:B20,*SP--[1]
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|| STDW .D1T1 A21:A20,*A15--[1]
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STDW .D2T2 B19:B18,*SP--[1]
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|| STDW .D1T1 A19:A18,*A15--[1]
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STDW .D2T2 B17:B16,*SP--[1]
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|| STDW .D1T1 A17:A16,*A15--[1]
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STDW .D2T2 B13:B12,*SP--[1] ; save PC and CSR
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STDW .D2T2 B11:B10,*SP--[1] ; save RILC and ILC
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STDW .D2T1 A5:A4,*SP--[1] ; save TSR and orig A4
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.endm
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RESTORE_ALL .macro __rp, __tsr
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LDDW .D2T2 *++SP[1],B9:B8 ; get TSR (B9)
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LDDW .D2T2 *++SP[1],B11:B10 ; get RILC (B11) and ILC (B10)
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LDDW .D2T2 *++SP[1],B13:B12 ; get PC (B13) and CSR (B12)
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ADDAW .D1X SP,30,A15
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LDDW .D1T1 *++A15[1],A17:A16
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|| LDDW .D2T2 *++SP[1],B17:B16
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LDDW .D1T1 *++A15[1],A19:A18
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|| LDDW .D2T2 *++SP[1],B19:B18
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LDDW .D1T1 *++A15[1],A21:A20
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|| LDDW .D2T2 *++SP[1],B21:B20
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LDDW .D1T1 *++A15[1],A23:A22
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|| LDDW .D2T2 *++SP[1],B23:B22
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LDDW .D1T1 *++A15[1],A25:A24
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|| LDDW .D2T2 *++SP[1],B25:B24
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LDDW .D1T1 *++A15[1],A27:A26
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|| LDDW .D2T2 *++SP[1],B27:B26
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LDDW .D1T1 *++A15[1],A29:A28
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|| LDDW .D2T2 *++SP[1],B29:B28
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LDDW .D1T1 *++A15[1],A31:A30
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|| LDDW .D2T2 *++SP[1],B31:B30
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LDDW .D1T1 *++A15[1],A1:A0
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|| LDDW .D2T2 *++SP[1],B1:B0
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LDDW .D1T1 *++A15[1],A3:A2
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|| LDDW .D2T2 *++SP[1],B3:B2
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|| MVC .S2 B9,__tsr
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LDDW .D1T1 *++A15[1],A5:A4
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|| LDDW .D2T2 *++SP[1],B5:B4
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|| MVC .S2 B11,RILC
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LDDW .D1T1 *++A15[1],A7:A6
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|| LDDW .D2T2 *++SP[1],B7:B6
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|| MVC .S2 B10,ILC
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LDDW .D1T1 *++A15[1],A9:A8
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|| LDDW .D2T2 *++SP[1],B9:B8
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|| MVC .S2 B13,__rp
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LDDW .D1T1 *++A15[1],A11:A10
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|| LDDW .D2T2 *++SP[1],B11:B10
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|| MVC .S2 B12,CSR
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LDDW .D1T1 *++A15[1],A13:A12
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|| LDDW .D2T2 *++SP[1],B13:B12
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MV .D2X A15,SP
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LDDW .D2T1 *++SP[1],A15:A14
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B .S2 __rp ; return from interruption
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LDDW .D2T2 *+SP[1],SP:DP
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NOP 4
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.endm
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;-----------------------------------------------------------
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; interrupt macro definition
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;-----------------------------------------------------------
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RT_INTERRUPT_ENTRY .macro
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SAVE_ALL IRP,ITSR
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.endm
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RT_CALL_INT .macro __isr
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CALLP __isr,B3
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B .S1 rt_interrupt_context_restore
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NOP 5
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.endm
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;-----------------------------------------------------------
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; execption macro definition
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;-----------------------------------------------------------
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RT_EXECPTION_ENTRY .macro
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SAVE_ALL NRP,NTSR
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.endm
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RT_EXECPTION_EXIT .macro
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RESTORE_ALL NRP,NTSR
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.endm
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;
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;-----------------------------------------------------------
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;
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.sect ".text"
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;
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;-----------------------------------------------------------
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;
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;-----------------------------------------------------------
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; handler NMI interrupt
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;-----------------------------------------------------------
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_nmi_handler:
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;{
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RT_EXECPTION_ENTRY
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MVC .S2 EFR,B2
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CMPEQ .L2 1,B2,B2
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|| MVC .S2 TSR,B1
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MV .D1X B2,A2
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|| CLR .S2 B1,10,10,B1
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MVC .S2 B1,TSR
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[!A2] MVKL .S1 rt_hw_process_exception,A0
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||[B2] MVKL .S2 rt_hw_software_exception,B1
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[!A2] MVKH .S1 rt_hw_process_exception,A0
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||[B2] MVKH .S2 rt_hw_software_exception,B1
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[!B2] B .S2X A0
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[B2] B .S2 B1
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[!B2] ADDAW .D2 SP,2,B1
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[!B2] MV .D1X B1,A4
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ADDKPC .S2 ret_from_trap,B3,2
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;
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; return from trap
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;
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ret_from_trap:
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MV .D2X A4,B0
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[!B0] MVKL .S2 ret_from_exception,B3
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[!B0] MVKH .S2 ret_from_exception,B3
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[!B0] BNOP .S2 B3,5
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;
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; return from trap<61><70>restore exception context
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;
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ret_from_exception:
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RT_EXECPTION_EXIT
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;
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rt_hw_software_exception:
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MVKL .S1 rt_hw_process_exception,A0
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MVKH .S1 rt_hw_process_exception,A0
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B .S2X A0
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ADDAW .D2 SP,2,B1
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MV .D1X B1,A4
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ADDKPC .S2 ret_from_trap,B3,2
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NOP 2
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;}
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;-----------------------------------------------------------
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; handler bad interrupt
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;-----------------------------------------------------------
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_bad_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_bad_handler
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;}
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;-----------------------------------------------------------
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; handler INT4 interrupt
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;-----------------------------------------------------------
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_int4_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int4_handler
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;}
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;-----------------------------------------------------------
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; handler INT5 interrupt
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;-----------------------------------------------------------
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_int5_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int5_handler
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;}
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;-----------------------------------------------------------
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; handler INT6 interrupt
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;-----------------------------------------------------------
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_int6_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int6_handler
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;}
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;-----------------------------------------------------------
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; handler INT7 interrupt
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;-----------------------------------------------------------
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_int7_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int7_handler
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;}
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;-----------------------------------------------------------
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; handler INT8 interrupt
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;-----------------------------------------------------------
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_int8_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int8_handler
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;}
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;-----------------------------------------------------------
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; handler INT9 interrupt
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;-----------------------------------------------------------
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_int9_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int9_handler
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;}
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;-----------------------------------------------------------
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; handler INT10 interrupt
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;-----------------------------------------------------------
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_int10_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int10_handler
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;}
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;-----------------------------------------------------------
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; handler INT11 interrupt
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;-----------------------------------------------------------
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_int11_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int11_handler
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;}
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;-----------------------------------------------------------
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; handler INT12 interrupt
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;-----------------------------------------------------------
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_int12_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int12_handler
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;}
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;-----------------------------------------------------------
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; handler INT13 interrupt
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;-----------------------------------------------------------
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_int13_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int13_handler
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;}
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;-----------------------------------------------------------
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; handler INT14 interrupt
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;-----------------------------------------------------------
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_int14_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int14_handler
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;}
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;-----------------------------------------------------------
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; handler INT15 interrupt
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;-----------------------------------------------------------
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_int15_handler:
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;{
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RT_INTERRUPT_ENTRY
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RT_CALL_INT hw_int15_handler
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;}
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.end
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