ecf2d82159
* Synchronize the code of the rt mart branch to the master branch.
* TTY device
* Add lwP code from rt-smart
* Add vnode in DFS, but DFS will be re-write for rt-smart
* There are three libcpu for rt-smart:
* arm/cortex-a, arm/aarch64
* riscv64
Co-authored-by: Rbb666 <zhangbingru@rt-thread.com>
Co-authored-by: zhkag <zhkag@foxmail.com>
63 lines
1.4 KiB
C
63 lines
1.4 KiB
C
/*
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* Copyright (c) 2006-2020, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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*/
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#ifndef __DRV_UART_H__
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#define __DRV_UART_H__
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#include "riscv_io.h"
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/**
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* uart ns16550a
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* http://byterunner.com/16550.html
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*/
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/* TRANSMIT AND RECEIVE HOLDING REGISTER */
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#define UART_RHR 0
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#define UART_THR 0
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/* INTERRUPT ENABLE REGISTER */
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#define UART_IER 1
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#define UART_IER_RX_ENABLE (1 << 0)
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#define UART_IER_TX_ENABLE (1 << 1)
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/* FIFO CONTROL REGISTER */
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#define UART_FCR 2
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#define UART_FCR_FIFO_ENABLE (1 << 0)
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#define UART_FCR_FIFO_CLEAR (3 << 1)
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/* INTERRUPT STATUS REGISTER */
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#define UART_ISR 2
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/* LINE CONTROL REGISTER */
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#define UART_LCR 3
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#define UART_LCR_EIGHT_BITS (3 << 0)
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// special mode to set baud rate
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#define UART_LCR_BAUD_LATCH (1 << 7)
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/* LINE STATUS REGISTER */
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#define UART_LSR 5
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// input is waiting to be read from RHR
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#define UART_LSR_RX_READY (1 << 0)
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// THR can accept another character to send
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#define UART_LSR_TX_IDLE (1 << 5)
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#define UART_REFERENCE_CLOCK 1843200
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#define UART_DEFAULT_BAUDRATE 115200
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extern void *uart0_base;
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#define write8_uart0(idx, value) __raw_writeb(((rt_uint8_t)value), (void*)((size_t)uart0_base + (idx)))
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#define read8_uart0(idx) __raw_readb((void*)((size_t)uart0_base + (idx)))
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void rt_hw_uart_start_rx_thread();
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int rt_hw_uart_init(void);
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void drv_uart_puts(char *str); // for syscall
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#endif /* __DRV_UART_H__ */
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