287 lines
8.2 KiB
C
287 lines
8.2 KiB
C
/**************************************************************************//**
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* @file system_fm33lc0xx.c
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* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Source File for
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* Device FM33LC0XX
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* @version V2.00
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* @date 15. March 2021
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*
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* @note
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*
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******************************************************************************/
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/* Copyright (c) 2012 ARM LIMITED
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All rights reserved.
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Redistribution and use in source and binary forms, with or without
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modification, are permitted provided that the following conditions are met:
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- Redistributions of source code must retain the above copyright
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notice, this list of conditions and the following disclaimer.
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- Redistributions in binary form must reproduce the above copyright
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notice, this list of conditions and the following disclaimer in the
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documentation and/or other materials provided with the distribution.
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- Neither the name of ARM nor the names of its contributors may be used
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to endorse or promote products derived from this software without
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specific prior written permission.
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*
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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POSSIBILITY OF SUCH DAMAGE.
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---------------------------------------------------------------------------*/
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#include "system_fm33lc0xx.h"
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/*----------------------------------------------------------------------------
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DEFINES
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*----------------------------------------------------------------------------*/
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/*----------------------------------------------------------------------------
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Define clocks
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*----------------------------------------------------------------------------*/
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/* ToDo: add here your necessary defines for device initialization
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following is an example for different system frequencies */
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/*----------------------------------------------------------------------------
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Clock Variable definitions
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*----------------------------------------------------------------------------*/
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/* ToDo: initialize SystemCoreClock with the system core clock frequency value
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achieved after system intitialization.
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This means system core clock frequency after call to SystemInit() */
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uint32_t SystemCoreClock = __SYSTEM_CLOCK; /*!< System Clock Frequency (Core Clock)*/
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/*----------------------------------------------------------------------------
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Clock functions
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*----------------------------------------------------------------------------*/
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static uint32_t SystemPLLClockUpdate(void)
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{
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uint32_t clock = 0;
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// 时钟源
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switch ((RCC->PLLCR >> 1) & 0x1)
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{
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case 0:
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switch ((RCC->RCHFCR >> 16) & 0xf)
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{
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case 1: // 16M
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clock = 16000000;
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break;
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case 2: // 24M
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clock = 24000000;
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break;
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case 0: // 8M
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default:
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clock = 8000000;
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break;
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}
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break;
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case 1:
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clock = XTHF_VALUE;
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break;
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}
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// 分频
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switch ((RCC->PLLCR >> 0x4) & 0x7)
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{
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case 0: // 不分频
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clock /= 1;
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break;
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case 1: // 2分频
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clock /= 2;
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break;
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case 2: // 4分频
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clock /= 4;
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break;
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case 3: // 8分频
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clock /= 8;
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break;
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case 4: // 12分频
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clock /= 12;
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break;
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case 5: // 16分频
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clock /= 16;
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break;
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case 6: // 24分频
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clock /= 24;
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break;
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case 7: // 32分频
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clock /= 32;
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break;
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}
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// 倍频比
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clock = clock * (((RCC->PLLCR >> 16) & 0x7f) + 1);
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// 输出选择
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if ((RCC->PLLCR >> 3) & 0x1)
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{
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clock *= 2;
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}
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return clock;
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}
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void SystemCoreClockUpdate (void) /* Get Core Clock Frequency */
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{
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switch ((RCC->SYSCLKCR >> 0) & 0x7)
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{
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case 1: // XTHF
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SystemCoreClock = XTHF_VALUE;
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break;
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case 2: // PLL
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SystemCoreClock = SystemPLLClockUpdate();
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break;
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case 4: // RCMF
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switch ((RCC->RCMFCR >> 16) & 0x3)
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{
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case 0: // 不分频
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SystemCoreClock = 4000000;
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break;
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case 1: // 4分频
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SystemCoreClock = 1000000;
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break;
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case 2: // 8分频
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SystemCoreClock = 500000;
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break;
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case 3: // 16分频
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SystemCoreClock = 250000;
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break;
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}
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break;
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case 5: // LSCLK
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case 6: // LPOSC
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SystemCoreClock = 32768;
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break;
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case 7: // USBBCK
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switch ((RCC->SYSCLKCR >> 3) & 0x1)
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{
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case 0: // USBBCK 48M
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SystemCoreClock = 48000000;
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break;
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case 1: // USBBCK 120M 2分频
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SystemCoreClock = 60000000;
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break;
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}
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break;
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default:
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switch ((RCC->RCHFCR >> 16) & 0xf)
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{
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case 1: // 16M
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SystemCoreClock = 16000000;
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break;
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case 2: // 24M
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SystemCoreClock = 24000000;
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break;
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case 0: // 8M
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default:
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SystemCoreClock = 8000000;
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break;
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}
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break;
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}
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}
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/**
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* @brief NVIC_Init config NVIC
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*
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* @param NVIC_configStruct configParams
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*
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* @param IRQn Interrupt number
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*
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* @retval None
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*/
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void NVIC_Init(NVIC_ConfigTypeDef *NVIC_configStruct,IRQn_Type IRQn)
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{
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/* Params Check */
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if(NVIC_configStruct->preemptPriority>3)
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{
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NVIC_configStruct->preemptPriority = 3;
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}
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NVIC_DisableIRQ(IRQn);
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NVIC_SetPriority(IRQn,NVIC_configStruct->preemptPriority);
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NVIC_EnableIRQ(IRQn);
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}
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/**
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* Initialize the system
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*
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* @param none
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* @return none
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*
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* @brief Setup the microcontroller system.
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* Initialize the System.
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*/
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void SystemInit (void)
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{
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uint32_t temp;
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/* */
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RCC->PLLCR = (uint32_t)0x00000000U;
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RCC->SYSCLKCR = (uint32_t)0x0A000000U;
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/* PAD RCC*/
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RCC->PCLKCR1 |= (0x1U << 7U);
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#ifdef USE_LSCLK_CLOCK_SRC_XTLF
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GPIOD->FCR |= 0x3C0000;
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/* XTLF*/
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RCC->XTLFCR = (uint32_t)(0x00000000U);
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/* XTLF*/
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RCC->XTLFCR |= (uint32_t)(0x00000005U<<8);
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for(temp = 2000;temp>0;temp--);
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/* LSCLKXTLF*/
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RCC->LSCLKSEL = 0xAA;
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/* LSCXTLF*/
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RCC->SYSCLKCR |= 0x8000000U;
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#else
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RCC->SYSCLKCR &= 0x7FFFFFFU;
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RCC->LSCLKSEL = 0x55;
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#endif
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/*PDR*/
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RMU->PDRCR |=0x01;
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/*BOR*/
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RMU->BORCR &=0xFE;
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/* DEBUG IWDT WWDT */
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DBG->CR =0x03;
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RCC->RCHFTR = RCHF24M_TRIM;
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RCC->RCMFTR = RCMF4M_TRIM;
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RCC->LPOSCTR = LPOSC_TRIM;
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GPIOD->PUEN |= 0x3 << 7;
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/* DMA Flash Channel: Flash->RAM */
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RCC->PCLKCR2 |= 0x1 << 4;
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DMA->CH7CR |= 0x1 << 10;
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RCC->PCLKCR2 &= ~(0x1 << 4);
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}
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