261 lines
8.4 KiB
C
261 lines
8.4 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fsdmmc_hw.c
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* Date: 2022-02-10 14:53:42
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* LastEditTime: 2022-02-18 08:54:02
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* Description: This file contains macros that can be used to access the device.
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 zhugengyu 2021/12/2 init
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*/
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/***************************** Include Files *********************************/
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#include "fassert.h"
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#include "fdebug.h"
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#include "fsdmmc_hw.h"
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#include "fsdmmc.h"
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/************************** Constant Definitions *****************************/
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/**************************** Type Definitions *******************************/
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/************************** Variable Definitions *****************************/
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FSDMMC_DEBUG_TAG "FSDMMC-HW"
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#define FSDMMC_ERROR(format, ...) FT_DEBUG_PRINT_E(FSDMMC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FSDMMC_WARN(format, ...) FT_DEBUG_PRINT_W(FSDMMC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FSDMMC_INFO(format, ...) FT_DEBUG_PRINT_I(FSDMMC_DEBUG_TAG, format, ##__VA_ARGS__)
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#define FSDMMC_DEBUG(format, ...) FT_DEBUG_PRINT_D(FSDMMC_DEBUG_TAG, format, ##__VA_ARGS__)
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/************************** Function Prototypes ******************************/
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/**
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* @name: FSdmmcSoftwareReset
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* @msg: 完成软复位
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* @return {*}
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* @param {uintptr} base_addr FSDMMC控制器基地址
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* @param {int} retries 重试次数
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*/
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FError FSdmmcSoftwareReset(uintptr base_addr, int retries)
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{
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FASSERT(retries > 1);
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u32 reg_val;
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FSDMMC_SET_BIT(base_addr, FSDMMC_SOFTWARE_RESET_REG_OFFSET, FSDMMC_SOFTWARE_RESET_SRST);
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FSDMMC_CLR_BIT(base_addr, FSDMMC_SOFTWARE_RESET_REG_OFFSET, FSDMMC_SOFTWARE_RESET_SRST);
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do
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{
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reg_val = FSDMMC_READ_REG(base_addr, FSDMMC_STATUS_REG_OFFSET);
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}
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while (!(reg_val & FSDMMC_STATUS_IDIE) &&
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(retries-- > 0));
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if (!(reg_val & FSDMMC_STATUS_IDIE) && (retries <= 0))
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{
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FSDMMC_ERROR("Software reset timeout!!! status: 0x%x", reg_val);
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return FSDMMC_ERR_TIMEOUT;
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}
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return FSDMMC_SUCCESS;
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}
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/**
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* @name: FSdmmcSetCardClk
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* @msg: 设置FSDMMC的时钟
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* @return {*}
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* @param {uintptr} base_addr FSDMMC控制器基地址
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* @param {u32} clk_freq_hz 时钟频率，HZ
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*/
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FError FSdmmcSetCardClk(uintptr base_addr, u32 clk_freq_hz)
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{
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FSDMMC_WRITE_REG(base_addr, FSDMMC_CLOCK_DIV_REG_OFFSET, FSDMMC_CLK_DIVIDER(clk_freq_hz));
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FSDMMC_WRITE_REG(base_addr, FSDMMC_SD_DRV_REG_OFFSET, FSDMMC_DEFAULT_DRV);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_SD_SAMP_REG_OFFSET, FSDMMC_DEFAULT_SAMP);
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return FSdmmcSoftwareReset(base_addr, FSDMMC_TIMEOUT);
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}
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static const char *FSdmmcGetRespTypeStr(u32 hw_cmd)
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{
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const char *str;
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switch (FSDMMC_CMD_RESP_MASK & hw_cmd)
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{
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case FSDMMC_CMD_NO_RESP:
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str = "NONE";
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break;
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case FSDMMC_CMD_RESP_136_BIT:
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str = "LONG";
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break;
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case FSDMMC_CMD_RESP_48_BIT:
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str = "SHORT";
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break;
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case FSDMMC_CMD_RESP_48_BIT_BUSY_CHECK:
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str = "SHORT CHECK BUSY";
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break;
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default:
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FASSERT(0);
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}
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return str;
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}
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/**
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* @name: FSdmmcSendPrivateCmd
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* @msg: 发送命令
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* @return {*}
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* @param {uintptr} base_addr FSDMMC控制器基地址
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* @param {u32} cmd 待发送的命令
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* @param {u32} arg 待发送命令的参数
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*/
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void FSdmmcSendPrivateCmd(uintptr base_addr, u32 cmd, u32 arg)
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{
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/* 清空状态寄存器 */
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FSdmmcClearNormalInterruptStatus(base_addr);
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FSdmmcClearErrorInterruptStatus(base_addr);
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FSdmmcClearBDInterruptStatus(base_addr);
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/* 设置命令 */
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FSDMMC_WRITE_REG(base_addr, FSDMMC_CMD_SETTING_REG_OFFSET, cmd);
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FSDMMC_DATA_BARRIER();
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/* 设置参数，同时触发发送命令 */
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FSDMMC_WRITE_REG(base_addr, FSDMMC_ARGUMENT_REG_OFFSET, FSDMMC_ARGUMENT_MASK & arg);
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FSDMMC_INFO("CMD: 0x%08x ", FSDMMC_READ_REG(base_addr, FSDMMC_CMD_SETTING_REG_OFFSET));
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FSDMMC_INFO("ARG: 0x%08x", FSDMMC_READ_REG(base_addr, FSDMMC_ARGUMENT_REG_OFFSET));
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FSDMMC_INFO("RESP: %s", FSdmmcGetRespTypeStr(cmd));
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}
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/**
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* @name: FSdmmcReset
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* @msg: 重置FSDMMC控制器
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* @return {*}
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* @param {uintptr} base_addr FSDMMC控制器基地址
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*/
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FError FSdmmcReset(uintptr base_addr)
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{
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u32 reg_val;
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FError ret = FSDMMC_SUCCESS;
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ret = FSdmmcSoftwareReset(base_addr, FSDMMC_TIMEOUT);
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if (FSDMMC_SUCCESS != ret)
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{
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return ret;
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}
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/* set card detection */
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FSDMMC_WRITE_REG(base_addr, FSDMMC_SD_SEN_REG_OFFSET, 0x0);
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reg_val = FSDMMC_SEN_CREFR_VAL | FSDMMC_SEN_DEBNCE_VAL;
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FSDMMC_WRITE_REG(base_addr, FSDMMC_SD_SEN_REG_OFFSET, reg_val);
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/* configure cmd data timeout */
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FSDMMC_WRITE_REG(base_addr, FSDMMC_TIMEOUT_CMD_REG_OFFSET, FSDMMC_CMD_TIMEOUT);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_TIMEOUT_DATA_REG_OFFSET, FSDMMC_DATA_TIMEOUT);
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/* handle DMA cache */
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FSDMMC_WRITE_REG(base_addr, FSDMMC_HDS_AXI_REG_CONF1_REG_OFFSET, FSDMMC_AXI_CONF1);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_HDS_AXI_REG_CONF2_REG_OFFSET, FSDMMC_AXI_CONF2);
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/* set ending */
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reg_val = FSDMMC_PERMDW_STD_END | FSDMMC_PERMDR_STD_END;
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FSDMMC_WRITE_REG(base_addr, FSDMMC_CONTROLL_SETTING_REG_OFFSET, reg_val);
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/* disable interrupt */
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FSDMMC_WRITE_REG(base_addr, FSDMMC_NORMAL_INT_EN_REG_OFFSET, 0x0);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_ERROR_INT_EN_REG_OFFSET, 0x0);
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FSDMMC_WRITE_REG(base_addr, FSDMMC_BD_ISR_EN_REG_OFFSET, 0x0);
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/* clear interrupr status */
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FSdmmcClearNormalInterruptStatus(base_addr);
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FSdmmcClearErrorInterruptStatus(base_addr);
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FSdmmcClearBDInterruptStatus(base_addr);
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return ret;
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}
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/**
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* @name: FSdmmcWaitStatus
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* @msg: 等待命令完成或者命令错误状态
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* @return {*}
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* @param {uintptr} base_addr FSDMMC控制器基地址
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* @param {int} retries 重试次数
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*/
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FError FSdmmcWaitStatus(uintptr base_addr, int retries)
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{
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FASSERT(retries > 1);
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const u32 status_mask = FSDMMC_NORMAL_INT_STATUS_CC | FSDMMC_NORMAL_INT_STATUS_EI; /* 等待命令完成或者发生错误 */
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u32 status;
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do
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{
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status = status_mask & FSDMMC_READ_REG(base_addr, FSDMMC_NORMAL_INT_STATUS_REG_OFFSET);
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}
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while ((!status) && (retries-- > 0));
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if (FSDMMC_NORMAL_INT_STATUS_EI & status)
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{
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FSDMMC_ERROR("Error status: 0x%x, remain retries: %d", status, retries);
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FSdmmcReset(base_addr);
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return FSDMMC_ERR_CMD_FAILED;
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}
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else if (0 >= retries)
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{
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FSDMMC_ERROR("Wait timeout!!! status 0x%x", status);
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return FSDMMC_ERR_TIMEOUT;
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}
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return FSDMMC_SUCCESS;
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}
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/**
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* @name: FSdmmcWaitDMAStatus
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* @msg: 等待数据传输完成或者传输错误状态
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* @return {*}
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* @param {uintptr} base_addr FSDMMC控制器基地址
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* @param {boolean} read TRUE: 当前是读数据 FALSE: 当前是写数据
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* @param {int} retries 重试次数
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*/
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FError FSdmmcWaitDMAStatus(uintptr base_addr, boolean read, int retries)
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{
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const u32 status_mask = read ?
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(FSDMMC_BD_ISR_REG_RESPE | FSDMMC_BD_ISR_REG_DAIS) : /* 等待DMA传输完成或者发生错误 */
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(FSDMMC_BD_ISR_REG_TRS | FSDMMC_BD_ISR_REG_DAIS); /* 等待DMA传输完成或者发生错误 */
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u32 status;
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/* 等待DMA传输完成或者发生错误 */
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do
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{
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status = status_mask & FSDMMC_READ_REG(base_addr, FSDMMC_BD_ISR_REG_OFFSET);
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}
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while ((!status) && (retries-- > 0));
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if (status & FSDMMC_BD_ISR_REG_DAIS)
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{
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FSDMMC_ERROR("BD Data error when %s blk!", read ? "read" : "write");
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FSdmmcReset(base_addr);
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return FSDMMC_ERR_DATA_FAILED;
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}
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else if (0 >= retries)
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{
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FSDMMC_ERROR("BD Data timeout !!!");
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return FSDMMC_ERR_TIMEOUT;
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}
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return FSDMMC_SUCCESS;
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} |