148 lines
4.0 KiB
C
148 lines
4.0 KiB
C
/*
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* File : board.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2015 RT-Thread Develop Team
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*
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* The license and distribution terms for this file may be
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* found in the file LICENSE in this distribution or at
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* http://www.rt-thread.org/license/LICENSE
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*
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* Change Logs:
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* Date Author Notes
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* 2009-01-05 Bernard first implementation
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "board.h"
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#include "drv_usart.h"
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#include "drv_mpu.h"
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/**
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* @addtogroup STM32
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*/
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/**
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* @brief System Clock Configuration
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* The system Clock is configured as follow :
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* System Clock source = PLL (HSE)
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* SYSCLK(Hz) = 200000000
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* HCLK(Hz) = 200000000
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* AHB Prescaler = 1
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* APB1 Prescaler = 4
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* APB2 Prescaler = 2
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* HSE Frequency(Hz) = 25000000
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* PLL_M = 25
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* PLL_N = 400
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* PLL_P = 2
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* PLLSAI_N = 384
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* PLLSAI_P = 8
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* VDD(V) = 3.3
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* Main regulator output voltage = Scale1 mode
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* Flash Latency(WS) = 6
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* @param None
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* @retval None
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*/
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static void SystemClock_Config(void)
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{
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RCC_ClkInitTypeDef RCC_ClkInitStruct;
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RCC_OscInitTypeDef RCC_OscInitStruct;
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HAL_StatusTypeDef ret = HAL_OK;
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/* Enable HSE Oscillator and activate PLL with HSE as source */
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RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
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RCC_OscInitStruct.HSEState = RCC_HSE_ON;
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RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
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RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
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RCC_OscInitStruct.PLL.PLLM = 25;
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RCC_OscInitStruct.PLL.PLLN = 400;
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RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2;
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HAL_RCC_OscConfig(&RCC_OscInitStruct);
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ret = HAL_PWREx_EnableOverDrive();
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if(ret != HAL_OK)
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{
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while(1) { ; }
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}
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/* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2
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clocks dividers */
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RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
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RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
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RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1;
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RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4;
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RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2;
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HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_6);
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}
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/**
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* @brief CPU L1-Cache enable.
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* @param None
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* @retval None
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*/
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static void CPU_CACHE_Enable(void)
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{
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/* Enable branch prediction */
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SCB->CCR |= (1 <<18);
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__DSB();
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/* Enable I-Cache */
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SCB_EnableICache();
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/* Enable D-Cache */
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SCB_EnableDCache();
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}
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/**
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* This is the timer interrupt service routine.
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*
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*/
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void SysTick_Handler(void)
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{
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/* tick for HAL Library */
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HAL_IncTick();
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/* enter interrupt */
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rt_interrupt_enter();
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/**
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* This function will initial STM32 board.
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*/
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void rt_hw_board_init()
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{
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/* Configure the MPU attributes as Write Through */
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mpu_init();
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/* Enable the CPU Cache */
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CPU_CACHE_Enable();
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/* STM32F7xx HAL library initialization:
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- Configure the Flash ART accelerator on ITCM interface
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- Configure the Systick to generate an interrupt each 1 msec
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- Set NVIC Group Priority to 4
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- Global MSP (MCU Support Package) initialization
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*/
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HAL_Init();
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/* Configure the system clock @ 200 Mhz */
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SystemClock_Config();
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/* init systick */
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SysTick_Config(SystemCoreClock / RT_TICK_PER_SECOND);
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/* set pend exception priority */
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NVIC_SetPriority(PendSV_IRQn, (1 << __NVIC_PRIO_BITS) - 1);
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stm32_hw_usart_init();
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#ifdef RT_USING_CONSOLE
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rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
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#endif
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}
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/*@}*/
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