274 lines
9.5 KiB
C
274 lines
9.5 KiB
C
/*
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* Copyright : (C) 2022 Phytium Information Technology, Inc.
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* All Rights Reserved.
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*
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* This program is OPEN SOURCE software: you can redistribute it and/or modify it
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* under the terms of the Phytium Public License as published by the Phytium Technology Co.,Ltd,
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* either version 1.0 of the License, or (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,but WITHOUT ANY WARRANTY;
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* without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
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* See the Phytium Public License for more details.
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*
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*
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* FilePath: fi2c_hw.h
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* Date: 2021-11-01 14:53:42
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* LastEditTime: 2022-02-18 08:36:32
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* Description: This file is for I2C register definition
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*
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* Modify History:
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* Ver Who Date Changes
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* ----- ------ -------- --------------------------------------
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* 1.0 zhugengyu 2021/11/1 first commit
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* 1.1 liushengming 2022/02/18 add fi2c_slave mode
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*/
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#ifndef FI2C_HW_H
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#define FI2C_HW_H
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/* - 传入模块基地址，不能复杂结构体
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- hardware interface of device || low-level driver function prototypes
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- 包括驱动寄存器参数和low-level操作定义
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1. 定义寄存器偏移
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2. 对上提供该模块寄存器操作的接口
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3. 一些简单外设提供直接操作接口
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4. 可以定义一些状态的接口，用于响应驱动状态的变化 */
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/***************************** Include Files *********************************/
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#include "fparameters.h"
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#include "fio.h"
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#include "ferror_code.h"
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#include "fkernel.h"
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#ifdef __cplusplus
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extern "C"
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{
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#endif
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/************************** Constant Definitions *****************************/
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/** @name Register Map
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*
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* Register offsets from the base address of an I2C device.
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* @{
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*/
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#define FI2C_CON_OFFSET 0x00
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#define FI2C_TAR_OFFSET 0x04
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#define FI2C_SAR_OFFSET 0x08
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#define FI2C_HS_MADDR_OFFSET 0x0C
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#define FI2C_DATA_CMD_OFFSET 0x10
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#define FI2C_SS_SCL_HCNT_OFFSET 0x14
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#define FI2C_SS_SCL_LCNT_OFFSET 0x18
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#define FI2C_FS_SCL_HCNT_OFFSET 0x1C
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#define FI2C_FS_SCL_LCNT_OFFSET 0x20
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#define FI2C_HS_SCL_HCNT_OFFSET 0x24
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#define FI2C_HS_SCL_LCNT_OFFSET 0x28
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#define FI2C_INTR_STAT_OFFSET 0x2C
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#define FI2C_INTR_MASK_OFFSET 0x30
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#define FI2C_RAW_INTR_STAT_OFFSET 0x34
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#define FI2C_RX_TL_OFFSET 0x38
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#define FI2C_TX_TL_OFFSET 0x3C
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#define FI2C_CLR_INTR_OFFSET 0x40
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#define FI2C_CLR_RX_UNDER_OFFSET 0x44
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#define FI2C_CLR_RX_OVER_OFFSET 0x48
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#define FI2C_CLR_TX_OVER_OFFSET 0x4C
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#define FI2C_CLR_RD_REQ_OFFSET 0x50
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#define FI2C_CLR_TX_ABRT_OFFSET 0x54
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#define FI2C_CLR_RX_DONE_OFFSET 0x58
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#define FI2C_CLR_ACTIVITY_OFFSET 0x5c
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#define FI2C_CLR_STOP_DET_OFFSET 0x60
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#define FI2C_CLR_START_DET_OFFSET 0x64
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#define FI2C_CLR_GEN_CALL_OFFSET 0x68
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#define FI2C_ENABLE_OFFSET 0x6C
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#define FI2C_STATUS_OFFSET 0x70
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#define FI2C_TXFLR_OFFSET 0x74
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#define FI2C_RXFLR_OFFSET 0x78
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#define FI2C_SDA_HOLD_OFFSET 0x7c
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#define FI2C_TX_ABRT_SOURCE_OFFSET 0x80
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#define FI2C_SLV_DATA_NACK_ONLY_OFFSET 0x84
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#define FI2C_DMA_CR_OFFSET 0x88
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#define FI2C_DMA_TDLR_OFFSET 0x8c
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#define FI2C_DMA_RDLR_OFFSET 0x90
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#define FI2C_SDA_SETUP_OFFSET 0x94
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#define FI2C_ACK_GENERAL_CALL_OFFSET 0x98
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#define FI2C_ENABLE_STATUS_OFFSET 0x9C
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#define FI2C_FS_SPKLEN_OFFSET 0xa0
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#define FI2C_HS_SPKLEN_OFFSET 0xa4
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#define FI2C_COMP_PARAM_1_OFFSET 0xf4
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#define FI2C_COMP_VERSION_OFFSET 0xf8
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#define FI2C_COMP_TYPE_OFFSET 0xfc
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/** @name FI2C_CON_OFFSET Register
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*/
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#define FI2C_CON_MASTER_MODE (0x1 << 0)
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#define FI2C_CON_SLAVE_MODE (0x0 << 0)
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#define FI2C_CON_SPEED_MASK GENMASK(2, 1)
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#define FI2C_CON_STD_SPEED (0x1 << 1)
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#define FI2C_CON_FAST_SPEED (0x2 << 1)
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#define FI2C_CON_HIGH_SPEED (0x3 << 1)
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/* for slave mode */
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#define FI2C_CON_SLAVE_ADR_7BIT (0x0 << 3)
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#define FI2C_CON_SLAVE_ADR_10BIT (0x1 << 3)
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/* for master mode */
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#define FI2C_CON_MASTER_ADR_7BIT (0x0 << 4)
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#define FI2C_CON_MASTER_ADR_10BIT (0x1 << 4)
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#define FI2C_CON_RESTART_EN (0x1 << 5)
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#define FI2C_CON_SLAVE_DISABLE (0x1 << 6)
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/** @name FI2C_TAR_OFFSET Register
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*/
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#define FI2C_IC_TAR_MASK GENMASK(9, 0)
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#define FI2C_GC_OR_START (0x1 << 10)
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#define FI2C_SPECIAL (0x1 << 11)
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#define FI2C_TAR_ADR_7BIT (0x0 << 12)
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#define FI2C_TAR_ADR_10BIT (0x1 << 12)
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/** @name FI2C_SAR_OFFSET Register
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*/
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#define FI2C_IC_SAR_MASK GENMASK(9, 0) //Slave addr when in slave mode
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/** @name FI2C_HS_MADDR_OFFSET Register
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*/
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#define FI2C_IC_HS_MAR GENMASK(2, 0) //I2C High Speed模式主机编码
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/** @name FI2C_DATA_CMD_OFFSET Register
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*/
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#define FI2C_DATA_MASK GENMASK(7, 0)
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#define FI2C_DATA_CMD_READ (0x1 << 8)
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#define FI2C_DATA_CMD_WRITE (0x0 << 8)
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#define FI2C_DATA_CMD_STOP (0x1 << 9)
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#define FI2C_DATA_CMD_RESTART (0x1 << 10)
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/** @name FI2C_INTR_STAT_OFFSET Register
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* @name FI2C_INTR_MASK_OFFSET Register
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* @name FI2C_RAW_INTR_STAT_OFFSET Register
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*/
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#define FI2C_INTR_RX_UNDER (0x1 << 0) /* 接收缓冲区为空 */
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#define FI2C_INTR_RX_OVER (0x1 << 1) /* 接收缓冲区大小达到 IC_RX_BUFFER_DEPTH ，且还继续从外部接收数据 */
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#define FI2C_INTR_RX_FULL (0x1 << 2) /* 接收缓冲区大于等于 IC_RX_TL 中设定的门限值（RX_TL) */
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#define FI2C_INTR_TX_OVER (0x1 << 3) /* 发送缓冲区大小达到 IC_TX_BUFFER_DEPTH，并且还在尝试写数据 */
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#define FI2C_INTR_TX_EMPTY (0x1 << 4) /* 发送缓冲区小于等于 IC_TX_TL 寄存器中设定的门限值 */
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#define FI2C_INTR_RD_REQ (0x1 << 5) /* 读请求标志 */
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#define FI2C_INTR_TX_ABRT (0x1 << 6) /* I2C 不能完成FIFO内容的传输 */
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#define FI2C_INTR_RX_DONE (0x1 << 7) /* Slave工作模式下，规定时间内没有Master的回应，通信结束 */
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#define FI2C_INTR_ACTIVITY (0x1 << 8) /* I2C 控制器的活动状态 */
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#define FI2C_INTR_STOP_DET (0x1 << 9) /* I2C 总线接口上是否产生了 STOP */
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#define FI2C_INTR_START_DET (0x1 << 10) /* I2C 总线接口上是否产生了 START 或 RESTART */
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#define FI2C_INTR_GEN_CALL (0x1 << 11) /* I2C 总线接口上接收并识别到General Call格式 */
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#define FI2C_INTR_ALL_MASK 0x8FF
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#define FI2C_INTR_MASTER_WR_MASK (FI2C_INTR_TX_EMPTY | FI2C_INTR_TX_ABRT)
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#define FI2C_INTR_MASTER_RD_MASK (FI2C_INTR_MASTER_WR_MASK | FI2C_INTR_RX_FULL)
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#define FI2C_INTR_SLAVE_DEF_MASK (FI2C_INTR_RX_FULL | FI2C_INTR_STOP_DET | \
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FI2C_INTR_RD_REQ | FI2C_INTR_RX_DONE | \
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FI2C_INTR_RX_UNDER | FI2C_INTR_TX_ABRT |\
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FI2C_INTR_START_DET)
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/** @name FI2C_RX_TL_OFFSET Register
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*/
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#define FI2C_RX_TL_MASK GENMASK(7, 0)
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/** @name FI2C_TX_TL_OFFSET Register
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*/
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#define FI2C_TX_TL_MASK GENMASK(7, 0)
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/** @name FI2C_IC_ENABLE_OFFSET Register
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*/
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#define FI2C_ENABLE_CONTROLLER (0x1 << 0)
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#define FI2C_DISABLE_CONTROLLER (0x0 << 0)
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/** @name FI2C_STATUS_OFFSET Register
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*/
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#define FI2C_STATUS_ACTIVITY (0x1 << 0)
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#define FI2C_STATUS_TFNF (0x1 << 1)
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#define FI2C_STATUS_TFE (0x1 << 2)
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#define FI2C_STATUS_RFNE (0x1 << 3)
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#define FI2C_STATUS_RFF (0x1 << 4)
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#define FI2C_STATUS_MST_ACTIVITY (0x1 << 5)
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#define FI2C_STATUS_SLV_ACTIVITY (0x1 << 6)
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/** @name FI2C_ENABLE_OFFSET Register
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*/
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#define FI2C_IC_ENABLE (0x1 << 0)
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#define FI2C_IC_DISABLE (0x0 << 0)
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#define FI2C_IC_ENABLE_MASK (0x1 << 0)
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#define FI2C_SLV_DISABLED_WHILE_BUSY (0x1 << 1)
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#define FI2C_SLV_RX_DATA_LOST (0x1 << 2)
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/* High and low times in different speed modes (in ns) */
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#define FI2C_MIN_SS_SCL_HIGHTIME 4000
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#define FI2C_MIN_SS_SCL_LOWTIME 4700
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#define FI2C_MIN_FS_SCL_HIGHTIME 600
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#define FI2C_MIN_FS_SCL_LOWTIME 1300
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#define FI2C_MIN_FP_SCL_HIGHTIME 500
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#define FI2C_MIN_FP_SCL_LOWTIME 500
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#define FI2C_MIN_HS_SCL_HIGHTIME 60
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#define FI2C_MIN_HS_SCL_LOWTIME 160
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#define FI2C_DEFAULT_SDA_HOLD_TIME 300
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#define FI2C_READ_REG32(addr, reg_offset) FtIn32((addr) + (u32)(reg_offset))
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#define FI2C_WRITE_REG32(addr, reg_offset, reg_value) FtOut32((addr) + (u32)(reg_offset), (u32)(reg_value))
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#define FI2C_IIC_FIFO_MAX_LV 8
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/**************************** Type Definitions *******************************/
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/************************** Variable Definitions *****************************/
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enum
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{
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FI2C_STANDARD_SPEED = 0,
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FI2C_FAST_SPEED,
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FI2C_SPEED_MODE_MAX
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};
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/***************** Macros (Inline Functions) Definitions *********************/
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#define FI2C_GET_INTRRUPT_MASK(addr) FI2C_READ_REG32((addr), FI2C_INTR_MASK_OFFSET)
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#define FI2C_SET_INTRRUPT_MASK(addr, mask) FI2C_WRITE_REG32((addr), FI2C_INTR_MASK_OFFSET, (mask))
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#define FI2C_CLEAR_INTR_STATUS(addr) FI2C_READ_REG32((addr), FI2C_CLR_INTR_OFFSET)
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#define FI2C_GET_STATUS(addr) FI2C_READ_REG32((addr), FI2C_STATUS_OFFSET)
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#define FI2C_READ_DATA(addr) (u8)(FI2C_DATA_MASK & FI2C_READ_REG32(addr, FI2C_DATA_CMD_OFFSET))
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#define FI2C_WRITE_DATA(addr, dat) FI2C_WRITE_REG32((addr), FI2C_DATA_CMD_OFFSET, (dat))
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#define FI2C_SET_RX_TL(addr, level) FI2C_WRITE_REG32((addr), FI2C_RX_TL_OFFSET, (level))
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#define FI2C_SET_TX_TL(addr, level) FI2C_WRITE_REG32((addr), FI2C_TX_TL_OFFSET, (level))
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#define FI2C_READ_INTR_STAT(addr) FI2C_READ_REG32((addr), FI2C_INTR_STAT_OFFSET)
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#define FI2C_READ_RAW_INTR_STAT(addr) FI2C_READ_REG32((addr), FI2C_RAW_INTR_STAT_OFFSET)
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inline static u32 FI2cGetEnable(uintptr addr)
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{
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return FI2C_READ_REG32(addr, FI2C_ENABLE_STATUS_OFFSET);
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}
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/************************** Function Prototypes ******************************/
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FError FI2cSetEnable(uintptr addr, boolean enable);
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FError FI2cSetSpeed(uintptr addr, u32 speed_rate);
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FError FI2cWaitStatus(uintptr addr, u32 stat_bit);
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FError FI2cWaitBusBusy(uintptr addr);
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FError FI2cSetTar(uintptr addr, u32 tar_addr);
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FError FI2cSetSar(uintptr addr, u32 sar_addr);
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FError FI2cFlushRxFifo(uintptr addr);
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u32 FI2cClearIntrBits(uintptr addr, u32 *last_err_p);
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#ifdef __cplusplus
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}
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#endif
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#endif |