657 lines
16 KiB
C
657 lines
16 KiB
C
/*
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* File : i2c-davinci.c
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* This file is part of RT-Thread RTOS
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* COPYRIGHT (C) 2006, RT-Thread Development Team
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License along
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* with this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Change Logs:
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* Date Author Notes
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* 2011-01-13 weety first version
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*/
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#include <rtthread.h>
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#include <drivers/i2c.h>
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#include <dm36x.h>
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/* ----- global defines ----------------------------------------------- */
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#define BIT(nr) (1UL << (nr))
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#define DAVINCI_I2C_TIMEOUT (1*RT_TICK_PER_SECOND)
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#define DAVINCI_I2C_MAX_TRIES 2
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#define I2C_DAVINCI_INTR_ALL (DAVINCI_I2C_IMR_AAS | \
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DAVINCI_I2C_IMR_SCD | \
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DAVINCI_I2C_IMR_ARDY | \
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DAVINCI_I2C_IMR_NACK | \
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DAVINCI_I2C_IMR_AL)
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#define DAVINCI_I2C_OAR_REG 0x00
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#define DAVINCI_I2C_IMR_REG 0x04
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#define DAVINCI_I2C_STR_REG 0x08
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#define DAVINCI_I2C_CLKL_REG 0x0c
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#define DAVINCI_I2C_CLKH_REG 0x10
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#define DAVINCI_I2C_CNT_REG 0x14
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#define DAVINCI_I2C_DRR_REG 0x18
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#define DAVINCI_I2C_SAR_REG 0x1c
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#define DAVINCI_I2C_DXR_REG 0x20
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#define DAVINCI_I2C_MDR_REG 0x24
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#define DAVINCI_I2C_IVR_REG 0x28
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#define DAVINCI_I2C_EMDR_REG 0x2c
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#define DAVINCI_I2C_PSC_REG 0x30
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#define DAVINCI_I2C_IVR_AAS 0x07
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#define DAVINCI_I2C_IVR_SCD 0x06
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#define DAVINCI_I2C_IVR_XRDY 0x05
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#define DAVINCI_I2C_IVR_RDR 0x04
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#define DAVINCI_I2C_IVR_ARDY 0x03
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#define DAVINCI_I2C_IVR_NACK 0x02
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#define DAVINCI_I2C_IVR_AL 0x01
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#define DAVINCI_I2C_STR_BB BIT(12)
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#define DAVINCI_I2C_STR_RSFULL BIT(11)
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#define DAVINCI_I2C_STR_SCD BIT(5)
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#define DAVINCI_I2C_STR_ARDY BIT(2)
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#define DAVINCI_I2C_STR_NACK BIT(1)
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#define DAVINCI_I2C_STR_AL BIT(0)
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#define DAVINCI_I2C_MDR_NACK BIT(15)
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#define DAVINCI_I2C_MDR_STT BIT(13)
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#define DAVINCI_I2C_MDR_STP BIT(11)
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#define DAVINCI_I2C_MDR_MST BIT(10)
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#define DAVINCI_I2C_MDR_TRX BIT(9)
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#define DAVINCI_I2C_MDR_XA BIT(8)
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#define DAVINCI_I2C_MDR_RM BIT(7)
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#define DAVINCI_I2C_MDR_IRS BIT(5)
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#define DAVINCI_I2C_IMR_AAS BIT(6)
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#define DAVINCI_I2C_IMR_SCD BIT(5)
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#define DAVINCI_I2C_IMR_XRDY BIT(4)
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#define DAVINCI_I2C_IMR_RRDY BIT(3)
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#define DAVINCI_I2C_IMR_ARDY BIT(2)
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#define DAVINCI_I2C_IMR_NACK BIT(1)
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#define DAVINCI_I2C_IMR_AL BIT(0)
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#ifdef RT_EDMA_DEBUG
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#define i2c_dbg(fmt, ...) rt_kprintf(fmt, ##__VA_ARGS__)
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#else
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#define i2c_dbg(fmt, ...)
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#endif
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struct davinci_i2c_dev {
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void *base;
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struct rt_semaphore completion;
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struct clk *clk;
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int cmd_err;
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rt_uint8_t *buf;
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rt_uint32_t buf_len;
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int irq;
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int stop;
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rt_uint8_t terminate;
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rt_uint32_t bus_freq;
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rt_uint32_t bus_delay;
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struct rt_i2c_bus_device *bus;
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};
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static inline void davinci_i2c_write_reg(struct davinci_i2c_dev *i2c_dev,
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int reg, rt_uint16_t val)
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{
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davinci_writew(val, i2c_dev->base + reg);
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}
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static inline rt_uint16_t davinci_i2c_read_reg(struct davinci_i2c_dev *i2c_dev, int reg)
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{
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return davinci_readw(i2c_dev->base + reg);
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}
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static void udelay (rt_uint32_t us)
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{
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rt_int32_t i;
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for (; us > 0; us--)
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{
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i = 50000;
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while(i > 0)
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{
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i--;
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}
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}
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}
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#if 0
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/* Generate a pulse on the i2c clock pin. */
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static void generic_i2c_clock_pulse(unsigned int scl_pin)
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{
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rt_uint16_t i;
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if (scl_pin) {
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/* Send high and low on the SCL line */
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for (i = 0; i < 9; i++) {
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gpio_set_value(scl_pin, 0);
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udelay(20);
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gpio_set_value(scl_pin, 1);
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udelay(20);
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}
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}
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}
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#endif
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/* This routine does i2c bus recovery as specified in the
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* i2c protocol Rev. 03 section 3.16 titled "Bus clear"
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*/
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static void i2c_recover_bus(struct davinci_i2c_dev *dev)
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{
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rt_uint32_t flag = 0;
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i2c_dbg("initiating i2c bus recovery\n");
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/* Send NACK to the slave */
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flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
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flag |= DAVINCI_I2C_MDR_NACK;
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/* write the data into mode register */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
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#if 0
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if (pdata)
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generic_i2c_clock_pulse(pdata->scl_pin);
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#endif
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/* Send STOP */
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flag = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
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flag |= DAVINCI_I2C_MDR_STP;
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
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}
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static inline void davinci_i2c_reset_ctrl(struct davinci_i2c_dev *i2c_dev,
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int val)
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{
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rt_uint16_t w;
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w = davinci_i2c_read_reg(i2c_dev, DAVINCI_I2C_MDR_REG);
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if (!val) /* put I2C into reset */
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w &= ~DAVINCI_I2C_MDR_IRS;
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else /* take I2C out of reset */
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w |= DAVINCI_I2C_MDR_IRS;
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davinci_i2c_write_reg(i2c_dev, DAVINCI_I2C_MDR_REG, w);
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}
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static void i2c_davinci_calc_clk_dividers(struct davinci_i2c_dev *dev)
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{
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rt_uint16_t psc;
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rt_uint32_t clk;
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rt_uint32_t d;
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rt_uint32_t clkh;
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rt_uint32_t clkl;
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rt_uint32_t input_clock = clk_get_rate(dev->clk);
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/* NOTE: I2C Clock divider programming info
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* As per I2C specs the following formulas provide prescaler
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* and low/high divider values
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* input clk --> PSC Div -----------> ICCL/H Div --> output clock
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* module clk
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*
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* output clk = module clk / (PSC + 1) [ (ICCL + d) + (ICCH + d) ]
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*
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* Thus,
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* (ICCL + ICCH) = clk = (input clk / ((psc +1) * output clk)) - 2d;
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*
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* where if PSC == 0, d = 7,
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* if PSC == 1, d = 6
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* if PSC > 1 , d = 5
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*/
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/* get minimum of 7 MHz clock, but max of 12 MHz */
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psc = (input_clock / 7000000) - 1;
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if ((input_clock / (psc + 1)) > 12000000)
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psc++; /* better to run under spec than over */
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d = (psc >= 2) ? 5 : 7 - psc;
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clk = ((input_clock / (psc + 1)) / (dev->bus_freq * 1000)) - (d << 1);
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clkh = clk >> 1;
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clkl = clk - clkh;
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davinci_i2c_write_reg(dev, DAVINCI_I2C_PSC_REG, psc);
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davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKH_REG, clkh);
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davinci_i2c_write_reg(dev, DAVINCI_I2C_CLKL_REG, clkl);
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i2c_dbg("input_clock = %d, CLK = %d\n", input_clock, clk);
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}
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/*
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* This function configures I2C and brings I2C out of reset.
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* This function is called during I2C init function. This function
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* also gets called if I2C encounters any errors.
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*/
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static int i2c_davinci_init(struct davinci_i2c_dev *dev)
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{
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/* put I2C into reset */
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davinci_i2c_reset_ctrl(dev, 0);
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/* compute clock dividers */
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i2c_davinci_calc_clk_dividers(dev);
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/* Respond at reserved "SMBus Host" slave address" (and zero);
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* we seem to have no option to not respond...
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*/
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davinci_i2c_write_reg(dev, DAVINCI_I2C_OAR_REG, 0x08);
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i2c_dbg("PSC = %d\n",
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davinci_i2c_read_reg(dev, DAVINCI_I2C_PSC_REG));
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i2c_dbg("CLKL = %d\n",
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davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKL_REG));
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i2c_dbg("CLKH = %d\n",
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davinci_i2c_read_reg(dev, DAVINCI_I2C_CLKH_REG));
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i2c_dbg("bus_freq = %dkHz, bus_delay = %d\n",
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dev->bus_freq, dev->bus_delay);
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/* Take the I2C module out of reset: */
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davinci_i2c_reset_ctrl(dev, 1);
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/* Enable interrupts */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, I2C_DAVINCI_INTR_ALL);
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return 0;
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}
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/*
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* Waiting for bus not busy
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*/
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static int i2c_davinci_wait_bus_not_busy(struct davinci_i2c_dev *dev,
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char allow_sleep)
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{
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unsigned long timeout;
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static rt_uint16_t to_cnt;
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RT_ASSERT(dev != RT_NULL);
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RT_ASSERT(dev->bus != RT_NULL);
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timeout = rt_tick_get() + dev->bus->timeout;
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while (davinci_i2c_read_reg(dev, DAVINCI_I2C_STR_REG)
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& DAVINCI_I2C_STR_BB) {
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if (to_cnt <= DAVINCI_I2C_MAX_TRIES) {
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if (rt_tick_get() >= timeout) {
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rt_kprintf("timeout waiting for bus ready\n");
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to_cnt++;
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return -RT_ETIMEOUT;
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} else {
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to_cnt = 0;
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i2c_recover_bus(dev);
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i2c_davinci_init(dev);
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}
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}
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if (allow_sleep)
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rt_thread_delay(2);
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}
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return 0;
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}
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/*
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* Low level master read/write transaction. This function is called
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* from i2c_davinci_xfer.
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*/
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static int
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i2c_davinci_xfer_msg(struct rt_i2c_bus_device *bus, struct rt_i2c_msg *msg, int stop)
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{
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struct davinci_i2c_dev *dev = bus->priv;
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rt_uint32_t flag;
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rt_uint16_t w;
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int r;
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/* Introduce a delay, required for some boards (e.g Davinci EVM) */
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if (dev->bus_delay)
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udelay(dev->bus_delay);
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/* set the slave address */
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davinci_i2c_write_reg(dev, DAVINCI_I2C_SAR_REG, msg->addr);
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dev->buf = msg->buf;
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dev->buf_len = msg->len;
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dev->stop = stop;
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davinci_i2c_write_reg(dev, DAVINCI_I2C_CNT_REG, dev->buf_len);
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//INIT_COMPLETION(dev->cmd_complete);
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dev->cmd_err = 0;
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/* Take I2C out of reset and configure it as master */
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flag = DAVINCI_I2C_MDR_IRS | DAVINCI_I2C_MDR_MST;
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/* if the slave address is ten bit address, enable XA bit */
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if (msg->flags & RT_I2C_ADDR_10BIT)
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flag |= DAVINCI_I2C_MDR_XA;
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if (!(msg->flags & RT_I2C_RD))
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flag |= DAVINCI_I2C_MDR_TRX;
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if (msg->len == 0)
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flag |= DAVINCI_I2C_MDR_RM;
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/* Enable receive or transmit interrupts */
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w = davinci_i2c_read_reg(dev, DAVINCI_I2C_IMR_REG);
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if (msg->flags & RT_I2C_RD)
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w |= DAVINCI_I2C_IMR_RRDY;
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else
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w |= DAVINCI_I2C_IMR_XRDY;
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davinci_i2c_write_reg(dev, DAVINCI_I2C_IMR_REG, w);
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dev->terminate = 0;
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/*
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* Write mode register first as needed for correct behaviour
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* on OMAP-L138, but don't set STT yet to avoid a race with XRDY
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* occurring before we have loaded DXR
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*/
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
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/*
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* First byte should be set here, not after interrupt,
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* because transmit-data-ready interrupt can come before
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* NACK-interrupt during sending of previous message and
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* ICDXR may have wrong data
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* It also saves us one interrupt, slightly faster
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*/
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if ((!(msg->flags & RT_I2C_RD)) && dev->buf_len)
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{
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davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG, *dev->buf++);
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dev->buf_len--;
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}
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/* Set STT to begin transmit now DXR is loaded */
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flag |= DAVINCI_I2C_MDR_STT;
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if (stop && msg->len != 0)
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flag |= DAVINCI_I2C_MDR_STP;
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, flag);
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r = rt_sem_take(&dev->completion, dev->bus->timeout);
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if (r == -RT_ETIMEOUT)
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{
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rt_kprintf("controller timed out\n");
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i2c_recover_bus(dev);
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i2c_davinci_init(dev);
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dev->buf_len = 0;
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return -RT_ETIMEOUT;
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}
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if (dev->buf_len)
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{
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/* This should be 0 if all bytes were transferred
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* or dev->cmd_err denotes an error.
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* A signal may have aborted the transfer.
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*/
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if (r == RT_EOK)
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{
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rt_kprintf("abnormal termination buf_len=%i\n",
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dev->buf_len);
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r = -RT_EIO;
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}
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dev->terminate = 1;
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dev->buf_len = 0;
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}
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if (r < 0)
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return r;
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/* no error */
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if (!dev->cmd_err)
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return msg->len;
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/* We have an error */
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if (dev->cmd_err & DAVINCI_I2C_STR_AL)
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{
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i2c_davinci_init(dev);
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return -RT_EIO;
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}
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if (dev->cmd_err & DAVINCI_I2C_STR_NACK)
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{
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if (msg->flags & RT_I2C_IGNORE_NACK)
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return msg->len;
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if (stop)
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{
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w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
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w |= DAVINCI_I2C_MDR_STP;
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davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
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}
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return -RT_EIO;
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}
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return -RT_EIO;
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}
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/*
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* Prepare controller for a transaction and call i2c_davinci_xfer_msg
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*/
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static int
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i2c_davinci_xfer(struct rt_i2c_bus_device *bus, struct rt_i2c_msg msgs[], int num)
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{
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struct davinci_i2c_dev *dev = bus->priv;
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int i;
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int ret;
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i2c_dbg("%s: msgs: %d\n", __func__, num);
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ret = i2c_davinci_wait_bus_not_busy(dev, 1);
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if (ret < 0)
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{
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i2c_dbg("timeout waiting for bus ready\n");
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return ret;
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}
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for (i = 0; i < num; i++)
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{
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ret = i2c_davinci_xfer_msg(bus, &msgs[i], (i == (num - 1)));
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i2c_dbg("%s [%d/%d] ret: %d\n", __func__, i + 1, num,
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ret);
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if (ret < 0)
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return ret;
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}
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return num;
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}
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static void terminate_read(struct davinci_i2c_dev *dev)
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{
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rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
|
|
w |= DAVINCI_I2C_MDR_NACK;
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
|
|
|
|
/* Throw away data */
|
|
davinci_i2c_read_reg(dev, DAVINCI_I2C_DRR_REG);
|
|
if (!dev->terminate)
|
|
rt_kprintf("RDR IRQ while no data requested\n");
|
|
}
|
|
static void terminate_write(struct davinci_i2c_dev *dev)
|
|
{
|
|
rt_uint16_t w = davinci_i2c_read_reg(dev, DAVINCI_I2C_MDR_REG);
|
|
w |= DAVINCI_I2C_MDR_RM | DAVINCI_I2C_MDR_STP;
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_MDR_REG, w);
|
|
|
|
if (!dev->terminate)
|
|
i2c_dbg("TDR IRQ while no data to send\n");
|
|
}
|
|
|
|
/*
|
|
* Interrupt service routine. This gets called whenever an I2C interrupt
|
|
* occurs.
|
|
*/
|
|
static void i2c_davinci_isr(int irq, void *param)
|
|
{
|
|
struct davinci_i2c_dev *dev = (struct davinci_i2c_dev *)param;
|
|
rt_uint32_t stat;
|
|
int count = 0;
|
|
rt_uint16_t w;
|
|
|
|
while ((stat = davinci_i2c_read_reg(dev, DAVINCI_I2C_IVR_REG))) {
|
|
i2c_dbg("%s: stat=0x%x\n", __func__, stat);
|
|
if (count++ == 100) {
|
|
rt_kprintf("Too much work in one IRQ\n");
|
|
break;
|
|
}
|
|
|
|
switch (stat) {
|
|
case DAVINCI_I2C_IVR_AL:
|
|
/* Arbitration lost, must retry */
|
|
dev->cmd_err |= DAVINCI_I2C_STR_AL;
|
|
dev->buf_len = 0;
|
|
rt_sem_release(&dev->completion);
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_NACK:
|
|
dev->cmd_err |= DAVINCI_I2C_STR_NACK;
|
|
dev->buf_len = 0;
|
|
rt_sem_release(&dev->completion);
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_ARDY:
|
|
davinci_i2c_write_reg(dev,
|
|
DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_ARDY);
|
|
if (((dev->buf_len == 0) && (dev->stop != 0)) ||
|
|
(dev->cmd_err & DAVINCI_I2C_STR_NACK)) {
|
|
w = davinci_i2c_read_reg(dev,
|
|
DAVINCI_I2C_MDR_REG);
|
|
w |= DAVINCI_I2C_MDR_STP;
|
|
davinci_i2c_write_reg(dev,
|
|
DAVINCI_I2C_MDR_REG, w);
|
|
}
|
|
rt_sem_release(&dev->completion);
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_RDR:
|
|
if (dev->buf_len) {
|
|
*dev->buf++ =
|
|
davinci_i2c_read_reg(dev,
|
|
DAVINCI_I2C_DRR_REG);
|
|
dev->buf_len--;
|
|
if (dev->buf_len)
|
|
continue;
|
|
|
|
davinci_i2c_write_reg(dev,
|
|
DAVINCI_I2C_STR_REG,
|
|
DAVINCI_I2C_IMR_RRDY);
|
|
} else {
|
|
/* signal can terminate transfer */
|
|
terminate_read(dev);
|
|
}
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_XRDY:
|
|
if (dev->buf_len) {
|
|
davinci_i2c_write_reg(dev, DAVINCI_I2C_DXR_REG,
|
|
*dev->buf++);
|
|
dev->buf_len--;
|
|
if (dev->buf_len)
|
|
continue;
|
|
|
|
w = davinci_i2c_read_reg(dev,
|
|
DAVINCI_I2C_IMR_REG);
|
|
w &= ~DAVINCI_I2C_IMR_XRDY;
|
|
davinci_i2c_write_reg(dev,
|
|
DAVINCI_I2C_IMR_REG,
|
|
w);
|
|
} else {
|
|
/* signal can terminate transfer */
|
|
terminate_write(dev);
|
|
}
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_SCD:
|
|
davinci_i2c_write_reg(dev,
|
|
DAVINCI_I2C_STR_REG, DAVINCI_I2C_STR_SCD);
|
|
rt_sem_release(&dev->completion);
|
|
break;
|
|
|
|
case DAVINCI_I2C_IVR_AAS:
|
|
i2c_dbg("Address as slave interrupt\n");
|
|
break;
|
|
|
|
default:
|
|
i2c_dbg("Unrecognized irq stat %d\n", stat);
|
|
break;
|
|
}
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static struct rt_i2c_bus_device_ops bus_ops = {
|
|
.master_xfer = i2c_davinci_xfer,
|
|
};
|
|
|
|
int davinci_i2c_init(char *bus_name)
|
|
{
|
|
struct rt_i2c_bus_device *bus;
|
|
struct davinci_i2c_dev *dev;
|
|
int r;
|
|
|
|
bus = rt_malloc(sizeof(struct rt_i2c_bus_device));
|
|
if (bus == RT_NULL)
|
|
{
|
|
rt_kprintf("rt_malloc failed\n");
|
|
return -RT_ENOMEM;
|
|
}
|
|
|
|
rt_memset((void *)bus, 0, sizeof(struct rt_i2c_bus_device));
|
|
|
|
bus->ops = &bus_ops;
|
|
bus->timeout = DAVINCI_I2C_TIMEOUT;
|
|
|
|
dev = rt_malloc(sizeof(struct davinci_i2c_dev));
|
|
if (!dev)
|
|
{
|
|
r = -RT_ENOMEM;
|
|
goto err;
|
|
}
|
|
|
|
rt_memset((void *)dev, 0, sizeof(struct davinci_i2c_dev));
|
|
|
|
rt_sem_init(&dev->completion, "i2c_ack", 0, RT_IPC_FLAG_FIFO);
|
|
|
|
dev->irq = IRQ_I2C;
|
|
|
|
dev->clk = clk_get("I2CCLK");
|
|
if (dev->clk == RT_NULL) {
|
|
r = -RT_ERROR;
|
|
goto err1;
|
|
}
|
|
|
|
psc_change_state(DAVINCI_DM365_LPSC_I2C, 3);
|
|
|
|
dev->base = DAVINCI_I2C_BASE;
|
|
dev->bus_freq = 100;
|
|
dev->bus_delay = 0;
|
|
dev->bus = bus;
|
|
|
|
bus->priv = dev;
|
|
|
|
i2c_davinci_init(dev);
|
|
|
|
rt_hw_interrupt_install(dev->irq, i2c_davinci_isr, (void *)dev, "I2C");
|
|
rt_hw_interrupt_umask(dev->irq);
|
|
|
|
return rt_i2c_bus_device_register(bus, bus_name);
|
|
|
|
err1:
|
|
rt_free(dev);
|
|
|
|
err:
|
|
rt_free(bus);
|
|
|
|
return r;
|
|
}
|
|
|
|
int rt_hw_iic_init(void)
|
|
{
|
|
davinci_i2c_init("I2C1");
|
|
}
|
|
|
|
INIT_DEVICE_EXPORT(rt_hw_iic_init);
|
|
|