258 lines
7.9 KiB
C
258 lines
7.9 KiB
C
/*
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* Copyright (c) 2006-2021, RT-Thread Development Team
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* Copyright (c) 2019-Present Nuclei Limited. All rights reserved.
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2020/03/26 Huaqi Nuclei RISC-V Core porting code.
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include <sys/types.h>
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#include <unistd.h>
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#include "cpuport.h"
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#define SYSTICK_TICK_CONST (SOC_TIMER_FREQ / RT_TICK_PER_SECOND)
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/* Interrupt level for kernel systimer interrupt and software timer interrupt */
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#define RT_KERNEL_INTERRUPT_LEVEL 0
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/* Initial CSR MSTATUS value when thread created */
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#define RT_INITIAL_MSTATUS (MSTATUS_MPP | MSTATUS_MPIE | MSTATUS_FS_INITIAL)
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/**
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* @brief from thread used interrupt context switch
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*
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*/
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volatile rt_ubase_t rt_interrupt_from_thread = 0;
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/**
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* @brief to thread used interrupt context switch
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*
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*/
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volatile rt_ubase_t rt_interrupt_to_thread = 0;
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/**
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* @brief flag to indicate context switch in interrupt or not
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*
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*/
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volatile rt_ubase_t rt_thread_switch_interrupt_flag = 0;
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/**
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* @brief thread stack frame of saved context
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*
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*/
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struct rt_hw_stack_frame
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{
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rt_ubase_t epc; /*!< epc - epc - program counter */
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rt_ubase_t ra; /*!< x1 - ra - return address for jumps */
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rt_ubase_t t0; /*!< x5 - t0 - temporary register 0 */
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rt_ubase_t t1; /*!< x6 - t1 - temporary register 1 */
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rt_ubase_t t2; /*!< x7 - t2 - temporary register 2 */
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rt_ubase_t s0_fp; /*!< x8 - s0/fp - saved register 0 or frame pointer */
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rt_ubase_t s1; /*!< x9 - s1 - saved register 1 */
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rt_ubase_t a0; /*!< x10 - a0 - return value or function argument 0 */
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rt_ubase_t a1; /*!< x11 - a1 - return value or function argument 1 */
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rt_ubase_t a2; /*!< x12 - a2 - function argument 2 */
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rt_ubase_t a3; /*!< x13 - a3 - function argument 3 */
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rt_ubase_t a4; /*!< x14 - a4 - function argument 4 */
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rt_ubase_t a5; /*!< x15 - a5 - function argument 5 */
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#ifndef __riscv_32e
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rt_ubase_t a6; /*!< x16 - a6 - function argument 6 */
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rt_ubase_t a7; /*!< x17 - s7 - function argument 7 */
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rt_ubase_t s2; /*!< x18 - s2 - saved register 2 */
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rt_ubase_t s3; /*!< x19 - s3 - saved register 3 */
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rt_ubase_t s4; /*!< x20 - s4 - saved register 4 */
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rt_ubase_t s5; /*!< x21 - s5 - saved register 5 */
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rt_ubase_t s6; /*!< x22 - s6 - saved register 6 */
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rt_ubase_t s7; /*!< x23 - s7 - saved register 7 */
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rt_ubase_t s8; /*!< x24 - s8 - saved register 8 */
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rt_ubase_t s9; /*!< x25 - s9 - saved register 9 */
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rt_ubase_t s10; /*!< x26 - s10 - saved register 10 */
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rt_ubase_t s11; /*!< x27 - s11 - saved register 11 */
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rt_ubase_t t3; /*!< x28 - t3 - temporary register 3 */
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rt_ubase_t t4; /*!< x29 - t4 - temporary register 4 */
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rt_ubase_t t5; /*!< x30 - t5 - temporary register 5 */
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rt_ubase_t t6; /*!< x31 - t6 - temporary register 6 */
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#endif
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rt_ubase_t mstatus; /*!< - machine status register */
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};
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/**
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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struct rt_hw_stack_frame *frame;
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rt_uint8_t *stk;
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int i;
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stk = stack_addr + sizeof(rt_ubase_t);
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stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
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stk -= sizeof(struct rt_hw_stack_frame);
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frame = (struct rt_hw_stack_frame *)stk;
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for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
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{
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((rt_ubase_t *)frame)[i] = 0xdeadbeef;
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}
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frame->ra = (rt_ubase_t)texit;
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frame->a0 = (rt_ubase_t)parameter;
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frame->epc = (rt_ubase_t)tentry;
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frame->mstatus = RT_INITIAL_MSTATUS;
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return stk;
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}
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/**
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* @brief Do rt-thread context switch in interrupt context
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*
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* @param from thread sp of from thread
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* @param to thread sp of to thread
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*/
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void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
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{
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if (rt_thread_switch_interrupt_flag == 0)
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rt_interrupt_from_thread = from;
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rt_interrupt_to_thread = to;
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rt_thread_switch_interrupt_flag = 1;
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RT_YIELD();
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}
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/**
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* @brief Do rt-thread context switch in task context
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*
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* @param from thread sp of from thread
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* @param to thread sp of to thread
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*/
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void rt_hw_context_switch(rt_ubase_t from, rt_ubase_t to)
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{
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rt_hw_context_switch_interrupt(from, to);
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}
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/**
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* @brief shutdown CPU
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*
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*/
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RT_WEAK void rt_hw_cpu_shutdown()
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{
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rt_base_t level;
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rt_kprintf("shutdown...\n");
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level = rt_hw_interrupt_disable();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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/**
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* @brief Do extra task switch code
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*
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* @details
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*
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* - Clear software timer interrupt request flag
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* - clear rt_thread_switch_interrupt_flag to 0
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*/
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void rt_hw_taskswitch(void)
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{
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/* Clear Software IRQ, A MUST */
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SysTimer_ClearSWIRQ();
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rt_thread_switch_interrupt_flag = 0;
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}
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/**
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* @brief Setup systimer and software timer interrupt
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*
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* @details
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*
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* - Set Systimer interrupt as NON-VECTOR interrupt with lowest interrupt level
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* - Set software timer interrupt as VECTOR interrupt with lowest interrupt level
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* - Enable these two interrupts
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*/
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void rt_hw_ticksetup(void)
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{
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uint64_t ticks = SYSTICK_TICK_CONST;
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/* Make SWI and SysTick the lowest priority interrupts. */
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/* Stop and clear the SysTimer. SysTimer as Non-Vector Interrupt */
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SysTick_Config(ticks);
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ECLIC_DisableIRQ(SysTimer_IRQn);
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ECLIC_SetLevelIRQ(SysTimer_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
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ECLIC_SetShvIRQ(SysTimer_IRQn, ECLIC_NON_VECTOR_INTERRUPT);
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ECLIC_EnableIRQ(SysTimer_IRQn);
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/* Set SWI interrupt level to lowest level/priority, SysTimerSW as Vector Interrupt */
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ECLIC_SetShvIRQ(SysTimerSW_IRQn, ECLIC_VECTOR_INTERRUPT);
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ECLIC_SetLevelIRQ(SysTimerSW_IRQn, RT_KERNEL_INTERRUPT_LEVEL);
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ECLIC_EnableIRQ(SysTimerSW_IRQn);
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}
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/**
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* systimer interrupt handler eclic_mtip_handler
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* is hard coded in startup_<Device>.S
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* We define SysTick_Handler as eclic_mtip_handler
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* for easy understanding
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*/
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#define SysTick_Handler eclic_mtip_handler
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/**
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* @brief This is the timer interrupt service routine.
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*
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*/
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void SysTick_Handler(void)
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{
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/* Reload systimer */
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SysTick_Reload(SYSTICK_TICK_CONST);
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/* enter interrupt */
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rt_interrupt_enter();
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/* tick increase */
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rt_tick_increase();
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/* leave interrupt */
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rt_interrupt_leave();
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}
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/**
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* @brief Disable cpu interrupt
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*
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* @details
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*
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* - Disable cpu interrupt by clear MIE bit in MSTATUS
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* - Return the previous value in MSTATUS before clear MIE bit
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*
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* @return the previous value in MSTATUS before clear MIE bit
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*/
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rt_base_t rt_hw_interrupt_disable(void)
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{
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return __RV_CSR_READ_CLEAR(CSR_MSTATUS, MSTATUS_MIE);
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}
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/**
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* @brief Restore previous saved interrupt status
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*
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* @param level previous saved MSTATUS value
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*/
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void rt_hw_interrupt_enable(rt_base_t level)
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{
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__RV_CSR_WRITE(CSR_MSTATUS, level);
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}
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