168 lines
4.7 KiB
ArmAsm
168 lines
4.7 KiB
ArmAsm
/*
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* Copyright (c) 2011-2022, Shanghai Real-Thread Electronic Technology Co.,Ltd
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*
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* Change Logs:
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* Date Author Notes
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* 2022-08-29 RT-Thread first version
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*/
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.globl rt_cpu_get_smp_id
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rt_cpu_get_smp_id:
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mrc p15, #0, r0, c0, c0, #5
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bx lr
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.globl rt_cpu_vector_set_base
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rt_cpu_vector_set_base:
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/* clear SCTRL.V to customize the vector address */
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mrc p15, #0, r1, c1, c0, #0
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bic r1, #(1 << 13)
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mcr p15, #0, r1, c1, c0, #0
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/* set up the vector address */
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mcr p15, #0, r0, c12, c0, #0
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dsb
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bx lr
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.globl rt_hw_cpu_dcache_enable
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rt_hw_cpu_dcache_enable:
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mrc p15, #0, r0, c1, c0, #0
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orr r0, r0, #0x00000004
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mcr p15, #0, r0, c1, c0, #0
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bx lr
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.globl rt_hw_cpu_icache_enable
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rt_hw_cpu_icache_enable:
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mrc p15, #0, r0, c1, c0, #0
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orr r0, r0, #0x00001000
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mcr p15, #0, r0, c1, c0, #0
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bx lr
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_FLD_MAX_WAY:
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.word 0x3ff
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_FLD_MAX_IDX:
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.word 0x7fff
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.globl rt_cpu_dcache_clean_flush
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rt_cpu_dcache_clean_flush:
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stmfd sp!, {r0-r12, lr}
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bl v7_flush_dcache_all
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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dsb
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isb
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ldmfd sp!, {r0-r12, lr}
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mov pc, lr
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v7_flush_dcache_all:
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dmb @ ensure ordering with previous memory accesses
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mrc p15, 1, r0, c0, c0, 1 @ read clidr
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ands r3, r0, #0x7000000 @ extract loc from clidr
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mov r3, r3, lsr #23 @ left align loc bit field
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beq finished @ if loc is 0, then no need to clean
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mov r10, #0 @ start clean at cache level 0
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loop1:
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add r2, r10, r10, lsr #1 @ work out 3x current cache level
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mov r1, r0, lsr r2 @ extract cache type bits from clidr
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and r1, r1, #7 @ mask of the bits for current cache only
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cmp r1, #2 @ see what cache we have at this level
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blt skip @ skip if no cache, or just i-cache
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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isb @ isb to sych the new cssr&csidr
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mrc p15, 1, r1, c0, c0, 0 @ read the new csidr
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and r2, r1, #7 @ extract the length of the cache lines
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add r2, r2, #4 @ add 4 (line length offset)
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ldr r4, =0x3ff
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ands r4, r4, r1, lsr #3 @ find maximum number on the way size
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clz r5, r4 @ find bit position of way size increment
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ldr r7, =0x7fff
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ands r7, r7, r1, lsr #13 @ extract max number of the index size
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loop2:
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mov r9, r4 @ create working copy of max way size
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loop3:
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orr r11, r10, r9, lsl r5 @ factor way and cache number into r11
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orr r11, r11, r7, lsl r2 @ factor index number into r11
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mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way
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subs r9, r9, #1 @ decrement the way
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bge loop3
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subs r7, r7, #1 @ decrement the index
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bge loop2
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skip:
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add r10, r10, #2 @ increment cache number
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cmp r3, r10
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bgt loop1
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finished:
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mov r10, #0 @ swith back to cache level 0
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mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr
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dsb
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isb
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mov pc, lr
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#if 0
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push {r4-r11}
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dmb
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mrc p15, #1, r0, c0, c0, #1 @ read clid register
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ands r3, r0, #0x7000000 @ get level of coherency
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mov r3, r3, lsr #23
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beq finished
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mov r10, #0
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loop1:
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add r2, r10, r10, lsr #1
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mov r1, r0, lsr r2
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and r1, r1, #7
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cmp r1, #2
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blt skip
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mcr p15, #2, r10, c0, c0, #0
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isb
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mrc p15, #1, r1, c0, c0, #0
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and r2, r1, #7
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add r2, r2, #4
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ldr r4, _FLD_MAX_WAY
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ands r4, r4, r1, lsr #3
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clz r5, r4
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ldr r7, _FLD_MAX_IDX
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ands r7, r7, r1, lsr #13
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loop2:
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mov r9, r4
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loop3:
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orr r11, r10, r9, lsl r5
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orr r11, r11, r7, lsl r2
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mcr p15, #0, r11, c7, c14, #2
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subs r9, r9, #1
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bge loop3
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subs r7, r7, #1
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bge loop2
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skip:
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add r10, r10, #2
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cmp r3, r10
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bgt loop1
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finished:
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dsb
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isb
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pop {r4-r11}
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bx lr
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#endif
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.globl rt_cpu_icache_flush
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rt_cpu_icache_flush:
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mov r0, #0
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mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate
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dsb
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isb
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bx lr
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.globl rt_hw_cpu_dcache_disable
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rt_hw_cpu_dcache_disable:
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push {r4-r11, lr}
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bl rt_cpu_dcache_clean_flush
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mrc p15, #0, r0, c1, c0, #0
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bic r0, r0, #0x00000004
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mcr p15, #0, r0, c1, c0, #0
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pop {r4-r11, lr}
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bx lr
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.globl rt_hw_cpu_icache_disable
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rt_hw_cpu_icache_disable:
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mrc p15, #0, r0, c1, c0, #0
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bic r0, r0, #0x00001000
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mcr p15, #0, r0, c1, c0, #0
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bx lr
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