507 lines
17 KiB
C
507 lines
17 KiB
C
//###########################################################################
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//
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// FILE: F2837xD_Gpio.c
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//
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// TITLE: GPIO module support functions
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//
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//###########################################################################
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// $TI Release: F2837xD Support Library v3.05.00.00 $
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// $Release Date: Tue Jun 26 03:15:23 CDT 2018 $
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// $Copyright:
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// Copyright (C) 2013-2018 Texas Instruments Incorporated - http://www.ti.com/
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//
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions
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// are met:
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//
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// Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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//
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// Redistributions in binary form must reproduce the above copyright
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// notice, this list of conditions and the following disclaimer in the
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// documentation and/or other materials provided with the
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// distribution.
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//
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// Neither the name of Texas Instruments Incorporated nor the names of
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// its contributors may be used to endorse or promote products derived
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// from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// $
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//###########################################################################
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//
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// Included Files
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//
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#include "F2837xD_device.h"
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#include "F2837xD_Examples.h"
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//
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//Low-level functions for GPIO configuration (CPU1 only)
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//
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#ifdef CPU1
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//
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// InitGpio - Sets all pins to be muxed to GPIO in input mode with pull-ups
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// enabled. Also resets CPU control to CPU1 and disables open
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// drain and polarity inversion and sets the qualification to
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// synchronous. Also unlocks all GPIOs. Only one CPU should call
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// this function.
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//
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void InitGpio()
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{
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volatile Uint32 *gpioBaseAddr;
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Uint16 regOffset;
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//
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//Disable pin locks
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//
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EALLOW;
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GpioCtrlRegs.GPALOCK.all = 0x00000000;
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GpioCtrlRegs.GPBLOCK.all = 0x00000000;
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GpioCtrlRegs.GPCLOCK.all = 0x00000000;
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GpioCtrlRegs.GPDLOCK.all = 0x00000000;
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GpioCtrlRegs.GPELOCK.all = 0x00000000;
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GpioCtrlRegs.GPFLOCK.all = 0x00000000;
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//
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// Fill all registers with zeros. Writing to each register separately
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// for six GPIO modules would make this function *very* long.
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// Fortunately, we'd be writing them all with zeros anyway, so this
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// saves a lot of space.
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//
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gpioBaseAddr = (Uint32 *)&GpioCtrlRegs;
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for (regOffset = 0; regOffset < sizeof(GpioCtrlRegs)/2; regOffset++)
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{
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//
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//Hack to avoid enabling pull-ups on all pins. GPyPUD is offset
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//0x0C in each register group of 0x40 words. Since this is a
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//32-bit pointer, the addresses must be divided by 2.
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//
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if (regOffset % (0x40/2) != (0x0C/2))
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{
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gpioBaseAddr[regOffset] = 0x00000000;
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}
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}
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gpioBaseAddr = (Uint32 *)&GpioDataRegs;
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for (regOffset = 0; regOffset < sizeof(GpioDataRegs)/2; regOffset++)
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{
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gpioBaseAddr[regOffset] = 0x00000000;
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}
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EDIS;
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}
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//
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// GPIO_SetupPinMux - Set the peripheral muxing for the specified pin. The
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// appropriate parameters can be found in the GPIO Muxed
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// Pins table(4.4) in the datasheet. Use the GPIO index
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// row (0 to 15) to select a muxing option for the GPIO.
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//
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void GPIO_SetupPinMux(Uint16 gpioNumber, Uint16 cpu, Uint16 muxPosition)
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{
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volatile Uint32 *gpioBaseAddr;
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volatile Uint32 *mux, *gmux, *csel;
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Uint16 pin32, pin16, pin8;
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pin32 = gpioNumber % 32;
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pin16 = gpioNumber % 16;
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pin8 = gpioNumber % 8;
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gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
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//
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//Sanity check for valid cpu and peripheral values
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//
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if (cpu > GPIO_MUX_CPU2CLA || muxPosition > 0xF)
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return;
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//
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//Create pointers to the appropriate registers. This is a workaround
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//for the way GPIO registers are defined. The standard definition
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//in the header file makes it very easy to do named accesses of one
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//register or bit, but hard to do arbitrary numerical accesses. It's
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//easier to have an array of GPIO modules with identical registers,
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//including arrays for multi-register groups like GPyCSEL1-4. But
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//the header file doesn't define anything we can turn into an array,
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//so manual pointer arithmetic is used instead.
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//
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mux = gpioBaseAddr + GPYMUX + pin32/16;
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gmux = gpioBaseAddr + GPYGMUX + pin32/16;
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csel = gpioBaseAddr + GPYCSEL + pin32/8;
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//
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//Now for the actual function
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//
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EALLOW;
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//
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//To change the muxing, set the peripheral mux to 0/GPIO first to avoid
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//glitches, then change the group mux, then set the peripheral mux to
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//its target value. Finally, set the CPU select. This procedure is
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//described in the TRM. Unfortunately, since we don't know the pin in
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//advance we can't hardcode a bitfield reference, so there's some
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//tricky bit twiddling here.
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//
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*mux &= ~(0x3UL << (2*pin16));
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*gmux &= ~(0x3UL << (2*pin16));
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*gmux |= (Uint32)((muxPosition >> 2) & 0x3UL) << (2*pin16);
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*mux |= (Uint32)(muxPosition & 0x3UL) << (2*pin16);
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*csel &= ~(0x3L << (4*pin8));
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*csel |= (Uint32)(cpu & 0x3L) << (4*pin8);
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//
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//WARNING: This code does not touch the analog mode select registers,
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//which are needed to give the USB module control of its IOs.
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//
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EDIS;
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}
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//
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// GPIO_SetupPinOptions - Setup up the GPIO input/output options for the
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// specified pin.
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//
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//The flags are a 16-bit mask produced by ORing together options.
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//For input pins, the valid flags are:
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//GPIO_PULLUP Enable pull-up
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//GPIO_INVERT Enable input polarity inversion
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//GPIO_SYNC Synchronize the input latch to PLLSYSCLK
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// (default -- you don't need to specify this)
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//GPIO_QUAL3 Use 3-sample qualification
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//GPIO_QUAL6 Use 6-sample qualification
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//GPIO_ASYNC Do not use synchronization or qualification
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//(Note: only one of SYNC, QUAL3, QUAL6, or ASYNC is allowed)
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//
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//For output pins, the valid flags are:
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//GPIO_OPENDRAIN Output in open drain mode
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//GPIO_PULLUP If open drain enabled, also enable the pull-up
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//and the input qualification flags (SYNC/QUAL3/QUAL6/SYNC) listed above.
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//
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//With no flags, the default input state is synchronous with no
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//pull-up or polarity inversion. The default output state is
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//the standard digital output.
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//
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void GPIO_SetupPinOptions(Uint16 gpioNumber, Uint16 output, Uint16 flags)
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{
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volatile Uint32 *gpioBaseAddr;
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volatile Uint32 *dir, *pud, *inv, *odr, *qsel;
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Uint32 pin32, pin16, pinMask, qual;
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pin32 = gpioNumber % 32;
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pin16 = gpioNumber % 16;
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pinMask = 1UL << pin32;
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gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
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//
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//Create pointers to the appropriate registers. This is a workaround
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//for the way GPIO registers are defined. The standard definition
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//in the header file makes it very easy to do named accesses of one
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//register or bit, but hard to do arbitrary numerical accesses. It's
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//easier to have an array of GPIO modules with identical registers,
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//including arrays for multi-register groups like GPyQSEL1-2. But
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//the header file doesn't define anything we can turn into an array,
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//so manual pointer arithmetic is used instead.
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//
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dir = gpioBaseAddr + GPYDIR;
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pud = gpioBaseAddr + GPYPUD;
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inv = gpioBaseAddr + GPYINV;
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odr = gpioBaseAddr + GPYODR;
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qsel = gpioBaseAddr + GPYQSEL + pin32/16;
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EALLOW;
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//
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//Set the data direction
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//
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*dir &= ~pinMask;
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if (output == 1)
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{
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//
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//Output, with optional open drain mode and pull-up
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//
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*dir |= pinMask;
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//
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//Enable open drain if necessary
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//
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if (flags & GPIO_OPENDRAIN)
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{
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*odr |= pinMask;
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}
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else
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{
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*odr &= ~pinMask;
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}
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//
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//Enable pull-up if necessary. Open drain mode must be active.
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//
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if (flags & (GPIO_OPENDRAIN | GPIO_PULLUP))
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{
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*pud &= ~pinMask;
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}
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else
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{
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*pud |= pinMask;
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}
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}
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else
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{
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//
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//Input, with optional pull-up, qualification, and polarity
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//inversion
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//
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*dir &= ~pinMask;
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//
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//Enable pull-up if necessary
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//
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if (flags & GPIO_PULLUP)
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{
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*pud &= ~pinMask;
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}
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else
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{
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*pud |= pinMask;
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}
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//
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//Invert polarity if necessary
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//
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if (flags & GPIO_INVERT)
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{
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*inv |= pinMask;
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}
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else
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{
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*inv &= ~pinMask;
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}
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}
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//
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//Extract the qualification parameter and load it into the register.
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//This is also needed for open drain outputs, so we might as well do it
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//all the time.
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//
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qual = (flags & GPIO_ASYNC) / GPIO_QUAL3;
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*qsel &= ~(0x3L << (2 * pin16));
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if (qual != 0x0)
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{
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*qsel |= qual << (2 * pin16);
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}
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EDIS;
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}
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//
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// GPIO_SetupLock - Enable or disable the GPIO register bit lock for the
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// specified pin.
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// The valid flags are:
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// GPIO_UNLOCK - Unlock the pin setup register bits for
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// the specified pin
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// GPIO_LOCK - Lock the pin setup register bits for the
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// specified pin
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//
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void GPIO_SetupLock(Uint16 gpioNumber, Uint16 flags)
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{
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volatile Uint32 *gpioBaseAddr;
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volatile Uint32 *lock;
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Uint32 pin32, pinMask;
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pin32 = gpioNumber % 32;
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pinMask = 1UL << pin32;
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gpioBaseAddr = (Uint32 *)&GpioCtrlRegs + (gpioNumber/32)*GPY_CTRL_OFFSET;
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//
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//Create pointers to the appropriate registers. This is a workaround
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//for the way GPIO registers are defined. The standard definition
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//in the header file makes it very easy to do named accesses of one
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//register or bit, but hard to do arbitrary numerical accesses. It's
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//easier to have an array of GPIO modules with identical registers,
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//including arrays for multi-register groups like GPyQSEL1-2. But
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//the header file doesn't define anything we can turn into an array,
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//so manual pointer arithmetic is used instead.
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//
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lock = gpioBaseAddr + GPYLOCK;
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EALLOW;
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if(flags)
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{
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//Lock the pin
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*lock |= pinMask;
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}
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else
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{
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//Unlock the pin
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*lock &= ~pinMask;
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}
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EDIS;
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}
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//
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//External interrupt setup
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//
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void GPIO_SetupXINT1Gpio(Uint16 gpioNumber)
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{
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EALLOW;
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InputXbarRegs.INPUT4SELECT = gpioNumber; //Set XINT1 source to GPIO-pin
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EDIS;
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}
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void GPIO_SetupXINT2Gpio(Uint16 gpioNumber)
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{
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EALLOW;
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InputXbarRegs.INPUT5SELECT = gpioNumber; //Set XINT2 source to GPIO-pin
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EDIS;
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}
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void GPIO_SetupXINT3Gpio(Uint16 gpioNumber)
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{
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EALLOW;
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InputXbarRegs.INPUT6SELECT = gpioNumber; //Set XINT3 source to GPIO-pin
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EDIS;
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}
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void GPIO_SetupXINT4Gpio(Uint16 gpioNumber)
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{
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EALLOW;
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InputXbarRegs.INPUT13SELECT = gpioNumber; //Set XINT4 source to GPIO-pin
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EDIS;
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}
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void GPIO_SetupXINT5Gpio(Uint16 gpioNumber)
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{
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EALLOW;
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InputXbarRegs.INPUT14SELECT = gpioNumber; //Set XINT5 source to GPIO-pin
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EDIS;
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}
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//
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//GPIO_EnableUnbondedIOPullupsFor176Pin - Enable pullups for the unbonded
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// GPIOs on the 176PTP package:
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// GPIOs Grp Bits
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// 95-132 C 31
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// D 31:0
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// E 4:0
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// 134-168 E 31:6
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// F 8:0
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//
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void GPIO_EnableUnbondedIOPullupsFor176Pin()
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{
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EALLOW;
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GpioCtrlRegs.GPCPUD.all = ~0x80000000; //GPIO 95
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GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127
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GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFDF; //GPIOs 128-159 except for 133
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GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168
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EDIS;
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}
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//
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// GPIO_EnableUnbondedIOPullupsFor100Pin - Enable pullups for the unbonded
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// GPIOs on the 100PZ package:
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// GPIOs Grp Bits
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// 0-1 A 1:0
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// 5-9 A 9:5
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// 22-40 A 31:22
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// B 8:0
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// 44-57 B 25:12
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// 67-68 C 4:3
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// 74-77 C 13:10
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// 79-83 C 19:15
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// 93-168 C 31:29
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// D 31:0
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// E 31:0
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// F 8:0
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//
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void GPIO_EnableUnbondedIOPullupsFor100Pin()
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{
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EALLOW;
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GpioCtrlRegs.GPAPUD.all = ~0xFFC003E3; //GPIOs 0-1, 5-9, 22-31
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GpioCtrlRegs.GPBPUD.all = ~0x03FFF1FF; //GPIOs 32-40, 44-57
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GpioCtrlRegs.GPCPUD.all = ~0xE10FBC18; //GPIOs 67-68, 74-77, 79-83, 93-95
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GpioCtrlRegs.GPDPUD.all = ~0xFFFFFFF7; //GPIOs 96-127
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GpioCtrlRegs.GPEPUD.all = ~0xFFFFFFFF; //GPIOs 128-159
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GpioCtrlRegs.GPFPUD.all = ~0x000001FF; //GPIOs 160-168
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EDIS;
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}
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//
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// GPIO_EnableUnbondedIOPullups - InitSysCtrl would call this function
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// this takes care of enabling IO pullups.
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//
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void GPIO_EnableUnbondedIOPullups()
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{
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//
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//bits 8-10 have pin count
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//
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unsigned char pin_count = ((DevCfgRegs.PARTIDL.all & 0x00000700) >> 8) ;
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//
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//5 = 100 pin
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//6 = 176 pin
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//7 = 337 pin
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//
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if(pin_count == 5)
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{
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GPIO_EnableUnbondedIOPullupsFor100Pin();
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}
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else if (pin_count == 6)
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{
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GPIO_EnableUnbondedIOPullupsFor176Pin();
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}
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else
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{
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//do nothing - this is 337 pin package
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}
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}
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#endif //CPU1
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//
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// GPIO_ReadPin - Read the GPyDAT register bit for the specified pin. Note that
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// this returns the actual state of the pin, not the state of
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// the output latch.
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//
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Uint16 GPIO_ReadPin(Uint16 gpioNumber)
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{
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volatile Uint32 *gpioDataReg;
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Uint16 pinVal;
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gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET;
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pinVal = (gpioDataReg[GPYDAT] >> (gpioNumber % 32)) & 0x1;
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return pinVal;
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}
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//
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// GPIO_WritePin - Set the GPyDAT register bit for the specified pin.
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//
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void GPIO_WritePin(Uint16 gpioNumber, Uint16 outVal)
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{
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volatile Uint32 *gpioDataReg;
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Uint32 pinMask;
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gpioDataReg = (volatile Uint32 *)&GpioDataRegs + (gpioNumber/32)*GPY_DATA_OFFSET;
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pinMask = 1UL << (gpioNumber % 32);
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if (outVal == 0)
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{
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gpioDataReg[GPYCLEAR] = pinMask;
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}
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else
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{
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gpioDataReg[GPYSET] = pinMask;
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}
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}
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//
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// End of file
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//
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