200 lines
6.7 KiB
C
200 lines
6.7 KiB
C
/*
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* Copyright (c) 2006-2022, RT-Thread Development Team
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Change Logs:
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* Date Author Notes
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* 2021-09-09 WCH the first version
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*/
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#include <rthw.h>
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#include <rtthread.h>
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#include "ch32v10x.h"
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#include "cpuport.h"
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#ifndef RT_USING_SMP
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volatile rt_ubase_t rt_interrupt_from_thread = 0;
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volatile rt_ubase_t rt_interrupt_to_thread = 0;
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volatile rt_uint32_t rt_thread_switch_interrupt_flag = 0;
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#endif
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struct rt_hw_stack_frame
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{
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rt_ubase_t epc; /* epc - epc - program counter */
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rt_ubase_t ra; /* x1 - ra - return address for jumps */
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rt_ubase_t mstatus; /* - machine status register */
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rt_ubase_t gp; /* x3 - gp - global pointer */
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rt_ubase_t tp; /* x4 - tp - thread pointer */
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rt_ubase_t t0; /* x5 - t0 - temporary register 0 */
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rt_ubase_t t1; /* x6 - t1 - temporary register 1 */
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rt_ubase_t t2; /* x7 - t2 - temporary register 2 */
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rt_ubase_t s0_fp; /* x8 - s0/fp - saved register 0 or frame pointer */
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rt_ubase_t s1; /* x9 - s1 - saved register 1 */
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rt_ubase_t a0; /* x10 - a0 - return value or function argument 0 */
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rt_ubase_t a1; /* x11 - a1 - return value or function argument 1 */
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rt_ubase_t a2; /* x12 - a2 - function argument 2 */
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rt_ubase_t a3; /* x13 - a3 - function argument 3 */
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rt_ubase_t a4; /* x14 - a4 - function argument 4 */
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rt_ubase_t a5; /* x15 - a5 - function argument 5 */
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rt_ubase_t a6; /* x16 - a6 - function argument 6 */
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rt_ubase_t a7; /* x17 - s7 - function argument 7 */
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rt_ubase_t s2; /* x18 - s2 - saved register 2 */
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rt_ubase_t s3; /* x19 - s3 - saved register 3 */
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rt_ubase_t s4; /* x20 - s4 - saved register 4 */
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rt_ubase_t s5; /* x21 - s5 - saved register 5 */
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rt_ubase_t s6; /* x22 - s6 - saved register 6 */
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rt_ubase_t s7; /* x23 - s7 - saved register 7 */
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rt_ubase_t s8; /* x24 - s8 - saved register 8 */
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rt_ubase_t s9; /* x25 - s9 - saved register 9 */
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rt_ubase_t s10; /* x26 - s10 - saved register 10 */
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rt_ubase_t s11; /* x27 - s11 - saved register 11 */
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rt_ubase_t t3; /* x28 - t3 - temporary register 3 */
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rt_ubase_t t4; /* x29 - t4 - temporary register 4 */
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rt_ubase_t t5; /* x30 - t5 - temporary register 5 */
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rt_ubase_t t6; /* x31 - t6 - temporary register 6 */
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/* float register */
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#ifdef ARCH_RISCV_FPU
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rv_floatreg_t f0; /* f0 */
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rv_floatreg_t f1; /* f1 */
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rv_floatreg_t f2; /* f2 */
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rv_floatreg_t f3; /* f3 */
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rv_floatreg_t f4; /* f4 */
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rv_floatreg_t f5; /* f5 */
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rv_floatreg_t f6; /* f6 */
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rv_floatreg_t f7; /* f7 */
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rv_floatreg_t f8; /* f8 */
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rv_floatreg_t f9; /* f9 */
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rv_floatreg_t f10; /* f10 */
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rv_floatreg_t f11; /* f11 */
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rv_floatreg_t f12; /* f12 */
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rv_floatreg_t f13; /* f13 */
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rv_floatreg_t f14; /* f14 */
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rv_floatreg_t f15; /* f15 */
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rv_floatreg_t f16; /* f16 */
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rv_floatreg_t f17; /* f17 */
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rv_floatreg_t f18; /* f18 */
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rv_floatreg_t f19; /* f19 */
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rv_floatreg_t f20; /* f20 */
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rv_floatreg_t f21; /* f21 */
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rv_floatreg_t f22; /* f22 */
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rv_floatreg_t f23; /* f23 */
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rv_floatreg_t f24; /* f24 */
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rv_floatreg_t f25; /* f25 */
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rv_floatreg_t f26; /* f26 */
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rv_floatreg_t f27; /* f27 */
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rv_floatreg_t f28; /* f28 */
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rv_floatreg_t f29; /* f29 */
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rv_floatreg_t f30; /* f30 */
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rv_floatreg_t f31; /* f31 */
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#endif
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};
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/*
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* This function will initialize thread stack
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*
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* @param tentry the entry of thread
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* @param parameter the parameter of entry
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* @param stack_addr the beginning stack address
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* @param texit the function will be called when thread exit
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*
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* @return stack address
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*/
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rt_uint8_t *rt_hw_stack_init(void *tentry,
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void *parameter,
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rt_uint8_t *stack_addr,
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void *texit)
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{
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struct rt_hw_stack_frame *frame;
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rt_uint8_t *stk;
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int i;
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stk = stack_addr + sizeof(rt_ubase_t);
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stk = (rt_uint8_t *)RT_ALIGN_DOWN((rt_ubase_t)stk, REGBYTES);
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stk -= sizeof(struct rt_hw_stack_frame);
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frame = (struct rt_hw_stack_frame *)stk;
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for (i = 0; i < sizeof(struct rt_hw_stack_frame) / sizeof(rt_ubase_t); i++)
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{
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((rt_ubase_t *)frame)[i] = 0xdeadbeef;
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}
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frame->ra = (rt_ubase_t)texit;
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frame->a0 = (rt_ubase_t)parameter;
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frame->epc = (rt_ubase_t)tentry;
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/* force to machine mode(MPP=11) and set MPIE to 1 and FS=11 */
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frame->mstatus = 0x00001880;
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return stk;
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}
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/*
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* trigger soft interrupt
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*/
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void sw_setpend(void)
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{
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NVIC_SetPendingIRQ(Software_IRQn);
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}
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/*
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* clear soft interrupt
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*/
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void sw_clearpend(void)
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{
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NVIC_ClearPendingIRQ(Software_IRQn);
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}
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/*
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* disable interrupt and save mstatus
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*/
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rt_base_t rt_hw_interrupt_disable(void)
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{
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register rt_base_t value = 0;
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asm("csrrw %0, mstatus, %1":"=r"(value):"r"(0x1800));
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return value;
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}
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/*
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* enable interrupt and resume mstatus
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*/
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void rt_hw_interrupt_enable(rt_base_t level)
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{
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asm("csrw mstatus, %0": :"r"(level));
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}
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/*
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* #ifdef RT_USING_SMP
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* void rt_hw_context_switch_interrupt(void *context, rt_ubase_t from, rt_ubase_t to, struct rt_thread *to_thread);
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* #else
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* void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to);
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* #endif
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*/
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void rt_hw_context_switch_interrupt(rt_ubase_t from, rt_ubase_t to)
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{
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if (rt_thread_switch_interrupt_flag == 0)
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rt_interrupt_from_thread = from;
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rt_interrupt_to_thread = to;
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rt_thread_switch_interrupt_flag = 1;
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/* switch just in sw_handler */
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sw_setpend();
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}
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/* shutdown CPU */
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void rt_hw_cpu_shutdown(void)
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{
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rt_base_t level;
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rt_kprintf("shutdown...\n");
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level = rt_hw_interrupt_disable();
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while (level)
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{
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RT_ASSERT(0);
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}
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}
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